-
Notifications
You must be signed in to change notification settings - Fork 1
/
Spi.hpp
207 lines (147 loc) · 4.02 KB
/
Spi.hpp
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
#pragma once
#include <cstdint>
#include "Pins.hpp"
#include "Reg.hpp"
//SPI 1/2/3
struct Spi : private Reg {
//internal SPI register order used here
enum SPIX { SPI3, SPI2, SPI4, SPI1 };
//instantiate spi number
//SPI2 uses PPS, so user will also have to setup pins
//(not done here as there are a number of pins, and not all always needed)
Spi (SPIX);
//==== SPIxCON ====
//framed support
auto
frame (bool) -> void;
enum
FRMDIR : bool { MASTER, SLAVE };
//frame sync pulse dir
auto
frame_dir (FRMDIR) -> void;
enum
FRMHL : bool { LOW, HIGH };
//frame sync polarity
auto
frame_pol (FRMHL) -> void;
//slave select enable
auto
slave_sel (bool) -> void;
enum
FRMPW : bool { CLKW, CHARW };
//1=1char, 0=1clk
auto
frame_pwidth (FRMPW) -> void;
enum
FRMCNT : uint8_t { CNT1, CNT2, CNT4, CNT8, CNT16, CNT32 };
//frame sync counter
auto
frame_count (FRMCNT) -> void;
enum
FRMEDGE : bool { B4BCLK, ATBCLK };
//frame sync edge sel
auto
frame_edge (FRMEDGE) -> void;
//enhanced buffer mode
auto
enhanced (bool) -> void;
//spi on/off
auto
on (bool) -> void;
//true: disable sdo pin
auto
dis_sdo (bool) -> void;
enum
MODE : uint8_t {
MODE8 = 0, MODE16, MODE32,
};
//set spi mode
auto
mode (MODE) -> void;
enum
PHASE : bool { SMPMID, SMPEND };
//sample phase bit
auto
phase (PHASE) -> void;
enum
CLKEDGE : bool { LEAD, TRAIL };
//clk edge sel
auto
clk_edge (CLKEDGE) -> void;
//slave select enable
auto
ss (bool) -> void;
enum
CLKPOL : bool { CLKH, CLKL }; //CLKH --> Idle Low, Active High | CLKL --> Idle High, Active Low
//clock polarity
auto
clk_pol (CLKPOL) -> void;
//master mode
auto
master (bool) -> void;
enum
TXIRQ : uint8_t { TDONE, TEMPTY, THALF, TNOTFULL };
//tx irq mode
auto
tx_irq (TXIRQ) -> void;
enum
RXIRQ : uint8_t { REMPTY, RANY, RHALF, RFULL };
//rx irq mode
auto
rx_irq (RXIRQ) -> void;
//==== SPIxSTAT ====
//enhanced rx buf count
auto
stat_rxcount () -> uint8_t;
//enhanced tx buf count
auto
stat_txcount () -> uint8_t;
//spi busy?
auto
stat_busy () -> bool;
//tx underrun error?
auto
stat_txurun () -> bool;
//shift reg empty?
auto
stat_sremty () -> bool;
//rx overflow?
auto
stat_oerr () -> bool;
//rx overflow clear
auto
stat_oerrclr () -> void;
//rx empty?
auto
stat_rxemty () -> bool;
//tx empty?
auto
stat_txemty () -> bool;
//tx full?
auto
stat_txfull () -> bool;
//rx full?
auto
stat_rxfull () -> bool;
//==== SPIxBUF ====
//write buf 8/16/32bit
auto
write (uint32_t) -> void;
//read buf 8/16/32bit
auto
read () -> uint32_t;
//==== SPIxBRG ====
//set baud
auto
baud (uint16_t) -> void;
//set frequency
auto
freq (uint32_t) -> void;
//get frequency
auto
freq () -> uint32_t;
private:
volatile uint32_t* m_spix_con;
volatile uint32_t& m_spixbuf; //use reference
uint32_t m_spix_freq; //set to actual spi freq
};