I am an experienced computer engineer specializing in hardware-software co-design, with a strong focus on developing and optimizing embedded systems and FPGA-based solutions. Currently pursuing a MASc in Computer Engineering at the University of Waterloo, I am deeply involved in the design and verification of advanced multicore RISC-V SoCs, with expertise in firmware development, memory subsystem optimization, and hypervisor integration. My professional journey has seen me lead critical projects, including the development of an Electric Vehicle Fleet Management Device and the design of a safety-critical medical ventilator. My skill set spans across a wide range of technologies, including RISCV and ARM assembly, SystemVerilog, RTOS, and AI frameworks, reflecting a commitment to precision and innovation in every project I undertake.
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apmu-os
apmu-os PublicCustom Developed OS for APMU Core - Supporting IPC, Event Triggered Scheduling and Dynamic Component Installation
C
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FreeRTOS-FAT-SDVB-CVA6
FreeRTOS-FAT-SDVB-CVA6 PublicPort of FreeRTOS with FAT library and baremetal port of San Diego Vision Benchmark for RISCV CVA6
C
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CVA6-Hypervisor-Platform
CVA6-Hypervisor-Platform PublicOpenSBI+Bao Hypervisor+Linux/Baremetal software stack for RISCV CVA6 based SoC
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baremetal-dynamic-linker-riscv
baremetal-dynamic-linker-riscv PublicBaremetal Dynamic Linker for RISCV32 - Capable of processing some basic relocations
C
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