diff --git a/src/processing_Element.v b/src/processing_Element.v
index 535d19c..09b2f28 100644
--- a/src/processing_Element.v
+++ b/src/processing_Element.v
@@ -1,25 +1,47 @@
-module processing_element(
+module processing_element #(
+   parameter INPUT_WIDTH = 8,
+    parameter OUTPUT_WIDTH = 32
+    parameter REG_FILE_DEPTH = 8, //number of registers in file
+    parameter REG_FILE_WIDTH = 3 //bit width of each register
+)(
     input wire clk,
     input wire rst,
-    input wire [15:0] data_in_2,
-    input wire [15:0] data_in_1,
-    output wire [31:0] data_out
+    input wire [INPUT_WIDTH-1:0] data_in_2,
+    input wire [INPUT_WIDTH-1:0] data_in_1,
+    output reg [OUTPUT_WIDTH-1:0] data_out
 );
 
-reg [31:0] acc ;
+reg [OUTPUT_WIDTH-1:0] acc;
 
     always @(posedge clk or posedge rst) begin
 
         if (rst) begin
-            acc <= 32'b0;
-            data_out <= 32'b0;
+            acc <= {output_width{1'b0}};
+            data_out <= {output_width{1'b0}};
         end else begin
-            acc <= acc + $signed(data_in_1) + $signed(data_in_2);
-            data_out <= acc;
-        end
-    end
-
+        
+            //to sign extend we:
+            //1. convert the input to signed
+            //2. add the sign bit to the rest of the bits, that is (output_Width-input_width) times 
+            //ie. if ur output is 16 bits but ur input is 8 bits then u need to add 4 bits to the left
+            //those 4 bits are of the same sign
+            //check 222 again
+            //3. assign the result to the acc
 
+            wire sign_bit1 = data_in_1[INPUT_WIDTH-1];
+            wire sign_bit2 = data_in_2[INPUT_WIDTH-1];
+            localparam LENGTH_EXTEND = OUTPUT_WIDTH - INPUT_WIDTH;
+            //locaparam is used to define a constant value that can be used in the module, better for compile time
+        
 
+        acc <= acc 
+            + $signed({{LENGTH_EXTEND{sign_bit1}}, data_in_1}) 
+            * $signed({{LENGTH_EXTEND{sign_bit2}}, data_in_2});
+            
+        end
+    end
 
-endmodule
+    always @(posedge clk) begin
+        data_out <= acc;
+    end
+endmodule
\ No newline at end of file
diff --git a/src/project.v b/src/project.v
index 3e3d694..9d9b939 100644
--- a/src/project.v
+++ b/src/project.v
@@ -5,7 +5,12 @@
 
 `default_nettype none
 
-module tt_um_pe_mariam (
+module tt_um_pe_mariam #(
+    parameter M = 2
+    parameter N = 2
+    parameter input_width = 8;
+    parameter output_width = 32;
+)(
     input  wire [7:0] ui_in,    // Dedicated inputs
     output wire [7:0] uo_out,   // Dedicated outputs
     input  wire [7:0] uio_in,   // IOs: Input path
@@ -15,13 +20,44 @@ module tt_um_pe_mariam (
     input  wire       clk,      // clock
     input  wire       rst_n     // reset_n - low to reset
 );
+//internal signals
+  //active high reset
+    wire rst = ~rst_n;
+  //precision mode
+    wire [1:0]precision_mode;
+  //data in according to parameters
+    wire [M-1:0] data_in_1;
+    wire [N-1:0] data_in_2;
+  //data out according to parameters
+    wire [M-1:0][N-1:0][output_width-1:0] data_out;
+    //creates an array of MxN PEs with bit size of output_width
+
+    //yapyap assign input data to the data_in_1 and data_in_2
+    //idk what signals/values to use but i need signals to instantiate it soooo
+    assign data_in_1 = {ui_in, 8'd0};
+    assign data_in_2 = {uio_in, 8'd0};
+
+
+pe_array #(
+        .M(M),
+        .N(N),
+        .INPUT_WIDTH(INPUT_WIDTH),
+        .OUTPUT_WIDTH(OUTPUT_WIDTH)
+    ) pe_array_inst (
+        .clk(clk),
+        .rst(rst),
+        .precision_mode(precision_mode),
+        .data_in_1(data_in_1),
+        .data_in_2(data_in_2),
+        .data_out(data_out)
+    );
 
   // All output pins must be assigned. If not used, assign to 0.
-  assign uo_out  = ui_in + uio_in;  // Example: ou_out is the sum of ui_in and uio_in
+  assign uo_out  = 0
   assign uio_out = 0;
   assign uio_oe  = 0;
 
   // List all unused inputs to prevent warnings
-  wire _unused = &{ena, clk, rst_n, 1'b0};
+  wire _unused = &{ena, 1'b0};
 
 endmodule