From c399fdc8ba38dbddcd78bd35599fd0b79ba9573c Mon Sep 17 00:00:00 2001 From: Augusto Fraga Giachero Date: Mon, 10 Feb 2020 07:24:27 -0300 Subject: [PATCH 1/8] Update submodule urls to point to the lnls-dig repositories --- .gitmodules | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/.gitmodules b/.gitmodules index 0dacc85..641c048 100644 --- a/.gitmodules +++ b/.gitmodules @@ -3,7 +3,7 @@ url = git://github.com/ARMmbed/mbed-os [submodule "nuttx"] path = nuttx - url = https://github.com/Palmitoxico/nuttx.git + url = https://github.com/lnls-dig/nuttx.git [submodule "apps"] path = apps - url = https://github.com/Palmitoxico/nuttx-apps.git + url = https://github.com/lnls-dig/nuttx-apps.git From 758befeda8b51d1a823f6a747dc9f821438fc655 Mon Sep 17 00:00:00 2001 From: Augusto Fraga Giachero Date: Fri, 14 Feb 2020 15:23:05 -0300 Subject: [PATCH 2/8] Honor the bootloader flag when calling reprogram [utils] The fw_type field should be set to 2 when reprogramming the bootloader. --- utils/rffe_nuttx_lib.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/utils/rffe_nuttx_lib.py b/utils/rffe_nuttx_lib.py index aac85eb..b46bcd7 100644 --- a/utils/rffe_nuttx_lib.py +++ b/utils/rffe_nuttx_lib.py @@ -185,7 +185,7 @@ def reprogram(self, file_path, version, bootloader=False): boot_sec[248] = major boot_sec[249] = minor boot_sec[250] = patch - boot_sec[251] = 1 + boot_sec[251] = 2 if bootloader else 1 boot_sec[252] = 0xAA boot_sec[253] = 0xAA boot_sec[254] = 0xAA From 3b80b59584e72b808268a8dbac9849f9ea0e801c Mon Sep 17 00:00:00 2001 From: Augusto Fraga Giachero Date: Fri, 14 Feb 2020 15:41:36 -0300 Subject: [PATCH 3/8] Add bootloader option in fw_update.py [utils] Now it is possible to update the bootloader via the fw_update.py script. --- utils/fw_update.py | 12 ++++++++++-- 1 file changed, 10 insertions(+), 2 deletions(-) diff --git a/utils/fw_update.py b/utils/fw_update.py index 2f699b8..22b301d 100755 --- a/utils/fw_update.py +++ b/utils/fw_update.py @@ -8,9 +8,17 @@ fw_file = sys.argv[2] version = sys.argv[3] except: - print("Usage: " + sys.argv[0] + " ip firmware_file version") + print("Usage: " + sys.argv[0] + " ip firmware_file version [bootloader]") exit(1) +boot = False +try: + boot_arg = sys.argv[4] + if (boot_arg == "bootloader"): + boot = True +except: + pass + print("Connecting to " + ip_addr + " ...") try: rffe = RFFEControllerBoard(ip_addr) @@ -19,5 +27,5 @@ exit(1) print("Connection established, writing new firmware...") -rffe.reprogram(fw_file, version) +rffe.reprogram(fw_file, version, boot) print("Finished!") From dd582272fb85f06001903e64845b723a1b440c1c Mon Sep 17 00:00:00 2001 From: Augusto Fraga Giachero Date: Fri, 14 Feb 2020 16:00:09 -0300 Subject: [PATCH 4/8] New bootloader code [bootloader] This new bootloader is a drop-in replacement that doesn't depends upon mbed-os and other legacy stuff. It also doesn't depends on source code with questionable licenses (looking at you LPCOpen). --- bootloader/.clang_complete | 1 + bootloader/.gitignore | 8 + bootloader/Makefile | 43 + bootloader/gdbcmd | 24 + bootloader/inc/LPC176x5x.h | 10643 ++++++++++++++++++++++++++ bootloader/inc/cmsis_armcc.h | 884 +++ bootloader/inc/cmsis_armclang.h | 1446 ++++ bootloader/inc/cmsis_armclang_ltm.h | 1893 +++++ bootloader/inc/cmsis_compiler.h | 283 + bootloader/inc/cmsis_gcc.h | 2177 ++++++ bootloader/inc/cmsis_iccarm.h | 966 +++ bootloader/inc/cmsis_version.h | 39 + bootloader/inc/core_cm3.h | 1938 +++++ bootloader/inc/mpu_armv7.h | 272 + bootloader/ld.script | 302 + bootloader/src/lpc17_clock.c | 344 + bootloader/src/lpc17_clock.h | 77 + bootloader/src/lpc17_iap.c | 99 + bootloader/src/lpc17_iap.h | 54 + bootloader/src/lpc17_pincfg.c | 106 + bootloader/src/lpc17_pincfg.h | 42 + bootloader/src/lpc17_progmem.c | 27 + bootloader/src/lpc17_uart.c | 94 + bootloader/src/lpc17_uart.h | 29 + bootloader/src/main.c | 186 + bootloader/src/start_app.c | 40 + bootloader/src/start_app.h | 26 + bootloader/src/startup.s | 229 + 28 files changed, 22272 insertions(+) create mode 100644 bootloader/.clang_complete create mode 100644 bootloader/.gitignore create mode 100644 bootloader/Makefile create mode 100644 bootloader/gdbcmd create mode 100644 bootloader/inc/LPC176x5x.h create mode 100644 bootloader/inc/cmsis_armcc.h create mode 100644 bootloader/inc/cmsis_armclang.h create mode 100644 bootloader/inc/cmsis_armclang_ltm.h create mode 100644 bootloader/inc/cmsis_compiler.h create mode 100644 bootloader/inc/cmsis_gcc.h create mode 100644 bootloader/inc/cmsis_iccarm.h create mode 100644 bootloader/inc/cmsis_version.h create mode 100644 bootloader/inc/core_cm3.h create mode 100644 bootloader/inc/mpu_armv7.h create mode 100644 bootloader/ld.script create mode 100644 bootloader/src/lpc17_clock.c create mode 100644 bootloader/src/lpc17_clock.h create mode 100644 bootloader/src/lpc17_iap.c create mode 100644 bootloader/src/lpc17_iap.h create mode 100644 bootloader/src/lpc17_pincfg.c create mode 100644 bootloader/src/lpc17_pincfg.h create mode 100644 bootloader/src/lpc17_progmem.c create mode 100644 bootloader/src/lpc17_uart.c create mode 100644 bootloader/src/lpc17_uart.h create mode 100644 bootloader/src/main.c create mode 100644 bootloader/src/start_app.c create mode 100644 bootloader/src/start_app.h create mode 100644 bootloader/src/startup.s diff --git a/bootloader/.clang_complete b/bootloader/.clang_complete new file mode 100644 index 0000000..41b1f49 --- /dev/null +++ b/bootloader/.clang_complete @@ -0,0 +1 @@ +-I./inc/ \ No newline at end of file diff --git a/bootloader/.gitignore b/bootloader/.gitignore new file mode 100644 index 0000000..e5386ff --- /dev/null +++ b/bootloader/.gitignore @@ -0,0 +1,8 @@ +*.o +*.a +*.hex +*.bin +*.elf +*.d +openocd.log +.interface diff --git a/bootloader/Makefile b/bootloader/Makefile new file mode 100644 index 0000000..da4223b --- /dev/null +++ b/bootloader/Makefile @@ -0,0 +1,43 @@ +PRJ_NAME = bootloader +CC = arm-none-eabi-gcc +SRCDIR = src +SRC = $(wildcard $(SRCDIR)/*.c) +ASRC = $(wildcard $(SRCDIR)/*.s) +OBJ = $(SRC:.c=.o) $(ASRC:.s=.o) +OBJCOPY = arm-none-eabi-objcopy +OBJDUMP = arm-none-eabi-objdump +PROGRAMMER = openocd +PGFLAGS = -f ../scripts/openocd/lpc17-cmsis.cfg -c "program $(PRJ_NAME).bin verify reset" -c shutdown +OPT ?= -Og +LDSCRIPT = ld.script +CFLAGS = -fdata-sections -ffunction-sections -g3 -Wall -mcpu=cortex-m3 -mlittle-endian -mthumb $(OPT) -I inc/ -mlong-calls +ASFLAGS = $(CFLAGS) +LDFLAGS = -T $(LDSCRIPT) -Wl,--gc-sections --specs=nano.specs --specs=nosys.specs + +.PHONY: all clean flash burn hex bin + +all: $(PRJ_NAME).bin + +$(PRJ_NAME).elf: $(OBJ) + $(CC) $(CFLAGS) $(OBJ) -o $@ $(LDFLAGS) + arm-none-eabi-size $(PRJ_NAME).elf + +%.o: %.c $(DEPS) + $(CC) -MMD -c $(CFLAGS) $< -o $@ + +%.o: %.s $(DEPS) + $(CC) -MMD -c $(ASFLAGS) $< -o $@ + +-include $(SRCDIR)/*.d + +clean: + rm -f $(OBJ) $(PRJ_NAME).elf $(PRJ_NAME)-pad.elf $(PRJ_NAME).hex $(PRJ_NAME).bin $(SRCDIR)/*.d + +flash: bin + $(PROGRAMMER) $(PGFLAGS) + +$(PRJ_NAME)-pad.elf: $(PRJ_NAME).elf + $(OBJCOPY) --gap-fill 0xFF --pad-to 0x10000 $< $@ + +$(PRJ_NAME).bin: $(PRJ_NAME)-pad.elf + $(OBJCOPY) -O binary $< $(PRJ_NAME).bin diff --git a/bootloader/gdbcmd b/bootloader/gdbcmd new file mode 100644 index 0000000..b16a49c --- /dev/null +++ b/bootloader/gdbcmd @@ -0,0 +1,24 @@ +define rst + tb main + monitor reset halt + c +end + +define ld + make + load + rst +end + +target remote | openocd -c "gdb_port pipe; log_output openocd.log" -f ../scripts/openocd/lpc17-cmsis.cfg + +python +from cmdebug.svd_gdb import LoadSVD +from cmdebug.dwt_gdb import DWT + +DWT() +LoadSVD() + +end + +svd_load ../scripts/gdb/LPC176x5x_v0.2.svd \ No newline at end of file diff --git a/bootloader/inc/LPC176x5x.h b/bootloader/inc/LPC176x5x.h new file mode 100644 index 0000000..2e946d4 --- /dev/null +++ b/bootloader/inc/LPC176x5x.h @@ -0,0 +1,10643 @@ +/* + * Copyright (c) 2009-2019 ARM Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * @file lpc17_headers//LPC176x5x.h + * @brief CMSIS HeaderFile + * @version 0.2 + * @date 06. February 2020 + * @note Generated by SVDConv V3.3.27 on Thursday, 06.02.2020 12:13:27 + * from File 'LPC176x5x_v0.2.svd', + */ + + + +/** @addtogroup + * @{ + */ + + +/** @addtogroup LPC176x5x + * @{ + */ + + +#ifndef LPC176X5X_H +#define LPC176X5X_H + +#ifdef __cplusplus +extern "C" { +#endif + + +/** @addtogroup Configuration_of_CMSIS + * @{ + */ + + + +/* =========================================================================================================================== */ +/* ================ Interrupt Number Definition ================ */ +/* =========================================================================================================================== */ + +typedef enum { +/* ======================================= ARM Cortex-M3 Specific Interrupt Numbers ======================================== */ + Reset_IRQn = -15, /*!< -15 Reset Vector, invoked on Power up and warm reset */ + NonMaskableInt_IRQn = -14, /*!< -14 Non maskable Interrupt, cannot be stopped or preempted */ + HardFault_IRQn = -13, /*!< -13 Hard Fault, all classes of Fault */ + MemoryManagement_IRQn = -12, /*!< -12 Memory Management, MPU mismatch, including Access Violation + and No Match */ + BusFault_IRQn = -11, /*!< -11 Bus Fault, Pre-Fetch-, Memory Access Fault, other address/memory + related Fault */ + UsageFault_IRQn = -10, /*!< -10 Usage Fault, i.e. Undef Instruction, Illegal State Transition */ + SVCall_IRQn = -5, /*!< -5 System Service Call via SVC instruction */ + DebugMonitor_IRQn = -4, /*!< -4 Debug Monitor */ + PendSV_IRQn = -2, /*!< -2 Pendable request for system service */ + SysTick_IRQn = -1, /*!< -1 System Tick Timer */ +/* ========================================= LPC176x5x Specific Interrupt Numbers ========================================== */ + WDT_IRQn = 0, /*!< 0 WDT */ + TIMER0_IRQn = 1, /*!< 1 TIMER0 */ + TIMER1_IRQn = 2, /*!< 2 TIMER1 */ + TIMER2_IRQn = 3, /*!< 3 TIMER2 */ + TIMER3_IRQn = 4, /*!< 4 TIMER3 */ + UART0_IRQn = 5, /*!< 5 UART0 */ + UART1_IRQn = 6, /*!< 6 UART1 */ + UART2_IRQn = 7, /*!< 7 UART2 */ + UART3_IRQn = 8, /*!< 8 UART3 */ + PWM1_IRQn = 9, /*!< 9 PWM1 */ + I2C0_IRQn = 10, /*!< 10 I2C0 */ + I2C1_IRQn = 11, /*!< 11 I2C1 */ + I2C2_IRQn = 12, /*!< 12 I2C2 */ + SPI_IRQn = 13, /*!< 13 SPI */ + SSP0_IRQn = 14, /*!< 14 SSP0 */ + SSP1_IRQn = 15, /*!< 15 SSP1 */ + PLL0_IRQn = 16, /*!< 16 PLL0 */ + RTC_IRQn = 17, /*!< 17 RTC */ + EINT0_IRQn = 18, /*!< 18 EINT0 */ + EINT1_IRQn = 19, /*!< 19 EINT1 */ + EINT2_IRQn = 20, /*!< 20 EINT2 */ + EINT3_IRQn = 21, /*!< 21 EINT3 */ + ADC_IRQn = 22, /*!< 22 ADC */ + BOD_IRQn = 23, /*!< 23 BOD */ + USB_IRQn = 24, /*!< 24 USB */ + CAN_IRQn = 25, /*!< 25 CAN */ + DMA_IRQn = 26, /*!< 26 DMA */ + I2S_IRQn = 27, /*!< 27 I2S */ + ENET_IRQn = 28, /*!< 28 ENET */ + RIT_IRQn = 29, /*!< 29 RIT */ + MCPWM_IRQn = 30, /*!< 30 MCPWM */ + QEI_IRQn = 31, /*!< 31 QEI */ + PLL1_IRQn = 32, /*!< 32 PLL1 */ + USBActivity_IRQn = 33, /*!< 33 USBActivity */ + CANActivity_IRQn = 34 /*!< 34 CANActivity */ +} IRQn_Type; + + + +/* =========================================================================================================================== */ +/* ================ Processor and Core Peripheral Section ================ */ +/* =========================================================================================================================== */ + +/* =========================== Configuration of the ARM Cortex-M3 Processor and Core Peripherals =========================== */ +#define __CM3_REV 0x0000U /*!< CM3 Core Revision */ +#define __NVIC_PRIO_BITS 5 /*!< Number of Bits used for Priority Levels */ +#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ +#define __MPU_PRESENT 1 /*!< MPU present */ +#define __FPU_PRESENT 0 /*!< FPU present */ + + +/** @} */ /* End of group Configuration_of_CMSIS */ + +#include "core_cm3.h" /*!< ARM Cortex-M3 processor and core peripherals */ +// #include "system_LPC176x5x.h" /*!< LPC176x5x System */ + +#ifndef __IM /*!< Fallback for older CMSIS versions */ + #define __IM __I +#endif +#ifndef __OM /*!< Fallback for older CMSIS versions */ + #define __OM __O +#endif +#ifndef __IOM /*!< Fallback for older CMSIS versions */ + #define __IOM __IO +#endif + + +/* ======================================== Start of section using anonymous unions ======================================== */ +#if defined (__CC_ARM) + #pragma push + #pragma anon_unions +#elif defined (__ICCARM__) + #pragma language=extended +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wc11-extensions" + #pragma clang diagnostic ignored "-Wreserved-id-macro" + #pragma clang diagnostic ignored "-Wgnu-anonymous-struct" + #pragma clang diagnostic ignored "-Wnested-anon-types" +#elif defined (__GNUC__) + /* anonymous unions are enabled by default */ +#elif defined (__TMS470__) + /* anonymous unions are enabled by default */ +#elif defined (__TASKING__) + #pragma warning 586 +#elif defined (__CSMC__) + /* anonymous unions are enabled by default */ +#else + #warning Not supported compiler type +#endif + + +/* =========================================================================================================================== */ +/* ================ Device Specific Peripheral Section ================ */ +/* =========================================================================================================================== */ + + +/** @addtogroup Device_Peripheral_peripherals + * @{ + */ + + + +/* =========================================================================================================================== */ +/* ================ WDT ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief Watchdog Timer (WDT) (WDT) + */ + +typedef struct { /*!< (@ 0x40000000) WDT Structure */ + __IOM uint32_t MOD; /*!< (@ 0x00000000) Watchdog mode register. This register determines + the basic mode and status of the Watchdog + Timer. */ + __IOM uint32_t TC; /*!< (@ 0x00000004) Watchdog timer constant register. The value in + this register determines the time-out value. */ + __OM uint32_t FEED; /*!< (@ 0x00000008) Watchdog feed sequence register. Writing 0xAA + followed by 0x55 to this register reloads + the Watchdog timer with the value contained + in WDTC. */ + __IM uint32_t TV; /*!< (@ 0x0000000C) Watchdog timer value register. This register + reads out the current value of the Watchdog + timer. */ + __IOM uint32_t CLKSEL; /*!< (@ 0x00000010) Watchdog clock select register. */ +} LPC_WDT_Type; /*!< Size = 20 (0x14) */ + + + +/* =========================================================================================================================== */ +/* ================ TIMER0 ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief Timer0/1/2/3 (TIMER0) + */ + +typedef struct { /*!< (@ 0x40004000) TIMER0 Structure */ + __IOM uint32_t IR; /*!< (@ 0x00000000) Interrupt Register. The IR can be written to + clear interrupts. The IR can be read to + identify which of eight possible interrupt + sources are pending. */ + __IOM uint32_t TCR; /*!< (@ 0x00000004) Timer Control Register. The TCR is used to control + the Timer Counter functions. The Timer Counter + can be disabled or reset through the TCR. */ + __IOM uint32_t TC; /*!< (@ 0x00000008) Timer Counter. The 32 bit TC is incremented every + PR+1 cycles of PCLK. The TC is controlled + through the TCR. */ + __IOM uint32_t PR; /*!< (@ 0x0000000C) Prescale Register. When the Prescale Counter + (PC) is equal to this value, the next clock + increments the TC and clears the PC. */ + __IOM uint32_t PC; /*!< (@ 0x00000010) Prescale Counter. The 32 bit PC is a counter + which is incremented to the value stored + in PR. When the value in PR is reached, + the TC is incremented and the PC is cleared. + The PC is observable and controllable through + the bus interface. */ + __IOM uint32_t MCR; /*!< (@ 0x00000014) Match Control Register. The MCR is used to control + if an interrupt is generated and if the + TC is reset when a Match occurs. */ + __IOM uint32_t MR[4]; /*!< (@ 0x00000018) Match Register 0. MR0 can be enabled through + the MCR to reset the TC, stop both the TC + and PC, and/or generate an interrupt every + time MR0 matches the TC. */ + __IOM uint32_t CCR; /*!< (@ 0x00000028) Capture Control Register. The CCR controls which + edges of the capture inputs are used to + load the Capture Registers and whether or + not an interrupt is generated when a capture + takes place. */ + __IM uint32_t CR[2]; /*!< (@ 0x0000002C) Capture Register 0. CR0 is loaded with the value + of TC when there is an event on the CAPn.0 + input. */ + __IM uint32_t RESERVED[2]; + __IOM uint32_t EMR; /*!< (@ 0x0000003C) External Match Register. The EMR controls the + external match pins. */ + __IM uint32_t RESERVED1[12]; + __IOM uint32_t CTCR; /*!< (@ 0x00000070) Count Control Register. The CTCR selects between + Timer and Counter mode, and in Counter mode + selects the signal and edge(s) for counting. */ +} LPC_TIMER0_Type; /*!< Size = 116 (0x74) */ + + + +/* =========================================================================================================================== */ +/* ================ TIMER1 ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief Timer0/1/2/3 (TIMER1) + */ + +typedef struct { /*!< (@ 0x40008000) TIMER1 Structure */ + __IOM uint32_t IR; /*!< (@ 0x00000000) Interrupt Register. The IR can be written to + clear interrupts. The IR can be read to + identify which of eight possible interrupt + sources are pending. */ + __IOM uint32_t TCR; /*!< (@ 0x00000004) Timer Control Register. The TCR is used to control + the Timer Counter functions. The Timer Counter + can be disabled or reset through the TCR. */ + __IOM uint32_t TC; /*!< (@ 0x00000008) Timer Counter. The 32 bit TC is incremented every + PR+1 cycles of PCLK. The TC is controlled + through the TCR. */ + __IOM uint32_t PR; /*!< (@ 0x0000000C) Prescale Register. When the Prescale Counter + (PC) is equal to this value, the next clock + increments the TC and clears the PC. */ + __IOM uint32_t PC; /*!< (@ 0x00000010) Prescale Counter. The 32 bit PC is a counter + which is incremented to the value stored + in PR. When the value in PR is reached, + the TC is incremented and the PC is cleared. + The PC is observable and controllable through + the bus interface. */ + __IOM uint32_t MCR; /*!< (@ 0x00000014) Match Control Register. The MCR is used to control + if an interrupt is generated and if the + TC is reset when a Match occurs. */ + __IOM uint32_t MR[4]; /*!< (@ 0x00000018) Match Register 0. MR0 can be enabled through + the MCR to reset the TC, stop both the TC + and PC, and/or generate an interrupt every + time MR0 matches the TC. */ + __IOM uint32_t CCR; /*!< (@ 0x00000028) Capture Control Register. The CCR controls which + edges of the capture inputs are used to + load the Capture Registers and whether or + not an interrupt is generated when a capture + takes place. */ + __IM uint32_t CR[2]; /*!< (@ 0x0000002C) Capture Register 0. CR0 is loaded with the value + of TC when there is an event on the CAPn.0 + input. */ + __IM uint32_t RESERVED[2]; + __IOM uint32_t EMR; /*!< (@ 0x0000003C) External Match Register. The EMR controls the + external match pins. */ + __IM uint32_t RESERVED1[12]; + __IOM uint32_t CTCR; /*!< (@ 0x00000070) Count Control Register. The CTCR selects between + Timer and Counter mode, and in Counter mode + selects the signal and edge(s) for counting. */ +} LPC_TIMER1_Type; /*!< Size = 116 (0x74) */ + + + +/* =========================================================================================================================== */ +/* ================ UART0 ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief UART0/2/3 (UART0) + */ + +typedef struct { /*!< (@ 0x4000C000) UART0 Structure */ + + union { + __IM uint32_t RBR; /*!< (@ 0x00000000) Receiver Buffer Register. Contains the next received + character to be read (DLAB =0). */ + __OM uint32_t THR; /*!< (@ 0x00000000) Transmit Holding Regiter. The next character + to be transmitted is written here (DLAB + =0). */ + __IOM uint32_t DLL; /*!< (@ 0x00000000) Divisor Latch LSB. Least significant byte of + the baud rate divisor value. The full divisor + is used to generate a baud rate from the + fractional rate divider (DLAB =1). */ + }; + + union { + __IOM uint32_t DLM; /*!< (@ 0x00000004) Divisor Latch MSB. Most significant byte of the + baud rate divisor value. The full divisor + is used to generate a baud rate from the + fractional rate divider (DLAB =1). */ + __IOM uint32_t IER; /*!< (@ 0x00000004) Interrupt Enable Register. Contains individual + interrupt enable bits for the 7 potential + UART interrupts (DLAB =0). */ + }; + + union { + __IM uint32_t IIR; /*!< (@ 0x00000008) Interrupt ID Register. Identifies which interrupt(s) + are pending. */ + __OM uint32_t FCR; /*!< (@ 0x00000008) FIFO Control Register. Controls UART FIFO usage + and modes. */ + }; + __IOM uint32_t LCR; /*!< (@ 0x0000000C) Line Control Register. Contains controls for + frame formatting and break generation. */ + __IM uint32_t RESERVED; + __IM uint32_t LSR; /*!< (@ 0x00000014) Line Status Register. Contains flags for transmit + and receive status, including line errors. */ + __IM uint32_t RESERVED1; + __IOM uint32_t SCR; /*!< (@ 0x0000001C) Scratch Pad Register. 8-bit temporary storage + for software. */ + __IOM uint32_t ACR; /*!< (@ 0x00000020) Auto-baud Control Register. Contains controls + for the auto-baud feature. */ + __IM uint32_t RESERVED2; + __IOM uint32_t FDR; /*!< (@ 0x00000028) Fractional Divider Register. Generates a clock + input for the baud rate divider. */ + __IM uint32_t RESERVED3; + __IOM uint32_t TER; /*!< (@ 0x00000030) Transmit Enable Register. Turns off UART transmitter + for use with software flow control. */ + __IM uint32_t RESERVED4[6]; + __IOM uint32_t RS485CTRL; /*!< (@ 0x0000004C) RS-485/EIA-485 Control. Contains controls to + configure various aspects of RS-485/EIA-485 + modes. */ + __IOM uint32_t RS485ADRMATCH; /*!< (@ 0x00000050) RS-485/EIA-485 address match. Contains the address + match value for RS-485/EIA-485 mode. */ + __IOM uint32_t RS485DLY; /*!< (@ 0x00000054) RS-485/EIA-485 direction control delay. */ +} LPC_UART0_Type; /*!< Size = 88 (0x58) */ + + + +/* =========================================================================================================================== */ +/* ================ UART1 ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief UART1 (UART1) + */ + +typedef struct { /*!< (@ 0x40010000) UART1 Structure */ + + union { + __IM uint32_t RBR; /*!< (@ 0x00000000) DLAB =0 Receiver Buffer Register. Contains the + next received character to be read. */ + __OM uint32_t THR; /*!< (@ 0x00000000) DLAB =0. Transmit Holding Register. The next + character to be transmitted is written here. */ + __IOM uint32_t DLL; /*!< (@ 0x00000000) DLAB =1. Divisor Latch LSB. Least significant + byte of the baud rate divisor value. The + full divisor is used to generate a baud + rate from the fractional rate divider. */ + }; + + union { + __IOM uint32_t DLM; /*!< (@ 0x00000004) DLAB =1. Divisor Latch MSB. Most significant + byte of the baud rate divisor value. The + full divisor is used to generate a baud + rate from the fractional rate divider. */ + __IOM uint32_t IER; /*!< (@ 0x00000004) DLAB =0. Interrupt Enable Register. Contains + individual interrupt enable bits for the + 7 potential UART1 interrupts. */ + }; + + union { + __IM uint32_t IIR; /*!< (@ 0x00000008) Interrupt ID Register. Identifies which interrupt(s) + are pending. */ + __OM uint32_t FCR; /*!< (@ 0x00000008) FIFO Control Register. Controls UART1 FIFO usage + and modes. */ + }; + __IOM uint32_t LCR; /*!< (@ 0x0000000C) Line Control Register. Contains controls for + frame formatting and break generation. */ + __IOM uint32_t MCR; /*!< (@ 0x00000010) Modem Control Register. Contains controls for + flow control handshaking and loopback mode. */ + __IM uint32_t LSR; /*!< (@ 0x00000014) Line Status Register. Contains flags for transmit + and receive status, including line errors. */ + __IM uint32_t MSR; /*!< (@ 0x00000018) Modem Status Register. Contains handshake signal + status flags. */ + __IOM uint32_t SCR; /*!< (@ 0x0000001C) Scratch Pad Register. 8-bit temporary storage + for software. */ + __IOM uint32_t ACR; /*!< (@ 0x00000020) Auto-baud Control Register. Contains controls + for the auto-baud feature. */ + __IM uint32_t RESERVED; + __IOM uint32_t FDR; /*!< (@ 0x00000028) Fractional Divider Register. Generates a clock + input for the baud rate divider. */ + __IM uint32_t RESERVED1; + __IOM uint32_t TER; /*!< (@ 0x00000030) Transmit Enable Register. Turns off UART transmitter + for use with software flow control. */ + __IM uint32_t RESERVED2[6]; + __IOM uint32_t RS485CTRL; /*!< (@ 0x0000004C) RS-485/EIA-485 Control. Contains controls to + configure various aspects of RS-485/EIA-485 + modes. */ + __IOM uint32_t RS485ADRMATCH; /*!< (@ 0x00000050) RS-485/EIA-485 address match. Contains the address + match value for RS-485/EIA-485 mode. */ + __IOM uint32_t RS485DLY; /*!< (@ 0x00000054) RS-485/EIA-485 direction control delay. */ +} LPC_UART1_Type; /*!< Size = 88 (0x58) */ + + + +/* =========================================================================================================================== */ +/* ================ PWM1 ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief Pulse Width Modulators (PWM1) (PWM1) + */ + +typedef struct { /*!< (@ 0x40018000) PWM1 Structure */ + __IOM uint32_t IR; /*!< (@ 0x00000000) Interrupt Register. The IR can be written to + clear interrupts, or read to identify which + PWM interrupt sources are pending. */ + __IOM uint32_t TCR; /*!< (@ 0x00000004) Timer Control Register. The TCR is used to control + the Timer Counter functions. */ + __IOM uint32_t TC; /*!< (@ 0x00000008) Timer Counter. The 32 bit TC is incremented every + PR+1 cycles of PCLK. The TC is controlled + through the TCR. */ + __IOM uint32_t PR; /*!< (@ 0x0000000C) Prescale Register. Determines how often the PWM + counter is incremented. */ + __IOM uint32_t PC; /*!< (@ 0x00000010) Prescale Counter. Prescaler for the main PWM + counter. */ + __IOM uint32_t MCR; /*!< (@ 0x00000014) Match Control Register. The MCR is used to control + whether an interrupt is generated and if + the PWM counter is reset when a Match occurs. */ + __IOM uint32_t MR0; /*!< (@ 0x00000018) Match Register. Match registersare continuously + compared to the PWM counter in order to + control PWMoutput edges. */ + __IOM uint32_t MR1; /*!< (@ 0x0000001C) Match Register. Match registersare continuously + compared to the PWM counter in order to + control PWMoutput edges. */ + __IOM uint32_t MR2; /*!< (@ 0x00000020) Match Register. Match registersare continuously + compared to the PWM counter in order to + control PWMoutput edges. */ + __IOM uint32_t MR3; /*!< (@ 0x00000024) Match Register. Match registersare continuously + compared to the PWM counter in order to + control PWMoutput edges. */ + __IOM uint32_t CCR; /*!< (@ 0x00000028) Capture Control Register. The CCR controls which + edges of the capture inputs are used to + load the Capture Registers and whether or + not an interrupt is generated for a capture + event. */ + __IOM uint32_t CR[2]; /*!< (@ 0x0000002C) PWM Control Register. Enables PWM outputs and + selects either single edge or double edge + controlled PWM outputs. */ + __IM uint32_t RESERVED[3]; + __IOM uint32_t MR4; /*!< (@ 0x00000040) Match Register. Match registersare continuously + compared to the PWM counter in order to + control PWMoutput edges. */ + __IOM uint32_t MR5; /*!< (@ 0x00000044) Match Register. Match registersare continuously + compared to the PWM counter in order to + control PWMoutput edges. */ + __IOM uint32_t MR6; /*!< (@ 0x00000048) Match Register. Match registersare continuously + compared to the PWM counter in order to + control PWMoutput edges. */ + __IOM uint32_t PCR; /*!< (@ 0x0000004C) PWM Control Register. Enables PWM outputs and + selects either single edge or double edge + controlled PWM outputs. */ + __IOM uint32_t LER; /*!< (@ 0x00000050) Load Enable Register. Enables use of updated + PWM match values. */ + __IM uint32_t RESERVED1[7]; + __IOM uint32_t CTCR; /*!< (@ 0x00000070) Count Control Register. The CTCR selects between + Timer and Counter mode, and in Counter mode + selects the signal and edge(s) for counting. */ +} LPC_PWM1_Type; /*!< Size = 116 (0x74) */ + + + +/* =========================================================================================================================== */ +/* ================ I2C0 ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief I2C bus interface (I2C0) + */ + +typedef struct { /*!< (@ 0x4001C000) I2C0 Structure */ + __IOM uint32_t CONSET; /*!< (@ 0x00000000) I2C Control Set Register. When a one is written + to a bit of this register, the corresponding + bit in the I2C control register is set. + Writing a zero has no effect on the corresponding + bit in the I2C control register. */ + __IM uint32_t STAT; /*!< (@ 0x00000004) I2C Status Register. During I2C operation, this + register provides detailed status codes + that allow software to determine the next + action needed. */ + __IOM uint32_t DAT; /*!< (@ 0x00000008) I2C Data Register. During master or slave transmit + mode, data to be transmitted is written + to this register. During master or slave + receive mode, data that has been received + may be read from this register. */ + __IOM uint32_t ADR0; /*!< (@ 0x0000000C) I2C Slave Address Register 0. Contains the 7-bit + slave address for operation of the I2C interface + in slave mode, and is not used in master + mode. The least significant bit determines + whether a slave responds to the General + Call address. */ + __IOM uint32_t SCLH; /*!< (@ 0x00000010) SCH Duty Cycle Register High Half Word. Determines + the high time of the I2C clock. */ + __IOM uint32_t SCLL; /*!< (@ 0x00000014) SCL Duty Cycle Register Low Half Word. Determines + the low time of the I2C clock. SCLL and + SCLH together determine the clock frequency + generated by an I2C master and certain times + used in slave mode. */ + __OM uint32_t CONCLR; /*!< (@ 0x00000018) I2C Control Clear Register. When a one is written + to a bit of this register, the corresponding + bit in the I2C control register is cleared. + Writing a zero has no effect on the corresponding + bit in the I2C control register. */ + __IOM uint32_t MMCTRL; /*!< (@ 0x0000001C) Monitor mode control register. */ + __IOM uint32_t ADR1; /*!< (@ 0x00000020) I2C Slave Address Register. Contains the 7-bit + slave address for operation of the I2C interface + in slave mode, and is not used in master + mode. The least significant bit determines + whether a slave responds to the General + Call address. */ + __IOM uint32_t ADR2; /*!< (@ 0x00000024) I2C Slave Address Register. Contains the 7-bit + slave address for operation of the I2C interface + in slave mode, and is not used in master + mode. The least significant bit determines + whether a slave responds to the General + Call address. */ + __IOM uint32_t ADR3; /*!< (@ 0x00000028) I2C Slave Address Register. Contains the 7-bit + slave address for operation of the I2C interface + in slave mode, and is not used in master + mode. The least significant bit determines + whether a slave responds to the General + Call address. */ + __IM uint32_t DATA_BUFFER; /*!< (@ 0x0000002C) Data buffer register. The contents of the 8 MSBs + of the DAT shift register will be transferred + to the DATA_BUFFER automatically after every + nine bits (8 bits of data plus ACK or NACK) + has been received on the bus. */ + __IOM uint32_t MASK[4]; /*!< (@ 0x00000030) I2C Slave address mask register */ +} LPC_I2C0_Type; /*!< Size = 64 (0x40) */ + + + +/* =========================================================================================================================== */ +/* ================ SPI ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief SPI (SPI) + */ + +typedef struct { /*!< (@ 0x40020000) SPI Structure */ + __IOM uint32_t CR; /*!< (@ 0x00000000) SPI Control Register. This register controls + the operation of the SPI. */ + __IM uint32_t SR; /*!< (@ 0x00000004) SPI Status Register. This register shows the + status of the SPI. */ + __IOM uint32_t DR; /*!< (@ 0x00000008) SPI Data Register. This bi-directional register + provides the transmit and receive data for + the SPI. Transmit data is provided to the + SPI0 by writing to this register. Data received + by the SPI0 can be read from this register. */ + __IOM uint32_t CCR; /*!< (@ 0x0000000C) SPI Clock Counter Register. This register controls + the frequency of a master's SCK0. */ + __IM uint32_t RESERVED[3]; + __IOM uint32_t INT; /*!< (@ 0x0000001C) SPI Interrupt Flag. This register contains the + interrupt flag for the SPI interface. */ +} LPC_SPI_Type; /*!< Size = 32 (0x20) */ + + + +/* =========================================================================================================================== */ +/* ================ RTC ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief Real Time Clock (RTC) (RTC) + */ + +typedef struct { /*!< (@ 0x40024000) RTC Structure */ + __IOM uint32_t ILR; /*!< (@ 0x00000000) Interrupt Location Register */ + __IM uint32_t RESERVED; + __IOM uint32_t CCR; /*!< (@ 0x00000008) Clock Control Register */ + __IOM uint32_t CIIR; /*!< (@ 0x0000000C) Counter Increment Interrupt Register */ + __IOM uint32_t AMR; /*!< (@ 0x00000010) Alarm Mask Register */ + __IM uint32_t CTIME0; /*!< (@ 0x00000014) Consolidated Time Register 0 */ + __IM uint32_t CTIME1; /*!< (@ 0x00000018) Consolidated Time Register 1 */ + __IM uint32_t CTIME2; /*!< (@ 0x0000001C) Consolidated Time Register 2 */ + __IOM uint32_t SEC; /*!< (@ 0x00000020) Seconds Counter */ + __IOM uint32_t MIN; /*!< (@ 0x00000024) Minutes Register */ + __IOM uint32_t HRS; /*!< (@ 0x00000028) Hours Register */ + __IOM uint32_t DOM; /*!< (@ 0x0000002C) Day of Month Register */ + __IOM uint32_t DOW; /*!< (@ 0x00000030) Day of Week Register */ + __IOM uint32_t DOY; /*!< (@ 0x00000034) Day of Year Register */ + __IOM uint32_t MONTH; /*!< (@ 0x00000038) Months Register */ + __IOM uint32_t YEAR; /*!< (@ 0x0000003C) Years Register */ + __IOM uint32_t CALIBRATION; /*!< (@ 0x00000040) Calibration Value Register */ + __IOM uint32_t GPREG0; /*!< (@ 0x00000044) General Purpose Register 0 */ + __IOM uint32_t GPREG1; /*!< (@ 0x00000048) General Purpose Register 0 */ + __IOM uint32_t GPREG2; /*!< (@ 0x0000004C) General Purpose Register 0 */ + __IOM uint32_t GPREG3; /*!< (@ 0x00000050) General Purpose Register 0 */ + __IOM uint32_t GPREG4; /*!< (@ 0x00000054) General Purpose Register 0 */ + __IOM uint32_t RTC_AUXEN; /*!< (@ 0x00000058) RTC Auxiliary Enable register */ + __IOM uint32_t RTC_AUX; /*!< (@ 0x0000005C) RTC Auxiliary control register */ + __IOM uint32_t ASEC; /*!< (@ 0x00000060) Alarm value for Seconds */ + __IOM uint32_t AMIN; /*!< (@ 0x00000064) Alarm value for Minutes */ + __IOM uint32_t AHRS; /*!< (@ 0x00000068) Alarm value for Hours */ + __IOM uint32_t ADOM; /*!< (@ 0x0000006C) Alarm value for Day of Month */ + __IOM uint32_t ADOW; /*!< (@ 0x00000070) Alarm value for Day of Week */ + __IOM uint32_t ADOY; /*!< (@ 0x00000074) Alarm value for Day of Year */ + __IOM uint32_t AMON; /*!< (@ 0x00000078) Alarm value for Months */ + __IOM uint32_t AYRS; /*!< (@ 0x0000007C) Alarm value for Year */ +} LPC_RTC_Type; /*!< Size = 128 (0x80) */ + + + +/* =========================================================================================================================== */ +/* ================ GPIOINT ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief GPIO (GPIOINT) + */ + +typedef struct { /*!< (@ 0x40028080) GPIOINT Structure */ + __IM uint32_t STATUS; /*!< (@ 0x00000000) GPIO overall Interrupt Status. */ + __IM uint32_t STATR0; /*!< (@ 0x00000004) GPIO Interrupt Status for Rising edge for Port + 0. */ + __IM uint32_t STATF0; /*!< (@ 0x00000008) GPIO Interrupt Status for Falling edge for Port + 0. */ + __OM uint32_t CLR0; /*!< (@ 0x0000000C) GPIO Interrupt Clear. */ + __IOM uint32_t ENR0; /*!< (@ 0x00000010) GPIO Interrupt Enable for Rising edge for Port + 0. */ + __IOM uint32_t ENF0; /*!< (@ 0x00000014) GPIO Interrupt Enable for Falling edge for Port + 0. */ + __IM uint32_t RESERVED[3]; + __IM uint32_t STATR2; /*!< (@ 0x00000024) GPIO Interrupt Status for Rising edge for Port + 0. */ + __IM uint32_t STATF2; /*!< (@ 0x00000028) GPIO Interrupt Status for Falling edge for Port + 0. */ + __OM uint32_t CLR2; /*!< (@ 0x0000002C) GPIO Interrupt Clear. */ + __IOM uint32_t ENR2; /*!< (@ 0x00000030) GPIO Interrupt Enable for Rising edge for Port + 0. */ + __IOM uint32_t ENF2; /*!< (@ 0x00000034) GPIO Interrupt Enable for Falling edge for Port + 0. */ +} LPC_GPIOINT_Type; /*!< Size = 56 (0x38) */ + + + +/* =========================================================================================================================== */ +/* ================ PINCONNECT ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief Pin connect block (PINCONNECT) + */ + +typedef struct { /*!< (@ 0x4002C000) PINCONNECT Structure */ + __IOM uint32_t PINSEL0; /*!< (@ 0x00000000) Pin function select register 0. */ + __IOM uint32_t PINSEL1; /*!< (@ 0x00000004) Pin function select register 1. */ + __IOM uint32_t PINSEL2; /*!< (@ 0x00000008) Pin function select register 2. */ + __IOM uint32_t PINSEL3; /*!< (@ 0x0000000C) Pin function select register 3. */ + __IOM uint32_t PINSEL4; /*!< (@ 0x00000010) Pin function select register 4 */ + __IM uint32_t RESERVED[2]; + __IOM uint32_t PINSEL7; /*!< (@ 0x0000001C) Pin function select register 7 */ + __IM uint32_t RESERVED1; + __IOM uint32_t PINSEL9; /*!< (@ 0x00000024) Pin function select register 9 */ + __IOM uint32_t PINSEL10; /*!< (@ 0x00000028) Pin function select register 10 */ + __IM uint32_t RESERVED2[5]; + __IOM uint32_t PINMODE0; /*!< (@ 0x00000040) Pin mode select register 0 */ + __IOM uint32_t PINMODE1; /*!< (@ 0x00000044) Pin mode select register 1 */ + __IOM uint32_t PINMODE2; /*!< (@ 0x00000048) Pin mode select register 2 */ + __IOM uint32_t PINMODE3; /*!< (@ 0x0000004C) Pin mode select register 3. */ + __IOM uint32_t PINMODE4; /*!< (@ 0x00000050) Pin mode select register 4 */ + __IM uint32_t RESERVED3[2]; + __IOM uint32_t PINMODE7; /*!< (@ 0x0000005C) Pin mode select register 7 */ + __IM uint32_t RESERVED4; + __IOM uint32_t PINMODE9; /*!< (@ 0x00000064) Pin mode select register 9 */ + __IOM uint32_t PINMODE_OD0; /*!< (@ 0x00000068) Open drain mode control register 0 */ + __IOM uint32_t PINMODE_OD1; /*!< (@ 0x0000006C) Open drain mode control register 1 */ + __IOM uint32_t PINMODE_OD2; /*!< (@ 0x00000070) Open drain mode control register 2 */ + __IOM uint32_t PINMODE_OD3; /*!< (@ 0x00000074) Open drain mode control register 3 */ + __IOM uint32_t PINMODE_OD4; /*!< (@ 0x00000078) Open drain mode control register 4 */ + __IOM uint32_t I2CPADCFG; /*!< (@ 0x0000007C) I2C Pin Configuration register */ +} LPC_PINCONNECT_Type; /*!< Size = 128 (0x80) */ + + + +/* =========================================================================================================================== */ +/* ================ SSP1 ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief SSP1 controller (SSP1) + */ + +typedef struct { /*!< (@ 0x40030000) SSP1 Structure */ + __IOM uint32_t CR0; /*!< (@ 0x00000000) Control Register 0. Selects the serial clock + rate, bus type, and data size. */ + __IOM uint32_t CR1; /*!< (@ 0x00000004) Control Register 1. Selects master/slave and + other modes. */ + __IOM uint32_t DR; /*!< (@ 0x00000008) Data Register. Writes fill the transmit FIFO, + and reads empty the receive FIFO. */ + __IM uint32_t SR; /*!< (@ 0x0000000C) Status Register */ + __IOM uint32_t CPSR; /*!< (@ 0x00000010) Clock Prescale Register */ + __IOM uint32_t IMSC; /*!< (@ 0x00000014) Interrupt Mask Set and Clear Register */ + __IM uint32_t RIS; /*!< (@ 0x00000018) Raw Interrupt Status Register */ + __IM uint32_t MIS; /*!< (@ 0x0000001C) Masked Interrupt Status Register */ + __OM uint32_t ICR; /*!< (@ 0x00000020) SSPICR Interrupt Clear Register */ + __IOM uint32_t DMACR; /*!< (@ 0x00000024) SSP0 DMA control register */ +} LPC_SSP1_Type; /*!< Size = 40 (0x28) */ + + + +/* =========================================================================================================================== */ +/* ================ ADC ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief Analog-to-Digital Converter (ADC) (ADC) + */ + +typedef struct { /*!< (@ 0x40034000) ADC Structure */ + __IOM uint32_t CR; /*!< (@ 0x00000000) A/D Control Register. The ADCR register must + be written to select the operating mode + before A/D conversion can occur. */ + __IOM uint32_t GDR; /*!< (@ 0x00000004) A/D Global Data Register. This register contains + the ADC's DONE bit and the result of the + most recent A/D conversion. */ + __IM uint32_t RESERVED; + __IOM uint32_t INTEN; /*!< (@ 0x0000000C) A/D Interrupt Enable Register. This register + contains enable bits that allow the DONE + flag of each A/D channel to be included + or excluded from contributing to the generation + of an A/D interrupt. */ + __IM uint32_t DR[8]; /*!< (@ 0x00000010) A/D Channel 0 Data Register. This register contains + the result of the most recent conversion + completed on channel 0. */ + __IM uint32_t STAT; /*!< (@ 0x00000030) A/D Status Register. This register contains DONE + and OVERRUN flags for all of the A/D channels, + as well as the A/D interrupt/DMA flag. */ + __IOM uint32_t TRM; /*!< (@ 0x00000034) ADC trim register. */ +} LPC_ADC_Type; /*!< Size = 56 (0x38) */ + + + +/* =========================================================================================================================== */ +/* ================ CANAFRAM ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief CAN acceptance filter RAM (CANAFRAM) + */ + +typedef struct { /*!< (@ 0x40038000) CANAFRAM Structure */ + __IOM uint32_t MASK[512]; /*!< (@ 0x00000000) CAN AF ram access register */ +} LPC_CANAFRAM_Type; /*!< Size = 2048 (0x800) */ + + + +/* =========================================================================================================================== */ +/* ================ CANAF ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief CAN controller acceptance filter (CANAF) + */ + +typedef struct { /*!< (@ 0x4003C000) CANAF Structure */ + __IOM uint32_t AFMR; /*!< (@ 0x00000000) Acceptance Filter Register */ + __IOM uint32_t SFF_SA; /*!< (@ 0x00000004) Standard Frame Individual Start Address Register */ + __IOM uint32_t SFF_GRP_SA; /*!< (@ 0x00000008) Standard Frame Group Start Address Register */ + __IOM uint32_t EFF_SA; /*!< (@ 0x0000000C) Extended Frame Start Address Register */ + __IOM uint32_t EFF_GRP_SA; /*!< (@ 0x00000010) Extended Frame Group Start Address Register */ + __IOM uint32_t ENDOFTABLE; /*!< (@ 0x00000014) End of AF Tables register */ + __IM uint32_t LUTERRAD; /*!< (@ 0x00000018) LUT Error Address register */ + __IM uint32_t LUTERR; /*!< (@ 0x0000001C) LUT Error Register */ + __IOM uint32_t FCANIE; /*!< (@ 0x00000020) FullCAN interrupt enable register */ + __IOM uint32_t FCANIC0; /*!< (@ 0x00000024) FullCAN interrupt and capture register0 */ + __IOM uint32_t FCANIC1; /*!< (@ 0x00000028) FullCAN interrupt and capture register1 */ +} LPC_CANAF_Type; /*!< Size = 44 (0x2c) */ + + + +/* =========================================================================================================================== */ +/* ================ CCAN ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief Central CAN controller (CCAN) + */ + +typedef struct { /*!< (@ 0x40040000) CCAN Structure */ + __IM uint32_t TXSR; /*!< (@ 0x00000000) CAN Central Transmit Status Register */ + __IM uint32_t RXSR; /*!< (@ 0x00000004) CAN Central Receive Status Register */ + __IM uint32_t MSR; /*!< (@ 0x00000008) CAN Central Miscellaneous Register */ +} LPC_CCAN_Type; /*!< Size = 12 (0xc) */ + + + +/* =========================================================================================================================== */ +/* ================ CAN1 ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief CAN1 controller (CAN1) + */ + +typedef struct { /*!< (@ 0x40044000) CAN1 Structure */ + __IOM uint32_t MOD; /*!< (@ 0x00000000) Controls the operating mode of the CAN Controller. */ + __OM uint32_t CMR; /*!< (@ 0x00000004) Command bits that affect the state of the CAN + Controller */ + __IM uint32_t GSR; /*!< (@ 0x00000008) Global Controller Status and Error Counters. + The error counters can only be written when + RM in CANMOD is 1. */ + __IM uint32_t ICR; /*!< (@ 0x0000000C) Interrupt status, Arbitration Lost Capture, Error + Code Capture */ + __IOM uint32_t IER; /*!< (@ 0x00000010) Interrupt Enable */ + __IOM uint32_t BTR; /*!< (@ 0x00000014) Bus Timing. Can only be written when RM in CANMOD + is 1. */ + __IOM uint32_t EWL; /*!< (@ 0x00000018) Error Warning Limit. Can only be written when + RM in CANMOD is 1. */ + __IM uint32_t SR; /*!< (@ 0x0000001C) Status Register */ + __IOM uint32_t RFS; /*!< (@ 0x00000020) Receive frame status. Can only be written when + RM in CANMOD is 1. */ + __IOM uint32_t RID; /*!< (@ 0x00000024) Received Identifier. Can only be written when + RM in CANMOD is 1. */ + __IOM uint32_t RDA; /*!< (@ 0x00000028) Received data bytes 1-4. Can only be written + when RM in CANMOD is 1. */ + __IOM uint32_t RDB; /*!< (@ 0x0000002C) Received data bytes 5-8. Can only be written + when RM in CANMOD is 1. */ + __IOM uint32_t TFI1; /*!< (@ 0x00000030) Transmitframe info (Tx Buffer ) */ + __IOM uint32_t TID1; /*!< (@ 0x00000034) TransmitIdentifier (Tx Buffer) */ + __IOM uint32_t TDA1; /*!< (@ 0x00000038) Transmitdata bytes 1-4 (Tx Buffer) */ + __IOM uint32_t TDB1; /*!< (@ 0x0000003C) Transmitdata bytes 5-8 (Tx Buffer ) */ + __IOM uint32_t TFI2; /*!< (@ 0x00000040) Transmitframe info (Tx Buffer ) */ + __IOM uint32_t TID2; /*!< (@ 0x00000044) TransmitIdentifier (Tx Buffer) */ + __IOM uint32_t TDA2; /*!< (@ 0x00000048) Transmitdata bytes 1-4 (Tx Buffer) */ + __IOM uint32_t TDB2; /*!< (@ 0x0000004C) Transmitdata bytes 5-8 (Tx Buffer ) */ + __IOM uint32_t TFI3; /*!< (@ 0x00000050) Transmitframe info (Tx Buffer ) */ + __IOM uint32_t TID3; /*!< (@ 0x00000054) TransmitIdentifier (Tx Buffer) */ + __IOM uint32_t TDA3; /*!< (@ 0x00000058) Transmitdata bytes 1-4 (Tx Buffer) */ + __IOM uint32_t TDB3; /*!< (@ 0x0000005C) Transmitdata bytes 5-8 (Tx Buffer ) */ +} LPC_CAN1_Type; /*!< Size = 96 (0x60) */ + + + +/* =========================================================================================================================== */ +/* ================ CAN2 ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief CAN1 controller (CAN2) + */ + +typedef struct { /*!< (@ 0x40048000) CAN2 Structure */ + __IOM uint32_t MOD; /*!< (@ 0x00000000) Controls the operating mode of the CAN Controller. */ + __OM uint32_t CMR; /*!< (@ 0x00000004) Command bits that affect the state of the CAN + Controller */ + __IM uint32_t GSR; /*!< (@ 0x00000008) Global Controller Status and Error Counters. + The error counters can only be written when + RM in CANMOD is 1. */ + __IM uint32_t ICR; /*!< (@ 0x0000000C) Interrupt status, Arbitration Lost Capture, Error + Code Capture */ + __IOM uint32_t IER; /*!< (@ 0x00000010) Interrupt Enable */ + __IOM uint32_t BTR; /*!< (@ 0x00000014) Bus Timing. Can only be written when RM in CANMOD + is 1. */ + __IOM uint32_t EWL; /*!< (@ 0x00000018) Error Warning Limit. Can only be written when + RM in CANMOD is 1. */ + __IM uint32_t SR; /*!< (@ 0x0000001C) Status Register */ + __IOM uint32_t RFS; /*!< (@ 0x00000020) Receive frame status. Can only be written when + RM in CANMOD is 1. */ + __IOM uint32_t RID; /*!< (@ 0x00000024) Received Identifier. Can only be written when + RM in CANMOD is 1. */ + __IOM uint32_t RDA; /*!< (@ 0x00000028) Received data bytes 1-4. Can only be written + when RM in CANMOD is 1. */ + __IOM uint32_t RDB; /*!< (@ 0x0000002C) Received data bytes 5-8. Can only be written + when RM in CANMOD is 1. */ + __IOM uint32_t TFI1; /*!< (@ 0x00000030) Transmitframe info (Tx Buffer ) */ + __IOM uint32_t TID1; /*!< (@ 0x00000034) TransmitIdentifier (Tx Buffer) */ + __IOM uint32_t TDA1; /*!< (@ 0x00000038) Transmitdata bytes 1-4 (Tx Buffer) */ + __IOM uint32_t TDB1; /*!< (@ 0x0000003C) Transmitdata bytes 5-8 (Tx Buffer ) */ + __IOM uint32_t TFI2; /*!< (@ 0x00000040) Transmitframe info (Tx Buffer ) */ + __IOM uint32_t TID2; /*!< (@ 0x00000044) TransmitIdentifier (Tx Buffer) */ + __IOM uint32_t TDA2; /*!< (@ 0x00000048) Transmitdata bytes 1-4 (Tx Buffer) */ + __IOM uint32_t TDB2; /*!< (@ 0x0000004C) Transmitdata bytes 5-8 (Tx Buffer ) */ + __IOM uint32_t TFI3; /*!< (@ 0x00000050) Transmitframe info (Tx Buffer ) */ + __IOM uint32_t TID3; /*!< (@ 0x00000054) TransmitIdentifier (Tx Buffer) */ + __IOM uint32_t TDA3; /*!< (@ 0x00000058) Transmitdata bytes 1-4 (Tx Buffer) */ + __IOM uint32_t TDB3; /*!< (@ 0x0000005C) Transmitdata bytes 5-8 (Tx Buffer ) */ +} LPC_CAN2_Type; /*!< Size = 96 (0x60) */ + + + +/* =========================================================================================================================== */ +/* ================ SSP0 ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief SSP controller (SSP0) + */ + +typedef struct { /*!< (@ 0x40088000) SSP0 Structure */ + __IOM uint32_t CR0; /*!< (@ 0x00000000) Control Register 0. Selects the serial clock + rate, bus type, and data size. */ + __IOM uint32_t CR1; /*!< (@ 0x00000004) Control Register 1. Selects master/slave and + other modes. */ + __IOM uint32_t DR; /*!< (@ 0x00000008) Data Register. Writes fill the transmit FIFO, + and reads empty the receive FIFO. */ + __IM uint32_t SR; /*!< (@ 0x0000000C) Status Register */ + __IOM uint32_t CPSR; /*!< (@ 0x00000010) Clock Prescale Register */ + __IOM uint32_t IMSC; /*!< (@ 0x00000014) Interrupt Mask Set and Clear Register */ + __IM uint32_t RIS; /*!< (@ 0x00000018) Raw Interrupt Status Register */ + __IM uint32_t MIS; /*!< (@ 0x0000001C) Masked Interrupt Status Register */ + __OM uint32_t ICR; /*!< (@ 0x00000020) SSPICR Interrupt Clear Register */ + __IOM uint32_t DMACR; /*!< (@ 0x00000024) SSP0 DMA control register */ +} LPC_SSP0_Type; /*!< Size = 40 (0x28) */ + + + +/* =========================================================================================================================== */ +/* ================ DAC ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief Digital-to-Analog Converter (DAC) (DAC) + */ + +typedef struct { /*!< (@ 0x4008C000) DAC Structure */ + __IOM uint32_t CR; /*!< (@ 0x00000000) D/A Converter Register. This register contains + the digital value to be converted to analog + and a power control bit. */ + __IOM uint32_t CTRL; /*!< (@ 0x00000004) DAC Control register. This register controls + DMA and timer operation. */ + __IOM uint32_t CNTVAL; /*!< (@ 0x00000008) DAC Counter Value register. This register contains + the reload value for the DAC DMA/Interrupt + timer. */ +} LPC_DAC_Type; /*!< Size = 12 (0xc) */ + + + +/* =========================================================================================================================== */ +/* ================ TIMER2 ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief Timer0/1/2/3 (TIMER2) + */ + +typedef struct { /*!< (@ 0x40090000) TIMER2 Structure */ + __IOM uint32_t IR; /*!< (@ 0x00000000) Interrupt Register. The IR can be written to + clear interrupts. The IR can be read to + identify which of eight possible interrupt + sources are pending. */ + __IOM uint32_t TCR; /*!< (@ 0x00000004) Timer Control Register. The TCR is used to control + the Timer Counter functions. The Timer Counter + can be disabled or reset through the TCR. */ + __IOM uint32_t TC; /*!< (@ 0x00000008) Timer Counter. The 32 bit TC is incremented every + PR+1 cycles of PCLK. The TC is controlled + through the TCR. */ + __IOM uint32_t PR; /*!< (@ 0x0000000C) Prescale Register. When the Prescale Counter + (PC) is equal to this value, the next clock + increments the TC and clears the PC. */ + __IOM uint32_t PC; /*!< (@ 0x00000010) Prescale Counter. The 32 bit PC is a counter + which is incremented to the value stored + in PR. When the value in PR is reached, + the TC is incremented and the PC is cleared. + The PC is observable and controllable through + the bus interface. */ + __IOM uint32_t MCR; /*!< (@ 0x00000014) Match Control Register. The MCR is used to control + if an interrupt is generated and if the + TC is reset when a Match occurs. */ + __IOM uint32_t MR[4]; /*!< (@ 0x00000018) Match Register 0. MR0 can be enabled through + the MCR to reset the TC, stop both the TC + and PC, and/or generate an interrupt every + time MR0 matches the TC. */ + __IOM uint32_t CCR; /*!< (@ 0x00000028) Capture Control Register. The CCR controls which + edges of the capture inputs are used to + load the Capture Registers and whether or + not an interrupt is generated when a capture + takes place. */ + __IM uint32_t CR[2]; /*!< (@ 0x0000002C) Capture Register 0. CR0 is loaded with the value + of TC when there is an event on the CAPn.0 + input. */ + __IM uint32_t RESERVED[2]; + __IOM uint32_t EMR; /*!< (@ 0x0000003C) External Match Register. The EMR controls the + external match pins. */ + __IM uint32_t RESERVED1[12]; + __IOM uint32_t CTCR; /*!< (@ 0x00000070) Count Control Register. The CTCR selects between + Timer and Counter mode, and in Counter mode + selects the signal and edge(s) for counting. */ +} LPC_TIMER2_Type; /*!< Size = 116 (0x74) */ + + + +/* =========================================================================================================================== */ +/* ================ TIMER3 ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief Timer0/1/2/3 (TIMER3) + */ + +typedef struct { /*!< (@ 0x40094000) TIMER3 Structure */ + __IOM uint32_t IR; /*!< (@ 0x00000000) Interrupt Register. The IR can be written to + clear interrupts. The IR can be read to + identify which of eight possible interrupt + sources are pending. */ + __IOM uint32_t TCR; /*!< (@ 0x00000004) Timer Control Register. The TCR is used to control + the Timer Counter functions. The Timer Counter + can be disabled or reset through the TCR. */ + __IOM uint32_t TC; /*!< (@ 0x00000008) Timer Counter. The 32 bit TC is incremented every + PR+1 cycles of PCLK. The TC is controlled + through the TCR. */ + __IOM uint32_t PR; /*!< (@ 0x0000000C) Prescale Register. When the Prescale Counter + (PC) is equal to this value, the next clock + increments the TC and clears the PC. */ + __IOM uint32_t PC; /*!< (@ 0x00000010) Prescale Counter. The 32 bit PC is a counter + which is incremented to the value stored + in PR. When the value in PR is reached, + the TC is incremented and the PC is cleared. + The PC is observable and controllable through + the bus interface. */ + __IOM uint32_t MCR; /*!< (@ 0x00000014) Match Control Register. The MCR is used to control + if an interrupt is generated and if the + TC is reset when a Match occurs. */ + __IOM uint32_t MR[4]; /*!< (@ 0x00000018) Match Register 0. MR0 can be enabled through + the MCR to reset the TC, stop both the TC + and PC, and/or generate an interrupt every + time MR0 matches the TC. */ + __IOM uint32_t CCR; /*!< (@ 0x00000028) Capture Control Register. The CCR controls which + edges of the capture inputs are used to + load the Capture Registers and whether or + not an interrupt is generated when a capture + takes place. */ + __IM uint32_t CR[2]; /*!< (@ 0x0000002C) Capture Register 0. CR0 is loaded with the value + of TC when there is an event on the CAPn.0 + input. */ + __IM uint32_t RESERVED[2]; + __IOM uint32_t EMR; /*!< (@ 0x0000003C) External Match Register. The EMR controls the + external match pins. */ + __IM uint32_t RESERVED1[12]; + __IOM uint32_t CTCR; /*!< (@ 0x00000070) Count Control Register. The CTCR selects between + Timer and Counter mode, and in Counter mode + selects the signal and edge(s) for counting. */ +} LPC_TIMER3_Type; /*!< Size = 116 (0x74) */ + + + +/* =========================================================================================================================== */ +/* ================ UART2 ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief UART0/2/3 (UART2) + */ + +typedef struct { /*!< (@ 0x40098000) UART2 Structure */ + + union { + __IM uint32_t RBR; /*!< (@ 0x00000000) Receiver Buffer Register. Contains the next received + character to be read (DLAB =0). */ + __OM uint32_t THR; /*!< (@ 0x00000000) Transmit Holding Regiter. The next character + to be transmitted is written here (DLAB + =0). */ + __IOM uint32_t DLL; /*!< (@ 0x00000000) Divisor Latch LSB. Least significant byte of + the baud rate divisor value. The full divisor + is used to generate a baud rate from the + fractional rate divider (DLAB =1). */ + }; + + union { + __IOM uint32_t DLM; /*!< (@ 0x00000004) Divisor Latch MSB. Most significant byte of the + baud rate divisor value. The full divisor + is used to generate a baud rate from the + fractional rate divider (DLAB =1). */ + __IOM uint32_t IER; /*!< (@ 0x00000004) Interrupt Enable Register. Contains individual + interrupt enable bits for the 7 potential + UART interrupts (DLAB =0). */ + }; + + union { + __IM uint32_t IIR; /*!< (@ 0x00000008) Interrupt ID Register. Identifies which interrupt(s) + are pending. */ + __OM uint32_t FCR; /*!< (@ 0x00000008) FIFO Control Register. Controls UART FIFO usage + and modes. */ + }; + __IOM uint32_t LCR; /*!< (@ 0x0000000C) Line Control Register. Contains controls for + frame formatting and break generation. */ + __IM uint32_t RESERVED; + __IM uint32_t LSR; /*!< (@ 0x00000014) Line Status Register. Contains flags for transmit + and receive status, including line errors. */ + __IM uint32_t RESERVED1; + __IOM uint32_t SCR; /*!< (@ 0x0000001C) Scratch Pad Register. 8-bit temporary storage + for software. */ + __IOM uint32_t ACR; /*!< (@ 0x00000020) Auto-baud Control Register. Contains controls + for the auto-baud feature. */ + __IM uint32_t RESERVED2; + __IOM uint32_t FDR; /*!< (@ 0x00000028) Fractional Divider Register. Generates a clock + input for the baud rate divider. */ + __IM uint32_t RESERVED3; + __IOM uint32_t TER; /*!< (@ 0x00000030) Transmit Enable Register. Turns off UART transmitter + for use with software flow control. */ + __IM uint32_t RESERVED4[6]; + __IOM uint32_t RS485CTRL; /*!< (@ 0x0000004C) RS-485/EIA-485 Control. Contains controls to + configure various aspects of RS-485/EIA-485 + modes. */ + __IOM uint32_t RS485ADRMATCH; /*!< (@ 0x00000050) RS-485/EIA-485 address match. Contains the address + match value for RS-485/EIA-485 mode. */ + __IOM uint32_t RS485DLY; /*!< (@ 0x00000054) RS-485/EIA-485 direction control delay. */ +} LPC_UART2_Type; /*!< Size = 88 (0x58) */ + + + +/* =========================================================================================================================== */ +/* ================ UART3 ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief UART0/2/3 (UART3) + */ + +typedef struct { /*!< (@ 0x4009C000) UART3 Structure */ + + union { + __IM uint32_t RBR; /*!< (@ 0x00000000) Receiver Buffer Register. Contains the next received + character to be read (DLAB =0). */ + __OM uint32_t THR; /*!< (@ 0x00000000) Transmit Holding Regiter. The next character + to be transmitted is written here (DLAB + =0). */ + __IOM uint32_t DLL; /*!< (@ 0x00000000) Divisor Latch LSB. Least significant byte of + the baud rate divisor value. The full divisor + is used to generate a baud rate from the + fractional rate divider (DLAB =1). */ + }; + + union { + __IOM uint32_t DLM; /*!< (@ 0x00000004) Divisor Latch MSB. Most significant byte of the + baud rate divisor value. The full divisor + is used to generate a baud rate from the + fractional rate divider (DLAB =1). */ + __IOM uint32_t IER; /*!< (@ 0x00000004) Interrupt Enable Register. Contains individual + interrupt enable bits for the 7 potential + UART interrupts (DLAB =0). */ + }; + + union { + __IM uint32_t IIR; /*!< (@ 0x00000008) Interrupt ID Register. Identifies which interrupt(s) + are pending. */ + __OM uint32_t FCR; /*!< (@ 0x00000008) FIFO Control Register. Controls UART FIFO usage + and modes. */ + }; + __IOM uint32_t LCR; /*!< (@ 0x0000000C) Line Control Register. Contains controls for + frame formatting and break generation. */ + __IM uint32_t RESERVED; + __IM uint32_t LSR; /*!< (@ 0x00000014) Line Status Register. Contains flags for transmit + and receive status, including line errors. */ + __IM uint32_t RESERVED1; + __IOM uint32_t SCR; /*!< (@ 0x0000001C) Scratch Pad Register. 8-bit temporary storage + for software. */ + __IOM uint32_t ACR; /*!< (@ 0x00000020) Auto-baud Control Register. Contains controls + for the auto-baud feature. */ + __IM uint32_t RESERVED2; + __IOM uint32_t FDR; /*!< (@ 0x00000028) Fractional Divider Register. Generates a clock + input for the baud rate divider. */ + __IM uint32_t RESERVED3; + __IOM uint32_t TER; /*!< (@ 0x00000030) Transmit Enable Register. Turns off UART transmitter + for use with software flow control. */ + __IM uint32_t RESERVED4[6]; + __IOM uint32_t RS485CTRL; /*!< (@ 0x0000004C) RS-485/EIA-485 Control. Contains controls to + configure various aspects of RS-485/EIA-485 + modes. */ + __IOM uint32_t RS485ADRMATCH; /*!< (@ 0x00000050) RS-485/EIA-485 address match. Contains the address + match value for RS-485/EIA-485 mode. */ + __IOM uint32_t RS485DLY; /*!< (@ 0x00000054) RS-485/EIA-485 direction control delay. */ +} LPC_UART3_Type; /*!< Size = 88 (0x58) */ + + + +/* =========================================================================================================================== */ +/* ================ I2S ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief I2S interface (I2S) + */ + +typedef struct { /*!< (@ 0x400A8000) I2S Structure */ + __IOM uint32_t DAO; /*!< (@ 0x00000000) I2S Digital Audio Output Register. Contains control + bits for the I2S transmit channel. */ + __IOM uint32_t DAI; /*!< (@ 0x00000004) I2S Digital Audio Input Register. Contains control + bits for the I2S receive channel. */ + __OM uint32_t TXFIFO; /*!< (@ 0x00000008) I2S Transmit FIFO. Access register for the 8 + x 32-bit transmitter FIFO. */ + __IM uint32_t RXFIFO; /*!< (@ 0x0000000C) I2S Receive FIFO. Access register for the 8 x + 32-bit receiver FIFO. */ + __IM uint32_t STATE; /*!< (@ 0x00000010) I2S Status Feedback Register. Contains status + information about the I2S interface. */ + __IOM uint32_t DMA1; /*!< (@ 0x00000014) I2S DMA Configuration Register 1. Contains control + information for DMA request 1. */ + __IOM uint32_t DMA2; /*!< (@ 0x00000018) I2S DMA Configuration Register 2. Contains control + information for DMA request 2. */ + __IOM uint32_t IRQ; /*!< (@ 0x0000001C) I2S Interrupt Request Control Register. Contains + bits that control how the I2S interrupt + request is generated. */ + __IOM uint32_t TXRATE; /*!< (@ 0x00000020) I2S Transmit MCLK divider. This register determines + the I2S TX MCLK rate by specifying the value + to divide PCLK by in order to produce MCLK. */ + __IOM uint32_t RXRATE; /*!< (@ 0x00000024) I2S Receive MCLK divider. This register determines + the I2S RX MCLK rate by specifying the value + to divide PCLK by in order to produce MCLK. */ + __IOM uint32_t TXBITRATE; /*!< (@ 0x00000028) I2S Transmit bit rate divider. This register + determines the I2S transmit bit rate by + specifying the value to divide TX_MCLK by + in order to produce the transmit bit clock. */ + __IOM uint32_t RXBITRATE; /*!< (@ 0x0000002C) I2S Receive bit rate divider. This register determines + the I2S receive bit rate by specifying the + value to divide RX_MCLK by in order to produce + the receive bit clock. */ + __IOM uint32_t TXMODE; /*!< (@ 0x00000030) I2S Transmit mode control. */ + __IOM uint32_t RXMODE; /*!< (@ 0x00000034) I2S Receive mode control. */ +} LPC_I2S_Type; /*!< Size = 56 (0x38) */ + + + +/* =========================================================================================================================== */ +/* ================ RITIMER ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief Repetitive Interrupt Timer (RIT) (RITIMER) + */ + +typedef struct { /*!< (@ 0x400B0000) RITIMER Structure */ + __IOM uint32_t COMPVAL; /*!< (@ 0x00000000) Compare register */ + __IOM uint32_t MASK; /*!< (@ 0x00000004) Mask register. This register holds the 32-bit + mask value. A 1 written to any bit will + force a compare on the corresponding bit + of the counter and compare register. */ + __IOM uint32_t CTRL; /*!< (@ 0x00000008) Control register. */ + __IOM uint32_t COUNTER; /*!< (@ 0x0000000C) 32-bit counter */ +} LPC_RITIMER_Type; /*!< Size = 16 (0x10) */ + + + +/* =========================================================================================================================== */ +/* ================ MCPWM ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief Motor Control PWM (MCPWM) + */ + +typedef struct { /*!< (@ 0x400B8000) MCPWM Structure */ + __IM uint32_t CON; /*!< (@ 0x00000000) PWM Control read address */ + __OM uint32_t CON_SET; /*!< (@ 0x00000004) PWM Control set address */ + __OM uint32_t CON_CLR; /*!< (@ 0x00000008) PWM Control clear address */ + __IM uint32_t CAPCON; /*!< (@ 0x0000000C) Capture Control read address */ + __OM uint32_t CAPCON_SET; /*!< (@ 0x00000010) Capture Control set address */ + __OM uint32_t CAPCON_CLR; /*!< (@ 0x00000014) Event Control clear address */ + __IOM uint32_t TC[3]; /*!< (@ 0x00000018) Timer Counter register */ + __IOM uint32_t LIM[3]; /*!< (@ 0x00000024) Limit register */ + __IOM uint32_t MAT[3]; /*!< (@ 0x00000030) Match register */ + __IOM uint32_t DT; /*!< (@ 0x0000003C) Dead time register */ + __IOM uint32_t CP; /*!< (@ 0x00000040) Communication Pattern register */ + __IM uint32_t CAP[3]; /*!< (@ 0x00000044) Capture register */ + __IM uint32_t INTEN; /*!< (@ 0x00000050) Interrupt Enable read address */ + __OM uint32_t INTEN_SET; /*!< (@ 0x00000054) Interrupt Enable set address */ + __OM uint32_t INTEN_CLR; /*!< (@ 0x00000058) Interrupt Enable clear address */ + __IM uint32_t CNTCON; /*!< (@ 0x0000005C) Count Control read address */ + __OM uint32_t CNTCON_SET; /*!< (@ 0x00000060) Count Control set address */ + __OM uint32_t CNTCON_CLR; /*!< (@ 0x00000064) Count Control clear address */ + __IM uint32_t INTF; /*!< (@ 0x00000068) Interrupt flags read address */ + __OM uint32_t INTF_SET; /*!< (@ 0x0000006C) Interrupt flags set address */ + __OM uint32_t INTF_CLR; /*!< (@ 0x00000070) Interrupt flags clear address */ + __OM uint32_t CAP_CLR; /*!< (@ 0x00000074) Capture clear address */ +} LPC_MCPWM_Type; /*!< Size = 120 (0x78) */ + + + +/* =========================================================================================================================== */ +/* ================ QEI ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief Quadrature Encoder Interface (QEI) (QEI) + */ + +typedef struct { /*!< (@ 0x400BC000) QEI Structure */ + __OM uint32_t CON; /*!< (@ 0x00000000) Control register */ + __IM uint32_t STAT; /*!< (@ 0x00000004) Status register */ + __IOM uint32_t CONF; /*!< (@ 0x00000008) Configuration register */ + __IM uint32_t POS; /*!< (@ 0x0000000C) Position register */ + __IOM uint32_t MAXPOS; /*!< (@ 0x00000010) Maximum position register */ + __IOM uint32_t CMPOS0; /*!< (@ 0x00000014) Position compare register 0 */ + __IOM uint32_t CMPOS1; /*!< (@ 0x00000018) Position compare register 1 */ + __IOM uint32_t CMPOS2; /*!< (@ 0x0000001C) Position compare register 2 */ + __IM uint32_t INXCNT; /*!< (@ 0x00000020) Index count register 0 */ + __IOM uint32_t INXCMP0; /*!< (@ 0x00000024) Index compare register 0 */ + __IOM uint32_t LOAD; /*!< (@ 0x00000028) Velocity timer reload register */ + __IM uint32_t TIME; /*!< (@ 0x0000002C) Velocity timer register */ + __IM uint32_t VEL; /*!< (@ 0x00000030) Velocity counter register */ + __IM uint32_t CAP; /*!< (@ 0x00000034) Velocity capture register */ + __IOM uint32_t VELCOMP; /*!< (@ 0x00000038) Velocity compare register */ + __IOM uint32_t FILTER; /*!< (@ 0x0000003C) Digital filter register */ + __IM uint32_t RESERVED[998]; + __OM uint32_t IEC; /*!< (@ 0x00000FD8) Interrupt enable clear register */ + __OM uint32_t IES; /*!< (@ 0x00000FDC) Interrupt enable set register */ + __IM uint32_t INTSTAT; /*!< (@ 0x00000FE0) Interrupt status register */ + __IM uint32_t IE; /*!< (@ 0x00000FE4) Interrupt enable register */ + __OM uint32_t CLR; /*!< (@ 0x00000FE8) Interrupt status clear register */ + __OM uint32_t SET; /*!< (@ 0x00000FEC) Interrupt status set register */ +} LPC_QEI_Type; /*!< Size = 4080 (0xff0) */ + + + +/* =========================================================================================================================== */ +/* ================ SYSCON ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief System and clock control (SYSCON) + */ + +typedef struct { /*!< (@ 0x400FC000) SYSCON Structure */ + __IOM uint32_t FLASHCFG; /*!< (@ 0x00000000) Flash Accelerator Configuration Register. Controls + flash access timing. */ + __IM uint32_t RESERVED[31]; + __IOM uint32_t PLL0CON; /*!< (@ 0x00000080) PLL0 Control Register */ + __IOM uint32_t PLL0CFG; /*!< (@ 0x00000084) PLL0 Configuration Register */ + __IM uint32_t PLL0STAT; /*!< (@ 0x00000088) PLL0 Status Register */ + __OM uint32_t PLL0FEED; /*!< (@ 0x0000008C) PLL0 Feed Register */ + __IM uint32_t RESERVED1[4]; + __IOM uint32_t PLL1CON; /*!< (@ 0x000000A0) PLL1 Control Register */ + __IOM uint32_t PLL1CFG; /*!< (@ 0x000000A4) PLL1 Configuration Register */ + __IM uint32_t PLL1STAT; /*!< (@ 0x000000A8) PLL1 Status Register */ + __OM uint32_t PLL1FEED; /*!< (@ 0x000000AC) PLL1 Feed Register */ + __IM uint32_t RESERVED2[4]; + __IOM uint32_t PCON; /*!< (@ 0x000000C0) Power Control Register */ + __IOM uint32_t PCONP; /*!< (@ 0x000000C4) Power Control for Peripherals Register */ + __IM uint32_t RESERVED3[15]; + __IOM uint32_t CCLKCFG; /*!< (@ 0x00000104) CPU Clock Configuration Register */ + __IOM uint32_t USBCLKCFG; /*!< (@ 0x00000108) USB Clock Configuration Register */ + __IOM uint32_t CLKSRCSEL; /*!< (@ 0x0000010C) Clock Source Select Register */ + __IOM uint32_t CANSLEEPCLR; /*!< (@ 0x00000110) Allows clearing the current CAN channel sleep + state as well as reading that state. */ + __IOM uint32_t CANWAKEFLAGS; /*!< (@ 0x00000114) Allows reading the wake-up state of the CAN channels. */ + __IM uint32_t RESERVED4[10]; + __IOM uint32_t EXTINT; /*!< (@ 0x00000140) External Interrupt Flag Register */ + __IM uint32_t RESERVED5; + __IOM uint32_t EXTMODE; /*!< (@ 0x00000148) External Interrupt Mode register */ + __IOM uint32_t EXTPOLAR; /*!< (@ 0x0000014C) External Interrupt Polarity Register */ + __IM uint32_t RESERVED6[12]; + __IOM uint32_t RSID; /*!< (@ 0x00000180) Reset Source Identification Register */ + __IM uint32_t RESERVED7[7]; + __IOM uint32_t SCS; /*!< (@ 0x000001A0) System control and status */ + __IM uint32_t RESERVED8; + __IOM uint32_t PCLKSEL0; /*!< (@ 0x000001A8) Peripheral Clock Selection register 0. */ + __IOM uint32_t PCLKSEL1; /*!< (@ 0x000001AC) Peripheral Clock Selection register 1. */ + __IM uint32_t RESERVED9[4]; + __IOM uint32_t USBINTST; /*!< (@ 0x000001C0) USB Interrupt Status */ + __IOM uint32_t DMACREQSEL; /*!< (@ 0x000001C4) Selects between alternative requests on DMA channels + 0 through 7 and 10 through 15 */ + __IOM uint32_t CLKOUTCFG; /*!< (@ 0x000001C8) Clock Output Configuration Register */ +} LPC_SYSCON_Type; /*!< Size = 460 (0x1cc) */ + + + +/* =========================================================================================================================== */ +/* ================ EMAC ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief Ethernet (EMAC) + */ + +typedef struct { /*!< (@ 0x50000000) EMAC Structure */ + __IOM uint32_t MAC1; /*!< (@ 0x00000000) MAC configuration register 1. */ + __IOM uint32_t MAC2; /*!< (@ 0x00000004) MAC configuration register 2. */ + __IOM uint32_t IPGT; /*!< (@ 0x00000008) Back-to-Back Inter-Packet-Gap register. */ + __IOM uint32_t IPGR; /*!< (@ 0x0000000C) Non Back-to-Back Inter-Packet-Gap register. */ + __IOM uint32_t CLRT; /*!< (@ 0x00000010) Collision window / Retry register. */ + __IOM uint32_t MAXF; /*!< (@ 0x00000014) Maximum Frame register. */ + __IOM uint32_t SUPP; /*!< (@ 0x00000018) PHY Support register. */ + __IOM uint32_t TEST; /*!< (@ 0x0000001C) Test register. */ + __IOM uint32_t MCFG; /*!< (@ 0x00000020) MII Mgmt Configuration register. */ + __IOM uint32_t MCMD; /*!< (@ 0x00000024) MII Mgmt Command register. */ + __IOM uint32_t MADR; /*!< (@ 0x00000028) MII Mgmt Address register. */ + __OM uint32_t MWTD; /*!< (@ 0x0000002C) MII Mgmt Write Data register. */ + __IM uint32_t MRDD; /*!< (@ 0x00000030) MII Mgmt Read Data register. */ + __IM uint32_t MIND; /*!< (@ 0x00000034) MII Mgmt Indicators register. */ + __IM uint32_t RESERVED[2]; + __IOM uint32_t SA0; /*!< (@ 0x00000040) Station Address 0 register. */ + __IOM uint32_t SA1; /*!< (@ 0x00000044) Station Address 1 register. */ + __IOM uint32_t SA2; /*!< (@ 0x00000048) Station Address 2 register. */ + __IM uint32_t RESERVED1[45]; + __IOM uint32_t COMMAND; /*!< (@ 0x00000100) Command register. */ + __IM uint32_t STATUS; /*!< (@ 0x00000104) Status register. */ + __IOM uint32_t RXDESCRIPTOR; /*!< (@ 0x00000108) Receive descriptor base address register. */ + __IOM uint32_t RXSTATUS; /*!< (@ 0x0000010C) Receive status base address register. */ + __IOM uint32_t RXDESCRIPTORNUMBER; /*!< (@ 0x00000110) Receive number of descriptors register. */ + __IM uint32_t RXPRODUCEINDEX; /*!< (@ 0x00000114) Receive produce index register. */ + __IOM uint32_t RXCONSUMEINDEX; /*!< (@ 0x00000118) Receive consume index register. */ + __IOM uint32_t TXDESCRIPTOR; /*!< (@ 0x0000011C) Transmit descriptor base address register. */ + __IOM uint32_t TXSTATUS; /*!< (@ 0x00000120) Transmit status base address register. */ + __IOM uint32_t TXDESCRIPTORNUMBER; /*!< (@ 0x00000124) Transmit number of descriptors register. */ + __IOM uint32_t TXPRODUCEINDEX; /*!< (@ 0x00000128) Transmit produce index register. */ + __IM uint32_t TXCONSUMEINDEX; /*!< (@ 0x0000012C) Transmit consume index register. */ + __IM uint32_t RESERVED2[10]; + __IM uint32_t TSV0; /*!< (@ 0x00000158) Transmit status vector 0 register. */ + __IM uint32_t TSV1; /*!< (@ 0x0000015C) Transmit status vector 1 register. */ + __IM uint32_t RSV; /*!< (@ 0x00000160) Receive status vector register. */ + __IM uint32_t RESERVED3[3]; + __IOM uint32_t FLOWCONTROLCOUNTER; /*!< (@ 0x00000170) Flow control counter register. */ + __IM uint32_t FLOWCONTROLSTATUS; /*!< (@ 0x00000174) Flow control status register. */ + __IM uint32_t RESERVED4[34]; + __IOM uint32_t RXFILTERCTRL; /*!< (@ 0x00000200) Receive filter control register. */ + __IM uint32_t RXFILTERWOLSTATUS; /*!< (@ 0x00000204) Receive filter WoL status register. */ + __OM uint32_t RXFILTERWOLCLEAR; /*!< (@ 0x00000208) Receive filter WoL clear register. */ + __IM uint32_t RESERVED5; + __IOM uint32_t HASHFILTERL; /*!< (@ 0x00000210) Hash filter table LSBs register. */ + __IOM uint32_t HASHFILTERH; /*!< (@ 0x00000214) Hash filter table MSBs register. */ + __IM uint32_t RESERVED6[882]; + __IM uint32_t INTSTATUS; /*!< (@ 0x00000FE0) Interrupt status register. */ + __IOM uint32_t INTENABLE; /*!< (@ 0x00000FE4) Interrupt enable register. */ + __OM uint32_t INTCLEAR; /*!< (@ 0x00000FE8) Interrupt clear register. */ + __OM uint32_t INTSET; /*!< (@ 0x00000FEC) Interrupt set register. */ + __IM uint32_t RESERVED7; + __IOM uint32_t POWERDOWN; /*!< (@ 0x00000FF4) Power-down register. */ +} LPC_EMAC_Type; /*!< Size = 4088 (0xff8) */ + + + +/* =========================================================================================================================== */ +/* ================ GPDMA ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief General purpose DMA controller (GPDMA) + */ + +typedef struct { /*!< (@ 0x50004000) GPDMA Structure */ + __IM uint32_t INTSTAT; /*!< (@ 0x00000000) DMA Interrupt Status Register */ + __IM uint32_t INTTCSTAT; /*!< (@ 0x00000004) DMA Interrupt Terminal Count Request Status Register */ + __OM uint32_t INTTCCLEAR; /*!< (@ 0x00000008) DMA Interrupt Terminal Count Request Clear Register */ + __IM uint32_t INTERRSTAT; /*!< (@ 0x0000000C) DMA Interrupt Error Status Register */ + __OM uint32_t INTERRCLR; /*!< (@ 0x00000010) DMA Interrupt Error Clear Register */ + __IM uint32_t RAWINTTCSTAT; /*!< (@ 0x00000014) DMA Raw Interrupt Terminal Count Status Register */ + __IM uint32_t RAWINTERRSTAT; /*!< (@ 0x00000018) DMA Raw Error Interrupt Status Register */ + __IM uint32_t ENBLDCHNS; /*!< (@ 0x0000001C) DMA Enabled Channel Register */ + __IOM uint32_t SOFTBREQ; /*!< (@ 0x00000020) DMA Software Burst Request Register */ + __IOM uint32_t SOFTSREQ; /*!< (@ 0x00000024) DMA Software Single Request Register */ + __IOM uint32_t SOFTLBREQ; /*!< (@ 0x00000028) DMA Software Last Burst Request Register */ + __IOM uint32_t SOFTLSREQ; /*!< (@ 0x0000002C) DMA Software Last Single Request Register */ + __IOM uint32_t CONFIG; /*!< (@ 0x00000030) DMA Configuration Register */ + __IOM uint32_t SYNC; /*!< (@ 0x00000034) DMA Synchronization Register */ + __IM uint32_t RESERVED[50]; + __IOM uint32_t SRCADDR0; /*!< (@ 0x00000100) DMA Channel 0 Source Address Register */ + __IOM uint32_t DESTADDR0; /*!< (@ 0x00000104) DMA Channel 0 Destination Address Register */ + __IOM uint32_t LLI0; /*!< (@ 0x00000108) DMA Channel 0 Linked List Item Register */ + __IOM uint32_t CONTROL0; /*!< (@ 0x0000010C) DMA Channel 0 Control Register */ + __IOM uint32_t CONFIG0; /*!< (@ 0x00000110) DMA Channel 0 Configuration Register[1] */ + __IM uint32_t RESERVED1[3]; + __IOM uint32_t SRCADDR1; /*!< (@ 0x00000120) DMA Channel 0 Source Address Register */ + __IOM uint32_t DESTADDR1; /*!< (@ 0x00000124) DMA Channel 0 Destination Address Register */ + __IOM uint32_t LLI1; /*!< (@ 0x00000128) DMA Channel 0 Linked List Item Register */ + __IOM uint32_t CONTROL1; /*!< (@ 0x0000012C) DMA Channel 0 Control Register */ + __IOM uint32_t CONFIG1; /*!< (@ 0x00000130) DMA Channel 0 Configuration Register[1] */ + __IM uint32_t RESERVED2[3]; + __IOM uint32_t SRCADDR2; /*!< (@ 0x00000140) DMA Channel 0 Source Address Register */ + __IOM uint32_t DESTADDR2; /*!< (@ 0x00000144) DMA Channel 0 Destination Address Register */ + __IOM uint32_t LLI2; /*!< (@ 0x00000148) DMA Channel 0 Linked List Item Register */ + __IOM uint32_t CONTROL2; /*!< (@ 0x0000014C) DMA Channel 0 Control Register */ + __IOM uint32_t CONFIG2; /*!< (@ 0x00000150) DMA Channel 0 Configuration Register[1] */ + __IM uint32_t RESERVED3[3]; + __IOM uint32_t SRCADDR3; /*!< (@ 0x00000160) DMA Channel 0 Source Address Register */ + __IOM uint32_t DESTADDR3; /*!< (@ 0x00000164) DMA Channel 0 Destination Address Register */ + __IOM uint32_t LLI3; /*!< (@ 0x00000168) DMA Channel 0 Linked List Item Register */ + __IOM uint32_t CONTROL3; /*!< (@ 0x0000016C) DMA Channel 0 Control Register */ + __IOM uint32_t CONFIG3; /*!< (@ 0x00000170) DMA Channel 0 Configuration Register[1] */ + __IM uint32_t RESERVED4[3]; + __IOM uint32_t SRCADDR4; /*!< (@ 0x00000180) DMA Channel 0 Source Address Register */ + __IOM uint32_t DESTADDR4; /*!< (@ 0x00000184) DMA Channel 0 Destination Address Register */ + __IOM uint32_t LLI4; /*!< (@ 0x00000188) DMA Channel 0 Linked List Item Register */ + __IOM uint32_t CONTROL4; /*!< (@ 0x0000018C) DMA Channel 0 Control Register */ + __IOM uint32_t CONFIG4; /*!< (@ 0x00000190) DMA Channel 0 Configuration Register[1] */ + __IM uint32_t RESERVED5[3]; + __IOM uint32_t SRCADDR5; /*!< (@ 0x000001A0) DMA Channel 0 Source Address Register */ + __IOM uint32_t DESTADDR5; /*!< (@ 0x000001A4) DMA Channel 0 Destination Address Register */ + __IOM uint32_t LLI5; /*!< (@ 0x000001A8) DMA Channel 0 Linked List Item Register */ + __IOM uint32_t CONTROL5; /*!< (@ 0x000001AC) DMA Channel 0 Control Register */ + __IOM uint32_t CONFIG5; /*!< (@ 0x000001B0) DMA Channel 0 Configuration Register[1] */ + __IM uint32_t RESERVED6[3]; + __IOM uint32_t SRCADDR6; /*!< (@ 0x000001C0) DMA Channel 0 Source Address Register */ + __IOM uint32_t DESTADDR6; /*!< (@ 0x000001C4) DMA Channel 0 Destination Address Register */ + __IOM uint32_t LLI6; /*!< (@ 0x000001C8) DMA Channel 0 Linked List Item Register */ + __IOM uint32_t CONTROL6; /*!< (@ 0x000001CC) DMA Channel 0 Control Register */ + __IOM uint32_t CONFIG6; /*!< (@ 0x000001D0) DMA Channel 0 Configuration Register[1] */ + __IM uint32_t RESERVED7[3]; + __IOM uint32_t SRCADDR7; /*!< (@ 0x000001E0) DMA Channel 0 Source Address Register */ + __IOM uint32_t DESTADDR7; /*!< (@ 0x000001E4) DMA Channel 0 Destination Address Register */ + __IOM uint32_t LLI7; /*!< (@ 0x000001E8) DMA Channel 0 Linked List Item Register */ + __IOM uint32_t CONTROL7; /*!< (@ 0x000001EC) DMA Channel 0 Control Register */ + __IOM uint32_t CONFIG7; /*!< (@ 0x000001F0) DMA Channel 0 Configuration Register[1] */ +} LPC_GPDMA_Type; /*!< Size = 500 (0x1f4) */ + + + +/* =========================================================================================================================== */ +/* ================ USB ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief USB device/host/OTG controller (USB) + */ + +typedef struct { /*!< (@ 0x50008000) USB Structure */ + __IM uint32_t RESERVED[55]; + __IM uint32_t RXPLEN; /*!< (@ 0x000000DC) USB Receive Packet Length */ + __IM uint32_t RESERVED1[8]; + __IM uint32_t INTST; /*!< (@ 0x00000100) OTG Interrupt Status */ + __IOM uint32_t INTEN; /*!< (@ 0x00000104) OTG Interrupt Enable */ + __OM uint32_t INTSET; /*!< (@ 0x00000108) OTG Interrupt Set */ + __OM uint32_t INTCLR; /*!< (@ 0x0000010C) OTG Interrupt Clear */ + __IOM uint32_t STCTRL; /*!< (@ 0x00000110) OTG Status and Control and USB port select */ + __IOM uint32_t TMR; /*!< (@ 0x00000114) OTG Timer */ + __IM uint32_t RESERVED2[58]; + __IM uint32_t DEVINTST; /*!< (@ 0x00000200) USB Device Interrupt Status */ + __IOM uint32_t DEVINTEN; /*!< (@ 0x00000204) USB Device Interrupt Enable */ + __OM uint32_t DEVINTCLR; /*!< (@ 0x00000208) USB Device Interrupt Clear */ + __OM uint32_t DEVINTSET; /*!< (@ 0x0000020C) USB Device Interrupt Set */ + __OM uint32_t CMDCODE; /*!< (@ 0x00000210) USB Command Code */ + __IM uint32_t CMDDATA; /*!< (@ 0x00000214) USB Command Data */ + __IM uint32_t RXDATA; /*!< (@ 0x00000218) USB Receive Data */ + __OM uint32_t TXDATA; /*!< (@ 0x0000021C) USB Transmit Data */ + __IM uint32_t RESERVED3; + __OM uint32_t TXPLEN; /*!< (@ 0x00000224) USB Transmit Packet Length */ + __IOM uint32_t CTRL; /*!< (@ 0x00000228) USB Control */ + __OM uint32_t DEVINTPRI; /*!< (@ 0x0000022C) USB Device Interrupt Priority */ + __IM uint32_t EPINTST; /*!< (@ 0x00000230) USB Endpoint Interrupt Status */ + __IOM uint32_t EPINTEN; /*!< (@ 0x00000234) USB Endpoint Interrupt Enable */ + __OM uint32_t EPINTCLR; /*!< (@ 0x00000238) USB Endpoint Interrupt Clear */ + __OM uint32_t EPINTSET; /*!< (@ 0x0000023C) USB Endpoint Interrupt Set */ + __OM uint32_t EPINTPRI; /*!< (@ 0x00000240) USB Endpoint Priority */ + __IOM uint32_t REEP; /*!< (@ 0x00000244) USB Realize Endpoint */ + __OM uint32_t EPIND; /*!< (@ 0x00000248) USB Endpoint Index */ + __IOM uint32_t MAXPSIZE; /*!< (@ 0x0000024C) USB MaxPacketSize */ + __IM uint32_t DMARST; /*!< (@ 0x00000250) USB DMA Request Status */ + __OM uint32_t DMARCLR; /*!< (@ 0x00000254) USB DMA Request Clear */ + __OM uint32_t DMARSET; /*!< (@ 0x00000258) USB DMA Request Set */ + __IM uint32_t RESERVED4[9]; + __IOM uint32_t UDCAH; /*!< (@ 0x00000280) USB UDCA Head */ + __IM uint32_t EPDMAST; /*!< (@ 0x00000284) USB Endpoint DMA Status */ + __OM uint32_t EPDMAEN; /*!< (@ 0x00000288) USB Endpoint DMA Enable */ + __OM uint32_t EPDMADIS; /*!< (@ 0x0000028C) USB Endpoint DMA Disable */ + __IM uint32_t DMAINTST; /*!< (@ 0x00000290) USB DMA Interrupt Status */ + __IOM uint32_t DMAINTEN; /*!< (@ 0x00000294) USB DMA Interrupt Enable */ + __IM uint32_t RESERVED5[2]; + __IM uint32_t EOTINTST; /*!< (@ 0x000002A0) USB End of Transfer Interrupt Status */ + __OM uint32_t EOTINTCLR; /*!< (@ 0x000002A4) USB End of Transfer Interrupt Clear */ + __OM uint32_t EOTINTSET; /*!< (@ 0x000002A8) USB End of Transfer Interrupt Set */ + __IM uint32_t NDDRINTST; /*!< (@ 0x000002AC) USB New DD Request Interrupt Status */ + __OM uint32_t NDDRINTCLR; /*!< (@ 0x000002B0) USB New DD Request Interrupt Clear */ + __OM uint32_t NDDRINTSET; /*!< (@ 0x000002B4) USB New DD Request Interrupt Set */ + __IM uint32_t SYSERRINTST; /*!< (@ 0x000002B8) USB System Error Interrupt Status */ + __OM uint32_t SYSERRINTCLR; /*!< (@ 0x000002BC) USB System Error Interrupt Clear */ + __OM uint32_t SYSERRINTSET; /*!< (@ 0x000002C0) USB System Error Interrupt Set */ + __IM uint32_t RESERVED6[15]; + + union { + __IM uint32_t I2C_RX; /*!< (@ 0x00000300) I2C Receive */ + __OM uint32_t I2C_WO; /*!< (@ 0x00000300) I2C Transmit */ + }; + __IM uint32_t I2C_STS; /*!< (@ 0x00000304) I2C Status */ + __IOM uint32_t I2C_CTL; /*!< (@ 0x00000308) I2C Control */ + __IOM uint32_t I2C_CLKHI; /*!< (@ 0x0000030C) I2C Clock High */ + __OM uint32_t I2C_CLKLO; /*!< (@ 0x00000310) I2C Clock Low */ + __IM uint32_t RESERVED7[824]; + + union { + __IOM uint32_t USBCLKCTRL; /*!< (@ 0x00000FF4) USB Clock Control */ + __IOM uint32_t OTGCLKCTRL; /*!< (@ 0x00000FF4) OTG clock controller */ + }; + + union { + __IM uint32_t USBCLKST; /*!< (@ 0x00000FF8) USB Clock Status */ + __IM uint32_t OTGCLKST; /*!< (@ 0x00000FF8) OTG clock status */ + }; +} LPC_USB_Type; /*!< Size = 4092 (0xffc) */ + + + +/* =========================================================================================================================== */ +/* ================ GPIO ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief General Purpose I/O (GPIO) + */ + +typedef struct { /*!< (@ 0x2009C000) GPIO Structure */ + __IOM uint32_t DIR0; /*!< (@ 0x00000000) GPIO Port Direction control register. */ + __IM uint32_t RESERVED[3]; + __IOM uint32_t MASK0; /*!< (@ 0x00000010) Mask register for Port. */ + __IOM uint32_t PIN0; /*!< (@ 0x00000014) Port Pin value register using FIOMASK. */ + __IOM uint32_t SET0; /*!< (@ 0x00000018) Port Output Set register using FIOMASK. */ + __OM uint32_t CLR0; /*!< (@ 0x0000001C) Port Output Clear register using FIOMASK. */ + __IOM uint32_t DIR1; /*!< (@ 0x00000020) GPIO Port Direction control register. */ + __IM uint32_t RESERVED1[3]; + __IOM uint32_t MASK1; /*!< (@ 0x00000030) Mask register for Port. */ + __IOM uint32_t PIN1; /*!< (@ 0x00000034) Port Pin value register using FIOMASK. */ + __IOM uint32_t SET1; /*!< (@ 0x00000038) Port Output Set register using FIOMASK. */ + __OM uint32_t CLR1; /*!< (@ 0x0000003C) Port Output Clear register using FIOMASK. */ + __IOM uint32_t DIR2; /*!< (@ 0x00000040) GPIO Port Direction control register. */ + __IM uint32_t RESERVED2[3]; + __IOM uint32_t MASK2; /*!< (@ 0x00000050) Mask register for Port. */ + __IOM uint32_t PIN2; /*!< (@ 0x00000054) Port Pin value register using FIOMASK. */ + __IOM uint32_t SET2; /*!< (@ 0x00000058) Port Output Set register using FIOMASK. */ + __OM uint32_t CLR2; /*!< (@ 0x0000005C) Port Output Clear register using FIOMASK. */ + __IOM uint32_t DIR3; /*!< (@ 0x00000060) GPIO Port Direction control register. */ + __IM uint32_t RESERVED3[3]; + __IOM uint32_t MASK3; /*!< (@ 0x00000070) Mask register for Port. */ + __IOM uint32_t PIN3; /*!< (@ 0x00000074) Port Pin value register using FIOMASK. */ + __IOM uint32_t SET3; /*!< (@ 0x00000078) Port Output Set register using FIOMASK. */ + __OM uint32_t CLR3; /*!< (@ 0x0000007C) Port Output Clear register using FIOMASK. */ + __IOM uint32_t DIR4; /*!< (@ 0x00000080) GPIO Port Direction control register. */ + __IM uint32_t RESERVED4[3]; + __IOM uint32_t MASK4; /*!< (@ 0x00000090) Mask register for Port. */ + __IOM uint32_t PIN4; /*!< (@ 0x00000094) Port Pin value register using FIOMASK. */ + __IOM uint32_t SET4; /*!< (@ 0x00000098) Port Output Set register using FIOMASK. */ + __OM uint32_t CLR4; /*!< (@ 0x0000009C) Port Output Clear register using FIOMASK. */ +} LPC_GPIO_Type; /*!< Size = 160 (0xa0) */ + + +/** @} */ /* End of group Device_Peripheral_peripherals */ + + +/* =========================================================================================================================== */ +/* ================ Device Specific Peripheral Address Map ================ */ +/* =========================================================================================================================== */ + + +/** @addtogroup Device_Peripheral_peripheralAddr + * @{ + */ + +#define LPC_WDT_BASE 0x40000000UL +#define LPC_TIMER0_BASE 0x40004000UL +#define LPC_TIMER1_BASE 0x40008000UL +#define LPC_UART0_BASE 0x4000C000UL +#define LPC_UART1_BASE 0x40010000UL +#define LPC_PWM1_BASE 0x40018000UL +#define LPC_I2C0_BASE 0x4001C000UL +#define LPC_SPI_BASE 0x40020000UL +#define LPC_RTC_BASE 0x40024000UL +#define LPC_GPIOINT_BASE 0x40028080UL +#define LPC_PINCONNECT_BASE 0x4002C000UL +#define LPC_SSP1_BASE 0x40030000UL +#define LPC_ADC_BASE 0x40034000UL +#define LPC_CANAFRAM_BASE 0x40038000UL +#define LPC_CANAF_BASE 0x4003C000UL +#define LPC_CCAN_BASE 0x40040000UL +#define LPC_CAN1_BASE 0x40044000UL +#define LPC_CAN2_BASE 0x40048000UL +#define LPC_I2C1_BASE 0x4005C000UL +#define LPC_SSP0_BASE 0x40088000UL +#define LPC_DAC_BASE 0x4008C000UL +#define LPC_TIMER2_BASE 0x40090000UL +#define LPC_TIMER3_BASE 0x40094000UL +#define LPC_UART2_BASE 0x40098000UL +#define LPC_UART3_BASE 0x4009C000UL +#define LPC_I2C2_BASE 0x400A0000UL +#define LPC_I2S_BASE 0x400A8000UL +#define LPC_RITIMER_BASE 0x400B0000UL +#define LPC_MCPWM_BASE 0x400B8000UL +#define LPC_QEI_BASE 0x400BC000UL +#define LPC_SYSCON_BASE 0x400FC000UL +#define LPC_EMAC_BASE 0x50000000UL +#define LPC_GPDMA_BASE 0x50004000UL +#define LPC_USB_BASE 0x50008000UL +#define LPC_GPIO_BASE 0x2009C000UL + +/** @} */ /* End of group Device_Peripheral_peripheralAddr */ + + +/* =========================================================================================================================== */ +/* ================ Peripheral declaration ================ */ +/* =========================================================================================================================== */ + + +/** @addtogroup Device_Peripheral_declaration + * @{ + */ + +#define LPC_WDT ((LPC_WDT_Type*) LPC_WDT_BASE) +#define LPC_TIMER0 ((LPC_TIMER0_Type*) LPC_TIMER0_BASE) +#define LPC_TIMER1 ((LPC_TIMER1_Type*) LPC_TIMER1_BASE) +#define LPC_UART0 ((LPC_UART0_Type*) LPC_UART0_BASE) +#define LPC_UART1 ((LPC_UART1_Type*) LPC_UART1_BASE) +#define LPC_PWM1 ((LPC_PWM1_Type*) LPC_PWM1_BASE) +#define LPC_I2C0 ((LPC_I2C0_Type*) LPC_I2C0_BASE) +#define LPC_SPI ((LPC_SPI_Type*) LPC_SPI_BASE) +#define LPC_RTC ((LPC_RTC_Type*) LPC_RTC_BASE) +#define LPC_GPIOINT ((LPC_GPIOINT_Type*) LPC_GPIOINT_BASE) +#define LPC_PINCONNECT ((LPC_PINCONNECT_Type*) LPC_PINCONNECT_BASE) +#define LPC_SSP1 ((LPC_SSP1_Type*) LPC_SSP1_BASE) +#define LPC_ADC ((LPC_ADC_Type*) LPC_ADC_BASE) +#define LPC_CANAFRAM ((LPC_CANAFRAM_Type*) LPC_CANAFRAM_BASE) +#define LPC_CANAF ((LPC_CANAF_Type*) LPC_CANAF_BASE) +#define LPC_CCAN ((LPC_CCAN_Type*) LPC_CCAN_BASE) +#define LPC_CAN1 ((LPC_CAN1_Type*) LPC_CAN1_BASE) +#define LPC_CAN2 ((LPC_CAN2_Type*) LPC_CAN2_BASE) +#define LPC_I2C1 ((LPC_I2C0_Type*) LPC_I2C1_BASE) +#define LPC_SSP0 ((LPC_SSP0_Type*) LPC_SSP0_BASE) +#define LPC_DAC ((LPC_DAC_Type*) LPC_DAC_BASE) +#define LPC_TIMER2 ((LPC_TIMER2_Type*) LPC_TIMER2_BASE) +#define LPC_TIMER3 ((LPC_TIMER3_Type*) LPC_TIMER3_BASE) +#define LPC_UART2 ((LPC_UART2_Type*) LPC_UART2_BASE) +#define LPC_UART3 ((LPC_UART3_Type*) LPC_UART3_BASE) +#define LPC_I2C2 ((LPC_I2C0_Type*) LPC_I2C2_BASE) +#define LPC_I2S ((LPC_I2S_Type*) LPC_I2S_BASE) +#define LPC_RITIMER ((LPC_RITIMER_Type*) LPC_RITIMER_BASE) +#define LPC_MCPWM ((LPC_MCPWM_Type*) LPC_MCPWM_BASE) +#define LPC_QEI ((LPC_QEI_Type*) LPC_QEI_BASE) +#define LPC_SYSCON ((LPC_SYSCON_Type*) LPC_SYSCON_BASE) +#define LPC_EMAC ((LPC_EMAC_Type*) LPC_EMAC_BASE) +#define LPC_GPDMA ((LPC_GPDMA_Type*) LPC_GPDMA_BASE) +#define LPC_USB ((LPC_USB_Type*) LPC_USB_BASE) +#define LPC_GPIO ((LPC_GPIO_Type*) LPC_GPIO_BASE) + +/** @} */ /* End of group Device_Peripheral_declaration */ + + +/* ========================================= End of section using anonymous unions ========================================= */ +#if defined (__CC_ARM) + #pragma pop +#elif defined (__ICCARM__) + /* leave anonymous unions enabled */ +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic pop +#elif defined (__GNUC__) + /* anonymous unions are enabled by default */ +#elif defined (__TMS470__) + /* anonymous unions are enabled by default */ +#elif defined (__TASKING__) + #pragma warning restore +#elif defined (__CSMC__) + /* anonymous unions are enabled by default */ +#endif + + +/* =========================================================================================================================== */ +/* ================ Pos/Mask Peripheral Section ================ */ +/* =========================================================================================================================== */ + + +/** @addtogroup PosMask_peripherals + * @{ + */ + + + +/* =========================================================================================================================== */ +/* ================ LPC_WDT ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== MOD ========================================================== */ +#define WDT_MOD_WDEN_Pos (0UL) /*!< WDEN (Bit 0) */ +#define WDT_MOD_WDEN_Msk (0x1UL) /*!< WDEN (Bitfield-Mask: 0x01) */ +#define WDT_MOD_WDRESET_Pos (1UL) /*!< WDRESET (Bit 1) */ +#define WDT_MOD_WDRESET_Msk (0x2UL) /*!< WDRESET (Bitfield-Mask: 0x01) */ +#define WDT_MOD_WDTOF_Pos (2UL) /*!< WDTOF (Bit 2) */ +#define WDT_MOD_WDTOF_Msk (0x4UL) /*!< WDTOF (Bitfield-Mask: 0x01) */ +#define WDT_MOD_WDINT_Pos (3UL) /*!< WDINT (Bit 3) */ +#define WDT_MOD_WDINT_Msk (0x8UL) /*!< WDINT (Bitfield-Mask: 0x01) */ +/* ========================================================== TC =========================================================== */ +#define WDT_TC_Count_Pos (0UL) /*!< Count (Bit 0) */ +#define WDT_TC_Count_Msk (0xffffffffUL) /*!< Count (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= FEED ========================================================== */ +#define WDT_FEED_Feed_Pos (0UL) /*!< Feed (Bit 0) */ +#define WDT_FEED_Feed_Msk (0xffUL) /*!< Feed (Bitfield-Mask: 0xff) */ +/* ========================================================== TV =========================================================== */ +#define WDT_TV_Count_Pos (0UL) /*!< Count (Bit 0) */ +#define WDT_TV_Count_Msk (0xffffffffUL) /*!< Count (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== CLKSEL ========================================================= */ +#define WDT_CLKSEL_CLKSEL_Pos (0UL) /*!< CLKSEL (Bit 0) */ +#define WDT_CLKSEL_CLKSEL_Msk (0x3UL) /*!< CLKSEL (Bitfield-Mask: 0x03) */ +#define WDT_CLKSEL_LOCK_Pos (31UL) /*!< LOCK (Bit 31) */ +#define WDT_CLKSEL_LOCK_Msk (0x80000000UL) /*!< LOCK (Bitfield-Mask: 0x01) */ + + +/* =========================================================================================================================== */ +/* ================ LPC_TIMER0 ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== IR =========================================================== */ +#define TIMER0_IR_MR0INT_Pos (0UL) /*!< MR0INT (Bit 0) */ +#define TIMER0_IR_MR0INT_Msk (0x1UL) /*!< MR0INT (Bitfield-Mask: 0x01) */ +#define TIMER0_IR_MR1INT_Pos (1UL) /*!< MR1INT (Bit 1) */ +#define TIMER0_IR_MR1INT_Msk (0x2UL) /*!< MR1INT (Bitfield-Mask: 0x01) */ +#define TIMER0_IR_MR2INT_Pos (2UL) /*!< MR2INT (Bit 2) */ +#define TIMER0_IR_MR2INT_Msk (0x4UL) /*!< MR2INT (Bitfield-Mask: 0x01) */ +#define TIMER0_IR_MR3INT_Pos (3UL) /*!< MR3INT (Bit 3) */ +#define TIMER0_IR_MR3INT_Msk (0x8UL) /*!< MR3INT (Bitfield-Mask: 0x01) */ +#define TIMER0_IR_CR0INT_Pos (4UL) /*!< CR0INT (Bit 4) */ +#define TIMER0_IR_CR0INT_Msk (0x10UL) /*!< CR0INT (Bitfield-Mask: 0x01) */ +#define TIMER0_IR_CR1INT_Pos (5UL) /*!< CR1INT (Bit 5) */ +#define TIMER0_IR_CR1INT_Msk (0x20UL) /*!< CR1INT (Bitfield-Mask: 0x01) */ +/* ========================================================== TCR ========================================================== */ +#define TIMER0_TCR_CEN_Pos (0UL) /*!< CEN (Bit 0) */ +#define TIMER0_TCR_CEN_Msk (0x1UL) /*!< CEN (Bitfield-Mask: 0x01) */ +#define TIMER0_TCR_CRST_Pos (1UL) /*!< CRST (Bit 1) */ +#define TIMER0_TCR_CRST_Msk (0x2UL) /*!< CRST (Bitfield-Mask: 0x01) */ +/* ========================================================== TC =========================================================== */ +#define TIMER0_TC_TC_Pos (0UL) /*!< TC (Bit 0) */ +#define TIMER0_TC_TC_Msk (0xffffffffUL) /*!< TC (Bitfield-Mask: 0xffffffff) */ +/* ========================================================== PR =========================================================== */ +#define TIMER0_PR_PM_Pos (0UL) /*!< PM (Bit 0) */ +#define TIMER0_PR_PM_Msk (0xffffffffUL) /*!< PM (Bitfield-Mask: 0xffffffff) */ +/* ========================================================== PC =========================================================== */ +#define TIMER0_PC_PC_Pos (0UL) /*!< PC (Bit 0) */ +#define TIMER0_PC_PC_Msk (0xffffffffUL) /*!< PC (Bitfield-Mask: 0xffffffff) */ +/* ========================================================== MCR ========================================================== */ +#define TIMER0_MCR_MR0I_Pos (0UL) /*!< MR0I (Bit 0) */ +#define TIMER0_MCR_MR0I_Msk (0x1UL) /*!< MR0I (Bitfield-Mask: 0x01) */ +#define TIMER0_MCR_MR0R_Pos (1UL) /*!< MR0R (Bit 1) */ +#define TIMER0_MCR_MR0R_Msk (0x2UL) /*!< MR0R (Bitfield-Mask: 0x01) */ +#define TIMER0_MCR_MR0S_Pos (2UL) /*!< MR0S (Bit 2) */ +#define TIMER0_MCR_MR0S_Msk (0x4UL) /*!< MR0S (Bitfield-Mask: 0x01) */ +#define TIMER0_MCR_MR1I_Pos (3UL) /*!< MR1I (Bit 3) */ +#define TIMER0_MCR_MR1I_Msk (0x8UL) /*!< MR1I (Bitfield-Mask: 0x01) */ +#define TIMER0_MCR_MR1R_Pos (4UL) /*!< MR1R (Bit 4) */ +#define TIMER0_MCR_MR1R_Msk (0x10UL) /*!< MR1R (Bitfield-Mask: 0x01) */ +#define TIMER0_MCR_MR1S_Pos (5UL) /*!< MR1S (Bit 5) */ +#define TIMER0_MCR_MR1S_Msk (0x20UL) /*!< MR1S (Bitfield-Mask: 0x01) */ +#define TIMER0_MCR_MR2I_Pos (6UL) /*!< MR2I (Bit 6) */ +#define TIMER0_MCR_MR2I_Msk (0x40UL) /*!< MR2I (Bitfield-Mask: 0x01) */ +#define TIMER0_MCR_MR2R_Pos (7UL) /*!< MR2R (Bit 7) */ +#define TIMER0_MCR_MR2R_Msk (0x80UL) /*!< MR2R (Bitfield-Mask: 0x01) */ +#define TIMER0_MCR_MR2S_Pos (8UL) /*!< MR2S (Bit 8) */ +#define TIMER0_MCR_MR2S_Msk (0x100UL) /*!< MR2S (Bitfield-Mask: 0x01) */ +#define TIMER0_MCR_MR3I_Pos (9UL) /*!< MR3I (Bit 9) */ +#define TIMER0_MCR_MR3I_Msk (0x200UL) /*!< MR3I (Bitfield-Mask: 0x01) */ +#define TIMER0_MCR_MR3R_Pos (10UL) /*!< MR3R (Bit 10) */ +#define TIMER0_MCR_MR3R_Msk (0x400UL) /*!< MR3R (Bitfield-Mask: 0x01) */ +#define TIMER0_MCR_MR3S_Pos (11UL) /*!< MR3S (Bit 11) */ +#define TIMER0_MCR_MR3S_Msk (0x800UL) /*!< MR3S (Bitfield-Mask: 0x01) */ +/* ========================================================== CCR ========================================================== */ +#define TIMER0_CCR_CAP0RE_Pos (0UL) /*!< CAP0RE (Bit 0) */ +#define TIMER0_CCR_CAP0RE_Msk (0x1UL) /*!< CAP0RE (Bitfield-Mask: 0x01) */ +#define TIMER0_CCR_CAP0FE_Pos (1UL) /*!< CAP0FE (Bit 1) */ +#define TIMER0_CCR_CAP0FE_Msk (0x2UL) /*!< CAP0FE (Bitfield-Mask: 0x01) */ +#define TIMER0_CCR_CAP0I_Pos (2UL) /*!< CAP0I (Bit 2) */ +#define TIMER0_CCR_CAP0I_Msk (0x4UL) /*!< CAP0I (Bitfield-Mask: 0x01) */ +#define TIMER0_CCR_CAP1RE_Pos (3UL) /*!< CAP1RE (Bit 3) */ +#define TIMER0_CCR_CAP1RE_Msk (0x8UL) /*!< CAP1RE (Bitfield-Mask: 0x01) */ +#define TIMER0_CCR_CAP1FE_Pos (4UL) /*!< CAP1FE (Bit 4) */ +#define TIMER0_CCR_CAP1FE_Msk (0x10UL) /*!< CAP1FE (Bitfield-Mask: 0x01) */ +#define TIMER0_CCR_CAP1I_Pos (5UL) /*!< CAP1I (Bit 5) */ +#define TIMER0_CCR_CAP1I_Msk (0x20UL) /*!< CAP1I (Bitfield-Mask: 0x01) */ +/* ========================================================== EMR ========================================================== */ +#define TIMER0_EMR_EM0_Pos (0UL) /*!< EM0 (Bit 0) */ +#define TIMER0_EMR_EM0_Msk (0x1UL) /*!< EM0 (Bitfield-Mask: 0x01) */ +#define TIMER0_EMR_EM1_Pos (1UL) /*!< EM1 (Bit 1) */ +#define TIMER0_EMR_EM1_Msk (0x2UL) /*!< EM1 (Bitfield-Mask: 0x01) */ +#define TIMER0_EMR_EM2_Pos (2UL) /*!< EM2 (Bit 2) */ +#define TIMER0_EMR_EM2_Msk (0x4UL) /*!< EM2 (Bitfield-Mask: 0x01) */ +#define TIMER0_EMR_EM3_Pos (3UL) /*!< EM3 (Bit 3) */ +#define TIMER0_EMR_EM3_Msk (0x8UL) /*!< EM3 (Bitfield-Mask: 0x01) */ +#define TIMER0_EMR_EMC0_Pos (4UL) /*!< EMC0 (Bit 4) */ +#define TIMER0_EMR_EMC0_Msk (0x30UL) /*!< EMC0 (Bitfield-Mask: 0x03) */ +#define TIMER0_EMR_EMC1_Pos (6UL) /*!< EMC1 (Bit 6) */ +#define TIMER0_EMR_EMC1_Msk (0xc0UL) /*!< EMC1 (Bitfield-Mask: 0x03) */ +#define TIMER0_EMR_EMC2_Pos (8UL) /*!< EMC2 (Bit 8) */ +#define TIMER0_EMR_EMC2_Msk (0x300UL) /*!< EMC2 (Bitfield-Mask: 0x03) */ +#define TIMER0_EMR_EMC3_Pos (10UL) /*!< EMC3 (Bit 10) */ +#define TIMER0_EMR_EMC3_Msk (0xc00UL) /*!< EMC3 (Bitfield-Mask: 0x03) */ +/* ========================================================= CTCR ========================================================== */ +#define TIMER0_CTCR_CTMODE_Pos (0UL) /*!< CTMODE (Bit 0) */ +#define TIMER0_CTCR_CTMODE_Msk (0x3UL) /*!< CTMODE (Bitfield-Mask: 0x03) */ +#define TIMER0_CTCR_CINSEL_Pos (2UL) /*!< CINSEL (Bit 2) */ +#define TIMER0_CTCR_CINSEL_Msk (0xcUL) /*!< CINSEL (Bitfield-Mask: 0x03) */ + + +/* =========================================================================================================================== */ +/* ================ LPC_TIMER1 ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== IR =========================================================== */ +#define TIMER1_IR_MR0INT_Pos (0UL) /*!< MR0INT (Bit 0) */ +#define TIMER1_IR_MR0INT_Msk (0x1UL) /*!< MR0INT (Bitfield-Mask: 0x01) */ +#define TIMER1_IR_MR1INT_Pos (1UL) /*!< MR1INT (Bit 1) */ +#define TIMER1_IR_MR1INT_Msk (0x2UL) /*!< MR1INT (Bitfield-Mask: 0x01) */ +#define TIMER1_IR_MR2INT_Pos (2UL) /*!< MR2INT (Bit 2) */ +#define TIMER1_IR_MR2INT_Msk (0x4UL) /*!< MR2INT (Bitfield-Mask: 0x01) */ +#define TIMER1_IR_MR3INT_Pos (3UL) /*!< MR3INT (Bit 3) */ +#define TIMER1_IR_MR3INT_Msk (0x8UL) /*!< MR3INT (Bitfield-Mask: 0x01) */ +#define TIMER1_IR_CR0INT_Pos (4UL) /*!< CR0INT (Bit 4) */ +#define TIMER1_IR_CR0INT_Msk (0x10UL) /*!< CR0INT (Bitfield-Mask: 0x01) */ +#define TIMER1_IR_CR1INT_Pos (5UL) /*!< CR1INT (Bit 5) */ +#define TIMER1_IR_CR1INT_Msk (0x20UL) /*!< CR1INT (Bitfield-Mask: 0x01) */ +/* ========================================================== TCR ========================================================== */ +#define TIMER1_TCR_CEN_Pos (0UL) /*!< CEN (Bit 0) */ +#define TIMER1_TCR_CEN_Msk (0x1UL) /*!< CEN (Bitfield-Mask: 0x01) */ +#define TIMER1_TCR_CRST_Pos (1UL) /*!< CRST (Bit 1) */ +#define TIMER1_TCR_CRST_Msk (0x2UL) /*!< CRST (Bitfield-Mask: 0x01) */ +/* ========================================================== TC =========================================================== */ +#define TIMER1_TC_TC_Pos (0UL) /*!< TC (Bit 0) */ +#define TIMER1_TC_TC_Msk (0xffffffffUL) /*!< TC (Bitfield-Mask: 0xffffffff) */ +/* ========================================================== PR =========================================================== */ +#define TIMER1_PR_PM_Pos (0UL) /*!< PM (Bit 0) */ +#define TIMER1_PR_PM_Msk (0xffffffffUL) /*!< PM (Bitfield-Mask: 0xffffffff) */ +/* ========================================================== PC =========================================================== */ +#define TIMER1_PC_PC_Pos (0UL) /*!< PC (Bit 0) */ +#define TIMER1_PC_PC_Msk (0xffffffffUL) /*!< PC (Bitfield-Mask: 0xffffffff) */ +/* ========================================================== MCR ========================================================== */ +#define TIMER1_MCR_MR0I_Pos (0UL) /*!< MR0I (Bit 0) */ +#define TIMER1_MCR_MR0I_Msk (0x1UL) /*!< MR0I (Bitfield-Mask: 0x01) */ +#define TIMER1_MCR_MR0R_Pos (1UL) /*!< MR0R (Bit 1) */ +#define TIMER1_MCR_MR0R_Msk (0x2UL) /*!< MR0R (Bitfield-Mask: 0x01) */ +#define TIMER1_MCR_MR0S_Pos (2UL) /*!< MR0S (Bit 2) */ +#define TIMER1_MCR_MR0S_Msk (0x4UL) /*!< MR0S (Bitfield-Mask: 0x01) */ +#define TIMER1_MCR_MR1I_Pos (3UL) /*!< MR1I (Bit 3) */ +#define TIMER1_MCR_MR1I_Msk (0x8UL) /*!< MR1I (Bitfield-Mask: 0x01) */ +#define TIMER1_MCR_MR1R_Pos (4UL) /*!< MR1R (Bit 4) */ +#define TIMER1_MCR_MR1R_Msk (0x10UL) /*!< MR1R (Bitfield-Mask: 0x01) */ +#define TIMER1_MCR_MR1S_Pos (5UL) /*!< MR1S (Bit 5) */ +#define TIMER1_MCR_MR1S_Msk (0x20UL) /*!< MR1S (Bitfield-Mask: 0x01) */ +#define TIMER1_MCR_MR2I_Pos (6UL) /*!< MR2I (Bit 6) */ +#define TIMER1_MCR_MR2I_Msk (0x40UL) /*!< MR2I (Bitfield-Mask: 0x01) */ +#define TIMER1_MCR_MR2R_Pos (7UL) /*!< MR2R (Bit 7) */ +#define TIMER1_MCR_MR2R_Msk (0x80UL) /*!< MR2R (Bitfield-Mask: 0x01) */ +#define TIMER1_MCR_MR2S_Pos (8UL) /*!< MR2S (Bit 8) */ +#define TIMER1_MCR_MR2S_Msk (0x100UL) /*!< MR2S (Bitfield-Mask: 0x01) */ +#define TIMER1_MCR_MR3I_Pos (9UL) /*!< MR3I (Bit 9) */ +#define TIMER1_MCR_MR3I_Msk (0x200UL) /*!< MR3I (Bitfield-Mask: 0x01) */ +#define TIMER1_MCR_MR3R_Pos (10UL) /*!< MR3R (Bit 10) */ +#define TIMER1_MCR_MR3R_Msk (0x400UL) /*!< MR3R (Bitfield-Mask: 0x01) */ +#define TIMER1_MCR_MR3S_Pos (11UL) /*!< MR3S (Bit 11) */ +#define TIMER1_MCR_MR3S_Msk (0x800UL) /*!< MR3S (Bitfield-Mask: 0x01) */ +/* ========================================================== CCR ========================================================== */ +#define TIMER1_CCR_CAP0RE_Pos (0UL) /*!< CAP0RE (Bit 0) */ +#define TIMER1_CCR_CAP0RE_Msk (0x1UL) /*!< CAP0RE (Bitfield-Mask: 0x01) */ +#define TIMER1_CCR_CAP0FE_Pos (1UL) /*!< CAP0FE (Bit 1) */ +#define TIMER1_CCR_CAP0FE_Msk (0x2UL) /*!< CAP0FE (Bitfield-Mask: 0x01) */ +#define TIMER1_CCR_CAP0I_Pos (2UL) /*!< CAP0I (Bit 2) */ +#define TIMER1_CCR_CAP0I_Msk (0x4UL) /*!< CAP0I (Bitfield-Mask: 0x01) */ +#define TIMER1_CCR_CAP1RE_Pos (3UL) /*!< CAP1RE (Bit 3) */ +#define TIMER1_CCR_CAP1RE_Msk (0x8UL) /*!< CAP1RE (Bitfield-Mask: 0x01) */ +#define TIMER1_CCR_CAP1FE_Pos (4UL) /*!< CAP1FE (Bit 4) */ +#define TIMER1_CCR_CAP1FE_Msk (0x10UL) /*!< CAP1FE (Bitfield-Mask: 0x01) */ +#define TIMER1_CCR_CAP1I_Pos (5UL) /*!< CAP1I (Bit 5) */ +#define TIMER1_CCR_CAP1I_Msk (0x20UL) /*!< CAP1I (Bitfield-Mask: 0x01) */ +/* ========================================================== EMR ========================================================== */ +#define TIMER1_EMR_EM0_Pos (0UL) /*!< EM0 (Bit 0) */ +#define TIMER1_EMR_EM0_Msk (0x1UL) /*!< EM0 (Bitfield-Mask: 0x01) */ +#define TIMER1_EMR_EM1_Pos (1UL) /*!< EM1 (Bit 1) */ +#define TIMER1_EMR_EM1_Msk (0x2UL) /*!< EM1 (Bitfield-Mask: 0x01) */ +#define TIMER1_EMR_EM2_Pos (2UL) /*!< EM2 (Bit 2) */ +#define TIMER1_EMR_EM2_Msk (0x4UL) /*!< EM2 (Bitfield-Mask: 0x01) */ +#define TIMER1_EMR_EM3_Pos (3UL) /*!< EM3 (Bit 3) */ +#define TIMER1_EMR_EM3_Msk (0x8UL) /*!< EM3 (Bitfield-Mask: 0x01) */ +#define TIMER1_EMR_EMC0_Pos (4UL) /*!< EMC0 (Bit 4) */ +#define TIMER1_EMR_EMC0_Msk (0x30UL) /*!< EMC0 (Bitfield-Mask: 0x03) */ +#define TIMER1_EMR_EMC1_Pos (6UL) /*!< EMC1 (Bit 6) */ +#define TIMER1_EMR_EMC1_Msk (0xc0UL) /*!< EMC1 (Bitfield-Mask: 0x03) */ +#define TIMER1_EMR_EMC2_Pos (8UL) /*!< EMC2 (Bit 8) */ +#define TIMER1_EMR_EMC2_Msk (0x300UL) /*!< EMC2 (Bitfield-Mask: 0x03) */ +#define TIMER1_EMR_EMC3_Pos (10UL) /*!< EMC3 (Bit 10) */ +#define TIMER1_EMR_EMC3_Msk (0xc00UL) /*!< EMC3 (Bitfield-Mask: 0x03) */ +/* ========================================================= CTCR ========================================================== */ +#define TIMER1_CTCR_CTMODE_Pos (0UL) /*!< CTMODE (Bit 0) */ +#define TIMER1_CTCR_CTMODE_Msk (0x3UL) /*!< CTMODE (Bitfield-Mask: 0x03) */ +#define TIMER1_CTCR_CINSEL_Pos (2UL) /*!< CINSEL (Bit 2) */ +#define TIMER1_CTCR_CINSEL_Msk (0xcUL) /*!< CINSEL (Bitfield-Mask: 0x03) */ + + +/* =========================================================================================================================== */ +/* ================ LPC_UART0 ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== RBR ========================================================== */ +#define UART0_RBR_RBR_Pos (0UL) /*!< RBR (Bit 0) */ +#define UART0_RBR_RBR_Msk (0xffUL) /*!< RBR (Bitfield-Mask: 0xff) */ +/* ========================================================== THR ========================================================== */ +#define UART0_THR_THR_Pos (0UL) /*!< THR (Bit 0) */ +#define UART0_THR_THR_Msk (0xffUL) /*!< THR (Bitfield-Mask: 0xff) */ +/* ========================================================== DLL ========================================================== */ +#define UART0_DLL_DLLSB_Pos (0UL) /*!< DLLSB (Bit 0) */ +#define UART0_DLL_DLLSB_Msk (0xffUL) /*!< DLLSB (Bitfield-Mask: 0xff) */ +/* ========================================================== DLM ========================================================== */ +#define UART0_DLM_DLMSB_Pos (0UL) /*!< DLMSB (Bit 0) */ +#define UART0_DLM_DLMSB_Msk (0xffUL) /*!< DLMSB (Bitfield-Mask: 0xff) */ +/* ========================================================== IER ========================================================== */ +#define UART0_IER_RBRIE_Pos (0UL) /*!< RBRIE (Bit 0) */ +#define UART0_IER_RBRIE_Msk (0x1UL) /*!< RBRIE (Bitfield-Mask: 0x01) */ +#define UART0_IER_THREIE_Pos (1UL) /*!< THREIE (Bit 1) */ +#define UART0_IER_THREIE_Msk (0x2UL) /*!< THREIE (Bitfield-Mask: 0x01) */ +#define UART0_IER_RXIE_Pos (2UL) /*!< RXIE (Bit 2) */ +#define UART0_IER_RXIE_Msk (0x4UL) /*!< RXIE (Bitfield-Mask: 0x01) */ +#define UART0_IER_ABEOINTEN_Pos (8UL) /*!< ABEOINTEN (Bit 8) */ +#define UART0_IER_ABEOINTEN_Msk (0x100UL) /*!< ABEOINTEN (Bitfield-Mask: 0x01) */ +#define UART0_IER_ABTOINTEN_Pos (9UL) /*!< ABTOINTEN (Bit 9) */ +#define UART0_IER_ABTOINTEN_Msk (0x200UL) /*!< ABTOINTEN (Bitfield-Mask: 0x01) */ +/* ========================================================== IIR ========================================================== */ +#define UART0_IIR_INTSTATUS_Pos (0UL) /*!< INTSTATUS (Bit 0) */ +#define UART0_IIR_INTSTATUS_Msk (0x1UL) /*!< INTSTATUS (Bitfield-Mask: 0x01) */ +#define UART0_IIR_INTID_Pos (1UL) /*!< INTID (Bit 1) */ +#define UART0_IIR_INTID_Msk (0xeUL) /*!< INTID (Bitfield-Mask: 0x07) */ +#define UART0_IIR_FIFOENABLE_Pos (6UL) /*!< FIFOENABLE (Bit 6) */ +#define UART0_IIR_FIFOENABLE_Msk (0xc0UL) /*!< FIFOENABLE (Bitfield-Mask: 0x03) */ +#define UART0_IIR_ABEOINT_Pos (8UL) /*!< ABEOINT (Bit 8) */ +#define UART0_IIR_ABEOINT_Msk (0x100UL) /*!< ABEOINT (Bitfield-Mask: 0x01) */ +#define UART0_IIR_ABTOINT_Pos (9UL) /*!< ABTOINT (Bit 9) */ +#define UART0_IIR_ABTOINT_Msk (0x200UL) /*!< ABTOINT (Bitfield-Mask: 0x01) */ +/* ========================================================== FCR ========================================================== */ +#define UART0_FCR_FIFOEN_Pos (0UL) /*!< FIFOEN (Bit 0) */ +#define UART0_FCR_FIFOEN_Msk (0x1UL) /*!< FIFOEN (Bitfield-Mask: 0x01) */ +#define UART0_FCR_RXFIFORES_Pos (1UL) /*!< RXFIFORES (Bit 1) */ +#define UART0_FCR_RXFIFORES_Msk (0x2UL) /*!< RXFIFORES (Bitfield-Mask: 0x01) */ +#define UART0_FCR_TXFIFORES_Pos (2UL) /*!< TXFIFORES (Bit 2) */ +#define UART0_FCR_TXFIFORES_Msk (0x4UL) /*!< TXFIFORES (Bitfield-Mask: 0x01) */ +#define UART0_FCR_DMAMODE_Pos (3UL) /*!< DMAMODE (Bit 3) */ +#define UART0_FCR_DMAMODE_Msk (0x8UL) /*!< DMAMODE (Bitfield-Mask: 0x01) */ +#define UART0_FCR_RXTRIGLVL_Pos (6UL) /*!< RXTRIGLVL (Bit 6) */ +#define UART0_FCR_RXTRIGLVL_Msk (0xc0UL) /*!< RXTRIGLVL (Bitfield-Mask: 0x03) */ +/* ========================================================== LCR ========================================================== */ +#define UART0_LCR_WLS_Pos (0UL) /*!< WLS (Bit 0) */ +#define UART0_LCR_WLS_Msk (0x3UL) /*!< WLS (Bitfield-Mask: 0x03) */ +#define UART0_LCR_SBS_Pos (2UL) /*!< SBS (Bit 2) */ +#define UART0_LCR_SBS_Msk (0x4UL) /*!< SBS (Bitfield-Mask: 0x01) */ +#define UART0_LCR_PE_Pos (3UL) /*!< PE (Bit 3) */ +#define UART0_LCR_PE_Msk (0x8UL) /*!< PE (Bitfield-Mask: 0x01) */ +#define UART0_LCR_PS_Pos (4UL) /*!< PS (Bit 4) */ +#define UART0_LCR_PS_Msk (0x30UL) /*!< PS (Bitfield-Mask: 0x03) */ +#define UART0_LCR_BC_Pos (6UL) /*!< BC (Bit 6) */ +#define UART0_LCR_BC_Msk (0x40UL) /*!< BC (Bitfield-Mask: 0x01) */ +#define UART0_LCR_DLAB_Pos (7UL) /*!< DLAB (Bit 7) */ +#define UART0_LCR_DLAB_Msk (0x80UL) /*!< DLAB (Bitfield-Mask: 0x01) */ +/* ========================================================== LSR ========================================================== */ +#define UART0_LSR_RDR_Pos (0UL) /*!< RDR (Bit 0) */ +#define UART0_LSR_RDR_Msk (0x1UL) /*!< RDR (Bitfield-Mask: 0x01) */ +#define UART0_LSR_OE_Pos (1UL) /*!< OE (Bit 1) */ +#define UART0_LSR_OE_Msk (0x2UL) /*!< OE (Bitfield-Mask: 0x01) */ +#define UART0_LSR_PE_Pos (2UL) /*!< PE (Bit 2) */ +#define UART0_LSR_PE_Msk (0x4UL) /*!< PE (Bitfield-Mask: 0x01) */ +#define UART0_LSR_FE_Pos (3UL) /*!< FE (Bit 3) */ +#define UART0_LSR_FE_Msk (0x8UL) /*!< FE (Bitfield-Mask: 0x01) */ +#define UART0_LSR_BI_Pos (4UL) /*!< BI (Bit 4) */ +#define UART0_LSR_BI_Msk (0x10UL) /*!< BI (Bitfield-Mask: 0x01) */ +#define UART0_LSR_THRE_Pos (5UL) /*!< THRE (Bit 5) */ +#define UART0_LSR_THRE_Msk (0x20UL) /*!< THRE (Bitfield-Mask: 0x01) */ +#define UART0_LSR_TEMT_Pos (6UL) /*!< TEMT (Bit 6) */ +#define UART0_LSR_TEMT_Msk (0x40UL) /*!< TEMT (Bitfield-Mask: 0x01) */ +#define UART0_LSR_RXFE_Pos (7UL) /*!< RXFE (Bit 7) */ +#define UART0_LSR_RXFE_Msk (0x80UL) /*!< RXFE (Bitfield-Mask: 0x01) */ +/* ========================================================== SCR ========================================================== */ +#define UART0_SCR_PAD_Pos (0UL) /*!< PAD (Bit 0) */ +#define UART0_SCR_PAD_Msk (0xffUL) /*!< PAD (Bitfield-Mask: 0xff) */ +/* ========================================================== ACR ========================================================== */ +#define UART0_ACR_START_Pos (0UL) /*!< START (Bit 0) */ +#define UART0_ACR_START_Msk (0x1UL) /*!< START (Bitfield-Mask: 0x01) */ +#define UART0_ACR_MODE_Pos (1UL) /*!< MODE (Bit 1) */ +#define UART0_ACR_MODE_Msk (0x2UL) /*!< MODE (Bitfield-Mask: 0x01) */ +#define UART0_ACR_AUTORESTART_Pos (2UL) /*!< AUTORESTART (Bit 2) */ +#define UART0_ACR_AUTORESTART_Msk (0x4UL) /*!< AUTORESTART (Bitfield-Mask: 0x01) */ +#define UART0_ACR_ABEOINTCLR_Pos (8UL) /*!< ABEOINTCLR (Bit 8) */ +#define UART0_ACR_ABEOINTCLR_Msk (0x100UL) /*!< ABEOINTCLR (Bitfield-Mask: 0x01) */ +#define UART0_ACR_ABTOINTCLR_Pos (9UL) /*!< ABTOINTCLR (Bit 9) */ +#define UART0_ACR_ABTOINTCLR_Msk (0x200UL) /*!< ABTOINTCLR (Bitfield-Mask: 0x01) */ +/* ========================================================== FDR ========================================================== */ +#define UART0_FDR_DIVADDVAL_Pos (0UL) /*!< DIVADDVAL (Bit 0) */ +#define UART0_FDR_DIVADDVAL_Msk (0xfUL) /*!< DIVADDVAL (Bitfield-Mask: 0x0f) */ +#define UART0_FDR_MULVAL_Pos (4UL) /*!< MULVAL (Bit 4) */ +#define UART0_FDR_MULVAL_Msk (0xf0UL) /*!< MULVAL (Bitfield-Mask: 0x0f) */ +/* ========================================================== TER ========================================================== */ +#define UART0_TER_TXEN_Pos (7UL) /*!< TXEN (Bit 7) */ +#define UART0_TER_TXEN_Msk (0x80UL) /*!< TXEN (Bitfield-Mask: 0x01) */ +/* ======================================================= RS485CTRL ======================================================= */ +#define UART0_RS485CTRL_NMMEN_Pos (0UL) /*!< NMMEN (Bit 0) */ +#define UART0_RS485CTRL_NMMEN_Msk (0x1UL) /*!< NMMEN (Bitfield-Mask: 0x01) */ +#define UART0_RS485CTRL_RXDIS_Pos (1UL) /*!< RXDIS (Bit 1) */ +#define UART0_RS485CTRL_RXDIS_Msk (0x2UL) /*!< RXDIS (Bitfield-Mask: 0x01) */ +#define UART0_RS485CTRL_AADEN_Pos (2UL) /*!< AADEN (Bit 2) */ +#define UART0_RS485CTRL_AADEN_Msk (0x4UL) /*!< AADEN (Bitfield-Mask: 0x01) */ +#define UART0_RS485CTRL_DCTRL_Pos (4UL) /*!< DCTRL (Bit 4) */ +#define UART0_RS485CTRL_DCTRL_Msk (0x10UL) /*!< DCTRL (Bitfield-Mask: 0x01) */ +#define UART0_RS485CTRL_OINV_Pos (5UL) /*!< OINV (Bit 5) */ +#define UART0_RS485CTRL_OINV_Msk (0x20UL) /*!< OINV (Bitfield-Mask: 0x01) */ +/* ===================================================== RS485ADRMATCH ===================================================== */ +#define UART0_RS485ADRMATCH_ADRMATCH_Pos (0UL) /*!< ADRMATCH (Bit 0) */ +#define UART0_RS485ADRMATCH_ADRMATCH_Msk (0xffUL) /*!< ADRMATCH (Bitfield-Mask: 0xff) */ +/* ======================================================= RS485DLY ======================================================== */ +#define UART0_RS485DLY_DLY_Pos (0UL) /*!< DLY (Bit 0) */ +#define UART0_RS485DLY_DLY_Msk (0xffUL) /*!< DLY (Bitfield-Mask: 0xff) */ + + +/* =========================================================================================================================== */ +/* ================ LPC_UART1 ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== RBR ========================================================== */ +#define UART1_RBR_RBR_Pos (0UL) /*!< RBR (Bit 0) */ +#define UART1_RBR_RBR_Msk (0xffUL) /*!< RBR (Bitfield-Mask: 0xff) */ +/* ========================================================== THR ========================================================== */ +#define UART1_THR_THR_Pos (0UL) /*!< THR (Bit 0) */ +#define UART1_THR_THR_Msk (0xffUL) /*!< THR (Bitfield-Mask: 0xff) */ +/* ========================================================== DLL ========================================================== */ +#define UART1_DLL_DLLSB_Pos (0UL) /*!< DLLSB (Bit 0) */ +#define UART1_DLL_DLLSB_Msk (0xffUL) /*!< DLLSB (Bitfield-Mask: 0xff) */ +/* ========================================================== DLM ========================================================== */ +#define UART1_DLM_DLMSB_Pos (0UL) /*!< DLMSB (Bit 0) */ +#define UART1_DLM_DLMSB_Msk (0xffUL) /*!< DLMSB (Bitfield-Mask: 0xff) */ +/* ========================================================== IER ========================================================== */ +#define UART1_IER_RBRIE_Pos (0UL) /*!< RBRIE (Bit 0) */ +#define UART1_IER_RBRIE_Msk (0x1UL) /*!< RBRIE (Bitfield-Mask: 0x01) */ +#define UART1_IER_THREIE_Pos (1UL) /*!< THREIE (Bit 1) */ +#define UART1_IER_THREIE_Msk (0x2UL) /*!< THREIE (Bitfield-Mask: 0x01) */ +#define UART1_IER_RXIE_Pos (2UL) /*!< RXIE (Bit 2) */ +#define UART1_IER_RXIE_Msk (0x4UL) /*!< RXIE (Bitfield-Mask: 0x01) */ +#define UART1_IER_MSIE_Pos (3UL) /*!< MSIE (Bit 3) */ +#define UART1_IER_MSIE_Msk (0x8UL) /*!< MSIE (Bitfield-Mask: 0x01) */ +#define UART1_IER_CTSIE_Pos (7UL) /*!< CTSIE (Bit 7) */ +#define UART1_IER_CTSIE_Msk (0x80UL) /*!< CTSIE (Bitfield-Mask: 0x01) */ +#define UART1_IER_ABEOIE_Pos (8UL) /*!< ABEOIE (Bit 8) */ +#define UART1_IER_ABEOIE_Msk (0x100UL) /*!< ABEOIE (Bitfield-Mask: 0x01) */ +#define UART1_IER_ABTOIE_Pos (9UL) /*!< ABTOIE (Bit 9) */ +#define UART1_IER_ABTOIE_Msk (0x200UL) /*!< ABTOIE (Bitfield-Mask: 0x01) */ +/* ========================================================== IIR ========================================================== */ +#define UART1_IIR_INTSTATUS_Pos (0UL) /*!< INTSTATUS (Bit 0) */ +#define UART1_IIR_INTSTATUS_Msk (0x1UL) /*!< INTSTATUS (Bitfield-Mask: 0x01) */ +#define UART1_IIR_INTID_Pos (1UL) /*!< INTID (Bit 1) */ +#define UART1_IIR_INTID_Msk (0xeUL) /*!< INTID (Bitfield-Mask: 0x07) */ +#define UART1_IIR_FIFOENABLE_Pos (6UL) /*!< FIFOENABLE (Bit 6) */ +#define UART1_IIR_FIFOENABLE_Msk (0xc0UL) /*!< FIFOENABLE (Bitfield-Mask: 0x03) */ +#define UART1_IIR_ABEOINT_Pos (8UL) /*!< ABEOINT (Bit 8) */ +#define UART1_IIR_ABEOINT_Msk (0x100UL) /*!< ABEOINT (Bitfield-Mask: 0x01) */ +#define UART1_IIR_ABTOINT_Pos (9UL) /*!< ABTOINT (Bit 9) */ +#define UART1_IIR_ABTOINT_Msk (0x200UL) /*!< ABTOINT (Bitfield-Mask: 0x01) */ +/* ========================================================== FCR ========================================================== */ +#define UART1_FCR_FIFOEN_Pos (0UL) /*!< FIFOEN (Bit 0) */ +#define UART1_FCR_FIFOEN_Msk (0x1UL) /*!< FIFOEN (Bitfield-Mask: 0x01) */ +#define UART1_FCR_RXFIFORES_Pos (1UL) /*!< RXFIFORES (Bit 1) */ +#define UART1_FCR_RXFIFORES_Msk (0x2UL) /*!< RXFIFORES (Bitfield-Mask: 0x01) */ +#define UART1_FCR_TXFIFORES_Pos (2UL) /*!< TXFIFORES (Bit 2) */ +#define UART1_FCR_TXFIFORES_Msk (0x4UL) /*!< TXFIFORES (Bitfield-Mask: 0x01) */ +#define UART1_FCR_DMAMODE_Pos (3UL) /*!< DMAMODE (Bit 3) */ +#define UART1_FCR_DMAMODE_Msk (0x8UL) /*!< DMAMODE (Bitfield-Mask: 0x01) */ +#define UART1_FCR_RXTRIGLVL_Pos (6UL) /*!< RXTRIGLVL (Bit 6) */ +#define UART1_FCR_RXTRIGLVL_Msk (0xc0UL) /*!< RXTRIGLVL (Bitfield-Mask: 0x03) */ +/* ========================================================== LCR ========================================================== */ +#define UART1_LCR_WLS_Pos (0UL) /*!< WLS (Bit 0) */ +#define UART1_LCR_WLS_Msk (0x3UL) /*!< WLS (Bitfield-Mask: 0x03) */ +#define UART1_LCR_SBS_Pos (2UL) /*!< SBS (Bit 2) */ +#define UART1_LCR_SBS_Msk (0x4UL) /*!< SBS (Bitfield-Mask: 0x01) */ +#define UART1_LCR_PE_Pos (3UL) /*!< PE (Bit 3) */ +#define UART1_LCR_PE_Msk (0x8UL) /*!< PE (Bitfield-Mask: 0x01) */ +#define UART1_LCR_PS_Pos (4UL) /*!< PS (Bit 4) */ +#define UART1_LCR_PS_Msk (0x30UL) /*!< PS (Bitfield-Mask: 0x03) */ +#define UART1_LCR_BC_Pos (6UL) /*!< BC (Bit 6) */ +#define UART1_LCR_BC_Msk (0x40UL) /*!< BC (Bitfield-Mask: 0x01) */ +#define UART1_LCR_DLAB_Pos (7UL) /*!< DLAB (Bit 7) */ +#define UART1_LCR_DLAB_Msk (0x80UL) /*!< DLAB (Bitfield-Mask: 0x01) */ +/* ========================================================== MCR ========================================================== */ +#define UART1_MCR_DTRCTRL_Pos (0UL) /*!< DTRCTRL (Bit 0) */ +#define UART1_MCR_DTRCTRL_Msk (0x1UL) /*!< DTRCTRL (Bitfield-Mask: 0x01) */ +#define UART1_MCR_RTSCTRL_Pos (1UL) /*!< RTSCTRL (Bit 1) */ +#define UART1_MCR_RTSCTRL_Msk (0x2UL) /*!< RTSCTRL (Bitfield-Mask: 0x01) */ +#define UART1_MCR_LMS_Pos (4UL) /*!< LMS (Bit 4) */ +#define UART1_MCR_LMS_Msk (0x10UL) /*!< LMS (Bitfield-Mask: 0x01) */ +#define UART1_MCR_RTSEN_Pos (6UL) /*!< RTSEN (Bit 6) */ +#define UART1_MCR_RTSEN_Msk (0x40UL) /*!< RTSEN (Bitfield-Mask: 0x01) */ +#define UART1_MCR_CTSEN_Pos (7UL) /*!< CTSEN (Bit 7) */ +#define UART1_MCR_CTSEN_Msk (0x80UL) /*!< CTSEN (Bitfield-Mask: 0x01) */ +/* ========================================================== LSR ========================================================== */ +#define UART1_LSR_RDR_Pos (0UL) /*!< RDR (Bit 0) */ +#define UART1_LSR_RDR_Msk (0x1UL) /*!< RDR (Bitfield-Mask: 0x01) */ +#define UART1_LSR_OE_Pos (1UL) /*!< OE (Bit 1) */ +#define UART1_LSR_OE_Msk (0x2UL) /*!< OE (Bitfield-Mask: 0x01) */ +#define UART1_LSR_PE_Pos (2UL) /*!< PE (Bit 2) */ +#define UART1_LSR_PE_Msk (0x4UL) /*!< PE (Bitfield-Mask: 0x01) */ +#define UART1_LSR_FE_Pos (3UL) /*!< FE (Bit 3) */ +#define UART1_LSR_FE_Msk (0x8UL) /*!< FE (Bitfield-Mask: 0x01) */ +#define UART1_LSR_BI_Pos (4UL) /*!< BI (Bit 4) */ +#define UART1_LSR_BI_Msk (0x10UL) /*!< BI (Bitfield-Mask: 0x01) */ +#define UART1_LSR_THRE_Pos (5UL) /*!< THRE (Bit 5) */ +#define UART1_LSR_THRE_Msk (0x20UL) /*!< THRE (Bitfield-Mask: 0x01) */ +#define UART1_LSR_TEMT_Pos (6UL) /*!< TEMT (Bit 6) */ +#define UART1_LSR_TEMT_Msk (0x40UL) /*!< TEMT (Bitfield-Mask: 0x01) */ +#define UART1_LSR_RXFE_Pos (7UL) /*!< RXFE (Bit 7) */ +#define UART1_LSR_RXFE_Msk (0x80UL) /*!< RXFE (Bitfield-Mask: 0x01) */ +/* ========================================================== MSR ========================================================== */ +#define UART1_MSR_DCTS_Pos (0UL) /*!< DCTS (Bit 0) */ +#define UART1_MSR_DCTS_Msk (0x1UL) /*!< DCTS (Bitfield-Mask: 0x01) */ +#define UART1_MSR_DDSR_Pos (1UL) /*!< DDSR (Bit 1) */ +#define UART1_MSR_DDSR_Msk (0x2UL) /*!< DDSR (Bitfield-Mask: 0x01) */ +#define UART1_MSR_TERI_Pos (2UL) /*!< TERI (Bit 2) */ +#define UART1_MSR_TERI_Msk (0x4UL) /*!< TERI (Bitfield-Mask: 0x01) */ +#define UART1_MSR_DDCD_Pos (3UL) /*!< DDCD (Bit 3) */ +#define UART1_MSR_DDCD_Msk (0x8UL) /*!< DDCD (Bitfield-Mask: 0x01) */ +#define UART1_MSR_CTS_Pos (4UL) /*!< CTS (Bit 4) */ +#define UART1_MSR_CTS_Msk (0x10UL) /*!< CTS (Bitfield-Mask: 0x01) */ +#define UART1_MSR_DSR_Pos (5UL) /*!< DSR (Bit 5) */ +#define UART1_MSR_DSR_Msk (0x20UL) /*!< DSR (Bitfield-Mask: 0x01) */ +#define UART1_MSR_RI_Pos (6UL) /*!< RI (Bit 6) */ +#define UART1_MSR_RI_Msk (0x40UL) /*!< RI (Bitfield-Mask: 0x01) */ +#define UART1_MSR_DCD_Pos (7UL) /*!< DCD (Bit 7) */ +#define UART1_MSR_DCD_Msk (0x80UL) /*!< DCD (Bitfield-Mask: 0x01) */ +/* ========================================================== SCR ========================================================== */ +#define UART1_SCR_Pad_Pos (0UL) /*!< Pad (Bit 0) */ +#define UART1_SCR_Pad_Msk (0xffUL) /*!< Pad (Bitfield-Mask: 0xff) */ +/* ========================================================== ACR ========================================================== */ +#define UART1_ACR_START_Pos (0UL) /*!< START (Bit 0) */ +#define UART1_ACR_START_Msk (0x1UL) /*!< START (Bitfield-Mask: 0x01) */ +#define UART1_ACR_MODE_Pos (1UL) /*!< MODE (Bit 1) */ +#define UART1_ACR_MODE_Msk (0x2UL) /*!< MODE (Bitfield-Mask: 0x01) */ +#define UART1_ACR_AUTORESTART_Pos (2UL) /*!< AUTORESTART (Bit 2) */ +#define UART1_ACR_AUTORESTART_Msk (0x4UL) /*!< AUTORESTART (Bitfield-Mask: 0x01) */ +#define UART1_ACR_ABEOINTCLR_Pos (8UL) /*!< ABEOINTCLR (Bit 8) */ +#define UART1_ACR_ABEOINTCLR_Msk (0x100UL) /*!< ABEOINTCLR (Bitfield-Mask: 0x01) */ +#define UART1_ACR_ABTOINTCLR_Pos (9UL) /*!< ABTOINTCLR (Bit 9) */ +#define UART1_ACR_ABTOINTCLR_Msk (0x200UL) /*!< ABTOINTCLR (Bitfield-Mask: 0x01) */ +/* ========================================================== FDR ========================================================== */ +#define UART1_FDR_DIVADDVAL_Pos (0UL) /*!< DIVADDVAL (Bit 0) */ +#define UART1_FDR_DIVADDVAL_Msk (0xfUL) /*!< DIVADDVAL (Bitfield-Mask: 0x0f) */ +#define UART1_FDR_MULVAL_Pos (4UL) /*!< MULVAL (Bit 4) */ +#define UART1_FDR_MULVAL_Msk (0xf0UL) /*!< MULVAL (Bitfield-Mask: 0x0f) */ +/* ========================================================== TER ========================================================== */ +#define UART1_TER_TXEN_Pos (7UL) /*!< TXEN (Bit 7) */ +#define UART1_TER_TXEN_Msk (0x80UL) /*!< TXEN (Bitfield-Mask: 0x01) */ +/* ======================================================= RS485CTRL ======================================================= */ +#define UART1_RS485CTRL_NMMEN_Pos (0UL) /*!< NMMEN (Bit 0) */ +#define UART1_RS485CTRL_NMMEN_Msk (0x1UL) /*!< NMMEN (Bitfield-Mask: 0x01) */ +#define UART1_RS485CTRL_RXDIS_Pos (1UL) /*!< RXDIS (Bit 1) */ +#define UART1_RS485CTRL_RXDIS_Msk (0x2UL) /*!< RXDIS (Bitfield-Mask: 0x01) */ +#define UART1_RS485CTRL_AADEN_Pos (2UL) /*!< AADEN (Bit 2) */ +#define UART1_RS485CTRL_AADEN_Msk (0x4UL) /*!< AADEN (Bitfield-Mask: 0x01) */ +#define UART1_RS485CTRL_SEL_Pos (3UL) /*!< SEL (Bit 3) */ +#define UART1_RS485CTRL_SEL_Msk (0x8UL) /*!< SEL (Bitfield-Mask: 0x01) */ +#define UART1_RS485CTRL_DCTRL_Pos (4UL) /*!< DCTRL (Bit 4) */ +#define UART1_RS485CTRL_DCTRL_Msk (0x10UL) /*!< DCTRL (Bitfield-Mask: 0x01) */ +#define UART1_RS485CTRL_OINV_Pos (5UL) /*!< OINV (Bit 5) */ +#define UART1_RS485CTRL_OINV_Msk (0x20UL) /*!< OINV (Bitfield-Mask: 0x01) */ +/* ===================================================== RS485ADRMATCH ===================================================== */ +#define UART1_RS485ADRMATCH_ADRMATCH_Pos (0UL) /*!< ADRMATCH (Bit 0) */ +#define UART1_RS485ADRMATCH_ADRMATCH_Msk (0xffUL) /*!< ADRMATCH (Bitfield-Mask: 0xff) */ +/* ======================================================= RS485DLY ======================================================== */ +#define UART1_RS485DLY_DLY_Pos (0UL) /*!< DLY (Bit 0) */ +#define UART1_RS485DLY_DLY_Msk (0xffUL) /*!< DLY (Bitfield-Mask: 0xff) */ + + +/* =========================================================================================================================== */ +/* ================ LPC_PWM1 ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== IR =========================================================== */ +#define PWM1_IR_PWMMR0INT_Pos (0UL) /*!< PWMMR0INT (Bit 0) */ +#define PWM1_IR_PWMMR0INT_Msk (0x1UL) /*!< PWMMR0INT (Bitfield-Mask: 0x01) */ +#define PWM1_IR_PWMMR1INT_Pos (1UL) /*!< PWMMR1INT (Bit 1) */ +#define PWM1_IR_PWMMR1INT_Msk (0x2UL) /*!< PWMMR1INT (Bitfield-Mask: 0x01) */ +#define PWM1_IR_PWMMR2INT_Pos (2UL) /*!< PWMMR2INT (Bit 2) */ +#define PWM1_IR_PWMMR2INT_Msk (0x4UL) /*!< PWMMR2INT (Bitfield-Mask: 0x01) */ +#define PWM1_IR_PWMMR3INT_Pos (3UL) /*!< PWMMR3INT (Bit 3) */ +#define PWM1_IR_PWMMR3INT_Msk (0x8UL) /*!< PWMMR3INT (Bitfield-Mask: 0x01) */ +#define PWM1_IR_PWMCAP0INT_Pos (4UL) /*!< PWMCAP0INT (Bit 4) */ +#define PWM1_IR_PWMCAP0INT_Msk (0x10UL) /*!< PWMCAP0INT (Bitfield-Mask: 0x01) */ +#define PWM1_IR_PWMCAP1INT_Pos (5UL) /*!< PWMCAP1INT (Bit 5) */ +#define PWM1_IR_PWMCAP1INT_Msk (0x20UL) /*!< PWMCAP1INT (Bitfield-Mask: 0x01) */ +#define PWM1_IR_PWMMR4INT_Pos (8UL) /*!< PWMMR4INT (Bit 8) */ +#define PWM1_IR_PWMMR4INT_Msk (0x100UL) /*!< PWMMR4INT (Bitfield-Mask: 0x01) */ +#define PWM1_IR_PWMMR5INT_Pos (9UL) /*!< PWMMR5INT (Bit 9) */ +#define PWM1_IR_PWMMR5INT_Msk (0x200UL) /*!< PWMMR5INT (Bitfield-Mask: 0x01) */ +#define PWM1_IR_PWMMR6INT_Pos (10UL) /*!< PWMMR6INT (Bit 10) */ +#define PWM1_IR_PWMMR6INT_Msk (0x400UL) /*!< PWMMR6INT (Bitfield-Mask: 0x01) */ +/* ========================================================== TCR ========================================================== */ +#define PWM1_TCR_CE_Pos (0UL) /*!< CE (Bit 0) */ +#define PWM1_TCR_CE_Msk (0x1UL) /*!< CE (Bitfield-Mask: 0x01) */ +#define PWM1_TCR_CR_Pos (1UL) /*!< CR (Bit 1) */ +#define PWM1_TCR_CR_Msk (0x2UL) /*!< CR (Bitfield-Mask: 0x01) */ +#define PWM1_TCR_PWMEN_Pos (3UL) /*!< PWMEN (Bit 3) */ +#define PWM1_TCR_PWMEN_Msk (0x8UL) /*!< PWMEN (Bitfield-Mask: 0x01) */ +#define PWM1_TCR_MDIS_Pos (4UL) /*!< MDIS (Bit 4) */ +#define PWM1_TCR_MDIS_Msk (0x10UL) /*!< MDIS (Bitfield-Mask: 0x01) */ +/* ========================================================== TC =========================================================== */ +#define PWM1_TC_TC_Pos (0UL) /*!< TC (Bit 0) */ +#define PWM1_TC_TC_Msk (0xffffffffUL) /*!< TC (Bitfield-Mask: 0xffffffff) */ +/* ========================================================== PR =========================================================== */ +#define PWM1_PR_PM_Pos (0UL) /*!< PM (Bit 0) */ +#define PWM1_PR_PM_Msk (0xffffffffUL) /*!< PM (Bitfield-Mask: 0xffffffff) */ +/* ========================================================== PC =========================================================== */ +#define PWM1_PC_PC_Pos (0UL) /*!< PC (Bit 0) */ +#define PWM1_PC_PC_Msk (0xffffffffUL) /*!< PC (Bitfield-Mask: 0xffffffff) */ +/* ========================================================== MCR ========================================================== */ +#define PWM1_MCR_PWMMR0I_Pos (0UL) /*!< PWMMR0I (Bit 0) */ +#define PWM1_MCR_PWMMR0I_Msk (0x1UL) /*!< PWMMR0I (Bitfield-Mask: 0x01) */ +#define PWM1_MCR_PWMMR0R_Pos (1UL) /*!< PWMMR0R (Bit 1) */ +#define PWM1_MCR_PWMMR0R_Msk (0x2UL) /*!< PWMMR0R (Bitfield-Mask: 0x01) */ +#define PWM1_MCR_PWMMR0S_Pos (2UL) /*!< PWMMR0S (Bit 2) */ +#define PWM1_MCR_PWMMR0S_Msk (0x4UL) /*!< PWMMR0S (Bitfield-Mask: 0x01) */ +#define PWM1_MCR_PWMMR1I_Pos (3UL) /*!< PWMMR1I (Bit 3) */ +#define PWM1_MCR_PWMMR1I_Msk (0x8UL) /*!< PWMMR1I (Bitfield-Mask: 0x01) */ +#define PWM1_MCR_PWMMR1R_Pos (4UL) /*!< PWMMR1R (Bit 4) */ +#define PWM1_MCR_PWMMR1R_Msk (0x10UL) /*!< PWMMR1R (Bitfield-Mask: 0x01) */ +#define PWM1_MCR_PWMMR1S_Pos (5UL) /*!< PWMMR1S (Bit 5) */ +#define PWM1_MCR_PWMMR1S_Msk (0x20UL) /*!< PWMMR1S (Bitfield-Mask: 0x01) */ +#define PWM1_MCR_PWMMR2I_Pos (6UL) /*!< PWMMR2I (Bit 6) */ +#define PWM1_MCR_PWMMR2I_Msk (0x40UL) /*!< PWMMR2I (Bitfield-Mask: 0x01) */ +#define PWM1_MCR_PWMMR2R_Pos (7UL) /*!< PWMMR2R (Bit 7) */ +#define PWM1_MCR_PWMMR2R_Msk (0x80UL) /*!< PWMMR2R (Bitfield-Mask: 0x01) */ +#define PWM1_MCR_PWMMR2S_Pos (8UL) /*!< PWMMR2S (Bit 8) */ +#define PWM1_MCR_PWMMR2S_Msk (0x100UL) /*!< PWMMR2S (Bitfield-Mask: 0x01) */ +#define PWM1_MCR_PWMMR3I_Pos (9UL) /*!< PWMMR3I (Bit 9) */ +#define PWM1_MCR_PWMMR3I_Msk (0x200UL) /*!< PWMMR3I (Bitfield-Mask: 0x01) */ +#define PWM1_MCR_PWMMR3R_Pos (10UL) /*!< PWMMR3R (Bit 10) */ +#define PWM1_MCR_PWMMR3R_Msk (0x400UL) /*!< PWMMR3R (Bitfield-Mask: 0x01) */ +#define PWM1_MCR_PWMMR3S_Pos (11UL) /*!< PWMMR3S (Bit 11) */ +#define PWM1_MCR_PWMMR3S_Msk (0x800UL) /*!< PWMMR3S (Bitfield-Mask: 0x01) */ +#define PWM1_MCR_PWMMR4I_Pos (12UL) /*!< PWMMR4I (Bit 12) */ +#define PWM1_MCR_PWMMR4I_Msk (0x1000UL) /*!< PWMMR4I (Bitfield-Mask: 0x01) */ +#define PWM1_MCR_PWMMR4R_Pos (13UL) /*!< PWMMR4R (Bit 13) */ +#define PWM1_MCR_PWMMR4R_Msk (0x2000UL) /*!< PWMMR4R (Bitfield-Mask: 0x01) */ +#define PWM1_MCR_PWMMR4S_Pos (14UL) /*!< PWMMR4S (Bit 14) */ +#define PWM1_MCR_PWMMR4S_Msk (0x4000UL) /*!< PWMMR4S (Bitfield-Mask: 0x01) */ +#define PWM1_MCR_PWMMR5I_Pos (15UL) /*!< PWMMR5I (Bit 15) */ +#define PWM1_MCR_PWMMR5I_Msk (0x8000UL) /*!< PWMMR5I (Bitfield-Mask: 0x01) */ +#define PWM1_MCR_PWMMR5R_Pos (16UL) /*!< PWMMR5R (Bit 16) */ +#define PWM1_MCR_PWMMR5R_Msk (0x10000UL) /*!< PWMMR5R (Bitfield-Mask: 0x01) */ +#define PWM1_MCR_PWMMR5S_Pos (17UL) /*!< PWMMR5S (Bit 17) */ +#define PWM1_MCR_PWMMR5S_Msk (0x20000UL) /*!< PWMMR5S (Bitfield-Mask: 0x01) */ +#define PWM1_MCR_PWMMR6I_Pos (18UL) /*!< PWMMR6I (Bit 18) */ +#define PWM1_MCR_PWMMR6I_Msk (0x40000UL) /*!< PWMMR6I (Bitfield-Mask: 0x01) */ +#define PWM1_MCR_PWMMR6R_Pos (19UL) /*!< PWMMR6R (Bit 19) */ +#define PWM1_MCR_PWMMR6R_Msk (0x80000UL) /*!< PWMMR6R (Bitfield-Mask: 0x01) */ +#define PWM1_MCR_PWMMR6S_Pos (20UL) /*!< PWMMR6S (Bit 20) */ +#define PWM1_MCR_PWMMR6S_Msk (0x100000UL) /*!< PWMMR6S (Bitfield-Mask: 0x01) */ +/* ========================================================== MR0 ========================================================== */ +#define PWM1_MR0_MATCH_Pos (0UL) /*!< MATCH (Bit 0) */ +#define PWM1_MR0_MATCH_Msk (0xffffffffUL) /*!< MATCH (Bitfield-Mask: 0xffffffff) */ +/* ========================================================== MR1 ========================================================== */ +#define PWM1_MR1_MATCH_Pos (0UL) /*!< MATCH (Bit 0) */ +#define PWM1_MR1_MATCH_Msk (0xffffffffUL) /*!< MATCH (Bitfield-Mask: 0xffffffff) */ +/* ========================================================== MR2 ========================================================== */ +#define PWM1_MR2_MATCH_Pos (0UL) /*!< MATCH (Bit 0) */ +#define PWM1_MR2_MATCH_Msk (0xffffffffUL) /*!< MATCH (Bitfield-Mask: 0xffffffff) */ +/* ========================================================== MR3 ========================================================== */ +#define PWM1_MR3_MATCH_Pos (0UL) /*!< MATCH (Bit 0) */ +#define PWM1_MR3_MATCH_Msk (0xffffffffUL) /*!< MATCH (Bitfield-Mask: 0xffffffff) */ +/* ========================================================== CCR ========================================================== */ +#define PWM1_CCR_CAP0_R_Pos (0UL) /*!< CAP0_R (Bit 0) */ +#define PWM1_CCR_CAP0_R_Msk (0x1UL) /*!< CAP0_R (Bitfield-Mask: 0x01) */ +#define PWM1_CCR_CAP0_F_Pos (1UL) /*!< CAP0_F (Bit 1) */ +#define PWM1_CCR_CAP0_F_Msk (0x2UL) /*!< CAP0_F (Bitfield-Mask: 0x01) */ +#define PWM1_CCR_CAP0_I_Pos (2UL) /*!< CAP0_I (Bit 2) */ +#define PWM1_CCR_CAP0_I_Msk (0x4UL) /*!< CAP0_I (Bitfield-Mask: 0x01) */ +#define PWM1_CCR_CAP1_R_Pos (3UL) /*!< CAP1_R (Bit 3) */ +#define PWM1_CCR_CAP1_R_Msk (0x8UL) /*!< CAP1_R (Bitfield-Mask: 0x01) */ +#define PWM1_CCR_CAP1_F_Pos (4UL) /*!< CAP1_F (Bit 4) */ +#define PWM1_CCR_CAP1_F_Msk (0x10UL) /*!< CAP1_F (Bitfield-Mask: 0x01) */ +#define PWM1_CCR_CAP1_I_Pos (5UL) /*!< CAP1_I (Bit 5) */ +#define PWM1_CCR_CAP1_I_Msk (0x20UL) /*!< CAP1_I (Bitfield-Mask: 0x01) */ +/* ========================================================== MR4 ========================================================== */ +#define PWM1_MR4_MATCH_Pos (0UL) /*!< MATCH (Bit 0) */ +#define PWM1_MR4_MATCH_Msk (0xffffffffUL) /*!< MATCH (Bitfield-Mask: 0xffffffff) */ +/* ========================================================== MR5 ========================================================== */ +#define PWM1_MR5_MATCH_Pos (0UL) /*!< MATCH (Bit 0) */ +#define PWM1_MR5_MATCH_Msk (0xffffffffUL) /*!< MATCH (Bitfield-Mask: 0xffffffff) */ +/* ========================================================== MR6 ========================================================== */ +#define PWM1_MR6_MATCH_Pos (0UL) /*!< MATCH (Bit 0) */ +#define PWM1_MR6_MATCH_Msk (0xffffffffUL) /*!< MATCH (Bitfield-Mask: 0xffffffff) */ +/* ========================================================== PCR ========================================================== */ +#define PWM1_PCR_PWMSEL2_Pos (2UL) /*!< PWMSEL2 (Bit 2) */ +#define PWM1_PCR_PWMSEL2_Msk (0x4UL) /*!< PWMSEL2 (Bitfield-Mask: 0x01) */ +#define PWM1_PCR_PWMSEL3_Pos (3UL) /*!< PWMSEL3 (Bit 3) */ +#define PWM1_PCR_PWMSEL3_Msk (0x8UL) /*!< PWMSEL3 (Bitfield-Mask: 0x01) */ +#define PWM1_PCR_PWMSEL4_Pos (4UL) /*!< PWMSEL4 (Bit 4) */ +#define PWM1_PCR_PWMSEL4_Msk (0x10UL) /*!< PWMSEL4 (Bitfield-Mask: 0x01) */ +#define PWM1_PCR_PWMSEL5_Pos (5UL) /*!< PWMSEL5 (Bit 5) */ +#define PWM1_PCR_PWMSEL5_Msk (0x20UL) /*!< PWMSEL5 (Bitfield-Mask: 0x01) */ +#define PWM1_PCR_PWMSEL6_Pos (6UL) /*!< PWMSEL6 (Bit 6) */ +#define PWM1_PCR_PWMSEL6_Msk (0x40UL) /*!< PWMSEL6 (Bitfield-Mask: 0x01) */ +#define PWM1_PCR_PWMENA1_Pos (9UL) /*!< PWMENA1 (Bit 9) */ +#define PWM1_PCR_PWMENA1_Msk (0x200UL) /*!< PWMENA1 (Bitfield-Mask: 0x01) */ +#define PWM1_PCR_PWMENA2_Pos (10UL) /*!< PWMENA2 (Bit 10) */ +#define PWM1_PCR_PWMENA2_Msk (0x400UL) /*!< PWMENA2 (Bitfield-Mask: 0x01) */ +#define PWM1_PCR_PWMENA3_Pos (11UL) /*!< PWMENA3 (Bit 11) */ +#define PWM1_PCR_PWMENA3_Msk (0x800UL) /*!< PWMENA3 (Bitfield-Mask: 0x01) */ +#define PWM1_PCR_PWMENA4_Pos (12UL) /*!< PWMENA4 (Bit 12) */ +#define PWM1_PCR_PWMENA4_Msk (0x1000UL) /*!< PWMENA4 (Bitfield-Mask: 0x01) */ +#define PWM1_PCR_PWMENA5_Pos (13UL) /*!< PWMENA5 (Bit 13) */ +#define PWM1_PCR_PWMENA5_Msk (0x2000UL) /*!< PWMENA5 (Bitfield-Mask: 0x01) */ +#define PWM1_PCR_PWMENA6_Pos (14UL) /*!< PWMENA6 (Bit 14) */ +#define PWM1_PCR_PWMENA6_Msk (0x4000UL) /*!< PWMENA6 (Bitfield-Mask: 0x01) */ +/* ========================================================== LER ========================================================== */ +#define PWM1_LER_MAT0LATCHEN_Pos (0UL) /*!< MAT0LATCHEN (Bit 0) */ +#define PWM1_LER_MAT0LATCHEN_Msk (0x1UL) /*!< MAT0LATCHEN (Bitfield-Mask: 0x01) */ +#define PWM1_LER_MAT1LATCHEN_Pos (1UL) /*!< MAT1LATCHEN (Bit 1) */ +#define PWM1_LER_MAT1LATCHEN_Msk (0x2UL) /*!< MAT1LATCHEN (Bitfield-Mask: 0x01) */ +#define PWM1_LER_MAT2LATCHEN_Pos (2UL) /*!< MAT2LATCHEN (Bit 2) */ +#define PWM1_LER_MAT2LATCHEN_Msk (0x4UL) /*!< MAT2LATCHEN (Bitfield-Mask: 0x01) */ +#define PWM1_LER_MAT3LATCHEN_Pos (3UL) /*!< MAT3LATCHEN (Bit 3) */ +#define PWM1_LER_MAT3LATCHEN_Msk (0x8UL) /*!< MAT3LATCHEN (Bitfield-Mask: 0x01) */ +#define PWM1_LER_MAT4LATCHEN_Pos (4UL) /*!< MAT4LATCHEN (Bit 4) */ +#define PWM1_LER_MAT4LATCHEN_Msk (0x10UL) /*!< MAT4LATCHEN (Bitfield-Mask: 0x01) */ +#define PWM1_LER_MAT5LATCHEN_Pos (5UL) /*!< MAT5LATCHEN (Bit 5) */ +#define PWM1_LER_MAT5LATCHEN_Msk (0x20UL) /*!< MAT5LATCHEN (Bitfield-Mask: 0x01) */ +#define PWM1_LER_MAT6LATCHEN_Pos (6UL) /*!< MAT6LATCHEN (Bit 6) */ +#define PWM1_LER_MAT6LATCHEN_Msk (0x40UL) /*!< MAT6LATCHEN (Bitfield-Mask: 0x01) */ +/* ========================================================= CTCR ========================================================== */ +#define PWM1_CTCR_MOD_Pos (0UL) /*!< MOD (Bit 0) */ +#define PWM1_CTCR_MOD_Msk (0x3UL) /*!< MOD (Bitfield-Mask: 0x03) */ +#define PWM1_CTCR_CIS_Pos (2UL) /*!< CIS (Bit 2) */ +#define PWM1_CTCR_CIS_Msk (0xcUL) /*!< CIS (Bitfield-Mask: 0x03) */ + + +/* =========================================================================================================================== */ +/* ================ LPC_I2C0 ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== CONSET ========================================================= */ +#define I2C0_CONSET_AA_Pos (2UL) /*!< AA (Bit 2) */ +#define I2C0_CONSET_AA_Msk (0x4UL) /*!< AA (Bitfield-Mask: 0x01) */ +#define I2C0_CONSET_SI_Pos (3UL) /*!< SI (Bit 3) */ +#define I2C0_CONSET_SI_Msk (0x8UL) /*!< SI (Bitfield-Mask: 0x01) */ +#define I2C0_CONSET_STO_Pos (4UL) /*!< STO (Bit 4) */ +#define I2C0_CONSET_STO_Msk (0x10UL) /*!< STO (Bitfield-Mask: 0x01) */ +#define I2C0_CONSET_STA_Pos (5UL) /*!< STA (Bit 5) */ +#define I2C0_CONSET_STA_Msk (0x20UL) /*!< STA (Bitfield-Mask: 0x01) */ +#define I2C0_CONSET_I2EN_Pos (6UL) /*!< I2EN (Bit 6) */ +#define I2C0_CONSET_I2EN_Msk (0x40UL) /*!< I2EN (Bitfield-Mask: 0x01) */ +/* ========================================================= STAT ========================================================== */ +#define I2C0_STAT_Status_Pos (3UL) /*!< Status (Bit 3) */ +#define I2C0_STAT_Status_Msk (0xf8UL) /*!< Status (Bitfield-Mask: 0x1f) */ +/* ========================================================== DAT ========================================================== */ +#define I2C0_DAT_Data_Pos (0UL) /*!< Data (Bit 0) */ +#define I2C0_DAT_Data_Msk (0xffUL) /*!< Data (Bitfield-Mask: 0xff) */ +/* ========================================================= ADR0 ========================================================== */ +#define I2C0_ADR0_GC_Pos (0UL) /*!< GC (Bit 0) */ +#define I2C0_ADR0_GC_Msk (0x1UL) /*!< GC (Bitfield-Mask: 0x01) */ +#define I2C0_ADR0_Address_Pos (1UL) /*!< Address (Bit 1) */ +#define I2C0_ADR0_Address_Msk (0xfeUL) /*!< Address (Bitfield-Mask: 0x7f) */ +/* ========================================================= SCLH ========================================================== */ +#define I2C0_SCLH_SCLH_Pos (0UL) /*!< SCLH (Bit 0) */ +#define I2C0_SCLH_SCLH_Msk (0xffffUL) /*!< SCLH (Bitfield-Mask: 0xffff) */ +/* ========================================================= SCLL ========================================================== */ +#define I2C0_SCLL_SCLL_Pos (0UL) /*!< SCLL (Bit 0) */ +#define I2C0_SCLL_SCLL_Msk (0xffffUL) /*!< SCLL (Bitfield-Mask: 0xffff) */ +/* ======================================================== CONCLR ========================================================= */ +#define I2C0_CONCLR_AAC_Pos (2UL) /*!< AAC (Bit 2) */ +#define I2C0_CONCLR_AAC_Msk (0x4UL) /*!< AAC (Bitfield-Mask: 0x01) */ +#define I2C0_CONCLR_SIC_Pos (3UL) /*!< SIC (Bit 3) */ +#define I2C0_CONCLR_SIC_Msk (0x8UL) /*!< SIC (Bitfield-Mask: 0x01) */ +#define I2C0_CONCLR_STAC_Pos (5UL) /*!< STAC (Bit 5) */ +#define I2C0_CONCLR_STAC_Msk (0x20UL) /*!< STAC (Bitfield-Mask: 0x01) */ +#define I2C0_CONCLR_I2ENC_Pos (6UL) /*!< I2ENC (Bit 6) */ +#define I2C0_CONCLR_I2ENC_Msk (0x40UL) /*!< I2ENC (Bitfield-Mask: 0x01) */ +/* ======================================================== MMCTRL ========================================================= */ +#define I2C0_MMCTRL_MM_ENA_Pos (0UL) /*!< MM_ENA (Bit 0) */ +#define I2C0_MMCTRL_MM_ENA_Msk (0x1UL) /*!< MM_ENA (Bitfield-Mask: 0x01) */ +#define I2C0_MMCTRL_ENA_SCL_Pos (1UL) /*!< ENA_SCL (Bit 1) */ +#define I2C0_MMCTRL_ENA_SCL_Msk (0x2UL) /*!< ENA_SCL (Bitfield-Mask: 0x01) */ +#define I2C0_MMCTRL_MATCH_ALL_Pos (2UL) /*!< MATCH_ALL (Bit 2) */ +#define I2C0_MMCTRL_MATCH_ALL_Msk (0x4UL) /*!< MATCH_ALL (Bitfield-Mask: 0x01) */ +/* ========================================================= ADR1 ========================================================== */ +#define I2C0_ADR1_GC_Pos (0UL) /*!< GC (Bit 0) */ +#define I2C0_ADR1_GC_Msk (0x1UL) /*!< GC (Bitfield-Mask: 0x01) */ +#define I2C0_ADR1_Address_Pos (1UL) /*!< Address (Bit 1) */ +#define I2C0_ADR1_Address_Msk (0xfeUL) /*!< Address (Bitfield-Mask: 0x7f) */ +/* ========================================================= ADR2 ========================================================== */ +#define I2C0_ADR2_GC_Pos (0UL) /*!< GC (Bit 0) */ +#define I2C0_ADR2_GC_Msk (0x1UL) /*!< GC (Bitfield-Mask: 0x01) */ +#define I2C0_ADR2_Address_Pos (1UL) /*!< Address (Bit 1) */ +#define I2C0_ADR2_Address_Msk (0xfeUL) /*!< Address (Bitfield-Mask: 0x7f) */ +/* ========================================================= ADR3 ========================================================== */ +#define I2C0_ADR3_GC_Pos (0UL) /*!< GC (Bit 0) */ +#define I2C0_ADR3_GC_Msk (0x1UL) /*!< GC (Bitfield-Mask: 0x01) */ +#define I2C0_ADR3_Address_Pos (1UL) /*!< Address (Bit 1) */ +#define I2C0_ADR3_Address_Msk (0xfeUL) /*!< Address (Bitfield-Mask: 0x7f) */ +/* ====================================================== DATA_BUFFER ====================================================== */ +#define I2C0_DATA_BUFFER_Data_Pos (0UL) /*!< Data (Bit 0) */ +#define I2C0_DATA_BUFFER_Data_Msk (0xffUL) /*!< Data (Bitfield-Mask: 0xff) */ + + +/* =========================================================================================================================== */ +/* ================ LPC_SPI ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== CR =========================================================== */ +#define SPI_CR_BITENABLE_Pos (2UL) /*!< BITENABLE (Bit 2) */ +#define SPI_CR_BITENABLE_Msk (0x4UL) /*!< BITENABLE (Bitfield-Mask: 0x01) */ +#define SPI_CR_CPHA_Pos (3UL) /*!< CPHA (Bit 3) */ +#define SPI_CR_CPHA_Msk (0x8UL) /*!< CPHA (Bitfield-Mask: 0x01) */ +#define SPI_CR_CPOL_Pos (4UL) /*!< CPOL (Bit 4) */ +#define SPI_CR_CPOL_Msk (0x10UL) /*!< CPOL (Bitfield-Mask: 0x01) */ +#define SPI_CR_MSTR_Pos (5UL) /*!< MSTR (Bit 5) */ +#define SPI_CR_MSTR_Msk (0x20UL) /*!< MSTR (Bitfield-Mask: 0x01) */ +#define SPI_CR_LSBF_Pos (6UL) /*!< LSBF (Bit 6) */ +#define SPI_CR_LSBF_Msk (0x40UL) /*!< LSBF (Bitfield-Mask: 0x01) */ +#define SPI_CR_SPIE_Pos (7UL) /*!< SPIE (Bit 7) */ +#define SPI_CR_SPIE_Msk (0x80UL) /*!< SPIE (Bitfield-Mask: 0x01) */ +#define SPI_CR_BITS_Pos (8UL) /*!< BITS (Bit 8) */ +#define SPI_CR_BITS_Msk (0xf00UL) /*!< BITS (Bitfield-Mask: 0x0f) */ +/* ========================================================== SR =========================================================== */ +#define SPI_SR_ABRT_Pos (3UL) /*!< ABRT (Bit 3) */ +#define SPI_SR_ABRT_Msk (0x8UL) /*!< ABRT (Bitfield-Mask: 0x01) */ +#define SPI_SR_MODF_Pos (4UL) /*!< MODF (Bit 4) */ +#define SPI_SR_MODF_Msk (0x10UL) /*!< MODF (Bitfield-Mask: 0x01) */ +#define SPI_SR_ROVR_Pos (5UL) /*!< ROVR (Bit 5) */ +#define SPI_SR_ROVR_Msk (0x20UL) /*!< ROVR (Bitfield-Mask: 0x01) */ +#define SPI_SR_WCOL_Pos (6UL) /*!< WCOL (Bit 6) */ +#define SPI_SR_WCOL_Msk (0x40UL) /*!< WCOL (Bitfield-Mask: 0x01) */ +#define SPI_SR_SPIF_Pos (7UL) /*!< SPIF (Bit 7) */ +#define SPI_SR_SPIF_Msk (0x80UL) /*!< SPIF (Bitfield-Mask: 0x01) */ +/* ========================================================== DR =========================================================== */ +#define SPI_DR_DATALOW_Pos (0UL) /*!< DATALOW (Bit 0) */ +#define SPI_DR_DATALOW_Msk (0xffUL) /*!< DATALOW (Bitfield-Mask: 0xff) */ +#define SPI_DR_DATAHIGH_Pos (8UL) /*!< DATAHIGH (Bit 8) */ +#define SPI_DR_DATAHIGH_Msk (0xff00UL) /*!< DATAHIGH (Bitfield-Mask: 0xff) */ +/* ========================================================== CCR ========================================================== */ +#define SPI_CCR_COUNTER_Pos (0UL) /*!< COUNTER (Bit 0) */ +#define SPI_CCR_COUNTER_Msk (0xffUL) /*!< COUNTER (Bitfield-Mask: 0xff) */ +/* ========================================================== INT ========================================================== */ +#define SPI_INT_SPIF_Pos (0UL) /*!< SPIF (Bit 0) */ +#define SPI_INT_SPIF_Msk (0x1UL) /*!< SPIF (Bitfield-Mask: 0x01) */ + + +/* =========================================================================================================================== */ +/* ================ LPC_RTC ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== ILR ========================================================== */ +#define RTC_ILR_RTCCIF_Pos (0UL) /*!< RTCCIF (Bit 0) */ +#define RTC_ILR_RTCCIF_Msk (0x1UL) /*!< RTCCIF (Bitfield-Mask: 0x01) */ +#define RTC_ILR_RTCALF_Pos (1UL) /*!< RTCALF (Bit 1) */ +#define RTC_ILR_RTCALF_Msk (0x2UL) /*!< RTCALF (Bitfield-Mask: 0x01) */ +/* ========================================================== CCR ========================================================== */ +#define RTC_CCR_CLKEN_Pos (0UL) /*!< CLKEN (Bit 0) */ +#define RTC_CCR_CLKEN_Msk (0x1UL) /*!< CLKEN (Bitfield-Mask: 0x01) */ +#define RTC_CCR_CTCRST_Pos (1UL) /*!< CTCRST (Bit 1) */ +#define RTC_CCR_CTCRST_Msk (0x2UL) /*!< CTCRST (Bitfield-Mask: 0x01) */ +#define RTC_CCR_CCALEN_Pos (4UL) /*!< CCALEN (Bit 4) */ +#define RTC_CCR_CCALEN_Msk (0x10UL) /*!< CCALEN (Bitfield-Mask: 0x01) */ +/* ========================================================= CIIR ========================================================== */ +#define RTC_CIIR_IMSEC_Pos (0UL) /*!< IMSEC (Bit 0) */ +#define RTC_CIIR_IMSEC_Msk (0x1UL) /*!< IMSEC (Bitfield-Mask: 0x01) */ +#define RTC_CIIR_IMMIN_Pos (1UL) /*!< IMMIN (Bit 1) */ +#define RTC_CIIR_IMMIN_Msk (0x2UL) /*!< IMMIN (Bitfield-Mask: 0x01) */ +#define RTC_CIIR_IMHOUR_Pos (2UL) /*!< IMHOUR (Bit 2) */ +#define RTC_CIIR_IMHOUR_Msk (0x4UL) /*!< IMHOUR (Bitfield-Mask: 0x01) */ +#define RTC_CIIR_IMDOM_Pos (3UL) /*!< IMDOM (Bit 3) */ +#define RTC_CIIR_IMDOM_Msk (0x8UL) /*!< IMDOM (Bitfield-Mask: 0x01) */ +#define RTC_CIIR_IMDOW_Pos (4UL) /*!< IMDOW (Bit 4) */ +#define RTC_CIIR_IMDOW_Msk (0x10UL) /*!< IMDOW (Bitfield-Mask: 0x01) */ +#define RTC_CIIR_IMDOY_Pos (5UL) /*!< IMDOY (Bit 5) */ +#define RTC_CIIR_IMDOY_Msk (0x20UL) /*!< IMDOY (Bitfield-Mask: 0x01) */ +#define RTC_CIIR_IMMON_Pos (6UL) /*!< IMMON (Bit 6) */ +#define RTC_CIIR_IMMON_Msk (0x40UL) /*!< IMMON (Bitfield-Mask: 0x01) */ +#define RTC_CIIR_IMYEAR_Pos (7UL) /*!< IMYEAR (Bit 7) */ +#define RTC_CIIR_IMYEAR_Msk (0x80UL) /*!< IMYEAR (Bitfield-Mask: 0x01) */ +/* ========================================================== AMR ========================================================== */ +#define RTC_AMR_AMRSEC_Pos (0UL) /*!< AMRSEC (Bit 0) */ +#define RTC_AMR_AMRSEC_Msk (0x1UL) /*!< AMRSEC (Bitfield-Mask: 0x01) */ +#define RTC_AMR_AMRMIN_Pos (1UL) /*!< AMRMIN (Bit 1) */ +#define RTC_AMR_AMRMIN_Msk (0x2UL) /*!< AMRMIN (Bitfield-Mask: 0x01) */ +#define RTC_AMR_AMRHOUR_Pos (2UL) /*!< AMRHOUR (Bit 2) */ +#define RTC_AMR_AMRHOUR_Msk (0x4UL) /*!< AMRHOUR (Bitfield-Mask: 0x01) */ +#define RTC_AMR_AMRDOM_Pos (3UL) /*!< AMRDOM (Bit 3) */ +#define RTC_AMR_AMRDOM_Msk (0x8UL) /*!< AMRDOM (Bitfield-Mask: 0x01) */ +#define RTC_AMR_AMRDOW_Pos (4UL) /*!< AMRDOW (Bit 4) */ +#define RTC_AMR_AMRDOW_Msk (0x10UL) /*!< AMRDOW (Bitfield-Mask: 0x01) */ +#define RTC_AMR_AMRDOY_Pos (5UL) /*!< AMRDOY (Bit 5) */ +#define RTC_AMR_AMRDOY_Msk (0x20UL) /*!< AMRDOY (Bitfield-Mask: 0x01) */ +#define RTC_AMR_AMRMON_Pos (6UL) /*!< AMRMON (Bit 6) */ +#define RTC_AMR_AMRMON_Msk (0x40UL) /*!< AMRMON (Bitfield-Mask: 0x01) */ +#define RTC_AMR_AMRYEAR_Pos (7UL) /*!< AMRYEAR (Bit 7) */ +#define RTC_AMR_AMRYEAR_Msk (0x80UL) /*!< AMRYEAR (Bitfield-Mask: 0x01) */ +/* ======================================================== CTIME0 ========================================================= */ +#define RTC_CTIME0_SECONDS_Pos (0UL) /*!< SECONDS (Bit 0) */ +#define RTC_CTIME0_SECONDS_Msk (0x3fUL) /*!< SECONDS (Bitfield-Mask: 0x3f) */ +#define RTC_CTIME0_MINUTES_Pos (8UL) /*!< MINUTES (Bit 8) */ +#define RTC_CTIME0_MINUTES_Msk (0x3f00UL) /*!< MINUTES (Bitfield-Mask: 0x3f) */ +#define RTC_CTIME0_HOURS_Pos (16UL) /*!< HOURS (Bit 16) */ +#define RTC_CTIME0_HOURS_Msk (0x1f0000UL) /*!< HOURS (Bitfield-Mask: 0x1f) */ +#define RTC_CTIME0_DOW_Pos (24UL) /*!< DOW (Bit 24) */ +#define RTC_CTIME0_DOW_Msk (0x7000000UL) /*!< DOW (Bitfield-Mask: 0x07) */ +/* ======================================================== CTIME1 ========================================================= */ +#define RTC_CTIME1_DOM_Pos (0UL) /*!< DOM (Bit 0) */ +#define RTC_CTIME1_DOM_Msk (0x1fUL) /*!< DOM (Bitfield-Mask: 0x1f) */ +#define RTC_CTIME1_MONTH_Pos (8UL) /*!< MONTH (Bit 8) */ +#define RTC_CTIME1_MONTH_Msk (0xf00UL) /*!< MONTH (Bitfield-Mask: 0x0f) */ +#define RTC_CTIME1_YEAR_Pos (16UL) /*!< YEAR (Bit 16) */ +#define RTC_CTIME1_YEAR_Msk (0xfff0000UL) /*!< YEAR (Bitfield-Mask: 0xfff) */ +/* ======================================================== CTIME2 ========================================================= */ +#define RTC_CTIME2_DOY_Pos (0UL) /*!< DOY (Bit 0) */ +#define RTC_CTIME2_DOY_Msk (0xfffUL) /*!< DOY (Bitfield-Mask: 0xfff) */ +/* ========================================================== SEC ========================================================== */ +#define RTC_SEC_SECONDS_Pos (0UL) /*!< SECONDS (Bit 0) */ +#define RTC_SEC_SECONDS_Msk (0x3fUL) /*!< SECONDS (Bitfield-Mask: 0x3f) */ +/* ========================================================== MIN ========================================================== */ +#define RTC_MIN_MINUTES_Pos (0UL) /*!< MINUTES (Bit 0) */ +#define RTC_MIN_MINUTES_Msk (0x3fUL) /*!< MINUTES (Bitfield-Mask: 0x3f) */ +/* ========================================================== HRS ========================================================== */ +#define RTC_HRS_HOURS_Pos (0UL) /*!< HOURS (Bit 0) */ +#define RTC_HRS_HOURS_Msk (0x1fUL) /*!< HOURS (Bitfield-Mask: 0x1f) */ +/* ========================================================== DOM ========================================================== */ +#define RTC_DOM_DOM_Pos (0UL) /*!< DOM (Bit 0) */ +#define RTC_DOM_DOM_Msk (0x1fUL) /*!< DOM (Bitfield-Mask: 0x1f) */ +/* ========================================================== DOW ========================================================== */ +#define RTC_DOW_DOW_Pos (0UL) /*!< DOW (Bit 0) */ +#define RTC_DOW_DOW_Msk (0x7UL) /*!< DOW (Bitfield-Mask: 0x07) */ +/* ========================================================== DOY ========================================================== */ +#define RTC_DOY_DOY_Pos (0UL) /*!< DOY (Bit 0) */ +#define RTC_DOY_DOY_Msk (0x1ffUL) /*!< DOY (Bitfield-Mask: 0x1ff) */ +/* ========================================================= MONTH ========================================================= */ +#define RTC_MONTH_MONTH_Pos (0UL) /*!< MONTH (Bit 0) */ +#define RTC_MONTH_MONTH_Msk (0xfUL) /*!< MONTH (Bitfield-Mask: 0x0f) */ +/* ========================================================= YEAR ========================================================== */ +#define RTC_YEAR_YEAR_Pos (0UL) /*!< YEAR (Bit 0) */ +#define RTC_YEAR_YEAR_Msk (0xfffUL) /*!< YEAR (Bitfield-Mask: 0xfff) */ +/* ====================================================== CALIBRATION ====================================================== */ +#define RTC_CALIBRATION_CALVAL_Pos (0UL) /*!< CALVAL (Bit 0) */ +#define RTC_CALIBRATION_CALVAL_Msk (0x1ffffUL) /*!< CALVAL (Bitfield-Mask: 0x1ffff) */ +#define RTC_CALIBRATION_CALDIR_Pos (17UL) /*!< CALDIR (Bit 17) */ +#define RTC_CALIBRATION_CALDIR_Msk (0x20000UL) /*!< CALDIR (Bitfield-Mask: 0x01) */ +/* ======================================================== GPREG0 ========================================================= */ +#define RTC_GPREG0_GP_Pos (0UL) /*!< GP (Bit 0) */ +#define RTC_GPREG0_GP_Msk (0xffffffffUL) /*!< GP (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== GPREG1 ========================================================= */ +#define RTC_GPREG1_GP_Pos (0UL) /*!< GP (Bit 0) */ +#define RTC_GPREG1_GP_Msk (0xffffffffUL) /*!< GP (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== GPREG2 ========================================================= */ +#define RTC_GPREG2_GP_Pos (0UL) /*!< GP (Bit 0) */ +#define RTC_GPREG2_GP_Msk (0xffffffffUL) /*!< GP (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== GPREG3 ========================================================= */ +#define RTC_GPREG3_GP_Pos (0UL) /*!< GP (Bit 0) */ +#define RTC_GPREG3_GP_Msk (0xffffffffUL) /*!< GP (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== GPREG4 ========================================================= */ +#define RTC_GPREG4_GP_Pos (0UL) /*!< GP (Bit 0) */ +#define RTC_GPREG4_GP_Msk (0xffffffffUL) /*!< GP (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== RTC_AUX ======================================================== */ +#define RTC_RTC_AUX_RTC_OSCF_Pos (4UL) /*!< RTC_OSCF (Bit 4) */ +#define RTC_RTC_AUX_RTC_OSCF_Msk (0x10UL) /*!< RTC_OSCF (Bitfield-Mask: 0x01) */ +#define RTC_RTC_AUX_RTC_PDOUT_Pos (6UL) /*!< RTC_PDOUT (Bit 6) */ +#define RTC_RTC_AUX_RTC_PDOUT_Msk (0x40UL) /*!< RTC_PDOUT (Bitfield-Mask: 0x01) */ +/* ======================================================= RTC_AUXEN ======================================================= */ +#define RTC_RTC_AUXEN_RTC_OSCFEN_Pos (4UL) /*!< RTC_OSCFEN (Bit 4) */ +#define RTC_RTC_AUXEN_RTC_OSCFEN_Msk (0x10UL) /*!< RTC_OSCFEN (Bitfield-Mask: 0x01) */ +/* ========================================================= ASEC ========================================================== */ +#define RTC_ASEC_SECONDS_Pos (0UL) /*!< SECONDS (Bit 0) */ +#define RTC_ASEC_SECONDS_Msk (0x3fUL) /*!< SECONDS (Bitfield-Mask: 0x3f) */ +/* ========================================================= AMIN ========================================================== */ +#define RTC_AMIN_MINUTES_Pos (0UL) /*!< MINUTES (Bit 0) */ +#define RTC_AMIN_MINUTES_Msk (0x3fUL) /*!< MINUTES (Bitfield-Mask: 0x3f) */ +/* ========================================================= AHRS ========================================================== */ +#define RTC_AHRS_HOURS_Pos (0UL) /*!< HOURS (Bit 0) */ +#define RTC_AHRS_HOURS_Msk (0x1fUL) /*!< HOURS (Bitfield-Mask: 0x1f) */ +/* ========================================================= ADOM ========================================================== */ +#define RTC_ADOM_DOM_Pos (0UL) /*!< DOM (Bit 0) */ +#define RTC_ADOM_DOM_Msk (0x1fUL) /*!< DOM (Bitfield-Mask: 0x1f) */ +/* ========================================================= ADOW ========================================================== */ +#define RTC_ADOW_DOW_Pos (0UL) /*!< DOW (Bit 0) */ +#define RTC_ADOW_DOW_Msk (0x7UL) /*!< DOW (Bitfield-Mask: 0x07) */ +/* ========================================================= ADOY ========================================================== */ +#define RTC_ADOY_DOY_Pos (0UL) /*!< DOY (Bit 0) */ +#define RTC_ADOY_DOY_Msk (0x1ffUL) /*!< DOY (Bitfield-Mask: 0x1ff) */ +/* ========================================================= AMON ========================================================== */ +#define RTC_AMON_MONTH_Pos (0UL) /*!< MONTH (Bit 0) */ +#define RTC_AMON_MONTH_Msk (0xfUL) /*!< MONTH (Bitfield-Mask: 0x0f) */ +/* ========================================================= AYRS ========================================================== */ +#define RTC_AYRS_YEAR_Pos (0UL) /*!< YEAR (Bit 0) */ +#define RTC_AYRS_YEAR_Msk (0xfffUL) /*!< YEAR (Bitfield-Mask: 0xfff) */ + + +/* =========================================================================================================================== */ +/* ================ LPC_GPIOINT ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== STATUS ========================================================= */ +#define GPIOINT_STATUS_P0INT_Pos (0UL) /*!< P0INT (Bit 0) */ +#define GPIOINT_STATUS_P0INT_Msk (0x1UL) /*!< P0INT (Bitfield-Mask: 0x01) */ +#define GPIOINT_STATUS_P2INT_Pos (2UL) /*!< P2INT (Bit 2) */ +#define GPIOINT_STATUS_P2INT_Msk (0x4UL) /*!< P2INT (Bitfield-Mask: 0x01) */ +/* ======================================================== STATR0 ========================================================= */ +#define GPIOINT_STATR0_P0_0REI_Pos (0UL) /*!< P0_0REI (Bit 0) */ +#define GPIOINT_STATR0_P0_0REI_Msk (0x1UL) /*!< P0_0REI (Bitfield-Mask: 0x01) */ +#define GPIOINT_STATR0_P0_1REI_Pos (1UL) /*!< P0_1REI (Bit 1) */ +#define GPIOINT_STATR0_P0_1REI_Msk (0x2UL) /*!< P0_1REI (Bitfield-Mask: 0x01) */ +#define GPIOINT_STATR0_P0_2REI_Pos (2UL) /*!< P0_2REI (Bit 2) */ +#define GPIOINT_STATR0_P0_2REI_Msk (0x4UL) /*!< P0_2REI (Bitfield-Mask: 0x01) */ +#define GPIOINT_STATR0_P0_3REI_Pos (3UL) /*!< P0_3REI (Bit 3) */ +#define GPIOINT_STATR0_P0_3REI_Msk (0x8UL) /*!< P0_3REI (Bitfield-Mask: 0x01) */ +#define GPIOINT_STATR0_P0_4REI_Pos (4UL) /*!< P0_4REI (Bit 4) */ +#define GPIOINT_STATR0_P0_4REI_Msk (0x10UL) /*!< P0_4REI (Bitfield-Mask: 0x01) */ +#define GPIOINT_STATR0_P0_5REI_Pos (5UL) /*!< P0_5REI (Bit 5) */ +#define GPIOINT_STATR0_P0_5REI_Msk (0x20UL) /*!< P0_5REI (Bitfield-Mask: 0x01) */ +#define GPIOINT_STATR0_P0_6REI_Pos (6UL) /*!< P0_6REI (Bit 6) */ +#define GPIOINT_STATR0_P0_6REI_Msk (0x40UL) /*!< P0_6REI (Bitfield-Mask: 0x01) */ +#define GPIOINT_STATR0_P0_7REI_Pos (7UL) /*!< P0_7REI (Bit 7) */ +#define GPIOINT_STATR0_P0_7REI_Msk (0x80UL) /*!< P0_7REI (Bitfield-Mask: 0x01) */ +#define GPIOINT_STATR0_P0_8REI_Pos (8UL) /*!< P0_8REI (Bit 8) */ +#define GPIOINT_STATR0_P0_8REI_Msk (0x100UL) /*!< P0_8REI (Bitfield-Mask: 0x01) */ +#define GPIOINT_STATR0_P0_9REI_Pos (9UL) /*!< P0_9REI (Bit 9) */ +#define GPIOINT_STATR0_P0_9REI_Msk (0x200UL) /*!< P0_9REI (Bitfield-Mask: 0x01) */ +#define GPIOINT_STATR0_P0_10REI_Pos (10UL) /*!< P0_10REI (Bit 10) */ +#define GPIOINT_STATR0_P0_10REI_Msk (0x400UL) /*!< P0_10REI (Bitfield-Mask: 0x01) */ +#define GPIOINT_STATR0_P0_11REI_Pos (11UL) /*!< P0_11REI (Bit 11) */ +#define GPIOINT_STATR0_P0_11REI_Msk (0x800UL) /*!< P0_11REI (Bitfield-Mask: 0x01) */ +#define GPIOINT_STATR0_P0_12REI_Pos (12UL) /*!< P0_12REI (Bit 12) */ +#define GPIOINT_STATR0_P0_12REI_Msk (0x1000UL) /*!< P0_12REI (Bitfield-Mask: 0x01) */ +#define GPIOINT_STATR0_P0_13REI_Pos (13UL) /*!< P0_13REI (Bit 13) */ +#define GPIOINT_STATR0_P0_13REI_Msk (0x2000UL) /*!< P0_13REI (Bitfield-Mask: 0x01) */ +#define GPIOINT_STATR0_P0_14REI_Pos (14UL) /*!< P0_14REI (Bit 14) */ +#define GPIOINT_STATR0_P0_14REI_Msk (0x4000UL) /*!< P0_14REI (Bitfield-Mask: 0x01) */ +#define GPIOINT_STATR0_P0_15REI_Pos (15UL) /*!< P0_15REI (Bit 15) */ +#define GPIOINT_STATR0_P0_15REI_Msk (0x8000UL) /*!< P0_15REI (Bitfield-Mask: 0x01) */ +#define GPIOINT_STATR0_P0_16REI_Pos (16UL) /*!< P0_16REI (Bit 16) */ +#define GPIOINT_STATR0_P0_16REI_Msk (0x10000UL) /*!< P0_16REI (Bitfield-Mask: 0x01) */ +#define GPIOINT_STATR0_P0_17REI_Pos (17UL) /*!< P0_17REI (Bit 17) */ +#define GPIOINT_STATR0_P0_17REI_Msk (0x20000UL) /*!< P0_17REI (Bitfield-Mask: 0x01) */ +#define GPIOINT_STATR0_P0_18REI_Pos (18UL) /*!< P0_18REI (Bit 18) */ +#define GPIOINT_STATR0_P0_18REI_Msk (0x40000UL) /*!< P0_18REI (Bitfield-Mask: 0x01) */ +#define GPIOINT_STATR0_P0_19REI_Pos (19UL) /*!< P0_19REI (Bit 19) */ +#define GPIOINT_STATR0_P0_19REI_Msk (0x80000UL) /*!< P0_19REI (Bitfield-Mask: 0x01) */ +#define GPIOINT_STATR0_P0_20REI_Pos (20UL) /*!< P0_20REI (Bit 20) */ +#define GPIOINT_STATR0_P0_20REI_Msk (0x100000UL) /*!< P0_20REI (Bitfield-Mask: 0x01) */ +#define GPIOINT_STATR0_P0_21REI_Pos (21UL) /*!< P0_21REI (Bit 21) */ +#define GPIOINT_STATR0_P0_21REI_Msk (0x200000UL) /*!< P0_21REI (Bitfield-Mask: 0x01) */ +#define GPIOINT_STATR0_P0_22REI_Pos (22UL) /*!< P0_22REI (Bit 22) */ +#define GPIOINT_STATR0_P0_22REI_Msk (0x400000UL) /*!< P0_22REI (Bitfield-Mask: 0x01) */ +#define GPIOINT_STATR0_P0_23REI_Pos (23UL) /*!< P0_23REI (Bit 23) */ +#define GPIOINT_STATR0_P0_23REI_Msk (0x800000UL) /*!< P0_23REI (Bitfield-Mask: 0x01) */ +#define GPIOINT_STATR0_P0_24REI_Pos (24UL) /*!< P0_24REI (Bit 24) */ +#define GPIOINT_STATR0_P0_24REI_Msk (0x1000000UL) /*!< P0_24REI (Bitfield-Mask: 0x01) */ +#define GPIOINT_STATR0_P0_25REI_Pos (25UL) /*!< P0_25REI (Bit 25) */ +#define GPIOINT_STATR0_P0_25REI_Msk (0x2000000UL) /*!< P0_25REI (Bitfield-Mask: 0x01) */ +#define GPIOINT_STATR0_P0_26REI_Pos (26UL) /*!< P0_26REI (Bit 26) */ +#define GPIOINT_STATR0_P0_26REI_Msk (0x4000000UL) /*!< P0_26REI (Bitfield-Mask: 0x01) */ +#define GPIOINT_STATR0_P0_27REI_Pos (27UL) /*!< P0_27REI (Bit 27) */ +#define GPIOINT_STATR0_P0_27REI_Msk (0x8000000UL) /*!< P0_27REI (Bitfield-Mask: 0x01) */ +#define GPIOINT_STATR0_P0_28REI_Pos (28UL) /*!< P0_28REI (Bit 28) */ +#define GPIOINT_STATR0_P0_28REI_Msk (0x10000000UL) /*!< P0_28REI (Bitfield-Mask: 0x01) */ +#define GPIOINT_STATR0_P0_29REI_Pos (29UL) /*!< P0_29REI (Bit 29) */ +#define GPIOINT_STATR0_P0_29REI_Msk (0x20000000UL) /*!< P0_29REI (Bitfield-Mask: 0x01) */ +#define GPIOINT_STATR0_P0_30REI_Pos (30UL) /*!< P0_30REI (Bit 30) */ +#define GPIOINT_STATR0_P0_30REI_Msk (0x40000000UL) /*!< P0_30REI (Bitfield-Mask: 0x01) */ +/* ======================================================== STATF0 ========================================================= */ +#define GPIOINT_STATF0_P0_0FEI_Pos (0UL) /*!< P0_0FEI (Bit 0) */ +#define GPIOINT_STATF0_P0_0FEI_Msk (0x1UL) /*!< P0_0FEI (Bitfield-Mask: 0x01) */ +#define GPIOINT_STATF0_P0_1FEI_Pos (1UL) /*!< P0_1FEI (Bit 1) */ +#define GPIOINT_STATF0_P0_1FEI_Msk (0x2UL) /*!< P0_1FEI (Bitfield-Mask: 0x01) */ +#define GPIOINT_STATF0_P0_2FEI_Pos (2UL) /*!< P0_2FEI (Bit 2) */ +#define GPIOINT_STATF0_P0_2FEI_Msk (0x4UL) /*!< P0_2FEI (Bitfield-Mask: 0x01) */ +#define GPIOINT_STATF0_P0_3FEI_Pos (3UL) /*!< P0_3FEI (Bit 3) */ +#define GPIOINT_STATF0_P0_3FEI_Msk (0x8UL) /*!< P0_3FEI (Bitfield-Mask: 0x01) */ +#define GPIOINT_STATF0_P0_4FEI_Pos (4UL) /*!< P0_4FEI (Bit 4) */ +#define GPIOINT_STATF0_P0_4FEI_Msk (0x10UL) /*!< P0_4FEI (Bitfield-Mask: 0x01) */ +#define GPIOINT_STATF0_P0_5FEI_Pos (5UL) /*!< P0_5FEI (Bit 5) */ +#define GPIOINT_STATF0_P0_5FEI_Msk (0x20UL) /*!< P0_5FEI (Bitfield-Mask: 0x01) */ +#define GPIOINT_STATF0_P0_6FEI_Pos (6UL) /*!< P0_6FEI (Bit 6) */ +#define GPIOINT_STATF0_P0_6FEI_Msk (0x40UL) /*!< P0_6FEI (Bitfield-Mask: 0x01) */ +#define GPIOINT_STATF0_P0_7FEI_Pos (7UL) /*!< P0_7FEI (Bit 7) */ +#define GPIOINT_STATF0_P0_7FEI_Msk (0x80UL) /*!< P0_7FEI (Bitfield-Mask: 0x01) */ +#define GPIOINT_STATF0_P0_8FEI_Pos (8UL) /*!< P0_8FEI (Bit 8) */ +#define GPIOINT_STATF0_P0_8FEI_Msk (0x100UL) /*!< P0_8FEI (Bitfield-Mask: 0x01) */ +#define GPIOINT_STATF0_P0_9FEI_Pos (9UL) /*!< P0_9FEI (Bit 9) */ +#define GPIOINT_STATF0_P0_9FEI_Msk (0x200UL) /*!< P0_9FEI (Bitfield-Mask: 0x01) */ +#define GPIOINT_STATF0_P0_10FEI_Pos (10UL) /*!< P0_10FEI (Bit 10) */ +#define GPIOINT_STATF0_P0_10FEI_Msk (0x400UL) /*!< P0_10FEI (Bitfield-Mask: 0x01) */ +#define GPIOINT_STATF0_P0_11FEI_Pos (11UL) /*!< P0_11FEI (Bit 11) */ +#define GPIOINT_STATF0_P0_11FEI_Msk (0x800UL) /*!< P0_11FEI (Bitfield-Mask: 0x01) */ +#define GPIOINT_STATF0_P0_12FEI_Pos (12UL) /*!< P0_12FEI (Bit 12) */ +#define GPIOINT_STATF0_P0_12FEI_Msk (0x1000UL) /*!< P0_12FEI (Bitfield-Mask: 0x01) */ +#define GPIOINT_STATF0_P0_13FEI_Pos (13UL) /*!< P0_13FEI (Bit 13) */ +#define GPIOINT_STATF0_P0_13FEI_Msk (0x2000UL) /*!< P0_13FEI (Bitfield-Mask: 0x01) */ +#define GPIOINT_STATF0_P0_14FEI_Pos (14UL) /*!< P0_14FEI (Bit 14) */ +#define GPIOINT_STATF0_P0_14FEI_Msk (0x4000UL) /*!< P0_14FEI (Bitfield-Mask: 0x01) */ +#define GPIOINT_STATF0_P0_15FEI_Pos (15UL) /*!< P0_15FEI (Bit 15) */ +#define GPIOINT_STATF0_P0_15FEI_Msk (0x8000UL) /*!< P0_15FEI (Bitfield-Mask: 0x01) */ +#define GPIOINT_STATF0_P0_16FEI_Pos (16UL) /*!< P0_16FEI (Bit 16) */ +#define GPIOINT_STATF0_P0_16FEI_Msk (0x10000UL) /*!< P0_16FEI (Bitfield-Mask: 0x01) */ +#define GPIOINT_STATF0_P0_17FEI_Pos (17UL) /*!< P0_17FEI (Bit 17) */ +#define GPIOINT_STATF0_P0_17FEI_Msk (0x20000UL) /*!< P0_17FEI (Bitfield-Mask: 0x01) */ +#define GPIOINT_STATF0_P0_18FEI_Pos (18UL) /*!< P0_18FEI (Bit 18) */ +#define GPIOINT_STATF0_P0_18FEI_Msk (0x40000UL) /*!< P0_18FEI (Bitfield-Mask: 0x01) */ +#define GPIOINT_STATF0_P0_19FEI_Pos (19UL) /*!< P0_19FEI (Bit 19) */ +#define GPIOINT_STATF0_P0_19FEI_Msk (0x80000UL) /*!< P0_19FEI (Bitfield-Mask: 0x01) */ +#define GPIOINT_STATF0_P0_20FEI_Pos (20UL) /*!< P0_20FEI (Bit 20) */ +#define GPIOINT_STATF0_P0_20FEI_Msk (0x100000UL) /*!< P0_20FEI (Bitfield-Mask: 0x01) */ +#define GPIOINT_STATF0_P0_21FEI_Pos (21UL) /*!< P0_21FEI (Bit 21) */ +#define GPIOINT_STATF0_P0_21FEI_Msk (0x200000UL) /*!< P0_21FEI (Bitfield-Mask: 0x01) */ +#define GPIOINT_STATF0_P0_22FEI_Pos (22UL) /*!< P0_22FEI (Bit 22) */ +#define GPIOINT_STATF0_P0_22FEI_Msk (0x400000UL) /*!< P0_22FEI (Bitfield-Mask: 0x01) */ +#define GPIOINT_STATF0_P0_23FEI_Pos (23UL) /*!< P0_23FEI (Bit 23) */ +#define GPIOINT_STATF0_P0_23FEI_Msk (0x800000UL) /*!< P0_23FEI (Bitfield-Mask: 0x01) */ +#define GPIOINT_STATF0_P0_24FEI_Pos (24UL) /*!< P0_24FEI (Bit 24) */ +#define GPIOINT_STATF0_P0_24FEI_Msk (0x1000000UL) /*!< P0_24FEI (Bitfield-Mask: 0x01) */ +#define GPIOINT_STATF0_P0_25FEI_Pos (25UL) /*!< P0_25FEI (Bit 25) */ +#define GPIOINT_STATF0_P0_25FEI_Msk (0x2000000UL) /*!< P0_25FEI (Bitfield-Mask: 0x01) */ +#define GPIOINT_STATF0_P0_26FEI_Pos (26UL) /*!< P0_26FEI (Bit 26) */ +#define GPIOINT_STATF0_P0_26FEI_Msk (0x4000000UL) /*!< P0_26FEI (Bitfield-Mask: 0x01) */ +#define GPIOINT_STATF0_P0_27FEI_Pos (27UL) /*!< P0_27FEI (Bit 27) */ +#define GPIOINT_STATF0_P0_27FEI_Msk (0x8000000UL) /*!< P0_27FEI (Bitfield-Mask: 0x01) */ +#define GPIOINT_STATF0_P0_28FEI_Pos (28UL) /*!< P0_28FEI (Bit 28) */ +#define GPIOINT_STATF0_P0_28FEI_Msk (0x10000000UL) /*!< P0_28FEI (Bitfield-Mask: 0x01) */ +#define GPIOINT_STATF0_P0_29FEI_Pos (29UL) /*!< P0_29FEI (Bit 29) */ +#define GPIOINT_STATF0_P0_29FEI_Msk (0x20000000UL) /*!< P0_29FEI (Bitfield-Mask: 0x01) */ +#define GPIOINT_STATF0_P0_30FEI_Pos (30UL) /*!< P0_30FEI (Bit 30) */ +#define GPIOINT_STATF0_P0_30FEI_Msk (0x40000000UL) /*!< P0_30FEI (Bitfield-Mask: 0x01) */ +/* ========================================================= CLR0 ========================================================== */ +#define GPIOINT_CLR0_P0_0CI_Pos (0UL) /*!< P0_0CI (Bit 0) */ +#define GPIOINT_CLR0_P0_0CI_Msk (0x1UL) /*!< P0_0CI (Bitfield-Mask: 0x01) */ +#define GPIOINT_CLR0_P0_1CI_Pos (1UL) /*!< P0_1CI (Bit 1) */ +#define GPIOINT_CLR0_P0_1CI_Msk (0x2UL) /*!< P0_1CI (Bitfield-Mask: 0x01) */ +#define GPIOINT_CLR0_P0_2CI_Pos (2UL) /*!< P0_2CI (Bit 2) */ +#define GPIOINT_CLR0_P0_2CI_Msk (0x4UL) /*!< P0_2CI (Bitfield-Mask: 0x01) */ +#define GPIOINT_CLR0_P0_3CI_Pos (3UL) /*!< P0_3CI (Bit 3) */ +#define GPIOINT_CLR0_P0_3CI_Msk (0x8UL) /*!< P0_3CI (Bitfield-Mask: 0x01) */ +#define GPIOINT_CLR0_P0_4CI_Pos (4UL) /*!< P0_4CI (Bit 4) */ +#define GPIOINT_CLR0_P0_4CI_Msk (0x10UL) /*!< P0_4CI (Bitfield-Mask: 0x01) */ +#define GPIOINT_CLR0_P0_5CI_Pos (5UL) /*!< P0_5CI (Bit 5) */ +#define GPIOINT_CLR0_P0_5CI_Msk (0x20UL) /*!< P0_5CI (Bitfield-Mask: 0x01) */ +#define GPIOINT_CLR0_P0_6CI_Pos (6UL) /*!< P0_6CI (Bit 6) */ +#define GPIOINT_CLR0_P0_6CI_Msk (0x40UL) /*!< P0_6CI (Bitfield-Mask: 0x01) */ +#define GPIOINT_CLR0_P0_7CI_Pos (7UL) /*!< P0_7CI (Bit 7) */ +#define GPIOINT_CLR0_P0_7CI_Msk (0x80UL) /*!< P0_7CI (Bitfield-Mask: 0x01) */ +#define GPIOINT_CLR0_P0_8CI_Pos (8UL) /*!< P0_8CI (Bit 8) */ +#define GPIOINT_CLR0_P0_8CI_Msk (0x100UL) /*!< P0_8CI (Bitfield-Mask: 0x01) */ +#define GPIOINT_CLR0_P0_9CI_Pos (9UL) /*!< P0_9CI (Bit 9) */ +#define GPIOINT_CLR0_P0_9CI_Msk (0x200UL) /*!< P0_9CI (Bitfield-Mask: 0x01) */ +#define GPIOINT_CLR0_P0_10CI_Pos (10UL) /*!< P0_10CI (Bit 10) */ +#define GPIOINT_CLR0_P0_10CI_Msk (0x400UL) /*!< P0_10CI (Bitfield-Mask: 0x01) */ +#define GPIOINT_CLR0_P0_11CI_Pos (11UL) /*!< P0_11CI (Bit 11) */ +#define GPIOINT_CLR0_P0_11CI_Msk (0x800UL) /*!< P0_11CI (Bitfield-Mask: 0x01) */ +#define GPIOINT_CLR0_P0_12CI_Pos (12UL) /*!< P0_12CI (Bit 12) */ +#define GPIOINT_CLR0_P0_12CI_Msk (0x1000UL) /*!< P0_12CI (Bitfield-Mask: 0x01) */ +#define GPIOINT_CLR0_P0_13CI_Pos (13UL) /*!< P0_13CI (Bit 13) */ +#define GPIOINT_CLR0_P0_13CI_Msk (0x2000UL) /*!< P0_13CI (Bitfield-Mask: 0x01) */ +#define GPIOINT_CLR0_P0_14CI_Pos (14UL) /*!< P0_14CI (Bit 14) */ +#define GPIOINT_CLR0_P0_14CI_Msk (0x4000UL) /*!< P0_14CI (Bitfield-Mask: 0x01) */ +#define GPIOINT_CLR0_P0_15CI_Pos (15UL) /*!< P0_15CI (Bit 15) */ +#define GPIOINT_CLR0_P0_15CI_Msk (0x8000UL) /*!< P0_15CI (Bitfield-Mask: 0x01) */ +#define GPIOINT_CLR0_P0_16CI_Pos (16UL) /*!< P0_16CI (Bit 16) */ +#define GPIOINT_CLR0_P0_16CI_Msk (0x10000UL) /*!< P0_16CI (Bitfield-Mask: 0x01) */ +#define GPIOINT_CLR0_P0_17CI_Pos (17UL) /*!< P0_17CI (Bit 17) */ +#define GPIOINT_CLR0_P0_17CI_Msk (0x20000UL) /*!< P0_17CI (Bitfield-Mask: 0x01) */ +#define GPIOINT_CLR0_P0_18CI_Pos (18UL) /*!< P0_18CI (Bit 18) */ +#define GPIOINT_CLR0_P0_18CI_Msk (0x40000UL) /*!< P0_18CI (Bitfield-Mask: 0x01) */ +#define GPIOINT_CLR0_P0_19CI_Pos (19UL) /*!< P0_19CI (Bit 19) */ +#define GPIOINT_CLR0_P0_19CI_Msk (0x80000UL) /*!< P0_19CI (Bitfield-Mask: 0x01) */ +#define GPIOINT_CLR0_P0_20CI_Pos (20UL) /*!< P0_20CI (Bit 20) */ +#define GPIOINT_CLR0_P0_20CI_Msk (0x100000UL) /*!< P0_20CI (Bitfield-Mask: 0x01) */ +#define GPIOINT_CLR0_P0_21CI_Pos (21UL) /*!< P0_21CI (Bit 21) */ +#define GPIOINT_CLR0_P0_21CI_Msk (0x200000UL) /*!< P0_21CI (Bitfield-Mask: 0x01) */ +#define GPIOINT_CLR0_P0_22CI_Pos (22UL) /*!< P0_22CI (Bit 22) */ +#define GPIOINT_CLR0_P0_22CI_Msk (0x400000UL) /*!< P0_22CI (Bitfield-Mask: 0x01) */ +#define GPIOINT_CLR0_P0_23CI_Pos (23UL) /*!< P0_23CI (Bit 23) */ +#define GPIOINT_CLR0_P0_23CI_Msk (0x800000UL) /*!< P0_23CI (Bitfield-Mask: 0x01) */ +#define GPIOINT_CLR0_P0_24CI_Pos (24UL) /*!< P0_24CI (Bit 24) */ +#define GPIOINT_CLR0_P0_24CI_Msk (0x1000000UL) /*!< P0_24CI (Bitfield-Mask: 0x01) */ +#define GPIOINT_CLR0_P0_25CI_Pos (25UL) /*!< P0_25CI (Bit 25) */ +#define GPIOINT_CLR0_P0_25CI_Msk (0x2000000UL) /*!< P0_25CI (Bitfield-Mask: 0x01) */ +#define GPIOINT_CLR0_P0_26CI_Pos (26UL) /*!< P0_26CI (Bit 26) */ +#define GPIOINT_CLR0_P0_26CI_Msk (0x4000000UL) /*!< P0_26CI (Bitfield-Mask: 0x01) */ +#define GPIOINT_CLR0_P0_27CI_Pos (27UL) /*!< P0_27CI (Bit 27) */ +#define GPIOINT_CLR0_P0_27CI_Msk (0x8000000UL) /*!< P0_27CI (Bitfield-Mask: 0x01) */ +#define GPIOINT_CLR0_P0_28CI_Pos (28UL) /*!< P0_28CI (Bit 28) */ +#define GPIOINT_CLR0_P0_28CI_Msk (0x10000000UL) /*!< P0_28CI (Bitfield-Mask: 0x01) */ +#define GPIOINT_CLR0_P0_29CI_Pos (29UL) /*!< P0_29CI (Bit 29) */ +#define GPIOINT_CLR0_P0_29CI_Msk (0x20000000UL) /*!< P0_29CI (Bitfield-Mask: 0x01) */ +#define GPIOINT_CLR0_P0_30CI_Pos (30UL) /*!< P0_30CI (Bit 30) */ +#define GPIOINT_CLR0_P0_30CI_Msk (0x40000000UL) /*!< P0_30CI (Bitfield-Mask: 0x01) */ +/* ========================================================= ENR0 ========================================================== */ +#define GPIOINT_ENR0_P0_0ER_Pos (0UL) /*!< P0_0ER (Bit 0) */ +#define GPIOINT_ENR0_P0_0ER_Msk (0x1UL) /*!< P0_0ER (Bitfield-Mask: 0x01) */ +#define GPIOINT_ENR0_P0_1ER_Pos (1UL) /*!< P0_1ER (Bit 1) */ +#define GPIOINT_ENR0_P0_1ER_Msk (0x2UL) /*!< P0_1ER (Bitfield-Mask: 0x01) */ +#define GPIOINT_ENR0_P0_2ER_Pos (2UL) /*!< P0_2ER (Bit 2) */ +#define GPIOINT_ENR0_P0_2ER_Msk (0x4UL) /*!< P0_2ER (Bitfield-Mask: 0x01) */ +#define GPIOINT_ENR0_P0_3ER_Pos (3UL) /*!< P0_3ER (Bit 3) */ +#define GPIOINT_ENR0_P0_3ER_Msk (0x8UL) /*!< P0_3ER (Bitfield-Mask: 0x01) */ +#define GPIOINT_ENR0_P0_4ER_Pos (4UL) /*!< P0_4ER (Bit 4) */ +#define GPIOINT_ENR0_P0_4ER_Msk (0x10UL) /*!< P0_4ER (Bitfield-Mask: 0x01) */ +#define GPIOINT_ENR0_P0_5ER_Pos (5UL) /*!< P0_5ER (Bit 5) */ +#define GPIOINT_ENR0_P0_5ER_Msk (0x20UL) /*!< P0_5ER (Bitfield-Mask: 0x01) */ +#define GPIOINT_ENR0_P0_6ER_Pos (6UL) /*!< P0_6ER (Bit 6) */ +#define GPIOINT_ENR0_P0_6ER_Msk (0x40UL) /*!< P0_6ER (Bitfield-Mask: 0x01) */ +#define GPIOINT_ENR0_P0_7ER_Pos (7UL) /*!< P0_7ER (Bit 7) */ +#define GPIOINT_ENR0_P0_7ER_Msk (0x80UL) /*!< P0_7ER (Bitfield-Mask: 0x01) */ +#define GPIOINT_ENR0_P0_8ER_Pos (8UL) /*!< P0_8ER (Bit 8) */ +#define GPIOINT_ENR0_P0_8ER_Msk (0x100UL) /*!< P0_8ER (Bitfield-Mask: 0x01) */ +#define GPIOINT_ENR0_P0_9ER_Pos (9UL) /*!< P0_9ER (Bit 9) */ +#define GPIOINT_ENR0_P0_9ER_Msk (0x200UL) /*!< P0_9ER (Bitfield-Mask: 0x01) */ +#define GPIOINT_ENR0_P0_10ER_Pos (10UL) /*!< P0_10ER (Bit 10) */ +#define GPIOINT_ENR0_P0_10ER_Msk (0x400UL) /*!< P0_10ER (Bitfield-Mask: 0x01) */ +#define GPIOINT_ENR0_P0_11ER_Pos (11UL) /*!< P0_11ER (Bit 11) */ +#define GPIOINT_ENR0_P0_11ER_Msk (0x800UL) /*!< P0_11ER (Bitfield-Mask: 0x01) */ +#define GPIOINT_ENR0_P0_12ER_Pos (12UL) /*!< P0_12ER (Bit 12) */ +#define GPIOINT_ENR0_P0_12ER_Msk (0x1000UL) /*!< P0_12ER (Bitfield-Mask: 0x01) */ +#define GPIOINT_ENR0_P0_13ER_Pos (13UL) /*!< P0_13ER (Bit 13) */ +#define GPIOINT_ENR0_P0_13ER_Msk (0x2000UL) /*!< P0_13ER (Bitfield-Mask: 0x01) */ +#define GPIOINT_ENR0_P0_14ER_Pos (14UL) /*!< P0_14ER (Bit 14) */ +#define GPIOINT_ENR0_P0_14ER_Msk (0x4000UL) /*!< P0_14ER (Bitfield-Mask: 0x01) */ +#define GPIOINT_ENR0_P0_15ER_Pos (15UL) /*!< P0_15ER (Bit 15) */ +#define GPIOINT_ENR0_P0_15ER_Msk (0x8000UL) /*!< P0_15ER (Bitfield-Mask: 0x01) */ +#define GPIOINT_ENR0_P0_16ER_Pos (16UL) /*!< P0_16ER (Bit 16) */ +#define GPIOINT_ENR0_P0_16ER_Msk (0x10000UL) /*!< P0_16ER (Bitfield-Mask: 0x01) */ +#define GPIOINT_ENR0_P0_17ER_Pos (17UL) /*!< P0_17ER (Bit 17) */ +#define GPIOINT_ENR0_P0_17ER_Msk (0x20000UL) /*!< P0_17ER (Bitfield-Mask: 0x01) */ +#define GPIOINT_ENR0_P0_18ER_Pos (18UL) /*!< P0_18ER (Bit 18) */ +#define GPIOINT_ENR0_P0_18ER_Msk (0x40000UL) /*!< P0_18ER (Bitfield-Mask: 0x01) */ +#define GPIOINT_ENR0_P0_19ER_Pos (19UL) /*!< P0_19ER (Bit 19) */ +#define GPIOINT_ENR0_P0_19ER_Msk (0x80000UL) /*!< P0_19ER (Bitfield-Mask: 0x01) */ +#define GPIOINT_ENR0_P0_20ER_Pos (20UL) /*!< P0_20ER (Bit 20) */ +#define GPIOINT_ENR0_P0_20ER_Msk (0x100000UL) /*!< P0_20ER (Bitfield-Mask: 0x01) */ +#define GPIOINT_ENR0_P0_21ER_Pos (21UL) /*!< P0_21ER (Bit 21) */ +#define GPIOINT_ENR0_P0_21ER_Msk (0x200000UL) /*!< P0_21ER (Bitfield-Mask: 0x01) */ +#define GPIOINT_ENR0_P0_22ER_Pos (22UL) /*!< P0_22ER (Bit 22) */ +#define GPIOINT_ENR0_P0_22ER_Msk (0x400000UL) /*!< P0_22ER (Bitfield-Mask: 0x01) */ +#define GPIOINT_ENR0_P0_23ER_Pos (23UL) /*!< P0_23ER (Bit 23) */ +#define GPIOINT_ENR0_P0_23ER_Msk (0x800000UL) /*!< P0_23ER (Bitfield-Mask: 0x01) */ +#define GPIOINT_ENR0_P0_24ER_Pos (24UL) /*!< P0_24ER (Bit 24) */ +#define GPIOINT_ENR0_P0_24ER_Msk (0x1000000UL) /*!< P0_24ER (Bitfield-Mask: 0x01) */ +#define GPIOINT_ENR0_P0_25ER_Pos (25UL) /*!< P0_25ER (Bit 25) */ +#define GPIOINT_ENR0_P0_25ER_Msk (0x2000000UL) /*!< P0_25ER (Bitfield-Mask: 0x01) */ +#define GPIOINT_ENR0_P0_26ER_Pos (26UL) /*!< P0_26ER (Bit 26) */ +#define GPIOINT_ENR0_P0_26ER_Msk (0x4000000UL) /*!< P0_26ER (Bitfield-Mask: 0x01) */ +#define GPIOINT_ENR0_P0_27ER_Pos (27UL) /*!< P0_27ER (Bit 27) */ +#define GPIOINT_ENR0_P0_27ER_Msk (0x8000000UL) /*!< P0_27ER (Bitfield-Mask: 0x01) */ +#define GPIOINT_ENR0_P0_28ER_Pos (28UL) /*!< P0_28ER (Bit 28) */ +#define GPIOINT_ENR0_P0_28ER_Msk (0x10000000UL) /*!< P0_28ER (Bitfield-Mask: 0x01) */ +#define GPIOINT_ENR0_P0_29ER_Pos (29UL) /*!< P0_29ER (Bit 29) */ +#define GPIOINT_ENR0_P0_29ER_Msk (0x20000000UL) /*!< P0_29ER (Bitfield-Mask: 0x01) */ +#define GPIOINT_ENR0_P0_30ER_Pos (30UL) /*!< P0_30ER (Bit 30) */ +#define GPIOINT_ENR0_P0_30ER_Msk (0x40000000UL) /*!< P0_30ER (Bitfield-Mask: 0x01) */ +/* ========================================================= ENF0 ========================================================== */ +#define GPIOINT_ENF0_P0_0EF_Pos (0UL) /*!< P0_0EF (Bit 0) */ +#define GPIOINT_ENF0_P0_0EF_Msk (0x1UL) /*!< P0_0EF (Bitfield-Mask: 0x01) */ +#define GPIOINT_ENF0_P0_1EF_Pos (1UL) /*!< P0_1EF (Bit 1) */ +#define GPIOINT_ENF0_P0_1EF_Msk (0x2UL) /*!< P0_1EF (Bitfield-Mask: 0x01) */ +#define GPIOINT_ENF0_P0_2EF_Pos (2UL) /*!< P0_2EF (Bit 2) */ +#define GPIOINT_ENF0_P0_2EF_Msk (0x4UL) /*!< P0_2EF (Bitfield-Mask: 0x01) */ +#define GPIOINT_ENF0_P0_3EF_Pos (3UL) /*!< P0_3EF (Bit 3) */ +#define GPIOINT_ENF0_P0_3EF_Msk (0x8UL) /*!< P0_3EF (Bitfield-Mask: 0x01) */ +#define GPIOINT_ENF0_P0_4EF_Pos (4UL) /*!< P0_4EF (Bit 4) */ +#define GPIOINT_ENF0_P0_4EF_Msk (0x10UL) /*!< P0_4EF (Bitfield-Mask: 0x01) */ +#define GPIOINT_ENF0_P0_5EF_Pos (5UL) /*!< P0_5EF (Bit 5) */ +#define GPIOINT_ENF0_P0_5EF_Msk (0x20UL) /*!< P0_5EF (Bitfield-Mask: 0x01) */ +#define GPIOINT_ENF0_P0_6EF_Pos (6UL) /*!< P0_6EF (Bit 6) */ +#define GPIOINT_ENF0_P0_6EF_Msk (0x40UL) /*!< P0_6EF (Bitfield-Mask: 0x01) */ +#define GPIOINT_ENF0_P0_7EF_Pos (7UL) /*!< P0_7EF (Bit 7) */ +#define GPIOINT_ENF0_P0_7EF_Msk (0x80UL) /*!< P0_7EF (Bitfield-Mask: 0x01) */ +#define GPIOINT_ENF0_P0_8EF_Pos (8UL) /*!< P0_8EF (Bit 8) */ +#define GPIOINT_ENF0_P0_8EF_Msk (0x100UL) /*!< P0_8EF (Bitfield-Mask: 0x01) */ +#define GPIOINT_ENF0_P0_9EF_Pos (9UL) /*!< P0_9EF (Bit 9) */ +#define GPIOINT_ENF0_P0_9EF_Msk (0x200UL) /*!< P0_9EF (Bitfield-Mask: 0x01) */ +#define GPIOINT_ENF0_P0_10EF_Pos (10UL) /*!< P0_10EF (Bit 10) */ +#define GPIOINT_ENF0_P0_10EF_Msk (0x400UL) /*!< P0_10EF (Bitfield-Mask: 0x01) */ +#define GPIOINT_ENF0_P0_11EF_Pos (11UL) /*!< P0_11EF (Bit 11) */ +#define GPIOINT_ENF0_P0_11EF_Msk (0x800UL) /*!< P0_11EF (Bitfield-Mask: 0x01) */ +#define GPIOINT_ENF0_P0_12EF_Pos (12UL) /*!< P0_12EF (Bit 12) */ +#define GPIOINT_ENF0_P0_12EF_Msk (0x1000UL) /*!< P0_12EF (Bitfield-Mask: 0x01) */ +#define GPIOINT_ENF0_P0_13EF_Pos (13UL) /*!< P0_13EF (Bit 13) */ +#define GPIOINT_ENF0_P0_13EF_Msk (0x2000UL) /*!< P0_13EF (Bitfield-Mask: 0x01) */ +#define GPIOINT_ENF0_P0_14EF_Pos (14UL) /*!< P0_14EF (Bit 14) */ +#define GPIOINT_ENF0_P0_14EF_Msk (0x4000UL) /*!< P0_14EF (Bitfield-Mask: 0x01) */ +#define GPIOINT_ENF0_P0_15EF_Pos (15UL) /*!< P0_15EF (Bit 15) */ +#define GPIOINT_ENF0_P0_15EF_Msk (0x8000UL) /*!< P0_15EF (Bitfield-Mask: 0x01) */ +#define GPIOINT_ENF0_P0_16EF_Pos (16UL) /*!< P0_16EF (Bit 16) */ +#define GPIOINT_ENF0_P0_16EF_Msk (0x10000UL) /*!< P0_16EF (Bitfield-Mask: 0x01) */ +#define GPIOINT_ENF0_P0_17EF_Pos (17UL) /*!< P0_17EF (Bit 17) */ +#define GPIOINT_ENF0_P0_17EF_Msk (0x20000UL) /*!< P0_17EF (Bitfield-Mask: 0x01) */ +#define GPIOINT_ENF0_P0_18EF_Pos (18UL) /*!< P0_18EF (Bit 18) */ +#define GPIOINT_ENF0_P0_18EF_Msk (0x40000UL) /*!< P0_18EF (Bitfield-Mask: 0x01) */ +#define GPIOINT_ENF0_P0_19EF_Pos (19UL) /*!< P0_19EF (Bit 19) */ +#define GPIOINT_ENF0_P0_19EF_Msk (0x80000UL) /*!< P0_19EF (Bitfield-Mask: 0x01) */ +#define GPIOINT_ENF0_P0_20EF_Pos (20UL) /*!< P0_20EF (Bit 20) */ +#define GPIOINT_ENF0_P0_20EF_Msk (0x100000UL) /*!< P0_20EF (Bitfield-Mask: 0x01) */ +#define GPIOINT_ENF0_P0_21EF_Pos (21UL) /*!< P0_21EF (Bit 21) */ +#define GPIOINT_ENF0_P0_21EF_Msk (0x200000UL) /*!< P0_21EF (Bitfield-Mask: 0x01) */ +#define GPIOINT_ENF0_P0_22EF_Pos (22UL) /*!< P0_22EF (Bit 22) */ +#define GPIOINT_ENF0_P0_22EF_Msk (0x400000UL) /*!< P0_22EF (Bitfield-Mask: 0x01) */ +#define GPIOINT_ENF0_P0_23EF_Pos (23UL) /*!< P0_23EF (Bit 23) */ +#define GPIOINT_ENF0_P0_23EF_Msk (0x800000UL) /*!< P0_23EF (Bitfield-Mask: 0x01) */ +#define GPIOINT_ENF0_P0_24EF_Pos (24UL) /*!< P0_24EF (Bit 24) */ +#define GPIOINT_ENF0_P0_24EF_Msk (0x1000000UL) /*!< P0_24EF (Bitfield-Mask: 0x01) */ +#define GPIOINT_ENF0_P0_25EF_Pos (25UL) /*!< P0_25EF (Bit 25) */ +#define GPIOINT_ENF0_P0_25EF_Msk (0x2000000UL) /*!< P0_25EF (Bitfield-Mask: 0x01) */ +#define GPIOINT_ENF0_P0_26EF_Pos (26UL) /*!< P0_26EF (Bit 26) */ +#define GPIOINT_ENF0_P0_26EF_Msk (0x4000000UL) /*!< P0_26EF (Bitfield-Mask: 0x01) */ +#define GPIOINT_ENF0_P0_27EF_Pos (27UL) /*!< P0_27EF (Bit 27) */ +#define GPIOINT_ENF0_P0_27EF_Msk (0x8000000UL) /*!< P0_27EF (Bitfield-Mask: 0x01) */ +#define GPIOINT_ENF0_P0_28EF_Pos (28UL) /*!< P0_28EF (Bit 28) */ +#define GPIOINT_ENF0_P0_28EF_Msk (0x10000000UL) /*!< P0_28EF (Bitfield-Mask: 0x01) */ +#define GPIOINT_ENF0_P0_29EF_Pos (29UL) /*!< P0_29EF (Bit 29) */ +#define GPIOINT_ENF0_P0_29EF_Msk (0x20000000UL) /*!< P0_29EF (Bitfield-Mask: 0x01) */ +#define GPIOINT_ENF0_P0_30EF_Pos (30UL) /*!< P0_30EF (Bit 30) */ +#define GPIOINT_ENF0_P0_30EF_Msk (0x40000000UL) /*!< P0_30EF (Bitfield-Mask: 0x01) */ +/* ======================================================== STATR2 ========================================================= */ +#define GPIOINT_STATR2_P2_0REI_Pos (0UL) /*!< P2_0REI (Bit 0) */ +#define GPIOINT_STATR2_P2_0REI_Msk (0x1UL) /*!< P2_0REI (Bitfield-Mask: 0x01) */ +#define GPIOINT_STATR2_P2_1REI_Pos (1UL) /*!< P2_1REI (Bit 1) */ +#define GPIOINT_STATR2_P2_1REI_Msk (0x2UL) /*!< P2_1REI (Bitfield-Mask: 0x01) */ +#define GPIOINT_STATR2_P2_2REI_Pos (2UL) /*!< P2_2REI (Bit 2) */ +#define GPIOINT_STATR2_P2_2REI_Msk (0x4UL) /*!< P2_2REI (Bitfield-Mask: 0x01) */ +#define GPIOINT_STATR2_P2_3REI_Pos (3UL) /*!< P2_3REI (Bit 3) */ +#define GPIOINT_STATR2_P2_3REI_Msk (0x8UL) /*!< P2_3REI (Bitfield-Mask: 0x01) */ +#define GPIOINT_STATR2_P2_4REI_Pos (4UL) /*!< P2_4REI (Bit 4) */ +#define GPIOINT_STATR2_P2_4REI_Msk (0x10UL) /*!< P2_4REI (Bitfield-Mask: 0x01) */ +#define GPIOINT_STATR2_P2_5REI_Pos (5UL) /*!< P2_5REI (Bit 5) */ +#define GPIOINT_STATR2_P2_5REI_Msk (0x20UL) /*!< P2_5REI (Bitfield-Mask: 0x01) */ +#define GPIOINT_STATR2_P2_6REI_Pos (6UL) /*!< P2_6REI (Bit 6) */ +#define GPIOINT_STATR2_P2_6REI_Msk (0x40UL) /*!< P2_6REI (Bitfield-Mask: 0x01) */ +#define GPIOINT_STATR2_P2_7REI_Pos (7UL) /*!< P2_7REI (Bit 7) */ +#define GPIOINT_STATR2_P2_7REI_Msk (0x80UL) /*!< P2_7REI (Bitfield-Mask: 0x01) */ +#define GPIOINT_STATR2_P2_8REI_Pos (8UL) /*!< P2_8REI (Bit 8) */ +#define GPIOINT_STATR2_P2_8REI_Msk (0x100UL) /*!< P2_8REI (Bitfield-Mask: 0x01) */ +#define GPIOINT_STATR2_P2_9REI_Pos (9UL) /*!< P2_9REI (Bit 9) */ +#define GPIOINT_STATR2_P2_9REI_Msk (0x200UL) /*!< P2_9REI (Bitfield-Mask: 0x01) */ +#define GPIOINT_STATR2_P2_10REI_Pos (10UL) /*!< P2_10REI (Bit 10) */ +#define GPIOINT_STATR2_P2_10REI_Msk (0x400UL) /*!< P2_10REI (Bitfield-Mask: 0x01) */ +#define GPIOINT_STATR2_P2_11REI_Pos (11UL) /*!< P2_11REI (Bit 11) */ +#define GPIOINT_STATR2_P2_11REI_Msk (0x800UL) /*!< P2_11REI (Bitfield-Mask: 0x01) */ +#define GPIOINT_STATR2_P2_12REI_Pos (12UL) /*!< P2_12REI (Bit 12) */ +#define GPIOINT_STATR2_P2_12REI_Msk (0x1000UL) /*!< P2_12REI (Bitfield-Mask: 0x01) */ +#define GPIOINT_STATR2_P2_13REI_Pos (13UL) /*!< P2_13REI (Bit 13) */ +#define GPIOINT_STATR2_P2_13REI_Msk (0x2000UL) /*!< P2_13REI (Bitfield-Mask: 0x01) */ +/* ======================================================== STATF2 ========================================================= */ +#define GPIOINT_STATF2_P2_0FEI_Pos (0UL) /*!< P2_0FEI (Bit 0) */ +#define GPIOINT_STATF2_P2_0FEI_Msk (0x1UL) /*!< P2_0FEI (Bitfield-Mask: 0x01) */ +#define GPIOINT_STATF2_P2_1FEI_Pos (1UL) /*!< P2_1FEI (Bit 1) */ +#define GPIOINT_STATF2_P2_1FEI_Msk (0x2UL) /*!< P2_1FEI (Bitfield-Mask: 0x01) */ +#define GPIOINT_STATF2_P2_2FEI_Pos (2UL) /*!< P2_2FEI (Bit 2) */ +#define GPIOINT_STATF2_P2_2FEI_Msk (0x4UL) /*!< P2_2FEI (Bitfield-Mask: 0x01) */ +#define GPIOINT_STATF2_P2_3FEI_Pos (3UL) /*!< P2_3FEI (Bit 3) */ +#define GPIOINT_STATF2_P2_3FEI_Msk (0x8UL) /*!< P2_3FEI (Bitfield-Mask: 0x01) */ +#define GPIOINT_STATF2_P2_4FEI_Pos (4UL) /*!< P2_4FEI (Bit 4) */ +#define GPIOINT_STATF2_P2_4FEI_Msk (0x10UL) /*!< P2_4FEI (Bitfield-Mask: 0x01) */ +#define GPIOINT_STATF2_P2_5FEI_Pos (5UL) /*!< P2_5FEI (Bit 5) */ +#define GPIOINT_STATF2_P2_5FEI_Msk (0x20UL) /*!< P2_5FEI (Bitfield-Mask: 0x01) */ +#define GPIOINT_STATF2_P2_6FEI_Pos (6UL) /*!< P2_6FEI (Bit 6) */ +#define GPIOINT_STATF2_P2_6FEI_Msk (0x40UL) /*!< P2_6FEI (Bitfield-Mask: 0x01) */ +#define GPIOINT_STATF2_P2_7FEI_Pos (7UL) /*!< P2_7FEI (Bit 7) */ +#define GPIOINT_STATF2_P2_7FEI_Msk (0x80UL) /*!< P2_7FEI (Bitfield-Mask: 0x01) */ +#define GPIOINT_STATF2_P2_8FEI_Pos (8UL) /*!< P2_8FEI (Bit 8) */ +#define GPIOINT_STATF2_P2_8FEI_Msk (0x100UL) /*!< P2_8FEI (Bitfield-Mask: 0x01) */ +#define GPIOINT_STATF2_P2_9FEI_Pos (9UL) /*!< P2_9FEI (Bit 9) */ +#define GPIOINT_STATF2_P2_9FEI_Msk (0x200UL) /*!< P2_9FEI (Bitfield-Mask: 0x01) */ +#define GPIOINT_STATF2_P2_10FEI_Pos (10UL) /*!< P2_10FEI (Bit 10) */ +#define GPIOINT_STATF2_P2_10FEI_Msk (0x400UL) /*!< P2_10FEI (Bitfield-Mask: 0x01) */ +#define GPIOINT_STATF2_P2_11FEI_Pos (11UL) /*!< P2_11FEI (Bit 11) */ +#define GPIOINT_STATF2_P2_11FEI_Msk (0x800UL) /*!< P2_11FEI (Bitfield-Mask: 0x01) */ +#define GPIOINT_STATF2_P2_12FEI_Pos (12UL) /*!< P2_12FEI (Bit 12) */ +#define GPIOINT_STATF2_P2_12FEI_Msk (0x1000UL) /*!< P2_12FEI (Bitfield-Mask: 0x01) */ +#define GPIOINT_STATF2_P2_13FEI_Pos (13UL) /*!< P2_13FEI (Bit 13) */ +#define GPIOINT_STATF2_P2_13FEI_Msk (0x2000UL) /*!< P2_13FEI (Bitfield-Mask: 0x01) */ +/* ========================================================= CLR2 ========================================================== */ +#define GPIOINT_CLR2_P2_0CI_Pos (0UL) /*!< P2_0CI (Bit 0) */ +#define GPIOINT_CLR2_P2_0CI_Msk (0x1UL) /*!< P2_0CI (Bitfield-Mask: 0x01) */ +#define GPIOINT_CLR2_P2_1CI_Pos (1UL) /*!< P2_1CI (Bit 1) */ +#define GPIOINT_CLR2_P2_1CI_Msk (0x2UL) /*!< P2_1CI (Bitfield-Mask: 0x01) */ +#define GPIOINT_CLR2_P2_2CI_Pos (2UL) /*!< P2_2CI (Bit 2) */ +#define GPIOINT_CLR2_P2_2CI_Msk (0x4UL) /*!< P2_2CI (Bitfield-Mask: 0x01) */ +#define GPIOINT_CLR2_P2_3CI_Pos (3UL) /*!< P2_3CI (Bit 3) */ +#define GPIOINT_CLR2_P2_3CI_Msk (0x8UL) /*!< P2_3CI (Bitfield-Mask: 0x01) */ +#define GPIOINT_CLR2_P2_4CI_Pos (4UL) /*!< P2_4CI (Bit 4) */ +#define GPIOINT_CLR2_P2_4CI_Msk (0x10UL) /*!< P2_4CI (Bitfield-Mask: 0x01) */ +#define GPIOINT_CLR2_P2_5CI_Pos (5UL) /*!< P2_5CI (Bit 5) */ +#define GPIOINT_CLR2_P2_5CI_Msk (0x20UL) /*!< P2_5CI (Bitfield-Mask: 0x01) */ +#define GPIOINT_CLR2_P2_6CI_Pos (6UL) /*!< P2_6CI (Bit 6) */ +#define GPIOINT_CLR2_P2_6CI_Msk (0x40UL) /*!< P2_6CI (Bitfield-Mask: 0x01) */ +#define GPIOINT_CLR2_P2_7CI_Pos (7UL) /*!< P2_7CI (Bit 7) */ +#define GPIOINT_CLR2_P2_7CI_Msk (0x80UL) /*!< P2_7CI (Bitfield-Mask: 0x01) */ +#define GPIOINT_CLR2_P2_8CI_Pos (8UL) /*!< P2_8CI (Bit 8) */ +#define GPIOINT_CLR2_P2_8CI_Msk (0x100UL) /*!< P2_8CI (Bitfield-Mask: 0x01) */ +#define GPIOINT_CLR2_P2_9CI_Pos (9UL) /*!< P2_9CI (Bit 9) */ +#define GPIOINT_CLR2_P2_9CI_Msk (0x200UL) /*!< P2_9CI (Bitfield-Mask: 0x01) */ +#define GPIOINT_CLR2_P2_10CI_Pos (10UL) /*!< P2_10CI (Bit 10) */ +#define GPIOINT_CLR2_P2_10CI_Msk (0x400UL) /*!< P2_10CI (Bitfield-Mask: 0x01) */ +#define GPIOINT_CLR2_P2_11CI_Pos (11UL) /*!< P2_11CI (Bit 11) */ +#define GPIOINT_CLR2_P2_11CI_Msk (0x800UL) /*!< P2_11CI (Bitfield-Mask: 0x01) */ +#define GPIOINT_CLR2_P2_12CI_Pos (12UL) /*!< P2_12CI (Bit 12) */ +#define GPIOINT_CLR2_P2_12CI_Msk (0x1000UL) /*!< P2_12CI (Bitfield-Mask: 0x01) */ +#define GPIOINT_CLR2_P2_13CI_Pos (13UL) /*!< P2_13CI (Bit 13) */ +#define GPIOINT_CLR2_P2_13CI_Msk (0x2000UL) /*!< P2_13CI (Bitfield-Mask: 0x01) */ +/* ========================================================= ENR2 ========================================================== */ +#define GPIOINT_ENR2_P2_0ER_Pos (0UL) /*!< P2_0ER (Bit 0) */ +#define GPIOINT_ENR2_P2_0ER_Msk (0x1UL) /*!< P2_0ER (Bitfield-Mask: 0x01) */ +#define GPIOINT_ENR2_P2_1ER_Pos (1UL) /*!< P2_1ER (Bit 1) */ +#define GPIOINT_ENR2_P2_1ER_Msk (0x2UL) /*!< P2_1ER (Bitfield-Mask: 0x01) */ +#define GPIOINT_ENR2_P2_2ER_Pos (2UL) /*!< P2_2ER (Bit 2) */ +#define GPIOINT_ENR2_P2_2ER_Msk (0x4UL) /*!< P2_2ER (Bitfield-Mask: 0x01) */ +#define GPIOINT_ENR2_P2_3ER_Pos (3UL) /*!< P2_3ER (Bit 3) */ +#define GPIOINT_ENR2_P2_3ER_Msk (0x8UL) /*!< P2_3ER (Bitfield-Mask: 0x01) */ +#define GPIOINT_ENR2_P2_4ER_Pos (4UL) /*!< P2_4ER (Bit 4) */ +#define GPIOINT_ENR2_P2_4ER_Msk (0x10UL) /*!< P2_4ER (Bitfield-Mask: 0x01) */ +#define GPIOINT_ENR2_P2_5ER_Pos (5UL) /*!< P2_5ER (Bit 5) */ +#define GPIOINT_ENR2_P2_5ER_Msk (0x20UL) /*!< P2_5ER (Bitfield-Mask: 0x01) */ +#define GPIOINT_ENR2_P2_6ER_Pos (6UL) /*!< P2_6ER (Bit 6) */ +#define GPIOINT_ENR2_P2_6ER_Msk (0x40UL) /*!< P2_6ER (Bitfield-Mask: 0x01) */ +#define GPIOINT_ENR2_P2_7ER_Pos (7UL) /*!< P2_7ER (Bit 7) */ +#define GPIOINT_ENR2_P2_7ER_Msk (0x80UL) /*!< P2_7ER (Bitfield-Mask: 0x01) */ +#define GPIOINT_ENR2_P2_8ER_Pos (8UL) /*!< P2_8ER (Bit 8) */ +#define GPIOINT_ENR2_P2_8ER_Msk (0x100UL) /*!< P2_8ER (Bitfield-Mask: 0x01) */ +#define GPIOINT_ENR2_P2_9ER_Pos (9UL) /*!< P2_9ER (Bit 9) */ +#define GPIOINT_ENR2_P2_9ER_Msk (0x200UL) /*!< P2_9ER (Bitfield-Mask: 0x01) */ +#define GPIOINT_ENR2_P2_10ER_Pos (10UL) /*!< P2_10ER (Bit 10) */ +#define GPIOINT_ENR2_P2_10ER_Msk (0x400UL) /*!< P2_10ER (Bitfield-Mask: 0x01) */ +#define GPIOINT_ENR2_P2_11ER_Pos (11UL) /*!< P2_11ER (Bit 11) */ +#define GPIOINT_ENR2_P2_11ER_Msk (0x800UL) /*!< P2_11ER (Bitfield-Mask: 0x01) */ +#define GPIOINT_ENR2_P2_12ER_Pos (12UL) /*!< P2_12ER (Bit 12) */ +#define GPIOINT_ENR2_P2_12ER_Msk (0x1000UL) /*!< P2_12ER (Bitfield-Mask: 0x01) */ +#define GPIOINT_ENR2_P2_13ER_Pos (13UL) /*!< P2_13ER (Bit 13) */ +#define GPIOINT_ENR2_P2_13ER_Msk (0x2000UL) /*!< P2_13ER (Bitfield-Mask: 0x01) */ +/* ========================================================= ENF2 ========================================================== */ +#define GPIOINT_ENF2_P2_0EF_Pos (0UL) /*!< P2_0EF (Bit 0) */ +#define GPIOINT_ENF2_P2_0EF_Msk (0x1UL) /*!< P2_0EF (Bitfield-Mask: 0x01) */ +#define GPIOINT_ENF2_P2_1EF_Pos (1UL) /*!< P2_1EF (Bit 1) */ +#define GPIOINT_ENF2_P2_1EF_Msk (0x2UL) /*!< P2_1EF (Bitfield-Mask: 0x01) */ +#define GPIOINT_ENF2_P2_2EF_Pos (2UL) /*!< P2_2EF (Bit 2) */ +#define GPIOINT_ENF2_P2_2EF_Msk (0x4UL) /*!< P2_2EF (Bitfield-Mask: 0x01) */ +#define GPIOINT_ENF2_P2_3EF_Pos (3UL) /*!< P2_3EF (Bit 3) */ +#define GPIOINT_ENF2_P2_3EF_Msk (0x8UL) /*!< P2_3EF (Bitfield-Mask: 0x01) */ +#define GPIOINT_ENF2_P2_4EF_Pos (4UL) /*!< P2_4EF (Bit 4) */ +#define GPIOINT_ENF2_P2_4EF_Msk (0x10UL) /*!< P2_4EF (Bitfield-Mask: 0x01) */ +#define GPIOINT_ENF2_P2_5EF_Pos (5UL) /*!< P2_5EF (Bit 5) */ +#define GPIOINT_ENF2_P2_5EF_Msk (0x20UL) /*!< P2_5EF (Bitfield-Mask: 0x01) */ +#define GPIOINT_ENF2_P2_6EF_Pos (6UL) /*!< P2_6EF (Bit 6) */ +#define GPIOINT_ENF2_P2_6EF_Msk (0x40UL) /*!< P2_6EF (Bitfield-Mask: 0x01) */ +#define GPIOINT_ENF2_P2_7EF_Pos (7UL) /*!< P2_7EF (Bit 7) */ +#define GPIOINT_ENF2_P2_7EF_Msk (0x80UL) /*!< P2_7EF (Bitfield-Mask: 0x01) */ +#define GPIOINT_ENF2_P2_8EF_Pos (8UL) /*!< P2_8EF (Bit 8) */ +#define GPIOINT_ENF2_P2_8EF_Msk (0x100UL) /*!< P2_8EF (Bitfield-Mask: 0x01) */ +#define GPIOINT_ENF2_P2_9EF_Pos (9UL) /*!< P2_9EF (Bit 9) */ +#define GPIOINT_ENF2_P2_9EF_Msk (0x200UL) /*!< P2_9EF (Bitfield-Mask: 0x01) */ +#define GPIOINT_ENF2_P2_10EF_Pos (10UL) /*!< P2_10EF (Bit 10) */ +#define GPIOINT_ENF2_P2_10EF_Msk (0x400UL) /*!< P2_10EF (Bitfield-Mask: 0x01) */ +#define GPIOINT_ENF2_P2_11EF_Pos (11UL) /*!< P2_11EF (Bit 11) */ +#define GPIOINT_ENF2_P2_11EF_Msk (0x800UL) /*!< P2_11EF (Bitfield-Mask: 0x01) */ +#define GPIOINT_ENF2_P2_12EF_Pos (12UL) /*!< P2_12EF (Bit 12) */ +#define GPIOINT_ENF2_P2_12EF_Msk (0x1000UL) /*!< P2_12EF (Bitfield-Mask: 0x01) */ +#define GPIOINT_ENF2_P2_13EF_Pos (13UL) /*!< P2_13EF (Bit 13) */ +#define GPIOINT_ENF2_P2_13EF_Msk (0x2000UL) /*!< P2_13EF (Bitfield-Mask: 0x01) */ + + +/* =========================================================================================================================== */ +/* ================ LPC_PINCONNECT ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== PINSEL0 ======================================================== */ +#define PINCONNECT_PINSEL0_P0_0_Pos (0UL) /*!< P0_0 (Bit 0) */ +#define PINCONNECT_PINSEL0_P0_0_Msk (0x3UL) /*!< P0_0 (Bitfield-Mask: 0x03) */ +#define PINCONNECT_PINSEL0_P0_1_Pos (2UL) /*!< P0_1 (Bit 2) */ +#define PINCONNECT_PINSEL0_P0_1_Msk (0xcUL) /*!< P0_1 (Bitfield-Mask: 0x03) */ +#define PINCONNECT_PINSEL0_P0_2_Pos (4UL) /*!< P0_2 (Bit 4) */ +#define PINCONNECT_PINSEL0_P0_2_Msk (0x30UL) /*!< P0_2 (Bitfield-Mask: 0x03) */ +#define PINCONNECT_PINSEL0_P0_3_Pos (6UL) /*!< P0_3 (Bit 6) */ +#define PINCONNECT_PINSEL0_P0_3_Msk (0xc0UL) /*!< P0_3 (Bitfield-Mask: 0x03) */ +#define PINCONNECT_PINSEL0_P0_4_Pos (8UL) /*!< P0_4 (Bit 8) */ +#define PINCONNECT_PINSEL0_P0_4_Msk (0x300UL) /*!< P0_4 (Bitfield-Mask: 0x03) */ +#define PINCONNECT_PINSEL0_P0_5_Pos (10UL) /*!< P0_5 (Bit 10) */ +#define PINCONNECT_PINSEL0_P0_5_Msk (0xc00UL) /*!< P0_5 (Bitfield-Mask: 0x03) */ +#define PINCONNECT_PINSEL0_P0_6_Pos (12UL) /*!< P0_6 (Bit 12) */ +#define PINCONNECT_PINSEL0_P0_6_Msk (0x3000UL) /*!< P0_6 (Bitfield-Mask: 0x03) */ +#define PINCONNECT_PINSEL0_P0_7_Pos (14UL) /*!< P0_7 (Bit 14) */ +#define PINCONNECT_PINSEL0_P0_7_Msk (0xc000UL) /*!< P0_7 (Bitfield-Mask: 0x03) */ +#define PINCONNECT_PINSEL0_P0_8_Pos (16UL) /*!< P0_8 (Bit 16) */ +#define PINCONNECT_PINSEL0_P0_8_Msk (0x30000UL) /*!< P0_8 (Bitfield-Mask: 0x03) */ +#define PINCONNECT_PINSEL0_P0_9_Pos (18UL) /*!< P0_9 (Bit 18) */ +#define PINCONNECT_PINSEL0_P0_9_Msk (0xc0000UL) /*!< P0_9 (Bitfield-Mask: 0x03) */ +#define PINCONNECT_PINSEL0_P0_10_Pos (20UL) /*!< P0_10 (Bit 20) */ +#define PINCONNECT_PINSEL0_P0_10_Msk (0x300000UL) /*!< P0_10 (Bitfield-Mask: 0x03) */ +#define PINCONNECT_PINSEL0_P0_11_Pos (22UL) /*!< P0_11 (Bit 22) */ +#define PINCONNECT_PINSEL0_P0_11_Msk (0xc00000UL) /*!< P0_11 (Bitfield-Mask: 0x03) */ +#define PINCONNECT_PINSEL0_P0_15_Pos (30UL) /*!< P0_15 (Bit 30) */ +#define PINCONNECT_PINSEL0_P0_15_Msk (0xc0000000UL) /*!< P0_15 (Bitfield-Mask: 0x03) */ +/* ======================================================== PINSEL1 ======================================================== */ +#define PINCONNECT_PINSEL1_P0_16_Pos (0UL) /*!< P0_16 (Bit 0) */ +#define PINCONNECT_PINSEL1_P0_16_Msk (0x3UL) /*!< P0_16 (Bitfield-Mask: 0x03) */ +#define PINCONNECT_PINSEL1_P0_17_Pos (2UL) /*!< P0_17 (Bit 2) */ +#define PINCONNECT_PINSEL1_P0_17_Msk (0xcUL) /*!< P0_17 (Bitfield-Mask: 0x03) */ +#define PINCONNECT_PINSEL1_P0_18_Pos (4UL) /*!< P0_18 (Bit 4) */ +#define PINCONNECT_PINSEL1_P0_18_Msk (0x30UL) /*!< P0_18 (Bitfield-Mask: 0x03) */ +#define PINCONNECT_PINSEL1_P0_19_Pos (6UL) /*!< P0_19 (Bit 6) */ +#define PINCONNECT_PINSEL1_P0_19_Msk (0xc0UL) /*!< P0_19 (Bitfield-Mask: 0x03) */ +#define PINCONNECT_PINSEL1_P0_20_Pos (8UL) /*!< P0_20 (Bit 8) */ +#define PINCONNECT_PINSEL1_P0_20_Msk (0x300UL) /*!< P0_20 (Bitfield-Mask: 0x03) */ +#define PINCONNECT_PINSEL1_P0_21_Pos (10UL) /*!< P0_21 (Bit 10) */ +#define PINCONNECT_PINSEL1_P0_21_Msk (0xc00UL) /*!< P0_21 (Bitfield-Mask: 0x03) */ +#define PINCONNECT_PINSEL1_P0_22_Pos (12UL) /*!< P0_22 (Bit 12) */ +#define PINCONNECT_PINSEL1_P0_22_Msk (0x3000UL) /*!< P0_22 (Bitfield-Mask: 0x03) */ +#define PINCONNECT_PINSEL1_P0_23_Pos (14UL) /*!< P0_23 (Bit 14) */ +#define PINCONNECT_PINSEL1_P0_23_Msk (0xc000UL) /*!< P0_23 (Bitfield-Mask: 0x03) */ +#define PINCONNECT_PINSEL1_P0_24_Pos (16UL) /*!< P0_24 (Bit 16) */ +#define PINCONNECT_PINSEL1_P0_24_Msk (0x30000UL) /*!< P0_24 (Bitfield-Mask: 0x03) */ +#define PINCONNECT_PINSEL1_P0_25_Pos (18UL) /*!< P0_25 (Bit 18) */ +#define PINCONNECT_PINSEL1_P0_25_Msk (0xc0000UL) /*!< P0_25 (Bitfield-Mask: 0x03) */ +#define PINCONNECT_PINSEL1_P0_26_Pos (20UL) /*!< P0_26 (Bit 20) */ +#define PINCONNECT_PINSEL1_P0_26_Msk (0x300000UL) /*!< P0_26 (Bitfield-Mask: 0x03) */ +#define PINCONNECT_PINSEL1_P0_27_Pos (22UL) /*!< P0_27 (Bit 22) */ +#define PINCONNECT_PINSEL1_P0_27_Msk (0xc00000UL) /*!< P0_27 (Bitfield-Mask: 0x03) */ +#define PINCONNECT_PINSEL1_P0_28_Pos (24UL) /*!< P0_28 (Bit 24) */ +#define PINCONNECT_PINSEL1_P0_28_Msk (0x3000000UL) /*!< P0_28 (Bitfield-Mask: 0x03) */ +#define PINCONNECT_PINSEL1_P0_29_Pos (26UL) /*!< P0_29 (Bit 26) */ +#define PINCONNECT_PINSEL1_P0_29_Msk (0xc000000UL) /*!< P0_29 (Bitfield-Mask: 0x03) */ +#define PINCONNECT_PINSEL1_P0_30_Pos (28UL) /*!< P0_30 (Bit 28) */ +#define PINCONNECT_PINSEL1_P0_30_Msk (0x30000000UL) /*!< P0_30 (Bitfield-Mask: 0x03) */ +/* ======================================================== PINSEL2 ======================================================== */ +#define PINCONNECT_PINSEL2_P1_0_Pos (0UL) /*!< P1_0 (Bit 0) */ +#define PINCONNECT_PINSEL2_P1_0_Msk (0x3UL) /*!< P1_0 (Bitfield-Mask: 0x03) */ +#define PINCONNECT_PINSEL2_P1_1_Pos (2UL) /*!< P1_1 (Bit 2) */ +#define PINCONNECT_PINSEL2_P1_1_Msk (0xcUL) /*!< P1_1 (Bitfield-Mask: 0x03) */ +#define PINCONNECT_PINSEL2_P1_4_Pos (8UL) /*!< P1_4 (Bit 8) */ +#define PINCONNECT_PINSEL2_P1_4_Msk (0x300UL) /*!< P1_4 (Bitfield-Mask: 0x03) */ +#define PINCONNECT_PINSEL2_P1_8_Pos (16UL) /*!< P1_8 (Bit 16) */ +#define PINCONNECT_PINSEL2_P1_8_Msk (0x30000UL) /*!< P1_8 (Bitfield-Mask: 0x03) */ +#define PINCONNECT_PINSEL2_P1_9_Pos (18UL) /*!< P1_9 (Bit 18) */ +#define PINCONNECT_PINSEL2_P1_9_Msk (0xc0000UL) /*!< P1_9 (Bitfield-Mask: 0x03) */ +#define PINCONNECT_PINSEL2_P1_10_Pos (20UL) /*!< P1_10 (Bit 20) */ +#define PINCONNECT_PINSEL2_P1_10_Msk (0x300000UL) /*!< P1_10 (Bitfield-Mask: 0x03) */ +#define PINCONNECT_PINSEL2_P1_14_Pos (22UL) /*!< P1_14 (Bit 22) */ +#define PINCONNECT_PINSEL2_P1_14_Msk (0xc00000UL) /*!< P1_14 (Bitfield-Mask: 0x03) */ +#define PINCONNECT_PINSEL2_P1_15_Pos (30UL) /*!< P1_15 (Bit 30) */ +#define PINCONNECT_PINSEL2_P1_15_Msk (0xc0000000UL) /*!< P1_15 (Bitfield-Mask: 0x03) */ +/* ======================================================== PINSEL3 ======================================================== */ +#define PINCONNECT_PINSEL3_P1_16_Pos (0UL) /*!< P1_16 (Bit 0) */ +#define PINCONNECT_PINSEL3_P1_16_Msk (0x3UL) /*!< P1_16 (Bitfield-Mask: 0x03) */ +#define PINCONNECT_PINSEL3_P1_17_Pos (2UL) /*!< P1_17 (Bit 2) */ +#define PINCONNECT_PINSEL3_P1_17_Msk (0xcUL) /*!< P1_17 (Bitfield-Mask: 0x03) */ +#define PINCONNECT_PINSEL3_P1_18_Pos (4UL) /*!< P1_18 (Bit 4) */ +#define PINCONNECT_PINSEL3_P1_18_Msk (0x30UL) /*!< P1_18 (Bitfield-Mask: 0x03) */ +#define PINCONNECT_PINSEL3_P1_19_Pos (6UL) /*!< P1_19 (Bit 6) */ +#define PINCONNECT_PINSEL3_P1_19_Msk (0xc0UL) /*!< P1_19 (Bitfield-Mask: 0x03) */ +#define PINCONNECT_PINSEL3_P1_20_Pos (8UL) /*!< P1_20 (Bit 8) */ +#define PINCONNECT_PINSEL3_P1_20_Msk (0x300UL) /*!< P1_20 (Bitfield-Mask: 0x03) */ +#define PINCONNECT_PINSEL3_P1_21_Pos (10UL) /*!< P1_21 (Bit 10) */ +#define PINCONNECT_PINSEL3_P1_21_Msk (0xc00UL) /*!< P1_21 (Bitfield-Mask: 0x03) */ +#define PINCONNECT_PINSEL3_P1_22_Pos (12UL) /*!< P1_22 (Bit 12) */ +#define PINCONNECT_PINSEL3_P1_22_Msk (0x3000UL) /*!< P1_22 (Bitfield-Mask: 0x03) */ +#define PINCONNECT_PINSEL3_P1_23_Pos (14UL) /*!< P1_23 (Bit 14) */ +#define PINCONNECT_PINSEL3_P1_23_Msk (0xc000UL) /*!< P1_23 (Bitfield-Mask: 0x03) */ +#define PINCONNECT_PINSEL3_P1_24_Pos (16UL) /*!< P1_24 (Bit 16) */ +#define PINCONNECT_PINSEL3_P1_24_Msk (0x30000UL) /*!< P1_24 (Bitfield-Mask: 0x03) */ +#define PINCONNECT_PINSEL3_P1_25_Pos (18UL) /*!< P1_25 (Bit 18) */ +#define PINCONNECT_PINSEL3_P1_25_Msk (0xc0000UL) /*!< P1_25 (Bitfield-Mask: 0x03) */ +#define PINCONNECT_PINSEL3_P1_26_Pos (20UL) /*!< P1_26 (Bit 20) */ +#define PINCONNECT_PINSEL3_P1_26_Msk (0x300000UL) /*!< P1_26 (Bitfield-Mask: 0x03) */ +#define PINCONNECT_PINSEL3_P1_27_Pos (22UL) /*!< P1_27 (Bit 22) */ +#define PINCONNECT_PINSEL3_P1_27_Msk (0xc00000UL) /*!< P1_27 (Bitfield-Mask: 0x03) */ +#define PINCONNECT_PINSEL3_P1_28_Pos (24UL) /*!< P1_28 (Bit 24) */ +#define PINCONNECT_PINSEL3_P1_28_Msk (0x3000000UL) /*!< P1_28 (Bitfield-Mask: 0x03) */ +#define PINCONNECT_PINSEL3_P1_29_Pos (26UL) /*!< P1_29 (Bit 26) */ +#define PINCONNECT_PINSEL3_P1_29_Msk (0xc000000UL) /*!< P1_29 (Bitfield-Mask: 0x03) */ +#define PINCONNECT_PINSEL3_P1_30_Pos (28UL) /*!< P1_30 (Bit 28) */ +#define PINCONNECT_PINSEL3_P1_30_Msk (0x30000000UL) /*!< P1_30 (Bitfield-Mask: 0x03) */ +#define PINCONNECT_PINSEL3_P1_31_Pos (30UL) /*!< P1_31 (Bit 30) */ +#define PINCONNECT_PINSEL3_P1_31_Msk (0xc0000000UL) /*!< P1_31 (Bitfield-Mask: 0x03) */ +/* ======================================================== PINSEL4 ======================================================== */ +#define PINCONNECT_PINSEL4_P2_0_Pos (0UL) /*!< P2_0 (Bit 0) */ +#define PINCONNECT_PINSEL4_P2_0_Msk (0x3UL) /*!< P2_0 (Bitfield-Mask: 0x03) */ +#define PINCONNECT_PINSEL4_P2_1_Pos (2UL) /*!< P2_1 (Bit 2) */ +#define PINCONNECT_PINSEL4_P2_1_Msk (0xcUL) /*!< P2_1 (Bitfield-Mask: 0x03) */ +#define PINCONNECT_PINSEL4_P2_2_Pos (4UL) /*!< P2_2 (Bit 4) */ +#define PINCONNECT_PINSEL4_P2_2_Msk (0x30UL) /*!< P2_2 (Bitfield-Mask: 0x03) */ +#define PINCONNECT_PINSEL4_P2_3_Pos (6UL) /*!< P2_3 (Bit 6) */ +#define PINCONNECT_PINSEL4_P2_3_Msk (0xc0UL) /*!< P2_3 (Bitfield-Mask: 0x03) */ +#define PINCONNECT_PINSEL4_P2_4_Pos (8UL) /*!< P2_4 (Bit 8) */ +#define PINCONNECT_PINSEL4_P2_4_Msk (0x300UL) /*!< P2_4 (Bitfield-Mask: 0x03) */ +#define PINCONNECT_PINSEL4_P2_5_Pos (10UL) /*!< P2_5 (Bit 10) */ +#define PINCONNECT_PINSEL4_P2_5_Msk (0xc00UL) /*!< P2_5 (Bitfield-Mask: 0x03) */ +#define PINCONNECT_PINSEL4_P2_6_Pos (12UL) /*!< P2_6 (Bit 12) */ +#define PINCONNECT_PINSEL4_P2_6_Msk (0x3000UL) /*!< P2_6 (Bitfield-Mask: 0x03) */ +#define PINCONNECT_PINSEL4_P2_7_Pos (14UL) /*!< P2_7 (Bit 14) */ +#define PINCONNECT_PINSEL4_P2_7_Msk (0xc000UL) /*!< P2_7 (Bitfield-Mask: 0x03) */ +#define PINCONNECT_PINSEL4_P2_8_Pos (16UL) /*!< P2_8 (Bit 16) */ +#define PINCONNECT_PINSEL4_P2_8_Msk (0x30000UL) /*!< P2_8 (Bitfield-Mask: 0x03) */ +#define PINCONNECT_PINSEL4_P2_9_Pos (18UL) /*!< P2_9 (Bit 18) */ +#define PINCONNECT_PINSEL4_P2_9_Msk (0xc0000UL) /*!< P2_9 (Bitfield-Mask: 0x03) */ +#define PINCONNECT_PINSEL4_P2_10_Pos (20UL) /*!< P2_10 (Bit 20) */ +#define PINCONNECT_PINSEL4_P2_10_Msk (0x300000UL) /*!< P2_10 (Bitfield-Mask: 0x03) */ +#define PINCONNECT_PINSEL4_P2_11_Pos (22UL) /*!< P2_11 (Bit 22) */ +#define PINCONNECT_PINSEL4_P2_11_Msk (0xc00000UL) /*!< P2_11 (Bitfield-Mask: 0x03) */ +#define PINCONNECT_PINSEL4_P2_12_Pos (24UL) /*!< P2_12 (Bit 24) */ +#define PINCONNECT_PINSEL4_P2_12_Msk (0x3000000UL) /*!< P2_12 (Bitfield-Mask: 0x03) */ +#define PINCONNECT_PINSEL4_P2_13_Pos (26UL) /*!< P2_13 (Bit 26) */ +#define PINCONNECT_PINSEL4_P2_13_Msk (0xc000000UL) /*!< P2_13 (Bitfield-Mask: 0x03) */ +/* ======================================================== PINSEL7 ======================================================== */ +#define PINCONNECT_PINSEL7_P3_25_Pos (18UL) /*!< P3_25 (Bit 18) */ +#define PINCONNECT_PINSEL7_P3_25_Msk (0xc0000UL) /*!< P3_25 (Bitfield-Mask: 0x03) */ +#define PINCONNECT_PINSEL7_P3_26_Pos (20UL) /*!< P3_26 (Bit 20) */ +#define PINCONNECT_PINSEL7_P3_26_Msk (0x300000UL) /*!< P3_26 (Bitfield-Mask: 0x03) */ +/* ======================================================== PINSEL9 ======================================================== */ +#define PINCONNECT_PINSEL9_P4_28_Pos (24UL) /*!< P4_28 (Bit 24) */ +#define PINCONNECT_PINSEL9_P4_28_Msk (0x3000000UL) /*!< P4_28 (Bitfield-Mask: 0x03) */ +#define PINCONNECT_PINSEL9_P4_29_Pos (26UL) /*!< P4_29 (Bit 26) */ +#define PINCONNECT_PINSEL9_P4_29_Msk (0xc000000UL) /*!< P4_29 (Bitfield-Mask: 0x03) */ +/* ======================================================= PINSEL10 ======================================================== */ +#define PINCONNECT_PINSEL10_TPIUCTRL_Pos (3UL) /*!< TPIUCTRL (Bit 3) */ +#define PINCONNECT_PINSEL10_TPIUCTRL_Msk (0x8UL) /*!< TPIUCTRL (Bitfield-Mask: 0x01) */ +/* ======================================================= PINMODE0 ======================================================== */ +#define PINCONNECT_PINMODE0_P0_00MODE_Pos (0UL) /*!< P0_00MODE (Bit 0) */ +#define PINCONNECT_PINMODE0_P0_00MODE_Msk (0x3UL) /*!< P0_00MODE (Bitfield-Mask: 0x03) */ +#define PINCONNECT_PINMODE0_P0_01MODE_Pos (2UL) /*!< P0_01MODE (Bit 2) */ +#define PINCONNECT_PINMODE0_P0_01MODE_Msk (0xcUL) /*!< P0_01MODE (Bitfield-Mask: 0x03) */ +#define PINCONNECT_PINMODE0_P0_02MODE_Pos (4UL) /*!< P0_02MODE (Bit 4) */ +#define PINCONNECT_PINMODE0_P0_02MODE_Msk (0x30UL) /*!< P0_02MODE (Bitfield-Mask: 0x03) */ +#define PINCONNECT_PINMODE0_P0_03MODE_Pos (6UL) /*!< P0_03MODE (Bit 6) */ +#define PINCONNECT_PINMODE0_P0_03MODE_Msk (0xc0UL) /*!< P0_03MODE (Bitfield-Mask: 0x03) */ +#define PINCONNECT_PINMODE0_P0_04MODE_Pos (8UL) /*!< P0_04MODE (Bit 8) */ +#define PINCONNECT_PINMODE0_P0_04MODE_Msk (0x300UL) /*!< P0_04MODE (Bitfield-Mask: 0x03) */ +#define PINCONNECT_PINMODE0_P0_05MODE_Pos (10UL) /*!< P0_05MODE (Bit 10) */ +#define PINCONNECT_PINMODE0_P0_05MODE_Msk (0xc00UL) /*!< P0_05MODE (Bitfield-Mask: 0x03) */ +#define PINCONNECT_PINMODE0_P0_06MODE_Pos (12UL) /*!< P0_06MODE (Bit 12) */ +#define PINCONNECT_PINMODE0_P0_06MODE_Msk (0x3000UL) /*!< P0_06MODE (Bitfield-Mask: 0x03) */ +#define PINCONNECT_PINMODE0_P0_07MODE_Pos (14UL) /*!< P0_07MODE (Bit 14) */ +#define PINCONNECT_PINMODE0_P0_07MODE_Msk (0xc000UL) /*!< P0_07MODE (Bitfield-Mask: 0x03) */ +#define PINCONNECT_PINMODE0_P0_08MODE_Pos (16UL) /*!< P0_08MODE (Bit 16) */ +#define PINCONNECT_PINMODE0_P0_08MODE_Msk (0x30000UL) /*!< P0_08MODE (Bitfield-Mask: 0x03) */ +#define PINCONNECT_PINMODE0_P0_09MODE_Pos (18UL) /*!< P0_09MODE (Bit 18) */ +#define PINCONNECT_PINMODE0_P0_09MODE_Msk (0xc0000UL) /*!< P0_09MODE (Bitfield-Mask: 0x03) */ +#define PINCONNECT_PINMODE0_P0_10MODE_Pos (20UL) /*!< P0_10MODE (Bit 20) */ +#define PINCONNECT_PINMODE0_P0_10MODE_Msk (0x300000UL) /*!< P0_10MODE (Bitfield-Mask: 0x03) */ +#define PINCONNECT_PINMODE0_P0_11MODE_Pos (22UL) /*!< P0_11MODE (Bit 22) */ +#define PINCONNECT_PINMODE0_P0_11MODE_Msk (0xc00000UL) /*!< P0_11MODE (Bitfield-Mask: 0x03) */ +#define PINCONNECT_PINMODE0_P0_15MODE_Pos (30UL) /*!< P0_15MODE (Bit 30) */ +#define PINCONNECT_PINMODE0_P0_15MODE_Msk (0xc0000000UL) /*!< P0_15MODE (Bitfield-Mask: 0x03) */ +/* ======================================================= PINMODE1 ======================================================== */ +#define PINCONNECT_PINMODE1_P0_16MODE_Pos (0UL) /*!< P0_16MODE (Bit 0) */ +#define PINCONNECT_PINMODE1_P0_16MODE_Msk (0x3UL) /*!< P0_16MODE (Bitfield-Mask: 0x03) */ +#define PINCONNECT_PINMODE1_P0_17MODE_Pos (2UL) /*!< P0_17MODE (Bit 2) */ +#define PINCONNECT_PINMODE1_P0_17MODE_Msk (0xcUL) /*!< P0_17MODE (Bitfield-Mask: 0x03) */ +#define PINCONNECT_PINMODE1_P0_18MODE_Pos (4UL) /*!< P0_18MODE (Bit 4) */ +#define PINCONNECT_PINMODE1_P0_18MODE_Msk (0x30UL) /*!< P0_18MODE (Bitfield-Mask: 0x03) */ +#define PINCONNECT_PINMODE1_P0_19MODE_Pos (6UL) /*!< P0_19MODE (Bit 6) */ +#define PINCONNECT_PINMODE1_P0_19MODE_Msk (0xc0UL) /*!< P0_19MODE (Bitfield-Mask: 0x03) */ +#define PINCONNECT_PINMODE1_P0_20MODE_Pos (8UL) /*!< P0_20MODE (Bit 8) */ +#define PINCONNECT_PINMODE1_P0_20MODE_Msk (0x300UL) /*!< P0_20MODE (Bitfield-Mask: 0x03) */ +#define PINCONNECT_PINMODE1_P0_21MODE_Pos (10UL) /*!< P0_21MODE (Bit 10) */ +#define PINCONNECT_PINMODE1_P0_21MODE_Msk (0xc00UL) /*!< P0_21MODE (Bitfield-Mask: 0x03) */ +#define PINCONNECT_PINMODE1_P0_22MODE_Pos (12UL) /*!< P0_22MODE (Bit 12) */ +#define PINCONNECT_PINMODE1_P0_22MODE_Msk (0x3000UL) /*!< P0_22MODE (Bitfield-Mask: 0x03) */ +#define PINCONNECT_PINMODE1_P0_23MODE_Pos (14UL) /*!< P0_23MODE (Bit 14) */ +#define PINCONNECT_PINMODE1_P0_23MODE_Msk (0xc000UL) /*!< P0_23MODE (Bitfield-Mask: 0x03) */ +#define PINCONNECT_PINMODE1_P0_24MODE_Pos (16UL) /*!< P0_24MODE (Bit 16) */ +#define PINCONNECT_PINMODE1_P0_24MODE_Msk (0x30000UL) /*!< P0_24MODE (Bitfield-Mask: 0x03) */ +#define PINCONNECT_PINMODE1_P0_25MODE_Pos (18UL) /*!< P0_25MODE (Bit 18) */ +#define PINCONNECT_PINMODE1_P0_25MODE_Msk (0xc0000UL) /*!< P0_25MODE (Bitfield-Mask: 0x03) */ +#define PINCONNECT_PINMODE1_P0_26MODE_Pos (20UL) /*!< P0_26MODE (Bit 20) */ +#define PINCONNECT_PINMODE1_P0_26MODE_Msk (0x300000UL) /*!< P0_26MODE (Bitfield-Mask: 0x03) */ +/* ======================================================= PINMODE2 ======================================================== */ +#define PINCONNECT_PINMODE2_P1_00MODE_Pos (0UL) /*!< P1_00MODE (Bit 0) */ +#define PINCONNECT_PINMODE2_P1_00MODE_Msk (0x3UL) /*!< P1_00MODE (Bitfield-Mask: 0x03) */ +#define PINCONNECT_PINMODE2_P1_01MODE_Pos (2UL) /*!< P1_01MODE (Bit 2) */ +#define PINCONNECT_PINMODE2_P1_01MODE_Msk (0xcUL) /*!< P1_01MODE (Bitfield-Mask: 0x03) */ +#define PINCONNECT_PINMODE2_P1_04MODE_Pos (8UL) /*!< P1_04MODE (Bit 8) */ +#define PINCONNECT_PINMODE2_P1_04MODE_Msk (0x300UL) /*!< P1_04MODE (Bitfield-Mask: 0x03) */ +#define PINCONNECT_PINMODE2_P1_08MODE_Pos (16UL) /*!< P1_08MODE (Bit 16) */ +#define PINCONNECT_PINMODE2_P1_08MODE_Msk (0x30000UL) /*!< P1_08MODE (Bitfield-Mask: 0x03) */ +#define PINCONNECT_PINMODE2_P1_09MODE_Pos (18UL) /*!< P1_09MODE (Bit 18) */ +#define PINCONNECT_PINMODE2_P1_09MODE_Msk (0xc0000UL) /*!< P1_09MODE (Bitfield-Mask: 0x03) */ +#define PINCONNECT_PINMODE2_P1_10MODE_Pos (20UL) /*!< P1_10MODE (Bit 20) */ +#define PINCONNECT_PINMODE2_P1_10MODE_Msk (0x300000UL) /*!< P1_10MODE (Bitfield-Mask: 0x03) */ +#define PINCONNECT_PINMODE2_P1_14MODE_Pos (28UL) /*!< P1_14MODE (Bit 28) */ +#define PINCONNECT_PINMODE2_P1_14MODE_Msk (0x30000000UL) /*!< P1_14MODE (Bitfield-Mask: 0x03) */ +#define PINCONNECT_PINMODE2_P1_15MODE_Pos (30UL) /*!< P1_15MODE (Bit 30) */ +#define PINCONNECT_PINMODE2_P1_15MODE_Msk (0xc0000000UL) /*!< P1_15MODE (Bitfield-Mask: 0x03) */ +/* ======================================================= PINMODE3 ======================================================== */ +#define PINCONNECT_PINMODE3_P1_16MODE_Pos (0UL) /*!< P1_16MODE (Bit 0) */ +#define PINCONNECT_PINMODE3_P1_16MODE_Msk (0x3UL) /*!< P1_16MODE (Bitfield-Mask: 0x03) */ +#define PINCONNECT_PINMODE3_P1_17MODE_Pos (2UL) /*!< P1_17MODE (Bit 2) */ +#define PINCONNECT_PINMODE3_P1_17MODE_Msk (0xcUL) /*!< P1_17MODE (Bitfield-Mask: 0x03) */ +#define PINCONNECT_PINMODE3_P1_18MODE_Pos (4UL) /*!< P1_18MODE (Bit 4) */ +#define PINCONNECT_PINMODE3_P1_18MODE_Msk (0x30UL) /*!< P1_18MODE (Bitfield-Mask: 0x03) */ +#define PINCONNECT_PINMODE3_P1_19MODE_Pos (6UL) /*!< P1_19MODE (Bit 6) */ +#define PINCONNECT_PINMODE3_P1_19MODE_Msk (0xc0UL) /*!< P1_19MODE (Bitfield-Mask: 0x03) */ +#define PINCONNECT_PINMODE3_P1_20MODE_Pos (8UL) /*!< P1_20MODE (Bit 8) */ +#define PINCONNECT_PINMODE3_P1_20MODE_Msk (0x300UL) /*!< P1_20MODE (Bitfield-Mask: 0x03) */ +#define PINCONNECT_PINMODE3_P1_21MODE_Pos (10UL) /*!< P1_21MODE (Bit 10) */ +#define PINCONNECT_PINMODE3_P1_21MODE_Msk (0xc00UL) /*!< P1_21MODE (Bitfield-Mask: 0x03) */ +#define PINCONNECT_PINMODE3_P1_22MODE_Pos (12UL) /*!< P1_22MODE (Bit 12) */ +#define PINCONNECT_PINMODE3_P1_22MODE_Msk (0x3000UL) /*!< P1_22MODE (Bitfield-Mask: 0x03) */ +#define PINCONNECT_PINMODE3_P1_23MODE_Pos (14UL) /*!< P1_23MODE (Bit 14) */ +#define PINCONNECT_PINMODE3_P1_23MODE_Msk (0xc000UL) /*!< P1_23MODE (Bitfield-Mask: 0x03) */ +#define PINCONNECT_PINMODE3_P1_24MODE_Pos (16UL) /*!< P1_24MODE (Bit 16) */ +#define PINCONNECT_PINMODE3_P1_24MODE_Msk (0x30000UL) /*!< P1_24MODE (Bitfield-Mask: 0x03) */ +#define PINCONNECT_PINMODE3_P1_25MODE_Pos (18UL) /*!< P1_25MODE (Bit 18) */ +#define PINCONNECT_PINMODE3_P1_25MODE_Msk (0xc0000UL) /*!< P1_25MODE (Bitfield-Mask: 0x03) */ +#define PINCONNECT_PINMODE3_P1_26MODE_Pos (20UL) /*!< P1_26MODE (Bit 20) */ +#define PINCONNECT_PINMODE3_P1_26MODE_Msk (0x300000UL) /*!< P1_26MODE (Bitfield-Mask: 0x03) */ +#define PINCONNECT_PINMODE3_P1_27MODE_Pos (22UL) /*!< P1_27MODE (Bit 22) */ +#define PINCONNECT_PINMODE3_P1_27MODE_Msk (0xc00000UL) /*!< P1_27MODE (Bitfield-Mask: 0x03) */ +#define PINCONNECT_PINMODE3_P1_28MODE_Pos (24UL) /*!< P1_28MODE (Bit 24) */ +#define PINCONNECT_PINMODE3_P1_28MODE_Msk (0x3000000UL) /*!< P1_28MODE (Bitfield-Mask: 0x03) */ +#define PINCONNECT_PINMODE3_P1_29MODE_Pos (26UL) /*!< P1_29MODE (Bit 26) */ +#define PINCONNECT_PINMODE3_P1_29MODE_Msk (0xc000000UL) /*!< P1_29MODE (Bitfield-Mask: 0x03) */ +#define PINCONNECT_PINMODE3_P1_30MODE_Pos (28UL) /*!< P1_30MODE (Bit 28) */ +#define PINCONNECT_PINMODE3_P1_30MODE_Msk (0x30000000UL) /*!< P1_30MODE (Bitfield-Mask: 0x03) */ +#define PINCONNECT_PINMODE3_P1_31MODE_Pos (30UL) /*!< P1_31MODE (Bit 30) */ +#define PINCONNECT_PINMODE3_P1_31MODE_Msk (0xc0000000UL) /*!< P1_31MODE (Bitfield-Mask: 0x03) */ +/* ======================================================= PINMODE4 ======================================================== */ +#define PINCONNECT_PINMODE4_P2_00MODE_Pos (0UL) /*!< P2_00MODE (Bit 0) */ +#define PINCONNECT_PINMODE4_P2_00MODE_Msk (0x3UL) /*!< P2_00MODE (Bitfield-Mask: 0x03) */ +#define PINCONNECT_PINMODE4_P2_01MODE_Pos (2UL) /*!< P2_01MODE (Bit 2) */ +#define PINCONNECT_PINMODE4_P2_01MODE_Msk (0xcUL) /*!< P2_01MODE (Bitfield-Mask: 0x03) */ +#define PINCONNECT_PINMODE4_P2_02MODE_Pos (4UL) /*!< P2_02MODE (Bit 4) */ +#define PINCONNECT_PINMODE4_P2_02MODE_Msk (0x30UL) /*!< P2_02MODE (Bitfield-Mask: 0x03) */ +#define PINCONNECT_PINMODE4_P2_03MODE_Pos (6UL) /*!< P2_03MODE (Bit 6) */ +#define PINCONNECT_PINMODE4_P2_03MODE_Msk (0xc0UL) /*!< P2_03MODE (Bitfield-Mask: 0x03) */ +#define PINCONNECT_PINMODE4_P2_04MODE_Pos (8UL) /*!< P2_04MODE (Bit 8) */ +#define PINCONNECT_PINMODE4_P2_04MODE_Msk (0x300UL) /*!< P2_04MODE (Bitfield-Mask: 0x03) */ +#define PINCONNECT_PINMODE4_P2_05MODE_Pos (10UL) /*!< P2_05MODE (Bit 10) */ +#define PINCONNECT_PINMODE4_P2_05MODE_Msk (0xc00UL) /*!< P2_05MODE (Bitfield-Mask: 0x03) */ +#define PINCONNECT_PINMODE4_P2_06MODE_Pos (12UL) /*!< P2_06MODE (Bit 12) */ +#define PINCONNECT_PINMODE4_P2_06MODE_Msk (0x3000UL) /*!< P2_06MODE (Bitfield-Mask: 0x03) */ +#define PINCONNECT_PINMODE4_P2_07MODE_Pos (14UL) /*!< P2_07MODE (Bit 14) */ +#define PINCONNECT_PINMODE4_P2_07MODE_Msk (0xc000UL) /*!< P2_07MODE (Bitfield-Mask: 0x03) */ +#define PINCONNECT_PINMODE4_P2_08MODE_Pos (16UL) /*!< P2_08MODE (Bit 16) */ +#define PINCONNECT_PINMODE4_P2_08MODE_Msk (0x30000UL) /*!< P2_08MODE (Bitfield-Mask: 0x03) */ +#define PINCONNECT_PINMODE4_P2_09MODE_Pos (18UL) /*!< P2_09MODE (Bit 18) */ +#define PINCONNECT_PINMODE4_P2_09MODE_Msk (0xc0000UL) /*!< P2_09MODE (Bitfield-Mask: 0x03) */ +#define PINCONNECT_PINMODE4_P2_10MODE_Pos (20UL) /*!< P2_10MODE (Bit 20) */ +#define PINCONNECT_PINMODE4_P2_10MODE_Msk (0x300000UL) /*!< P2_10MODE (Bitfield-Mask: 0x03) */ +#define PINCONNECT_PINMODE4_P2_11MODE_Pos (22UL) /*!< P2_11MODE (Bit 22) */ +#define PINCONNECT_PINMODE4_P2_11MODE_Msk (0xc00000UL) /*!< P2_11MODE (Bitfield-Mask: 0x03) */ +#define PINCONNECT_PINMODE4_P2_12MODE_Pos (24UL) /*!< P2_12MODE (Bit 24) */ +#define PINCONNECT_PINMODE4_P2_12MODE_Msk (0x3000000UL) /*!< P2_12MODE (Bitfield-Mask: 0x03) */ +#define PINCONNECT_PINMODE4_P2_13MODE_Pos (26UL) /*!< P2_13MODE (Bit 26) */ +#define PINCONNECT_PINMODE4_P2_13MODE_Msk (0xc000000UL) /*!< P2_13MODE (Bitfield-Mask: 0x03) */ +/* ======================================================= PINMODE7 ======================================================== */ +#define PINCONNECT_PINMODE7_P3_25MODE_Pos (18UL) /*!< P3_25MODE (Bit 18) */ +#define PINCONNECT_PINMODE7_P3_25MODE_Msk (0xc0000UL) /*!< P3_25MODE (Bitfield-Mask: 0x03) */ +#define PINCONNECT_PINMODE7_P3_26MODE_Pos (20UL) /*!< P3_26MODE (Bit 20) */ +#define PINCONNECT_PINMODE7_P3_26MODE_Msk (0x300000UL) /*!< P3_26MODE (Bitfield-Mask: 0x03) */ +/* ======================================================= PINMODE9 ======================================================== */ +#define PINCONNECT_PINMODE9_P4_28MODE_Pos (24UL) /*!< P4_28MODE (Bit 24) */ +#define PINCONNECT_PINMODE9_P4_28MODE_Msk (0x3000000UL) /*!< P4_28MODE (Bitfield-Mask: 0x03) */ +#define PINCONNECT_PINMODE9_P4_29MODE_Pos (26UL) /*!< P4_29MODE (Bit 26) */ +#define PINCONNECT_PINMODE9_P4_29MODE_Msk (0xc000000UL) /*!< P4_29MODE (Bitfield-Mask: 0x03) */ +/* ====================================================== PINMODE_OD0 ====================================================== */ +#define PINCONNECT_PINMODE_OD0_P0_00OD_Pos (0UL) /*!< P0_00OD (Bit 0) */ +#define PINCONNECT_PINMODE_OD0_P0_00OD_Msk (0x1UL) /*!< P0_00OD (Bitfield-Mask: 0x01) */ +#define PINCONNECT_PINMODE_OD0_P0_01OD_Pos (1UL) /*!< P0_01OD (Bit 1) */ +#define PINCONNECT_PINMODE_OD0_P0_01OD_Msk (0x2UL) /*!< P0_01OD (Bitfield-Mask: 0x01) */ +#define PINCONNECT_PINMODE_OD0_P0_02OD_Pos (2UL) /*!< P0_02OD (Bit 2) */ +#define PINCONNECT_PINMODE_OD0_P0_02OD_Msk (0x4UL) /*!< P0_02OD (Bitfield-Mask: 0x01) */ +#define PINCONNECT_PINMODE_OD0_P0_03OD_Pos (3UL) /*!< P0_03OD (Bit 3) */ +#define PINCONNECT_PINMODE_OD0_P0_03OD_Msk (0x8UL) /*!< P0_03OD (Bitfield-Mask: 0x01) */ +#define PINCONNECT_PINMODE_OD0_P0_04OD_Pos (4UL) /*!< P0_04OD (Bit 4) */ +#define PINCONNECT_PINMODE_OD0_P0_04OD_Msk (0x10UL) /*!< P0_04OD (Bitfield-Mask: 0x01) */ +#define PINCONNECT_PINMODE_OD0_P0_05OD_Pos (5UL) /*!< P0_05OD (Bit 5) */ +#define PINCONNECT_PINMODE_OD0_P0_05OD_Msk (0x20UL) /*!< P0_05OD (Bitfield-Mask: 0x01) */ +#define PINCONNECT_PINMODE_OD0_P0_06OD_Pos (6UL) /*!< P0_06OD (Bit 6) */ +#define PINCONNECT_PINMODE_OD0_P0_06OD_Msk (0x40UL) /*!< P0_06OD (Bitfield-Mask: 0x01) */ +#define PINCONNECT_PINMODE_OD0_P0_07OD_Pos (7UL) /*!< P0_07OD (Bit 7) */ +#define PINCONNECT_PINMODE_OD0_P0_07OD_Msk (0x80UL) /*!< P0_07OD (Bitfield-Mask: 0x01) */ +#define PINCONNECT_PINMODE_OD0_P0_08OD_Pos (8UL) /*!< P0_08OD (Bit 8) */ +#define PINCONNECT_PINMODE_OD0_P0_08OD_Msk (0x100UL) /*!< P0_08OD (Bitfield-Mask: 0x01) */ +#define PINCONNECT_PINMODE_OD0_P0_09OD_Pos (9UL) /*!< P0_09OD (Bit 9) */ +#define PINCONNECT_PINMODE_OD0_P0_09OD_Msk (0x200UL) /*!< P0_09OD (Bitfield-Mask: 0x01) */ +#define PINCONNECT_PINMODE_OD0_P0_10OD_Pos (10UL) /*!< P0_10OD (Bit 10) */ +#define PINCONNECT_PINMODE_OD0_P0_10OD_Msk (0x400UL) /*!< P0_10OD (Bitfield-Mask: 0x01) */ +#define PINCONNECT_PINMODE_OD0_P0_11OD_Pos (11UL) /*!< P0_11OD (Bit 11) */ +#define PINCONNECT_PINMODE_OD0_P0_11OD_Msk (0x800UL) /*!< P0_11OD (Bitfield-Mask: 0x01) */ +#define PINCONNECT_PINMODE_OD0_P0_15OD_Pos (15UL) /*!< P0_15OD (Bit 15) */ +#define PINCONNECT_PINMODE_OD0_P0_15OD_Msk (0x8000UL) /*!< P0_15OD (Bitfield-Mask: 0x01) */ +#define PINCONNECT_PINMODE_OD0_P0_16OD_Pos (16UL) /*!< P0_16OD (Bit 16) */ +#define PINCONNECT_PINMODE_OD0_P0_16OD_Msk (0x10000UL) /*!< P0_16OD (Bitfield-Mask: 0x01) */ +#define PINCONNECT_PINMODE_OD0_P0_17OD_Pos (17UL) /*!< P0_17OD (Bit 17) */ +#define PINCONNECT_PINMODE_OD0_P0_17OD_Msk (0x20000UL) /*!< P0_17OD (Bitfield-Mask: 0x01) */ +#define PINCONNECT_PINMODE_OD0_P0_18OD_Pos (18UL) /*!< P0_18OD (Bit 18) */ +#define PINCONNECT_PINMODE_OD0_P0_18OD_Msk (0x40000UL) /*!< P0_18OD (Bitfield-Mask: 0x01) */ +#define PINCONNECT_PINMODE_OD0_P0_19OD_Pos (19UL) /*!< P0_19OD (Bit 19) */ +#define PINCONNECT_PINMODE_OD0_P0_19OD_Msk (0x80000UL) /*!< P0_19OD (Bitfield-Mask: 0x01) */ +#define PINCONNECT_PINMODE_OD0_P0_20OD_Pos (20UL) /*!< P0_20OD (Bit 20) */ +#define PINCONNECT_PINMODE_OD0_P0_20OD_Msk (0x100000UL) /*!< P0_20OD (Bitfield-Mask: 0x01) */ +#define PINCONNECT_PINMODE_OD0_P0_21OD_Pos (21UL) /*!< P0_21OD (Bit 21) */ +#define PINCONNECT_PINMODE_OD0_P0_21OD_Msk (0x200000UL) /*!< P0_21OD (Bitfield-Mask: 0x01) */ +#define PINCONNECT_PINMODE_OD0_P0_22OD_Pos (22UL) /*!< P0_22OD (Bit 22) */ +#define PINCONNECT_PINMODE_OD0_P0_22OD_Msk (0x400000UL) /*!< P0_22OD (Bitfield-Mask: 0x01) */ +#define PINCONNECT_PINMODE_OD0_P0_23OD_Pos (23UL) /*!< P0_23OD (Bit 23) */ +#define PINCONNECT_PINMODE_OD0_P0_23OD_Msk (0x800000UL) /*!< P0_23OD (Bitfield-Mask: 0x01) */ +#define PINCONNECT_PINMODE_OD0_P0_24OD_Pos (24UL) /*!< P0_24OD (Bit 24) */ +#define PINCONNECT_PINMODE_OD0_P0_24OD_Msk (0x1000000UL) /*!< P0_24OD (Bitfield-Mask: 0x01) */ +#define PINCONNECT_PINMODE_OD0_P0_25OD_Pos (25UL) /*!< P0_25OD (Bit 25) */ +#define PINCONNECT_PINMODE_OD0_P0_25OD_Msk (0x2000000UL) /*!< P0_25OD (Bitfield-Mask: 0x01) */ +#define PINCONNECT_PINMODE_OD0_P0_26OD_Pos (26UL) /*!< P0_26OD (Bit 26) */ +#define PINCONNECT_PINMODE_OD0_P0_26OD_Msk (0x4000000UL) /*!< P0_26OD (Bitfield-Mask: 0x01) */ +#define PINCONNECT_PINMODE_OD0_P0_29OD_Pos (29UL) /*!< P0_29OD (Bit 29) */ +#define PINCONNECT_PINMODE_OD0_P0_29OD_Msk (0x20000000UL) /*!< P0_29OD (Bitfield-Mask: 0x01) */ +#define PINCONNECT_PINMODE_OD0_P0_30OD_Pos (30UL) /*!< P0_30OD (Bit 30) */ +#define PINCONNECT_PINMODE_OD0_P0_30OD_Msk (0x40000000UL) /*!< P0_30OD (Bitfield-Mask: 0x01) */ +/* ====================================================== PINMODE_OD1 ====================================================== */ +#define PINCONNECT_PINMODE_OD1_P1_00OD_Pos (0UL) /*!< P1_00OD (Bit 0) */ +#define PINCONNECT_PINMODE_OD1_P1_00OD_Msk (0x1UL) /*!< P1_00OD (Bitfield-Mask: 0x01) */ +#define PINCONNECT_PINMODE_OD1_P1_01OD_Pos (1UL) /*!< P1_01OD (Bit 1) */ +#define PINCONNECT_PINMODE_OD1_P1_01OD_Msk (0x2UL) /*!< P1_01OD (Bitfield-Mask: 0x01) */ +#define PINCONNECT_PINMODE_OD1_P1_04OD_Pos (4UL) /*!< P1_04OD (Bit 4) */ +#define PINCONNECT_PINMODE_OD1_P1_04OD_Msk (0x10UL) /*!< P1_04OD (Bitfield-Mask: 0x01) */ +#define PINCONNECT_PINMODE_OD1_P1_08OD_Pos (8UL) /*!< P1_08OD (Bit 8) */ +#define PINCONNECT_PINMODE_OD1_P1_08OD_Msk (0x100UL) /*!< P1_08OD (Bitfield-Mask: 0x01) */ +#define PINCONNECT_PINMODE_OD1_P1_09OD_Pos (9UL) /*!< P1_09OD (Bit 9) */ +#define PINCONNECT_PINMODE_OD1_P1_09OD_Msk (0x200UL) /*!< P1_09OD (Bitfield-Mask: 0x01) */ +#define PINCONNECT_PINMODE_OD1_P1_10OD_Pos (10UL) /*!< P1_10OD (Bit 10) */ +#define PINCONNECT_PINMODE_OD1_P1_10OD_Msk (0x400UL) /*!< P1_10OD (Bitfield-Mask: 0x01) */ +#define PINCONNECT_PINMODE_OD1_P1_14OD_Pos (14UL) /*!< P1_14OD (Bit 14) */ +#define PINCONNECT_PINMODE_OD1_P1_14OD_Msk (0x4000UL) /*!< P1_14OD (Bitfield-Mask: 0x01) */ +#define PINCONNECT_PINMODE_OD1_P1_15OD_Pos (15UL) /*!< P1_15OD (Bit 15) */ +#define PINCONNECT_PINMODE_OD1_P1_15OD_Msk (0x8000UL) /*!< P1_15OD (Bitfield-Mask: 0x01) */ +#define PINCONNECT_PINMODE_OD1_P1_16OD_Pos (16UL) /*!< P1_16OD (Bit 16) */ +#define PINCONNECT_PINMODE_OD1_P1_16OD_Msk (0x10000UL) /*!< P1_16OD (Bitfield-Mask: 0x01) */ +#define PINCONNECT_PINMODE_OD1_P1_17OD_Pos (17UL) /*!< P1_17OD (Bit 17) */ +#define PINCONNECT_PINMODE_OD1_P1_17OD_Msk (0x20000UL) /*!< P1_17OD (Bitfield-Mask: 0x01) */ +#define PINCONNECT_PINMODE_OD1_P1_18OD_Pos (18UL) /*!< P1_18OD (Bit 18) */ +#define PINCONNECT_PINMODE_OD1_P1_18OD_Msk (0x40000UL) /*!< P1_18OD (Bitfield-Mask: 0x01) */ +#define PINCONNECT_PINMODE_OD1_P1_19OD_Pos (19UL) /*!< P1_19OD (Bit 19) */ +#define PINCONNECT_PINMODE_OD1_P1_19OD_Msk (0x80000UL) /*!< P1_19OD (Bitfield-Mask: 0x01) */ +#define PINCONNECT_PINMODE_OD1_P1_20OD_Pos (20UL) /*!< P1_20OD (Bit 20) */ +#define PINCONNECT_PINMODE_OD1_P1_20OD_Msk (0x100000UL) /*!< P1_20OD (Bitfield-Mask: 0x01) */ +#define PINCONNECT_PINMODE_OD1_P1_21OD_Pos (21UL) /*!< P1_21OD (Bit 21) */ +#define PINCONNECT_PINMODE_OD1_P1_21OD_Msk (0x200000UL) /*!< P1_21OD (Bitfield-Mask: 0x01) */ +#define PINCONNECT_PINMODE_OD1_P1_22OD_Pos (22UL) /*!< P1_22OD (Bit 22) */ +#define PINCONNECT_PINMODE_OD1_P1_22OD_Msk (0x400000UL) /*!< P1_22OD (Bitfield-Mask: 0x01) */ +#define PINCONNECT_PINMODE_OD1_P1_23OD_Pos (23UL) /*!< P1_23OD (Bit 23) */ +#define PINCONNECT_PINMODE_OD1_P1_23OD_Msk (0x800000UL) /*!< P1_23OD (Bitfield-Mask: 0x01) */ +#define PINCONNECT_PINMODE_OD1_P1_24OD_Pos (24UL) /*!< P1_24OD (Bit 24) */ +#define PINCONNECT_PINMODE_OD1_P1_24OD_Msk (0x1000000UL) /*!< P1_24OD (Bitfield-Mask: 0x01) */ +#define PINCONNECT_PINMODE_OD1_P1_25OD_Pos (25UL) /*!< P1_25OD (Bit 25) */ +#define PINCONNECT_PINMODE_OD1_P1_25OD_Msk (0x2000000UL) /*!< P1_25OD (Bitfield-Mask: 0x01) */ +#define PINCONNECT_PINMODE_OD1_P1_26OD_Pos (26UL) /*!< P1_26OD (Bit 26) */ +#define PINCONNECT_PINMODE_OD1_P1_26OD_Msk (0x4000000UL) /*!< P1_26OD (Bitfield-Mask: 0x01) */ +#define PINCONNECT_PINMODE_OD1_P1_27OD_Pos (27UL) /*!< P1_27OD (Bit 27) */ +#define PINCONNECT_PINMODE_OD1_P1_27OD_Msk (0x8000000UL) /*!< P1_27OD (Bitfield-Mask: 0x01) */ +#define PINCONNECT_PINMODE_OD1_P1_28OD_Pos (28UL) /*!< P1_28OD (Bit 28) */ +#define PINCONNECT_PINMODE_OD1_P1_28OD_Msk (0x10000000UL) /*!< P1_28OD (Bitfield-Mask: 0x01) */ +#define PINCONNECT_PINMODE_OD1_P1_29OD_Pos (29UL) /*!< P1_29OD (Bit 29) */ +#define PINCONNECT_PINMODE_OD1_P1_29OD_Msk (0x20000000UL) /*!< P1_29OD (Bitfield-Mask: 0x01) */ +#define PINCONNECT_PINMODE_OD1_P1_30OD_Pos (30UL) /*!< P1_30OD (Bit 30) */ +#define PINCONNECT_PINMODE_OD1_P1_30OD_Msk (0x40000000UL) /*!< P1_30OD (Bitfield-Mask: 0x01) */ +#define PINCONNECT_PINMODE_OD1_P1_31OD_Pos (31UL) /*!< P1_31OD (Bit 31) */ +#define PINCONNECT_PINMODE_OD1_P1_31OD_Msk (0x80000000UL) /*!< P1_31OD (Bitfield-Mask: 0x01) */ +/* ====================================================== PINMODE_OD2 ====================================================== */ +#define PINCONNECT_PINMODE_OD2_P2_00OD_Pos (0UL) /*!< P2_00OD (Bit 0) */ +#define PINCONNECT_PINMODE_OD2_P2_00OD_Msk (0x1UL) /*!< P2_00OD (Bitfield-Mask: 0x01) */ +#define PINCONNECT_PINMODE_OD2_P2_01OD_Pos (1UL) /*!< P2_01OD (Bit 1) */ +#define PINCONNECT_PINMODE_OD2_P2_01OD_Msk (0x2UL) /*!< P2_01OD (Bitfield-Mask: 0x01) */ +#define PINCONNECT_PINMODE_OD2_P2_02OD_Pos (2UL) /*!< P2_02OD (Bit 2) */ +#define PINCONNECT_PINMODE_OD2_P2_02OD_Msk (0x4UL) /*!< P2_02OD (Bitfield-Mask: 0x01) */ +#define PINCONNECT_PINMODE_OD2_P2_03OD_Pos (3UL) /*!< P2_03OD (Bit 3) */ +#define PINCONNECT_PINMODE_OD2_P2_03OD_Msk (0x8UL) /*!< P2_03OD (Bitfield-Mask: 0x01) */ +#define PINCONNECT_PINMODE_OD2_P2_04OD_Pos (4UL) /*!< P2_04OD (Bit 4) */ +#define PINCONNECT_PINMODE_OD2_P2_04OD_Msk (0x10UL) /*!< P2_04OD (Bitfield-Mask: 0x01) */ +#define PINCONNECT_PINMODE_OD2_P2_05OD_Pos (5UL) /*!< P2_05OD (Bit 5) */ +#define PINCONNECT_PINMODE_OD2_P2_05OD_Msk (0x20UL) /*!< P2_05OD (Bitfield-Mask: 0x01) */ +#define PINCONNECT_PINMODE_OD2_P2_06OD_Pos (6UL) /*!< P2_06OD (Bit 6) */ +#define PINCONNECT_PINMODE_OD2_P2_06OD_Msk (0x40UL) /*!< P2_06OD (Bitfield-Mask: 0x01) */ +#define PINCONNECT_PINMODE_OD2_P2_07OD_Pos (7UL) /*!< P2_07OD (Bit 7) */ +#define PINCONNECT_PINMODE_OD2_P2_07OD_Msk (0x80UL) /*!< P2_07OD (Bitfield-Mask: 0x01) */ +#define PINCONNECT_PINMODE_OD2_P2_08OD_Pos (8UL) /*!< P2_08OD (Bit 8) */ +#define PINCONNECT_PINMODE_OD2_P2_08OD_Msk (0x100UL) /*!< P2_08OD (Bitfield-Mask: 0x01) */ +#define PINCONNECT_PINMODE_OD2_P2_09OD_Pos (9UL) /*!< P2_09OD (Bit 9) */ +#define PINCONNECT_PINMODE_OD2_P2_09OD_Msk (0x200UL) /*!< P2_09OD (Bitfield-Mask: 0x01) */ +#define PINCONNECT_PINMODE_OD2_P2_10OD_Pos (10UL) /*!< P2_10OD (Bit 10) */ +#define PINCONNECT_PINMODE_OD2_P2_10OD_Msk (0x400UL) /*!< P2_10OD (Bitfield-Mask: 0x01) */ +#define PINCONNECT_PINMODE_OD2_P2_11OD_Pos (11UL) /*!< P2_11OD (Bit 11) */ +#define PINCONNECT_PINMODE_OD2_P2_11OD_Msk (0x800UL) /*!< P2_11OD (Bitfield-Mask: 0x01) */ +#define PINCONNECT_PINMODE_OD2_P2_12OD_Pos (12UL) /*!< P2_12OD (Bit 12) */ +#define PINCONNECT_PINMODE_OD2_P2_12OD_Msk (0x1000UL) /*!< P2_12OD (Bitfield-Mask: 0x01) */ +#define PINCONNECT_PINMODE_OD2_P2_13OD_Pos (13UL) /*!< P2_13OD (Bit 13) */ +#define PINCONNECT_PINMODE_OD2_P2_13OD_Msk (0x2000UL) /*!< P2_13OD (Bitfield-Mask: 0x01) */ +/* ====================================================== PINMODE_OD3 ====================================================== */ +#define PINCONNECT_PINMODE_OD3_P3_25OD_Pos (25UL) /*!< P3_25OD (Bit 25) */ +#define PINCONNECT_PINMODE_OD3_P3_25OD_Msk (0x2000000UL) /*!< P3_25OD (Bitfield-Mask: 0x01) */ +#define PINCONNECT_PINMODE_OD3_P3_26OD_Pos (26UL) /*!< P3_26OD (Bit 26) */ +#define PINCONNECT_PINMODE_OD3_P3_26OD_Msk (0x4000000UL) /*!< P3_26OD (Bitfield-Mask: 0x01) */ +/* ====================================================== PINMODE_OD4 ====================================================== */ +#define PINCONNECT_PINMODE_OD4_P4_28OD_Pos (28UL) /*!< P4_28OD (Bit 28) */ +#define PINCONNECT_PINMODE_OD4_P4_28OD_Msk (0x10000000UL) /*!< P4_28OD (Bitfield-Mask: 0x01) */ +#define PINCONNECT_PINMODE_OD4_P4_29OD_Pos (29UL) /*!< P4_29OD (Bit 29) */ +#define PINCONNECT_PINMODE_OD4_P4_29OD_Msk (0x20000000UL) /*!< P4_29OD (Bitfield-Mask: 0x01) */ +/* ======================================================= I2CPADCFG ======================================================= */ +#define PINCONNECT_I2CPADCFG_SDADRV0_Pos (0UL) /*!< SDADRV0 (Bit 0) */ +#define PINCONNECT_I2CPADCFG_SDADRV0_Msk (0x1UL) /*!< SDADRV0 (Bitfield-Mask: 0x01) */ +#define PINCONNECT_I2CPADCFG_SDAI2C0_Pos (1UL) /*!< SDAI2C0 (Bit 1) */ +#define PINCONNECT_I2CPADCFG_SDAI2C0_Msk (0x2UL) /*!< SDAI2C0 (Bitfield-Mask: 0x01) */ +#define PINCONNECT_I2CPADCFG_SCLDRV0_Pos (2UL) /*!< SCLDRV0 (Bit 2) */ +#define PINCONNECT_I2CPADCFG_SCLDRV0_Msk (0x4UL) /*!< SCLDRV0 (Bitfield-Mask: 0x01) */ +#define PINCONNECT_I2CPADCFG_SCLI2C0_Pos (3UL) /*!< SCLI2C0 (Bit 3) */ +#define PINCONNECT_I2CPADCFG_SCLI2C0_Msk (0x8UL) /*!< SCLI2C0 (Bitfield-Mask: 0x01) */ + + +/* =========================================================================================================================== */ +/* ================ LPC_SSP1 ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== CR0 ========================================================== */ +#define SSP1_CR0_DSS_Pos (0UL) /*!< DSS (Bit 0) */ +#define SSP1_CR0_DSS_Msk (0xfUL) /*!< DSS (Bitfield-Mask: 0x0f) */ +#define SSP1_CR0_FRF_Pos (4UL) /*!< FRF (Bit 4) */ +#define SSP1_CR0_FRF_Msk (0x30UL) /*!< FRF (Bitfield-Mask: 0x03) */ +#define SSP1_CR0_CPOL_Pos (6UL) /*!< CPOL (Bit 6) */ +#define SSP1_CR0_CPOL_Msk (0x40UL) /*!< CPOL (Bitfield-Mask: 0x01) */ +#define SSP1_CR0_CPHA_Pos (7UL) /*!< CPHA (Bit 7) */ +#define SSP1_CR0_CPHA_Msk (0x80UL) /*!< CPHA (Bitfield-Mask: 0x01) */ +#define SSP1_CR0_SCR_Pos (8UL) /*!< SCR (Bit 8) */ +#define SSP1_CR0_SCR_Msk (0xff00UL) /*!< SCR (Bitfield-Mask: 0xff) */ +/* ========================================================== CR1 ========================================================== */ +#define SSP1_CR1_LBM_Pos (0UL) /*!< LBM (Bit 0) */ +#define SSP1_CR1_LBM_Msk (0x1UL) /*!< LBM (Bitfield-Mask: 0x01) */ +#define SSP1_CR1_SSE_Pos (1UL) /*!< SSE (Bit 1) */ +#define SSP1_CR1_SSE_Msk (0x2UL) /*!< SSE (Bitfield-Mask: 0x01) */ +#define SSP1_CR1_MS_Pos (2UL) /*!< MS (Bit 2) */ +#define SSP1_CR1_MS_Msk (0x4UL) /*!< MS (Bitfield-Mask: 0x01) */ +#define SSP1_CR1_SOD_Pos (3UL) /*!< SOD (Bit 3) */ +#define SSP1_CR1_SOD_Msk (0x8UL) /*!< SOD (Bitfield-Mask: 0x01) */ +/* ========================================================== DR =========================================================== */ +#define SSP1_DR_DATA_Pos (0UL) /*!< DATA (Bit 0) */ +#define SSP1_DR_DATA_Msk (0xffffUL) /*!< DATA (Bitfield-Mask: 0xffff) */ +/* ========================================================== SR =========================================================== */ +#define SSP1_SR_TFE_Pos (0UL) /*!< TFE (Bit 0) */ +#define SSP1_SR_TFE_Msk (0x1UL) /*!< TFE (Bitfield-Mask: 0x01) */ +#define SSP1_SR_TNF_Pos (1UL) /*!< TNF (Bit 1) */ +#define SSP1_SR_TNF_Msk (0x2UL) /*!< TNF (Bitfield-Mask: 0x01) */ +#define SSP1_SR_RNE_Pos (2UL) /*!< RNE (Bit 2) */ +#define SSP1_SR_RNE_Msk (0x4UL) /*!< RNE (Bitfield-Mask: 0x01) */ +#define SSP1_SR_RFF_Pos (3UL) /*!< RFF (Bit 3) */ +#define SSP1_SR_RFF_Msk (0x8UL) /*!< RFF (Bitfield-Mask: 0x01) */ +#define SSP1_SR_BSY_Pos (4UL) /*!< BSY (Bit 4) */ +#define SSP1_SR_BSY_Msk (0x10UL) /*!< BSY (Bitfield-Mask: 0x01) */ +/* ========================================================= CPSR ========================================================== */ +#define SSP1_CPSR_CPSDVSR_Pos (0UL) /*!< CPSDVSR (Bit 0) */ +#define SSP1_CPSR_CPSDVSR_Msk (0xffUL) /*!< CPSDVSR (Bitfield-Mask: 0xff) */ +/* ========================================================= IMSC ========================================================== */ +#define SSP1_IMSC_RORIM_Pos (0UL) /*!< RORIM (Bit 0) */ +#define SSP1_IMSC_RORIM_Msk (0x1UL) /*!< RORIM (Bitfield-Mask: 0x01) */ +#define SSP1_IMSC_RTIM_Pos (1UL) /*!< RTIM (Bit 1) */ +#define SSP1_IMSC_RTIM_Msk (0x2UL) /*!< RTIM (Bitfield-Mask: 0x01) */ +#define SSP1_IMSC_RXIM_Pos (2UL) /*!< RXIM (Bit 2) */ +#define SSP1_IMSC_RXIM_Msk (0x4UL) /*!< RXIM (Bitfield-Mask: 0x01) */ +#define SSP1_IMSC_TXIM_Pos (3UL) /*!< TXIM (Bit 3) */ +#define SSP1_IMSC_TXIM_Msk (0x8UL) /*!< TXIM (Bitfield-Mask: 0x01) */ +/* ========================================================== RIS ========================================================== */ +#define SSP1_RIS_RORRIS_Pos (0UL) /*!< RORRIS (Bit 0) */ +#define SSP1_RIS_RORRIS_Msk (0x1UL) /*!< RORRIS (Bitfield-Mask: 0x01) */ +#define SSP1_RIS_RTRIS_Pos (1UL) /*!< RTRIS (Bit 1) */ +#define SSP1_RIS_RTRIS_Msk (0x2UL) /*!< RTRIS (Bitfield-Mask: 0x01) */ +#define SSP1_RIS_RXRIS_Pos (2UL) /*!< RXRIS (Bit 2) */ +#define SSP1_RIS_RXRIS_Msk (0x4UL) /*!< RXRIS (Bitfield-Mask: 0x01) */ +#define SSP1_RIS_TXRIS_Pos (3UL) /*!< TXRIS (Bit 3) */ +#define SSP1_RIS_TXRIS_Msk (0x8UL) /*!< TXRIS (Bitfield-Mask: 0x01) */ +/* ========================================================== MIS ========================================================== */ +#define SSP1_MIS_RORMIS_Pos (0UL) /*!< RORMIS (Bit 0) */ +#define SSP1_MIS_RORMIS_Msk (0x1UL) /*!< RORMIS (Bitfield-Mask: 0x01) */ +#define SSP1_MIS_RTMIS_Pos (1UL) /*!< RTMIS (Bit 1) */ +#define SSP1_MIS_RTMIS_Msk (0x2UL) /*!< RTMIS (Bitfield-Mask: 0x01) */ +#define SSP1_MIS_RXMIS_Pos (2UL) /*!< RXMIS (Bit 2) */ +#define SSP1_MIS_RXMIS_Msk (0x4UL) /*!< RXMIS (Bitfield-Mask: 0x01) */ +#define SSP1_MIS_TXMIS_Pos (3UL) /*!< TXMIS (Bit 3) */ +#define SSP1_MIS_TXMIS_Msk (0x8UL) /*!< TXMIS (Bitfield-Mask: 0x01) */ +/* ========================================================== ICR ========================================================== */ +#define SSP1_ICR_RORIC_Pos (0UL) /*!< RORIC (Bit 0) */ +#define SSP1_ICR_RORIC_Msk (0x1UL) /*!< RORIC (Bitfield-Mask: 0x01) */ +#define SSP1_ICR_RTIC_Pos (1UL) /*!< RTIC (Bit 1) */ +#define SSP1_ICR_RTIC_Msk (0x2UL) /*!< RTIC (Bitfield-Mask: 0x01) */ +/* ========================================================= DMACR ========================================================= */ +#define SSP1_DMACR_RXDMAE_Pos (0UL) /*!< RXDMAE (Bit 0) */ +#define SSP1_DMACR_RXDMAE_Msk (0x1UL) /*!< RXDMAE (Bitfield-Mask: 0x01) */ +#define SSP1_DMACR_TXDMAE_Pos (1UL) /*!< TXDMAE (Bit 1) */ +#define SSP1_DMACR_TXDMAE_Msk (0x2UL) /*!< TXDMAE (Bitfield-Mask: 0x01) */ + + +/* =========================================================================================================================== */ +/* ================ LPC_ADC ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== CR =========================================================== */ +#define ADC_CR_SEL_Pos (0UL) /*!< SEL (Bit 0) */ +#define ADC_CR_SEL_Msk (0xffUL) /*!< SEL (Bitfield-Mask: 0xff) */ +#define ADC_CR_CLKDIV_Pos (8UL) /*!< CLKDIV (Bit 8) */ +#define ADC_CR_CLKDIV_Msk (0xff00UL) /*!< CLKDIV (Bitfield-Mask: 0xff) */ +#define ADC_CR_BURST_Pos (16UL) /*!< BURST (Bit 16) */ +#define ADC_CR_BURST_Msk (0x10000UL) /*!< BURST (Bitfield-Mask: 0x01) */ +#define ADC_CR_PDN_Pos (21UL) /*!< PDN (Bit 21) */ +#define ADC_CR_PDN_Msk (0x200000UL) /*!< PDN (Bitfield-Mask: 0x01) */ +#define ADC_CR_START_Pos (24UL) /*!< START (Bit 24) */ +#define ADC_CR_START_Msk (0x7000000UL) /*!< START (Bitfield-Mask: 0x07) */ +#define ADC_CR_EDGE_Pos (27UL) /*!< EDGE (Bit 27) */ +#define ADC_CR_EDGE_Msk (0x8000000UL) /*!< EDGE (Bitfield-Mask: 0x01) */ +/* ========================================================== GDR ========================================================== */ +#define ADC_GDR_RESULT_Pos (4UL) /*!< RESULT (Bit 4) */ +#define ADC_GDR_RESULT_Msk (0xfff0UL) /*!< RESULT (Bitfield-Mask: 0xfff) */ +#define ADC_GDR_CHN_Pos (24UL) /*!< CHN (Bit 24) */ +#define ADC_GDR_CHN_Msk (0x7000000UL) /*!< CHN (Bitfield-Mask: 0x07) */ +#define ADC_GDR_OVERRUN_Pos (30UL) /*!< OVERRUN (Bit 30) */ +#define ADC_GDR_OVERRUN_Msk (0x40000000UL) /*!< OVERRUN (Bitfield-Mask: 0x01) */ +#define ADC_GDR_DONE_Pos (31UL) /*!< DONE (Bit 31) */ +#define ADC_GDR_DONE_Msk (0x80000000UL) /*!< DONE (Bitfield-Mask: 0x01) */ +/* ========================================================= INTEN ========================================================= */ +#define ADC_INTEN_ADINTEN0_Pos (0UL) /*!< ADINTEN0 (Bit 0) */ +#define ADC_INTEN_ADINTEN0_Msk (0x1UL) /*!< ADINTEN0 (Bitfield-Mask: 0x01) */ +#define ADC_INTEN_ADINTEN1_Pos (1UL) /*!< ADINTEN1 (Bit 1) */ +#define ADC_INTEN_ADINTEN1_Msk (0x2UL) /*!< ADINTEN1 (Bitfield-Mask: 0x01) */ +#define ADC_INTEN_ADINTEN2_Pos (2UL) /*!< ADINTEN2 (Bit 2) */ +#define ADC_INTEN_ADINTEN2_Msk (0x4UL) /*!< ADINTEN2 (Bitfield-Mask: 0x01) */ +#define ADC_INTEN_ADINTEN3_Pos (3UL) /*!< ADINTEN3 (Bit 3) */ +#define ADC_INTEN_ADINTEN3_Msk (0x8UL) /*!< ADINTEN3 (Bitfield-Mask: 0x01) */ +#define ADC_INTEN_ADINTEN4_Pos (4UL) /*!< ADINTEN4 (Bit 4) */ +#define ADC_INTEN_ADINTEN4_Msk (0x10UL) /*!< ADINTEN4 (Bitfield-Mask: 0x01) */ +#define ADC_INTEN_ADINTEN5_Pos (5UL) /*!< ADINTEN5 (Bit 5) */ +#define ADC_INTEN_ADINTEN5_Msk (0x20UL) /*!< ADINTEN5 (Bitfield-Mask: 0x01) */ +#define ADC_INTEN_ADINTEN6_Pos (6UL) /*!< ADINTEN6 (Bit 6) */ +#define ADC_INTEN_ADINTEN6_Msk (0x40UL) /*!< ADINTEN6 (Bitfield-Mask: 0x01) */ +#define ADC_INTEN_ADINTEN7_Pos (7UL) /*!< ADINTEN7 (Bit 7) */ +#define ADC_INTEN_ADINTEN7_Msk (0x80UL) /*!< ADINTEN7 (Bitfield-Mask: 0x01) */ +#define ADC_INTEN_ADGINTEN_Pos (8UL) /*!< ADGINTEN (Bit 8) */ +#define ADC_INTEN_ADGINTEN_Msk (0x100UL) /*!< ADGINTEN (Bitfield-Mask: 0x01) */ +/* ========================================================= STAT ========================================================== */ +#define ADC_STAT_DONE0_Pos (0UL) /*!< DONE0 (Bit 0) */ +#define ADC_STAT_DONE0_Msk (0x1UL) /*!< DONE0 (Bitfield-Mask: 0x01) */ +#define ADC_STAT_DONE1_Pos (1UL) /*!< DONE1 (Bit 1) */ +#define ADC_STAT_DONE1_Msk (0x2UL) /*!< DONE1 (Bitfield-Mask: 0x01) */ +#define ADC_STAT_DONE2_Pos (2UL) /*!< DONE2 (Bit 2) */ +#define ADC_STAT_DONE2_Msk (0x4UL) /*!< DONE2 (Bitfield-Mask: 0x01) */ +#define ADC_STAT_DONE3_Pos (3UL) /*!< DONE3 (Bit 3) */ +#define ADC_STAT_DONE3_Msk (0x8UL) /*!< DONE3 (Bitfield-Mask: 0x01) */ +#define ADC_STAT_DONE4_Pos (4UL) /*!< DONE4 (Bit 4) */ +#define ADC_STAT_DONE4_Msk (0x10UL) /*!< DONE4 (Bitfield-Mask: 0x01) */ +#define ADC_STAT_DONE5_Pos (5UL) /*!< DONE5 (Bit 5) */ +#define ADC_STAT_DONE5_Msk (0x20UL) /*!< DONE5 (Bitfield-Mask: 0x01) */ +#define ADC_STAT_DONE6_Pos (6UL) /*!< DONE6 (Bit 6) */ +#define ADC_STAT_DONE6_Msk (0x40UL) /*!< DONE6 (Bitfield-Mask: 0x01) */ +#define ADC_STAT_DONE7_Pos (7UL) /*!< DONE7 (Bit 7) */ +#define ADC_STAT_DONE7_Msk (0x80UL) /*!< DONE7 (Bitfield-Mask: 0x01) */ +#define ADC_STAT_OVERRUN0_Pos (8UL) /*!< OVERRUN0 (Bit 8) */ +#define ADC_STAT_OVERRUN0_Msk (0x100UL) /*!< OVERRUN0 (Bitfield-Mask: 0x01) */ +#define ADC_STAT_OVERRUN1_Pos (9UL) /*!< OVERRUN1 (Bit 9) */ +#define ADC_STAT_OVERRUN1_Msk (0x200UL) /*!< OVERRUN1 (Bitfield-Mask: 0x01) */ +#define ADC_STAT_OVERRUN2_Pos (10UL) /*!< OVERRUN2 (Bit 10) */ +#define ADC_STAT_OVERRUN2_Msk (0x400UL) /*!< OVERRUN2 (Bitfield-Mask: 0x01) */ +#define ADC_STAT_OVERRUN3_Pos (11UL) /*!< OVERRUN3 (Bit 11) */ +#define ADC_STAT_OVERRUN3_Msk (0x800UL) /*!< OVERRUN3 (Bitfield-Mask: 0x01) */ +#define ADC_STAT_OVERRUN4_Pos (12UL) /*!< OVERRUN4 (Bit 12) */ +#define ADC_STAT_OVERRUN4_Msk (0x1000UL) /*!< OVERRUN4 (Bitfield-Mask: 0x01) */ +#define ADC_STAT_OVERRUN5_Pos (13UL) /*!< OVERRUN5 (Bit 13) */ +#define ADC_STAT_OVERRUN5_Msk (0x2000UL) /*!< OVERRUN5 (Bitfield-Mask: 0x01) */ +#define ADC_STAT_OVERRUN6_Pos (14UL) /*!< OVERRUN6 (Bit 14) */ +#define ADC_STAT_OVERRUN6_Msk (0x4000UL) /*!< OVERRUN6 (Bitfield-Mask: 0x01) */ +#define ADC_STAT_OVERRUN7_Pos (15UL) /*!< OVERRUN7 (Bit 15) */ +#define ADC_STAT_OVERRUN7_Msk (0x8000UL) /*!< OVERRUN7 (Bitfield-Mask: 0x01) */ +#define ADC_STAT_ADINT_Pos (16UL) /*!< ADINT (Bit 16) */ +#define ADC_STAT_ADINT_Msk (0x10000UL) /*!< ADINT (Bitfield-Mask: 0x01) */ +/* ========================================================== TRM ========================================================== */ +#define ADC_TRM_ADCOFFS_Pos (4UL) /*!< ADCOFFS (Bit 4) */ +#define ADC_TRM_ADCOFFS_Msk (0xf0UL) /*!< ADCOFFS (Bitfield-Mask: 0x0f) */ +#define ADC_TRM_TRIM_Pos (8UL) /*!< TRIM (Bit 8) */ +#define ADC_TRM_TRIM_Msk (0xf00UL) /*!< TRIM (Bitfield-Mask: 0x0f) */ + + +/* =========================================================================================================================== */ +/* ================ LPC_CANAFRAM ================ */ +/* =========================================================================================================================== */ + + + +/* =========================================================================================================================== */ +/* ================ LPC_CANAF ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= AFMR ========================================================== */ +#define CANAF_AFMR_ACCOFF_Pos (0UL) /*!< ACCOFF (Bit 0) */ +#define CANAF_AFMR_ACCOFF_Msk (0x1UL) /*!< ACCOFF (Bitfield-Mask: 0x01) */ +#define CANAF_AFMR_ACCBP_Pos (1UL) /*!< ACCBP (Bit 1) */ +#define CANAF_AFMR_ACCBP_Msk (0x2UL) /*!< ACCBP (Bitfield-Mask: 0x01) */ +#define CANAF_AFMR_EFCAN_Pos (2UL) /*!< EFCAN (Bit 2) */ +#define CANAF_AFMR_EFCAN_Msk (0x4UL) /*!< EFCAN (Bitfield-Mask: 0x01) */ +/* ======================================================== SFF_SA ========================================================= */ +#define CANAF_SFF_SA_SFF_SA_Pos (2UL) /*!< SFF_SA (Bit 2) */ +#define CANAF_SFF_SA_SFF_SA_Msk (0x7fcUL) /*!< SFF_SA (Bitfield-Mask: 0x1ff) */ +/* ====================================================== SFF_GRP_SA ======================================================= */ +#define CANAF_SFF_GRP_SA_SFF_GRP_SA_Pos (2UL) /*!< SFF_GRP_SA (Bit 2) */ +#define CANAF_SFF_GRP_SA_SFF_GRP_SA_Msk (0xffcUL) /*!< SFF_GRP_SA (Bitfield-Mask: 0x3ff) */ +/* ======================================================== EFF_SA ========================================================= */ +#define CANAF_EFF_SA_EFF_SA_Pos (2UL) /*!< EFF_SA (Bit 2) */ +#define CANAF_EFF_SA_EFF_SA_Msk (0x7fcUL) /*!< EFF_SA (Bitfield-Mask: 0x1ff) */ +/* ====================================================== EFF_GRP_SA ======================================================= */ +#define CANAF_EFF_GRP_SA_EFF_GRP_SA_Pos (2UL) /*!< EFF_GRP_SA (Bit 2) */ +#define CANAF_EFF_GRP_SA_EFF_GRP_SA_Msk (0xffcUL) /*!< EFF_GRP_SA (Bitfield-Mask: 0x3ff) */ +/* ====================================================== ENDOFTABLE ======================================================= */ +#define CANAF_ENDOFTABLE_ENDOFTABLE_Pos (2UL) /*!< ENDOFTABLE (Bit 2) */ +#define CANAF_ENDOFTABLE_ENDOFTABLE_Msk (0xffcUL) /*!< ENDOFTABLE (Bitfield-Mask: 0x3ff) */ +/* ======================================================= LUTERRAD ======================================================== */ +#define CANAF_LUTERRAD_LUTERRAD_Pos (2UL) /*!< LUTERRAD (Bit 2) */ +#define CANAF_LUTERRAD_LUTERRAD_Msk (0x7fcUL) /*!< LUTERRAD (Bitfield-Mask: 0x1ff) */ +/* ======================================================== LUTERR ========================================================= */ +#define CANAF_LUTERR_LUTERR_Pos (0UL) /*!< LUTERR (Bit 0) */ +#define CANAF_LUTERR_LUTERR_Msk (0x1UL) /*!< LUTERR (Bitfield-Mask: 0x01) */ +/* ======================================================== FCANIE ========================================================= */ +#define CANAF_FCANIE_FCANIE_Pos (0UL) /*!< FCANIE (Bit 0) */ +#define CANAF_FCANIE_FCANIE_Msk (0x1UL) /*!< FCANIE (Bitfield-Mask: 0x01) */ +/* ======================================================== FCANIC0 ======================================================== */ +#define CANAF_FCANIC0_INTPND_Pos (0UL) /*!< INTPND (Bit 0) */ +#define CANAF_FCANIC0_INTPND_Msk (0xffffffffUL) /*!< INTPND (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== FCANIC1 ======================================================== */ +#define CANAF_FCANIC1_IntPnd32_Pos (0UL) /*!< IntPnd32 (Bit 0) */ +#define CANAF_FCANIC1_IntPnd32_Msk (0xffffffffUL) /*!< IntPnd32 (Bitfield-Mask: 0xffffffff) */ + + +/* =========================================================================================================================== */ +/* ================ LPC_CCAN ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= TXSR ========================================================== */ +#define CCAN_TXSR_TS1_Pos (0UL) /*!< TS1 (Bit 0) */ +#define CCAN_TXSR_TS1_Msk (0x1UL) /*!< TS1 (Bitfield-Mask: 0x01) */ +#define CCAN_TXSR_TS2_Pos (1UL) /*!< TS2 (Bit 1) */ +#define CCAN_TXSR_TS2_Msk (0x2UL) /*!< TS2 (Bitfield-Mask: 0x01) */ +#define CCAN_TXSR_TBS1_Pos (8UL) /*!< TBS1 (Bit 8) */ +#define CCAN_TXSR_TBS1_Msk (0x100UL) /*!< TBS1 (Bitfield-Mask: 0x01) */ +#define CCAN_TXSR_TBS2_Pos (9UL) /*!< TBS2 (Bit 9) */ +#define CCAN_TXSR_TBS2_Msk (0x200UL) /*!< TBS2 (Bitfield-Mask: 0x01) */ +#define CCAN_TXSR_TCS1_Pos (16UL) /*!< TCS1 (Bit 16) */ +#define CCAN_TXSR_TCS1_Msk (0x10000UL) /*!< TCS1 (Bitfield-Mask: 0x01) */ +#define CCAN_TXSR_TCS2_Pos (17UL) /*!< TCS2 (Bit 17) */ +#define CCAN_TXSR_TCS2_Msk (0x20000UL) /*!< TCS2 (Bitfield-Mask: 0x01) */ +/* ========================================================= RXSR ========================================================== */ +#define CCAN_RXSR_RS1_Pos (0UL) /*!< RS1 (Bit 0) */ +#define CCAN_RXSR_RS1_Msk (0x1UL) /*!< RS1 (Bitfield-Mask: 0x01) */ +#define CCAN_RXSR_RS2_Pos (1UL) /*!< RS2 (Bit 1) */ +#define CCAN_RXSR_RS2_Msk (0x2UL) /*!< RS2 (Bitfield-Mask: 0x01) */ +#define CCAN_RXSR_RB1_Pos (8UL) /*!< RB1 (Bit 8) */ +#define CCAN_RXSR_RB1_Msk (0x100UL) /*!< RB1 (Bitfield-Mask: 0x01) */ +#define CCAN_RXSR_RB2_Pos (9UL) /*!< RB2 (Bit 9) */ +#define CCAN_RXSR_RB2_Msk (0x200UL) /*!< RB2 (Bitfield-Mask: 0x01) */ +#define CCAN_RXSR_DOS1_Pos (16UL) /*!< DOS1 (Bit 16) */ +#define CCAN_RXSR_DOS1_Msk (0x10000UL) /*!< DOS1 (Bitfield-Mask: 0x01) */ +#define CCAN_RXSR_DOS2_Pos (17UL) /*!< DOS2 (Bit 17) */ +#define CCAN_RXSR_DOS2_Msk (0x20000UL) /*!< DOS2 (Bitfield-Mask: 0x01) */ +/* ========================================================== MSR ========================================================== */ +#define CCAN_MSR_E1_Pos (0UL) /*!< E1 (Bit 0) */ +#define CCAN_MSR_E1_Msk (0x1UL) /*!< E1 (Bitfield-Mask: 0x01) */ +#define CCAN_MSR_E2_Pos (1UL) /*!< E2 (Bit 1) */ +#define CCAN_MSR_E2_Msk (0x2UL) /*!< E2 (Bitfield-Mask: 0x01) */ +#define CCAN_MSR_BS1_Pos (8UL) /*!< BS1 (Bit 8) */ +#define CCAN_MSR_BS1_Msk (0x100UL) /*!< BS1 (Bitfield-Mask: 0x01) */ +#define CCAN_MSR_BS2_Pos (9UL) /*!< BS2 (Bit 9) */ +#define CCAN_MSR_BS2_Msk (0x200UL) /*!< BS2 (Bitfield-Mask: 0x01) */ + + +/* =========================================================================================================================== */ +/* ================ LPC_CAN1 ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== MOD ========================================================== */ +#define CAN1_MOD_RM_Pos (0UL) /*!< RM (Bit 0) */ +#define CAN1_MOD_RM_Msk (0x1UL) /*!< RM (Bitfield-Mask: 0x01) */ +#define CAN1_MOD_LOM_Pos (1UL) /*!< LOM (Bit 1) */ +#define CAN1_MOD_LOM_Msk (0x2UL) /*!< LOM (Bitfield-Mask: 0x01) */ +#define CAN1_MOD_STM_Pos (2UL) /*!< STM (Bit 2) */ +#define CAN1_MOD_STM_Msk (0x4UL) /*!< STM (Bitfield-Mask: 0x01) */ +#define CAN1_MOD_TPM_Pos (3UL) /*!< TPM (Bit 3) */ +#define CAN1_MOD_TPM_Msk (0x8UL) /*!< TPM (Bitfield-Mask: 0x01) */ +#define CAN1_MOD_SM_Pos (4UL) /*!< SM (Bit 4) */ +#define CAN1_MOD_SM_Msk (0x10UL) /*!< SM (Bitfield-Mask: 0x01) */ +#define CAN1_MOD_RPM_Pos (5UL) /*!< RPM (Bit 5) */ +#define CAN1_MOD_RPM_Msk (0x20UL) /*!< RPM (Bitfield-Mask: 0x01) */ +#define CAN1_MOD_TM_Pos (7UL) /*!< TM (Bit 7) */ +#define CAN1_MOD_TM_Msk (0x80UL) /*!< TM (Bitfield-Mask: 0x01) */ +/* ========================================================== CMR ========================================================== */ +#define CAN1_CMR_TR_Pos (0UL) /*!< TR (Bit 0) */ +#define CAN1_CMR_TR_Msk (0x1UL) /*!< TR (Bitfield-Mask: 0x01) */ +#define CAN1_CMR_AT_Pos (1UL) /*!< AT (Bit 1) */ +#define CAN1_CMR_AT_Msk (0x2UL) /*!< AT (Bitfield-Mask: 0x01) */ +#define CAN1_CMR_RRB_Pos (2UL) /*!< RRB (Bit 2) */ +#define CAN1_CMR_RRB_Msk (0x4UL) /*!< RRB (Bitfield-Mask: 0x01) */ +#define CAN1_CMR_CDO_Pos (3UL) /*!< CDO (Bit 3) */ +#define CAN1_CMR_CDO_Msk (0x8UL) /*!< CDO (Bitfield-Mask: 0x01) */ +#define CAN1_CMR_SRR_Pos (4UL) /*!< SRR (Bit 4) */ +#define CAN1_CMR_SRR_Msk (0x10UL) /*!< SRR (Bitfield-Mask: 0x01) */ +#define CAN1_CMR_STB1_Pos (5UL) /*!< STB1 (Bit 5) */ +#define CAN1_CMR_STB1_Msk (0x20UL) /*!< STB1 (Bitfield-Mask: 0x01) */ +#define CAN1_CMR_STB2_Pos (6UL) /*!< STB2 (Bit 6) */ +#define CAN1_CMR_STB2_Msk (0x40UL) /*!< STB2 (Bitfield-Mask: 0x01) */ +#define CAN1_CMR_STB3_Pos (7UL) /*!< STB3 (Bit 7) */ +#define CAN1_CMR_STB3_Msk (0x80UL) /*!< STB3 (Bitfield-Mask: 0x01) */ +/* ========================================================== GSR ========================================================== */ +#define CAN1_GSR_RBS_Pos (0UL) /*!< RBS (Bit 0) */ +#define CAN1_GSR_RBS_Msk (0x1UL) /*!< RBS (Bitfield-Mask: 0x01) */ +#define CAN1_GSR_DOS_Pos (1UL) /*!< DOS (Bit 1) */ +#define CAN1_GSR_DOS_Msk (0x2UL) /*!< DOS (Bitfield-Mask: 0x01) */ +#define CAN1_GSR_TBS_Pos (2UL) /*!< TBS (Bit 2) */ +#define CAN1_GSR_TBS_Msk (0x4UL) /*!< TBS (Bitfield-Mask: 0x01) */ +#define CAN1_GSR_TCS_Pos (3UL) /*!< TCS (Bit 3) */ +#define CAN1_GSR_TCS_Msk (0x8UL) /*!< TCS (Bitfield-Mask: 0x01) */ +#define CAN1_GSR_RS_Pos (4UL) /*!< RS (Bit 4) */ +#define CAN1_GSR_RS_Msk (0x10UL) /*!< RS (Bitfield-Mask: 0x01) */ +#define CAN1_GSR_TS_Pos (5UL) /*!< TS (Bit 5) */ +#define CAN1_GSR_TS_Msk (0x20UL) /*!< TS (Bitfield-Mask: 0x01) */ +#define CAN1_GSR_ES_Pos (6UL) /*!< ES (Bit 6) */ +#define CAN1_GSR_ES_Msk (0x40UL) /*!< ES (Bitfield-Mask: 0x01) */ +#define CAN1_GSR_BS_Pos (7UL) /*!< BS (Bit 7) */ +#define CAN1_GSR_BS_Msk (0x80UL) /*!< BS (Bitfield-Mask: 0x01) */ +#define CAN1_GSR_RXERR_Pos (16UL) /*!< RXERR (Bit 16) */ +#define CAN1_GSR_RXERR_Msk (0xff0000UL) /*!< RXERR (Bitfield-Mask: 0xff) */ +#define CAN1_GSR_TXERR_Pos (24UL) /*!< TXERR (Bit 24) */ +#define CAN1_GSR_TXERR_Msk (0xff000000UL) /*!< TXERR (Bitfield-Mask: 0xff) */ +/* ========================================================== ICR ========================================================== */ +#define CAN1_ICR_RI_Pos (0UL) /*!< RI (Bit 0) */ +#define CAN1_ICR_RI_Msk (0x1UL) /*!< RI (Bitfield-Mask: 0x01) */ +#define CAN1_ICR_TI1_Pos (1UL) /*!< TI1 (Bit 1) */ +#define CAN1_ICR_TI1_Msk (0x2UL) /*!< TI1 (Bitfield-Mask: 0x01) */ +#define CAN1_ICR_EI_Pos (2UL) /*!< EI (Bit 2) */ +#define CAN1_ICR_EI_Msk (0x4UL) /*!< EI (Bitfield-Mask: 0x01) */ +#define CAN1_ICR_DOI_Pos (3UL) /*!< DOI (Bit 3) */ +#define CAN1_ICR_DOI_Msk (0x8UL) /*!< DOI (Bitfield-Mask: 0x01) */ +#define CAN1_ICR_WUI_Pos (4UL) /*!< WUI (Bit 4) */ +#define CAN1_ICR_WUI_Msk (0x10UL) /*!< WUI (Bitfield-Mask: 0x01) */ +#define CAN1_ICR_EPI_Pos (5UL) /*!< EPI (Bit 5) */ +#define CAN1_ICR_EPI_Msk (0x20UL) /*!< EPI (Bitfield-Mask: 0x01) */ +#define CAN1_ICR_ALI_Pos (6UL) /*!< ALI (Bit 6) */ +#define CAN1_ICR_ALI_Msk (0x40UL) /*!< ALI (Bitfield-Mask: 0x01) */ +#define CAN1_ICR_BEI_Pos (7UL) /*!< BEI (Bit 7) */ +#define CAN1_ICR_BEI_Msk (0x80UL) /*!< BEI (Bitfield-Mask: 0x01) */ +#define CAN1_ICR_IDI_Pos (8UL) /*!< IDI (Bit 8) */ +#define CAN1_ICR_IDI_Msk (0x100UL) /*!< IDI (Bitfield-Mask: 0x01) */ +#define CAN1_ICR_TI2_Pos (9UL) /*!< TI2 (Bit 9) */ +#define CAN1_ICR_TI2_Msk (0x200UL) /*!< TI2 (Bitfield-Mask: 0x01) */ +#define CAN1_ICR_TI3_Pos (10UL) /*!< TI3 (Bit 10) */ +#define CAN1_ICR_TI3_Msk (0x400UL) /*!< TI3 (Bitfield-Mask: 0x01) */ +#define CAN1_ICR_ERRBIT4_0_Pos (16UL) /*!< ERRBIT4_0 (Bit 16) */ +#define CAN1_ICR_ERRBIT4_0_Msk (0x1f0000UL) /*!< ERRBIT4_0 (Bitfield-Mask: 0x1f) */ +#define CAN1_ICR_ERRDIR_Pos (21UL) /*!< ERRDIR (Bit 21) */ +#define CAN1_ICR_ERRDIR_Msk (0x200000UL) /*!< ERRDIR (Bitfield-Mask: 0x01) */ +#define CAN1_ICR_ERRC1_0_Pos (22UL) /*!< ERRC1_0 (Bit 22) */ +#define CAN1_ICR_ERRC1_0_Msk (0xc00000UL) /*!< ERRC1_0 (Bitfield-Mask: 0x03) */ +#define CAN1_ICR_ALCBIT_Pos (24UL) /*!< ALCBIT (Bit 24) */ +#define CAN1_ICR_ALCBIT_Msk (0xff000000UL) /*!< ALCBIT (Bitfield-Mask: 0xff) */ +/* ========================================================== IER ========================================================== */ +#define CAN1_IER_RIE_Pos (0UL) /*!< RIE (Bit 0) */ +#define CAN1_IER_RIE_Msk (0x1UL) /*!< RIE (Bitfield-Mask: 0x01) */ +#define CAN1_IER_TIE1_Pos (1UL) /*!< TIE1 (Bit 1) */ +#define CAN1_IER_TIE1_Msk (0x2UL) /*!< TIE1 (Bitfield-Mask: 0x01) */ +#define CAN1_IER_EIE_Pos (2UL) /*!< EIE (Bit 2) */ +#define CAN1_IER_EIE_Msk (0x4UL) /*!< EIE (Bitfield-Mask: 0x01) */ +#define CAN1_IER_DOIE_Pos (3UL) /*!< DOIE (Bit 3) */ +#define CAN1_IER_DOIE_Msk (0x8UL) /*!< DOIE (Bitfield-Mask: 0x01) */ +#define CAN1_IER_WUIE_Pos (4UL) /*!< WUIE (Bit 4) */ +#define CAN1_IER_WUIE_Msk (0x10UL) /*!< WUIE (Bitfield-Mask: 0x01) */ +#define CAN1_IER_EPIE_Pos (5UL) /*!< EPIE (Bit 5) */ +#define CAN1_IER_EPIE_Msk (0x20UL) /*!< EPIE (Bitfield-Mask: 0x01) */ +#define CAN1_IER_ALIE_Pos (6UL) /*!< ALIE (Bit 6) */ +#define CAN1_IER_ALIE_Msk (0x40UL) /*!< ALIE (Bitfield-Mask: 0x01) */ +#define CAN1_IER_BEIE_Pos (7UL) /*!< BEIE (Bit 7) */ +#define CAN1_IER_BEIE_Msk (0x80UL) /*!< BEIE (Bitfield-Mask: 0x01) */ +#define CAN1_IER_IDIE_Pos (8UL) /*!< IDIE (Bit 8) */ +#define CAN1_IER_IDIE_Msk (0x100UL) /*!< IDIE (Bitfield-Mask: 0x01) */ +#define CAN1_IER_TIE2_Pos (9UL) /*!< TIE2 (Bit 9) */ +#define CAN1_IER_TIE2_Msk (0x200UL) /*!< TIE2 (Bitfield-Mask: 0x01) */ +#define CAN1_IER_TIE3_Pos (10UL) /*!< TIE3 (Bit 10) */ +#define CAN1_IER_TIE3_Msk (0x400UL) /*!< TIE3 (Bitfield-Mask: 0x01) */ +/* ========================================================== BTR ========================================================== */ +#define CAN1_BTR_BRP_Pos (0UL) /*!< BRP (Bit 0) */ +#define CAN1_BTR_BRP_Msk (0x3ffUL) /*!< BRP (Bitfield-Mask: 0x3ff) */ +#define CAN1_BTR_SJW_Pos (14UL) /*!< SJW (Bit 14) */ +#define CAN1_BTR_SJW_Msk (0xc000UL) /*!< SJW (Bitfield-Mask: 0x03) */ +#define CAN1_BTR_TESG1_Pos (16UL) /*!< TESG1 (Bit 16) */ +#define CAN1_BTR_TESG1_Msk (0xf0000UL) /*!< TESG1 (Bitfield-Mask: 0x0f) */ +#define CAN1_BTR_TESG2_Pos (20UL) /*!< TESG2 (Bit 20) */ +#define CAN1_BTR_TESG2_Msk (0x700000UL) /*!< TESG2 (Bitfield-Mask: 0x07) */ +#define CAN1_BTR_SAM_Pos (23UL) /*!< SAM (Bit 23) */ +#define CAN1_BTR_SAM_Msk (0x800000UL) /*!< SAM (Bitfield-Mask: 0x01) */ +/* ========================================================== EWL ========================================================== */ +#define CAN1_EWL_EWL_Pos (0UL) /*!< EWL (Bit 0) */ +#define CAN1_EWL_EWL_Msk (0xffUL) /*!< EWL (Bitfield-Mask: 0xff) */ +/* ========================================================== SR =========================================================== */ +#define CAN1_SR_RBS_1_Pos (0UL) /*!< RBS_1 (Bit 0) */ +#define CAN1_SR_RBS_1_Msk (0x1UL) /*!< RBS_1 (Bitfield-Mask: 0x01) */ +#define CAN1_SR_DOS_1_Pos (1UL) /*!< DOS_1 (Bit 1) */ +#define CAN1_SR_DOS_1_Msk (0x2UL) /*!< DOS_1 (Bitfield-Mask: 0x01) */ +#define CAN1_SR_TBS1_1_Pos (2UL) /*!< TBS1_1 (Bit 2) */ +#define CAN1_SR_TBS1_1_Msk (0x4UL) /*!< TBS1_1 (Bitfield-Mask: 0x01) */ +#define CAN1_SR_TCS1_1_Pos (3UL) /*!< TCS1_1 (Bit 3) */ +#define CAN1_SR_TCS1_1_Msk (0x8UL) /*!< TCS1_1 (Bitfield-Mask: 0x01) */ +#define CAN1_SR_RS_1_Pos (4UL) /*!< RS_1 (Bit 4) */ +#define CAN1_SR_RS_1_Msk (0x10UL) /*!< RS_1 (Bitfield-Mask: 0x01) */ +#define CAN1_SR_TS1_1_Pos (5UL) /*!< TS1_1 (Bit 5) */ +#define CAN1_SR_TS1_1_Msk (0x20UL) /*!< TS1_1 (Bitfield-Mask: 0x01) */ +#define CAN1_SR_ES_1_Pos (6UL) /*!< ES_1 (Bit 6) */ +#define CAN1_SR_ES_1_Msk (0x40UL) /*!< ES_1 (Bitfield-Mask: 0x01) */ +#define CAN1_SR_BS_1_Pos (7UL) /*!< BS_1 (Bit 7) */ +#define CAN1_SR_BS_1_Msk (0x80UL) /*!< BS_1 (Bitfield-Mask: 0x01) */ +#define CAN1_SR_RBS_2_Pos (8UL) /*!< RBS_2 (Bit 8) */ +#define CAN1_SR_RBS_2_Msk (0x100UL) /*!< RBS_2 (Bitfield-Mask: 0x01) */ +#define CAN1_SR_DOS_2_Pos (9UL) /*!< DOS_2 (Bit 9) */ +#define CAN1_SR_DOS_2_Msk (0x200UL) /*!< DOS_2 (Bitfield-Mask: 0x01) */ +#define CAN1_SR_TBS2_2_Pos (10UL) /*!< TBS2_2 (Bit 10) */ +#define CAN1_SR_TBS2_2_Msk (0x400UL) /*!< TBS2_2 (Bitfield-Mask: 0x01) */ +#define CAN1_SR_TCS2_2_Pos (11UL) /*!< TCS2_2 (Bit 11) */ +#define CAN1_SR_TCS2_2_Msk (0x800UL) /*!< TCS2_2 (Bitfield-Mask: 0x01) */ +#define CAN1_SR_RS_2_Pos (12UL) /*!< RS_2 (Bit 12) */ +#define CAN1_SR_RS_2_Msk (0x1000UL) /*!< RS_2 (Bitfield-Mask: 0x01) */ +#define CAN1_SR_TS2_2_Pos (13UL) /*!< TS2_2 (Bit 13) */ +#define CAN1_SR_TS2_2_Msk (0x2000UL) /*!< TS2_2 (Bitfield-Mask: 0x01) */ +#define CAN1_SR_ES_2_Pos (14UL) /*!< ES_2 (Bit 14) */ +#define CAN1_SR_ES_2_Msk (0x4000UL) /*!< ES_2 (Bitfield-Mask: 0x01) */ +#define CAN1_SR_BS_2_Pos (15UL) /*!< BS_2 (Bit 15) */ +#define CAN1_SR_BS_2_Msk (0x8000UL) /*!< BS_2 (Bitfield-Mask: 0x01) */ +#define CAN1_SR_RBS_3_Pos (16UL) /*!< RBS_3 (Bit 16) */ +#define CAN1_SR_RBS_3_Msk (0x10000UL) /*!< RBS_3 (Bitfield-Mask: 0x01) */ +#define CAN1_SR_DOS_3_Pos (17UL) /*!< DOS_3 (Bit 17) */ +#define CAN1_SR_DOS_3_Msk (0x20000UL) /*!< DOS_3 (Bitfield-Mask: 0x01) */ +#define CAN1_SR_TBS3_3_Pos (18UL) /*!< TBS3_3 (Bit 18) */ +#define CAN1_SR_TBS3_3_Msk (0x40000UL) /*!< TBS3_3 (Bitfield-Mask: 0x01) */ +#define CAN1_SR_TCS3_3_Pos (19UL) /*!< TCS3_3 (Bit 19) */ +#define CAN1_SR_TCS3_3_Msk (0x80000UL) /*!< TCS3_3 (Bitfield-Mask: 0x01) */ +#define CAN1_SR_RS_3_Pos (20UL) /*!< RS_3 (Bit 20) */ +#define CAN1_SR_RS_3_Msk (0x100000UL) /*!< RS_3 (Bitfield-Mask: 0x01) */ +#define CAN1_SR_TS3_3_Pos (21UL) /*!< TS3_3 (Bit 21) */ +#define CAN1_SR_TS3_3_Msk (0x200000UL) /*!< TS3_3 (Bitfield-Mask: 0x01) */ +#define CAN1_SR_ES_3_Pos (22UL) /*!< ES_3 (Bit 22) */ +#define CAN1_SR_ES_3_Msk (0x400000UL) /*!< ES_3 (Bitfield-Mask: 0x01) */ +#define CAN1_SR_BS_3_Pos (23UL) /*!< BS_3 (Bit 23) */ +#define CAN1_SR_BS_3_Msk (0x800000UL) /*!< BS_3 (Bitfield-Mask: 0x01) */ +/* ========================================================== RFS ========================================================== */ +#define CAN1_RFS_IDINDEX_Pos (0UL) /*!< IDINDEX (Bit 0) */ +#define CAN1_RFS_IDINDEX_Msk (0x3ffUL) /*!< IDINDEX (Bitfield-Mask: 0x3ff) */ +#define CAN1_RFS_BP_Pos (10UL) /*!< BP (Bit 10) */ +#define CAN1_RFS_BP_Msk (0x400UL) /*!< BP (Bitfield-Mask: 0x01) */ +#define CAN1_RFS_DLC_Pos (16UL) /*!< DLC (Bit 16) */ +#define CAN1_RFS_DLC_Msk (0xf0000UL) /*!< DLC (Bitfield-Mask: 0x0f) */ +#define CAN1_RFS_RTR_Pos (30UL) /*!< RTR (Bit 30) */ +#define CAN1_RFS_RTR_Msk (0x40000000UL) /*!< RTR (Bitfield-Mask: 0x01) */ +#define CAN1_RFS_FF_Pos (31UL) /*!< FF (Bit 31) */ +#define CAN1_RFS_FF_Msk (0x80000000UL) /*!< FF (Bitfield-Mask: 0x01) */ +/* ========================================================== RID ========================================================== */ +#define CAN1_RID_ID_Pos (0UL) /*!< ID (Bit 0) */ +#define CAN1_RID_ID_Msk (0x7ffUL) /*!< ID (Bitfield-Mask: 0x7ff) */ +/* ========================================================== RDA ========================================================== */ +#define CAN1_RDA_DATA1_Pos (0UL) /*!< DATA1 (Bit 0) */ +#define CAN1_RDA_DATA1_Msk (0xffUL) /*!< DATA1 (Bitfield-Mask: 0xff) */ +#define CAN1_RDA_DATA2_Pos (8UL) /*!< DATA2 (Bit 8) */ +#define CAN1_RDA_DATA2_Msk (0xff00UL) /*!< DATA2 (Bitfield-Mask: 0xff) */ +#define CAN1_RDA_DATA3_Pos (16UL) /*!< DATA3 (Bit 16) */ +#define CAN1_RDA_DATA3_Msk (0xff0000UL) /*!< DATA3 (Bitfield-Mask: 0xff) */ +#define CAN1_RDA_DATA4_Pos (24UL) /*!< DATA4 (Bit 24) */ +#define CAN1_RDA_DATA4_Msk (0xff000000UL) /*!< DATA4 (Bitfield-Mask: 0xff) */ +/* ========================================================== RDB ========================================================== */ +#define CAN1_RDB_DATA5_Pos (0UL) /*!< DATA5 (Bit 0) */ +#define CAN1_RDB_DATA5_Msk (0xffUL) /*!< DATA5 (Bitfield-Mask: 0xff) */ +#define CAN1_RDB_DATA6_Pos (8UL) /*!< DATA6 (Bit 8) */ +#define CAN1_RDB_DATA6_Msk (0xff00UL) /*!< DATA6 (Bitfield-Mask: 0xff) */ +#define CAN1_RDB_DATA7_Pos (16UL) /*!< DATA7 (Bit 16) */ +#define CAN1_RDB_DATA7_Msk (0xff0000UL) /*!< DATA7 (Bitfield-Mask: 0xff) */ +#define CAN1_RDB_DATA8_Pos (24UL) /*!< DATA8 (Bit 24) */ +#define CAN1_RDB_DATA8_Msk (0xff000000UL) /*!< DATA8 (Bitfield-Mask: 0xff) */ +/* ========================================================= TFI1 ========================================================== */ +#define CAN1_TFI1_PRIO_Pos (0UL) /*!< PRIO (Bit 0) */ +#define CAN1_TFI1_PRIO_Msk (0xffUL) /*!< PRIO (Bitfield-Mask: 0xff) */ +#define CAN1_TFI1_DLC_Pos (16UL) /*!< DLC (Bit 16) */ +#define CAN1_TFI1_DLC_Msk (0xf0000UL) /*!< DLC (Bitfield-Mask: 0x0f) */ +#define CAN1_TFI1_RTR_Pos (30UL) /*!< RTR (Bit 30) */ +#define CAN1_TFI1_RTR_Msk (0x40000000UL) /*!< RTR (Bitfield-Mask: 0x01) */ +#define CAN1_TFI1_FF_Pos (31UL) /*!< FF (Bit 31) */ +#define CAN1_TFI1_FF_Msk (0x80000000UL) /*!< FF (Bitfield-Mask: 0x01) */ +/* ========================================================= TFI2 ========================================================== */ +#define CAN1_TFI2_PRIO_Pos (0UL) /*!< PRIO (Bit 0) */ +#define CAN1_TFI2_PRIO_Msk (0xffUL) /*!< PRIO (Bitfield-Mask: 0xff) */ +#define CAN1_TFI2_DLC_Pos (16UL) /*!< DLC (Bit 16) */ +#define CAN1_TFI2_DLC_Msk (0xf0000UL) /*!< DLC (Bitfield-Mask: 0x0f) */ +#define CAN1_TFI2_RTR_Pos (30UL) /*!< RTR (Bit 30) */ +#define CAN1_TFI2_RTR_Msk (0x40000000UL) /*!< RTR (Bitfield-Mask: 0x01) */ +#define CAN1_TFI2_FF_Pos (31UL) /*!< FF (Bit 31) */ +#define CAN1_TFI2_FF_Msk (0x80000000UL) /*!< FF (Bitfield-Mask: 0x01) */ +/* ========================================================= TFI3 ========================================================== */ +#define CAN1_TFI3_PRIO_Pos (0UL) /*!< PRIO (Bit 0) */ +#define CAN1_TFI3_PRIO_Msk (0xffUL) /*!< PRIO (Bitfield-Mask: 0xff) */ +#define CAN1_TFI3_DLC_Pos (16UL) /*!< DLC (Bit 16) */ +#define CAN1_TFI3_DLC_Msk (0xf0000UL) /*!< DLC (Bitfield-Mask: 0x0f) */ +#define CAN1_TFI3_RTR_Pos (30UL) /*!< RTR (Bit 30) */ +#define CAN1_TFI3_RTR_Msk (0x40000000UL) /*!< RTR (Bitfield-Mask: 0x01) */ +#define CAN1_TFI3_FF_Pos (31UL) /*!< FF (Bit 31) */ +#define CAN1_TFI3_FF_Msk (0x80000000UL) /*!< FF (Bitfield-Mask: 0x01) */ +/* ========================================================= TID1 ========================================================== */ +#define CAN1_TID1_ID_Pos (0UL) /*!< ID (Bit 0) */ +#define CAN1_TID1_ID_Msk (0x7ffUL) /*!< ID (Bitfield-Mask: 0x7ff) */ +/* ========================================================= TID2 ========================================================== */ +#define CAN1_TID2_ID_Pos (0UL) /*!< ID (Bit 0) */ +#define CAN1_TID2_ID_Msk (0x7ffUL) /*!< ID (Bitfield-Mask: 0x7ff) */ +/* ========================================================= TID3 ========================================================== */ +#define CAN1_TID3_ID_Pos (0UL) /*!< ID (Bit 0) */ +#define CAN1_TID3_ID_Msk (0x7ffUL) /*!< ID (Bitfield-Mask: 0x7ff) */ +/* ========================================================= TDA1 ========================================================== */ +#define CAN1_TDA1_DATA1_Pos (0UL) /*!< DATA1 (Bit 0) */ +#define CAN1_TDA1_DATA1_Msk (0xffUL) /*!< DATA1 (Bitfield-Mask: 0xff) */ +#define CAN1_TDA1_DATA2_Pos (8UL) /*!< DATA2 (Bit 8) */ +#define CAN1_TDA1_DATA2_Msk (0xff00UL) /*!< DATA2 (Bitfield-Mask: 0xff) */ +#define CAN1_TDA1_DATA3_Pos (16UL) /*!< DATA3 (Bit 16) */ +#define CAN1_TDA1_DATA3_Msk (0xff0000UL) /*!< DATA3 (Bitfield-Mask: 0xff) */ +#define CAN1_TDA1_DATA4_Pos (24UL) /*!< DATA4 (Bit 24) */ +#define CAN1_TDA1_DATA4_Msk (0xff000000UL) /*!< DATA4 (Bitfield-Mask: 0xff) */ +/* ========================================================= TDA2 ========================================================== */ +#define CAN1_TDA2_DATA1_Pos (0UL) /*!< DATA1 (Bit 0) */ +#define CAN1_TDA2_DATA1_Msk (0xffUL) /*!< DATA1 (Bitfield-Mask: 0xff) */ +#define CAN1_TDA2_DATA2_Pos (8UL) /*!< DATA2 (Bit 8) */ +#define CAN1_TDA2_DATA2_Msk (0xff00UL) /*!< DATA2 (Bitfield-Mask: 0xff) */ +#define CAN1_TDA2_DATA3_Pos (16UL) /*!< DATA3 (Bit 16) */ +#define CAN1_TDA2_DATA3_Msk (0xff0000UL) /*!< DATA3 (Bitfield-Mask: 0xff) */ +#define CAN1_TDA2_DATA4_Pos (24UL) /*!< DATA4 (Bit 24) */ +#define CAN1_TDA2_DATA4_Msk (0xff000000UL) /*!< DATA4 (Bitfield-Mask: 0xff) */ +/* ========================================================= TDA3 ========================================================== */ +#define CAN1_TDA3_DATA1_Pos (0UL) /*!< DATA1 (Bit 0) */ +#define CAN1_TDA3_DATA1_Msk (0xffUL) /*!< DATA1 (Bitfield-Mask: 0xff) */ +#define CAN1_TDA3_DATA2_Pos (8UL) /*!< DATA2 (Bit 8) */ +#define CAN1_TDA3_DATA2_Msk (0xff00UL) /*!< DATA2 (Bitfield-Mask: 0xff) */ +#define CAN1_TDA3_DATA3_Pos (16UL) /*!< DATA3 (Bit 16) */ +#define CAN1_TDA3_DATA3_Msk (0xff0000UL) /*!< DATA3 (Bitfield-Mask: 0xff) */ +#define CAN1_TDA3_DATA4_Pos (24UL) /*!< DATA4 (Bit 24) */ +#define CAN1_TDA3_DATA4_Msk (0xff000000UL) /*!< DATA4 (Bitfield-Mask: 0xff) */ +/* ========================================================= TDB1 ========================================================== */ +#define CAN1_TDB1_DATA5_Pos (0UL) /*!< DATA5 (Bit 0) */ +#define CAN1_TDB1_DATA5_Msk (0xffUL) /*!< DATA5 (Bitfield-Mask: 0xff) */ +#define CAN1_TDB1_DATA6_Pos (8UL) /*!< DATA6 (Bit 8) */ +#define CAN1_TDB1_DATA6_Msk (0xff00UL) /*!< DATA6 (Bitfield-Mask: 0xff) */ +#define CAN1_TDB1_DATA7_Pos (16UL) /*!< DATA7 (Bit 16) */ +#define CAN1_TDB1_DATA7_Msk (0xff0000UL) /*!< DATA7 (Bitfield-Mask: 0xff) */ +#define CAN1_TDB1_DATA8_Pos (24UL) /*!< DATA8 (Bit 24) */ +#define CAN1_TDB1_DATA8_Msk (0xff000000UL) /*!< DATA8 (Bitfield-Mask: 0xff) */ +/* ========================================================= TDB2 ========================================================== */ +#define CAN1_TDB2_DATA5_Pos (0UL) /*!< DATA5 (Bit 0) */ +#define CAN1_TDB2_DATA5_Msk (0xffUL) /*!< DATA5 (Bitfield-Mask: 0xff) */ +#define CAN1_TDB2_DATA6_Pos (8UL) /*!< DATA6 (Bit 8) */ +#define CAN1_TDB2_DATA6_Msk (0xff00UL) /*!< DATA6 (Bitfield-Mask: 0xff) */ +#define CAN1_TDB2_DATA7_Pos (16UL) /*!< DATA7 (Bit 16) */ +#define CAN1_TDB2_DATA7_Msk (0xff0000UL) /*!< DATA7 (Bitfield-Mask: 0xff) */ +#define CAN1_TDB2_DATA8_Pos (24UL) /*!< DATA8 (Bit 24) */ +#define CAN1_TDB2_DATA8_Msk (0xff000000UL) /*!< DATA8 (Bitfield-Mask: 0xff) */ +/* ========================================================= TDB3 ========================================================== */ +#define CAN1_TDB3_DATA5_Pos (0UL) /*!< DATA5 (Bit 0) */ +#define CAN1_TDB3_DATA5_Msk (0xffUL) /*!< DATA5 (Bitfield-Mask: 0xff) */ +#define CAN1_TDB3_DATA6_Pos (8UL) /*!< DATA6 (Bit 8) */ +#define CAN1_TDB3_DATA6_Msk (0xff00UL) /*!< DATA6 (Bitfield-Mask: 0xff) */ +#define CAN1_TDB3_DATA7_Pos (16UL) /*!< DATA7 (Bit 16) */ +#define CAN1_TDB3_DATA7_Msk (0xff0000UL) /*!< DATA7 (Bitfield-Mask: 0xff) */ +#define CAN1_TDB3_DATA8_Pos (24UL) /*!< DATA8 (Bit 24) */ +#define CAN1_TDB3_DATA8_Msk (0xff000000UL) /*!< DATA8 (Bitfield-Mask: 0xff) */ + + +/* =========================================================================================================================== */ +/* ================ LPC_CAN2 ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== MOD ========================================================== */ +#define CAN2_MOD_RM_Pos (0UL) /*!< RM (Bit 0) */ +#define CAN2_MOD_RM_Msk (0x1UL) /*!< RM (Bitfield-Mask: 0x01) */ +#define CAN2_MOD_LOM_Pos (1UL) /*!< LOM (Bit 1) */ +#define CAN2_MOD_LOM_Msk (0x2UL) /*!< LOM (Bitfield-Mask: 0x01) */ +#define CAN2_MOD_STM_Pos (2UL) /*!< STM (Bit 2) */ +#define CAN2_MOD_STM_Msk (0x4UL) /*!< STM (Bitfield-Mask: 0x01) */ +#define CAN2_MOD_TPM_Pos (3UL) /*!< TPM (Bit 3) */ +#define CAN2_MOD_TPM_Msk (0x8UL) /*!< TPM (Bitfield-Mask: 0x01) */ +#define CAN2_MOD_SM_Pos (4UL) /*!< SM (Bit 4) */ +#define CAN2_MOD_SM_Msk (0x10UL) /*!< SM (Bitfield-Mask: 0x01) */ +#define CAN2_MOD_RPM_Pos (5UL) /*!< RPM (Bit 5) */ +#define CAN2_MOD_RPM_Msk (0x20UL) /*!< RPM (Bitfield-Mask: 0x01) */ +#define CAN2_MOD_TM_Pos (7UL) /*!< TM (Bit 7) */ +#define CAN2_MOD_TM_Msk (0x80UL) /*!< TM (Bitfield-Mask: 0x01) */ +/* ========================================================== CMR ========================================================== */ +#define CAN2_CMR_TR_Pos (0UL) /*!< TR (Bit 0) */ +#define CAN2_CMR_TR_Msk (0x1UL) /*!< TR (Bitfield-Mask: 0x01) */ +#define CAN2_CMR_AT_Pos (1UL) /*!< AT (Bit 1) */ +#define CAN2_CMR_AT_Msk (0x2UL) /*!< AT (Bitfield-Mask: 0x01) */ +#define CAN2_CMR_RRB_Pos (2UL) /*!< RRB (Bit 2) */ +#define CAN2_CMR_RRB_Msk (0x4UL) /*!< RRB (Bitfield-Mask: 0x01) */ +#define CAN2_CMR_CDO_Pos (3UL) /*!< CDO (Bit 3) */ +#define CAN2_CMR_CDO_Msk (0x8UL) /*!< CDO (Bitfield-Mask: 0x01) */ +#define CAN2_CMR_SRR_Pos (4UL) /*!< SRR (Bit 4) */ +#define CAN2_CMR_SRR_Msk (0x10UL) /*!< SRR (Bitfield-Mask: 0x01) */ +#define CAN2_CMR_STB1_Pos (5UL) /*!< STB1 (Bit 5) */ +#define CAN2_CMR_STB1_Msk (0x20UL) /*!< STB1 (Bitfield-Mask: 0x01) */ +#define CAN2_CMR_STB2_Pos (6UL) /*!< STB2 (Bit 6) */ +#define CAN2_CMR_STB2_Msk (0x40UL) /*!< STB2 (Bitfield-Mask: 0x01) */ +#define CAN2_CMR_STB3_Pos (7UL) /*!< STB3 (Bit 7) */ +#define CAN2_CMR_STB3_Msk (0x80UL) /*!< STB3 (Bitfield-Mask: 0x01) */ +/* ========================================================== GSR ========================================================== */ +#define CAN2_GSR_RBS_Pos (0UL) /*!< RBS (Bit 0) */ +#define CAN2_GSR_RBS_Msk (0x1UL) /*!< RBS (Bitfield-Mask: 0x01) */ +#define CAN2_GSR_DOS_Pos (1UL) /*!< DOS (Bit 1) */ +#define CAN2_GSR_DOS_Msk (0x2UL) /*!< DOS (Bitfield-Mask: 0x01) */ +#define CAN2_GSR_TBS_Pos (2UL) /*!< TBS (Bit 2) */ +#define CAN2_GSR_TBS_Msk (0x4UL) /*!< TBS (Bitfield-Mask: 0x01) */ +#define CAN2_GSR_TCS_Pos (3UL) /*!< TCS (Bit 3) */ +#define CAN2_GSR_TCS_Msk (0x8UL) /*!< TCS (Bitfield-Mask: 0x01) */ +#define CAN2_GSR_RS_Pos (4UL) /*!< RS (Bit 4) */ +#define CAN2_GSR_RS_Msk (0x10UL) /*!< RS (Bitfield-Mask: 0x01) */ +#define CAN2_GSR_TS_Pos (5UL) /*!< TS (Bit 5) */ +#define CAN2_GSR_TS_Msk (0x20UL) /*!< TS (Bitfield-Mask: 0x01) */ +#define CAN2_GSR_ES_Pos (6UL) /*!< ES (Bit 6) */ +#define CAN2_GSR_ES_Msk (0x40UL) /*!< ES (Bitfield-Mask: 0x01) */ +#define CAN2_GSR_BS_Pos (7UL) /*!< BS (Bit 7) */ +#define CAN2_GSR_BS_Msk (0x80UL) /*!< BS (Bitfield-Mask: 0x01) */ +#define CAN2_GSR_RXERR_Pos (16UL) /*!< RXERR (Bit 16) */ +#define CAN2_GSR_RXERR_Msk (0xff0000UL) /*!< RXERR (Bitfield-Mask: 0xff) */ +#define CAN2_GSR_TXERR_Pos (24UL) /*!< TXERR (Bit 24) */ +#define CAN2_GSR_TXERR_Msk (0xff000000UL) /*!< TXERR (Bitfield-Mask: 0xff) */ +/* ========================================================== ICR ========================================================== */ +#define CAN2_ICR_RI_Pos (0UL) /*!< RI (Bit 0) */ +#define CAN2_ICR_RI_Msk (0x1UL) /*!< RI (Bitfield-Mask: 0x01) */ +#define CAN2_ICR_TI1_Pos (1UL) /*!< TI1 (Bit 1) */ +#define CAN2_ICR_TI1_Msk (0x2UL) /*!< TI1 (Bitfield-Mask: 0x01) */ +#define CAN2_ICR_EI_Pos (2UL) /*!< EI (Bit 2) */ +#define CAN2_ICR_EI_Msk (0x4UL) /*!< EI (Bitfield-Mask: 0x01) */ +#define CAN2_ICR_DOI_Pos (3UL) /*!< DOI (Bit 3) */ +#define CAN2_ICR_DOI_Msk (0x8UL) /*!< DOI (Bitfield-Mask: 0x01) */ +#define CAN2_ICR_WUI_Pos (4UL) /*!< WUI (Bit 4) */ +#define CAN2_ICR_WUI_Msk (0x10UL) /*!< WUI (Bitfield-Mask: 0x01) */ +#define CAN2_ICR_EPI_Pos (5UL) /*!< EPI (Bit 5) */ +#define CAN2_ICR_EPI_Msk (0x20UL) /*!< EPI (Bitfield-Mask: 0x01) */ +#define CAN2_ICR_ALI_Pos (6UL) /*!< ALI (Bit 6) */ +#define CAN2_ICR_ALI_Msk (0x40UL) /*!< ALI (Bitfield-Mask: 0x01) */ +#define CAN2_ICR_BEI_Pos (7UL) /*!< BEI (Bit 7) */ +#define CAN2_ICR_BEI_Msk (0x80UL) /*!< BEI (Bitfield-Mask: 0x01) */ +#define CAN2_ICR_IDI_Pos (8UL) /*!< IDI (Bit 8) */ +#define CAN2_ICR_IDI_Msk (0x100UL) /*!< IDI (Bitfield-Mask: 0x01) */ +#define CAN2_ICR_TI2_Pos (9UL) /*!< TI2 (Bit 9) */ +#define CAN2_ICR_TI2_Msk (0x200UL) /*!< TI2 (Bitfield-Mask: 0x01) */ +#define CAN2_ICR_TI3_Pos (10UL) /*!< TI3 (Bit 10) */ +#define CAN2_ICR_TI3_Msk (0x400UL) /*!< TI3 (Bitfield-Mask: 0x01) */ +#define CAN2_ICR_ERRBIT4_0_Pos (16UL) /*!< ERRBIT4_0 (Bit 16) */ +#define CAN2_ICR_ERRBIT4_0_Msk (0x1f0000UL) /*!< ERRBIT4_0 (Bitfield-Mask: 0x1f) */ +#define CAN2_ICR_ERRDIR_Pos (21UL) /*!< ERRDIR (Bit 21) */ +#define CAN2_ICR_ERRDIR_Msk (0x200000UL) /*!< ERRDIR (Bitfield-Mask: 0x01) */ +#define CAN2_ICR_ERRC1_0_Pos (22UL) /*!< ERRC1_0 (Bit 22) */ +#define CAN2_ICR_ERRC1_0_Msk (0xc00000UL) /*!< ERRC1_0 (Bitfield-Mask: 0x03) */ +#define CAN2_ICR_ALCBIT_Pos (24UL) /*!< ALCBIT (Bit 24) */ +#define CAN2_ICR_ALCBIT_Msk (0xff000000UL) /*!< ALCBIT (Bitfield-Mask: 0xff) */ +/* ========================================================== IER ========================================================== */ +#define CAN2_IER_RIE_Pos (0UL) /*!< RIE (Bit 0) */ +#define CAN2_IER_RIE_Msk (0x1UL) /*!< RIE (Bitfield-Mask: 0x01) */ +#define CAN2_IER_TIE1_Pos (1UL) /*!< TIE1 (Bit 1) */ +#define CAN2_IER_TIE1_Msk (0x2UL) /*!< TIE1 (Bitfield-Mask: 0x01) */ +#define CAN2_IER_EIE_Pos (2UL) /*!< EIE (Bit 2) */ +#define CAN2_IER_EIE_Msk (0x4UL) /*!< EIE (Bitfield-Mask: 0x01) */ +#define CAN2_IER_DOIE_Pos (3UL) /*!< DOIE (Bit 3) */ +#define CAN2_IER_DOIE_Msk (0x8UL) /*!< DOIE (Bitfield-Mask: 0x01) */ +#define CAN2_IER_WUIE_Pos (4UL) /*!< WUIE (Bit 4) */ +#define CAN2_IER_WUIE_Msk (0x10UL) /*!< WUIE (Bitfield-Mask: 0x01) */ +#define CAN2_IER_EPIE_Pos (5UL) /*!< EPIE (Bit 5) */ +#define CAN2_IER_EPIE_Msk (0x20UL) /*!< EPIE (Bitfield-Mask: 0x01) */ +#define CAN2_IER_ALIE_Pos (6UL) /*!< ALIE (Bit 6) */ +#define CAN2_IER_ALIE_Msk (0x40UL) /*!< ALIE (Bitfield-Mask: 0x01) */ +#define CAN2_IER_BEIE_Pos (7UL) /*!< BEIE (Bit 7) */ +#define CAN2_IER_BEIE_Msk (0x80UL) /*!< BEIE (Bitfield-Mask: 0x01) */ +#define CAN2_IER_IDIE_Pos (8UL) /*!< IDIE (Bit 8) */ +#define CAN2_IER_IDIE_Msk (0x100UL) /*!< IDIE (Bitfield-Mask: 0x01) */ +#define CAN2_IER_TIE2_Pos (9UL) /*!< TIE2 (Bit 9) */ +#define CAN2_IER_TIE2_Msk (0x200UL) /*!< TIE2 (Bitfield-Mask: 0x01) */ +#define CAN2_IER_TIE3_Pos (10UL) /*!< TIE3 (Bit 10) */ +#define CAN2_IER_TIE3_Msk (0x400UL) /*!< TIE3 (Bitfield-Mask: 0x01) */ +/* ========================================================== BTR ========================================================== */ +#define CAN2_BTR_BRP_Pos (0UL) /*!< BRP (Bit 0) */ +#define CAN2_BTR_BRP_Msk (0x3ffUL) /*!< BRP (Bitfield-Mask: 0x3ff) */ +#define CAN2_BTR_SJW_Pos (14UL) /*!< SJW (Bit 14) */ +#define CAN2_BTR_SJW_Msk (0xc000UL) /*!< SJW (Bitfield-Mask: 0x03) */ +#define CAN2_BTR_TESG1_Pos (16UL) /*!< TESG1 (Bit 16) */ +#define CAN2_BTR_TESG1_Msk (0xf0000UL) /*!< TESG1 (Bitfield-Mask: 0x0f) */ +#define CAN2_BTR_TESG2_Pos (20UL) /*!< TESG2 (Bit 20) */ +#define CAN2_BTR_TESG2_Msk (0x700000UL) /*!< TESG2 (Bitfield-Mask: 0x07) */ +#define CAN2_BTR_SAM_Pos (23UL) /*!< SAM (Bit 23) */ +#define CAN2_BTR_SAM_Msk (0x800000UL) /*!< SAM (Bitfield-Mask: 0x01) */ +/* ========================================================== EWL ========================================================== */ +#define CAN2_EWL_EWL_Pos (0UL) /*!< EWL (Bit 0) */ +#define CAN2_EWL_EWL_Msk (0xffUL) /*!< EWL (Bitfield-Mask: 0xff) */ +/* ========================================================== SR =========================================================== */ +#define CAN2_SR_RBS_1_Pos (0UL) /*!< RBS_1 (Bit 0) */ +#define CAN2_SR_RBS_1_Msk (0x1UL) /*!< RBS_1 (Bitfield-Mask: 0x01) */ +#define CAN2_SR_DOS_1_Pos (1UL) /*!< DOS_1 (Bit 1) */ +#define CAN2_SR_DOS_1_Msk (0x2UL) /*!< DOS_1 (Bitfield-Mask: 0x01) */ +#define CAN2_SR_TBS1_1_Pos (2UL) /*!< TBS1_1 (Bit 2) */ +#define CAN2_SR_TBS1_1_Msk (0x4UL) /*!< TBS1_1 (Bitfield-Mask: 0x01) */ +#define CAN2_SR_TCS1_1_Pos (3UL) /*!< TCS1_1 (Bit 3) */ +#define CAN2_SR_TCS1_1_Msk (0x8UL) /*!< TCS1_1 (Bitfield-Mask: 0x01) */ +#define CAN2_SR_RS_1_Pos (4UL) /*!< RS_1 (Bit 4) */ +#define CAN2_SR_RS_1_Msk (0x10UL) /*!< RS_1 (Bitfield-Mask: 0x01) */ +#define CAN2_SR_TS1_1_Pos (5UL) /*!< TS1_1 (Bit 5) */ +#define CAN2_SR_TS1_1_Msk (0x20UL) /*!< TS1_1 (Bitfield-Mask: 0x01) */ +#define CAN2_SR_ES_1_Pos (6UL) /*!< ES_1 (Bit 6) */ +#define CAN2_SR_ES_1_Msk (0x40UL) /*!< ES_1 (Bitfield-Mask: 0x01) */ +#define CAN2_SR_BS_1_Pos (7UL) /*!< BS_1 (Bit 7) */ +#define CAN2_SR_BS_1_Msk (0x80UL) /*!< BS_1 (Bitfield-Mask: 0x01) */ +#define CAN2_SR_RBS_2_Pos (8UL) /*!< RBS_2 (Bit 8) */ +#define CAN2_SR_RBS_2_Msk (0x100UL) /*!< RBS_2 (Bitfield-Mask: 0x01) */ +#define CAN2_SR_DOS_2_Pos (9UL) /*!< DOS_2 (Bit 9) */ +#define CAN2_SR_DOS_2_Msk (0x200UL) /*!< DOS_2 (Bitfield-Mask: 0x01) */ +#define CAN2_SR_TBS2_2_Pos (10UL) /*!< TBS2_2 (Bit 10) */ +#define CAN2_SR_TBS2_2_Msk (0x400UL) /*!< TBS2_2 (Bitfield-Mask: 0x01) */ +#define CAN2_SR_TCS2_2_Pos (11UL) /*!< TCS2_2 (Bit 11) */ +#define CAN2_SR_TCS2_2_Msk (0x800UL) /*!< TCS2_2 (Bitfield-Mask: 0x01) */ +#define CAN2_SR_RS_2_Pos (12UL) /*!< RS_2 (Bit 12) */ +#define CAN2_SR_RS_2_Msk (0x1000UL) /*!< RS_2 (Bitfield-Mask: 0x01) */ +#define CAN2_SR_TS2_2_Pos (13UL) /*!< TS2_2 (Bit 13) */ +#define CAN2_SR_TS2_2_Msk (0x2000UL) /*!< TS2_2 (Bitfield-Mask: 0x01) */ +#define CAN2_SR_ES_2_Pos (14UL) /*!< ES_2 (Bit 14) */ +#define CAN2_SR_ES_2_Msk (0x4000UL) /*!< ES_2 (Bitfield-Mask: 0x01) */ +#define CAN2_SR_BS_2_Pos (15UL) /*!< BS_2 (Bit 15) */ +#define CAN2_SR_BS_2_Msk (0x8000UL) /*!< BS_2 (Bitfield-Mask: 0x01) */ +#define CAN2_SR_RBS_3_Pos (16UL) /*!< RBS_3 (Bit 16) */ +#define CAN2_SR_RBS_3_Msk (0x10000UL) /*!< RBS_3 (Bitfield-Mask: 0x01) */ +#define CAN2_SR_DOS_3_Pos (17UL) /*!< DOS_3 (Bit 17) */ +#define CAN2_SR_DOS_3_Msk (0x20000UL) /*!< DOS_3 (Bitfield-Mask: 0x01) */ +#define CAN2_SR_TBS3_3_Pos (18UL) /*!< TBS3_3 (Bit 18) */ +#define CAN2_SR_TBS3_3_Msk (0x40000UL) /*!< TBS3_3 (Bitfield-Mask: 0x01) */ +#define CAN2_SR_TCS3_3_Pos (19UL) /*!< TCS3_3 (Bit 19) */ +#define CAN2_SR_TCS3_3_Msk (0x80000UL) /*!< TCS3_3 (Bitfield-Mask: 0x01) */ +#define CAN2_SR_RS_3_Pos (20UL) /*!< RS_3 (Bit 20) */ +#define CAN2_SR_RS_3_Msk (0x100000UL) /*!< RS_3 (Bitfield-Mask: 0x01) */ +#define CAN2_SR_TS3_3_Pos (21UL) /*!< TS3_3 (Bit 21) */ +#define CAN2_SR_TS3_3_Msk (0x200000UL) /*!< TS3_3 (Bitfield-Mask: 0x01) */ +#define CAN2_SR_ES_3_Pos (22UL) /*!< ES_3 (Bit 22) */ +#define CAN2_SR_ES_3_Msk (0x400000UL) /*!< ES_3 (Bitfield-Mask: 0x01) */ +#define CAN2_SR_BS_3_Pos (23UL) /*!< BS_3 (Bit 23) */ +#define CAN2_SR_BS_3_Msk (0x800000UL) /*!< BS_3 (Bitfield-Mask: 0x01) */ +/* ========================================================== RFS ========================================================== */ +#define CAN2_RFS_IDINDEX_Pos (0UL) /*!< IDINDEX (Bit 0) */ +#define CAN2_RFS_IDINDEX_Msk (0x3ffUL) /*!< IDINDEX (Bitfield-Mask: 0x3ff) */ +#define CAN2_RFS_BP_Pos (10UL) /*!< BP (Bit 10) */ +#define CAN2_RFS_BP_Msk (0x400UL) /*!< BP (Bitfield-Mask: 0x01) */ +#define CAN2_RFS_DLC_Pos (16UL) /*!< DLC (Bit 16) */ +#define CAN2_RFS_DLC_Msk (0xf0000UL) /*!< DLC (Bitfield-Mask: 0x0f) */ +#define CAN2_RFS_RTR_Pos (30UL) /*!< RTR (Bit 30) */ +#define CAN2_RFS_RTR_Msk (0x40000000UL) /*!< RTR (Bitfield-Mask: 0x01) */ +#define CAN2_RFS_FF_Pos (31UL) /*!< FF (Bit 31) */ +#define CAN2_RFS_FF_Msk (0x80000000UL) /*!< FF (Bitfield-Mask: 0x01) */ +/* ========================================================== RID ========================================================== */ +#define CAN2_RID_ID_Pos (0UL) /*!< ID (Bit 0) */ +#define CAN2_RID_ID_Msk (0x7ffUL) /*!< ID (Bitfield-Mask: 0x7ff) */ +/* ========================================================== RDA ========================================================== */ +#define CAN2_RDA_DATA1_Pos (0UL) /*!< DATA1 (Bit 0) */ +#define CAN2_RDA_DATA1_Msk (0xffUL) /*!< DATA1 (Bitfield-Mask: 0xff) */ +#define CAN2_RDA_DATA2_Pos (8UL) /*!< DATA2 (Bit 8) */ +#define CAN2_RDA_DATA2_Msk (0xff00UL) /*!< DATA2 (Bitfield-Mask: 0xff) */ +#define CAN2_RDA_DATA3_Pos (16UL) /*!< DATA3 (Bit 16) */ +#define CAN2_RDA_DATA3_Msk (0xff0000UL) /*!< DATA3 (Bitfield-Mask: 0xff) */ +#define CAN2_RDA_DATA4_Pos (24UL) /*!< DATA4 (Bit 24) */ +#define CAN2_RDA_DATA4_Msk (0xff000000UL) /*!< DATA4 (Bitfield-Mask: 0xff) */ +/* ========================================================== RDB ========================================================== */ +#define CAN2_RDB_DATA5_Pos (0UL) /*!< DATA5 (Bit 0) */ +#define CAN2_RDB_DATA5_Msk (0xffUL) /*!< DATA5 (Bitfield-Mask: 0xff) */ +#define CAN2_RDB_DATA6_Pos (8UL) /*!< DATA6 (Bit 8) */ +#define CAN2_RDB_DATA6_Msk (0xff00UL) /*!< DATA6 (Bitfield-Mask: 0xff) */ +#define CAN2_RDB_DATA7_Pos (16UL) /*!< DATA7 (Bit 16) */ +#define CAN2_RDB_DATA7_Msk (0xff0000UL) /*!< DATA7 (Bitfield-Mask: 0xff) */ +#define CAN2_RDB_DATA8_Pos (24UL) /*!< DATA8 (Bit 24) */ +#define CAN2_RDB_DATA8_Msk (0xff000000UL) /*!< DATA8 (Bitfield-Mask: 0xff) */ +/* ========================================================= TFI1 ========================================================== */ +#define CAN2_TFI1_PRIO_Pos (0UL) /*!< PRIO (Bit 0) */ +#define CAN2_TFI1_PRIO_Msk (0xffUL) /*!< PRIO (Bitfield-Mask: 0xff) */ +#define CAN2_TFI1_DLC_Pos (16UL) /*!< DLC (Bit 16) */ +#define CAN2_TFI1_DLC_Msk (0xf0000UL) /*!< DLC (Bitfield-Mask: 0x0f) */ +#define CAN2_TFI1_RTR_Pos (30UL) /*!< RTR (Bit 30) */ +#define CAN2_TFI1_RTR_Msk (0x40000000UL) /*!< RTR (Bitfield-Mask: 0x01) */ +#define CAN2_TFI1_FF_Pos (31UL) /*!< FF (Bit 31) */ +#define CAN2_TFI1_FF_Msk (0x80000000UL) /*!< FF (Bitfield-Mask: 0x01) */ +/* ========================================================= TFI2 ========================================================== */ +#define CAN2_TFI2_PRIO_Pos (0UL) /*!< PRIO (Bit 0) */ +#define CAN2_TFI2_PRIO_Msk (0xffUL) /*!< PRIO (Bitfield-Mask: 0xff) */ +#define CAN2_TFI2_DLC_Pos (16UL) /*!< DLC (Bit 16) */ +#define CAN2_TFI2_DLC_Msk (0xf0000UL) /*!< DLC (Bitfield-Mask: 0x0f) */ +#define CAN2_TFI2_RTR_Pos (30UL) /*!< RTR (Bit 30) */ +#define CAN2_TFI2_RTR_Msk (0x40000000UL) /*!< RTR (Bitfield-Mask: 0x01) */ +#define CAN2_TFI2_FF_Pos (31UL) /*!< FF (Bit 31) */ +#define CAN2_TFI2_FF_Msk (0x80000000UL) /*!< FF (Bitfield-Mask: 0x01) */ +/* ========================================================= TFI3 ========================================================== */ +#define CAN2_TFI3_PRIO_Pos (0UL) /*!< PRIO (Bit 0) */ +#define CAN2_TFI3_PRIO_Msk (0xffUL) /*!< PRIO (Bitfield-Mask: 0xff) */ +#define CAN2_TFI3_DLC_Pos (16UL) /*!< DLC (Bit 16) */ +#define CAN2_TFI3_DLC_Msk (0xf0000UL) /*!< DLC (Bitfield-Mask: 0x0f) */ +#define CAN2_TFI3_RTR_Pos (30UL) /*!< RTR (Bit 30) */ +#define CAN2_TFI3_RTR_Msk (0x40000000UL) /*!< RTR (Bitfield-Mask: 0x01) */ +#define CAN2_TFI3_FF_Pos (31UL) /*!< FF (Bit 31) */ +#define CAN2_TFI3_FF_Msk (0x80000000UL) /*!< FF (Bitfield-Mask: 0x01) */ +/* ========================================================= TID1 ========================================================== */ +#define CAN2_TID1_ID_Pos (0UL) /*!< ID (Bit 0) */ +#define CAN2_TID1_ID_Msk (0x7ffUL) /*!< ID (Bitfield-Mask: 0x7ff) */ +/* ========================================================= TID2 ========================================================== */ +#define CAN2_TID2_ID_Pos (0UL) /*!< ID (Bit 0) */ +#define CAN2_TID2_ID_Msk (0x7ffUL) /*!< ID (Bitfield-Mask: 0x7ff) */ +/* ========================================================= TID3 ========================================================== */ +#define CAN2_TID3_ID_Pos (0UL) /*!< ID (Bit 0) */ +#define CAN2_TID3_ID_Msk (0x7ffUL) /*!< ID (Bitfield-Mask: 0x7ff) */ +/* ========================================================= TDA1 ========================================================== */ +#define CAN2_TDA1_DATA1_Pos (0UL) /*!< DATA1 (Bit 0) */ +#define CAN2_TDA1_DATA1_Msk (0xffUL) /*!< DATA1 (Bitfield-Mask: 0xff) */ +#define CAN2_TDA1_DATA2_Pos (8UL) /*!< DATA2 (Bit 8) */ +#define CAN2_TDA1_DATA2_Msk (0xff00UL) /*!< DATA2 (Bitfield-Mask: 0xff) */ +#define CAN2_TDA1_DATA3_Pos (16UL) /*!< DATA3 (Bit 16) */ +#define CAN2_TDA1_DATA3_Msk (0xff0000UL) /*!< DATA3 (Bitfield-Mask: 0xff) */ +#define CAN2_TDA1_DATA4_Pos (24UL) /*!< DATA4 (Bit 24) */ +#define CAN2_TDA1_DATA4_Msk (0xff000000UL) /*!< DATA4 (Bitfield-Mask: 0xff) */ +/* ========================================================= TDA2 ========================================================== */ +#define CAN2_TDA2_DATA1_Pos (0UL) /*!< DATA1 (Bit 0) */ +#define CAN2_TDA2_DATA1_Msk (0xffUL) /*!< DATA1 (Bitfield-Mask: 0xff) */ +#define CAN2_TDA2_DATA2_Pos (8UL) /*!< DATA2 (Bit 8) */ +#define CAN2_TDA2_DATA2_Msk (0xff00UL) /*!< DATA2 (Bitfield-Mask: 0xff) */ +#define CAN2_TDA2_DATA3_Pos (16UL) /*!< DATA3 (Bit 16) */ +#define CAN2_TDA2_DATA3_Msk (0xff0000UL) /*!< DATA3 (Bitfield-Mask: 0xff) */ +#define CAN2_TDA2_DATA4_Pos (24UL) /*!< DATA4 (Bit 24) */ +#define CAN2_TDA2_DATA4_Msk (0xff000000UL) /*!< DATA4 (Bitfield-Mask: 0xff) */ +/* ========================================================= TDA3 ========================================================== */ +#define CAN2_TDA3_DATA1_Pos (0UL) /*!< DATA1 (Bit 0) */ +#define CAN2_TDA3_DATA1_Msk (0xffUL) /*!< DATA1 (Bitfield-Mask: 0xff) */ +#define CAN2_TDA3_DATA2_Pos (8UL) /*!< DATA2 (Bit 8) */ +#define CAN2_TDA3_DATA2_Msk (0xff00UL) /*!< DATA2 (Bitfield-Mask: 0xff) */ +#define CAN2_TDA3_DATA3_Pos (16UL) /*!< DATA3 (Bit 16) */ +#define CAN2_TDA3_DATA3_Msk (0xff0000UL) /*!< DATA3 (Bitfield-Mask: 0xff) */ +#define CAN2_TDA3_DATA4_Pos (24UL) /*!< DATA4 (Bit 24) */ +#define CAN2_TDA3_DATA4_Msk (0xff000000UL) /*!< DATA4 (Bitfield-Mask: 0xff) */ +/* ========================================================= TDB1 ========================================================== */ +#define CAN2_TDB1_DATA5_Pos (0UL) /*!< DATA5 (Bit 0) */ +#define CAN2_TDB1_DATA5_Msk (0xffUL) /*!< DATA5 (Bitfield-Mask: 0xff) */ +#define CAN2_TDB1_DATA6_Pos (8UL) /*!< DATA6 (Bit 8) */ +#define CAN2_TDB1_DATA6_Msk (0xff00UL) /*!< DATA6 (Bitfield-Mask: 0xff) */ +#define CAN2_TDB1_DATA7_Pos (16UL) /*!< DATA7 (Bit 16) */ +#define CAN2_TDB1_DATA7_Msk (0xff0000UL) /*!< DATA7 (Bitfield-Mask: 0xff) */ +#define CAN2_TDB1_DATA8_Pos (24UL) /*!< DATA8 (Bit 24) */ +#define CAN2_TDB1_DATA8_Msk (0xff000000UL) /*!< DATA8 (Bitfield-Mask: 0xff) */ +/* ========================================================= TDB2 ========================================================== */ +#define CAN2_TDB2_DATA5_Pos (0UL) /*!< DATA5 (Bit 0) */ +#define CAN2_TDB2_DATA5_Msk (0xffUL) /*!< DATA5 (Bitfield-Mask: 0xff) */ +#define CAN2_TDB2_DATA6_Pos (8UL) /*!< DATA6 (Bit 8) */ +#define CAN2_TDB2_DATA6_Msk (0xff00UL) /*!< DATA6 (Bitfield-Mask: 0xff) */ +#define CAN2_TDB2_DATA7_Pos (16UL) /*!< DATA7 (Bit 16) */ +#define CAN2_TDB2_DATA7_Msk (0xff0000UL) /*!< DATA7 (Bitfield-Mask: 0xff) */ +#define CAN2_TDB2_DATA8_Pos (24UL) /*!< DATA8 (Bit 24) */ +#define CAN2_TDB2_DATA8_Msk (0xff000000UL) /*!< DATA8 (Bitfield-Mask: 0xff) */ +/* ========================================================= TDB3 ========================================================== */ +#define CAN2_TDB3_DATA5_Pos (0UL) /*!< DATA5 (Bit 0) */ +#define CAN2_TDB3_DATA5_Msk (0xffUL) /*!< DATA5 (Bitfield-Mask: 0xff) */ +#define CAN2_TDB3_DATA6_Pos (8UL) /*!< DATA6 (Bit 8) */ +#define CAN2_TDB3_DATA6_Msk (0xff00UL) /*!< DATA6 (Bitfield-Mask: 0xff) */ +#define CAN2_TDB3_DATA7_Pos (16UL) /*!< DATA7 (Bit 16) */ +#define CAN2_TDB3_DATA7_Msk (0xff0000UL) /*!< DATA7 (Bitfield-Mask: 0xff) */ +#define CAN2_TDB3_DATA8_Pos (24UL) /*!< DATA8 (Bit 24) */ +#define CAN2_TDB3_DATA8_Msk (0xff000000UL) /*!< DATA8 (Bitfield-Mask: 0xff) */ + + +/* =========================================================================================================================== */ +/* ================ LPC_SSP0 ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== CR0 ========================================================== */ +#define SSP0_CR0_DSS_Pos (0UL) /*!< DSS (Bit 0) */ +#define SSP0_CR0_DSS_Msk (0xfUL) /*!< DSS (Bitfield-Mask: 0x0f) */ +#define SSP0_CR0_FRF_Pos (4UL) /*!< FRF (Bit 4) */ +#define SSP0_CR0_FRF_Msk (0x30UL) /*!< FRF (Bitfield-Mask: 0x03) */ +#define SSP0_CR0_CPOL_Pos (6UL) /*!< CPOL (Bit 6) */ +#define SSP0_CR0_CPOL_Msk (0x40UL) /*!< CPOL (Bitfield-Mask: 0x01) */ +#define SSP0_CR0_CPHA_Pos (7UL) /*!< CPHA (Bit 7) */ +#define SSP0_CR0_CPHA_Msk (0x80UL) /*!< CPHA (Bitfield-Mask: 0x01) */ +#define SSP0_CR0_SCR_Pos (8UL) /*!< SCR (Bit 8) */ +#define SSP0_CR0_SCR_Msk (0xff00UL) /*!< SCR (Bitfield-Mask: 0xff) */ +/* ========================================================== CR1 ========================================================== */ +#define SSP0_CR1_LBM_Pos (0UL) /*!< LBM (Bit 0) */ +#define SSP0_CR1_LBM_Msk (0x1UL) /*!< LBM (Bitfield-Mask: 0x01) */ +#define SSP0_CR1_SSE_Pos (1UL) /*!< SSE (Bit 1) */ +#define SSP0_CR1_SSE_Msk (0x2UL) /*!< SSE (Bitfield-Mask: 0x01) */ +#define SSP0_CR1_MS_Pos (2UL) /*!< MS (Bit 2) */ +#define SSP0_CR1_MS_Msk (0x4UL) /*!< MS (Bitfield-Mask: 0x01) */ +#define SSP0_CR1_SOD_Pos (3UL) /*!< SOD (Bit 3) */ +#define SSP0_CR1_SOD_Msk (0x8UL) /*!< SOD (Bitfield-Mask: 0x01) */ +/* ========================================================== DR =========================================================== */ +#define SSP0_DR_DATA_Pos (0UL) /*!< DATA (Bit 0) */ +#define SSP0_DR_DATA_Msk (0xffffUL) /*!< DATA (Bitfield-Mask: 0xffff) */ +/* ========================================================== SR =========================================================== */ +#define SSP0_SR_TFE_Pos (0UL) /*!< TFE (Bit 0) */ +#define SSP0_SR_TFE_Msk (0x1UL) /*!< TFE (Bitfield-Mask: 0x01) */ +#define SSP0_SR_TNF_Pos (1UL) /*!< TNF (Bit 1) */ +#define SSP0_SR_TNF_Msk (0x2UL) /*!< TNF (Bitfield-Mask: 0x01) */ +#define SSP0_SR_RNE_Pos (2UL) /*!< RNE (Bit 2) */ +#define SSP0_SR_RNE_Msk (0x4UL) /*!< RNE (Bitfield-Mask: 0x01) */ +#define SSP0_SR_RFF_Pos (3UL) /*!< RFF (Bit 3) */ +#define SSP0_SR_RFF_Msk (0x8UL) /*!< RFF (Bitfield-Mask: 0x01) */ +#define SSP0_SR_BSY_Pos (4UL) /*!< BSY (Bit 4) */ +#define SSP0_SR_BSY_Msk (0x10UL) /*!< BSY (Bitfield-Mask: 0x01) */ +/* ========================================================= CPSR ========================================================== */ +#define SSP0_CPSR_CPSDVSR_Pos (0UL) /*!< CPSDVSR (Bit 0) */ +#define SSP0_CPSR_CPSDVSR_Msk (0xffUL) /*!< CPSDVSR (Bitfield-Mask: 0xff) */ +/* ========================================================= IMSC ========================================================== */ +#define SSP0_IMSC_RORIM_Pos (0UL) /*!< RORIM (Bit 0) */ +#define SSP0_IMSC_RORIM_Msk (0x1UL) /*!< RORIM (Bitfield-Mask: 0x01) */ +#define SSP0_IMSC_RTIM_Pos (1UL) /*!< RTIM (Bit 1) */ +#define SSP0_IMSC_RTIM_Msk (0x2UL) /*!< RTIM (Bitfield-Mask: 0x01) */ +#define SSP0_IMSC_RXIM_Pos (2UL) /*!< RXIM (Bit 2) */ +#define SSP0_IMSC_RXIM_Msk (0x4UL) /*!< RXIM (Bitfield-Mask: 0x01) */ +#define SSP0_IMSC_TXIM_Pos (3UL) /*!< TXIM (Bit 3) */ +#define SSP0_IMSC_TXIM_Msk (0x8UL) /*!< TXIM (Bitfield-Mask: 0x01) */ +/* ========================================================== RIS ========================================================== */ +#define SSP0_RIS_RORRIS_Pos (0UL) /*!< RORRIS (Bit 0) */ +#define SSP0_RIS_RORRIS_Msk (0x1UL) /*!< RORRIS (Bitfield-Mask: 0x01) */ +#define SSP0_RIS_RTRIS_Pos (1UL) /*!< RTRIS (Bit 1) */ +#define SSP0_RIS_RTRIS_Msk (0x2UL) /*!< RTRIS (Bitfield-Mask: 0x01) */ +#define SSP0_RIS_RXRIS_Pos (2UL) /*!< RXRIS (Bit 2) */ +#define SSP0_RIS_RXRIS_Msk (0x4UL) /*!< RXRIS (Bitfield-Mask: 0x01) */ +#define SSP0_RIS_TXRIS_Pos (3UL) /*!< TXRIS (Bit 3) */ +#define SSP0_RIS_TXRIS_Msk (0x8UL) /*!< TXRIS (Bitfield-Mask: 0x01) */ +/* ========================================================== MIS ========================================================== */ +#define SSP0_MIS_RORMIS_Pos (0UL) /*!< RORMIS (Bit 0) */ +#define SSP0_MIS_RORMIS_Msk (0x1UL) /*!< RORMIS (Bitfield-Mask: 0x01) */ +#define SSP0_MIS_RTMIS_Pos (1UL) /*!< RTMIS (Bit 1) */ +#define SSP0_MIS_RTMIS_Msk (0x2UL) /*!< RTMIS (Bitfield-Mask: 0x01) */ +#define SSP0_MIS_RXMIS_Pos (2UL) /*!< RXMIS (Bit 2) */ +#define SSP0_MIS_RXMIS_Msk (0x4UL) /*!< RXMIS (Bitfield-Mask: 0x01) */ +#define SSP0_MIS_TXMIS_Pos (3UL) /*!< TXMIS (Bit 3) */ +#define SSP0_MIS_TXMIS_Msk (0x8UL) /*!< TXMIS (Bitfield-Mask: 0x01) */ +/* ========================================================== ICR ========================================================== */ +#define SSP0_ICR_RORIC_Pos (0UL) /*!< RORIC (Bit 0) */ +#define SSP0_ICR_RORIC_Msk (0x1UL) /*!< RORIC (Bitfield-Mask: 0x01) */ +#define SSP0_ICR_RTIC_Pos (1UL) /*!< RTIC (Bit 1) */ +#define SSP0_ICR_RTIC_Msk (0x2UL) /*!< RTIC (Bitfield-Mask: 0x01) */ +/* ========================================================= DMACR ========================================================= */ +#define SSP0_DMACR_RXDMAE_Pos (0UL) /*!< RXDMAE (Bit 0) */ +#define SSP0_DMACR_RXDMAE_Msk (0x1UL) /*!< RXDMAE (Bitfield-Mask: 0x01) */ +#define SSP0_DMACR_TXDMAE_Pos (1UL) /*!< TXDMAE (Bit 1) */ +#define SSP0_DMACR_TXDMAE_Msk (0x2UL) /*!< TXDMAE (Bitfield-Mask: 0x01) */ + + +/* =========================================================================================================================== */ +/* ================ LPC_DAC ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== CR =========================================================== */ +#define DAC_CR_VALUE_Pos (6UL) /*!< VALUE (Bit 6) */ +#define DAC_CR_VALUE_Msk (0xffc0UL) /*!< VALUE (Bitfield-Mask: 0x3ff) */ +#define DAC_CR_BIAS_Pos (16UL) /*!< BIAS (Bit 16) */ +#define DAC_CR_BIAS_Msk (0x10000UL) /*!< BIAS (Bitfield-Mask: 0x01) */ +/* ========================================================= CTRL ========================================================== */ +#define DAC_CTRL_INT_DMA_REQ_Pos (0UL) /*!< INT_DMA_REQ (Bit 0) */ +#define DAC_CTRL_INT_DMA_REQ_Msk (0x1UL) /*!< INT_DMA_REQ (Bitfield-Mask: 0x01) */ +#define DAC_CTRL_DBLBUF_ENA_Pos (1UL) /*!< DBLBUF_ENA (Bit 1) */ +#define DAC_CTRL_DBLBUF_ENA_Msk (0x2UL) /*!< DBLBUF_ENA (Bitfield-Mask: 0x01) */ +#define DAC_CTRL_CNT_ENA_Pos (2UL) /*!< CNT_ENA (Bit 2) */ +#define DAC_CTRL_CNT_ENA_Msk (0x4UL) /*!< CNT_ENA (Bitfield-Mask: 0x01) */ +#define DAC_CTRL_DMA_ENA_Pos (3UL) /*!< DMA_ENA (Bit 3) */ +#define DAC_CTRL_DMA_ENA_Msk (0x8UL) /*!< DMA_ENA (Bitfield-Mask: 0x01) */ +/* ======================================================== CNTVAL ========================================================= */ +#define DAC_CNTVAL_VALUE_Pos (0UL) /*!< VALUE (Bit 0) */ +#define DAC_CNTVAL_VALUE_Msk (0xffffUL) /*!< VALUE (Bitfield-Mask: 0xffff) */ + + +/* =========================================================================================================================== */ +/* ================ LPC_TIMER2 ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== IR =========================================================== */ +#define TIMER2_IR_MR0INT_Pos (0UL) /*!< MR0INT (Bit 0) */ +#define TIMER2_IR_MR0INT_Msk (0x1UL) /*!< MR0INT (Bitfield-Mask: 0x01) */ +#define TIMER2_IR_MR1INT_Pos (1UL) /*!< MR1INT (Bit 1) */ +#define TIMER2_IR_MR1INT_Msk (0x2UL) /*!< MR1INT (Bitfield-Mask: 0x01) */ +#define TIMER2_IR_MR2INT_Pos (2UL) /*!< MR2INT (Bit 2) */ +#define TIMER2_IR_MR2INT_Msk (0x4UL) /*!< MR2INT (Bitfield-Mask: 0x01) */ +#define TIMER2_IR_MR3INT_Pos (3UL) /*!< MR3INT (Bit 3) */ +#define TIMER2_IR_MR3INT_Msk (0x8UL) /*!< MR3INT (Bitfield-Mask: 0x01) */ +#define TIMER2_IR_CR0INT_Pos (4UL) /*!< CR0INT (Bit 4) */ +#define TIMER2_IR_CR0INT_Msk (0x10UL) /*!< CR0INT (Bitfield-Mask: 0x01) */ +#define TIMER2_IR_CR1INT_Pos (5UL) /*!< CR1INT (Bit 5) */ +#define TIMER2_IR_CR1INT_Msk (0x20UL) /*!< CR1INT (Bitfield-Mask: 0x01) */ +/* ========================================================== TCR ========================================================== */ +#define TIMER2_TCR_CEN_Pos (0UL) /*!< CEN (Bit 0) */ +#define TIMER2_TCR_CEN_Msk (0x1UL) /*!< CEN (Bitfield-Mask: 0x01) */ +#define TIMER2_TCR_CRST_Pos (1UL) /*!< CRST (Bit 1) */ +#define TIMER2_TCR_CRST_Msk (0x2UL) /*!< CRST (Bitfield-Mask: 0x01) */ +/* ========================================================== TC =========================================================== */ +#define TIMER2_TC_TC_Pos (0UL) /*!< TC (Bit 0) */ +#define TIMER2_TC_TC_Msk (0xffffffffUL) /*!< TC (Bitfield-Mask: 0xffffffff) */ +/* ========================================================== PR =========================================================== */ +#define TIMER2_PR_PM_Pos (0UL) /*!< PM (Bit 0) */ +#define TIMER2_PR_PM_Msk (0xffffffffUL) /*!< PM (Bitfield-Mask: 0xffffffff) */ +/* ========================================================== PC =========================================================== */ +#define TIMER2_PC_PC_Pos (0UL) /*!< PC (Bit 0) */ +#define TIMER2_PC_PC_Msk (0xffffffffUL) /*!< PC (Bitfield-Mask: 0xffffffff) */ +/* ========================================================== MCR ========================================================== */ +#define TIMER2_MCR_MR0I_Pos (0UL) /*!< MR0I (Bit 0) */ +#define TIMER2_MCR_MR0I_Msk (0x1UL) /*!< MR0I (Bitfield-Mask: 0x01) */ +#define TIMER2_MCR_MR0R_Pos (1UL) /*!< MR0R (Bit 1) */ +#define TIMER2_MCR_MR0R_Msk (0x2UL) /*!< MR0R (Bitfield-Mask: 0x01) */ +#define TIMER2_MCR_MR0S_Pos (2UL) /*!< MR0S (Bit 2) */ +#define TIMER2_MCR_MR0S_Msk (0x4UL) /*!< MR0S (Bitfield-Mask: 0x01) */ +#define TIMER2_MCR_MR1I_Pos (3UL) /*!< MR1I (Bit 3) */ +#define TIMER2_MCR_MR1I_Msk (0x8UL) /*!< MR1I (Bitfield-Mask: 0x01) */ +#define TIMER2_MCR_MR1R_Pos (4UL) /*!< MR1R (Bit 4) */ +#define TIMER2_MCR_MR1R_Msk (0x10UL) /*!< MR1R (Bitfield-Mask: 0x01) */ +#define TIMER2_MCR_MR1S_Pos (5UL) /*!< MR1S (Bit 5) */ +#define TIMER2_MCR_MR1S_Msk (0x20UL) /*!< MR1S (Bitfield-Mask: 0x01) */ +#define TIMER2_MCR_MR2I_Pos (6UL) /*!< MR2I (Bit 6) */ +#define TIMER2_MCR_MR2I_Msk (0x40UL) /*!< MR2I (Bitfield-Mask: 0x01) */ +#define TIMER2_MCR_MR2R_Pos (7UL) /*!< MR2R (Bit 7) */ +#define TIMER2_MCR_MR2R_Msk (0x80UL) /*!< MR2R (Bitfield-Mask: 0x01) */ +#define TIMER2_MCR_MR2S_Pos (8UL) /*!< MR2S (Bit 8) */ +#define TIMER2_MCR_MR2S_Msk (0x100UL) /*!< MR2S (Bitfield-Mask: 0x01) */ +#define TIMER2_MCR_MR3I_Pos (9UL) /*!< MR3I (Bit 9) */ +#define TIMER2_MCR_MR3I_Msk (0x200UL) /*!< MR3I (Bitfield-Mask: 0x01) */ +#define TIMER2_MCR_MR3R_Pos (10UL) /*!< MR3R (Bit 10) */ +#define TIMER2_MCR_MR3R_Msk (0x400UL) /*!< MR3R (Bitfield-Mask: 0x01) */ +#define TIMER2_MCR_MR3S_Pos (11UL) /*!< MR3S (Bit 11) */ +#define TIMER2_MCR_MR3S_Msk (0x800UL) /*!< MR3S (Bitfield-Mask: 0x01) */ +/* ========================================================== CCR ========================================================== */ +#define TIMER2_CCR_CAP0RE_Pos (0UL) /*!< CAP0RE (Bit 0) */ +#define TIMER2_CCR_CAP0RE_Msk (0x1UL) /*!< CAP0RE (Bitfield-Mask: 0x01) */ +#define TIMER2_CCR_CAP0FE_Pos (1UL) /*!< CAP0FE (Bit 1) */ +#define TIMER2_CCR_CAP0FE_Msk (0x2UL) /*!< CAP0FE (Bitfield-Mask: 0x01) */ +#define TIMER2_CCR_CAP0I_Pos (2UL) /*!< CAP0I (Bit 2) */ +#define TIMER2_CCR_CAP0I_Msk (0x4UL) /*!< CAP0I (Bitfield-Mask: 0x01) */ +#define TIMER2_CCR_CAP1RE_Pos (3UL) /*!< CAP1RE (Bit 3) */ +#define TIMER2_CCR_CAP1RE_Msk (0x8UL) /*!< CAP1RE (Bitfield-Mask: 0x01) */ +#define TIMER2_CCR_CAP1FE_Pos (4UL) /*!< CAP1FE (Bit 4) */ +#define TIMER2_CCR_CAP1FE_Msk (0x10UL) /*!< CAP1FE (Bitfield-Mask: 0x01) */ +#define TIMER2_CCR_CAP1I_Pos (5UL) /*!< CAP1I (Bit 5) */ +#define TIMER2_CCR_CAP1I_Msk (0x20UL) /*!< CAP1I (Bitfield-Mask: 0x01) */ +/* ========================================================== EMR ========================================================== */ +#define TIMER2_EMR_EM0_Pos (0UL) /*!< EM0 (Bit 0) */ +#define TIMER2_EMR_EM0_Msk (0x1UL) /*!< EM0 (Bitfield-Mask: 0x01) */ +#define TIMER2_EMR_EM1_Pos (1UL) /*!< EM1 (Bit 1) */ +#define TIMER2_EMR_EM1_Msk (0x2UL) /*!< EM1 (Bitfield-Mask: 0x01) */ +#define TIMER2_EMR_EM2_Pos (2UL) /*!< EM2 (Bit 2) */ +#define TIMER2_EMR_EM2_Msk (0x4UL) /*!< EM2 (Bitfield-Mask: 0x01) */ +#define TIMER2_EMR_EM3_Pos (3UL) /*!< EM3 (Bit 3) */ +#define TIMER2_EMR_EM3_Msk (0x8UL) /*!< EM3 (Bitfield-Mask: 0x01) */ +#define TIMER2_EMR_EMC0_Pos (4UL) /*!< EMC0 (Bit 4) */ +#define TIMER2_EMR_EMC0_Msk (0x30UL) /*!< EMC0 (Bitfield-Mask: 0x03) */ +#define TIMER2_EMR_EMC1_Pos (6UL) /*!< EMC1 (Bit 6) */ +#define TIMER2_EMR_EMC1_Msk (0xc0UL) /*!< EMC1 (Bitfield-Mask: 0x03) */ +#define TIMER2_EMR_EMC2_Pos (8UL) /*!< EMC2 (Bit 8) */ +#define TIMER2_EMR_EMC2_Msk (0x300UL) /*!< EMC2 (Bitfield-Mask: 0x03) */ +#define TIMER2_EMR_EMC3_Pos (10UL) /*!< EMC3 (Bit 10) */ +#define TIMER2_EMR_EMC3_Msk (0xc00UL) /*!< EMC3 (Bitfield-Mask: 0x03) */ +/* ========================================================= CTCR ========================================================== */ +#define TIMER2_CTCR_CTMODE_Pos (0UL) /*!< CTMODE (Bit 0) */ +#define TIMER2_CTCR_CTMODE_Msk (0x3UL) /*!< CTMODE (Bitfield-Mask: 0x03) */ +#define TIMER2_CTCR_CINSEL_Pos (2UL) /*!< CINSEL (Bit 2) */ +#define TIMER2_CTCR_CINSEL_Msk (0xcUL) /*!< CINSEL (Bitfield-Mask: 0x03) */ + + +/* =========================================================================================================================== */ +/* ================ LPC_TIMER3 ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== IR =========================================================== */ +#define TIMER3_IR_MR0INT_Pos (0UL) /*!< MR0INT (Bit 0) */ +#define TIMER3_IR_MR0INT_Msk (0x1UL) /*!< MR0INT (Bitfield-Mask: 0x01) */ +#define TIMER3_IR_MR1INT_Pos (1UL) /*!< MR1INT (Bit 1) */ +#define TIMER3_IR_MR1INT_Msk (0x2UL) /*!< MR1INT (Bitfield-Mask: 0x01) */ +#define TIMER3_IR_MR2INT_Pos (2UL) /*!< MR2INT (Bit 2) */ +#define TIMER3_IR_MR2INT_Msk (0x4UL) /*!< MR2INT (Bitfield-Mask: 0x01) */ +#define TIMER3_IR_MR3INT_Pos (3UL) /*!< MR3INT (Bit 3) */ +#define TIMER3_IR_MR3INT_Msk (0x8UL) /*!< MR3INT (Bitfield-Mask: 0x01) */ +#define TIMER3_IR_CR0INT_Pos (4UL) /*!< CR0INT (Bit 4) */ +#define TIMER3_IR_CR0INT_Msk (0x10UL) /*!< CR0INT (Bitfield-Mask: 0x01) */ +#define TIMER3_IR_CR1INT_Pos (5UL) /*!< CR1INT (Bit 5) */ +#define TIMER3_IR_CR1INT_Msk (0x20UL) /*!< CR1INT (Bitfield-Mask: 0x01) */ +/* ========================================================== TCR ========================================================== */ +#define TIMER3_TCR_CEN_Pos (0UL) /*!< CEN (Bit 0) */ +#define TIMER3_TCR_CEN_Msk (0x1UL) /*!< CEN (Bitfield-Mask: 0x01) */ +#define TIMER3_TCR_CRST_Pos (1UL) /*!< CRST (Bit 1) */ +#define TIMER3_TCR_CRST_Msk (0x2UL) /*!< CRST (Bitfield-Mask: 0x01) */ +/* ========================================================== TC =========================================================== */ +#define TIMER3_TC_TC_Pos (0UL) /*!< TC (Bit 0) */ +#define TIMER3_TC_TC_Msk (0xffffffffUL) /*!< TC (Bitfield-Mask: 0xffffffff) */ +/* ========================================================== PR =========================================================== */ +#define TIMER3_PR_PM_Pos (0UL) /*!< PM (Bit 0) */ +#define TIMER3_PR_PM_Msk (0xffffffffUL) /*!< PM (Bitfield-Mask: 0xffffffff) */ +/* ========================================================== PC =========================================================== */ +#define TIMER3_PC_PC_Pos (0UL) /*!< PC (Bit 0) */ +#define TIMER3_PC_PC_Msk (0xffffffffUL) /*!< PC (Bitfield-Mask: 0xffffffff) */ +/* ========================================================== MCR ========================================================== */ +#define TIMER3_MCR_MR0I_Pos (0UL) /*!< MR0I (Bit 0) */ +#define TIMER3_MCR_MR0I_Msk (0x1UL) /*!< MR0I (Bitfield-Mask: 0x01) */ +#define TIMER3_MCR_MR0R_Pos (1UL) /*!< MR0R (Bit 1) */ +#define TIMER3_MCR_MR0R_Msk (0x2UL) /*!< MR0R (Bitfield-Mask: 0x01) */ +#define TIMER3_MCR_MR0S_Pos (2UL) /*!< MR0S (Bit 2) */ +#define TIMER3_MCR_MR0S_Msk (0x4UL) /*!< MR0S (Bitfield-Mask: 0x01) */ +#define TIMER3_MCR_MR1I_Pos (3UL) /*!< MR1I (Bit 3) */ +#define TIMER3_MCR_MR1I_Msk (0x8UL) /*!< MR1I (Bitfield-Mask: 0x01) */ +#define TIMER3_MCR_MR1R_Pos (4UL) /*!< MR1R (Bit 4) */ +#define TIMER3_MCR_MR1R_Msk (0x10UL) /*!< MR1R (Bitfield-Mask: 0x01) */ +#define TIMER3_MCR_MR1S_Pos (5UL) /*!< MR1S (Bit 5) */ +#define TIMER3_MCR_MR1S_Msk (0x20UL) /*!< MR1S (Bitfield-Mask: 0x01) */ +#define TIMER3_MCR_MR2I_Pos (6UL) /*!< MR2I (Bit 6) */ +#define TIMER3_MCR_MR2I_Msk (0x40UL) /*!< MR2I (Bitfield-Mask: 0x01) */ +#define TIMER3_MCR_MR2R_Pos (7UL) /*!< MR2R (Bit 7) */ +#define TIMER3_MCR_MR2R_Msk (0x80UL) /*!< MR2R (Bitfield-Mask: 0x01) */ +#define TIMER3_MCR_MR2S_Pos (8UL) /*!< MR2S (Bit 8) */ +#define TIMER3_MCR_MR2S_Msk (0x100UL) /*!< MR2S (Bitfield-Mask: 0x01) */ +#define TIMER3_MCR_MR3I_Pos (9UL) /*!< MR3I (Bit 9) */ +#define TIMER3_MCR_MR3I_Msk (0x200UL) /*!< MR3I (Bitfield-Mask: 0x01) */ +#define TIMER3_MCR_MR3R_Pos (10UL) /*!< MR3R (Bit 10) */ +#define TIMER3_MCR_MR3R_Msk (0x400UL) /*!< MR3R (Bitfield-Mask: 0x01) */ +#define TIMER3_MCR_MR3S_Pos (11UL) /*!< MR3S (Bit 11) */ +#define TIMER3_MCR_MR3S_Msk (0x800UL) /*!< MR3S (Bitfield-Mask: 0x01) */ +/* ========================================================== CCR ========================================================== */ +#define TIMER3_CCR_CAP0RE_Pos (0UL) /*!< CAP0RE (Bit 0) */ +#define TIMER3_CCR_CAP0RE_Msk (0x1UL) /*!< CAP0RE (Bitfield-Mask: 0x01) */ +#define TIMER3_CCR_CAP0FE_Pos (1UL) /*!< CAP0FE (Bit 1) */ +#define TIMER3_CCR_CAP0FE_Msk (0x2UL) /*!< CAP0FE (Bitfield-Mask: 0x01) */ +#define TIMER3_CCR_CAP0I_Pos (2UL) /*!< CAP0I (Bit 2) */ +#define TIMER3_CCR_CAP0I_Msk (0x4UL) /*!< CAP0I (Bitfield-Mask: 0x01) */ +#define TIMER3_CCR_CAP1RE_Pos (3UL) /*!< CAP1RE (Bit 3) */ +#define TIMER3_CCR_CAP1RE_Msk (0x8UL) /*!< CAP1RE (Bitfield-Mask: 0x01) */ +#define TIMER3_CCR_CAP1FE_Pos (4UL) /*!< CAP1FE (Bit 4) */ +#define TIMER3_CCR_CAP1FE_Msk (0x10UL) /*!< CAP1FE (Bitfield-Mask: 0x01) */ +#define TIMER3_CCR_CAP1I_Pos (5UL) /*!< CAP1I (Bit 5) */ +#define TIMER3_CCR_CAP1I_Msk (0x20UL) /*!< CAP1I (Bitfield-Mask: 0x01) */ +/* ========================================================== EMR ========================================================== */ +#define TIMER3_EMR_EM0_Pos (0UL) /*!< EM0 (Bit 0) */ +#define TIMER3_EMR_EM0_Msk (0x1UL) /*!< EM0 (Bitfield-Mask: 0x01) */ +#define TIMER3_EMR_EM1_Pos (1UL) /*!< EM1 (Bit 1) */ +#define TIMER3_EMR_EM1_Msk (0x2UL) /*!< EM1 (Bitfield-Mask: 0x01) */ +#define TIMER3_EMR_EM2_Pos (2UL) /*!< EM2 (Bit 2) */ +#define TIMER3_EMR_EM2_Msk (0x4UL) /*!< EM2 (Bitfield-Mask: 0x01) */ +#define TIMER3_EMR_EM3_Pos (3UL) /*!< EM3 (Bit 3) */ +#define TIMER3_EMR_EM3_Msk (0x8UL) /*!< EM3 (Bitfield-Mask: 0x01) */ +#define TIMER3_EMR_EMC0_Pos (4UL) /*!< EMC0 (Bit 4) */ +#define TIMER3_EMR_EMC0_Msk (0x30UL) /*!< EMC0 (Bitfield-Mask: 0x03) */ +#define TIMER3_EMR_EMC1_Pos (6UL) /*!< EMC1 (Bit 6) */ +#define TIMER3_EMR_EMC1_Msk (0xc0UL) /*!< EMC1 (Bitfield-Mask: 0x03) */ +#define TIMER3_EMR_EMC2_Pos (8UL) /*!< EMC2 (Bit 8) */ +#define TIMER3_EMR_EMC2_Msk (0x300UL) /*!< EMC2 (Bitfield-Mask: 0x03) */ +#define TIMER3_EMR_EMC3_Pos (10UL) /*!< EMC3 (Bit 10) */ +#define TIMER3_EMR_EMC3_Msk (0xc00UL) /*!< EMC3 (Bitfield-Mask: 0x03) */ +/* ========================================================= CTCR ========================================================== */ +#define TIMER3_CTCR_CTMODE_Pos (0UL) /*!< CTMODE (Bit 0) */ +#define TIMER3_CTCR_CTMODE_Msk (0x3UL) /*!< CTMODE (Bitfield-Mask: 0x03) */ +#define TIMER3_CTCR_CINSEL_Pos (2UL) /*!< CINSEL (Bit 2) */ +#define TIMER3_CTCR_CINSEL_Msk (0xcUL) /*!< CINSEL (Bitfield-Mask: 0x03) */ + + +/* =========================================================================================================================== */ +/* ================ LPC_UART2 ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== RBR ========================================================== */ +#define UART2_RBR_RBR_Pos (0UL) /*!< RBR (Bit 0) */ +#define UART2_RBR_RBR_Msk (0xffUL) /*!< RBR (Bitfield-Mask: 0xff) */ +/* ========================================================== THR ========================================================== */ +#define UART2_THR_THR_Pos (0UL) /*!< THR (Bit 0) */ +#define UART2_THR_THR_Msk (0xffUL) /*!< THR (Bitfield-Mask: 0xff) */ +/* ========================================================== DLL ========================================================== */ +#define UART2_DLL_DLLSB_Pos (0UL) /*!< DLLSB (Bit 0) */ +#define UART2_DLL_DLLSB_Msk (0xffUL) /*!< DLLSB (Bitfield-Mask: 0xff) */ +/* ========================================================== DLM ========================================================== */ +#define UART2_DLM_DLMSB_Pos (0UL) /*!< DLMSB (Bit 0) */ +#define UART2_DLM_DLMSB_Msk (0xffUL) /*!< DLMSB (Bitfield-Mask: 0xff) */ +/* ========================================================== IER ========================================================== */ +#define UART2_IER_RBRIE_Pos (0UL) /*!< RBRIE (Bit 0) */ +#define UART2_IER_RBRIE_Msk (0x1UL) /*!< RBRIE (Bitfield-Mask: 0x01) */ +#define UART2_IER_THREIE_Pos (1UL) /*!< THREIE (Bit 1) */ +#define UART2_IER_THREIE_Msk (0x2UL) /*!< THREIE (Bitfield-Mask: 0x01) */ +#define UART2_IER_RXIE_Pos (2UL) /*!< RXIE (Bit 2) */ +#define UART2_IER_RXIE_Msk (0x4UL) /*!< RXIE (Bitfield-Mask: 0x01) */ +#define UART2_IER_ABEOINTEN_Pos (8UL) /*!< ABEOINTEN (Bit 8) */ +#define UART2_IER_ABEOINTEN_Msk (0x100UL) /*!< ABEOINTEN (Bitfield-Mask: 0x01) */ +#define UART2_IER_ABTOINTEN_Pos (9UL) /*!< ABTOINTEN (Bit 9) */ +#define UART2_IER_ABTOINTEN_Msk (0x200UL) /*!< ABTOINTEN (Bitfield-Mask: 0x01) */ +/* ========================================================== IIR ========================================================== */ +#define UART2_IIR_INTSTATUS_Pos (0UL) /*!< INTSTATUS (Bit 0) */ +#define UART2_IIR_INTSTATUS_Msk (0x1UL) /*!< INTSTATUS (Bitfield-Mask: 0x01) */ +#define UART2_IIR_INTID_Pos (1UL) /*!< INTID (Bit 1) */ +#define UART2_IIR_INTID_Msk (0xeUL) /*!< INTID (Bitfield-Mask: 0x07) */ +#define UART2_IIR_FIFOENABLE_Pos (6UL) /*!< FIFOENABLE (Bit 6) */ +#define UART2_IIR_FIFOENABLE_Msk (0xc0UL) /*!< FIFOENABLE (Bitfield-Mask: 0x03) */ +#define UART2_IIR_ABEOINT_Pos (8UL) /*!< ABEOINT (Bit 8) */ +#define UART2_IIR_ABEOINT_Msk (0x100UL) /*!< ABEOINT (Bitfield-Mask: 0x01) */ +#define UART2_IIR_ABTOINT_Pos (9UL) /*!< ABTOINT (Bit 9) */ +#define UART2_IIR_ABTOINT_Msk (0x200UL) /*!< ABTOINT (Bitfield-Mask: 0x01) */ +/* ========================================================== FCR ========================================================== */ +#define UART2_FCR_FIFOEN_Pos (0UL) /*!< FIFOEN (Bit 0) */ +#define UART2_FCR_FIFOEN_Msk (0x1UL) /*!< FIFOEN (Bitfield-Mask: 0x01) */ +#define UART2_FCR_RXFIFORES_Pos (1UL) /*!< RXFIFORES (Bit 1) */ +#define UART2_FCR_RXFIFORES_Msk (0x2UL) /*!< RXFIFORES (Bitfield-Mask: 0x01) */ +#define UART2_FCR_TXFIFORES_Pos (2UL) /*!< TXFIFORES (Bit 2) */ +#define UART2_FCR_TXFIFORES_Msk (0x4UL) /*!< TXFIFORES (Bitfield-Mask: 0x01) */ +#define UART2_FCR_DMAMODE_Pos (3UL) /*!< DMAMODE (Bit 3) */ +#define UART2_FCR_DMAMODE_Msk (0x8UL) /*!< DMAMODE (Bitfield-Mask: 0x01) */ +#define UART2_FCR_RXTRIGLVL_Pos (6UL) /*!< RXTRIGLVL (Bit 6) */ +#define UART2_FCR_RXTRIGLVL_Msk (0xc0UL) /*!< RXTRIGLVL (Bitfield-Mask: 0x03) */ +/* ========================================================== LCR ========================================================== */ +#define UART2_LCR_WLS_Pos (0UL) /*!< WLS (Bit 0) */ +#define UART2_LCR_WLS_Msk (0x3UL) /*!< WLS (Bitfield-Mask: 0x03) */ +#define UART2_LCR_SBS_Pos (2UL) /*!< SBS (Bit 2) */ +#define UART2_LCR_SBS_Msk (0x4UL) /*!< SBS (Bitfield-Mask: 0x01) */ +#define UART2_LCR_PE_Pos (3UL) /*!< PE (Bit 3) */ +#define UART2_LCR_PE_Msk (0x8UL) /*!< PE (Bitfield-Mask: 0x01) */ +#define UART2_LCR_PS_Pos (4UL) /*!< PS (Bit 4) */ +#define UART2_LCR_PS_Msk (0x30UL) /*!< PS (Bitfield-Mask: 0x03) */ +#define UART2_LCR_BC_Pos (6UL) /*!< BC (Bit 6) */ +#define UART2_LCR_BC_Msk (0x40UL) /*!< BC (Bitfield-Mask: 0x01) */ +#define UART2_LCR_DLAB_Pos (7UL) /*!< DLAB (Bit 7) */ +#define UART2_LCR_DLAB_Msk (0x80UL) /*!< DLAB (Bitfield-Mask: 0x01) */ +/* ========================================================== LSR ========================================================== */ +#define UART2_LSR_RDR_Pos (0UL) /*!< RDR (Bit 0) */ +#define UART2_LSR_RDR_Msk (0x1UL) /*!< RDR (Bitfield-Mask: 0x01) */ +#define UART2_LSR_OE_Pos (1UL) /*!< OE (Bit 1) */ +#define UART2_LSR_OE_Msk (0x2UL) /*!< OE (Bitfield-Mask: 0x01) */ +#define UART2_LSR_PE_Pos (2UL) /*!< PE (Bit 2) */ +#define UART2_LSR_PE_Msk (0x4UL) /*!< PE (Bitfield-Mask: 0x01) */ +#define UART2_LSR_FE_Pos (3UL) /*!< FE (Bit 3) */ +#define UART2_LSR_FE_Msk (0x8UL) /*!< FE (Bitfield-Mask: 0x01) */ +#define UART2_LSR_BI_Pos (4UL) /*!< BI (Bit 4) */ +#define UART2_LSR_BI_Msk (0x10UL) /*!< BI (Bitfield-Mask: 0x01) */ +#define UART2_LSR_THRE_Pos (5UL) /*!< THRE (Bit 5) */ +#define UART2_LSR_THRE_Msk (0x20UL) /*!< THRE (Bitfield-Mask: 0x01) */ +#define UART2_LSR_TEMT_Pos (6UL) /*!< TEMT (Bit 6) */ +#define UART2_LSR_TEMT_Msk (0x40UL) /*!< TEMT (Bitfield-Mask: 0x01) */ +#define UART2_LSR_RXFE_Pos (7UL) /*!< RXFE (Bit 7) */ +#define UART2_LSR_RXFE_Msk (0x80UL) /*!< RXFE (Bitfield-Mask: 0x01) */ +/* ========================================================== SCR ========================================================== */ +#define UART2_SCR_PAD_Pos (0UL) /*!< PAD (Bit 0) */ +#define UART2_SCR_PAD_Msk (0xffUL) /*!< PAD (Bitfield-Mask: 0xff) */ +/* ========================================================== ACR ========================================================== */ +#define UART2_ACR_START_Pos (0UL) /*!< START (Bit 0) */ +#define UART2_ACR_START_Msk (0x1UL) /*!< START (Bitfield-Mask: 0x01) */ +#define UART2_ACR_MODE_Pos (1UL) /*!< MODE (Bit 1) */ +#define UART2_ACR_MODE_Msk (0x2UL) /*!< MODE (Bitfield-Mask: 0x01) */ +#define UART2_ACR_AUTORESTART_Pos (2UL) /*!< AUTORESTART (Bit 2) */ +#define UART2_ACR_AUTORESTART_Msk (0x4UL) /*!< AUTORESTART (Bitfield-Mask: 0x01) */ +#define UART2_ACR_ABEOINTCLR_Pos (8UL) /*!< ABEOINTCLR (Bit 8) */ +#define UART2_ACR_ABEOINTCLR_Msk (0x100UL) /*!< ABEOINTCLR (Bitfield-Mask: 0x01) */ +#define UART2_ACR_ABTOINTCLR_Pos (9UL) /*!< ABTOINTCLR (Bit 9) */ +#define UART2_ACR_ABTOINTCLR_Msk (0x200UL) /*!< ABTOINTCLR (Bitfield-Mask: 0x01) */ +/* ========================================================== FDR ========================================================== */ +#define UART2_FDR_DIVADDVAL_Pos (0UL) /*!< DIVADDVAL (Bit 0) */ +#define UART2_FDR_DIVADDVAL_Msk (0xfUL) /*!< DIVADDVAL (Bitfield-Mask: 0x0f) */ +#define UART2_FDR_MULVAL_Pos (4UL) /*!< MULVAL (Bit 4) */ +#define UART2_FDR_MULVAL_Msk (0xf0UL) /*!< MULVAL (Bitfield-Mask: 0x0f) */ +/* ========================================================== TER ========================================================== */ +#define UART2_TER_TXEN_Pos (7UL) /*!< TXEN (Bit 7) */ +#define UART2_TER_TXEN_Msk (0x80UL) /*!< TXEN (Bitfield-Mask: 0x01) */ +/* ======================================================= RS485CTRL ======================================================= */ +#define UART2_RS485CTRL_NMMEN_Pos (0UL) /*!< NMMEN (Bit 0) */ +#define UART2_RS485CTRL_NMMEN_Msk (0x1UL) /*!< NMMEN (Bitfield-Mask: 0x01) */ +#define UART2_RS485CTRL_RXDIS_Pos (1UL) /*!< RXDIS (Bit 1) */ +#define UART2_RS485CTRL_RXDIS_Msk (0x2UL) /*!< RXDIS (Bitfield-Mask: 0x01) */ +#define UART2_RS485CTRL_AADEN_Pos (2UL) /*!< AADEN (Bit 2) */ +#define UART2_RS485CTRL_AADEN_Msk (0x4UL) /*!< AADEN (Bitfield-Mask: 0x01) */ +#define UART2_RS485CTRL_DCTRL_Pos (4UL) /*!< DCTRL (Bit 4) */ +#define UART2_RS485CTRL_DCTRL_Msk (0x10UL) /*!< DCTRL (Bitfield-Mask: 0x01) */ +#define UART2_RS485CTRL_OINV_Pos (5UL) /*!< OINV (Bit 5) */ +#define UART2_RS485CTRL_OINV_Msk (0x20UL) /*!< OINV (Bitfield-Mask: 0x01) */ +/* ===================================================== RS485ADRMATCH ===================================================== */ +#define UART2_RS485ADRMATCH_ADRMATCH_Pos (0UL) /*!< ADRMATCH (Bit 0) */ +#define UART2_RS485ADRMATCH_ADRMATCH_Msk (0xffUL) /*!< ADRMATCH (Bitfield-Mask: 0xff) */ +/* ======================================================= RS485DLY ======================================================== */ +#define UART2_RS485DLY_DLY_Pos (0UL) /*!< DLY (Bit 0) */ +#define UART2_RS485DLY_DLY_Msk (0xffUL) /*!< DLY (Bitfield-Mask: 0xff) */ + + +/* =========================================================================================================================== */ +/* ================ LPC_UART3 ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== RBR ========================================================== */ +#define UART3_RBR_RBR_Pos (0UL) /*!< RBR (Bit 0) */ +#define UART3_RBR_RBR_Msk (0xffUL) /*!< RBR (Bitfield-Mask: 0xff) */ +/* ========================================================== THR ========================================================== */ +#define UART3_THR_THR_Pos (0UL) /*!< THR (Bit 0) */ +#define UART3_THR_THR_Msk (0xffUL) /*!< THR (Bitfield-Mask: 0xff) */ +/* ========================================================== DLL ========================================================== */ +#define UART3_DLL_DLLSB_Pos (0UL) /*!< DLLSB (Bit 0) */ +#define UART3_DLL_DLLSB_Msk (0xffUL) /*!< DLLSB (Bitfield-Mask: 0xff) */ +/* ========================================================== DLM ========================================================== */ +#define UART3_DLM_DLMSB_Pos (0UL) /*!< DLMSB (Bit 0) */ +#define UART3_DLM_DLMSB_Msk (0xffUL) /*!< DLMSB (Bitfield-Mask: 0xff) */ +/* ========================================================== IER ========================================================== */ +#define UART3_IER_RBRIE_Pos (0UL) /*!< RBRIE (Bit 0) */ +#define UART3_IER_RBRIE_Msk (0x1UL) /*!< RBRIE (Bitfield-Mask: 0x01) */ +#define UART3_IER_THREIE_Pos (1UL) /*!< THREIE (Bit 1) */ +#define UART3_IER_THREIE_Msk (0x2UL) /*!< THREIE (Bitfield-Mask: 0x01) */ +#define UART3_IER_RXIE_Pos (2UL) /*!< RXIE (Bit 2) */ +#define UART3_IER_RXIE_Msk (0x4UL) /*!< RXIE (Bitfield-Mask: 0x01) */ +#define UART3_IER_ABEOINTEN_Pos (8UL) /*!< ABEOINTEN (Bit 8) */ +#define UART3_IER_ABEOINTEN_Msk (0x100UL) /*!< ABEOINTEN (Bitfield-Mask: 0x01) */ +#define UART3_IER_ABTOINTEN_Pos (9UL) /*!< ABTOINTEN (Bit 9) */ +#define UART3_IER_ABTOINTEN_Msk (0x200UL) /*!< ABTOINTEN (Bitfield-Mask: 0x01) */ +/* ========================================================== IIR ========================================================== */ +#define UART3_IIR_INTSTATUS_Pos (0UL) /*!< INTSTATUS (Bit 0) */ +#define UART3_IIR_INTSTATUS_Msk (0x1UL) /*!< INTSTATUS (Bitfield-Mask: 0x01) */ +#define UART3_IIR_INTID_Pos (1UL) /*!< INTID (Bit 1) */ +#define UART3_IIR_INTID_Msk (0xeUL) /*!< INTID (Bitfield-Mask: 0x07) */ +#define UART3_IIR_FIFOENABLE_Pos (6UL) /*!< FIFOENABLE (Bit 6) */ +#define UART3_IIR_FIFOENABLE_Msk (0xc0UL) /*!< FIFOENABLE (Bitfield-Mask: 0x03) */ +#define UART3_IIR_ABEOINT_Pos (8UL) /*!< ABEOINT (Bit 8) */ +#define UART3_IIR_ABEOINT_Msk (0x100UL) /*!< ABEOINT (Bitfield-Mask: 0x01) */ +#define UART3_IIR_ABTOINT_Pos (9UL) /*!< ABTOINT (Bit 9) */ +#define UART3_IIR_ABTOINT_Msk (0x200UL) /*!< ABTOINT (Bitfield-Mask: 0x01) */ +/* ========================================================== FCR ========================================================== */ +#define UART3_FCR_FIFOEN_Pos (0UL) /*!< FIFOEN (Bit 0) */ +#define UART3_FCR_FIFOEN_Msk (0x1UL) /*!< FIFOEN (Bitfield-Mask: 0x01) */ +#define UART3_FCR_RXFIFORES_Pos (1UL) /*!< RXFIFORES (Bit 1) */ +#define UART3_FCR_RXFIFORES_Msk (0x2UL) /*!< RXFIFORES (Bitfield-Mask: 0x01) */ +#define UART3_FCR_TXFIFORES_Pos (2UL) /*!< TXFIFORES (Bit 2) */ +#define UART3_FCR_TXFIFORES_Msk (0x4UL) /*!< TXFIFORES (Bitfield-Mask: 0x01) */ +#define UART3_FCR_DMAMODE_Pos (3UL) /*!< DMAMODE (Bit 3) */ +#define UART3_FCR_DMAMODE_Msk (0x8UL) /*!< DMAMODE (Bitfield-Mask: 0x01) */ +#define UART3_FCR_RXTRIGLVL_Pos (6UL) /*!< RXTRIGLVL (Bit 6) */ +#define UART3_FCR_RXTRIGLVL_Msk (0xc0UL) /*!< RXTRIGLVL (Bitfield-Mask: 0x03) */ +/* ========================================================== LCR ========================================================== */ +#define UART3_LCR_WLS_Pos (0UL) /*!< WLS (Bit 0) */ +#define UART3_LCR_WLS_Msk (0x3UL) /*!< WLS (Bitfield-Mask: 0x03) */ +#define UART3_LCR_SBS_Pos (2UL) /*!< SBS (Bit 2) */ +#define UART3_LCR_SBS_Msk (0x4UL) /*!< SBS (Bitfield-Mask: 0x01) */ +#define UART3_LCR_PE_Pos (3UL) /*!< PE (Bit 3) */ +#define UART3_LCR_PE_Msk (0x8UL) /*!< PE (Bitfield-Mask: 0x01) */ +#define UART3_LCR_PS_Pos (4UL) /*!< PS (Bit 4) */ +#define UART3_LCR_PS_Msk (0x30UL) /*!< PS (Bitfield-Mask: 0x03) */ +#define UART3_LCR_BC_Pos (6UL) /*!< BC (Bit 6) */ +#define UART3_LCR_BC_Msk (0x40UL) /*!< BC (Bitfield-Mask: 0x01) */ +#define UART3_LCR_DLAB_Pos (7UL) /*!< DLAB (Bit 7) */ +#define UART3_LCR_DLAB_Msk (0x80UL) /*!< DLAB (Bitfield-Mask: 0x01) */ +/* ========================================================== LSR ========================================================== */ +#define UART3_LSR_RDR_Pos (0UL) /*!< RDR (Bit 0) */ +#define UART3_LSR_RDR_Msk (0x1UL) /*!< RDR (Bitfield-Mask: 0x01) */ +#define UART3_LSR_OE_Pos (1UL) /*!< OE (Bit 1) */ +#define UART3_LSR_OE_Msk (0x2UL) /*!< OE (Bitfield-Mask: 0x01) */ +#define UART3_LSR_PE_Pos (2UL) /*!< PE (Bit 2) */ +#define UART3_LSR_PE_Msk (0x4UL) /*!< PE (Bitfield-Mask: 0x01) */ +#define UART3_LSR_FE_Pos (3UL) /*!< FE (Bit 3) */ +#define UART3_LSR_FE_Msk (0x8UL) /*!< FE (Bitfield-Mask: 0x01) */ +#define UART3_LSR_BI_Pos (4UL) /*!< BI (Bit 4) */ +#define UART3_LSR_BI_Msk (0x10UL) /*!< BI (Bitfield-Mask: 0x01) */ +#define UART3_LSR_THRE_Pos (5UL) /*!< THRE (Bit 5) */ +#define UART3_LSR_THRE_Msk (0x20UL) /*!< THRE (Bitfield-Mask: 0x01) */ +#define UART3_LSR_TEMT_Pos (6UL) /*!< TEMT (Bit 6) */ +#define UART3_LSR_TEMT_Msk (0x40UL) /*!< TEMT (Bitfield-Mask: 0x01) */ +#define UART3_LSR_RXFE_Pos (7UL) /*!< RXFE (Bit 7) */ +#define UART3_LSR_RXFE_Msk (0x80UL) /*!< RXFE (Bitfield-Mask: 0x01) */ +/* ========================================================== SCR ========================================================== */ +#define UART3_SCR_PAD_Pos (0UL) /*!< PAD (Bit 0) */ +#define UART3_SCR_PAD_Msk (0xffUL) /*!< PAD (Bitfield-Mask: 0xff) */ +/* ========================================================== ACR ========================================================== */ +#define UART3_ACR_START_Pos (0UL) /*!< START (Bit 0) */ +#define UART3_ACR_START_Msk (0x1UL) /*!< START (Bitfield-Mask: 0x01) */ +#define UART3_ACR_MODE_Pos (1UL) /*!< MODE (Bit 1) */ +#define UART3_ACR_MODE_Msk (0x2UL) /*!< MODE (Bitfield-Mask: 0x01) */ +#define UART3_ACR_AUTORESTART_Pos (2UL) /*!< AUTORESTART (Bit 2) */ +#define UART3_ACR_AUTORESTART_Msk (0x4UL) /*!< AUTORESTART (Bitfield-Mask: 0x01) */ +#define UART3_ACR_ABEOINTCLR_Pos (8UL) /*!< ABEOINTCLR (Bit 8) */ +#define UART3_ACR_ABEOINTCLR_Msk (0x100UL) /*!< ABEOINTCLR (Bitfield-Mask: 0x01) */ +#define UART3_ACR_ABTOINTCLR_Pos (9UL) /*!< ABTOINTCLR (Bit 9) */ +#define UART3_ACR_ABTOINTCLR_Msk (0x200UL) /*!< ABTOINTCLR (Bitfield-Mask: 0x01) */ +/* ========================================================== FDR ========================================================== */ +#define UART3_FDR_DIVADDVAL_Pos (0UL) /*!< DIVADDVAL (Bit 0) */ +#define UART3_FDR_DIVADDVAL_Msk (0xfUL) /*!< DIVADDVAL (Bitfield-Mask: 0x0f) */ +#define UART3_FDR_MULVAL_Pos (4UL) /*!< MULVAL (Bit 4) */ +#define UART3_FDR_MULVAL_Msk (0xf0UL) /*!< MULVAL (Bitfield-Mask: 0x0f) */ +/* ========================================================== TER ========================================================== */ +#define UART3_TER_TXEN_Pos (7UL) /*!< TXEN (Bit 7) */ +#define UART3_TER_TXEN_Msk (0x80UL) /*!< TXEN (Bitfield-Mask: 0x01) */ +/* ======================================================= RS485CTRL ======================================================= */ +#define UART3_RS485CTRL_NMMEN_Pos (0UL) /*!< NMMEN (Bit 0) */ +#define UART3_RS485CTRL_NMMEN_Msk (0x1UL) /*!< NMMEN (Bitfield-Mask: 0x01) */ +#define UART3_RS485CTRL_RXDIS_Pos (1UL) /*!< RXDIS (Bit 1) */ +#define UART3_RS485CTRL_RXDIS_Msk (0x2UL) /*!< RXDIS (Bitfield-Mask: 0x01) */ +#define UART3_RS485CTRL_AADEN_Pos (2UL) /*!< AADEN (Bit 2) */ +#define UART3_RS485CTRL_AADEN_Msk (0x4UL) /*!< AADEN (Bitfield-Mask: 0x01) */ +#define UART3_RS485CTRL_DCTRL_Pos (4UL) /*!< DCTRL (Bit 4) */ +#define UART3_RS485CTRL_DCTRL_Msk (0x10UL) /*!< DCTRL (Bitfield-Mask: 0x01) */ +#define UART3_RS485CTRL_OINV_Pos (5UL) /*!< OINV (Bit 5) */ +#define UART3_RS485CTRL_OINV_Msk (0x20UL) /*!< OINV (Bitfield-Mask: 0x01) */ +/* ===================================================== RS485ADRMATCH ===================================================== */ +#define UART3_RS485ADRMATCH_ADRMATCH_Pos (0UL) /*!< ADRMATCH (Bit 0) */ +#define UART3_RS485ADRMATCH_ADRMATCH_Msk (0xffUL) /*!< ADRMATCH (Bitfield-Mask: 0xff) */ +/* ======================================================= RS485DLY ======================================================== */ +#define UART3_RS485DLY_DLY_Pos (0UL) /*!< DLY (Bit 0) */ +#define UART3_RS485DLY_DLY_Msk (0xffUL) /*!< DLY (Bitfield-Mask: 0xff) */ + + +/* =========================================================================================================================== */ +/* ================ LPC_I2S ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== DAO ========================================================== */ +#define I2S_DAO_WORDWIDTH_Pos (0UL) /*!< WORDWIDTH (Bit 0) */ +#define I2S_DAO_WORDWIDTH_Msk (0x3UL) /*!< WORDWIDTH (Bitfield-Mask: 0x03) */ +#define I2S_DAO_MONO_Pos (2UL) /*!< MONO (Bit 2) */ +#define I2S_DAO_MONO_Msk (0x4UL) /*!< MONO (Bitfield-Mask: 0x01) */ +#define I2S_DAO_STOP_Pos (3UL) /*!< STOP (Bit 3) */ +#define I2S_DAO_STOP_Msk (0x8UL) /*!< STOP (Bitfield-Mask: 0x01) */ +#define I2S_DAO_RESET_Pos (4UL) /*!< RESET (Bit 4) */ +#define I2S_DAO_RESET_Msk (0x10UL) /*!< RESET (Bitfield-Mask: 0x01) */ +#define I2S_DAO_WS_SEL_Pos (5UL) /*!< WS_SEL (Bit 5) */ +#define I2S_DAO_WS_SEL_Msk (0x20UL) /*!< WS_SEL (Bitfield-Mask: 0x01) */ +#define I2S_DAO_WS_HALFPERIOD_Pos (6UL) /*!< WS_HALFPERIOD (Bit 6) */ +#define I2S_DAO_WS_HALFPERIOD_Msk (0x7fc0UL) /*!< WS_HALFPERIOD (Bitfield-Mask: 0x1ff) */ +#define I2S_DAO_MUTE_Pos (15UL) /*!< MUTE (Bit 15) */ +#define I2S_DAO_MUTE_Msk (0x8000UL) /*!< MUTE (Bitfield-Mask: 0x01) */ +/* ========================================================== DAI ========================================================== */ +#define I2S_DAI_WORDWIDTH_Pos (0UL) /*!< WORDWIDTH (Bit 0) */ +#define I2S_DAI_WORDWIDTH_Msk (0x3UL) /*!< WORDWIDTH (Bitfield-Mask: 0x03) */ +#define I2S_DAI_MONO_Pos (2UL) /*!< MONO (Bit 2) */ +#define I2S_DAI_MONO_Msk (0x4UL) /*!< MONO (Bitfield-Mask: 0x01) */ +#define I2S_DAI_STOP_Pos (3UL) /*!< STOP (Bit 3) */ +#define I2S_DAI_STOP_Msk (0x8UL) /*!< STOP (Bitfield-Mask: 0x01) */ +#define I2S_DAI_RESET_Pos (4UL) /*!< RESET (Bit 4) */ +#define I2S_DAI_RESET_Msk (0x10UL) /*!< RESET (Bitfield-Mask: 0x01) */ +#define I2S_DAI_WS_SEL_Pos (5UL) /*!< WS_SEL (Bit 5) */ +#define I2S_DAI_WS_SEL_Msk (0x20UL) /*!< WS_SEL (Bitfield-Mask: 0x01) */ +#define I2S_DAI_WS_HALFPERIOD_Pos (6UL) /*!< WS_HALFPERIOD (Bit 6) */ +#define I2S_DAI_WS_HALFPERIOD_Msk (0x7fc0UL) /*!< WS_HALFPERIOD (Bitfield-Mask: 0x1ff) */ +/* ======================================================== TXFIFO ========================================================= */ +#define I2S_TXFIFO_I2STXFIFO_Pos (0UL) /*!< I2STXFIFO (Bit 0) */ +#define I2S_TXFIFO_I2STXFIFO_Msk (0xffffffffUL) /*!< I2STXFIFO (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== RXFIFO ========================================================= */ +#define I2S_RXFIFO_I2SRXFIFO_Pos (0UL) /*!< I2SRXFIFO (Bit 0) */ +#define I2S_RXFIFO_I2SRXFIFO_Msk (0xffffffffUL) /*!< I2SRXFIFO (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= STATE ========================================================= */ +#define I2S_STATE_IRQ_Pos (0UL) /*!< IRQ (Bit 0) */ +#define I2S_STATE_IRQ_Msk (0x1UL) /*!< IRQ (Bitfield-Mask: 0x01) */ +#define I2S_STATE_DMAREQ1_Pos (1UL) /*!< DMAREQ1 (Bit 1) */ +#define I2S_STATE_DMAREQ1_Msk (0x2UL) /*!< DMAREQ1 (Bitfield-Mask: 0x01) */ +#define I2S_STATE_DMAREQ2_Pos (2UL) /*!< DMAREQ2 (Bit 2) */ +#define I2S_STATE_DMAREQ2_Msk (0x4UL) /*!< DMAREQ2 (Bitfield-Mask: 0x01) */ +#define I2S_STATE_RX_LEVEL_Pos (8UL) /*!< RX_LEVEL (Bit 8) */ +#define I2S_STATE_RX_LEVEL_Msk (0xf00UL) /*!< RX_LEVEL (Bitfield-Mask: 0x0f) */ +#define I2S_STATE_TX_LEVEL_Pos (16UL) /*!< TX_LEVEL (Bit 16) */ +#define I2S_STATE_TX_LEVEL_Msk (0xf0000UL) /*!< TX_LEVEL (Bitfield-Mask: 0x0f) */ +/* ========================================================= DMA1 ========================================================== */ +#define I2S_DMA1_RX_DMA1_ENABLE_Pos (0UL) /*!< RX_DMA1_ENABLE (Bit 0) */ +#define I2S_DMA1_RX_DMA1_ENABLE_Msk (0x1UL) /*!< RX_DMA1_ENABLE (Bitfield-Mask: 0x01) */ +#define I2S_DMA1_TX_DMA1_ENABLE_Pos (1UL) /*!< TX_DMA1_ENABLE (Bit 1) */ +#define I2S_DMA1_TX_DMA1_ENABLE_Msk (0x2UL) /*!< TX_DMA1_ENABLE (Bitfield-Mask: 0x01) */ +#define I2S_DMA1_RX_DEPTH_DMA1_Pos (8UL) /*!< RX_DEPTH_DMA1 (Bit 8) */ +#define I2S_DMA1_RX_DEPTH_DMA1_Msk (0xf00UL) /*!< RX_DEPTH_DMA1 (Bitfield-Mask: 0x0f) */ +#define I2S_DMA1_TX_DEPTH_DMA1_Pos (16UL) /*!< TX_DEPTH_DMA1 (Bit 16) */ +#define I2S_DMA1_TX_DEPTH_DMA1_Msk (0xf0000UL) /*!< TX_DEPTH_DMA1 (Bitfield-Mask: 0x0f) */ +/* ========================================================= DMA2 ========================================================== */ +#define I2S_DMA2_RX_DMA2_ENABLE_Pos (0UL) /*!< RX_DMA2_ENABLE (Bit 0) */ +#define I2S_DMA2_RX_DMA2_ENABLE_Msk (0x1UL) /*!< RX_DMA2_ENABLE (Bitfield-Mask: 0x01) */ +#define I2S_DMA2_TX_DMA2_ENABLE_Pos (1UL) /*!< TX_DMA2_ENABLE (Bit 1) */ +#define I2S_DMA2_TX_DMA2_ENABLE_Msk (0x2UL) /*!< TX_DMA2_ENABLE (Bitfield-Mask: 0x01) */ +#define I2S_DMA2_RX_DEPTH_DMA2_Pos (8UL) /*!< RX_DEPTH_DMA2 (Bit 8) */ +#define I2S_DMA2_RX_DEPTH_DMA2_Msk (0xf00UL) /*!< RX_DEPTH_DMA2 (Bitfield-Mask: 0x0f) */ +#define I2S_DMA2_TX_DEPTH_DMA2_Pos (16UL) /*!< TX_DEPTH_DMA2 (Bit 16) */ +#define I2S_DMA2_TX_DEPTH_DMA2_Msk (0xf0000UL) /*!< TX_DEPTH_DMA2 (Bitfield-Mask: 0x0f) */ +/* ========================================================== IRQ ========================================================== */ +#define I2S_IRQ_RX_IRQ_ENABLE_Pos (0UL) /*!< RX_IRQ_ENABLE (Bit 0) */ +#define I2S_IRQ_RX_IRQ_ENABLE_Msk (0x1UL) /*!< RX_IRQ_ENABLE (Bitfield-Mask: 0x01) */ +#define I2S_IRQ_TX_IRQ_ENABLE_Pos (1UL) /*!< TX_IRQ_ENABLE (Bit 1) */ +#define I2S_IRQ_TX_IRQ_ENABLE_Msk (0x2UL) /*!< TX_IRQ_ENABLE (Bitfield-Mask: 0x01) */ +#define I2S_IRQ_RX_DEPTH_IRQ_Pos (8UL) /*!< RX_DEPTH_IRQ (Bit 8) */ +#define I2S_IRQ_RX_DEPTH_IRQ_Msk (0xf00UL) /*!< RX_DEPTH_IRQ (Bitfield-Mask: 0x0f) */ +#define I2S_IRQ_TX_DEPTH_IRQ_Pos (16UL) /*!< TX_DEPTH_IRQ (Bit 16) */ +#define I2S_IRQ_TX_DEPTH_IRQ_Msk (0xf0000UL) /*!< TX_DEPTH_IRQ (Bitfield-Mask: 0x0f) */ +/* ======================================================== TXRATE ========================================================= */ +#define I2S_TXRATE_Y_DIVIDER_Pos (0UL) /*!< Y_DIVIDER (Bit 0) */ +#define I2S_TXRATE_Y_DIVIDER_Msk (0xffUL) /*!< Y_DIVIDER (Bitfield-Mask: 0xff) */ +#define I2S_TXRATE_X_DIVIDER_Pos (8UL) /*!< X_DIVIDER (Bit 8) */ +#define I2S_TXRATE_X_DIVIDER_Msk (0xff00UL) /*!< X_DIVIDER (Bitfield-Mask: 0xff) */ +/* ======================================================== RXRATE ========================================================= */ +#define I2S_RXRATE_Y_DIVIDER_Pos (0UL) /*!< Y_DIVIDER (Bit 0) */ +#define I2S_RXRATE_Y_DIVIDER_Msk (0xffUL) /*!< Y_DIVIDER (Bitfield-Mask: 0xff) */ +#define I2S_RXRATE_X_DIVIDER_Pos (8UL) /*!< X_DIVIDER (Bit 8) */ +#define I2S_RXRATE_X_DIVIDER_Msk (0xff00UL) /*!< X_DIVIDER (Bitfield-Mask: 0xff) */ +/* ======================================================= TXBITRATE ======================================================= */ +#define I2S_TXBITRATE_TX_BITRATE_Pos (0UL) /*!< TX_BITRATE (Bit 0) */ +#define I2S_TXBITRATE_TX_BITRATE_Msk (0x3fUL) /*!< TX_BITRATE (Bitfield-Mask: 0x3f) */ +/* ======================================================= RXBITRATE ======================================================= */ +#define I2S_RXBITRATE_RX_BITRATE_Pos (0UL) /*!< RX_BITRATE (Bit 0) */ +#define I2S_RXBITRATE_RX_BITRATE_Msk (0x3fUL) /*!< RX_BITRATE (Bitfield-Mask: 0x3f) */ +/* ======================================================== TXMODE ========================================================= */ +#define I2S_TXMODE_TXCLKSEL_Pos (0UL) /*!< TXCLKSEL (Bit 0) */ +#define I2S_TXMODE_TXCLKSEL_Msk (0x3UL) /*!< TXCLKSEL (Bitfield-Mask: 0x03) */ +#define I2S_TXMODE_TX4PIN_Pos (2UL) /*!< TX4PIN (Bit 2) */ +#define I2S_TXMODE_TX4PIN_Msk (0x4UL) /*!< TX4PIN (Bitfield-Mask: 0x01) */ +#define I2S_TXMODE_TXMCENA_Pos (3UL) /*!< TXMCENA (Bit 3) */ +#define I2S_TXMODE_TXMCENA_Msk (0x8UL) /*!< TXMCENA (Bitfield-Mask: 0x01) */ +/* ======================================================== RXMODE ========================================================= */ +#define I2S_RXMODE_RXCLKSEL_Pos (0UL) /*!< RXCLKSEL (Bit 0) */ +#define I2S_RXMODE_RXCLKSEL_Msk (0x3UL) /*!< RXCLKSEL (Bitfield-Mask: 0x03) */ +#define I2S_RXMODE_RX4PIN_Pos (2UL) /*!< RX4PIN (Bit 2) */ +#define I2S_RXMODE_RX4PIN_Msk (0x4UL) /*!< RX4PIN (Bitfield-Mask: 0x01) */ +#define I2S_RXMODE_RXMCENA_Pos (3UL) /*!< RXMCENA (Bit 3) */ +#define I2S_RXMODE_RXMCENA_Msk (0x8UL) /*!< RXMCENA (Bitfield-Mask: 0x01) */ + + +/* =========================================================================================================================== */ +/* ================ LPC_RITIMER ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== COMPVAL ======================================================== */ +#define RITIMER_COMPVAL_RICOMP_Pos (0UL) /*!< RICOMP (Bit 0) */ +#define RITIMER_COMPVAL_RICOMP_Msk (0xffffffffUL) /*!< RICOMP (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= MASK ========================================================== */ +#define RITIMER_MASK_RIMASK_Pos (0UL) /*!< RIMASK (Bit 0) */ +#define RITIMER_MASK_RIMASK_Msk (0xffffffffUL) /*!< RIMASK (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= CTRL ========================================================== */ +#define RITIMER_CTRL_RITINT_Pos (0UL) /*!< RITINT (Bit 0) */ +#define RITIMER_CTRL_RITINT_Msk (0x1UL) /*!< RITINT (Bitfield-Mask: 0x01) */ +#define RITIMER_CTRL_RITENCLR_Pos (1UL) /*!< RITENCLR (Bit 1) */ +#define RITIMER_CTRL_RITENCLR_Msk (0x2UL) /*!< RITENCLR (Bitfield-Mask: 0x01) */ +#define RITIMER_CTRL_RITENBR_Pos (2UL) /*!< RITENBR (Bit 2) */ +#define RITIMER_CTRL_RITENBR_Msk (0x4UL) /*!< RITENBR (Bitfield-Mask: 0x01) */ +#define RITIMER_CTRL_RITEN_Pos (3UL) /*!< RITEN (Bit 3) */ +#define RITIMER_CTRL_RITEN_Msk (0x8UL) /*!< RITEN (Bitfield-Mask: 0x01) */ +/* ======================================================== COUNTER ======================================================== */ +#define RITIMER_COUNTER_RICOUNTER_Pos (0UL) /*!< RICOUNTER (Bit 0) */ +#define RITIMER_COUNTER_RICOUNTER_Msk (0xffffffffUL) /*!< RICOUNTER (Bitfield-Mask: 0xffffffff) */ + + +/* =========================================================================================================================== */ +/* ================ LPC_MCPWM ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== CON ========================================================== */ +#define MCPWM_CON_RUN0_Pos (0UL) /*!< RUN0 (Bit 0) */ +#define MCPWM_CON_RUN0_Msk (0x1UL) /*!< RUN0 (Bitfield-Mask: 0x01) */ +#define MCPWM_CON_CENTER0_Pos (1UL) /*!< CENTER0 (Bit 1) */ +#define MCPWM_CON_CENTER0_Msk (0x2UL) /*!< CENTER0 (Bitfield-Mask: 0x01) */ +#define MCPWM_CON_POLA0_Pos (2UL) /*!< POLA0 (Bit 2) */ +#define MCPWM_CON_POLA0_Msk (0x4UL) /*!< POLA0 (Bitfield-Mask: 0x01) */ +#define MCPWM_CON_DTE0_Pos (3UL) /*!< DTE0 (Bit 3) */ +#define MCPWM_CON_DTE0_Msk (0x8UL) /*!< DTE0 (Bitfield-Mask: 0x01) */ +#define MCPWM_CON_DISUP0_Pos (4UL) /*!< DISUP0 (Bit 4) */ +#define MCPWM_CON_DISUP0_Msk (0x10UL) /*!< DISUP0 (Bitfield-Mask: 0x01) */ +#define MCPWM_CON_RUN1_Pos (8UL) /*!< RUN1 (Bit 8) */ +#define MCPWM_CON_RUN1_Msk (0x100UL) /*!< RUN1 (Bitfield-Mask: 0x01) */ +#define MCPWM_CON_CENTER1_Pos (9UL) /*!< CENTER1 (Bit 9) */ +#define MCPWM_CON_CENTER1_Msk (0x200UL) /*!< CENTER1 (Bitfield-Mask: 0x01) */ +#define MCPWM_CON_POLA1_Pos (10UL) /*!< POLA1 (Bit 10) */ +#define MCPWM_CON_POLA1_Msk (0x400UL) /*!< POLA1 (Bitfield-Mask: 0x01) */ +#define MCPWM_CON_DTE1_Pos (11UL) /*!< DTE1 (Bit 11) */ +#define MCPWM_CON_DTE1_Msk (0x800UL) /*!< DTE1 (Bitfield-Mask: 0x01) */ +#define MCPWM_CON_DISUP1_Pos (12UL) /*!< DISUP1 (Bit 12) */ +#define MCPWM_CON_DISUP1_Msk (0x1000UL) /*!< DISUP1 (Bitfield-Mask: 0x01) */ +#define MCPWM_CON_RUN2_Pos (16UL) /*!< RUN2 (Bit 16) */ +#define MCPWM_CON_RUN2_Msk (0x10000UL) /*!< RUN2 (Bitfield-Mask: 0x01) */ +#define MCPWM_CON_CENTER2_Pos (17UL) /*!< CENTER2 (Bit 17) */ +#define MCPWM_CON_CENTER2_Msk (0x20000UL) /*!< CENTER2 (Bitfield-Mask: 0x01) */ +#define MCPWM_CON_POLA2_Pos (18UL) /*!< POLA2 (Bit 18) */ +#define MCPWM_CON_POLA2_Msk (0x40000UL) /*!< POLA2 (Bitfield-Mask: 0x01) */ +#define MCPWM_CON_DTE2_Pos (19UL) /*!< DTE2 (Bit 19) */ +#define MCPWM_CON_DTE2_Msk (0x80000UL) /*!< DTE2 (Bitfield-Mask: 0x01) */ +#define MCPWM_CON_DISUP2_Pos (20UL) /*!< DISUP2 (Bit 20) */ +#define MCPWM_CON_DISUP2_Msk (0x100000UL) /*!< DISUP2 (Bitfield-Mask: 0x01) */ +#define MCPWM_CON_INVBDC_Pos (29UL) /*!< INVBDC (Bit 29) */ +#define MCPWM_CON_INVBDC_Msk (0x20000000UL) /*!< INVBDC (Bitfield-Mask: 0x01) */ +#define MCPWM_CON_ACMODE_Pos (30UL) /*!< ACMODE (Bit 30) */ +#define MCPWM_CON_ACMODE_Msk (0x40000000UL) /*!< ACMODE (Bitfield-Mask: 0x01) */ +#define MCPWM_CON_DCMODE_Pos (31UL) /*!< DCMODE (Bit 31) */ +#define MCPWM_CON_DCMODE_Msk (0x80000000UL) /*!< DCMODE (Bitfield-Mask: 0x01) */ +/* ======================================================== CON_SET ======================================================== */ +#define MCPWM_CON_SET_RUN0_SET_Pos (0UL) /*!< RUN0_SET (Bit 0) */ +#define MCPWM_CON_SET_RUN0_SET_Msk (0x1UL) /*!< RUN0_SET (Bitfield-Mask: 0x01) */ +#define MCPWM_CON_SET_CENTER0_SET_Pos (1UL) /*!< CENTER0_SET (Bit 1) */ +#define MCPWM_CON_SET_CENTER0_SET_Msk (0x2UL) /*!< CENTER0_SET (Bitfield-Mask: 0x01) */ +#define MCPWM_CON_SET_POLA0_SET_Pos (2UL) /*!< POLA0_SET (Bit 2) */ +#define MCPWM_CON_SET_POLA0_SET_Msk (0x4UL) /*!< POLA0_SET (Bitfield-Mask: 0x01) */ +#define MCPWM_CON_SET_DTE0_SET_Pos (3UL) /*!< DTE0_SET (Bit 3) */ +#define MCPWM_CON_SET_DTE0_SET_Msk (0x8UL) /*!< DTE0_SET (Bitfield-Mask: 0x01) */ +#define MCPWM_CON_SET_DISUP0_SET_Pos (4UL) /*!< DISUP0_SET (Bit 4) */ +#define MCPWM_CON_SET_DISUP0_SET_Msk (0x10UL) /*!< DISUP0_SET (Bitfield-Mask: 0x01) */ +#define MCPWM_CON_SET_RUN1_SET_Pos (8UL) /*!< RUN1_SET (Bit 8) */ +#define MCPWM_CON_SET_RUN1_SET_Msk (0x100UL) /*!< RUN1_SET (Bitfield-Mask: 0x01) */ +#define MCPWM_CON_SET_CENTER1_SET_Pos (9UL) /*!< CENTER1_SET (Bit 9) */ +#define MCPWM_CON_SET_CENTER1_SET_Msk (0x200UL) /*!< CENTER1_SET (Bitfield-Mask: 0x01) */ +#define MCPWM_CON_SET_POLA1_SET_Pos (10UL) /*!< POLA1_SET (Bit 10) */ +#define MCPWM_CON_SET_POLA1_SET_Msk (0x400UL) /*!< POLA1_SET (Bitfield-Mask: 0x01) */ +#define MCPWM_CON_SET_DTE1_SET_Pos (11UL) /*!< DTE1_SET (Bit 11) */ +#define MCPWM_CON_SET_DTE1_SET_Msk (0x800UL) /*!< DTE1_SET (Bitfield-Mask: 0x01) */ +#define MCPWM_CON_SET_DISUP1_SET_Pos (12UL) /*!< DISUP1_SET (Bit 12) */ +#define MCPWM_CON_SET_DISUP1_SET_Msk (0x1000UL) /*!< DISUP1_SET (Bitfield-Mask: 0x01) */ +#define MCPWM_CON_SET_RUN2_SET_Pos (16UL) /*!< RUN2_SET (Bit 16) */ +#define MCPWM_CON_SET_RUN2_SET_Msk (0x10000UL) /*!< RUN2_SET (Bitfield-Mask: 0x01) */ +#define MCPWM_CON_SET_CENTER2_SET_Pos (17UL) /*!< CENTER2_SET (Bit 17) */ +#define MCPWM_CON_SET_CENTER2_SET_Msk (0x20000UL) /*!< CENTER2_SET (Bitfield-Mask: 0x01) */ +#define MCPWM_CON_SET_POLA2_SET_Pos (18UL) /*!< POLA2_SET (Bit 18) */ +#define MCPWM_CON_SET_POLA2_SET_Msk (0x40000UL) /*!< POLA2_SET (Bitfield-Mask: 0x01) */ +#define MCPWM_CON_SET_DTE2_SET_Pos (19UL) /*!< DTE2_SET (Bit 19) */ +#define MCPWM_CON_SET_DTE2_SET_Msk (0x80000UL) /*!< DTE2_SET (Bitfield-Mask: 0x01) */ +#define MCPWM_CON_SET_DISUP2_SET_Pos (20UL) /*!< DISUP2_SET (Bit 20) */ +#define MCPWM_CON_SET_DISUP2_SET_Msk (0x100000UL) /*!< DISUP2_SET (Bitfield-Mask: 0x01) */ +#define MCPWM_CON_SET_INVBDC_SET_Pos (29UL) /*!< INVBDC_SET (Bit 29) */ +#define MCPWM_CON_SET_INVBDC_SET_Msk (0x20000000UL) /*!< INVBDC_SET (Bitfield-Mask: 0x01) */ +#define MCPWM_CON_SET_ACMODE_SET_Pos (30UL) /*!< ACMODE_SET (Bit 30) */ +#define MCPWM_CON_SET_ACMODE_SET_Msk (0x40000000UL) /*!< ACMODE_SET (Bitfield-Mask: 0x01) */ +#define MCPWM_CON_SET_DCMODE_SET_Pos (31UL) /*!< DCMODE_SET (Bit 31) */ +#define MCPWM_CON_SET_DCMODE_SET_Msk (0x80000000UL) /*!< DCMODE_SET (Bitfield-Mask: 0x01) */ +/* ======================================================== CON_CLR ======================================================== */ +#define MCPWM_CON_CLR_RUN0_CLR_Pos (0UL) /*!< RUN0_CLR (Bit 0) */ +#define MCPWM_CON_CLR_RUN0_CLR_Msk (0x1UL) /*!< RUN0_CLR (Bitfield-Mask: 0x01) */ +#define MCPWM_CON_CLR_CENTER0_CLR_Pos (1UL) /*!< CENTER0_CLR (Bit 1) */ +#define MCPWM_CON_CLR_CENTER0_CLR_Msk (0x2UL) /*!< CENTER0_CLR (Bitfield-Mask: 0x01) */ +#define MCPWM_CON_CLR_POLA0_CLR_Pos (2UL) /*!< POLA0_CLR (Bit 2) */ +#define MCPWM_CON_CLR_POLA0_CLR_Msk (0x4UL) /*!< POLA0_CLR (Bitfield-Mask: 0x01) */ +#define MCPWM_CON_CLR_DTE0_CLR_Pos (3UL) /*!< DTE0_CLR (Bit 3) */ +#define MCPWM_CON_CLR_DTE0_CLR_Msk (0x8UL) /*!< DTE0_CLR (Bitfield-Mask: 0x01) */ +#define MCPWM_CON_CLR_DISUP0_CLR_Pos (4UL) /*!< DISUP0_CLR (Bit 4) */ +#define MCPWM_CON_CLR_DISUP0_CLR_Msk (0x10UL) /*!< DISUP0_CLR (Bitfield-Mask: 0x01) */ +#define MCPWM_CON_CLR_RUN1_CLR_Pos (8UL) /*!< RUN1_CLR (Bit 8) */ +#define MCPWM_CON_CLR_RUN1_CLR_Msk (0x100UL) /*!< RUN1_CLR (Bitfield-Mask: 0x01) */ +#define MCPWM_CON_CLR_CENTER1_CLR_Pos (9UL) /*!< CENTER1_CLR (Bit 9) */ +#define MCPWM_CON_CLR_CENTER1_CLR_Msk (0x200UL) /*!< CENTER1_CLR (Bitfield-Mask: 0x01) */ +#define MCPWM_CON_CLR_POLA1_CLR_Pos (10UL) /*!< POLA1_CLR (Bit 10) */ +#define MCPWM_CON_CLR_POLA1_CLR_Msk (0x400UL) /*!< POLA1_CLR (Bitfield-Mask: 0x01) */ +#define MCPWM_CON_CLR_DTE1_CLR_Pos (11UL) /*!< DTE1_CLR (Bit 11) */ +#define MCPWM_CON_CLR_DTE1_CLR_Msk (0x800UL) /*!< DTE1_CLR (Bitfield-Mask: 0x01) */ +#define MCPWM_CON_CLR_DISUP1_CLR_Pos (12UL) /*!< DISUP1_CLR (Bit 12) */ +#define MCPWM_CON_CLR_DISUP1_CLR_Msk (0x1000UL) /*!< DISUP1_CLR (Bitfield-Mask: 0x01) */ +#define MCPWM_CON_CLR_RUN2_CLR_Pos (16UL) /*!< RUN2_CLR (Bit 16) */ +#define MCPWM_CON_CLR_RUN2_CLR_Msk (0x10000UL) /*!< RUN2_CLR (Bitfield-Mask: 0x01) */ +#define MCPWM_CON_CLR_CENTER2_CLR_Pos (17UL) /*!< CENTER2_CLR (Bit 17) */ +#define MCPWM_CON_CLR_CENTER2_CLR_Msk (0x20000UL) /*!< CENTER2_CLR (Bitfield-Mask: 0x01) */ +#define MCPWM_CON_CLR_POLA2_CLR_Pos (18UL) /*!< POLA2_CLR (Bit 18) */ +#define MCPWM_CON_CLR_POLA2_CLR_Msk (0x40000UL) /*!< POLA2_CLR (Bitfield-Mask: 0x01) */ +#define MCPWM_CON_CLR_DTE2_CLR_Pos (19UL) /*!< DTE2_CLR (Bit 19) */ +#define MCPWM_CON_CLR_DTE2_CLR_Msk (0x80000UL) /*!< DTE2_CLR (Bitfield-Mask: 0x01) */ +#define MCPWM_CON_CLR_DISUP2_CLR_Pos (20UL) /*!< DISUP2_CLR (Bit 20) */ +#define MCPWM_CON_CLR_DISUP2_CLR_Msk (0x100000UL) /*!< DISUP2_CLR (Bitfield-Mask: 0x01) */ +#define MCPWM_CON_CLR_INVBDC_CLR_Pos (29UL) /*!< INVBDC_CLR (Bit 29) */ +#define MCPWM_CON_CLR_INVBDC_CLR_Msk (0x20000000UL) /*!< INVBDC_CLR (Bitfield-Mask: 0x01) */ +#define MCPWM_CON_CLR_ACMOD_CLR_Pos (30UL) /*!< ACMOD_CLR (Bit 30) */ +#define MCPWM_CON_CLR_ACMOD_CLR_Msk (0x40000000UL) /*!< ACMOD_CLR (Bitfield-Mask: 0x01) */ +#define MCPWM_CON_CLR_DCMODE_CLR_Pos (31UL) /*!< DCMODE_CLR (Bit 31) */ +#define MCPWM_CON_CLR_DCMODE_CLR_Msk (0x80000000UL) /*!< DCMODE_CLR (Bitfield-Mask: 0x01) */ +/* ======================================================== CAPCON ========================================================= */ +#define MCPWM_CAPCON_CAP0MCI0_RE_Pos (0UL) /*!< CAP0MCI0_RE (Bit 0) */ +#define MCPWM_CAPCON_CAP0MCI0_RE_Msk (0x1UL) /*!< CAP0MCI0_RE (Bitfield-Mask: 0x01) */ +#define MCPWM_CAPCON_CAP0MCI0_FE_Pos (1UL) /*!< CAP0MCI0_FE (Bit 1) */ +#define MCPWM_CAPCON_CAP0MCI0_FE_Msk (0x2UL) /*!< CAP0MCI0_FE (Bitfield-Mask: 0x01) */ +#define MCPWM_CAPCON_CAP0MCI1_RE_Pos (2UL) /*!< CAP0MCI1_RE (Bit 2) */ +#define MCPWM_CAPCON_CAP0MCI1_RE_Msk (0x4UL) /*!< CAP0MCI1_RE (Bitfield-Mask: 0x01) */ +#define MCPWM_CAPCON_CAP0MCI1_FE_Pos (3UL) /*!< CAP0MCI1_FE (Bit 3) */ +#define MCPWM_CAPCON_CAP0MCI1_FE_Msk (0x8UL) /*!< CAP0MCI1_FE (Bitfield-Mask: 0x01) */ +#define MCPWM_CAPCON_CAP0MCI2_RE_Pos (4UL) /*!< CAP0MCI2_RE (Bit 4) */ +#define MCPWM_CAPCON_CAP0MCI2_RE_Msk (0x10UL) /*!< CAP0MCI2_RE (Bitfield-Mask: 0x01) */ +#define MCPWM_CAPCON_CAP0MCI2_FE_Pos (5UL) /*!< CAP0MCI2_FE (Bit 5) */ +#define MCPWM_CAPCON_CAP0MCI2_FE_Msk (0x20UL) /*!< CAP0MCI2_FE (Bitfield-Mask: 0x01) */ +#define MCPWM_CAPCON_CAP1MCI0_RE_Pos (6UL) /*!< CAP1MCI0_RE (Bit 6) */ +#define MCPWM_CAPCON_CAP1MCI0_RE_Msk (0x40UL) /*!< CAP1MCI0_RE (Bitfield-Mask: 0x01) */ +#define MCPWM_CAPCON_CAP1MCI0_FE_Pos (7UL) /*!< CAP1MCI0_FE (Bit 7) */ +#define MCPWM_CAPCON_CAP1MCI0_FE_Msk (0x80UL) /*!< CAP1MCI0_FE (Bitfield-Mask: 0x01) */ +#define MCPWM_CAPCON_CAP1MCI1_RE_Pos (8UL) /*!< CAP1MCI1_RE (Bit 8) */ +#define MCPWM_CAPCON_CAP1MCI1_RE_Msk (0x100UL) /*!< CAP1MCI1_RE (Bitfield-Mask: 0x01) */ +#define MCPWM_CAPCON_CAP1MCI1_FE_Pos (9UL) /*!< CAP1MCI1_FE (Bit 9) */ +#define MCPWM_CAPCON_CAP1MCI1_FE_Msk (0x200UL) /*!< CAP1MCI1_FE (Bitfield-Mask: 0x01) */ +#define MCPWM_CAPCON_CAP1MCI2_RE_Pos (10UL) /*!< CAP1MCI2_RE (Bit 10) */ +#define MCPWM_CAPCON_CAP1MCI2_RE_Msk (0x400UL) /*!< CAP1MCI2_RE (Bitfield-Mask: 0x01) */ +#define MCPWM_CAPCON_CAP1MCI2_FE_Pos (11UL) /*!< CAP1MCI2_FE (Bit 11) */ +#define MCPWM_CAPCON_CAP1MCI2_FE_Msk (0x800UL) /*!< CAP1MCI2_FE (Bitfield-Mask: 0x01) */ +#define MCPWM_CAPCON_CAP2MCI0_RE_Pos (12UL) /*!< CAP2MCI0_RE (Bit 12) */ +#define MCPWM_CAPCON_CAP2MCI0_RE_Msk (0x1000UL) /*!< CAP2MCI0_RE (Bitfield-Mask: 0x01) */ +#define MCPWM_CAPCON_CAP2MCI0_FE_Pos (13UL) /*!< CAP2MCI0_FE (Bit 13) */ +#define MCPWM_CAPCON_CAP2MCI0_FE_Msk (0x2000UL) /*!< CAP2MCI0_FE (Bitfield-Mask: 0x01) */ +#define MCPWM_CAPCON_CAP2MCI1_RE_Pos (14UL) /*!< CAP2MCI1_RE (Bit 14) */ +#define MCPWM_CAPCON_CAP2MCI1_RE_Msk (0x4000UL) /*!< CAP2MCI1_RE (Bitfield-Mask: 0x01) */ +#define MCPWM_CAPCON_CAP2MCI1_FE_Pos (15UL) /*!< CAP2MCI1_FE (Bit 15) */ +#define MCPWM_CAPCON_CAP2MCI1_FE_Msk (0x8000UL) /*!< CAP2MCI1_FE (Bitfield-Mask: 0x01) */ +#define MCPWM_CAPCON_CAP2MCI2_RE_Pos (16UL) /*!< CAP2MCI2_RE (Bit 16) */ +#define MCPWM_CAPCON_CAP2MCI2_RE_Msk (0x10000UL) /*!< CAP2MCI2_RE (Bitfield-Mask: 0x01) */ +#define MCPWM_CAPCON_CAP2MCI2_FE_Pos (17UL) /*!< CAP2MCI2_FE (Bit 17) */ +#define MCPWM_CAPCON_CAP2MCI2_FE_Msk (0x20000UL) /*!< CAP2MCI2_FE (Bitfield-Mask: 0x01) */ +#define MCPWM_CAPCON_RT0_Pos (18UL) /*!< RT0 (Bit 18) */ +#define MCPWM_CAPCON_RT0_Msk (0x40000UL) /*!< RT0 (Bitfield-Mask: 0x01) */ +#define MCPWM_CAPCON_RT1_Pos (19UL) /*!< RT1 (Bit 19) */ +#define MCPWM_CAPCON_RT1_Msk (0x80000UL) /*!< RT1 (Bitfield-Mask: 0x01) */ +#define MCPWM_CAPCON_RT2_Pos (20UL) /*!< RT2 (Bit 20) */ +#define MCPWM_CAPCON_RT2_Msk (0x100000UL) /*!< RT2 (Bitfield-Mask: 0x01) */ +/* ====================================================== CAPCON_SET ======================================================= */ +#define MCPWM_CAPCON_SET_CAP0MCI0_RE_SET_Pos (0UL) /*!< CAP0MCI0_RE_SET (Bit 0) */ +#define MCPWM_CAPCON_SET_CAP0MCI0_RE_SET_Msk (0x1UL) /*!< CAP0MCI0_RE_SET (Bitfield-Mask: 0x01) */ +#define MCPWM_CAPCON_SET_CAP0MCI0_FE_SET_Pos (1UL) /*!< CAP0MCI0_FE_SET (Bit 1) */ +#define MCPWM_CAPCON_SET_CAP0MCI0_FE_SET_Msk (0x2UL) /*!< CAP0MCI0_FE_SET (Bitfield-Mask: 0x01) */ +#define MCPWM_CAPCON_SET_CAP0MCI1_RE_SET_Pos (2UL) /*!< CAP0MCI1_RE_SET (Bit 2) */ +#define MCPWM_CAPCON_SET_CAP0MCI1_RE_SET_Msk (0x4UL) /*!< CAP0MCI1_RE_SET (Bitfield-Mask: 0x01) */ +#define MCPWM_CAPCON_SET_CAP0MCI1_FE_SET_Pos (3UL) /*!< CAP0MCI1_FE_SET (Bit 3) */ +#define MCPWM_CAPCON_SET_CAP0MCI1_FE_SET_Msk (0x8UL) /*!< CAP0MCI1_FE_SET (Bitfield-Mask: 0x01) */ +#define MCPWM_CAPCON_SET_CAP0MCI2_RE_SET_Pos (4UL) /*!< CAP0MCI2_RE_SET (Bit 4) */ +#define MCPWM_CAPCON_SET_CAP0MCI2_RE_SET_Msk (0x10UL) /*!< CAP0MCI2_RE_SET (Bitfield-Mask: 0x01) */ +#define MCPWM_CAPCON_SET_CAP0MCI2_FE_SET_Pos (5UL) /*!< CAP0MCI2_FE_SET (Bit 5) */ +#define MCPWM_CAPCON_SET_CAP0MCI2_FE_SET_Msk (0x20UL) /*!< CAP0MCI2_FE_SET (Bitfield-Mask: 0x01) */ +#define MCPWM_CAPCON_SET_CAP1MCI0_RE_SET_Pos (6UL) /*!< CAP1MCI0_RE_SET (Bit 6) */ +#define MCPWM_CAPCON_SET_CAP1MCI0_RE_SET_Msk (0x40UL) /*!< CAP1MCI0_RE_SET (Bitfield-Mask: 0x01) */ +#define MCPWM_CAPCON_SET_CAP1MCI0_FE_SET_Pos (7UL) /*!< CAP1MCI0_FE_SET (Bit 7) */ +#define MCPWM_CAPCON_SET_CAP1MCI0_FE_SET_Msk (0x80UL) /*!< CAP1MCI0_FE_SET (Bitfield-Mask: 0x01) */ +#define MCPWM_CAPCON_SET_CAP1MCI1_RE_SET_Pos (8UL) /*!< CAP1MCI1_RE_SET (Bit 8) */ +#define MCPWM_CAPCON_SET_CAP1MCI1_RE_SET_Msk (0x100UL) /*!< CAP1MCI1_RE_SET (Bitfield-Mask: 0x01) */ +#define MCPWM_CAPCON_SET_CAP1MCI1_FE_SET_Pos (9UL) /*!< CAP1MCI1_FE_SET (Bit 9) */ +#define MCPWM_CAPCON_SET_CAP1MCI1_FE_SET_Msk (0x200UL) /*!< CAP1MCI1_FE_SET (Bitfield-Mask: 0x01) */ +#define MCPWM_CAPCON_SET_CAP1MCI2_RE_SET_Pos (10UL) /*!< CAP1MCI2_RE_SET (Bit 10) */ +#define MCPWM_CAPCON_SET_CAP1MCI2_RE_SET_Msk (0x400UL) /*!< CAP1MCI2_RE_SET (Bitfield-Mask: 0x01) */ +#define MCPWM_CAPCON_SET_CAP1MCI2_FE_SET_Pos (11UL) /*!< CAP1MCI2_FE_SET (Bit 11) */ +#define MCPWM_CAPCON_SET_CAP1MCI2_FE_SET_Msk (0x800UL) /*!< CAP1MCI2_FE_SET (Bitfield-Mask: 0x01) */ +#define MCPWM_CAPCON_SET_CAP2MCI0_RE_SET_Pos (12UL) /*!< CAP2MCI0_RE_SET (Bit 12) */ +#define MCPWM_CAPCON_SET_CAP2MCI0_RE_SET_Msk (0x1000UL) /*!< CAP2MCI0_RE_SET (Bitfield-Mask: 0x01) */ +#define MCPWM_CAPCON_SET_CAP2MCI0_FE_SET_Pos (13UL) /*!< CAP2MCI0_FE_SET (Bit 13) */ +#define MCPWM_CAPCON_SET_CAP2MCI0_FE_SET_Msk (0x2000UL) /*!< CAP2MCI0_FE_SET (Bitfield-Mask: 0x01) */ +#define MCPWM_CAPCON_SET_CAP2MCI1_RE_SET_Pos (14UL) /*!< CAP2MCI1_RE_SET (Bit 14) */ +#define MCPWM_CAPCON_SET_CAP2MCI1_RE_SET_Msk (0x4000UL) /*!< CAP2MCI1_RE_SET (Bitfield-Mask: 0x01) */ +#define MCPWM_CAPCON_SET_CAP2MCI1_FE_SET_Pos (15UL) /*!< CAP2MCI1_FE_SET (Bit 15) */ +#define MCPWM_CAPCON_SET_CAP2MCI1_FE_SET_Msk (0x8000UL) /*!< CAP2MCI1_FE_SET (Bitfield-Mask: 0x01) */ +#define MCPWM_CAPCON_SET_CAP2MCI2_RE_SET_Pos (16UL) /*!< CAP2MCI2_RE_SET (Bit 16) */ +#define MCPWM_CAPCON_SET_CAP2MCI2_RE_SET_Msk (0x10000UL) /*!< CAP2MCI2_RE_SET (Bitfield-Mask: 0x01) */ +#define MCPWM_CAPCON_SET_CAP2MCI2_FE_SET_Pos (17UL) /*!< CAP2MCI2_FE_SET (Bit 17) */ +#define MCPWM_CAPCON_SET_CAP2MCI2_FE_SET_Msk (0x20000UL) /*!< CAP2MCI2_FE_SET (Bitfield-Mask: 0x01) */ +#define MCPWM_CAPCON_SET_RT0_SET_Pos (18UL) /*!< RT0_SET (Bit 18) */ +#define MCPWM_CAPCON_SET_RT0_SET_Msk (0x40000UL) /*!< RT0_SET (Bitfield-Mask: 0x01) */ +#define MCPWM_CAPCON_SET_RT1_SET_Pos (19UL) /*!< RT1_SET (Bit 19) */ +#define MCPWM_CAPCON_SET_RT1_SET_Msk (0x80000UL) /*!< RT1_SET (Bitfield-Mask: 0x01) */ +#define MCPWM_CAPCON_SET_RT2_SET_Pos (20UL) /*!< RT2_SET (Bit 20) */ +#define MCPWM_CAPCON_SET_RT2_SET_Msk (0x100000UL) /*!< RT2_SET (Bitfield-Mask: 0x01) */ +/* ====================================================== CAPCON_CLR ======================================================= */ +#define MCPWM_CAPCON_CLR_CAP0MCI0_RE_CLR_Pos (0UL) /*!< CAP0MCI0_RE_CLR (Bit 0) */ +#define MCPWM_CAPCON_CLR_CAP0MCI0_RE_CLR_Msk (0x1UL) /*!< CAP0MCI0_RE_CLR (Bitfield-Mask: 0x01) */ +#define MCPWM_CAPCON_CLR_CAP0MCI0_FE_CLR_Pos (1UL) /*!< CAP0MCI0_FE_CLR (Bit 1) */ +#define MCPWM_CAPCON_CLR_CAP0MCI0_FE_CLR_Msk (0x2UL) /*!< CAP0MCI0_FE_CLR (Bitfield-Mask: 0x01) */ +#define MCPWM_CAPCON_CLR_CAP0MCI1_RE_CLR_Pos (2UL) /*!< CAP0MCI1_RE_CLR (Bit 2) */ +#define MCPWM_CAPCON_CLR_CAP0MCI1_RE_CLR_Msk (0x4UL) /*!< CAP0MCI1_RE_CLR (Bitfield-Mask: 0x01) */ +#define MCPWM_CAPCON_CLR_CAP0MCI1_FE_CLR_Pos (3UL) /*!< CAP0MCI1_FE_CLR (Bit 3) */ +#define MCPWM_CAPCON_CLR_CAP0MCI1_FE_CLR_Msk (0x8UL) /*!< CAP0MCI1_FE_CLR (Bitfield-Mask: 0x01) */ +#define MCPWM_CAPCON_CLR_CAP0MCI2_RE_CLR_Pos (4UL) /*!< CAP0MCI2_RE_CLR (Bit 4) */ +#define MCPWM_CAPCON_CLR_CAP0MCI2_RE_CLR_Msk (0x10UL) /*!< CAP0MCI2_RE_CLR (Bitfield-Mask: 0x01) */ +#define MCPWM_CAPCON_CLR_CAP0MCI2_FE_CLR_Pos (5UL) /*!< CAP0MCI2_FE_CLR (Bit 5) */ +#define MCPWM_CAPCON_CLR_CAP0MCI2_FE_CLR_Msk (0x20UL) /*!< CAP0MCI2_FE_CLR (Bitfield-Mask: 0x01) */ +#define MCPWM_CAPCON_CLR_CAP1MCI0_RE_CLR_Pos (6UL) /*!< CAP1MCI0_RE_CLR (Bit 6) */ +#define MCPWM_CAPCON_CLR_CAP1MCI0_RE_CLR_Msk (0x40UL) /*!< CAP1MCI0_RE_CLR (Bitfield-Mask: 0x01) */ +#define MCPWM_CAPCON_CLR_CAP1MCI0_FE_CLR_Pos (7UL) /*!< CAP1MCI0_FE_CLR (Bit 7) */ +#define MCPWM_CAPCON_CLR_CAP1MCI0_FE_CLR_Msk (0x80UL) /*!< CAP1MCI0_FE_CLR (Bitfield-Mask: 0x01) */ +#define MCPWM_CAPCON_CLR_CAP1MCI1_RE_CLR_Pos (8UL) /*!< CAP1MCI1_RE_CLR (Bit 8) */ +#define MCPWM_CAPCON_CLR_CAP1MCI1_RE_CLR_Msk (0x100UL) /*!< CAP1MCI1_RE_CLR (Bitfield-Mask: 0x01) */ +#define MCPWM_CAPCON_CLR_CAP1MCI1_FE_CLR_Pos (9UL) /*!< CAP1MCI1_FE_CLR (Bit 9) */ +#define MCPWM_CAPCON_CLR_CAP1MCI1_FE_CLR_Msk (0x200UL) /*!< CAP1MCI1_FE_CLR (Bitfield-Mask: 0x01) */ +#define MCPWM_CAPCON_CLR_CAP1MCI2_RE_CLR_Pos (10UL) /*!< CAP1MCI2_RE_CLR (Bit 10) */ +#define MCPWM_CAPCON_CLR_CAP1MCI2_RE_CLR_Msk (0x400UL) /*!< CAP1MCI2_RE_CLR (Bitfield-Mask: 0x01) */ +#define MCPWM_CAPCON_CLR_CAP1MCI2_FE_CLR_Pos (11UL) /*!< CAP1MCI2_FE_CLR (Bit 11) */ +#define MCPWM_CAPCON_CLR_CAP1MCI2_FE_CLR_Msk (0x800UL) /*!< CAP1MCI2_FE_CLR (Bitfield-Mask: 0x01) */ +#define MCPWM_CAPCON_CLR_CAP2MCI0_RE_CLR_Pos (12UL) /*!< CAP2MCI0_RE_CLR (Bit 12) */ +#define MCPWM_CAPCON_CLR_CAP2MCI0_RE_CLR_Msk (0x1000UL) /*!< CAP2MCI0_RE_CLR (Bitfield-Mask: 0x01) */ +#define MCPWM_CAPCON_CLR_CAP2MCI0_FE_CLR_Pos (13UL) /*!< CAP2MCI0_FE_CLR (Bit 13) */ +#define MCPWM_CAPCON_CLR_CAP2MCI0_FE_CLR_Msk (0x2000UL) /*!< CAP2MCI0_FE_CLR (Bitfield-Mask: 0x01) */ +#define MCPWM_CAPCON_CLR_CAP2MCI1_RE_CLR_Pos (14UL) /*!< CAP2MCI1_RE_CLR (Bit 14) */ +#define MCPWM_CAPCON_CLR_CAP2MCI1_RE_CLR_Msk (0x4000UL) /*!< CAP2MCI1_RE_CLR (Bitfield-Mask: 0x01) */ +#define MCPWM_CAPCON_CLR_CAP2MCI1_FE_CLR_Pos (15UL) /*!< CAP2MCI1_FE_CLR (Bit 15) */ +#define MCPWM_CAPCON_CLR_CAP2MCI1_FE_CLR_Msk (0x8000UL) /*!< CAP2MCI1_FE_CLR (Bitfield-Mask: 0x01) */ +#define MCPWM_CAPCON_CLR_CAP2MCI2_RE_CLR_Pos (16UL) /*!< CAP2MCI2_RE_CLR (Bit 16) */ +#define MCPWM_CAPCON_CLR_CAP2MCI2_RE_CLR_Msk (0x10000UL) /*!< CAP2MCI2_RE_CLR (Bitfield-Mask: 0x01) */ +#define MCPWM_CAPCON_CLR_CAP2MCI2_FE_CLR_Pos (17UL) /*!< CAP2MCI2_FE_CLR (Bit 17) */ +#define MCPWM_CAPCON_CLR_CAP2MCI2_FE_CLR_Msk (0x20000UL) /*!< CAP2MCI2_FE_CLR (Bitfield-Mask: 0x01) */ +#define MCPWM_CAPCON_CLR_RT0_CLR_Pos (18UL) /*!< RT0_CLR (Bit 18) */ +#define MCPWM_CAPCON_CLR_RT0_CLR_Msk (0x40000UL) /*!< RT0_CLR (Bitfield-Mask: 0x01) */ +#define MCPWM_CAPCON_CLR_RT1_CLR_Pos (19UL) /*!< RT1_CLR (Bit 19) */ +#define MCPWM_CAPCON_CLR_RT1_CLR_Msk (0x80000UL) /*!< RT1_CLR (Bitfield-Mask: 0x01) */ +#define MCPWM_CAPCON_CLR_RT2_CLR_Pos (20UL) /*!< RT2_CLR (Bit 20) */ +#define MCPWM_CAPCON_CLR_RT2_CLR_Msk (0x100000UL) /*!< RT2_CLR (Bitfield-Mask: 0x01) */ +/* ========================================================== DT =========================================================== */ +#define MCPWM_DT_DT0_Pos (0UL) /*!< DT0 (Bit 0) */ +#define MCPWM_DT_DT0_Msk (0x3ffUL) /*!< DT0 (Bitfield-Mask: 0x3ff) */ +#define MCPWM_DT_DT1_Pos (10UL) /*!< DT1 (Bit 10) */ +#define MCPWM_DT_DT1_Msk (0xffc00UL) /*!< DT1 (Bitfield-Mask: 0x3ff) */ +#define MCPWM_DT_DT2_Pos (20UL) /*!< DT2 (Bit 20) */ +#define MCPWM_DT_DT2_Msk (0x3ff00000UL) /*!< DT2 (Bitfield-Mask: 0x3ff) */ +/* ========================================================== CP =========================================================== */ +#define MCPWM_CP_CCPA0_Pos (0UL) /*!< CCPA0 (Bit 0) */ +#define MCPWM_CP_CCPA0_Msk (0x1UL) /*!< CCPA0 (Bitfield-Mask: 0x01) */ +#define MCPWM_CP_CCPB0_Pos (1UL) /*!< CCPB0 (Bit 1) */ +#define MCPWM_CP_CCPB0_Msk (0x2UL) /*!< CCPB0 (Bitfield-Mask: 0x01) */ +#define MCPWM_CP_CCPA1_Pos (2UL) /*!< CCPA1 (Bit 2) */ +#define MCPWM_CP_CCPA1_Msk (0x4UL) /*!< CCPA1 (Bitfield-Mask: 0x01) */ +#define MCPWM_CP_CCPB1_Pos (3UL) /*!< CCPB1 (Bit 3) */ +#define MCPWM_CP_CCPB1_Msk (0x8UL) /*!< CCPB1 (Bitfield-Mask: 0x01) */ +#define MCPWM_CP_CCPA2_Pos (4UL) /*!< CCPA2 (Bit 4) */ +#define MCPWM_CP_CCPA2_Msk (0x10UL) /*!< CCPA2 (Bitfield-Mask: 0x01) */ +#define MCPWM_CP_CCPB2_Pos (5UL) /*!< CCPB2 (Bit 5) */ +#define MCPWM_CP_CCPB2_Msk (0x20UL) /*!< CCPB2 (Bitfield-Mask: 0x01) */ +/* ========================================================= INTEN ========================================================= */ +#define MCPWM_INTEN_ILIM0_Pos (0UL) /*!< ILIM0 (Bit 0) */ +#define MCPWM_INTEN_ILIM0_Msk (0x1UL) /*!< ILIM0 (Bitfield-Mask: 0x01) */ +#define MCPWM_INTEN_IMAT0_Pos (1UL) /*!< IMAT0 (Bit 1) */ +#define MCPWM_INTEN_IMAT0_Msk (0x2UL) /*!< IMAT0 (Bitfield-Mask: 0x01) */ +#define MCPWM_INTEN_ICAP0_Pos (2UL) /*!< ICAP0 (Bit 2) */ +#define MCPWM_INTEN_ICAP0_Msk (0x4UL) /*!< ICAP0 (Bitfield-Mask: 0x01) */ +#define MCPWM_INTEN_ILIM1_Pos (4UL) /*!< ILIM1 (Bit 4) */ +#define MCPWM_INTEN_ILIM1_Msk (0x10UL) /*!< ILIM1 (Bitfield-Mask: 0x01) */ +#define MCPWM_INTEN_IMAT1_Pos (5UL) /*!< IMAT1 (Bit 5) */ +#define MCPWM_INTEN_IMAT1_Msk (0x20UL) /*!< IMAT1 (Bitfield-Mask: 0x01) */ +#define MCPWM_INTEN_ICAP1_Pos (6UL) /*!< ICAP1 (Bit 6) */ +#define MCPWM_INTEN_ICAP1_Msk (0x40UL) /*!< ICAP1 (Bitfield-Mask: 0x01) */ +#define MCPWM_INTEN_ILIM2_Pos (8UL) /*!< ILIM2 (Bit 8) */ +#define MCPWM_INTEN_ILIM2_Msk (0x100UL) /*!< ILIM2 (Bitfield-Mask: 0x01) */ +#define MCPWM_INTEN_IMAT2_Pos (9UL) /*!< IMAT2 (Bit 9) */ +#define MCPWM_INTEN_IMAT2_Msk (0x200UL) /*!< IMAT2 (Bitfield-Mask: 0x01) */ +#define MCPWM_INTEN_ICAP2_Pos (10UL) /*!< ICAP2 (Bit 10) */ +#define MCPWM_INTEN_ICAP2_Msk (0x400UL) /*!< ICAP2 (Bitfield-Mask: 0x01) */ +#define MCPWM_INTEN_ABORT_Pos (15UL) /*!< ABORT (Bit 15) */ +#define MCPWM_INTEN_ABORT_Msk (0x8000UL) /*!< ABORT (Bitfield-Mask: 0x01) */ +/* ======================================================= INTEN_SET ======================================================= */ +#define MCPWM_INTEN_SET_ILIM0_SET_Pos (0UL) /*!< ILIM0_SET (Bit 0) */ +#define MCPWM_INTEN_SET_ILIM0_SET_Msk (0x1UL) /*!< ILIM0_SET (Bitfield-Mask: 0x01) */ +#define MCPWM_INTEN_SET_IMAT0_SET_Pos (1UL) /*!< IMAT0_SET (Bit 1) */ +#define MCPWM_INTEN_SET_IMAT0_SET_Msk (0x2UL) /*!< IMAT0_SET (Bitfield-Mask: 0x01) */ +#define MCPWM_INTEN_SET_ICAP0_SET_Pos (2UL) /*!< ICAP0_SET (Bit 2) */ +#define MCPWM_INTEN_SET_ICAP0_SET_Msk (0x4UL) /*!< ICAP0_SET (Bitfield-Mask: 0x01) */ +#define MCPWM_INTEN_SET_ILIM1_SET_Pos (4UL) /*!< ILIM1_SET (Bit 4) */ +#define MCPWM_INTEN_SET_ILIM1_SET_Msk (0x10UL) /*!< ILIM1_SET (Bitfield-Mask: 0x01) */ +#define MCPWM_INTEN_SET_IMAT1_SET_Pos (5UL) /*!< IMAT1_SET (Bit 5) */ +#define MCPWM_INTEN_SET_IMAT1_SET_Msk (0x20UL) /*!< IMAT1_SET (Bitfield-Mask: 0x01) */ +#define MCPWM_INTEN_SET_ICAP1_SET_Pos (6UL) /*!< ICAP1_SET (Bit 6) */ +#define MCPWM_INTEN_SET_ICAP1_SET_Msk (0x40UL) /*!< ICAP1_SET (Bitfield-Mask: 0x01) */ +#define MCPWM_INTEN_SET_ILIM2_SET_Pos (9UL) /*!< ILIM2_SET (Bit 9) */ +#define MCPWM_INTEN_SET_ILIM2_SET_Msk (0x200UL) /*!< ILIM2_SET (Bitfield-Mask: 0x01) */ +#define MCPWM_INTEN_SET_IMAT2_SET_Pos (10UL) /*!< IMAT2_SET (Bit 10) */ +#define MCPWM_INTEN_SET_IMAT2_SET_Msk (0x400UL) /*!< IMAT2_SET (Bitfield-Mask: 0x01) */ +#define MCPWM_INTEN_SET_ICAP2_SET_Pos (11UL) /*!< ICAP2_SET (Bit 11) */ +#define MCPWM_INTEN_SET_ICAP2_SET_Msk (0x800UL) /*!< ICAP2_SET (Bitfield-Mask: 0x01) */ +#define MCPWM_INTEN_SET_ABORT_SET_Pos (15UL) /*!< ABORT_SET (Bit 15) */ +#define MCPWM_INTEN_SET_ABORT_SET_Msk (0x8000UL) /*!< ABORT_SET (Bitfield-Mask: 0x01) */ +/* ======================================================= INTEN_CLR ======================================================= */ +#define MCPWM_INTEN_CLR_ILIM0_CLR_Pos (0UL) /*!< ILIM0_CLR (Bit 0) */ +#define MCPWM_INTEN_CLR_ILIM0_CLR_Msk (0x1UL) /*!< ILIM0_CLR (Bitfield-Mask: 0x01) */ +#define MCPWM_INTEN_CLR_IMAT0_CLR_Pos (1UL) /*!< IMAT0_CLR (Bit 1) */ +#define MCPWM_INTEN_CLR_IMAT0_CLR_Msk (0x2UL) /*!< IMAT0_CLR (Bitfield-Mask: 0x01) */ +#define MCPWM_INTEN_CLR_ICAP0_CLR_Pos (2UL) /*!< ICAP0_CLR (Bit 2) */ +#define MCPWM_INTEN_CLR_ICAP0_CLR_Msk (0x4UL) /*!< ICAP0_CLR (Bitfield-Mask: 0x01) */ +#define MCPWM_INTEN_CLR_ILIM1_CLR_Pos (4UL) /*!< ILIM1_CLR (Bit 4) */ +#define MCPWM_INTEN_CLR_ILIM1_CLR_Msk (0x10UL) /*!< ILIM1_CLR (Bitfield-Mask: 0x01) */ +#define MCPWM_INTEN_CLR_IMAT1_CLR_Pos (5UL) /*!< IMAT1_CLR (Bit 5) */ +#define MCPWM_INTEN_CLR_IMAT1_CLR_Msk (0x20UL) /*!< IMAT1_CLR (Bitfield-Mask: 0x01) */ +#define MCPWM_INTEN_CLR_ICAP1_CLR_Pos (6UL) /*!< ICAP1_CLR (Bit 6) */ +#define MCPWM_INTEN_CLR_ICAP1_CLR_Msk (0x40UL) /*!< ICAP1_CLR (Bitfield-Mask: 0x01) */ +#define MCPWM_INTEN_CLR_ILIM2_CLR_Pos (8UL) /*!< ILIM2_CLR (Bit 8) */ +#define MCPWM_INTEN_CLR_ILIM2_CLR_Msk (0x100UL) /*!< ILIM2_CLR (Bitfield-Mask: 0x01) */ +#define MCPWM_INTEN_CLR_IMAT2_CLR_Pos (9UL) /*!< IMAT2_CLR (Bit 9) */ +#define MCPWM_INTEN_CLR_IMAT2_CLR_Msk (0x200UL) /*!< IMAT2_CLR (Bitfield-Mask: 0x01) */ +#define MCPWM_INTEN_CLR_ICAP2_CLR_Pos (10UL) /*!< ICAP2_CLR (Bit 10) */ +#define MCPWM_INTEN_CLR_ICAP2_CLR_Msk (0x400UL) /*!< ICAP2_CLR (Bitfield-Mask: 0x01) */ +#define MCPWM_INTEN_CLR_ABORT_CLR_Pos (15UL) /*!< ABORT_CLR (Bit 15) */ +#define MCPWM_INTEN_CLR_ABORT_CLR_Msk (0x8000UL) /*!< ABORT_CLR (Bitfield-Mask: 0x01) */ +/* ========================================================= INTF ========================================================== */ +#define MCPWM_INTF_ILIM0_F_Pos (0UL) /*!< ILIM0_F (Bit 0) */ +#define MCPWM_INTF_ILIM0_F_Msk (0x1UL) /*!< ILIM0_F (Bitfield-Mask: 0x01) */ +#define MCPWM_INTF_IMAT0_F_Pos (1UL) /*!< IMAT0_F (Bit 1) */ +#define MCPWM_INTF_IMAT0_F_Msk (0x2UL) /*!< IMAT0_F (Bitfield-Mask: 0x01) */ +#define MCPWM_INTF_ICAP0_F_Pos (2UL) /*!< ICAP0_F (Bit 2) */ +#define MCPWM_INTF_ICAP0_F_Msk (0x4UL) /*!< ICAP0_F (Bitfield-Mask: 0x01) */ +#define MCPWM_INTF_ILIM1_F_Pos (4UL) /*!< ILIM1_F (Bit 4) */ +#define MCPWM_INTF_ILIM1_F_Msk (0x10UL) /*!< ILIM1_F (Bitfield-Mask: 0x01) */ +#define MCPWM_INTF_IMAT1_F_Pos (5UL) /*!< IMAT1_F (Bit 5) */ +#define MCPWM_INTF_IMAT1_F_Msk (0x20UL) /*!< IMAT1_F (Bitfield-Mask: 0x01) */ +#define MCPWM_INTF_ICAP1_F_Pos (6UL) /*!< ICAP1_F (Bit 6) */ +#define MCPWM_INTF_ICAP1_F_Msk (0x40UL) /*!< ICAP1_F (Bitfield-Mask: 0x01) */ +#define MCPWM_INTF_ILIM2_F_Pos (8UL) /*!< ILIM2_F (Bit 8) */ +#define MCPWM_INTF_ILIM2_F_Msk (0x100UL) /*!< ILIM2_F (Bitfield-Mask: 0x01) */ +#define MCPWM_INTF_IMAT2_F_Pos (9UL) /*!< IMAT2_F (Bit 9) */ +#define MCPWM_INTF_IMAT2_F_Msk (0x200UL) /*!< IMAT2_F (Bitfield-Mask: 0x01) */ +#define MCPWM_INTF_ICAP2_F_Pos (10UL) /*!< ICAP2_F (Bit 10) */ +#define MCPWM_INTF_ICAP2_F_Msk (0x400UL) /*!< ICAP2_F (Bitfield-Mask: 0x01) */ +#define MCPWM_INTF_ABORT_F_Pos (15UL) /*!< ABORT_F (Bit 15) */ +#define MCPWM_INTF_ABORT_F_Msk (0x8000UL) /*!< ABORT_F (Bitfield-Mask: 0x01) */ +/* ======================================================= INTF_SET ======================================================== */ +#define MCPWM_INTF_SET_ILIM0_F_SET_Pos (0UL) /*!< ILIM0_F_SET (Bit 0) */ +#define MCPWM_INTF_SET_ILIM0_F_SET_Msk (0x1UL) /*!< ILIM0_F_SET (Bitfield-Mask: 0x01) */ +#define MCPWM_INTF_SET_IMAT0_F_SET_Pos (1UL) /*!< IMAT0_F_SET (Bit 1) */ +#define MCPWM_INTF_SET_IMAT0_F_SET_Msk (0x2UL) /*!< IMAT0_F_SET (Bitfield-Mask: 0x01) */ +#define MCPWM_INTF_SET_ICAP0_F_SET_Pos (2UL) /*!< ICAP0_F_SET (Bit 2) */ +#define MCPWM_INTF_SET_ICAP0_F_SET_Msk (0x4UL) /*!< ICAP0_F_SET (Bitfield-Mask: 0x01) */ +#define MCPWM_INTF_SET_ILIM1_F_SET_Pos (4UL) /*!< ILIM1_F_SET (Bit 4) */ +#define MCPWM_INTF_SET_ILIM1_F_SET_Msk (0x10UL) /*!< ILIM1_F_SET (Bitfield-Mask: 0x01) */ +#define MCPWM_INTF_SET_IMAT1_F_SET_Pos (5UL) /*!< IMAT1_F_SET (Bit 5) */ +#define MCPWM_INTF_SET_IMAT1_F_SET_Msk (0x20UL) /*!< IMAT1_F_SET (Bitfield-Mask: 0x01) */ +#define MCPWM_INTF_SET_ICAP1_F_SET_Pos (6UL) /*!< ICAP1_F_SET (Bit 6) */ +#define MCPWM_INTF_SET_ICAP1_F_SET_Msk (0x40UL) /*!< ICAP1_F_SET (Bitfield-Mask: 0x01) */ +#define MCPWM_INTF_SET_ILIM2_F_SET_Pos (8UL) /*!< ILIM2_F_SET (Bit 8) */ +#define MCPWM_INTF_SET_ILIM2_F_SET_Msk (0x100UL) /*!< ILIM2_F_SET (Bitfield-Mask: 0x01) */ +#define MCPWM_INTF_SET_IMAT2_F_SET_Pos (9UL) /*!< IMAT2_F_SET (Bit 9) */ +#define MCPWM_INTF_SET_IMAT2_F_SET_Msk (0x200UL) /*!< IMAT2_F_SET (Bitfield-Mask: 0x01) */ +#define MCPWM_INTF_SET_ICAP2_F_SET_Pos (10UL) /*!< ICAP2_F_SET (Bit 10) */ +#define MCPWM_INTF_SET_ICAP2_F_SET_Msk (0x400UL) /*!< ICAP2_F_SET (Bitfield-Mask: 0x01) */ +#define MCPWM_INTF_SET_ABORT_F_SET_Pos (15UL) /*!< ABORT_F_SET (Bit 15) */ +#define MCPWM_INTF_SET_ABORT_F_SET_Msk (0x8000UL) /*!< ABORT_F_SET (Bitfield-Mask: 0x01) */ +/* ======================================================= INTF_CLR ======================================================== */ +#define MCPWM_INTF_CLR_ILIM0_F_CLR_Pos (0UL) /*!< ILIM0_F_CLR (Bit 0) */ +#define MCPWM_INTF_CLR_ILIM0_F_CLR_Msk (0x1UL) /*!< ILIM0_F_CLR (Bitfield-Mask: 0x01) */ +#define MCPWM_INTF_CLR_IMAT0_F_CLR_Pos (1UL) /*!< IMAT0_F_CLR (Bit 1) */ +#define MCPWM_INTF_CLR_IMAT0_F_CLR_Msk (0x2UL) /*!< IMAT0_F_CLR (Bitfield-Mask: 0x01) */ +#define MCPWM_INTF_CLR_ICAP0_F_CLR_Pos (2UL) /*!< ICAP0_F_CLR (Bit 2) */ +#define MCPWM_INTF_CLR_ICAP0_F_CLR_Msk (0x4UL) /*!< ICAP0_F_CLR (Bitfield-Mask: 0x01) */ +#define MCPWM_INTF_CLR_ILIM1_F_CLR_Pos (4UL) /*!< ILIM1_F_CLR (Bit 4) */ +#define MCPWM_INTF_CLR_ILIM1_F_CLR_Msk (0x10UL) /*!< ILIM1_F_CLR (Bitfield-Mask: 0x01) */ +#define MCPWM_INTF_CLR_IMAT1_F_CLR_Pos (5UL) /*!< IMAT1_F_CLR (Bit 5) */ +#define MCPWM_INTF_CLR_IMAT1_F_CLR_Msk (0x20UL) /*!< IMAT1_F_CLR (Bitfield-Mask: 0x01) */ +#define MCPWM_INTF_CLR_ICAP1_F_CLR_Pos (6UL) /*!< ICAP1_F_CLR (Bit 6) */ +#define MCPWM_INTF_CLR_ICAP1_F_CLR_Msk (0x40UL) /*!< ICAP1_F_CLR (Bitfield-Mask: 0x01) */ +#define MCPWM_INTF_CLR_ILIM2_F_CLR_Pos (8UL) /*!< ILIM2_F_CLR (Bit 8) */ +#define MCPWM_INTF_CLR_ILIM2_F_CLR_Msk (0x100UL) /*!< ILIM2_F_CLR (Bitfield-Mask: 0x01) */ +#define MCPWM_INTF_CLR_IMAT2_F_CLR_Pos (9UL) /*!< IMAT2_F_CLR (Bit 9) */ +#define MCPWM_INTF_CLR_IMAT2_F_CLR_Msk (0x200UL) /*!< IMAT2_F_CLR (Bitfield-Mask: 0x01) */ +#define MCPWM_INTF_CLR_ICAP2_F_CLR_Pos (10UL) /*!< ICAP2_F_CLR (Bit 10) */ +#define MCPWM_INTF_CLR_ICAP2_F_CLR_Msk (0x400UL) /*!< ICAP2_F_CLR (Bitfield-Mask: 0x01) */ +#define MCPWM_INTF_CLR_ABORT_F_CLR_Pos (15UL) /*!< ABORT_F_CLR (Bit 15) */ +#define MCPWM_INTF_CLR_ABORT_F_CLR_Msk (0x8000UL) /*!< ABORT_F_CLR (Bitfield-Mask: 0x01) */ +/* ======================================================== CNTCON ========================================================= */ +#define MCPWM_CNTCON_TC0MCI0_RE_Pos (0UL) /*!< TC0MCI0_RE (Bit 0) */ +#define MCPWM_CNTCON_TC0MCI0_RE_Msk (0x1UL) /*!< TC0MCI0_RE (Bitfield-Mask: 0x01) */ +#define MCPWM_CNTCON_TC0MCI0_FE_Pos (1UL) /*!< TC0MCI0_FE (Bit 1) */ +#define MCPWM_CNTCON_TC0MCI0_FE_Msk (0x2UL) /*!< TC0MCI0_FE (Bitfield-Mask: 0x01) */ +#define MCPWM_CNTCON_TC0MCI1_RE_Pos (2UL) /*!< TC0MCI1_RE (Bit 2) */ +#define MCPWM_CNTCON_TC0MCI1_RE_Msk (0x4UL) /*!< TC0MCI1_RE (Bitfield-Mask: 0x01) */ +#define MCPWM_CNTCON_TC0MCI1_FE_Pos (3UL) /*!< TC0MCI1_FE (Bit 3) */ +#define MCPWM_CNTCON_TC0MCI1_FE_Msk (0x8UL) /*!< TC0MCI1_FE (Bitfield-Mask: 0x01) */ +#define MCPWM_CNTCON_TC0MCI2_RE_Pos (4UL) /*!< TC0MCI2_RE (Bit 4) */ +#define MCPWM_CNTCON_TC0MCI2_RE_Msk (0x10UL) /*!< TC0MCI2_RE (Bitfield-Mask: 0x01) */ +#define MCPWM_CNTCON_TC0MCI2_FE_Pos (5UL) /*!< TC0MCI2_FE (Bit 5) */ +#define MCPWM_CNTCON_TC0MCI2_FE_Msk (0x20UL) /*!< TC0MCI2_FE (Bitfield-Mask: 0x01) */ +#define MCPWM_CNTCON_TC1MCI0_RE_Pos (6UL) /*!< TC1MCI0_RE (Bit 6) */ +#define MCPWM_CNTCON_TC1MCI0_RE_Msk (0x40UL) /*!< TC1MCI0_RE (Bitfield-Mask: 0x01) */ +#define MCPWM_CNTCON_TC1MCI0_FE_Pos (7UL) /*!< TC1MCI0_FE (Bit 7) */ +#define MCPWM_CNTCON_TC1MCI0_FE_Msk (0x80UL) /*!< TC1MCI0_FE (Bitfield-Mask: 0x01) */ +#define MCPWM_CNTCON_TC1MCI1_RE_Pos (8UL) /*!< TC1MCI1_RE (Bit 8) */ +#define MCPWM_CNTCON_TC1MCI1_RE_Msk (0x100UL) /*!< TC1MCI1_RE (Bitfield-Mask: 0x01) */ +#define MCPWM_CNTCON_TC1MCI1_FE_Pos (9UL) /*!< TC1MCI1_FE (Bit 9) */ +#define MCPWM_CNTCON_TC1MCI1_FE_Msk (0x200UL) /*!< TC1MCI1_FE (Bitfield-Mask: 0x01) */ +#define MCPWM_CNTCON_TC1MCI2_RE_Pos (10UL) /*!< TC1MCI2_RE (Bit 10) */ +#define MCPWM_CNTCON_TC1MCI2_RE_Msk (0x400UL) /*!< TC1MCI2_RE (Bitfield-Mask: 0x01) */ +#define MCPWM_CNTCON_TC1MCI2_FE_Pos (11UL) /*!< TC1MCI2_FE (Bit 11) */ +#define MCPWM_CNTCON_TC1MCI2_FE_Msk (0x800UL) /*!< TC1MCI2_FE (Bitfield-Mask: 0x01) */ +#define MCPWM_CNTCON_TC2MCI0_RE_Pos (12UL) /*!< TC2MCI0_RE (Bit 12) */ +#define MCPWM_CNTCON_TC2MCI0_RE_Msk (0x1000UL) /*!< TC2MCI0_RE (Bitfield-Mask: 0x01) */ +#define MCPWM_CNTCON_TC2MCI0_FE_Pos (13UL) /*!< TC2MCI0_FE (Bit 13) */ +#define MCPWM_CNTCON_TC2MCI0_FE_Msk (0x2000UL) /*!< TC2MCI0_FE (Bitfield-Mask: 0x01) */ +#define MCPWM_CNTCON_TC2MCI1_RE_Pos (14UL) /*!< TC2MCI1_RE (Bit 14) */ +#define MCPWM_CNTCON_TC2MCI1_RE_Msk (0x4000UL) /*!< TC2MCI1_RE (Bitfield-Mask: 0x01) */ +#define MCPWM_CNTCON_TC2MCI1_FE_Pos (15UL) /*!< TC2MCI1_FE (Bit 15) */ +#define MCPWM_CNTCON_TC2MCI1_FE_Msk (0x8000UL) /*!< TC2MCI1_FE (Bitfield-Mask: 0x01) */ +#define MCPWM_CNTCON_TC2MCI2_RE_Pos (16UL) /*!< TC2MCI2_RE (Bit 16) */ +#define MCPWM_CNTCON_TC2MCI2_RE_Msk (0x10000UL) /*!< TC2MCI2_RE (Bitfield-Mask: 0x01) */ +#define MCPWM_CNTCON_TC2MCI2_FE_Pos (17UL) /*!< TC2MCI2_FE (Bit 17) */ +#define MCPWM_CNTCON_TC2MCI2_FE_Msk (0x20000UL) /*!< TC2MCI2_FE (Bitfield-Mask: 0x01) */ +#define MCPWM_CNTCON_CNTR0_Pos (29UL) /*!< CNTR0 (Bit 29) */ +#define MCPWM_CNTCON_CNTR0_Msk (0x20000000UL) /*!< CNTR0 (Bitfield-Mask: 0x01) */ +#define MCPWM_CNTCON_CNTR1_Pos (30UL) /*!< CNTR1 (Bit 30) */ +#define MCPWM_CNTCON_CNTR1_Msk (0x40000000UL) /*!< CNTR1 (Bitfield-Mask: 0x01) */ +#define MCPWM_CNTCON_CNTR2_Pos (31UL) /*!< CNTR2 (Bit 31) */ +#define MCPWM_CNTCON_CNTR2_Msk (0x80000000UL) /*!< CNTR2 (Bitfield-Mask: 0x01) */ +/* ====================================================== CNTCON_SET ======================================================= */ +#define MCPWM_CNTCON_SET_TC0MCI0_RE_SET_Pos (0UL) /*!< TC0MCI0_RE_SET (Bit 0) */ +#define MCPWM_CNTCON_SET_TC0MCI0_RE_SET_Msk (0x1UL) /*!< TC0MCI0_RE_SET (Bitfield-Mask: 0x01) */ +#define MCPWM_CNTCON_SET_TC0MCI0_FE_SET_Pos (1UL) /*!< TC0MCI0_FE_SET (Bit 1) */ +#define MCPWM_CNTCON_SET_TC0MCI0_FE_SET_Msk (0x2UL) /*!< TC0MCI0_FE_SET (Bitfield-Mask: 0x01) */ +#define MCPWM_CNTCON_SET_TC0MCI1_RE_SET_Pos (2UL) /*!< TC0MCI1_RE_SET (Bit 2) */ +#define MCPWM_CNTCON_SET_TC0MCI1_RE_SET_Msk (0x4UL) /*!< TC0MCI1_RE_SET (Bitfield-Mask: 0x01) */ +#define MCPWM_CNTCON_SET_TC0MCI1_FE_SET_Pos (3UL) /*!< TC0MCI1_FE_SET (Bit 3) */ +#define MCPWM_CNTCON_SET_TC0MCI1_FE_SET_Msk (0x8UL) /*!< TC0MCI1_FE_SET (Bitfield-Mask: 0x01) */ +#define MCPWM_CNTCON_SET_TC0MCI2_RE_SET_Pos (4UL) /*!< TC0MCI2_RE_SET (Bit 4) */ +#define MCPWM_CNTCON_SET_TC0MCI2_RE_SET_Msk (0x10UL) /*!< TC0MCI2_RE_SET (Bitfield-Mask: 0x01) */ +#define MCPWM_CNTCON_SET_TC0MCI2_FE_SET_Pos (5UL) /*!< TC0MCI2_FE_SET (Bit 5) */ +#define MCPWM_CNTCON_SET_TC0MCI2_FE_SET_Msk (0x20UL) /*!< TC0MCI2_FE_SET (Bitfield-Mask: 0x01) */ +#define MCPWM_CNTCON_SET_TC1MCI0_RE_SET_Pos (6UL) /*!< TC1MCI0_RE_SET (Bit 6) */ +#define MCPWM_CNTCON_SET_TC1MCI0_RE_SET_Msk (0x40UL) /*!< TC1MCI0_RE_SET (Bitfield-Mask: 0x01) */ +#define MCPWM_CNTCON_SET_TC1MCI0_FE_SET_Pos (7UL) /*!< TC1MCI0_FE_SET (Bit 7) */ +#define MCPWM_CNTCON_SET_TC1MCI0_FE_SET_Msk (0x80UL) /*!< TC1MCI0_FE_SET (Bitfield-Mask: 0x01) */ +#define MCPWM_CNTCON_SET_TC1MCI1_RE_SET_Pos (8UL) /*!< TC1MCI1_RE_SET (Bit 8) */ +#define MCPWM_CNTCON_SET_TC1MCI1_RE_SET_Msk (0x100UL) /*!< TC1MCI1_RE_SET (Bitfield-Mask: 0x01) */ +#define MCPWM_CNTCON_SET_TC1MCI1_FE_SET_Pos (9UL) /*!< TC1MCI1_FE_SET (Bit 9) */ +#define MCPWM_CNTCON_SET_TC1MCI1_FE_SET_Msk (0x200UL) /*!< TC1MCI1_FE_SET (Bitfield-Mask: 0x01) */ +#define MCPWM_CNTCON_SET_TC1MCI2_RE_SET_Pos (10UL) /*!< TC1MCI2_RE_SET (Bit 10) */ +#define MCPWM_CNTCON_SET_TC1MCI2_RE_SET_Msk (0x400UL) /*!< TC1MCI2_RE_SET (Bitfield-Mask: 0x01) */ +#define MCPWM_CNTCON_SET_TC1MCI2_FE_SET_Pos (11UL) /*!< TC1MCI2_FE_SET (Bit 11) */ +#define MCPWM_CNTCON_SET_TC1MCI2_FE_SET_Msk (0x800UL) /*!< TC1MCI2_FE_SET (Bitfield-Mask: 0x01) */ +#define MCPWM_CNTCON_SET_TC2MCI0_RE_SET_Pos (12UL) /*!< TC2MCI0_RE_SET (Bit 12) */ +#define MCPWM_CNTCON_SET_TC2MCI0_RE_SET_Msk (0x1000UL) /*!< TC2MCI0_RE_SET (Bitfield-Mask: 0x01) */ +#define MCPWM_CNTCON_SET_TC2MCI0_FE_SET_Pos (13UL) /*!< TC2MCI0_FE_SET (Bit 13) */ +#define MCPWM_CNTCON_SET_TC2MCI0_FE_SET_Msk (0x2000UL) /*!< TC2MCI0_FE_SET (Bitfield-Mask: 0x01) */ +#define MCPWM_CNTCON_SET_TC2MCI1_RE_SET_Pos (14UL) /*!< TC2MCI1_RE_SET (Bit 14) */ +#define MCPWM_CNTCON_SET_TC2MCI1_RE_SET_Msk (0x4000UL) /*!< TC2MCI1_RE_SET (Bitfield-Mask: 0x01) */ +#define MCPWM_CNTCON_SET_TC2MCI1_FE_SET_Pos (15UL) /*!< TC2MCI1_FE_SET (Bit 15) */ +#define MCPWM_CNTCON_SET_TC2MCI1_FE_SET_Msk (0x8000UL) /*!< TC2MCI1_FE_SET (Bitfield-Mask: 0x01) */ +#define MCPWM_CNTCON_SET_TC2MCI2_RE_SET_Pos (16UL) /*!< TC2MCI2_RE_SET (Bit 16) */ +#define MCPWM_CNTCON_SET_TC2MCI2_RE_SET_Msk (0x10000UL) /*!< TC2MCI2_RE_SET (Bitfield-Mask: 0x01) */ +#define MCPWM_CNTCON_SET_TC2MCI2_FE_SET_Pos (17UL) /*!< TC2MCI2_FE_SET (Bit 17) */ +#define MCPWM_CNTCON_SET_TC2MCI2_FE_SET_Msk (0x20000UL) /*!< TC2MCI2_FE_SET (Bitfield-Mask: 0x01) */ +#define MCPWM_CNTCON_SET_CNTR0_SET_Pos (29UL) /*!< CNTR0_SET (Bit 29) */ +#define MCPWM_CNTCON_SET_CNTR0_SET_Msk (0x20000000UL) /*!< CNTR0_SET (Bitfield-Mask: 0x01) */ +#define MCPWM_CNTCON_SET_CNTR1_SET_Pos (30UL) /*!< CNTR1_SET (Bit 30) */ +#define MCPWM_CNTCON_SET_CNTR1_SET_Msk (0x40000000UL) /*!< CNTR1_SET (Bitfield-Mask: 0x01) */ +#define MCPWM_CNTCON_SET_CNTR2_SET_Pos (31UL) /*!< CNTR2_SET (Bit 31) */ +#define MCPWM_CNTCON_SET_CNTR2_SET_Msk (0x80000000UL) /*!< CNTR2_SET (Bitfield-Mask: 0x01) */ +/* ====================================================== CNTCON_CLR ======================================================= */ +#define MCPWM_CNTCON_CLR_TC0MCI0_RE_CLR_Pos (0UL) /*!< TC0MCI0_RE_CLR (Bit 0) */ +#define MCPWM_CNTCON_CLR_TC0MCI0_RE_CLR_Msk (0x1UL) /*!< TC0MCI0_RE_CLR (Bitfield-Mask: 0x01) */ +#define MCPWM_CNTCON_CLR_TC0MCI0_FE_CLR_Pos (1UL) /*!< TC0MCI0_FE_CLR (Bit 1) */ +#define MCPWM_CNTCON_CLR_TC0MCI0_FE_CLR_Msk (0x2UL) /*!< TC0MCI0_FE_CLR (Bitfield-Mask: 0x01) */ +#define MCPWM_CNTCON_CLR_TC0MCI1_RE_CLR_Pos (2UL) /*!< TC0MCI1_RE_CLR (Bit 2) */ +#define MCPWM_CNTCON_CLR_TC0MCI1_RE_CLR_Msk (0x4UL) /*!< TC0MCI1_RE_CLR (Bitfield-Mask: 0x01) */ +#define MCPWM_CNTCON_CLR_TC0MCI1_FE_CLR_Pos (3UL) /*!< TC0MCI1_FE_CLR (Bit 3) */ +#define MCPWM_CNTCON_CLR_TC0MCI1_FE_CLR_Msk (0x8UL) /*!< TC0MCI1_FE_CLR (Bitfield-Mask: 0x01) */ +#define MCPWM_CNTCON_CLR_TC0MCI2_RE_Pos (4UL) /*!< TC0MCI2_RE (Bit 4) */ +#define MCPWM_CNTCON_CLR_TC0MCI2_RE_Msk (0x10UL) /*!< TC0MCI2_RE (Bitfield-Mask: 0x01) */ +#define MCPWM_CNTCON_CLR_TC0MCI2_FE_CLR_Pos (5UL) /*!< TC0MCI2_FE_CLR (Bit 5) */ +#define MCPWM_CNTCON_CLR_TC0MCI2_FE_CLR_Msk (0x20UL) /*!< TC0MCI2_FE_CLR (Bitfield-Mask: 0x01) */ +#define MCPWM_CNTCON_CLR_TC1MCI0_RE_CLR_Pos (6UL) /*!< TC1MCI0_RE_CLR (Bit 6) */ +#define MCPWM_CNTCON_CLR_TC1MCI0_RE_CLR_Msk (0x40UL) /*!< TC1MCI0_RE_CLR (Bitfield-Mask: 0x01) */ +#define MCPWM_CNTCON_CLR_TC1MCI0_FE_CLR_Pos (7UL) /*!< TC1MCI0_FE_CLR (Bit 7) */ +#define MCPWM_CNTCON_CLR_TC1MCI0_FE_CLR_Msk (0x80UL) /*!< TC1MCI0_FE_CLR (Bitfield-Mask: 0x01) */ +#define MCPWM_CNTCON_CLR_TC1MCI1_RE_CLR_Pos (8UL) /*!< TC1MCI1_RE_CLR (Bit 8) */ +#define MCPWM_CNTCON_CLR_TC1MCI1_RE_CLR_Msk (0x100UL) /*!< TC1MCI1_RE_CLR (Bitfield-Mask: 0x01) */ +#define MCPWM_CNTCON_CLR_TC1MCI1_FE_CLR_Pos (9UL) /*!< TC1MCI1_FE_CLR (Bit 9) */ +#define MCPWM_CNTCON_CLR_TC1MCI1_FE_CLR_Msk (0x200UL) /*!< TC1MCI1_FE_CLR (Bitfield-Mask: 0x01) */ +#define MCPWM_CNTCON_CLR_TC1MCI2_RE_CLR_Pos (10UL) /*!< TC1MCI2_RE_CLR (Bit 10) */ +#define MCPWM_CNTCON_CLR_TC1MCI2_RE_CLR_Msk (0x400UL) /*!< TC1MCI2_RE_CLR (Bitfield-Mask: 0x01) */ +#define MCPWM_CNTCON_CLR_TC1MCI2_FE_CLR_Pos (11UL) /*!< TC1MCI2_FE_CLR (Bit 11) */ +#define MCPWM_CNTCON_CLR_TC1MCI2_FE_CLR_Msk (0x800UL) /*!< TC1MCI2_FE_CLR (Bitfield-Mask: 0x01) */ +#define MCPWM_CNTCON_CLR_TC2MCI0_RE_CLR_Pos (12UL) /*!< TC2MCI0_RE_CLR (Bit 12) */ +#define MCPWM_CNTCON_CLR_TC2MCI0_RE_CLR_Msk (0x1000UL) /*!< TC2MCI0_RE_CLR (Bitfield-Mask: 0x01) */ +#define MCPWM_CNTCON_CLR_TC2MCI0_FE_CLR_Pos (13UL) /*!< TC2MCI0_FE_CLR (Bit 13) */ +#define MCPWM_CNTCON_CLR_TC2MCI0_FE_CLR_Msk (0x2000UL) /*!< TC2MCI0_FE_CLR (Bitfield-Mask: 0x01) */ +#define MCPWM_CNTCON_CLR_TC2MCI1_RE_CLR_Pos (14UL) /*!< TC2MCI1_RE_CLR (Bit 14) */ +#define MCPWM_CNTCON_CLR_TC2MCI1_RE_CLR_Msk (0x4000UL) /*!< TC2MCI1_RE_CLR (Bitfield-Mask: 0x01) */ +#define MCPWM_CNTCON_CLR_TC2MCI1_FE_CLR_Pos (15UL) /*!< TC2MCI1_FE_CLR (Bit 15) */ +#define MCPWM_CNTCON_CLR_TC2MCI1_FE_CLR_Msk (0x8000UL) /*!< TC2MCI1_FE_CLR (Bitfield-Mask: 0x01) */ +#define MCPWM_CNTCON_CLR_TC2MCI2_RE_CLR_Pos (16UL) /*!< TC2MCI2_RE_CLR (Bit 16) */ +#define MCPWM_CNTCON_CLR_TC2MCI2_RE_CLR_Msk (0x10000UL) /*!< TC2MCI2_RE_CLR (Bitfield-Mask: 0x01) */ +#define MCPWM_CNTCON_CLR_TC2MCI2_FE_CLR_Pos (17UL) /*!< TC2MCI2_FE_CLR (Bit 17) */ +#define MCPWM_CNTCON_CLR_TC2MCI2_FE_CLR_Msk (0x20000UL) /*!< TC2MCI2_FE_CLR (Bitfield-Mask: 0x01) */ +#define MCPWM_CNTCON_CLR_CNTR0_CLR_Pos (29UL) /*!< CNTR0_CLR (Bit 29) */ +#define MCPWM_CNTCON_CLR_CNTR0_CLR_Msk (0x20000000UL) /*!< CNTR0_CLR (Bitfield-Mask: 0x01) */ +#define MCPWM_CNTCON_CLR_CNTR1_CLR_Pos (30UL) /*!< CNTR1_CLR (Bit 30) */ +#define MCPWM_CNTCON_CLR_CNTR1_CLR_Msk (0x40000000UL) /*!< CNTR1_CLR (Bitfield-Mask: 0x01) */ +#define MCPWM_CNTCON_CLR_CNTR2_CLR_Pos (31UL) /*!< CNTR2_CLR (Bit 31) */ +#define MCPWM_CNTCON_CLR_CNTR2_CLR_Msk (0x80000000UL) /*!< CNTR2_CLR (Bitfield-Mask: 0x01) */ +/* ======================================================== CAP_CLR ======================================================== */ +#define MCPWM_CAP_CLR_CAP_CLR0_Pos (0UL) /*!< CAP_CLR0 (Bit 0) */ +#define MCPWM_CAP_CLR_CAP_CLR0_Msk (0x1UL) /*!< CAP_CLR0 (Bitfield-Mask: 0x01) */ +#define MCPWM_CAP_CLR_CAP_CLR1_Pos (1UL) /*!< CAP_CLR1 (Bit 1) */ +#define MCPWM_CAP_CLR_CAP_CLR1_Msk (0x2UL) /*!< CAP_CLR1 (Bitfield-Mask: 0x01) */ +#define MCPWM_CAP_CLR_CAP_CLR2_Pos (2UL) /*!< CAP_CLR2 (Bit 2) */ +#define MCPWM_CAP_CLR_CAP_CLR2_Msk (0x4UL) /*!< CAP_CLR2 (Bitfield-Mask: 0x01) */ + + +/* =========================================================================================================================== */ +/* ================ LPC_QEI ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== CON ========================================================== */ +#define QEI_CON_RESP_Pos (0UL) /*!< RESP (Bit 0) */ +#define QEI_CON_RESP_Msk (0x1UL) /*!< RESP (Bitfield-Mask: 0x01) */ +#define QEI_CON_RESPI_Pos (1UL) /*!< RESPI (Bit 1) */ +#define QEI_CON_RESPI_Msk (0x2UL) /*!< RESPI (Bitfield-Mask: 0x01) */ +#define QEI_CON_RESV_Pos (2UL) /*!< RESV (Bit 2) */ +#define QEI_CON_RESV_Msk (0x4UL) /*!< RESV (Bitfield-Mask: 0x01) */ +#define QEI_CON_RESI_Pos (3UL) /*!< RESI (Bit 3) */ +#define QEI_CON_RESI_Msk (0x8UL) /*!< RESI (Bitfield-Mask: 0x01) */ +/* ========================================================= CONF ========================================================== */ +#define QEI_CONF_DIRINV_Pos (0UL) /*!< DIRINV (Bit 0) */ +#define QEI_CONF_DIRINV_Msk (0x1UL) /*!< DIRINV (Bitfield-Mask: 0x01) */ +#define QEI_CONF_SIGMODE_Pos (1UL) /*!< SIGMODE (Bit 1) */ +#define QEI_CONF_SIGMODE_Msk (0x2UL) /*!< SIGMODE (Bitfield-Mask: 0x01) */ +#define QEI_CONF_CAPMODE_Pos (2UL) /*!< CAPMODE (Bit 2) */ +#define QEI_CONF_CAPMODE_Msk (0x4UL) /*!< CAPMODE (Bitfield-Mask: 0x01) */ +#define QEI_CONF_INVINX_Pos (3UL) /*!< INVINX (Bit 3) */ +#define QEI_CONF_INVINX_Msk (0x8UL) /*!< INVINX (Bitfield-Mask: 0x01) */ +#define QEI_CONF_CRESPI_Pos (4UL) /*!< CRESPI (Bit 4) */ +#define QEI_CONF_CRESPI_Msk (0x10UL) /*!< CRESPI (Bitfield-Mask: 0x01) */ +#define QEI_CONF_INXGATE_Pos (16UL) /*!< INXGATE (Bit 16) */ +#define QEI_CONF_INXGATE_Msk (0xf0000UL) /*!< INXGATE (Bitfield-Mask: 0x0f) */ +/* ========================================================= STAT ========================================================== */ +#define QEI_STAT_DIR_Pos (0UL) /*!< DIR (Bit 0) */ +#define QEI_STAT_DIR_Msk (0x1UL) /*!< DIR (Bitfield-Mask: 0x01) */ +/* ========================================================== POS ========================================================== */ +#define QEI_POS_POS_Pos (0UL) /*!< POS (Bit 0) */ +#define QEI_POS_POS_Msk (0xffffffffUL) /*!< POS (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== MAXPOS ========================================================= */ +#define QEI_MAXPOS_MAXPOS_Pos (0UL) /*!< MAXPOS (Bit 0) */ +#define QEI_MAXPOS_MAXPOS_Msk (0xffffffffUL) /*!< MAXPOS (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== CMPOS0 ========================================================= */ +#define QEI_CMPOS0_PCMP0_Pos (0UL) /*!< PCMP0 (Bit 0) */ +#define QEI_CMPOS0_PCMP0_Msk (0xffffffffUL) /*!< PCMP0 (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== CMPOS1 ========================================================= */ +#define QEI_CMPOS1_PCMP1_Pos (0UL) /*!< PCMP1 (Bit 0) */ +#define QEI_CMPOS1_PCMP1_Msk (0xffffffffUL) /*!< PCMP1 (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== CMPOS2 ========================================================= */ +#define QEI_CMPOS2_PCMP2_Pos (0UL) /*!< PCMP2 (Bit 0) */ +#define QEI_CMPOS2_PCMP2_Msk (0xffffffffUL) /*!< PCMP2 (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== INXCNT ========================================================= */ +#define QEI_INXCNT_ENCPOS_Pos (0UL) /*!< ENCPOS (Bit 0) */ +#define QEI_INXCNT_ENCPOS_Msk (0xffffffffUL) /*!< ENCPOS (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== INXCMP0 ======================================================== */ +#define QEI_INXCMP0_ICMP0_Pos (0UL) /*!< ICMP0 (Bit 0) */ +#define QEI_INXCMP0_ICMP0_Msk (0xffffffffUL) /*!< ICMP0 (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= LOAD ========================================================== */ +#define QEI_LOAD_VELLOAD_Pos (0UL) /*!< VELLOAD (Bit 0) */ +#define QEI_LOAD_VELLOAD_Msk (0xffffffffUL) /*!< VELLOAD (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= TIME ========================================================== */ +#define QEI_TIME_VELVAL_Pos (0UL) /*!< VELVAL (Bit 0) */ +#define QEI_TIME_VELVAL_Msk (0xffffffffUL) /*!< VELVAL (Bitfield-Mask: 0xffffffff) */ +/* ========================================================== VEL ========================================================== */ +#define QEI_VEL_VELPC_Pos (0UL) /*!< VELPC (Bit 0) */ +#define QEI_VEL_VELPC_Msk (0xffffffffUL) /*!< VELPC (Bitfield-Mask: 0xffffffff) */ +/* ========================================================== CAP ========================================================== */ +#define QEI_CAP_VELCAP_Pos (0UL) /*!< VELCAP (Bit 0) */ +#define QEI_CAP_VELCAP_Msk (0xffffffffUL) /*!< VELCAP (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== VELCOMP ======================================================== */ +#define QEI_VELCOMP_VELPC_Pos (0UL) /*!< VELPC (Bit 0) */ +#define QEI_VELCOMP_VELPC_Msk (0xffffffffUL) /*!< VELPC (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== FILTER ========================================================= */ +#define QEI_FILTER_FILTA_Pos (0UL) /*!< FILTA (Bit 0) */ +#define QEI_FILTER_FILTA_Msk (0xffffffffUL) /*!< FILTA (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== INTSTAT ======================================================== */ +#define QEI_INTSTAT_INX_INT_Pos (0UL) /*!< INX_INT (Bit 0) */ +#define QEI_INTSTAT_INX_INT_Msk (0x1UL) /*!< INX_INT (Bitfield-Mask: 0x01) */ +#define QEI_INTSTAT_TIM_INT_Pos (1UL) /*!< TIM_INT (Bit 1) */ +#define QEI_INTSTAT_TIM_INT_Msk (0x2UL) /*!< TIM_INT (Bitfield-Mask: 0x01) */ +#define QEI_INTSTAT_VELC_INT_Pos (2UL) /*!< VELC_INT (Bit 2) */ +#define QEI_INTSTAT_VELC_INT_Msk (0x4UL) /*!< VELC_INT (Bitfield-Mask: 0x01) */ +#define QEI_INTSTAT_DIR_INT_Pos (3UL) /*!< DIR_INT (Bit 3) */ +#define QEI_INTSTAT_DIR_INT_Msk (0x8UL) /*!< DIR_INT (Bitfield-Mask: 0x01) */ +#define QEI_INTSTAT_ERR_INT_Pos (4UL) /*!< ERR_INT (Bit 4) */ +#define QEI_INTSTAT_ERR_INT_Msk (0x10UL) /*!< ERR_INT (Bitfield-Mask: 0x01) */ +#define QEI_INTSTAT_ENCLK_INT_Pos (5UL) /*!< ENCLK_INT (Bit 5) */ +#define QEI_INTSTAT_ENCLK_INT_Msk (0x20UL) /*!< ENCLK_INT (Bitfield-Mask: 0x01) */ +#define QEI_INTSTAT_POS0_INT_Pos (6UL) /*!< POS0_INT (Bit 6) */ +#define QEI_INTSTAT_POS0_INT_Msk (0x40UL) /*!< POS0_INT (Bitfield-Mask: 0x01) */ +#define QEI_INTSTAT_POS1_INT_Pos (7UL) /*!< POS1_INT (Bit 7) */ +#define QEI_INTSTAT_POS1_INT_Msk (0x80UL) /*!< POS1_INT (Bitfield-Mask: 0x01) */ +#define QEI_INTSTAT_POS2_INT_Pos (8UL) /*!< POS2_INT (Bit 8) */ +#define QEI_INTSTAT_POS2_INT_Msk (0x100UL) /*!< POS2_INT (Bitfield-Mask: 0x01) */ +#define QEI_INTSTAT_REV0_INT_Pos (9UL) /*!< REV0_INT (Bit 9) */ +#define QEI_INTSTAT_REV0_INT_Msk (0x200UL) /*!< REV0_INT (Bitfield-Mask: 0x01) */ +#define QEI_INTSTAT_POS0REV_INT_Pos (10UL) /*!< POS0REV_INT (Bit 10) */ +#define QEI_INTSTAT_POS0REV_INT_Msk (0x400UL) /*!< POS0REV_INT (Bitfield-Mask: 0x01) */ +#define QEI_INTSTAT_POS1REV_INT_Pos (11UL) /*!< POS1REV_INT (Bit 11) */ +#define QEI_INTSTAT_POS1REV_INT_Msk (0x800UL) /*!< POS1REV_INT (Bitfield-Mask: 0x01) */ +#define QEI_INTSTAT_POS2REV_INT_Pos (12UL) /*!< POS2REV_INT (Bit 12) */ +#define QEI_INTSTAT_POS2REV_INT_Msk (0x1000UL) /*!< POS2REV_INT (Bitfield-Mask: 0x01) */ +#define QEI_INTSTAT_REV1_INT_Pos (13UL) /*!< REV1_INT (Bit 13) */ +#define QEI_INTSTAT_REV1_INT_Msk (0x2000UL) /*!< REV1_INT (Bitfield-Mask: 0x01) */ +#define QEI_INTSTAT_REV2_INT_Pos (14UL) /*!< REV2_INT (Bit 14) */ +#define QEI_INTSTAT_REV2_INT_Msk (0x4000UL) /*!< REV2_INT (Bitfield-Mask: 0x01) */ +#define QEI_INTSTAT_MAXPOS_INT_Pos (15UL) /*!< MAXPOS_INT (Bit 15) */ +#define QEI_INTSTAT_MAXPOS_INT_Msk (0x8000UL) /*!< MAXPOS_INT (Bitfield-Mask: 0x01) */ +/* ========================================================== SET ========================================================== */ +#define QEI_SET_INX_INT_Pos (0UL) /*!< INX_INT (Bit 0) */ +#define QEI_SET_INX_INT_Msk (0x1UL) /*!< INX_INT (Bitfield-Mask: 0x01) */ +#define QEI_SET_TIM_INT_Pos (1UL) /*!< TIM_INT (Bit 1) */ +#define QEI_SET_TIM_INT_Msk (0x2UL) /*!< TIM_INT (Bitfield-Mask: 0x01) */ +#define QEI_SET_VELC_INT_Pos (2UL) /*!< VELC_INT (Bit 2) */ +#define QEI_SET_VELC_INT_Msk (0x4UL) /*!< VELC_INT (Bitfield-Mask: 0x01) */ +#define QEI_SET_DIR_INT_Pos (3UL) /*!< DIR_INT (Bit 3) */ +#define QEI_SET_DIR_INT_Msk (0x8UL) /*!< DIR_INT (Bitfield-Mask: 0x01) */ +#define QEI_SET_ERR_INT_Pos (4UL) /*!< ERR_INT (Bit 4) */ +#define QEI_SET_ERR_INT_Msk (0x10UL) /*!< ERR_INT (Bitfield-Mask: 0x01) */ +#define QEI_SET_ENCLK_INT_Pos (5UL) /*!< ENCLK_INT (Bit 5) */ +#define QEI_SET_ENCLK_INT_Msk (0x20UL) /*!< ENCLK_INT (Bitfield-Mask: 0x01) */ +#define QEI_SET_POS0_INT_Pos (6UL) /*!< POS0_INT (Bit 6) */ +#define QEI_SET_POS0_INT_Msk (0x40UL) /*!< POS0_INT (Bitfield-Mask: 0x01) */ +#define QEI_SET_POS1_INT_Pos (7UL) /*!< POS1_INT (Bit 7) */ +#define QEI_SET_POS1_INT_Msk (0x80UL) /*!< POS1_INT (Bitfield-Mask: 0x01) */ +#define QEI_SET_POS2_INT_Pos (8UL) /*!< POS2_INT (Bit 8) */ +#define QEI_SET_POS2_INT_Msk (0x100UL) /*!< POS2_INT (Bitfield-Mask: 0x01) */ +#define QEI_SET_REV0_INT_Pos (9UL) /*!< REV0_INT (Bit 9) */ +#define QEI_SET_REV0_INT_Msk (0x200UL) /*!< REV0_INT (Bitfield-Mask: 0x01) */ +#define QEI_SET_POS0REV_INT_Pos (10UL) /*!< POS0REV_INT (Bit 10) */ +#define QEI_SET_POS0REV_INT_Msk (0x400UL) /*!< POS0REV_INT (Bitfield-Mask: 0x01) */ +#define QEI_SET_POS1REV_INT_Pos (11UL) /*!< POS1REV_INT (Bit 11) */ +#define QEI_SET_POS1REV_INT_Msk (0x800UL) /*!< POS1REV_INT (Bitfield-Mask: 0x01) */ +#define QEI_SET_POS2REV_INT_Pos (12UL) /*!< POS2REV_INT (Bit 12) */ +#define QEI_SET_POS2REV_INT_Msk (0x1000UL) /*!< POS2REV_INT (Bitfield-Mask: 0x01) */ +#define QEI_SET_REV1_INT_Pos (13UL) /*!< REV1_INT (Bit 13) */ +#define QEI_SET_REV1_INT_Msk (0x2000UL) /*!< REV1_INT (Bitfield-Mask: 0x01) */ +#define QEI_SET_REV2_INT_Pos (14UL) /*!< REV2_INT (Bit 14) */ +#define QEI_SET_REV2_INT_Msk (0x4000UL) /*!< REV2_INT (Bitfield-Mask: 0x01) */ +#define QEI_SET_MAXPOS_INT_Pos (15UL) /*!< MAXPOS_INT (Bit 15) */ +#define QEI_SET_MAXPOS_INT_Msk (0x8000UL) /*!< MAXPOS_INT (Bitfield-Mask: 0x01) */ +/* ========================================================== CLR ========================================================== */ +#define QEI_CLR_INX_INT_Pos (0UL) /*!< INX_INT (Bit 0) */ +#define QEI_CLR_INX_INT_Msk (0x1UL) /*!< INX_INT (Bitfield-Mask: 0x01) */ +#define QEI_CLR_TIM_INT_Pos (1UL) /*!< TIM_INT (Bit 1) */ +#define QEI_CLR_TIM_INT_Msk (0x2UL) /*!< TIM_INT (Bitfield-Mask: 0x01) */ +#define QEI_CLR_VELC_INT_Pos (2UL) /*!< VELC_INT (Bit 2) */ +#define QEI_CLR_VELC_INT_Msk (0x4UL) /*!< VELC_INT (Bitfield-Mask: 0x01) */ +#define QEI_CLR_DIR_INT_Pos (3UL) /*!< DIR_INT (Bit 3) */ +#define QEI_CLR_DIR_INT_Msk (0x8UL) /*!< DIR_INT (Bitfield-Mask: 0x01) */ +#define QEI_CLR_ERR_INT_Pos (4UL) /*!< ERR_INT (Bit 4) */ +#define QEI_CLR_ERR_INT_Msk (0x10UL) /*!< ERR_INT (Bitfield-Mask: 0x01) */ +#define QEI_CLR_ENCLK_INT_Pos (5UL) /*!< ENCLK_INT (Bit 5) */ +#define QEI_CLR_ENCLK_INT_Msk (0x20UL) /*!< ENCLK_INT (Bitfield-Mask: 0x01) */ +#define QEI_CLR_POS0_INT_Pos (6UL) /*!< POS0_INT (Bit 6) */ +#define QEI_CLR_POS0_INT_Msk (0x40UL) /*!< POS0_INT (Bitfield-Mask: 0x01) */ +#define QEI_CLR_POS1_INT_Pos (7UL) /*!< POS1_INT (Bit 7) */ +#define QEI_CLR_POS1_INT_Msk (0x80UL) /*!< POS1_INT (Bitfield-Mask: 0x01) */ +#define QEI_CLR_POS2_INT_Pos (8UL) /*!< POS2_INT (Bit 8) */ +#define QEI_CLR_POS2_INT_Msk (0x100UL) /*!< POS2_INT (Bitfield-Mask: 0x01) */ +#define QEI_CLR_REV0_INT_Pos (9UL) /*!< REV0_INT (Bit 9) */ +#define QEI_CLR_REV0_INT_Msk (0x200UL) /*!< REV0_INT (Bitfield-Mask: 0x01) */ +#define QEI_CLR_POS0REV_INT_Pos (10UL) /*!< POS0REV_INT (Bit 10) */ +#define QEI_CLR_POS0REV_INT_Msk (0x400UL) /*!< POS0REV_INT (Bitfield-Mask: 0x01) */ +#define QEI_CLR_POS1REV_INT_Pos (11UL) /*!< POS1REV_INT (Bit 11) */ +#define QEI_CLR_POS1REV_INT_Msk (0x800UL) /*!< POS1REV_INT (Bitfield-Mask: 0x01) */ +#define QEI_CLR_POS2REV_INT_Pos (12UL) /*!< POS2REV_INT (Bit 12) */ +#define QEI_CLR_POS2REV_INT_Msk (0x1000UL) /*!< POS2REV_INT (Bitfield-Mask: 0x01) */ +#define QEI_CLR_REV1_INT_Pos (13UL) /*!< REV1_INT (Bit 13) */ +#define QEI_CLR_REV1_INT_Msk (0x2000UL) /*!< REV1_INT (Bitfield-Mask: 0x01) */ +#define QEI_CLR_REV2_INT_Pos (14UL) /*!< REV2_INT (Bit 14) */ +#define QEI_CLR_REV2_INT_Msk (0x4000UL) /*!< REV2_INT (Bitfield-Mask: 0x01) */ +#define QEI_CLR_MAXPOS_INT_Pos (15UL) /*!< MAXPOS_INT (Bit 15) */ +#define QEI_CLR_MAXPOS_INT_Msk (0x8000UL) /*!< MAXPOS_INT (Bitfield-Mask: 0x01) */ +/* ========================================================== IE =========================================================== */ +#define QEI_IE_INX_INT_Pos (0UL) /*!< INX_INT (Bit 0) */ +#define QEI_IE_INX_INT_Msk (0x1UL) /*!< INX_INT (Bitfield-Mask: 0x01) */ +#define QEI_IE_TIM_INT_Pos (1UL) /*!< TIM_INT (Bit 1) */ +#define QEI_IE_TIM_INT_Msk (0x2UL) /*!< TIM_INT (Bitfield-Mask: 0x01) */ +#define QEI_IE_VELC_INT_Pos (2UL) /*!< VELC_INT (Bit 2) */ +#define QEI_IE_VELC_INT_Msk (0x4UL) /*!< VELC_INT (Bitfield-Mask: 0x01) */ +#define QEI_IE_DIR_INT_Pos (3UL) /*!< DIR_INT (Bit 3) */ +#define QEI_IE_DIR_INT_Msk (0x8UL) /*!< DIR_INT (Bitfield-Mask: 0x01) */ +#define QEI_IE_ERR_INT_Pos (4UL) /*!< ERR_INT (Bit 4) */ +#define QEI_IE_ERR_INT_Msk (0x10UL) /*!< ERR_INT (Bitfield-Mask: 0x01) */ +#define QEI_IE_ENCLK_INT_Pos (5UL) /*!< ENCLK_INT (Bit 5) */ +#define QEI_IE_ENCLK_INT_Msk (0x20UL) /*!< ENCLK_INT (Bitfield-Mask: 0x01) */ +#define QEI_IE_POS0_INT_Pos (6UL) /*!< POS0_INT (Bit 6) */ +#define QEI_IE_POS0_INT_Msk (0x40UL) /*!< POS0_INT (Bitfield-Mask: 0x01) */ +#define QEI_IE_POS1_INT_Pos (7UL) /*!< POS1_INT (Bit 7) */ +#define QEI_IE_POS1_INT_Msk (0x80UL) /*!< POS1_INT (Bitfield-Mask: 0x01) */ +#define QEI_IE_POS2_INT_Pos (8UL) /*!< POS2_INT (Bit 8) */ +#define QEI_IE_POS2_INT_Msk (0x100UL) /*!< POS2_INT (Bitfield-Mask: 0x01) */ +#define QEI_IE_REV0_INT_Pos (9UL) /*!< REV0_INT (Bit 9) */ +#define QEI_IE_REV0_INT_Msk (0x200UL) /*!< REV0_INT (Bitfield-Mask: 0x01) */ +#define QEI_IE_POS0REV_INT_Pos (10UL) /*!< POS0REV_INT (Bit 10) */ +#define QEI_IE_POS0REV_INT_Msk (0x400UL) /*!< POS0REV_INT (Bitfield-Mask: 0x01) */ +#define QEI_IE_POS1REV_INT_Pos (11UL) /*!< POS1REV_INT (Bit 11) */ +#define QEI_IE_POS1REV_INT_Msk (0x800UL) /*!< POS1REV_INT (Bitfield-Mask: 0x01) */ +#define QEI_IE_POS2REV_INT_Pos (12UL) /*!< POS2REV_INT (Bit 12) */ +#define QEI_IE_POS2REV_INT_Msk (0x1000UL) /*!< POS2REV_INT (Bitfield-Mask: 0x01) */ +#define QEI_IE_REV1_INT_Pos (13UL) /*!< REV1_INT (Bit 13) */ +#define QEI_IE_REV1_INT_Msk (0x2000UL) /*!< REV1_INT (Bitfield-Mask: 0x01) */ +#define QEI_IE_REV2_INT_Pos (14UL) /*!< REV2_INT (Bit 14) */ +#define QEI_IE_REV2_INT_Msk (0x4000UL) /*!< REV2_INT (Bitfield-Mask: 0x01) */ +#define QEI_IE_MAXPOS_INT_Pos (15UL) /*!< MAXPOS_INT (Bit 15) */ +#define QEI_IE_MAXPOS_INT_Msk (0x8000UL) /*!< MAXPOS_INT (Bitfield-Mask: 0x01) */ +/* ========================================================== IES ========================================================== */ +#define QEI_IES_INX_INT_Pos (0UL) /*!< INX_INT (Bit 0) */ +#define QEI_IES_INX_INT_Msk (0x1UL) /*!< INX_INT (Bitfield-Mask: 0x01) */ +#define QEI_IES_TIM_INT_Pos (1UL) /*!< TIM_INT (Bit 1) */ +#define QEI_IES_TIM_INT_Msk (0x2UL) /*!< TIM_INT (Bitfield-Mask: 0x01) */ +#define QEI_IES_VELC_INT_Pos (2UL) /*!< VELC_INT (Bit 2) */ +#define QEI_IES_VELC_INT_Msk (0x4UL) /*!< VELC_INT (Bitfield-Mask: 0x01) */ +#define QEI_IES_DIR_INT_Pos (3UL) /*!< DIR_INT (Bit 3) */ +#define QEI_IES_DIR_INT_Msk (0x8UL) /*!< DIR_INT (Bitfield-Mask: 0x01) */ +#define QEI_IES_ERR_INT_Pos (4UL) /*!< ERR_INT (Bit 4) */ +#define QEI_IES_ERR_INT_Msk (0x10UL) /*!< ERR_INT (Bitfield-Mask: 0x01) */ +#define QEI_IES_ENCLK_INT_Pos (5UL) /*!< ENCLK_INT (Bit 5) */ +#define QEI_IES_ENCLK_INT_Msk (0x20UL) /*!< ENCLK_INT (Bitfield-Mask: 0x01) */ +#define QEI_IES_POS0_INT_Pos (6UL) /*!< POS0_INT (Bit 6) */ +#define QEI_IES_POS0_INT_Msk (0x40UL) /*!< POS0_INT (Bitfield-Mask: 0x01) */ +#define QEI_IES_POS1_INT_Pos (7UL) /*!< POS1_INT (Bit 7) */ +#define QEI_IES_POS1_INT_Msk (0x80UL) /*!< POS1_INT (Bitfield-Mask: 0x01) */ +#define QEI_IES_POS2_INT_Pos (8UL) /*!< POS2_INT (Bit 8) */ +#define QEI_IES_POS2_INT_Msk (0x100UL) /*!< POS2_INT (Bitfield-Mask: 0x01) */ +#define QEI_IES_REV0_INT_Pos (9UL) /*!< REV0_INT (Bit 9) */ +#define QEI_IES_REV0_INT_Msk (0x200UL) /*!< REV0_INT (Bitfield-Mask: 0x01) */ +#define QEI_IES_POS0REV_INT_Pos (10UL) /*!< POS0REV_INT (Bit 10) */ +#define QEI_IES_POS0REV_INT_Msk (0x400UL) /*!< POS0REV_INT (Bitfield-Mask: 0x01) */ +#define QEI_IES_POS1REV_INT_Pos (11UL) /*!< POS1REV_INT (Bit 11) */ +#define QEI_IES_POS1REV_INT_Msk (0x800UL) /*!< POS1REV_INT (Bitfield-Mask: 0x01) */ +#define QEI_IES_POS2REV_INT_Pos (12UL) /*!< POS2REV_INT (Bit 12) */ +#define QEI_IES_POS2REV_INT_Msk (0x1000UL) /*!< POS2REV_INT (Bitfield-Mask: 0x01) */ +#define QEI_IES_REV1_INT_Pos (13UL) /*!< REV1_INT (Bit 13) */ +#define QEI_IES_REV1_INT_Msk (0x2000UL) /*!< REV1_INT (Bitfield-Mask: 0x01) */ +#define QEI_IES_REV2_INT_Pos (14UL) /*!< REV2_INT (Bit 14) */ +#define QEI_IES_REV2_INT_Msk (0x4000UL) /*!< REV2_INT (Bitfield-Mask: 0x01) */ +#define QEI_IES_MAXPOS_INT_Pos (15UL) /*!< MAXPOS_INT (Bit 15) */ +#define QEI_IES_MAXPOS_INT_Msk (0x8000UL) /*!< MAXPOS_INT (Bitfield-Mask: 0x01) */ +/* ========================================================== IEC ========================================================== */ +#define QEI_IEC_INX_INT_Pos (0UL) /*!< INX_INT (Bit 0) */ +#define QEI_IEC_INX_INT_Msk (0x1UL) /*!< INX_INT (Bitfield-Mask: 0x01) */ +#define QEI_IEC_TIM_INT_Pos (1UL) /*!< TIM_INT (Bit 1) */ +#define QEI_IEC_TIM_INT_Msk (0x2UL) /*!< TIM_INT (Bitfield-Mask: 0x01) */ +#define QEI_IEC_VELC_INT_Pos (2UL) /*!< VELC_INT (Bit 2) */ +#define QEI_IEC_VELC_INT_Msk (0x4UL) /*!< VELC_INT (Bitfield-Mask: 0x01) */ +#define QEI_IEC_DIR_INT_Pos (3UL) /*!< DIR_INT (Bit 3) */ +#define QEI_IEC_DIR_INT_Msk (0x8UL) /*!< DIR_INT (Bitfield-Mask: 0x01) */ +#define QEI_IEC_ERR_INT_Pos (4UL) /*!< ERR_INT (Bit 4) */ +#define QEI_IEC_ERR_INT_Msk (0x10UL) /*!< ERR_INT (Bitfield-Mask: 0x01) */ +#define QEI_IEC_ENCLK_INT_Pos (5UL) /*!< ENCLK_INT (Bit 5) */ +#define QEI_IEC_ENCLK_INT_Msk (0x20UL) /*!< ENCLK_INT (Bitfield-Mask: 0x01) */ +#define QEI_IEC_POS0_INT_Pos (6UL) /*!< POS0_INT (Bit 6) */ +#define QEI_IEC_POS0_INT_Msk (0x40UL) /*!< POS0_INT (Bitfield-Mask: 0x01) */ +#define QEI_IEC_POS1_INT_Pos (7UL) /*!< POS1_INT (Bit 7) */ +#define QEI_IEC_POS1_INT_Msk (0x80UL) /*!< POS1_INT (Bitfield-Mask: 0x01) */ +#define QEI_IEC_POS2_INT_Pos (8UL) /*!< POS2_INT (Bit 8) */ +#define QEI_IEC_POS2_INT_Msk (0x100UL) /*!< POS2_INT (Bitfield-Mask: 0x01) */ +#define QEI_IEC_REV0_INT_Pos (9UL) /*!< REV0_INT (Bit 9) */ +#define QEI_IEC_REV0_INT_Msk (0x200UL) /*!< REV0_INT (Bitfield-Mask: 0x01) */ +#define QEI_IEC_POS0REV_INT_Pos (10UL) /*!< POS0REV_INT (Bit 10) */ +#define QEI_IEC_POS0REV_INT_Msk (0x400UL) /*!< POS0REV_INT (Bitfield-Mask: 0x01) */ +#define QEI_IEC_POS1REV_INT_Pos (11UL) /*!< POS1REV_INT (Bit 11) */ +#define QEI_IEC_POS1REV_INT_Msk (0x800UL) /*!< POS1REV_INT (Bitfield-Mask: 0x01) */ +#define QEI_IEC_POS2REV_INT_Pos (12UL) /*!< POS2REV_INT (Bit 12) */ +#define QEI_IEC_POS2REV_INT_Msk (0x1000UL) /*!< POS2REV_INT (Bitfield-Mask: 0x01) */ +#define QEI_IEC_REV1_INT_Pos (13UL) /*!< REV1_INT (Bit 13) */ +#define QEI_IEC_REV1_INT_Msk (0x2000UL) /*!< REV1_INT (Bitfield-Mask: 0x01) */ +#define QEI_IEC_REV2_INT_Pos (14UL) /*!< REV2_INT (Bit 14) */ +#define QEI_IEC_REV2_INT_Msk (0x4000UL) /*!< REV2_INT (Bitfield-Mask: 0x01) */ +#define QEI_IEC_MAXPOS_INT_Pos (15UL) /*!< MAXPOS_INT (Bit 15) */ +#define QEI_IEC_MAXPOS_INT_Msk (0x8000UL) /*!< MAXPOS_INT (Bitfield-Mask: 0x01) */ + + +/* =========================================================================================================================== */ +/* ================ LPC_SYSCON ================ */ +/* =========================================================================================================================== */ + +/* ======================================================= FLASHCFG ======================================================== */ +#define SYSCON_FLASHCFG_FLASHTIM_Pos (12UL) /*!< FLASHTIM (Bit 12) */ +#define SYSCON_FLASHCFG_FLASHTIM_Msk (0xf000UL) /*!< FLASHTIM (Bitfield-Mask: 0x0f) */ +/* ======================================================== PLL0CON ======================================================== */ +#define SYSCON_PLL0CON_PLLE0_Pos (0UL) /*!< PLLE0 (Bit 0) */ +#define SYSCON_PLL0CON_PLLE0_Msk (0x1UL) /*!< PLLE0 (Bitfield-Mask: 0x01) */ +#define SYSCON_PLL0CON_PLLC0_Pos (1UL) /*!< PLLC0 (Bit 1) */ +#define SYSCON_PLL0CON_PLLC0_Msk (0x2UL) /*!< PLLC0 (Bitfield-Mask: 0x01) */ +/* ======================================================== PLL0CFG ======================================================== */ +#define SYSCON_PLL0CFG_MSEL0_Pos (0UL) /*!< MSEL0 (Bit 0) */ +#define SYSCON_PLL0CFG_MSEL0_Msk (0x7fffUL) /*!< MSEL0 (Bitfield-Mask: 0x7fff) */ +#define SYSCON_PLL0CFG_NSEL0_Pos (16UL) /*!< NSEL0 (Bit 16) */ +#define SYSCON_PLL0CFG_NSEL0_Msk (0xff0000UL) /*!< NSEL0 (Bitfield-Mask: 0xff) */ +/* ======================================================= PLL0STAT ======================================================== */ +#define SYSCON_PLL0STAT_MSEL0_Pos (0UL) /*!< MSEL0 (Bit 0) */ +#define SYSCON_PLL0STAT_MSEL0_Msk (0x7fffUL) /*!< MSEL0 (Bitfield-Mask: 0x7fff) */ +#define SYSCON_PLL0STAT_NSEL0_Pos (16UL) /*!< NSEL0 (Bit 16) */ +#define SYSCON_PLL0STAT_NSEL0_Msk (0xff0000UL) /*!< NSEL0 (Bitfield-Mask: 0xff) */ +#define SYSCON_PLL0STAT_PLLE0_STAT_Pos (24UL) /*!< PLLE0_STAT (Bit 24) */ +#define SYSCON_PLL0STAT_PLLE0_STAT_Msk (0x1000000UL) /*!< PLLE0_STAT (Bitfield-Mask: 0x01) */ +#define SYSCON_PLL0STAT_PLLC0_STAT_Pos (25UL) /*!< PLLC0_STAT (Bit 25) */ +#define SYSCON_PLL0STAT_PLLC0_STAT_Msk (0x2000000UL) /*!< PLLC0_STAT (Bitfield-Mask: 0x01) */ +#define SYSCON_PLL0STAT_PLOCK0_Pos (26UL) /*!< PLOCK0 (Bit 26) */ +#define SYSCON_PLL0STAT_PLOCK0_Msk (0x4000000UL) /*!< PLOCK0 (Bitfield-Mask: 0x01) */ +/* ======================================================= PLL0FEED ======================================================== */ +#define SYSCON_PLL0FEED_PLL0FEED_Pos (0UL) /*!< PLL0FEED (Bit 0) */ +#define SYSCON_PLL0FEED_PLL0FEED_Msk (0xffUL) /*!< PLL0FEED (Bitfield-Mask: 0xff) */ +/* ======================================================== PLL1CON ======================================================== */ +#define SYSCON_PLL1CON_PLLE1_Pos (0UL) /*!< PLLE1 (Bit 0) */ +#define SYSCON_PLL1CON_PLLE1_Msk (0x1UL) /*!< PLLE1 (Bitfield-Mask: 0x01) */ +#define SYSCON_PLL1CON_PLLC1_Pos (1UL) /*!< PLLC1 (Bit 1) */ +#define SYSCON_PLL1CON_PLLC1_Msk (0x2UL) /*!< PLLC1 (Bitfield-Mask: 0x01) */ +/* ======================================================== PLL1CFG ======================================================== */ +#define SYSCON_PLL1CFG_MSEL1_Pos (0UL) /*!< MSEL1 (Bit 0) */ +#define SYSCON_PLL1CFG_MSEL1_Msk (0x1fUL) /*!< MSEL1 (Bitfield-Mask: 0x1f) */ +#define SYSCON_PLL1CFG_PSEL1_Pos (5UL) /*!< PSEL1 (Bit 5) */ +#define SYSCON_PLL1CFG_PSEL1_Msk (0x60UL) /*!< PSEL1 (Bitfield-Mask: 0x03) */ +/* ======================================================= PLL1STAT ======================================================== */ +#define SYSCON_PLL1STAT_MSEL1_Pos (0UL) /*!< MSEL1 (Bit 0) */ +#define SYSCON_PLL1STAT_MSEL1_Msk (0x1fUL) /*!< MSEL1 (Bitfield-Mask: 0x1f) */ +#define SYSCON_PLL1STAT_PSEL1_Pos (5UL) /*!< PSEL1 (Bit 5) */ +#define SYSCON_PLL1STAT_PSEL1_Msk (0x60UL) /*!< PSEL1 (Bitfield-Mask: 0x03) */ +#define SYSCON_PLL1STAT_PLLE1_STAT_Pos (8UL) /*!< PLLE1_STAT (Bit 8) */ +#define SYSCON_PLL1STAT_PLLE1_STAT_Msk (0x100UL) /*!< PLLE1_STAT (Bitfield-Mask: 0x01) */ +#define SYSCON_PLL1STAT_PLLC1_STAT_Pos (9UL) /*!< PLLC1_STAT (Bit 9) */ +#define SYSCON_PLL1STAT_PLLC1_STAT_Msk (0x200UL) /*!< PLLC1_STAT (Bitfield-Mask: 0x01) */ +#define SYSCON_PLL1STAT_PLOCK1_Pos (10UL) /*!< PLOCK1 (Bit 10) */ +#define SYSCON_PLL1STAT_PLOCK1_Msk (0x400UL) /*!< PLOCK1 (Bitfield-Mask: 0x01) */ +/* ======================================================= PLL1FEED ======================================================== */ +#define SYSCON_PLL1FEED_PLL1FEED_Pos (0UL) /*!< PLL1FEED (Bit 0) */ +#define SYSCON_PLL1FEED_PLL1FEED_Msk (0xffUL) /*!< PLL1FEED (Bitfield-Mask: 0xff) */ +/* ========================================================= PCON ========================================================== */ +#define SYSCON_PCON_PM0_Pos (0UL) /*!< PM0 (Bit 0) */ +#define SYSCON_PCON_PM0_Msk (0x1UL) /*!< PM0 (Bitfield-Mask: 0x01) */ +#define SYSCON_PCON_PM1_Pos (1UL) /*!< PM1 (Bit 1) */ +#define SYSCON_PCON_PM1_Msk (0x2UL) /*!< PM1 (Bitfield-Mask: 0x01) */ +#define SYSCON_PCON_BODRPM_Pos (2UL) /*!< BODRPM (Bit 2) */ +#define SYSCON_PCON_BODRPM_Msk (0x4UL) /*!< BODRPM (Bitfield-Mask: 0x01) */ +#define SYSCON_PCON_BOGD_Pos (3UL) /*!< BOGD (Bit 3) */ +#define SYSCON_PCON_BOGD_Msk (0x8UL) /*!< BOGD (Bitfield-Mask: 0x01) */ +#define SYSCON_PCON_BORD_Pos (4UL) /*!< BORD (Bit 4) */ +#define SYSCON_PCON_BORD_Msk (0x10UL) /*!< BORD (Bitfield-Mask: 0x01) */ +#define SYSCON_PCON_SMFLAG_Pos (8UL) /*!< SMFLAG (Bit 8) */ +#define SYSCON_PCON_SMFLAG_Msk (0x100UL) /*!< SMFLAG (Bitfield-Mask: 0x01) */ +#define SYSCON_PCON_DSFLAG_Pos (9UL) /*!< DSFLAG (Bit 9) */ +#define SYSCON_PCON_DSFLAG_Msk (0x200UL) /*!< DSFLAG (Bitfield-Mask: 0x01) */ +#define SYSCON_PCON_PDFLAG_Pos (10UL) /*!< PDFLAG (Bit 10) */ +#define SYSCON_PCON_PDFLAG_Msk (0x400UL) /*!< PDFLAG (Bitfield-Mask: 0x01) */ +#define SYSCON_PCON_DPDFLAG_Pos (11UL) /*!< DPDFLAG (Bit 11) */ +#define SYSCON_PCON_DPDFLAG_Msk (0x800UL) /*!< DPDFLAG (Bitfield-Mask: 0x01) */ +/* ========================================================= PCONP ========================================================= */ +#define SYSCON_PCONP_PCTIM0_Pos (1UL) /*!< PCTIM0 (Bit 1) */ +#define SYSCON_PCONP_PCTIM0_Msk (0x2UL) /*!< PCTIM0 (Bitfield-Mask: 0x01) */ +#define SYSCON_PCONP_PCTIM1_Pos (2UL) /*!< PCTIM1 (Bit 2) */ +#define SYSCON_PCONP_PCTIM1_Msk (0x4UL) /*!< PCTIM1 (Bitfield-Mask: 0x01) */ +#define SYSCON_PCONP_PCUART0_Pos (3UL) /*!< PCUART0 (Bit 3) */ +#define SYSCON_PCONP_PCUART0_Msk (0x8UL) /*!< PCUART0 (Bitfield-Mask: 0x01) */ +#define SYSCON_PCONP_PCUART1_Pos (4UL) /*!< PCUART1 (Bit 4) */ +#define SYSCON_PCONP_PCUART1_Msk (0x10UL) /*!< PCUART1 (Bitfield-Mask: 0x01) */ +#define SYSCON_PCONP_PCPWM1_Pos (6UL) /*!< PCPWM1 (Bit 6) */ +#define SYSCON_PCONP_PCPWM1_Msk (0x40UL) /*!< PCPWM1 (Bitfield-Mask: 0x01) */ +#define SYSCON_PCONP_PCI2C0_Pos (7UL) /*!< PCI2C0 (Bit 7) */ +#define SYSCON_PCONP_PCI2C0_Msk (0x80UL) /*!< PCI2C0 (Bitfield-Mask: 0x01) */ +#define SYSCON_PCONP_PCSPI_Pos (8UL) /*!< PCSPI (Bit 8) */ +#define SYSCON_PCONP_PCSPI_Msk (0x100UL) /*!< PCSPI (Bitfield-Mask: 0x01) */ +#define SYSCON_PCONP_PCRTC_Pos (9UL) /*!< PCRTC (Bit 9) */ +#define SYSCON_PCONP_PCRTC_Msk (0x200UL) /*!< PCRTC (Bitfield-Mask: 0x01) */ +#define SYSCON_PCONP_PCSSP1_Pos (10UL) /*!< PCSSP1 (Bit 10) */ +#define SYSCON_PCONP_PCSSP1_Msk (0x400UL) /*!< PCSSP1 (Bitfield-Mask: 0x01) */ +#define SYSCON_PCONP_PCADC_Pos (12UL) /*!< PCADC (Bit 12) */ +#define SYSCON_PCONP_PCADC_Msk (0x1000UL) /*!< PCADC (Bitfield-Mask: 0x01) */ +#define SYSCON_PCONP_PCCAN1_Pos (13UL) /*!< PCCAN1 (Bit 13) */ +#define SYSCON_PCONP_PCCAN1_Msk (0x2000UL) /*!< PCCAN1 (Bitfield-Mask: 0x01) */ +#define SYSCON_PCONP_PCCAN2_Pos (14UL) /*!< PCCAN2 (Bit 14) */ +#define SYSCON_PCONP_PCCAN2_Msk (0x4000UL) /*!< PCCAN2 (Bitfield-Mask: 0x01) */ +#define SYSCON_PCONP_PCGPIO_Pos (15UL) /*!< PCGPIO (Bit 15) */ +#define SYSCON_PCONP_PCGPIO_Msk (0x8000UL) /*!< PCGPIO (Bitfield-Mask: 0x01) */ +#define SYSCON_PCONP_PCRIT_Pos (16UL) /*!< PCRIT (Bit 16) */ +#define SYSCON_PCONP_PCRIT_Msk (0x10000UL) /*!< PCRIT (Bitfield-Mask: 0x01) */ +#define SYSCON_PCONP_PCMCPWM_Pos (17UL) /*!< PCMCPWM (Bit 17) */ +#define SYSCON_PCONP_PCMCPWM_Msk (0x20000UL) /*!< PCMCPWM (Bitfield-Mask: 0x01) */ +#define SYSCON_PCONP_PCQEI_Pos (18UL) /*!< PCQEI (Bit 18) */ +#define SYSCON_PCONP_PCQEI_Msk (0x40000UL) /*!< PCQEI (Bitfield-Mask: 0x01) */ +#define SYSCON_PCONP_PCI2C1_Pos (19UL) /*!< PCI2C1 (Bit 19) */ +#define SYSCON_PCONP_PCI2C1_Msk (0x80000UL) /*!< PCI2C1 (Bitfield-Mask: 0x01) */ +#define SYSCON_PCONP_PCSSP0_Pos (21UL) /*!< PCSSP0 (Bit 21) */ +#define SYSCON_PCONP_PCSSP0_Msk (0x200000UL) /*!< PCSSP0 (Bitfield-Mask: 0x01) */ +#define SYSCON_PCONP_PCTIM2_Pos (22UL) /*!< PCTIM2 (Bit 22) */ +#define SYSCON_PCONP_PCTIM2_Msk (0x400000UL) /*!< PCTIM2 (Bitfield-Mask: 0x01) */ +#define SYSCON_PCONP_PCTIM3_Pos (23UL) /*!< PCTIM3 (Bit 23) */ +#define SYSCON_PCONP_PCTIM3_Msk (0x800000UL) /*!< PCTIM3 (Bitfield-Mask: 0x01) */ +#define SYSCON_PCONP_PCUART2_Pos (24UL) /*!< PCUART2 (Bit 24) */ +#define SYSCON_PCONP_PCUART2_Msk (0x1000000UL) /*!< PCUART2 (Bitfield-Mask: 0x01) */ +#define SYSCON_PCONP_PCUART3_Pos (25UL) /*!< PCUART3 (Bit 25) */ +#define SYSCON_PCONP_PCUART3_Msk (0x2000000UL) /*!< PCUART3 (Bitfield-Mask: 0x01) */ +#define SYSCON_PCONP_PCI2C2_Pos (26UL) /*!< PCI2C2 (Bit 26) */ +#define SYSCON_PCONP_PCI2C2_Msk (0x4000000UL) /*!< PCI2C2 (Bitfield-Mask: 0x01) */ +#define SYSCON_PCONP_PCI2S_Pos (27UL) /*!< PCI2S (Bit 27) */ +#define SYSCON_PCONP_PCI2S_Msk (0x8000000UL) /*!< PCI2S (Bitfield-Mask: 0x01) */ +#define SYSCON_PCONP_PCGPDMA_Pos (29UL) /*!< PCGPDMA (Bit 29) */ +#define SYSCON_PCONP_PCGPDMA_Msk (0x20000000UL) /*!< PCGPDMA (Bitfield-Mask: 0x01) */ +#define SYSCON_PCONP_PCENET_Pos (30UL) /*!< PCENET (Bit 30) */ +#define SYSCON_PCONP_PCENET_Msk (0x40000000UL) /*!< PCENET (Bitfield-Mask: 0x01) */ +#define SYSCON_PCONP_PCUSB_Pos (31UL) /*!< PCUSB (Bit 31) */ +#define SYSCON_PCONP_PCUSB_Msk (0x80000000UL) /*!< PCUSB (Bitfield-Mask: 0x01) */ +/* ======================================================== CCLKCFG ======================================================== */ +#define SYSCON_CCLKCFG_CCLKSEL_Pos (0UL) /*!< CCLKSEL (Bit 0) */ +#define SYSCON_CCLKCFG_CCLKSEL_Msk (0xffUL) /*!< CCLKSEL (Bitfield-Mask: 0xff) */ +/* ======================================================= USBCLKCFG ======================================================= */ +#define SYSCON_USBCLKCFG_USBSEL_Pos (0UL) /*!< USBSEL (Bit 0) */ +#define SYSCON_USBCLKCFG_USBSEL_Msk (0xfUL) /*!< USBSEL (Bitfield-Mask: 0x0f) */ +/* ======================================================= CLKSRCSEL ======================================================= */ +#define SYSCON_CLKSRCSEL_CLKSRC_Pos (0UL) /*!< CLKSRC (Bit 0) */ +#define SYSCON_CLKSRCSEL_CLKSRC_Msk (0x3UL) /*!< CLKSRC (Bitfield-Mask: 0x03) */ +/* ====================================================== CANSLEEPCLR ====================================================== */ +#define SYSCON_CANSLEEPCLR_CAN1SLEEP_Pos (1UL) /*!< CAN1SLEEP (Bit 1) */ +#define SYSCON_CANSLEEPCLR_CAN1SLEEP_Msk (0x2UL) /*!< CAN1SLEEP (Bitfield-Mask: 0x01) */ +#define SYSCON_CANSLEEPCLR_CAN2SLEEP_Pos (2UL) /*!< CAN2SLEEP (Bit 2) */ +#define SYSCON_CANSLEEPCLR_CAN2SLEEP_Msk (0x4UL) /*!< CAN2SLEEP (Bitfield-Mask: 0x01) */ +/* ===================================================== CANWAKEFLAGS ====================================================== */ +#define SYSCON_CANWAKEFLAGS_CAN1WAKE_Pos (1UL) /*!< CAN1WAKE (Bit 1) */ +#define SYSCON_CANWAKEFLAGS_CAN1WAKE_Msk (0x2UL) /*!< CAN1WAKE (Bitfield-Mask: 0x01) */ +#define SYSCON_CANWAKEFLAGS_CAN2WAKE_Pos (2UL) /*!< CAN2WAKE (Bit 2) */ +#define SYSCON_CANWAKEFLAGS_CAN2WAKE_Msk (0x4UL) /*!< CAN2WAKE (Bitfield-Mask: 0x01) */ +/* ======================================================== EXTINT ========================================================= */ +#define SYSCON_EXTINT_EINT0_Pos (0UL) /*!< EINT0 (Bit 0) */ +#define SYSCON_EXTINT_EINT0_Msk (0x1UL) /*!< EINT0 (Bitfield-Mask: 0x01) */ +#define SYSCON_EXTINT_EINT1_Pos (1UL) /*!< EINT1 (Bit 1) */ +#define SYSCON_EXTINT_EINT1_Msk (0x2UL) /*!< EINT1 (Bitfield-Mask: 0x01) */ +#define SYSCON_EXTINT_EINT2_Pos (2UL) /*!< EINT2 (Bit 2) */ +#define SYSCON_EXTINT_EINT2_Msk (0x4UL) /*!< EINT2 (Bitfield-Mask: 0x01) */ +#define SYSCON_EXTINT_EINT3_Pos (3UL) /*!< EINT3 (Bit 3) */ +#define SYSCON_EXTINT_EINT3_Msk (0x8UL) /*!< EINT3 (Bitfield-Mask: 0x01) */ +/* ======================================================== EXTMODE ======================================================== */ +#define SYSCON_EXTMODE_EXTMODE0_Pos (0UL) /*!< EXTMODE0 (Bit 0) */ +#define SYSCON_EXTMODE_EXTMODE0_Msk (0x1UL) /*!< EXTMODE0 (Bitfield-Mask: 0x01) */ +#define SYSCON_EXTMODE_EXTMODE1_Pos (1UL) /*!< EXTMODE1 (Bit 1) */ +#define SYSCON_EXTMODE_EXTMODE1_Msk (0x2UL) /*!< EXTMODE1 (Bitfield-Mask: 0x01) */ +#define SYSCON_EXTMODE_EXTMODE2_Pos (2UL) /*!< EXTMODE2 (Bit 2) */ +#define SYSCON_EXTMODE_EXTMODE2_Msk (0x4UL) /*!< EXTMODE2 (Bitfield-Mask: 0x01) */ +#define SYSCON_EXTMODE_EXTMODE3_Pos (3UL) /*!< EXTMODE3 (Bit 3) */ +#define SYSCON_EXTMODE_EXTMODE3_Msk (0x8UL) /*!< EXTMODE3 (Bitfield-Mask: 0x01) */ +/* ======================================================= EXTPOLAR ======================================================== */ +#define SYSCON_EXTPOLAR_EXTPOLAR0_Pos (0UL) /*!< EXTPOLAR0 (Bit 0) */ +#define SYSCON_EXTPOLAR_EXTPOLAR0_Msk (0x1UL) /*!< EXTPOLAR0 (Bitfield-Mask: 0x01) */ +#define SYSCON_EXTPOLAR_EXTPOLAR1_Pos (1UL) /*!< EXTPOLAR1 (Bit 1) */ +#define SYSCON_EXTPOLAR_EXTPOLAR1_Msk (0x2UL) /*!< EXTPOLAR1 (Bitfield-Mask: 0x01) */ +#define SYSCON_EXTPOLAR_EXTPOLAR2_Pos (2UL) /*!< EXTPOLAR2 (Bit 2) */ +#define SYSCON_EXTPOLAR_EXTPOLAR2_Msk (0x4UL) /*!< EXTPOLAR2 (Bitfield-Mask: 0x01) */ +#define SYSCON_EXTPOLAR_EXTPOLAR3_Pos (3UL) /*!< EXTPOLAR3 (Bit 3) */ +#define SYSCON_EXTPOLAR_EXTPOLAR3_Msk (0x8UL) /*!< EXTPOLAR3 (Bitfield-Mask: 0x01) */ +/* ========================================================= RSID ========================================================== */ +#define SYSCON_RSID_POR_Pos (0UL) /*!< POR (Bit 0) */ +#define SYSCON_RSID_POR_Msk (0x1UL) /*!< POR (Bitfield-Mask: 0x01) */ +#define SYSCON_RSID_EXTR_Pos (1UL) /*!< EXTR (Bit 1) */ +#define SYSCON_RSID_EXTR_Msk (0x2UL) /*!< EXTR (Bitfield-Mask: 0x01) */ +#define SYSCON_RSID_WDTR_Pos (2UL) /*!< WDTR (Bit 2) */ +#define SYSCON_RSID_WDTR_Msk (0x4UL) /*!< WDTR (Bitfield-Mask: 0x01) */ +#define SYSCON_RSID_BODR_Pos (3UL) /*!< BODR (Bit 3) */ +#define SYSCON_RSID_BODR_Msk (0x8UL) /*!< BODR (Bitfield-Mask: 0x01) */ +/* ========================================================== SCS ========================================================== */ +#define SYSCON_SCS_OSCRANGE_Pos (4UL) /*!< OSCRANGE (Bit 4) */ +#define SYSCON_SCS_OSCRANGE_Msk (0x10UL) /*!< OSCRANGE (Bitfield-Mask: 0x01) */ +#define SYSCON_SCS_OSCEN_Pos (5UL) /*!< OSCEN (Bit 5) */ +#define SYSCON_SCS_OSCEN_Msk (0x20UL) /*!< OSCEN (Bitfield-Mask: 0x01) */ +#define SYSCON_SCS_OSCSTAT_Pos (6UL) /*!< OSCSTAT (Bit 6) */ +#define SYSCON_SCS_OSCSTAT_Msk (0x40UL) /*!< OSCSTAT (Bitfield-Mask: 0x01) */ +/* ======================================================= PCLKSEL0 ======================================================== */ +#define SYSCON_PCLKSEL0_PCLK_WDT_Pos (0UL) /*!< PCLK_WDT (Bit 0) */ +#define SYSCON_PCLKSEL0_PCLK_WDT_Msk (0x3UL) /*!< PCLK_WDT (Bitfield-Mask: 0x03) */ +#define SYSCON_PCLKSEL0_PCLK_TIMER0_Pos (2UL) /*!< PCLK_TIMER0 (Bit 2) */ +#define SYSCON_PCLKSEL0_PCLK_TIMER0_Msk (0xcUL) /*!< PCLK_TIMER0 (Bitfield-Mask: 0x03) */ +#define SYSCON_PCLKSEL0_PCLK_TIMER1_Pos (4UL) /*!< PCLK_TIMER1 (Bit 4) */ +#define SYSCON_PCLKSEL0_PCLK_TIMER1_Msk (0x30UL) /*!< PCLK_TIMER1 (Bitfield-Mask: 0x03) */ +#define SYSCON_PCLKSEL0_PCLK_UART0_Pos (6UL) /*!< PCLK_UART0 (Bit 6) */ +#define SYSCON_PCLKSEL0_PCLK_UART0_Msk (0xc0UL) /*!< PCLK_UART0 (Bitfield-Mask: 0x03) */ +#define SYSCON_PCLKSEL0_PCLK_UART1_Pos (8UL) /*!< PCLK_UART1 (Bit 8) */ +#define SYSCON_PCLKSEL0_PCLK_UART1_Msk (0x300UL) /*!< PCLK_UART1 (Bitfield-Mask: 0x03) */ +#define SYSCON_PCLKSEL0_PCLK_PWM1_Pos (12UL) /*!< PCLK_PWM1 (Bit 12) */ +#define SYSCON_PCLKSEL0_PCLK_PWM1_Msk (0x3000UL) /*!< PCLK_PWM1 (Bitfield-Mask: 0x03) */ +#define SYSCON_PCLKSEL0_PCLK_I2C0_Pos (14UL) /*!< PCLK_I2C0 (Bit 14) */ +#define SYSCON_PCLKSEL0_PCLK_I2C0_Msk (0xc000UL) /*!< PCLK_I2C0 (Bitfield-Mask: 0x03) */ +#define SYSCON_PCLKSEL0_PCLK_SPI_Pos (16UL) /*!< PCLK_SPI (Bit 16) */ +#define SYSCON_PCLKSEL0_PCLK_SPI_Msk (0x30000UL) /*!< PCLK_SPI (Bitfield-Mask: 0x03) */ +#define SYSCON_PCLKSEL0_PCLK_SSP1_Pos (20UL) /*!< PCLK_SSP1 (Bit 20) */ +#define SYSCON_PCLKSEL0_PCLK_SSP1_Msk (0x300000UL) /*!< PCLK_SSP1 (Bitfield-Mask: 0x03) */ +#define SYSCON_PCLKSEL0_PCLK_DAC_Pos (22UL) /*!< PCLK_DAC (Bit 22) */ +#define SYSCON_PCLKSEL0_PCLK_DAC_Msk (0xc00000UL) /*!< PCLK_DAC (Bitfield-Mask: 0x03) */ +#define SYSCON_PCLKSEL0_PCLK_ADC_Pos (24UL) /*!< PCLK_ADC (Bit 24) */ +#define SYSCON_PCLKSEL0_PCLK_ADC_Msk (0x3000000UL) /*!< PCLK_ADC (Bitfield-Mask: 0x03) */ +#define SYSCON_PCLKSEL0_PCLK_CAN1_Pos (26UL) /*!< PCLK_CAN1 (Bit 26) */ +#define SYSCON_PCLKSEL0_PCLK_CAN1_Msk (0xc000000UL) /*!< PCLK_CAN1 (Bitfield-Mask: 0x03) */ +#define SYSCON_PCLKSEL0_PCLK_CAN2_Pos (28UL) /*!< PCLK_CAN2 (Bit 28) */ +#define SYSCON_PCLKSEL0_PCLK_CAN2_Msk (0x30000000UL) /*!< PCLK_CAN2 (Bitfield-Mask: 0x03) */ +#define SYSCON_PCLKSEL0_PCLK_ACF_Pos (30UL) /*!< PCLK_ACF (Bit 30) */ +#define SYSCON_PCLKSEL0_PCLK_ACF_Msk (0xc0000000UL) /*!< PCLK_ACF (Bitfield-Mask: 0x03) */ +/* ======================================================= PCLKSEL1 ======================================================== */ +#define SYSCON_PCLKSEL1_PCLK_QEI_Pos (0UL) /*!< PCLK_QEI (Bit 0) */ +#define SYSCON_PCLKSEL1_PCLK_QEI_Msk (0x3UL) /*!< PCLK_QEI (Bitfield-Mask: 0x03) */ +#define SYSCON_PCLKSEL1_PCLK_GPIOINT_Pos (2UL) /*!< PCLK_GPIOINT (Bit 2) */ +#define SYSCON_PCLKSEL1_PCLK_GPIOINT_Msk (0xcUL) /*!< PCLK_GPIOINT (Bitfield-Mask: 0x03) */ +#define SYSCON_PCLKSEL1_PCLK_PCB_Pos (4UL) /*!< PCLK_PCB (Bit 4) */ +#define SYSCON_PCLKSEL1_PCLK_PCB_Msk (0x30UL) /*!< PCLK_PCB (Bitfield-Mask: 0x03) */ +#define SYSCON_PCLKSEL1_PCLK_I2C1_Pos (6UL) /*!< PCLK_I2C1 (Bit 6) */ +#define SYSCON_PCLKSEL1_PCLK_I2C1_Msk (0xc0UL) /*!< PCLK_I2C1 (Bitfield-Mask: 0x03) */ +#define SYSCON_PCLKSEL1_PCLK_SSP0_Pos (10UL) /*!< PCLK_SSP0 (Bit 10) */ +#define SYSCON_PCLKSEL1_PCLK_SSP0_Msk (0xc00UL) /*!< PCLK_SSP0 (Bitfield-Mask: 0x03) */ +#define SYSCON_PCLKSEL1_PCLK_TIMER2_Pos (12UL) /*!< PCLK_TIMER2 (Bit 12) */ +#define SYSCON_PCLKSEL1_PCLK_TIMER2_Msk (0x3000UL) /*!< PCLK_TIMER2 (Bitfield-Mask: 0x03) */ +#define SYSCON_PCLKSEL1_PCLK_TIMER3_Pos (14UL) /*!< PCLK_TIMER3 (Bit 14) */ +#define SYSCON_PCLKSEL1_PCLK_TIMER3_Msk (0xc000UL) /*!< PCLK_TIMER3 (Bitfield-Mask: 0x03) */ +#define SYSCON_PCLKSEL1_PCLK_UART2_Pos (16UL) /*!< PCLK_UART2 (Bit 16) */ +#define SYSCON_PCLKSEL1_PCLK_UART2_Msk (0x30000UL) /*!< PCLK_UART2 (Bitfield-Mask: 0x03) */ +#define SYSCON_PCLKSEL1_PCLK_UART3_Pos (18UL) /*!< PCLK_UART3 (Bit 18) */ +#define SYSCON_PCLKSEL1_PCLK_UART3_Msk (0xc0000UL) /*!< PCLK_UART3 (Bitfield-Mask: 0x03) */ +#define SYSCON_PCLKSEL1_PCLK_I2C2_Pos (20UL) /*!< PCLK_I2C2 (Bit 20) */ +#define SYSCON_PCLKSEL1_PCLK_I2C2_Msk (0x300000UL) /*!< PCLK_I2C2 (Bitfield-Mask: 0x03) */ +#define SYSCON_PCLKSEL1_PCLK_I2S_Pos (22UL) /*!< PCLK_I2S (Bit 22) */ +#define SYSCON_PCLKSEL1_PCLK_I2S_Msk (0xc00000UL) /*!< PCLK_I2S (Bitfield-Mask: 0x03) */ +#define SYSCON_PCLKSEL1_PCLK_RIT_Pos (26UL) /*!< PCLK_RIT (Bit 26) */ +#define SYSCON_PCLKSEL1_PCLK_RIT_Msk (0xc000000UL) /*!< PCLK_RIT (Bitfield-Mask: 0x03) */ +#define SYSCON_PCLKSEL1_PCLK_SYSCON_Pos (28UL) /*!< PCLK_SYSCON (Bit 28) */ +#define SYSCON_PCLKSEL1_PCLK_SYSCON_Msk (0x30000000UL) /*!< PCLK_SYSCON (Bitfield-Mask: 0x03) */ +#define SYSCON_PCLKSEL1_PCLK_MC_Pos (30UL) /*!< PCLK_MC (Bit 30) */ +#define SYSCON_PCLKSEL1_PCLK_MC_Msk (0xc0000000UL) /*!< PCLK_MC (Bitfield-Mask: 0x03) */ +/* ======================================================= USBINTST ======================================================== */ +#define SYSCON_USBINTST_USB_INT_REQ_LP_Pos (0UL) /*!< USB_INT_REQ_LP (Bit 0) */ +#define SYSCON_USBINTST_USB_INT_REQ_LP_Msk (0x1UL) /*!< USB_INT_REQ_LP (Bitfield-Mask: 0x01) */ +#define SYSCON_USBINTST_USB_INT_REQ_HP_Pos (1UL) /*!< USB_INT_REQ_HP (Bit 1) */ +#define SYSCON_USBINTST_USB_INT_REQ_HP_Msk (0x2UL) /*!< USB_INT_REQ_HP (Bitfield-Mask: 0x01) */ +#define SYSCON_USBINTST_USB_INT_REQ_DMA_Pos (2UL) /*!< USB_INT_REQ_DMA (Bit 2) */ +#define SYSCON_USBINTST_USB_INT_REQ_DMA_Msk (0x4UL) /*!< USB_INT_REQ_DMA (Bitfield-Mask: 0x01) */ +#define SYSCON_USBINTST_USB_HOST_INT_Pos (3UL) /*!< USB_HOST_INT (Bit 3) */ +#define SYSCON_USBINTST_USB_HOST_INT_Msk (0x8UL) /*!< USB_HOST_INT (Bitfield-Mask: 0x01) */ +#define SYSCON_USBINTST_USB_ATX_INT_Pos (4UL) /*!< USB_ATX_INT (Bit 4) */ +#define SYSCON_USBINTST_USB_ATX_INT_Msk (0x10UL) /*!< USB_ATX_INT (Bitfield-Mask: 0x01) */ +#define SYSCON_USBINTST_USB_OTG_INT_Pos (5UL) /*!< USB_OTG_INT (Bit 5) */ +#define SYSCON_USBINTST_USB_OTG_INT_Msk (0x20UL) /*!< USB_OTG_INT (Bitfield-Mask: 0x01) */ +#define SYSCON_USBINTST_USB_I2C_INT_Pos (6UL) /*!< USB_I2C_INT (Bit 6) */ +#define SYSCON_USBINTST_USB_I2C_INT_Msk (0x40UL) /*!< USB_I2C_INT (Bitfield-Mask: 0x01) */ +#define SYSCON_USBINTST_USB_NEED_CLK_Pos (8UL) /*!< USB_NEED_CLK (Bit 8) */ +#define SYSCON_USBINTST_USB_NEED_CLK_Msk (0x100UL) /*!< USB_NEED_CLK (Bitfield-Mask: 0x01) */ +#define SYSCON_USBINTST_EN_USB_INTS_Pos (31UL) /*!< EN_USB_INTS (Bit 31) */ +#define SYSCON_USBINTST_EN_USB_INTS_Msk (0x80000000UL) /*!< EN_USB_INTS (Bitfield-Mask: 0x01) */ +/* ====================================================== DMACREQSEL ======================================================= */ +#define SYSCON_DMACREQSEL_DMASEL08_Pos (0UL) /*!< DMASEL08 (Bit 0) */ +#define SYSCON_DMACREQSEL_DMASEL08_Msk (0x1UL) /*!< DMASEL08 (Bitfield-Mask: 0x01) */ +#define SYSCON_DMACREQSEL_DMASEL09_Pos (1UL) /*!< DMASEL09 (Bit 1) */ +#define SYSCON_DMACREQSEL_DMASEL09_Msk (0x2UL) /*!< DMASEL09 (Bitfield-Mask: 0x01) */ +#define SYSCON_DMACREQSEL_DMASEL10_Pos (2UL) /*!< DMASEL10 (Bit 2) */ +#define SYSCON_DMACREQSEL_DMASEL10_Msk (0x4UL) /*!< DMASEL10 (Bitfield-Mask: 0x01) */ +#define SYSCON_DMACREQSEL_DMASEL11_Pos (3UL) /*!< DMASEL11 (Bit 3) */ +#define SYSCON_DMACREQSEL_DMASEL11_Msk (0x8UL) /*!< DMASEL11 (Bitfield-Mask: 0x01) */ +#define SYSCON_DMACREQSEL_DMASEL12_Pos (4UL) /*!< DMASEL12 (Bit 4) */ +#define SYSCON_DMACREQSEL_DMASEL12_Msk (0x10UL) /*!< DMASEL12 (Bitfield-Mask: 0x01) */ +#define SYSCON_DMACREQSEL_DMASEL13_Pos (5UL) /*!< DMASEL13 (Bit 5) */ +#define SYSCON_DMACREQSEL_DMASEL13_Msk (0x20UL) /*!< DMASEL13 (Bitfield-Mask: 0x01) */ +#define SYSCON_DMACREQSEL_DMASEL14_Pos (6UL) /*!< DMASEL14 (Bit 6) */ +#define SYSCON_DMACREQSEL_DMASEL14_Msk (0x40UL) /*!< DMASEL14 (Bitfield-Mask: 0x01) */ +#define SYSCON_DMACREQSEL_DMASEL15_Pos (7UL) /*!< DMASEL15 (Bit 7) */ +#define SYSCON_DMACREQSEL_DMASEL15_Msk (0x80UL) /*!< DMASEL15 (Bitfield-Mask: 0x01) */ +/* ======================================================= CLKOUTCFG ======================================================= */ +#define SYSCON_CLKOUTCFG_CLKOUTSEL_Pos (0UL) /*!< CLKOUTSEL (Bit 0) */ +#define SYSCON_CLKOUTCFG_CLKOUTSEL_Msk (0xfUL) /*!< CLKOUTSEL (Bitfield-Mask: 0x0f) */ +#define SYSCON_CLKOUTCFG_CLKOUTDIV_Pos (4UL) /*!< CLKOUTDIV (Bit 4) */ +#define SYSCON_CLKOUTCFG_CLKOUTDIV_Msk (0xf0UL) /*!< CLKOUTDIV (Bitfield-Mask: 0x0f) */ +#define SYSCON_CLKOUTCFG_CLKOUT_EN_Pos (8UL) /*!< CLKOUT_EN (Bit 8) */ +#define SYSCON_CLKOUTCFG_CLKOUT_EN_Msk (0x100UL) /*!< CLKOUT_EN (Bitfield-Mask: 0x01) */ +#define SYSCON_CLKOUTCFG_CLKOUT_ACT_Pos (9UL) /*!< CLKOUT_ACT (Bit 9) */ +#define SYSCON_CLKOUTCFG_CLKOUT_ACT_Msk (0x200UL) /*!< CLKOUT_ACT (Bitfield-Mask: 0x01) */ + + +/* =========================================================================================================================== */ +/* ================ LPC_EMAC ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= MAC1 ========================================================== */ +#define EMAC_MAC1_RXENABLE_Pos (0UL) /*!< RXENABLE (Bit 0) */ +#define EMAC_MAC1_RXENABLE_Msk (0x1UL) /*!< RXENABLE (Bitfield-Mask: 0x01) */ +#define EMAC_MAC1_PARF_Pos (1UL) /*!< PARF (Bit 1) */ +#define EMAC_MAC1_PARF_Msk (0x2UL) /*!< PARF (Bitfield-Mask: 0x01) */ +#define EMAC_MAC1_RXFLOWCTRL_Pos (2UL) /*!< RXFLOWCTRL (Bit 2) */ +#define EMAC_MAC1_RXFLOWCTRL_Msk (0x4UL) /*!< RXFLOWCTRL (Bitfield-Mask: 0x01) */ +#define EMAC_MAC1_TXFLOWCTRL_Pos (3UL) /*!< TXFLOWCTRL (Bit 3) */ +#define EMAC_MAC1_TXFLOWCTRL_Msk (0x8UL) /*!< TXFLOWCTRL (Bitfield-Mask: 0x01) */ +#define EMAC_MAC1_LOOPBACK_Pos (4UL) /*!< LOOPBACK (Bit 4) */ +#define EMAC_MAC1_LOOPBACK_Msk (0x10UL) /*!< LOOPBACK (Bitfield-Mask: 0x01) */ +#define EMAC_MAC1_RESETTX_Pos (8UL) /*!< RESETTX (Bit 8) */ +#define EMAC_MAC1_RESETTX_Msk (0x100UL) /*!< RESETTX (Bitfield-Mask: 0x01) */ +#define EMAC_MAC1_RESETMCSTX_Pos (9UL) /*!< RESETMCSTX (Bit 9) */ +#define EMAC_MAC1_RESETMCSTX_Msk (0x200UL) /*!< RESETMCSTX (Bitfield-Mask: 0x01) */ +#define EMAC_MAC1_RESETRX_Pos (10UL) /*!< RESETRX (Bit 10) */ +#define EMAC_MAC1_RESETRX_Msk (0x400UL) /*!< RESETRX (Bitfield-Mask: 0x01) */ +#define EMAC_MAC1_RESETMCSRX_Pos (11UL) /*!< RESETMCSRX (Bit 11) */ +#define EMAC_MAC1_RESETMCSRX_Msk (0x800UL) /*!< RESETMCSRX (Bitfield-Mask: 0x01) */ +#define EMAC_MAC1_SIMRESET_Pos (14UL) /*!< SIMRESET (Bit 14) */ +#define EMAC_MAC1_SIMRESET_Msk (0x4000UL) /*!< SIMRESET (Bitfield-Mask: 0x01) */ +#define EMAC_MAC1_SOFTRESET_Pos (15UL) /*!< SOFTRESET (Bit 15) */ +#define EMAC_MAC1_SOFTRESET_Msk (0x8000UL) /*!< SOFTRESET (Bitfield-Mask: 0x01) */ +/* ========================================================= MAC2 ========================================================== */ +#define EMAC_MAC2_FULLDUPLEX_Pos (0UL) /*!< FULLDUPLEX (Bit 0) */ +#define EMAC_MAC2_FULLDUPLEX_Msk (0x1UL) /*!< FULLDUPLEX (Bitfield-Mask: 0x01) */ +#define EMAC_MAC2_FLC_Pos (1UL) /*!< FLC (Bit 1) */ +#define EMAC_MAC2_FLC_Msk (0x2UL) /*!< FLC (Bitfield-Mask: 0x01) */ +#define EMAC_MAC2_HFEN_Pos (2UL) /*!< HFEN (Bit 2) */ +#define EMAC_MAC2_HFEN_Msk (0x4UL) /*!< HFEN (Bitfield-Mask: 0x01) */ +#define EMAC_MAC2_DELAYEDCRC_Pos (3UL) /*!< DELAYEDCRC (Bit 3) */ +#define EMAC_MAC2_DELAYEDCRC_Msk (0x8UL) /*!< DELAYEDCRC (Bitfield-Mask: 0x01) */ +#define EMAC_MAC2_CRCEN_Pos (4UL) /*!< CRCEN (Bit 4) */ +#define EMAC_MAC2_CRCEN_Msk (0x10UL) /*!< CRCEN (Bitfield-Mask: 0x01) */ +#define EMAC_MAC2_PADCRCEN_Pos (5UL) /*!< PADCRCEN (Bit 5) */ +#define EMAC_MAC2_PADCRCEN_Msk (0x20UL) /*!< PADCRCEN (Bitfield-Mask: 0x01) */ +#define EMAC_MAC2_VLANPADEN_Pos (6UL) /*!< VLANPADEN (Bit 6) */ +#define EMAC_MAC2_VLANPADEN_Msk (0x40UL) /*!< VLANPADEN (Bitfield-Mask: 0x01) */ +#define EMAC_MAC2_AUTODETPADEN_Pos (7UL) /*!< AUTODETPADEN (Bit 7) */ +#define EMAC_MAC2_AUTODETPADEN_Msk (0x80UL) /*!< AUTODETPADEN (Bitfield-Mask: 0x01) */ +#define EMAC_MAC2_PPENF_Pos (8UL) /*!< PPENF (Bit 8) */ +#define EMAC_MAC2_PPENF_Msk (0x100UL) /*!< PPENF (Bitfield-Mask: 0x01) */ +#define EMAC_MAC2_LPENF_Pos (9UL) /*!< LPENF (Bit 9) */ +#define EMAC_MAC2_LPENF_Msk (0x200UL) /*!< LPENF (Bitfield-Mask: 0x01) */ +#define EMAC_MAC2_NOBACKOFF_Pos (12UL) /*!< NOBACKOFF (Bit 12) */ +#define EMAC_MAC2_NOBACKOFF_Msk (0x1000UL) /*!< NOBACKOFF (Bitfield-Mask: 0x01) */ +#define EMAC_MAC2_BP_NOBACKOFF_Pos (13UL) /*!< BP_NOBACKOFF (Bit 13) */ +#define EMAC_MAC2_BP_NOBACKOFF_Msk (0x2000UL) /*!< BP_NOBACKOFF (Bitfield-Mask: 0x01) */ +#define EMAC_MAC2_EXCESSDEFER_Pos (14UL) /*!< EXCESSDEFER (Bit 14) */ +#define EMAC_MAC2_EXCESSDEFER_Msk (0x4000UL) /*!< EXCESSDEFER (Bitfield-Mask: 0x01) */ +/* ========================================================= IPGT ========================================================== */ +#define EMAC_IPGT_BTOBINTEGAP_Pos (0UL) /*!< BTOBINTEGAP (Bit 0) */ +#define EMAC_IPGT_BTOBINTEGAP_Msk (0x7fUL) /*!< BTOBINTEGAP (Bitfield-Mask: 0x7f) */ +/* ========================================================= IPGR ========================================================== */ +#define EMAC_IPGR_NBTOBINTEGAP2_Pos (0UL) /*!< NBTOBINTEGAP2 (Bit 0) */ +#define EMAC_IPGR_NBTOBINTEGAP2_Msk (0x7fUL) /*!< NBTOBINTEGAP2 (Bitfield-Mask: 0x7f) */ +#define EMAC_IPGR_NBTOBINTEGAP1_Pos (8UL) /*!< NBTOBINTEGAP1 (Bit 8) */ +#define EMAC_IPGR_NBTOBINTEGAP1_Msk (0x7f00UL) /*!< NBTOBINTEGAP1 (Bitfield-Mask: 0x7f) */ +/* ========================================================= CLRT ========================================================== */ +#define EMAC_CLRT_RETRANSMAX_Pos (0UL) /*!< RETRANSMAX (Bit 0) */ +#define EMAC_CLRT_RETRANSMAX_Msk (0xfUL) /*!< RETRANSMAX (Bitfield-Mask: 0x0f) */ +#define EMAC_CLRT_COLLWIN_Pos (8UL) /*!< COLLWIN (Bit 8) */ +#define EMAC_CLRT_COLLWIN_Msk (0x3f00UL) /*!< COLLWIN (Bitfield-Mask: 0x3f) */ +/* ========================================================= MAXF ========================================================== */ +#define EMAC_MAXF_MAXFLEN_Pos (0UL) /*!< MAXFLEN (Bit 0) */ +#define EMAC_MAXF_MAXFLEN_Msk (0xffffUL) /*!< MAXFLEN (Bitfield-Mask: 0xffff) */ +/* ========================================================= SUPP ========================================================== */ +#define EMAC_SUPP_SPEED_Pos (8UL) /*!< SPEED (Bit 8) */ +#define EMAC_SUPP_SPEED_Msk (0x100UL) /*!< SPEED (Bitfield-Mask: 0x01) */ +/* ========================================================= TEST ========================================================== */ +#define EMAC_TEST_SCPQ_Pos (0UL) /*!< SCPQ (Bit 0) */ +#define EMAC_TEST_SCPQ_Msk (0x1UL) /*!< SCPQ (Bitfield-Mask: 0x01) */ +#define EMAC_TEST_TESTPAUSE_Pos (1UL) /*!< TESTPAUSE (Bit 1) */ +#define EMAC_TEST_TESTPAUSE_Msk (0x2UL) /*!< TESTPAUSE (Bitfield-Mask: 0x01) */ +#define EMAC_TEST_TESTBP_Pos (2UL) /*!< TESTBP (Bit 2) */ +#define EMAC_TEST_TESTBP_Msk (0x4UL) /*!< TESTBP (Bitfield-Mask: 0x01) */ +/* ========================================================= MCFG ========================================================== */ +#define EMAC_MCFG_SCANINC_Pos (0UL) /*!< SCANINC (Bit 0) */ +#define EMAC_MCFG_SCANINC_Msk (0x1UL) /*!< SCANINC (Bitfield-Mask: 0x01) */ +#define EMAC_MCFG_SUPPPREAMBLE_Pos (1UL) /*!< SUPPPREAMBLE (Bit 1) */ +#define EMAC_MCFG_SUPPPREAMBLE_Msk (0x2UL) /*!< SUPPPREAMBLE (Bitfield-Mask: 0x01) */ +#define EMAC_MCFG_CLOCKSEL_Pos (2UL) /*!< CLOCKSEL (Bit 2) */ +#define EMAC_MCFG_CLOCKSEL_Msk (0x3cUL) /*!< CLOCKSEL (Bitfield-Mask: 0x0f) */ +#define EMAC_MCFG_RESETMIIMGMT_Pos (15UL) /*!< RESETMIIMGMT (Bit 15) */ +#define EMAC_MCFG_RESETMIIMGMT_Msk (0x8000UL) /*!< RESETMIIMGMT (Bitfield-Mask: 0x01) */ +/* ========================================================= MCMD ========================================================== */ +#define EMAC_MCMD_READ_Pos (0UL) /*!< READ (Bit 0) */ +#define EMAC_MCMD_READ_Msk (0x1UL) /*!< READ (Bitfield-Mask: 0x01) */ +#define EMAC_MCMD_SCAN_Pos (1UL) /*!< SCAN (Bit 1) */ +#define EMAC_MCMD_SCAN_Msk (0x2UL) /*!< SCAN (Bitfield-Mask: 0x01) */ +/* ========================================================= MADR ========================================================== */ +#define EMAC_MADR_REGADDR_Pos (0UL) /*!< REGADDR (Bit 0) */ +#define EMAC_MADR_REGADDR_Msk (0x1fUL) /*!< REGADDR (Bitfield-Mask: 0x1f) */ +#define EMAC_MADR_PHYADDR_Pos (8UL) /*!< PHYADDR (Bit 8) */ +#define EMAC_MADR_PHYADDR_Msk (0x1f00UL) /*!< PHYADDR (Bitfield-Mask: 0x1f) */ +/* ========================================================= MWTD ========================================================== */ +#define EMAC_MWTD_WRITEDATA_Pos (0UL) /*!< WRITEDATA (Bit 0) */ +#define EMAC_MWTD_WRITEDATA_Msk (0xffffUL) /*!< WRITEDATA (Bitfield-Mask: 0xffff) */ +/* ========================================================= MRDD ========================================================== */ +#define EMAC_MRDD_READDATA_Pos (0UL) /*!< READDATA (Bit 0) */ +#define EMAC_MRDD_READDATA_Msk (0xffffUL) /*!< READDATA (Bitfield-Mask: 0xffff) */ +/* ========================================================= MIND ========================================================== */ +#define EMAC_MIND_BUSY_Pos (0UL) /*!< BUSY (Bit 0) */ +#define EMAC_MIND_BUSY_Msk (0x1UL) /*!< BUSY (Bitfield-Mask: 0x01) */ +#define EMAC_MIND_SCANNING_Pos (1UL) /*!< SCANNING (Bit 1) */ +#define EMAC_MIND_SCANNING_Msk (0x2UL) /*!< SCANNING (Bitfield-Mask: 0x01) */ +#define EMAC_MIND_NOTVALID_Pos (2UL) /*!< NOTVALID (Bit 2) */ +#define EMAC_MIND_NOTVALID_Msk (0x4UL) /*!< NOTVALID (Bitfield-Mask: 0x01) */ +#define EMAC_MIND_MIILINKFAIL_Pos (3UL) /*!< MIILINKFAIL (Bit 3) */ +#define EMAC_MIND_MIILINKFAIL_Msk (0x8UL) /*!< MIILINKFAIL (Bitfield-Mask: 0x01) */ +/* ========================================================== SA0 ========================================================== */ +#define EMAC_SA0_SADDR2_Pos (0UL) /*!< SADDR2 (Bit 0) */ +#define EMAC_SA0_SADDR2_Msk (0xffUL) /*!< SADDR2 (Bitfield-Mask: 0xff) */ +#define EMAC_SA0_SADDR1_Pos (8UL) /*!< SADDR1 (Bit 8) */ +#define EMAC_SA0_SADDR1_Msk (0xff00UL) /*!< SADDR1 (Bitfield-Mask: 0xff) */ +/* ========================================================== SA1 ========================================================== */ +#define EMAC_SA1_SADDR4_Pos (0UL) /*!< SADDR4 (Bit 0) */ +#define EMAC_SA1_SADDR4_Msk (0xffUL) /*!< SADDR4 (Bitfield-Mask: 0xff) */ +#define EMAC_SA1_SADDR3_Pos (8UL) /*!< SADDR3 (Bit 8) */ +#define EMAC_SA1_SADDR3_Msk (0xff00UL) /*!< SADDR3 (Bitfield-Mask: 0xff) */ +/* ========================================================== SA2 ========================================================== */ +#define EMAC_SA2_SADDR6_Pos (0UL) /*!< SADDR6 (Bit 0) */ +#define EMAC_SA2_SADDR6_Msk (0xffUL) /*!< SADDR6 (Bitfield-Mask: 0xff) */ +#define EMAC_SA2_SADDR5_Pos (8UL) /*!< SADDR5 (Bit 8) */ +#define EMAC_SA2_SADDR5_Msk (0xff00UL) /*!< SADDR5 (Bitfield-Mask: 0xff) */ +/* ======================================================== COMMAND ======================================================== */ +#define EMAC_COMMAND_RXENABLE_Pos (0UL) /*!< RXENABLE (Bit 0) */ +#define EMAC_COMMAND_RXENABLE_Msk (0x1UL) /*!< RXENABLE (Bitfield-Mask: 0x01) */ +#define EMAC_COMMAND_TXENABLE_Pos (1UL) /*!< TXENABLE (Bit 1) */ +#define EMAC_COMMAND_TXENABLE_Msk (0x2UL) /*!< TXENABLE (Bitfield-Mask: 0x01) */ +#define EMAC_COMMAND_REGRESET_Pos (3UL) /*!< REGRESET (Bit 3) */ +#define EMAC_COMMAND_REGRESET_Msk (0x8UL) /*!< REGRESET (Bitfield-Mask: 0x01) */ +#define EMAC_COMMAND_TXRESET_Pos (4UL) /*!< TXRESET (Bit 4) */ +#define EMAC_COMMAND_TXRESET_Msk (0x10UL) /*!< TXRESET (Bitfield-Mask: 0x01) */ +#define EMAC_COMMAND_RXRESET_Pos (5UL) /*!< RXRESET (Bit 5) */ +#define EMAC_COMMAND_RXRESET_Msk (0x20UL) /*!< RXRESET (Bitfield-Mask: 0x01) */ +#define EMAC_COMMAND_PASSRUNTFRAME_Pos (6UL) /*!< PASSRUNTFRAME (Bit 6) */ +#define EMAC_COMMAND_PASSRUNTFRAME_Msk (0x40UL) /*!< PASSRUNTFRAME (Bitfield-Mask: 0x01) */ +#define EMAC_COMMAND_PASSRXFILTER_Pos (7UL) /*!< PASSRXFILTER (Bit 7) */ +#define EMAC_COMMAND_PASSRXFILTER_Msk (0x80UL) /*!< PASSRXFILTER (Bitfield-Mask: 0x01) */ +#define EMAC_COMMAND_TXFLOWCONTROL_Pos (8UL) /*!< TXFLOWCONTROL (Bit 8) */ +#define EMAC_COMMAND_TXFLOWCONTROL_Msk (0x100UL) /*!< TXFLOWCONTROL (Bitfield-Mask: 0x01) */ +#define EMAC_COMMAND_RMII_Pos (9UL) /*!< RMII (Bit 9) */ +#define EMAC_COMMAND_RMII_Msk (0x200UL) /*!< RMII (Bitfield-Mask: 0x01) */ +#define EMAC_COMMAND_FULLDUPLEX_Pos (10UL) /*!< FULLDUPLEX (Bit 10) */ +#define EMAC_COMMAND_FULLDUPLEX_Msk (0x400UL) /*!< FULLDUPLEX (Bitfield-Mask: 0x01) */ +/* ======================================================== STATUS ========================================================= */ +#define EMAC_STATUS_RXSTATUS_Pos (0UL) /*!< RXSTATUS (Bit 0) */ +#define EMAC_STATUS_RXSTATUS_Msk (0x1UL) /*!< RXSTATUS (Bitfield-Mask: 0x01) */ +#define EMAC_STATUS_TXSTATUS_Pos (1UL) /*!< TXSTATUS (Bit 1) */ +#define EMAC_STATUS_TXSTATUS_Msk (0x2UL) /*!< TXSTATUS (Bitfield-Mask: 0x01) */ +/* ===================================================== RXDESCRIPTOR ====================================================== */ +#define EMAC_RXDESCRIPTOR_RXDESCRIPTOR_Pos (2UL) /*!< RXDESCRIPTOR (Bit 2) */ +#define EMAC_RXDESCRIPTOR_RXDESCRIPTOR_Msk (0xfffffffcUL) /*!< RXDESCRIPTOR (Bitfield-Mask: 0x3fffffff) */ +/* ======================================================= RXSTATUS ======================================================== */ +#define EMAC_RXSTATUS_RXSTATUS_Pos (3UL) /*!< RXSTATUS (Bit 3) */ +#define EMAC_RXSTATUS_RXSTATUS_Msk (0xfffffff8UL) /*!< RXSTATUS (Bitfield-Mask: 0x1fffffff) */ +/* ================================================== RXDESCRIPTORNUMBER =================================================== */ +#define EMAC_RXDESCRIPTORNUMBER_RXDESCRIPTORN_Pos (0UL) /*!< RXDESCRIPTORN (Bit 0) */ +#define EMAC_RXDESCRIPTORNUMBER_RXDESCRIPTORN_Msk (0xffffUL) /*!< RXDESCRIPTORN (Bitfield-Mask: 0xffff) */ +/* ==================================================== RXPRODUCEINDEX ===================================================== */ +#define EMAC_RXPRODUCEINDEX_RXPRODUCEIX_Pos (0UL) /*!< RXPRODUCEIX (Bit 0) */ +#define EMAC_RXPRODUCEINDEX_RXPRODUCEIX_Msk (0xffffUL) /*!< RXPRODUCEIX (Bitfield-Mask: 0xffff) */ +/* ==================================================== RXCONSUMEINDEX ===================================================== */ +#define EMAC_RXCONSUMEINDEX_RXCONSUMEIX_Pos (0UL) /*!< RXCONSUMEIX (Bit 0) */ +#define EMAC_RXCONSUMEINDEX_RXCONSUMEIX_Msk (0xffffUL) /*!< RXCONSUMEIX (Bitfield-Mask: 0xffff) */ +/* ===================================================== TXDESCRIPTOR ====================================================== */ +#define EMAC_TXDESCRIPTOR_TXD_Pos (2UL) /*!< TXD (Bit 2) */ +#define EMAC_TXDESCRIPTOR_TXD_Msk (0xfffffffcUL) /*!< TXD (Bitfield-Mask: 0x3fffffff) */ +/* ======================================================= TXSTATUS ======================================================== */ +#define EMAC_TXSTATUS_TXSTAT_Pos (2UL) /*!< TXSTAT (Bit 2) */ +#define EMAC_TXSTATUS_TXSTAT_Msk (0xfffffffcUL) /*!< TXSTAT (Bitfield-Mask: 0x3fffffff) */ +/* ================================================== TXDESCRIPTORNUMBER =================================================== */ +#define EMAC_TXDESCRIPTORNUMBER_TXDN_Pos (0UL) /*!< TXDN (Bit 0) */ +#define EMAC_TXDESCRIPTORNUMBER_TXDN_Msk (0xffffUL) /*!< TXDN (Bitfield-Mask: 0xffff) */ +/* ==================================================== TXPRODUCEINDEX ===================================================== */ +#define EMAC_TXPRODUCEINDEX_TXPI_Pos (0UL) /*!< TXPI (Bit 0) */ +#define EMAC_TXPRODUCEINDEX_TXPI_Msk (0xffffUL) /*!< TXPI (Bitfield-Mask: 0xffff) */ +/* ==================================================== TXCONSUMEINDEX ===================================================== */ +#define EMAC_TXCONSUMEINDEX_TXCI_Pos (0UL) /*!< TXCI (Bit 0) */ +#define EMAC_TXCONSUMEINDEX_TXCI_Msk (0xffffUL) /*!< TXCI (Bitfield-Mask: 0xffff) */ +/* ========================================================= TSV0 ========================================================== */ +#define EMAC_TSV0_CRCERR_Pos (0UL) /*!< CRCERR (Bit 0) */ +#define EMAC_TSV0_CRCERR_Msk (0x1UL) /*!< CRCERR (Bitfield-Mask: 0x01) */ +#define EMAC_TSV0_LCE_Pos (1UL) /*!< LCE (Bit 1) */ +#define EMAC_TSV0_LCE_Msk (0x2UL) /*!< LCE (Bitfield-Mask: 0x01) */ +#define EMAC_TSV0_LOR_Pos (2UL) /*!< LOR (Bit 2) */ +#define EMAC_TSV0_LOR_Msk (0x4UL) /*!< LOR (Bitfield-Mask: 0x01) */ +#define EMAC_TSV0_DONE_Pos (3UL) /*!< DONE (Bit 3) */ +#define EMAC_TSV0_DONE_Msk (0x8UL) /*!< DONE (Bitfield-Mask: 0x01) */ +#define EMAC_TSV0_MULTICAST_Pos (4UL) /*!< MULTICAST (Bit 4) */ +#define EMAC_TSV0_MULTICAST_Msk (0x10UL) /*!< MULTICAST (Bitfield-Mask: 0x01) */ +#define EMAC_TSV0_BROADCAST_Pos (5UL) /*!< BROADCAST (Bit 5) */ +#define EMAC_TSV0_BROADCAST_Msk (0x20UL) /*!< BROADCAST (Bitfield-Mask: 0x01) */ +#define EMAC_TSV0_PACKETDEFER_Pos (6UL) /*!< PACKETDEFER (Bit 6) */ +#define EMAC_TSV0_PACKETDEFER_Msk (0x40UL) /*!< PACKETDEFER (Bitfield-Mask: 0x01) */ +#define EMAC_TSV0_EXDF_Pos (7UL) /*!< EXDF (Bit 7) */ +#define EMAC_TSV0_EXDF_Msk (0x80UL) /*!< EXDF (Bitfield-Mask: 0x01) */ +#define EMAC_TSV0_EXCOL_Pos (8UL) /*!< EXCOL (Bit 8) */ +#define EMAC_TSV0_EXCOL_Msk (0x100UL) /*!< EXCOL (Bitfield-Mask: 0x01) */ +#define EMAC_TSV0_LCOL_Pos (9UL) /*!< LCOL (Bit 9) */ +#define EMAC_TSV0_LCOL_Msk (0x200UL) /*!< LCOL (Bitfield-Mask: 0x01) */ +#define EMAC_TSV0_GIANT_Pos (10UL) /*!< GIANT (Bit 10) */ +#define EMAC_TSV0_GIANT_Msk (0x400UL) /*!< GIANT (Bitfield-Mask: 0x01) */ +#define EMAC_TSV0_UNDERRUN_Pos (11UL) /*!< UNDERRUN (Bit 11) */ +#define EMAC_TSV0_UNDERRUN_Msk (0x800UL) /*!< UNDERRUN (Bitfield-Mask: 0x01) */ +#define EMAC_TSV0_TOTALBYTES_Pos (12UL) /*!< TOTALBYTES (Bit 12) */ +#define EMAC_TSV0_TOTALBYTES_Msk (0xffff000UL) /*!< TOTALBYTES (Bitfield-Mask: 0xffff) */ +#define EMAC_TSV0_CONTROLFRAME_Pos (28UL) /*!< CONTROLFRAME (Bit 28) */ +#define EMAC_TSV0_CONTROLFRAME_Msk (0x10000000UL) /*!< CONTROLFRAME (Bitfield-Mask: 0x01) */ +#define EMAC_TSV0_PAUSE_Pos (29UL) /*!< PAUSE (Bit 29) */ +#define EMAC_TSV0_PAUSE_Msk (0x20000000UL) /*!< PAUSE (Bitfield-Mask: 0x01) */ +#define EMAC_TSV0_BACKPRESSURE_Pos (30UL) /*!< BACKPRESSURE (Bit 30) */ +#define EMAC_TSV0_BACKPRESSURE_Msk (0x40000000UL) /*!< BACKPRESSURE (Bitfield-Mask: 0x01) */ +#define EMAC_TSV0_VLAN_Pos (31UL) /*!< VLAN (Bit 31) */ +#define EMAC_TSV0_VLAN_Msk (0x80000000UL) /*!< VLAN (Bitfield-Mask: 0x01) */ +/* ========================================================= TSV1 ========================================================== */ +#define EMAC_TSV1_TBC_Pos (0UL) /*!< TBC (Bit 0) */ +#define EMAC_TSV1_TBC_Msk (0xffffUL) /*!< TBC (Bitfield-Mask: 0xffff) */ +#define EMAC_TSV1_TCC_Pos (16UL) /*!< TCC (Bit 16) */ +#define EMAC_TSV1_TCC_Msk (0xf0000UL) /*!< TCC (Bitfield-Mask: 0x0f) */ +/* ========================================================== RSV ========================================================== */ +#define EMAC_RSV_RBC_Pos (0UL) /*!< RBC (Bit 0) */ +#define EMAC_RSV_RBC_Msk (0xffffUL) /*!< RBC (Bitfield-Mask: 0xffff) */ +#define EMAC_RSV_PPI_Pos (16UL) /*!< PPI (Bit 16) */ +#define EMAC_RSV_PPI_Msk (0x10000UL) /*!< PPI (Bitfield-Mask: 0x01) */ +#define EMAC_RSV_RXDVSEEN_Pos (17UL) /*!< RXDVSEEN (Bit 17) */ +#define EMAC_RSV_RXDVSEEN_Msk (0x20000UL) /*!< RXDVSEEN (Bitfield-Mask: 0x01) */ +#define EMAC_RSV_CESEEN_Pos (18UL) /*!< CESEEN (Bit 18) */ +#define EMAC_RSV_CESEEN_Msk (0x40000UL) /*!< CESEEN (Bitfield-Mask: 0x01) */ +#define EMAC_RSV_RCV_Pos (19UL) /*!< RCV (Bit 19) */ +#define EMAC_RSV_RCV_Msk (0x80000UL) /*!< RCV (Bitfield-Mask: 0x01) */ +#define EMAC_RSV_CRCERR_Pos (20UL) /*!< CRCERR (Bit 20) */ +#define EMAC_RSV_CRCERR_Msk (0x100000UL) /*!< CRCERR (Bitfield-Mask: 0x01) */ +#define EMAC_RSV_LCERR_Pos (21UL) /*!< LCERR (Bit 21) */ +#define EMAC_RSV_LCERR_Msk (0x200000UL) /*!< LCERR (Bitfield-Mask: 0x01) */ +#define EMAC_RSV_LOR_Pos (22UL) /*!< LOR (Bit 22) */ +#define EMAC_RSV_LOR_Msk (0x400000UL) /*!< LOR (Bitfield-Mask: 0x01) */ +#define EMAC_RSV_ROK_Pos (23UL) /*!< ROK (Bit 23) */ +#define EMAC_RSV_ROK_Msk (0x800000UL) /*!< ROK (Bitfield-Mask: 0x01) */ +#define EMAC_RSV_MULTICAST_Pos (24UL) /*!< MULTICAST (Bit 24) */ +#define EMAC_RSV_MULTICAST_Msk (0x1000000UL) /*!< MULTICAST (Bitfield-Mask: 0x01) */ +#define EMAC_RSV_BROADCAST_Pos (25UL) /*!< BROADCAST (Bit 25) */ +#define EMAC_RSV_BROADCAST_Msk (0x2000000UL) /*!< BROADCAST (Bitfield-Mask: 0x01) */ +#define EMAC_RSV_DRIBBLENIBBLE_Pos (26UL) /*!< DRIBBLENIBBLE (Bit 26) */ +#define EMAC_RSV_DRIBBLENIBBLE_Msk (0x4000000UL) /*!< DRIBBLENIBBLE (Bitfield-Mask: 0x01) */ +#define EMAC_RSV_CONTROLFRAME_Pos (27UL) /*!< CONTROLFRAME (Bit 27) */ +#define EMAC_RSV_CONTROLFRAME_Msk (0x8000000UL) /*!< CONTROLFRAME (Bitfield-Mask: 0x01) */ +#define EMAC_RSV_PAUSE_Pos (28UL) /*!< PAUSE (Bit 28) */ +#define EMAC_RSV_PAUSE_Msk (0x10000000UL) /*!< PAUSE (Bitfield-Mask: 0x01) */ +#define EMAC_RSV_UO_Pos (29UL) /*!< UO (Bit 29) */ +#define EMAC_RSV_UO_Msk (0x20000000UL) /*!< UO (Bitfield-Mask: 0x01) */ +#define EMAC_RSV_VLAN_Pos (30UL) /*!< VLAN (Bit 30) */ +#define EMAC_RSV_VLAN_Msk (0x40000000UL) /*!< VLAN (Bitfield-Mask: 0x01) */ +/* ================================================== FLOWCONTROLCOUNTER =================================================== */ +#define EMAC_FLOWCONTROLCOUNTER_MC_Pos (0UL) /*!< MC (Bit 0) */ +#define EMAC_FLOWCONTROLCOUNTER_MC_Msk (0xffffUL) /*!< MC (Bitfield-Mask: 0xffff) */ +#define EMAC_FLOWCONTROLCOUNTER_PT_Pos (16UL) /*!< PT (Bit 16) */ +#define EMAC_FLOWCONTROLCOUNTER_PT_Msk (0xffff0000UL) /*!< PT (Bitfield-Mask: 0xffff) */ +/* =================================================== FLOWCONTROLSTATUS =================================================== */ +#define EMAC_FLOWCONTROLSTATUS_MCC_Pos (0UL) /*!< MCC (Bit 0) */ +#define EMAC_FLOWCONTROLSTATUS_MCC_Msk (0xffffUL) /*!< MCC (Bitfield-Mask: 0xffff) */ +/* ===================================================== RXFILTERCTRL ====================================================== */ +#define EMAC_RXFILTERCTRL_AUE_Pos (0UL) /*!< AUE (Bit 0) */ +#define EMAC_RXFILTERCTRL_AUE_Msk (0x1UL) /*!< AUE (Bitfield-Mask: 0x01) */ +#define EMAC_RXFILTERCTRL_ABE_Pos (1UL) /*!< ABE (Bit 1) */ +#define EMAC_RXFILTERCTRL_ABE_Msk (0x2UL) /*!< ABE (Bitfield-Mask: 0x01) */ +#define EMAC_RXFILTERCTRL_AME_Pos (2UL) /*!< AME (Bit 2) */ +#define EMAC_RXFILTERCTRL_AME_Msk (0x4UL) /*!< AME (Bitfield-Mask: 0x01) */ +#define EMAC_RXFILTERCTRL_AUHE_Pos (3UL) /*!< AUHE (Bit 3) */ +#define EMAC_RXFILTERCTRL_AUHE_Msk (0x8UL) /*!< AUHE (Bitfield-Mask: 0x01) */ +#define EMAC_RXFILTERCTRL_AMHE_Pos (4UL) /*!< AMHE (Bit 4) */ +#define EMAC_RXFILTERCTRL_AMHE_Msk (0x10UL) /*!< AMHE (Bitfield-Mask: 0x01) */ +#define EMAC_RXFILTERCTRL_APE_Pos (5UL) /*!< APE (Bit 5) */ +#define EMAC_RXFILTERCTRL_APE_Msk (0x20UL) /*!< APE (Bitfield-Mask: 0x01) */ +#define EMAC_RXFILTERCTRL_MPEW_Pos (12UL) /*!< MPEW (Bit 12) */ +#define EMAC_RXFILTERCTRL_MPEW_Msk (0x1000UL) /*!< MPEW (Bitfield-Mask: 0x01) */ +#define EMAC_RXFILTERCTRL_RFEW_Pos (13UL) /*!< RFEW (Bit 13) */ +#define EMAC_RXFILTERCTRL_RFEW_Msk (0x2000UL) /*!< RFEW (Bitfield-Mask: 0x01) */ +/* =================================================== RXFILTERWOLSTATUS =================================================== */ +#define EMAC_RXFILTERWOLSTATUS_AUW_Pos (0UL) /*!< AUW (Bit 0) */ +#define EMAC_RXFILTERWOLSTATUS_AUW_Msk (0x1UL) /*!< AUW (Bitfield-Mask: 0x01) */ +#define EMAC_RXFILTERWOLSTATUS_ABW_Pos (1UL) /*!< ABW (Bit 1) */ +#define EMAC_RXFILTERWOLSTATUS_ABW_Msk (0x2UL) /*!< ABW (Bitfield-Mask: 0x01) */ +#define EMAC_RXFILTERWOLSTATUS_AMW_Pos (2UL) /*!< AMW (Bit 2) */ +#define EMAC_RXFILTERWOLSTATUS_AMW_Msk (0x4UL) /*!< AMW (Bitfield-Mask: 0x01) */ +#define EMAC_RXFILTERWOLSTATUS_AUHW_Pos (3UL) /*!< AUHW (Bit 3) */ +#define EMAC_RXFILTERWOLSTATUS_AUHW_Msk (0x8UL) /*!< AUHW (Bitfield-Mask: 0x01) */ +#define EMAC_RXFILTERWOLSTATUS_AMHW_Pos (4UL) /*!< AMHW (Bit 4) */ +#define EMAC_RXFILTERWOLSTATUS_AMHW_Msk (0x10UL) /*!< AMHW (Bitfield-Mask: 0x01) */ +#define EMAC_RXFILTERWOLSTATUS_APW_Pos (5UL) /*!< APW (Bit 5) */ +#define EMAC_RXFILTERWOLSTATUS_APW_Msk (0x20UL) /*!< APW (Bitfield-Mask: 0x01) */ +#define EMAC_RXFILTERWOLSTATUS_RFW_Pos (7UL) /*!< RFW (Bit 7) */ +#define EMAC_RXFILTERWOLSTATUS_RFW_Msk (0x80UL) /*!< RFW (Bitfield-Mask: 0x01) */ +#define EMAC_RXFILTERWOLSTATUS_MPW_Pos (8UL) /*!< MPW (Bit 8) */ +#define EMAC_RXFILTERWOLSTATUS_MPW_Msk (0x100UL) /*!< MPW (Bitfield-Mask: 0x01) */ +/* =================================================== RXFILTERWOLCLEAR ==================================================== */ +#define EMAC_RXFILTERWOLCLEAR_AUWCLR_Pos (0UL) /*!< AUWCLR (Bit 0) */ +#define EMAC_RXFILTERWOLCLEAR_AUWCLR_Msk (0x1UL) /*!< AUWCLR (Bitfield-Mask: 0x01) */ +#define EMAC_RXFILTERWOLCLEAR_ABWCLR_Pos (1UL) /*!< ABWCLR (Bit 1) */ +#define EMAC_RXFILTERWOLCLEAR_ABWCLR_Msk (0x2UL) /*!< ABWCLR (Bitfield-Mask: 0x01) */ +#define EMAC_RXFILTERWOLCLEAR_AMWCLR_Pos (2UL) /*!< AMWCLR (Bit 2) */ +#define EMAC_RXFILTERWOLCLEAR_AMWCLR_Msk (0x4UL) /*!< AMWCLR (Bitfield-Mask: 0x01) */ +#define EMAC_RXFILTERWOLCLEAR_AUHWCLR_Pos (3UL) /*!< AUHWCLR (Bit 3) */ +#define EMAC_RXFILTERWOLCLEAR_AUHWCLR_Msk (0x8UL) /*!< AUHWCLR (Bitfield-Mask: 0x01) */ +#define EMAC_RXFILTERWOLCLEAR_AMHWCLR_Pos (4UL) /*!< AMHWCLR (Bit 4) */ +#define EMAC_RXFILTERWOLCLEAR_AMHWCLR_Msk (0x10UL) /*!< AMHWCLR (Bitfield-Mask: 0x01) */ +#define EMAC_RXFILTERWOLCLEAR_APWCLR_Pos (5UL) /*!< APWCLR (Bit 5) */ +#define EMAC_RXFILTERWOLCLEAR_APWCLR_Msk (0x20UL) /*!< APWCLR (Bitfield-Mask: 0x01) */ +#define EMAC_RXFILTERWOLCLEAR_RFWCLR_Pos (7UL) /*!< RFWCLR (Bit 7) */ +#define EMAC_RXFILTERWOLCLEAR_RFWCLR_Msk (0x80UL) /*!< RFWCLR (Bitfield-Mask: 0x01) */ +#define EMAC_RXFILTERWOLCLEAR_MPWCLR_Pos (8UL) /*!< MPWCLR (Bit 8) */ +#define EMAC_RXFILTERWOLCLEAR_MPWCLR_Msk (0x100UL) /*!< MPWCLR (Bitfield-Mask: 0x01) */ +/* ====================================================== HASHFILTERL ====================================================== */ +#define EMAC_HASHFILTERL_HFL_Pos (0UL) /*!< HFL (Bit 0) */ +#define EMAC_HASHFILTERL_HFL_Msk (0xffffffffUL) /*!< HFL (Bitfield-Mask: 0xffffffff) */ +/* ====================================================== HASHFILTERH ====================================================== */ +#define EMAC_HASHFILTERH_HFH_Pos (0UL) /*!< HFH (Bit 0) */ +#define EMAC_HASHFILTERH_HFH_Msk (0xffffffffUL) /*!< HFH (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= INTSTATUS ======================================================= */ +#define EMAC_INTSTATUS_RXOVERRUNINT_Pos (0UL) /*!< RXOVERRUNINT (Bit 0) */ +#define EMAC_INTSTATUS_RXOVERRUNINT_Msk (0x1UL) /*!< RXOVERRUNINT (Bitfield-Mask: 0x01) */ +#define EMAC_INTSTATUS_RXERRORINT_Pos (1UL) /*!< RXERRORINT (Bit 1) */ +#define EMAC_INTSTATUS_RXERRORINT_Msk (0x2UL) /*!< RXERRORINT (Bitfield-Mask: 0x01) */ +#define EMAC_INTSTATUS_RXFINISHEDINT_Pos (2UL) /*!< RXFINISHEDINT (Bit 2) */ +#define EMAC_INTSTATUS_RXFINISHEDINT_Msk (0x4UL) /*!< RXFINISHEDINT (Bitfield-Mask: 0x01) */ +#define EMAC_INTSTATUS_RXDONEINT_Pos (3UL) /*!< RXDONEINT (Bit 3) */ +#define EMAC_INTSTATUS_RXDONEINT_Msk (0x8UL) /*!< RXDONEINT (Bitfield-Mask: 0x01) */ +#define EMAC_INTSTATUS_TXUNDERRUNINT_Pos (4UL) /*!< TXUNDERRUNINT (Bit 4) */ +#define EMAC_INTSTATUS_TXUNDERRUNINT_Msk (0x10UL) /*!< TXUNDERRUNINT (Bitfield-Mask: 0x01) */ +#define EMAC_INTSTATUS_TXERRORINT_Pos (5UL) /*!< TXERRORINT (Bit 5) */ +#define EMAC_INTSTATUS_TXERRORINT_Msk (0x20UL) /*!< TXERRORINT (Bitfield-Mask: 0x01) */ +#define EMAC_INTSTATUS_TXFINISHEDINT_Pos (6UL) /*!< TXFINISHEDINT (Bit 6) */ +#define EMAC_INTSTATUS_TXFINISHEDINT_Msk (0x40UL) /*!< TXFINISHEDINT (Bitfield-Mask: 0x01) */ +#define EMAC_INTSTATUS_TXDONEINT_Pos (7UL) /*!< TXDONEINT (Bit 7) */ +#define EMAC_INTSTATUS_TXDONEINT_Msk (0x80UL) /*!< TXDONEINT (Bitfield-Mask: 0x01) */ +#define EMAC_INTSTATUS_SOFTINT_Pos (12UL) /*!< SOFTINT (Bit 12) */ +#define EMAC_INTSTATUS_SOFTINT_Msk (0x1000UL) /*!< SOFTINT (Bitfield-Mask: 0x01) */ +#define EMAC_INTSTATUS_WAKEUPINT_Pos (13UL) /*!< WAKEUPINT (Bit 13) */ +#define EMAC_INTSTATUS_WAKEUPINT_Msk (0x2000UL) /*!< WAKEUPINT (Bitfield-Mask: 0x01) */ +/* ======================================================= INTENABLE ======================================================= */ +#define EMAC_INTENABLE_RXOVERRUNINTEN_Pos (0UL) /*!< RXOVERRUNINTEN (Bit 0) */ +#define EMAC_INTENABLE_RXOVERRUNINTEN_Msk (0x1UL) /*!< RXOVERRUNINTEN (Bitfield-Mask: 0x01) */ +#define EMAC_INTENABLE_RXERRORINTEN_Pos (1UL) /*!< RXERRORINTEN (Bit 1) */ +#define EMAC_INTENABLE_RXERRORINTEN_Msk (0x2UL) /*!< RXERRORINTEN (Bitfield-Mask: 0x01) */ +#define EMAC_INTENABLE_RXFINISHEDINTEN_Pos (2UL) /*!< RXFINISHEDINTEN (Bit 2) */ +#define EMAC_INTENABLE_RXFINISHEDINTEN_Msk (0x4UL) /*!< RXFINISHEDINTEN (Bitfield-Mask: 0x01) */ +#define EMAC_INTENABLE_RXDONEINTEN_Pos (3UL) /*!< RXDONEINTEN (Bit 3) */ +#define EMAC_INTENABLE_RXDONEINTEN_Msk (0x8UL) /*!< RXDONEINTEN (Bitfield-Mask: 0x01) */ +#define EMAC_INTENABLE_TXUNDERRUNINTEN_Pos (4UL) /*!< TXUNDERRUNINTEN (Bit 4) */ +#define EMAC_INTENABLE_TXUNDERRUNINTEN_Msk (0x10UL) /*!< TXUNDERRUNINTEN (Bitfield-Mask: 0x01) */ +#define EMAC_INTENABLE_TXERRORINTEN_Pos (5UL) /*!< TXERRORINTEN (Bit 5) */ +#define EMAC_INTENABLE_TXERRORINTEN_Msk (0x20UL) /*!< TXERRORINTEN (Bitfield-Mask: 0x01) */ +#define EMAC_INTENABLE_TXFINISHEDINTEN_Pos (6UL) /*!< TXFINISHEDINTEN (Bit 6) */ +#define EMAC_INTENABLE_TXFINISHEDINTEN_Msk (0x40UL) /*!< TXFINISHEDINTEN (Bitfield-Mask: 0x01) */ +#define EMAC_INTENABLE_TXDONEINTEN_Pos (7UL) /*!< TXDONEINTEN (Bit 7) */ +#define EMAC_INTENABLE_TXDONEINTEN_Msk (0x80UL) /*!< TXDONEINTEN (Bitfield-Mask: 0x01) */ +#define EMAC_INTENABLE_SOFTINTEN_Pos (12UL) /*!< SOFTINTEN (Bit 12) */ +#define EMAC_INTENABLE_SOFTINTEN_Msk (0x1000UL) /*!< SOFTINTEN (Bitfield-Mask: 0x01) */ +#define EMAC_INTENABLE_WAKEUPINTEN_Pos (13UL) /*!< WAKEUPINTEN (Bit 13) */ +#define EMAC_INTENABLE_WAKEUPINTEN_Msk (0x2000UL) /*!< WAKEUPINTEN (Bitfield-Mask: 0x01) */ +/* ======================================================= INTCLEAR ======================================================== */ +#define EMAC_INTCLEAR_RXOVERRUNINTCLR_Pos (0UL) /*!< RXOVERRUNINTCLR (Bit 0) */ +#define EMAC_INTCLEAR_RXOVERRUNINTCLR_Msk (0x1UL) /*!< RXOVERRUNINTCLR (Bitfield-Mask: 0x01) */ +#define EMAC_INTCLEAR_RXERRORINTCLR_Pos (1UL) /*!< RXERRORINTCLR (Bit 1) */ +#define EMAC_INTCLEAR_RXERRORINTCLR_Msk (0x2UL) /*!< RXERRORINTCLR (Bitfield-Mask: 0x01) */ +#define EMAC_INTCLEAR_RXFINISHEDINTCLR_Pos (2UL) /*!< RXFINISHEDINTCLR (Bit 2) */ +#define EMAC_INTCLEAR_RXFINISHEDINTCLR_Msk (0x4UL) /*!< RXFINISHEDINTCLR (Bitfield-Mask: 0x01) */ +#define EMAC_INTCLEAR_RXDONEINTCLR_Pos (3UL) /*!< RXDONEINTCLR (Bit 3) */ +#define EMAC_INTCLEAR_RXDONEINTCLR_Msk (0x8UL) /*!< RXDONEINTCLR (Bitfield-Mask: 0x01) */ +#define EMAC_INTCLEAR_TXUNDERRUNINTCLR_Pos (4UL) /*!< TXUNDERRUNINTCLR (Bit 4) */ +#define EMAC_INTCLEAR_TXUNDERRUNINTCLR_Msk (0x10UL) /*!< TXUNDERRUNINTCLR (Bitfield-Mask: 0x01) */ +#define EMAC_INTCLEAR_TXERRORINTCLR_Pos (5UL) /*!< TXERRORINTCLR (Bit 5) */ +#define EMAC_INTCLEAR_TXERRORINTCLR_Msk (0x20UL) /*!< TXERRORINTCLR (Bitfield-Mask: 0x01) */ +#define EMAC_INTCLEAR_TXFINISHEDINTCLR_Pos (6UL) /*!< TXFINISHEDINTCLR (Bit 6) */ +#define EMAC_INTCLEAR_TXFINISHEDINTCLR_Msk (0x40UL) /*!< TXFINISHEDINTCLR (Bitfield-Mask: 0x01) */ +#define EMAC_INTCLEAR_TXDONEINTCLR_Pos (7UL) /*!< TXDONEINTCLR (Bit 7) */ +#define EMAC_INTCLEAR_TXDONEINTCLR_Msk (0x80UL) /*!< TXDONEINTCLR (Bitfield-Mask: 0x01) */ +#define EMAC_INTCLEAR_SOFTINTCLR_Pos (12UL) /*!< SOFTINTCLR (Bit 12) */ +#define EMAC_INTCLEAR_SOFTINTCLR_Msk (0x1000UL) /*!< SOFTINTCLR (Bitfield-Mask: 0x01) */ +#define EMAC_INTCLEAR_WAKEUPINTCLR_Pos (13UL) /*!< WAKEUPINTCLR (Bit 13) */ +#define EMAC_INTCLEAR_WAKEUPINTCLR_Msk (0x2000UL) /*!< WAKEUPINTCLR (Bitfield-Mask: 0x01) */ +/* ======================================================== INTSET ========================================================= */ +#define EMAC_INTSET_RXOVERRUNINTSET_Pos (0UL) /*!< RXOVERRUNINTSET (Bit 0) */ +#define EMAC_INTSET_RXOVERRUNINTSET_Msk (0x1UL) /*!< RXOVERRUNINTSET (Bitfield-Mask: 0x01) */ +#define EMAC_INTSET_RXERRORINTSET_Pos (1UL) /*!< RXERRORINTSET (Bit 1) */ +#define EMAC_INTSET_RXERRORINTSET_Msk (0x2UL) /*!< RXERRORINTSET (Bitfield-Mask: 0x01) */ +#define EMAC_INTSET_RXFINISHEDINTSET_Pos (2UL) /*!< RXFINISHEDINTSET (Bit 2) */ +#define EMAC_INTSET_RXFINISHEDINTSET_Msk (0x4UL) /*!< RXFINISHEDINTSET (Bitfield-Mask: 0x01) */ +#define EMAC_INTSET_RXDONEINTSET_Pos (3UL) /*!< RXDONEINTSET (Bit 3) */ +#define EMAC_INTSET_RXDONEINTSET_Msk (0x8UL) /*!< RXDONEINTSET (Bitfield-Mask: 0x01) */ +#define EMAC_INTSET_TXUNDERRUNINTSET_Pos (4UL) /*!< TXUNDERRUNINTSET (Bit 4) */ +#define EMAC_INTSET_TXUNDERRUNINTSET_Msk (0x10UL) /*!< TXUNDERRUNINTSET (Bitfield-Mask: 0x01) */ +#define EMAC_INTSET_TXERRORINTSET_Pos (5UL) /*!< TXERRORINTSET (Bit 5) */ +#define EMAC_INTSET_TXERRORINTSET_Msk (0x20UL) /*!< TXERRORINTSET (Bitfield-Mask: 0x01) */ +#define EMAC_INTSET_TXFINISHEDINTSET_Pos (6UL) /*!< TXFINISHEDINTSET (Bit 6) */ +#define EMAC_INTSET_TXFINISHEDINTSET_Msk (0x40UL) /*!< TXFINISHEDINTSET (Bitfield-Mask: 0x01) */ +#define EMAC_INTSET_TXDONEINTSET_Pos (7UL) /*!< TXDONEINTSET (Bit 7) */ +#define EMAC_INTSET_TXDONEINTSET_Msk (0x80UL) /*!< TXDONEINTSET (Bitfield-Mask: 0x01) */ +#define EMAC_INTSET_SOFTINTSET_Pos (12UL) /*!< SOFTINTSET (Bit 12) */ +#define EMAC_INTSET_SOFTINTSET_Msk (0x1000UL) /*!< SOFTINTSET (Bitfield-Mask: 0x01) */ +#define EMAC_INTSET_WAKEUPINTSET_Pos (13UL) /*!< WAKEUPINTSET (Bit 13) */ +#define EMAC_INTSET_WAKEUPINTSET_Msk (0x2000UL) /*!< WAKEUPINTSET (Bitfield-Mask: 0x01) */ +/* ======================================================= POWERDOWN ======================================================= */ +#define EMAC_POWERDOWN_PD_Pos (31UL) /*!< PD (Bit 31) */ +#define EMAC_POWERDOWN_PD_Msk (0x80000000UL) /*!< PD (Bitfield-Mask: 0x01) */ + + +/* =========================================================================================================================== */ +/* ================ LPC_GPDMA ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== INTSTAT ======================================================== */ +#define GPDMA_INTSTAT_INTSTAT0_Pos (0UL) /*!< INTSTAT0 (Bit 0) */ +#define GPDMA_INTSTAT_INTSTAT0_Msk (0x1UL) /*!< INTSTAT0 (Bitfield-Mask: 0x01) */ +#define GPDMA_INTSTAT_INTSTAT1_Pos (1UL) /*!< INTSTAT1 (Bit 1) */ +#define GPDMA_INTSTAT_INTSTAT1_Msk (0x2UL) /*!< INTSTAT1 (Bitfield-Mask: 0x01) */ +#define GPDMA_INTSTAT_INTSTAT2_Pos (2UL) /*!< INTSTAT2 (Bit 2) */ +#define GPDMA_INTSTAT_INTSTAT2_Msk (0x4UL) /*!< INTSTAT2 (Bitfield-Mask: 0x01) */ +#define GPDMA_INTSTAT_INTSTAT3_Pos (3UL) /*!< INTSTAT3 (Bit 3) */ +#define GPDMA_INTSTAT_INTSTAT3_Msk (0x8UL) /*!< INTSTAT3 (Bitfield-Mask: 0x01) */ +#define GPDMA_INTSTAT_INTSTAT4_Pos (4UL) /*!< INTSTAT4 (Bit 4) */ +#define GPDMA_INTSTAT_INTSTAT4_Msk (0x10UL) /*!< INTSTAT4 (Bitfield-Mask: 0x01) */ +#define GPDMA_INTSTAT_INTSTAT5_Pos (5UL) /*!< INTSTAT5 (Bit 5) */ +#define GPDMA_INTSTAT_INTSTAT5_Msk (0x20UL) /*!< INTSTAT5 (Bitfield-Mask: 0x01) */ +#define GPDMA_INTSTAT_INTSTAT6_Pos (6UL) /*!< INTSTAT6 (Bit 6) */ +#define GPDMA_INTSTAT_INTSTAT6_Msk (0x40UL) /*!< INTSTAT6 (Bitfield-Mask: 0x01) */ +#define GPDMA_INTSTAT_INTSTAT7_Pos (7UL) /*!< INTSTAT7 (Bit 7) */ +#define GPDMA_INTSTAT_INTSTAT7_Msk (0x80UL) /*!< INTSTAT7 (Bitfield-Mask: 0x01) */ +/* ======================================================= INTTCSTAT ======================================================= */ +#define GPDMA_INTTCSTAT_INTTCSTAT0_Pos (0UL) /*!< INTTCSTAT0 (Bit 0) */ +#define GPDMA_INTTCSTAT_INTTCSTAT0_Msk (0x1UL) /*!< INTTCSTAT0 (Bitfield-Mask: 0x01) */ +#define GPDMA_INTTCSTAT_INTTCSTAT1_Pos (1UL) /*!< INTTCSTAT1 (Bit 1) */ +#define GPDMA_INTTCSTAT_INTTCSTAT1_Msk (0x2UL) /*!< INTTCSTAT1 (Bitfield-Mask: 0x01) */ +#define GPDMA_INTTCSTAT_INTTCSTAT2_Pos (2UL) /*!< INTTCSTAT2 (Bit 2) */ +#define GPDMA_INTTCSTAT_INTTCSTAT2_Msk (0x4UL) /*!< INTTCSTAT2 (Bitfield-Mask: 0x01) */ +#define GPDMA_INTTCSTAT_INTTCSTAT3_Pos (3UL) /*!< INTTCSTAT3 (Bit 3) */ +#define GPDMA_INTTCSTAT_INTTCSTAT3_Msk (0x8UL) /*!< INTTCSTAT3 (Bitfield-Mask: 0x01) */ +#define GPDMA_INTTCSTAT_INTTCSTAT4_Pos (4UL) /*!< INTTCSTAT4 (Bit 4) */ +#define GPDMA_INTTCSTAT_INTTCSTAT4_Msk (0x10UL) /*!< INTTCSTAT4 (Bitfield-Mask: 0x01) */ +#define GPDMA_INTTCSTAT_INTTCSTAT5_Pos (5UL) /*!< INTTCSTAT5 (Bit 5) */ +#define GPDMA_INTTCSTAT_INTTCSTAT5_Msk (0x20UL) /*!< INTTCSTAT5 (Bitfield-Mask: 0x01) */ +#define GPDMA_INTTCSTAT_INTTCSTAT6_Pos (6UL) /*!< INTTCSTAT6 (Bit 6) */ +#define GPDMA_INTTCSTAT_INTTCSTAT6_Msk (0x40UL) /*!< INTTCSTAT6 (Bitfield-Mask: 0x01) */ +#define GPDMA_INTTCSTAT_INTTCSTAT7_Pos (7UL) /*!< INTTCSTAT7 (Bit 7) */ +#define GPDMA_INTTCSTAT_INTTCSTAT7_Msk (0x80UL) /*!< INTTCSTAT7 (Bitfield-Mask: 0x01) */ +/* ====================================================== INTTCCLEAR ======================================================= */ +#define GPDMA_INTTCCLEAR_INTTCCLEAR0_Pos (0UL) /*!< INTTCCLEAR0 (Bit 0) */ +#define GPDMA_INTTCCLEAR_INTTCCLEAR0_Msk (0x1UL) /*!< INTTCCLEAR0 (Bitfield-Mask: 0x01) */ +#define GPDMA_INTTCCLEAR_INTTCCLEAR1_Pos (1UL) /*!< INTTCCLEAR1 (Bit 1) */ +#define GPDMA_INTTCCLEAR_INTTCCLEAR1_Msk (0x2UL) /*!< INTTCCLEAR1 (Bitfield-Mask: 0x01) */ +#define GPDMA_INTTCCLEAR_INTTCCLEAR2_Pos (2UL) /*!< INTTCCLEAR2 (Bit 2) */ +#define GPDMA_INTTCCLEAR_INTTCCLEAR2_Msk (0x4UL) /*!< INTTCCLEAR2 (Bitfield-Mask: 0x01) */ +#define GPDMA_INTTCCLEAR_INTTCCLEAR3_Pos (3UL) /*!< INTTCCLEAR3 (Bit 3) */ +#define GPDMA_INTTCCLEAR_INTTCCLEAR3_Msk (0x8UL) /*!< INTTCCLEAR3 (Bitfield-Mask: 0x01) */ +#define GPDMA_INTTCCLEAR_INTTCCLEAR4_Pos (4UL) /*!< INTTCCLEAR4 (Bit 4) */ +#define GPDMA_INTTCCLEAR_INTTCCLEAR4_Msk (0x10UL) /*!< INTTCCLEAR4 (Bitfield-Mask: 0x01) */ +#define GPDMA_INTTCCLEAR_INTTCCLEAR5_Pos (5UL) /*!< INTTCCLEAR5 (Bit 5) */ +#define GPDMA_INTTCCLEAR_INTTCCLEAR5_Msk (0x20UL) /*!< INTTCCLEAR5 (Bitfield-Mask: 0x01) */ +#define GPDMA_INTTCCLEAR_INTTCCLEAR6_Pos (6UL) /*!< INTTCCLEAR6 (Bit 6) */ +#define GPDMA_INTTCCLEAR_INTTCCLEAR6_Msk (0x40UL) /*!< INTTCCLEAR6 (Bitfield-Mask: 0x01) */ +#define GPDMA_INTTCCLEAR_INTTCCLEAR7_Pos (7UL) /*!< INTTCCLEAR7 (Bit 7) */ +#define GPDMA_INTTCCLEAR_INTTCCLEAR7_Msk (0x80UL) /*!< INTTCCLEAR7 (Bitfield-Mask: 0x01) */ +/* ====================================================== INTERRSTAT ======================================================= */ +#define GPDMA_INTERRSTAT_INTERRSTAT0_Pos (0UL) /*!< INTERRSTAT0 (Bit 0) */ +#define GPDMA_INTERRSTAT_INTERRSTAT0_Msk (0x1UL) /*!< INTERRSTAT0 (Bitfield-Mask: 0x01) */ +#define GPDMA_INTERRSTAT_INTERRSTAT1_Pos (1UL) /*!< INTERRSTAT1 (Bit 1) */ +#define GPDMA_INTERRSTAT_INTERRSTAT1_Msk (0x2UL) /*!< INTERRSTAT1 (Bitfield-Mask: 0x01) */ +#define GPDMA_INTERRSTAT_INTERRSTAT2_Pos (2UL) /*!< INTERRSTAT2 (Bit 2) */ +#define GPDMA_INTERRSTAT_INTERRSTAT2_Msk (0x4UL) /*!< INTERRSTAT2 (Bitfield-Mask: 0x01) */ +#define GPDMA_INTERRSTAT_INTERRSTAT3_Pos (3UL) /*!< INTERRSTAT3 (Bit 3) */ +#define GPDMA_INTERRSTAT_INTERRSTAT3_Msk (0x8UL) /*!< INTERRSTAT3 (Bitfield-Mask: 0x01) */ +#define GPDMA_INTERRSTAT_INTERRSTAT4_Pos (4UL) /*!< INTERRSTAT4 (Bit 4) */ +#define GPDMA_INTERRSTAT_INTERRSTAT4_Msk (0x10UL) /*!< INTERRSTAT4 (Bitfield-Mask: 0x01) */ +#define GPDMA_INTERRSTAT_INTERRSTAT5_Pos (5UL) /*!< INTERRSTAT5 (Bit 5) */ +#define GPDMA_INTERRSTAT_INTERRSTAT5_Msk (0x20UL) /*!< INTERRSTAT5 (Bitfield-Mask: 0x01) */ +#define GPDMA_INTERRSTAT_INTERRSTAT6_Pos (6UL) /*!< INTERRSTAT6 (Bit 6) */ +#define GPDMA_INTERRSTAT_INTERRSTAT6_Msk (0x40UL) /*!< INTERRSTAT6 (Bitfield-Mask: 0x01) */ +#define GPDMA_INTERRSTAT_INTERRSTAT7_Pos (7UL) /*!< INTERRSTAT7 (Bit 7) */ +#define GPDMA_INTERRSTAT_INTERRSTAT7_Msk (0x80UL) /*!< INTERRSTAT7 (Bitfield-Mask: 0x01) */ +/* ======================================================= INTERRCLR ======================================================= */ +#define GPDMA_INTERRCLR_INTERRCLR0_Pos (0UL) /*!< INTERRCLR0 (Bit 0) */ +#define GPDMA_INTERRCLR_INTERRCLR0_Msk (0x1UL) /*!< INTERRCLR0 (Bitfield-Mask: 0x01) */ +#define GPDMA_INTERRCLR_INTERRCLR1_Pos (1UL) /*!< INTERRCLR1 (Bit 1) */ +#define GPDMA_INTERRCLR_INTERRCLR1_Msk (0x2UL) /*!< INTERRCLR1 (Bitfield-Mask: 0x01) */ +#define GPDMA_INTERRCLR_INTERRCLR2_Pos (2UL) /*!< INTERRCLR2 (Bit 2) */ +#define GPDMA_INTERRCLR_INTERRCLR2_Msk (0x4UL) /*!< INTERRCLR2 (Bitfield-Mask: 0x01) */ +#define GPDMA_INTERRCLR_INTERRCLR3_Pos (3UL) /*!< INTERRCLR3 (Bit 3) */ +#define GPDMA_INTERRCLR_INTERRCLR3_Msk (0x8UL) /*!< INTERRCLR3 (Bitfield-Mask: 0x01) */ +#define GPDMA_INTERRCLR_INTERRCLR4_Pos (4UL) /*!< INTERRCLR4 (Bit 4) */ +#define GPDMA_INTERRCLR_INTERRCLR4_Msk (0x10UL) /*!< INTERRCLR4 (Bitfield-Mask: 0x01) */ +#define GPDMA_INTERRCLR_INTERRCLR5_Pos (5UL) /*!< INTERRCLR5 (Bit 5) */ +#define GPDMA_INTERRCLR_INTERRCLR5_Msk (0x20UL) /*!< INTERRCLR5 (Bitfield-Mask: 0x01) */ +#define GPDMA_INTERRCLR_INTERRCLR6_Pos (6UL) /*!< INTERRCLR6 (Bit 6) */ +#define GPDMA_INTERRCLR_INTERRCLR6_Msk (0x40UL) /*!< INTERRCLR6 (Bitfield-Mask: 0x01) */ +#define GPDMA_INTERRCLR_INTERRCLR7_Pos (7UL) /*!< INTERRCLR7 (Bit 7) */ +#define GPDMA_INTERRCLR_INTERRCLR7_Msk (0x80UL) /*!< INTERRCLR7 (Bitfield-Mask: 0x01) */ +/* ===================================================== RAWINTTCSTAT ====================================================== */ +#define GPDMA_RAWINTTCSTAT_RAWINTTCSTAT0_Pos (0UL) /*!< RAWINTTCSTAT0 (Bit 0) */ +#define GPDMA_RAWINTTCSTAT_RAWINTTCSTAT0_Msk (0x1UL) /*!< RAWINTTCSTAT0 (Bitfield-Mask: 0x01) */ +#define GPDMA_RAWINTTCSTAT_RAWINTTCSTAT1_Pos (1UL) /*!< RAWINTTCSTAT1 (Bit 1) */ +#define GPDMA_RAWINTTCSTAT_RAWINTTCSTAT1_Msk (0x2UL) /*!< RAWINTTCSTAT1 (Bitfield-Mask: 0x01) */ +#define GPDMA_RAWINTTCSTAT_RAWINTTCSTAT2_Pos (2UL) /*!< RAWINTTCSTAT2 (Bit 2) */ +#define GPDMA_RAWINTTCSTAT_RAWINTTCSTAT2_Msk (0x4UL) /*!< RAWINTTCSTAT2 (Bitfield-Mask: 0x01) */ +#define GPDMA_RAWINTTCSTAT_RAWINTTCSTAT3_Pos (3UL) /*!< RAWINTTCSTAT3 (Bit 3) */ +#define GPDMA_RAWINTTCSTAT_RAWINTTCSTAT3_Msk (0x8UL) /*!< RAWINTTCSTAT3 (Bitfield-Mask: 0x01) */ +#define GPDMA_RAWINTTCSTAT_RAWINTTCSTAT4_Pos (4UL) /*!< RAWINTTCSTAT4 (Bit 4) */ +#define GPDMA_RAWINTTCSTAT_RAWINTTCSTAT4_Msk (0x10UL) /*!< RAWINTTCSTAT4 (Bitfield-Mask: 0x01) */ +#define GPDMA_RAWINTTCSTAT_RAWINTTCSTAT5_Pos (5UL) /*!< RAWINTTCSTAT5 (Bit 5) */ +#define GPDMA_RAWINTTCSTAT_RAWINTTCSTAT5_Msk (0x20UL) /*!< RAWINTTCSTAT5 (Bitfield-Mask: 0x01) */ +#define GPDMA_RAWINTTCSTAT_RAWINTTCSTAT6_Pos (6UL) /*!< RAWINTTCSTAT6 (Bit 6) */ +#define GPDMA_RAWINTTCSTAT_RAWINTTCSTAT6_Msk (0x40UL) /*!< RAWINTTCSTAT6 (Bitfield-Mask: 0x01) */ +#define GPDMA_RAWINTTCSTAT_RAWINTTCSTAT7_Pos (7UL) /*!< RAWINTTCSTAT7 (Bit 7) */ +#define GPDMA_RAWINTTCSTAT_RAWINTTCSTAT7_Msk (0x80UL) /*!< RAWINTTCSTAT7 (Bitfield-Mask: 0x01) */ +/* ===================================================== RAWINTERRSTAT ===================================================== */ +#define GPDMA_RAWINTERRSTAT_RAWINTERRSTAT0_Pos (0UL) /*!< RAWINTERRSTAT0 (Bit 0) */ +#define GPDMA_RAWINTERRSTAT_RAWINTERRSTAT0_Msk (0x1UL) /*!< RAWINTERRSTAT0 (Bitfield-Mask: 0x01) */ +#define GPDMA_RAWINTERRSTAT_RAWINTERRSTAT1_Pos (1UL) /*!< RAWINTERRSTAT1 (Bit 1) */ +#define GPDMA_RAWINTERRSTAT_RAWINTERRSTAT1_Msk (0x2UL) /*!< RAWINTERRSTAT1 (Bitfield-Mask: 0x01) */ +#define GPDMA_RAWINTERRSTAT_RAWINTERRSTAT2_Pos (2UL) /*!< RAWINTERRSTAT2 (Bit 2) */ +#define GPDMA_RAWINTERRSTAT_RAWINTERRSTAT2_Msk (0x4UL) /*!< RAWINTERRSTAT2 (Bitfield-Mask: 0x01) */ +#define GPDMA_RAWINTERRSTAT_RAWINTERRSTAT3_Pos (3UL) /*!< RAWINTERRSTAT3 (Bit 3) */ +#define GPDMA_RAWINTERRSTAT_RAWINTERRSTAT3_Msk (0x8UL) /*!< RAWINTERRSTAT3 (Bitfield-Mask: 0x01) */ +#define GPDMA_RAWINTERRSTAT_RAWINTERRSTAT4_Pos (4UL) /*!< RAWINTERRSTAT4 (Bit 4) */ +#define GPDMA_RAWINTERRSTAT_RAWINTERRSTAT4_Msk (0x10UL) /*!< RAWINTERRSTAT4 (Bitfield-Mask: 0x01) */ +#define GPDMA_RAWINTERRSTAT_RAWINTERRSTAT5_Pos (5UL) /*!< RAWINTERRSTAT5 (Bit 5) */ +#define GPDMA_RAWINTERRSTAT_RAWINTERRSTAT5_Msk (0x20UL) /*!< RAWINTERRSTAT5 (Bitfield-Mask: 0x01) */ +#define GPDMA_RAWINTERRSTAT_RAWINTERRSTAT6_Pos (6UL) /*!< RAWINTERRSTAT6 (Bit 6) */ +#define GPDMA_RAWINTERRSTAT_RAWINTERRSTAT6_Msk (0x40UL) /*!< RAWINTERRSTAT6 (Bitfield-Mask: 0x01) */ +#define GPDMA_RAWINTERRSTAT_RAWINTERRSTAT7_Pos (7UL) /*!< RAWINTERRSTAT7 (Bit 7) */ +#define GPDMA_RAWINTERRSTAT_RAWINTERRSTAT7_Msk (0x80UL) /*!< RAWINTERRSTAT7 (Bitfield-Mask: 0x01) */ +/* ======================================================= ENBLDCHNS ======================================================= */ +#define GPDMA_ENBLDCHNS_ENABLEDCHANNELS0_Pos (0UL) /*!< ENABLEDCHANNELS0 (Bit 0) */ +#define GPDMA_ENBLDCHNS_ENABLEDCHANNELS0_Msk (0x1UL) /*!< ENABLEDCHANNELS0 (Bitfield-Mask: 0x01) */ +#define GPDMA_ENBLDCHNS_ENABLEDCHANNELS1_Pos (1UL) /*!< ENABLEDCHANNELS1 (Bit 1) */ +#define GPDMA_ENBLDCHNS_ENABLEDCHANNELS1_Msk (0x2UL) /*!< ENABLEDCHANNELS1 (Bitfield-Mask: 0x01) */ +#define GPDMA_ENBLDCHNS_ENABLEDCHANNELS2_Pos (2UL) /*!< ENABLEDCHANNELS2 (Bit 2) */ +#define GPDMA_ENBLDCHNS_ENABLEDCHANNELS2_Msk (0x4UL) /*!< ENABLEDCHANNELS2 (Bitfield-Mask: 0x01) */ +#define GPDMA_ENBLDCHNS_ENABLEDCHANNELS3_Pos (3UL) /*!< ENABLEDCHANNELS3 (Bit 3) */ +#define GPDMA_ENBLDCHNS_ENABLEDCHANNELS3_Msk (0x8UL) /*!< ENABLEDCHANNELS3 (Bitfield-Mask: 0x01) */ +#define GPDMA_ENBLDCHNS_ENABLEDCHANNELS4_Pos (4UL) /*!< ENABLEDCHANNELS4 (Bit 4) */ +#define GPDMA_ENBLDCHNS_ENABLEDCHANNELS4_Msk (0x10UL) /*!< ENABLEDCHANNELS4 (Bitfield-Mask: 0x01) */ +#define GPDMA_ENBLDCHNS_ENABLEDCHANNELS5_Pos (5UL) /*!< ENABLEDCHANNELS5 (Bit 5) */ +#define GPDMA_ENBLDCHNS_ENABLEDCHANNELS5_Msk (0x20UL) /*!< ENABLEDCHANNELS5 (Bitfield-Mask: 0x01) */ +#define GPDMA_ENBLDCHNS_ENABLEDCHANNELS6_Pos (6UL) /*!< ENABLEDCHANNELS6 (Bit 6) */ +#define GPDMA_ENBLDCHNS_ENABLEDCHANNELS6_Msk (0x40UL) /*!< ENABLEDCHANNELS6 (Bitfield-Mask: 0x01) */ +#define GPDMA_ENBLDCHNS_ENABLEDCHANNELS7_Pos (7UL) /*!< ENABLEDCHANNELS7 (Bit 7) */ +#define GPDMA_ENBLDCHNS_ENABLEDCHANNELS7_Msk (0x80UL) /*!< ENABLEDCHANNELS7 (Bitfield-Mask: 0x01) */ +/* ======================================================= SOFTBREQ ======================================================== */ +#define GPDMA_SOFTBREQ_SOFTBREQ0_Pos (0UL) /*!< SOFTBREQ0 (Bit 0) */ +#define GPDMA_SOFTBREQ_SOFTBREQ0_Msk (0x1UL) /*!< SOFTBREQ0 (Bitfield-Mask: 0x01) */ +#define GPDMA_SOFTBREQ_SOFTBREQ1_Pos (1UL) /*!< SOFTBREQ1 (Bit 1) */ +#define GPDMA_SOFTBREQ_SOFTBREQ1_Msk (0x2UL) /*!< SOFTBREQ1 (Bitfield-Mask: 0x01) */ +#define GPDMA_SOFTBREQ_SOFTBREQ2_Pos (2UL) /*!< SOFTBREQ2 (Bit 2) */ +#define GPDMA_SOFTBREQ_SOFTBREQ2_Msk (0x4UL) /*!< SOFTBREQ2 (Bitfield-Mask: 0x01) */ +#define GPDMA_SOFTBREQ_SOFTBREQ3_Pos (3UL) /*!< SOFTBREQ3 (Bit 3) */ +#define GPDMA_SOFTBREQ_SOFTBREQ3_Msk (0x8UL) /*!< SOFTBREQ3 (Bitfield-Mask: 0x01) */ +#define GPDMA_SOFTBREQ_SOFTBREQ4_Pos (4UL) /*!< SOFTBREQ4 (Bit 4) */ +#define GPDMA_SOFTBREQ_SOFTBREQ4_Msk (0x10UL) /*!< SOFTBREQ4 (Bitfield-Mask: 0x01) */ +#define GPDMA_SOFTBREQ_SOFTBREQ5_Pos (5UL) /*!< SOFTBREQ5 (Bit 5) */ +#define GPDMA_SOFTBREQ_SOFTBREQ5_Msk (0x20UL) /*!< SOFTBREQ5 (Bitfield-Mask: 0x01) */ +#define GPDMA_SOFTBREQ_SOFTBREQ6_Pos (6UL) /*!< SOFTBREQ6 (Bit 6) */ +#define GPDMA_SOFTBREQ_SOFTBREQ6_Msk (0x40UL) /*!< SOFTBREQ6 (Bitfield-Mask: 0x01) */ +#define GPDMA_SOFTBREQ_SOFTBREQ7_Pos (7UL) /*!< SOFTBREQ7 (Bit 7) */ +#define GPDMA_SOFTBREQ_SOFTBREQ7_Msk (0x80UL) /*!< SOFTBREQ7 (Bitfield-Mask: 0x01) */ +#define GPDMA_SOFTBREQ_SOFTBREQ8_Pos (8UL) /*!< SOFTBREQ8 (Bit 8) */ +#define GPDMA_SOFTBREQ_SOFTBREQ8_Msk (0x100UL) /*!< SOFTBREQ8 (Bitfield-Mask: 0x01) */ +#define GPDMA_SOFTBREQ_SOFTBREQ9_Pos (9UL) /*!< SOFTBREQ9 (Bit 9) */ +#define GPDMA_SOFTBREQ_SOFTBREQ9_Msk (0x200UL) /*!< SOFTBREQ9 (Bitfield-Mask: 0x01) */ +#define GPDMA_SOFTBREQ_SOFTBREQ10_Pos (10UL) /*!< SOFTBREQ10 (Bit 10) */ +#define GPDMA_SOFTBREQ_SOFTBREQ10_Msk (0x400UL) /*!< SOFTBREQ10 (Bitfield-Mask: 0x01) */ +#define GPDMA_SOFTBREQ_SOFTBREQ11_Pos (11UL) /*!< SOFTBREQ11 (Bit 11) */ +#define GPDMA_SOFTBREQ_SOFTBREQ11_Msk (0x800UL) /*!< SOFTBREQ11 (Bitfield-Mask: 0x01) */ +#define GPDMA_SOFTBREQ_SOFTBREQ12_Pos (12UL) /*!< SOFTBREQ12 (Bit 12) */ +#define GPDMA_SOFTBREQ_SOFTBREQ12_Msk (0x1000UL) /*!< SOFTBREQ12 (Bitfield-Mask: 0x01) */ +#define GPDMA_SOFTBREQ_SOFTBREQ13_Pos (13UL) /*!< SOFTBREQ13 (Bit 13) */ +#define GPDMA_SOFTBREQ_SOFTBREQ13_Msk (0x2000UL) /*!< SOFTBREQ13 (Bitfield-Mask: 0x01) */ +#define GPDMA_SOFTBREQ_SOFTBREQ14_Pos (14UL) /*!< SOFTBREQ14 (Bit 14) */ +#define GPDMA_SOFTBREQ_SOFTBREQ14_Msk (0x4000UL) /*!< SOFTBREQ14 (Bitfield-Mask: 0x01) */ +#define GPDMA_SOFTBREQ_SOFTBREQ15_Pos (15UL) /*!< SOFTBREQ15 (Bit 15) */ +#define GPDMA_SOFTBREQ_SOFTBREQ15_Msk (0x8000UL) /*!< SOFTBREQ15 (Bitfield-Mask: 0x01) */ +/* ======================================================= SOFTSREQ ======================================================== */ +#define GPDMA_SOFTSREQ_SOFTSREQ0_Pos (0UL) /*!< SOFTSREQ0 (Bit 0) */ +#define GPDMA_SOFTSREQ_SOFTSREQ0_Msk (0x1UL) /*!< SOFTSREQ0 (Bitfield-Mask: 0x01) */ +#define GPDMA_SOFTSREQ_SOFTSREQ1_Pos (1UL) /*!< SOFTSREQ1 (Bit 1) */ +#define GPDMA_SOFTSREQ_SOFTSREQ1_Msk (0x2UL) /*!< SOFTSREQ1 (Bitfield-Mask: 0x01) */ +#define GPDMA_SOFTSREQ_SOFTSREQ2_Pos (2UL) /*!< SOFTSREQ2 (Bit 2) */ +#define GPDMA_SOFTSREQ_SOFTSREQ2_Msk (0x4UL) /*!< SOFTSREQ2 (Bitfield-Mask: 0x01) */ +#define GPDMA_SOFTSREQ_SOFTSREQ3_Pos (3UL) /*!< SOFTSREQ3 (Bit 3) */ +#define GPDMA_SOFTSREQ_SOFTSREQ3_Msk (0x8UL) /*!< SOFTSREQ3 (Bitfield-Mask: 0x01) */ +#define GPDMA_SOFTSREQ_SOFTSREQ4_Pos (4UL) /*!< SOFTSREQ4 (Bit 4) */ +#define GPDMA_SOFTSREQ_SOFTSREQ4_Msk (0x10UL) /*!< SOFTSREQ4 (Bitfield-Mask: 0x01) */ +#define GPDMA_SOFTSREQ_SOFTSREQ5_Pos (5UL) /*!< SOFTSREQ5 (Bit 5) */ +#define GPDMA_SOFTSREQ_SOFTSREQ5_Msk (0x20UL) /*!< SOFTSREQ5 (Bitfield-Mask: 0x01) */ +#define GPDMA_SOFTSREQ_SOFTSREQ6_Pos (6UL) /*!< SOFTSREQ6 (Bit 6) */ +#define GPDMA_SOFTSREQ_SOFTSREQ6_Msk (0x40UL) /*!< SOFTSREQ6 (Bitfield-Mask: 0x01) */ +#define GPDMA_SOFTSREQ_SOFTSREQ7_Pos (7UL) /*!< SOFTSREQ7 (Bit 7) */ +#define GPDMA_SOFTSREQ_SOFTSREQ7_Msk (0x80UL) /*!< SOFTSREQ7 (Bitfield-Mask: 0x01) */ +#define GPDMA_SOFTSREQ_SOFTSREQ8_Pos (8UL) /*!< SOFTSREQ8 (Bit 8) */ +#define GPDMA_SOFTSREQ_SOFTSREQ8_Msk (0x100UL) /*!< SOFTSREQ8 (Bitfield-Mask: 0x01) */ +#define GPDMA_SOFTSREQ_SOFTSREQ9_Pos (9UL) /*!< SOFTSREQ9 (Bit 9) */ +#define GPDMA_SOFTSREQ_SOFTSREQ9_Msk (0x200UL) /*!< SOFTSREQ9 (Bitfield-Mask: 0x01) */ +#define GPDMA_SOFTSREQ_SOFTSREQ10_Pos (10UL) /*!< SOFTSREQ10 (Bit 10) */ +#define GPDMA_SOFTSREQ_SOFTSREQ10_Msk (0x400UL) /*!< SOFTSREQ10 (Bitfield-Mask: 0x01) */ +#define GPDMA_SOFTSREQ_SOFTSREQ11_Pos (11UL) /*!< SOFTSREQ11 (Bit 11) */ +#define GPDMA_SOFTSREQ_SOFTSREQ11_Msk (0x800UL) /*!< SOFTSREQ11 (Bitfield-Mask: 0x01) */ +#define GPDMA_SOFTSREQ_SOFTSREQ12_Pos (12UL) /*!< SOFTSREQ12 (Bit 12) */ +#define GPDMA_SOFTSREQ_SOFTSREQ12_Msk (0x1000UL) /*!< SOFTSREQ12 (Bitfield-Mask: 0x01) */ +#define GPDMA_SOFTSREQ_SOFTSREQ13_Pos (13UL) /*!< SOFTSREQ13 (Bit 13) */ +#define GPDMA_SOFTSREQ_SOFTSREQ13_Msk (0x2000UL) /*!< SOFTSREQ13 (Bitfield-Mask: 0x01) */ +#define GPDMA_SOFTSREQ_SOFTSREQ14_Pos (14UL) /*!< SOFTSREQ14 (Bit 14) */ +#define GPDMA_SOFTSREQ_SOFTSREQ14_Msk (0x4000UL) /*!< SOFTSREQ14 (Bitfield-Mask: 0x01) */ +#define GPDMA_SOFTSREQ_SOFTSREQ15_Pos (15UL) /*!< SOFTSREQ15 (Bit 15) */ +#define GPDMA_SOFTSREQ_SOFTSREQ15_Msk (0x8000UL) /*!< SOFTSREQ15 (Bitfield-Mask: 0x01) */ +/* ======================================================= SOFTLBREQ ======================================================= */ +#define GPDMA_SOFTLBREQ_SOFTLBREQ0_Pos (0UL) /*!< SOFTLBREQ0 (Bit 0) */ +#define GPDMA_SOFTLBREQ_SOFTLBREQ0_Msk (0x1UL) /*!< SOFTLBREQ0 (Bitfield-Mask: 0x01) */ +#define GPDMA_SOFTLBREQ_SOFTLBREQ1_Pos (1UL) /*!< SOFTLBREQ1 (Bit 1) */ +#define GPDMA_SOFTLBREQ_SOFTLBREQ1_Msk (0x2UL) /*!< SOFTLBREQ1 (Bitfield-Mask: 0x01) */ +#define GPDMA_SOFTLBREQ_SOFTLBREQ2_Pos (2UL) /*!< SOFTLBREQ2 (Bit 2) */ +#define GPDMA_SOFTLBREQ_SOFTLBREQ2_Msk (0x4UL) /*!< SOFTLBREQ2 (Bitfield-Mask: 0x01) */ +#define GPDMA_SOFTLBREQ_SOFTLBREQ3_Pos (3UL) /*!< SOFTLBREQ3 (Bit 3) */ +#define GPDMA_SOFTLBREQ_SOFTLBREQ3_Msk (0x8UL) /*!< SOFTLBREQ3 (Bitfield-Mask: 0x01) */ +#define GPDMA_SOFTLBREQ_SOFTLBREQ4_Pos (4UL) /*!< SOFTLBREQ4 (Bit 4) */ +#define GPDMA_SOFTLBREQ_SOFTLBREQ4_Msk (0x10UL) /*!< SOFTLBREQ4 (Bitfield-Mask: 0x01) */ +#define GPDMA_SOFTLBREQ_SOFTLBREQ5_Pos (5UL) /*!< SOFTLBREQ5 (Bit 5) */ +#define GPDMA_SOFTLBREQ_SOFTLBREQ5_Msk (0x20UL) /*!< SOFTLBREQ5 (Bitfield-Mask: 0x01) */ +#define GPDMA_SOFTLBREQ_SOFTLBREQ6_Pos (6UL) /*!< SOFTLBREQ6 (Bit 6) */ +#define GPDMA_SOFTLBREQ_SOFTLBREQ6_Msk (0x40UL) /*!< SOFTLBREQ6 (Bitfield-Mask: 0x01) */ +#define GPDMA_SOFTLBREQ_SOFTLBREQ7_Pos (7UL) /*!< SOFTLBREQ7 (Bit 7) */ +#define GPDMA_SOFTLBREQ_SOFTLBREQ7_Msk (0x80UL) /*!< SOFTLBREQ7 (Bitfield-Mask: 0x01) */ +#define GPDMA_SOFTLBREQ_SOFTLBREQ8_Pos (8UL) /*!< SOFTLBREQ8 (Bit 8) */ +#define GPDMA_SOFTLBREQ_SOFTLBREQ8_Msk (0x100UL) /*!< SOFTLBREQ8 (Bitfield-Mask: 0x01) */ +#define GPDMA_SOFTLBREQ_SOFTLBREQ9_Pos (9UL) /*!< SOFTLBREQ9 (Bit 9) */ +#define GPDMA_SOFTLBREQ_SOFTLBREQ9_Msk (0x200UL) /*!< SOFTLBREQ9 (Bitfield-Mask: 0x01) */ +#define GPDMA_SOFTLBREQ_SOFTLBREQ10_Pos (10UL) /*!< SOFTLBREQ10 (Bit 10) */ +#define GPDMA_SOFTLBREQ_SOFTLBREQ10_Msk (0x400UL) /*!< SOFTLBREQ10 (Bitfield-Mask: 0x01) */ +#define GPDMA_SOFTLBREQ_SOFTLBREQ11_Pos (11UL) /*!< SOFTLBREQ11 (Bit 11) */ +#define GPDMA_SOFTLBREQ_SOFTLBREQ11_Msk (0x800UL) /*!< SOFTLBREQ11 (Bitfield-Mask: 0x01) */ +#define GPDMA_SOFTLBREQ_SOFTLBREQ12_Pos (12UL) /*!< SOFTLBREQ12 (Bit 12) */ +#define GPDMA_SOFTLBREQ_SOFTLBREQ12_Msk (0x1000UL) /*!< SOFTLBREQ12 (Bitfield-Mask: 0x01) */ +#define GPDMA_SOFTLBREQ_SOFTLBREQ13_Pos (13UL) /*!< SOFTLBREQ13 (Bit 13) */ +#define GPDMA_SOFTLBREQ_SOFTLBREQ13_Msk (0x2000UL) /*!< SOFTLBREQ13 (Bitfield-Mask: 0x01) */ +#define GPDMA_SOFTLBREQ_SOFTLBREQ14_Pos (14UL) /*!< SOFTLBREQ14 (Bit 14) */ +#define GPDMA_SOFTLBREQ_SOFTLBREQ14_Msk (0x4000UL) /*!< SOFTLBREQ14 (Bitfield-Mask: 0x01) */ +#define GPDMA_SOFTLBREQ_SOFTLBREQ15_Pos (15UL) /*!< SOFTLBREQ15 (Bit 15) */ +#define GPDMA_SOFTLBREQ_SOFTLBREQ15_Msk (0x8000UL) /*!< SOFTLBREQ15 (Bitfield-Mask: 0x01) */ +/* ======================================================= SOFTLSREQ ======================================================= */ +#define GPDMA_SOFTLSREQ_SOFTLSREQ0_Pos (0UL) /*!< SOFTLSREQ0 (Bit 0) */ +#define GPDMA_SOFTLSREQ_SOFTLSREQ0_Msk (0x1UL) /*!< SOFTLSREQ0 (Bitfield-Mask: 0x01) */ +#define GPDMA_SOFTLSREQ_SOFTLSREQ1_Pos (1UL) /*!< SOFTLSREQ1 (Bit 1) */ +#define GPDMA_SOFTLSREQ_SOFTLSREQ1_Msk (0x2UL) /*!< SOFTLSREQ1 (Bitfield-Mask: 0x01) */ +#define GPDMA_SOFTLSREQ_SOFTLSREQ2_Pos (2UL) /*!< SOFTLSREQ2 (Bit 2) */ +#define GPDMA_SOFTLSREQ_SOFTLSREQ2_Msk (0x4UL) /*!< SOFTLSREQ2 (Bitfield-Mask: 0x01) */ +#define GPDMA_SOFTLSREQ_SOFTLSREQ3_Pos (3UL) /*!< SOFTLSREQ3 (Bit 3) */ +#define GPDMA_SOFTLSREQ_SOFTLSREQ3_Msk (0x8UL) /*!< SOFTLSREQ3 (Bitfield-Mask: 0x01) */ +#define GPDMA_SOFTLSREQ_SOFTLSREQ4_Pos (4UL) /*!< SOFTLSREQ4 (Bit 4) */ +#define GPDMA_SOFTLSREQ_SOFTLSREQ4_Msk (0x10UL) /*!< SOFTLSREQ4 (Bitfield-Mask: 0x01) */ +#define GPDMA_SOFTLSREQ_SOFTLSREQ5_Pos (5UL) /*!< SOFTLSREQ5 (Bit 5) */ +#define GPDMA_SOFTLSREQ_SOFTLSREQ5_Msk (0x20UL) /*!< SOFTLSREQ5 (Bitfield-Mask: 0x01) */ +#define GPDMA_SOFTLSREQ_SOFTLSREQ6_Pos (6UL) /*!< SOFTLSREQ6 (Bit 6) */ +#define GPDMA_SOFTLSREQ_SOFTLSREQ6_Msk (0x40UL) /*!< SOFTLSREQ6 (Bitfield-Mask: 0x01) */ +#define GPDMA_SOFTLSREQ_SOFTLSREQ7_Pos (7UL) /*!< SOFTLSREQ7 (Bit 7) */ +#define GPDMA_SOFTLSREQ_SOFTLSREQ7_Msk (0x80UL) /*!< SOFTLSREQ7 (Bitfield-Mask: 0x01) */ +#define GPDMA_SOFTLSREQ_SOFTLSREQ8_Pos (8UL) /*!< SOFTLSREQ8 (Bit 8) */ +#define GPDMA_SOFTLSREQ_SOFTLSREQ8_Msk (0x100UL) /*!< SOFTLSREQ8 (Bitfield-Mask: 0x01) */ +#define GPDMA_SOFTLSREQ_SOFTLSREQ9_Pos (9UL) /*!< SOFTLSREQ9 (Bit 9) */ +#define GPDMA_SOFTLSREQ_SOFTLSREQ9_Msk (0x200UL) /*!< SOFTLSREQ9 (Bitfield-Mask: 0x01) */ +#define GPDMA_SOFTLSREQ_SOFTLSREQ10_Pos (10UL) /*!< SOFTLSREQ10 (Bit 10) */ +#define GPDMA_SOFTLSREQ_SOFTLSREQ10_Msk (0x400UL) /*!< SOFTLSREQ10 (Bitfield-Mask: 0x01) */ +#define GPDMA_SOFTLSREQ_SOFTLSREQ11_Pos (11UL) /*!< SOFTLSREQ11 (Bit 11) */ +#define GPDMA_SOFTLSREQ_SOFTLSREQ11_Msk (0x800UL) /*!< SOFTLSREQ11 (Bitfield-Mask: 0x01) */ +#define GPDMA_SOFTLSREQ_SOFTLSREQ12_Pos (12UL) /*!< SOFTLSREQ12 (Bit 12) */ +#define GPDMA_SOFTLSREQ_SOFTLSREQ12_Msk (0x1000UL) /*!< SOFTLSREQ12 (Bitfield-Mask: 0x01) */ +#define GPDMA_SOFTLSREQ_SOFTLSREQ13_Pos (13UL) /*!< SOFTLSREQ13 (Bit 13) */ +#define GPDMA_SOFTLSREQ_SOFTLSREQ13_Msk (0x2000UL) /*!< SOFTLSREQ13 (Bitfield-Mask: 0x01) */ +#define GPDMA_SOFTLSREQ_SOFTLSREQ14_Pos (14UL) /*!< SOFTLSREQ14 (Bit 14) */ +#define GPDMA_SOFTLSREQ_SOFTLSREQ14_Msk (0x4000UL) /*!< SOFTLSREQ14 (Bitfield-Mask: 0x01) */ +#define GPDMA_SOFTLSREQ_SOFTLSREQ15_Pos (15UL) /*!< SOFTLSREQ15 (Bit 15) */ +#define GPDMA_SOFTLSREQ_SOFTLSREQ15_Msk (0x8000UL) /*!< SOFTLSREQ15 (Bitfield-Mask: 0x01) */ +/* ======================================================== CONFIG ========================================================= */ +#define GPDMA_CONFIG_E_Pos (0UL) /*!< E (Bit 0) */ +#define GPDMA_CONFIG_E_Msk (0x1UL) /*!< E (Bitfield-Mask: 0x01) */ +#define GPDMA_CONFIG_M_Pos (1UL) /*!< M (Bit 1) */ +#define GPDMA_CONFIG_M_Msk (0x2UL) /*!< M (Bitfield-Mask: 0x01) */ +/* ========================================================= SYNC ========================================================== */ +#define GPDMA_SYNC_DMACSYNC0_Pos (0UL) /*!< DMACSYNC0 (Bit 0) */ +#define GPDMA_SYNC_DMACSYNC0_Msk (0x1UL) /*!< DMACSYNC0 (Bitfield-Mask: 0x01) */ +#define GPDMA_SYNC_DMACSYNC1_Pos (1UL) /*!< DMACSYNC1 (Bit 1) */ +#define GPDMA_SYNC_DMACSYNC1_Msk (0x2UL) /*!< DMACSYNC1 (Bitfield-Mask: 0x01) */ +#define GPDMA_SYNC_DMACSYNC2_Pos (2UL) /*!< DMACSYNC2 (Bit 2) */ +#define GPDMA_SYNC_DMACSYNC2_Msk (0x4UL) /*!< DMACSYNC2 (Bitfield-Mask: 0x01) */ +#define GPDMA_SYNC_DMACSYNC3_Pos (3UL) /*!< DMACSYNC3 (Bit 3) */ +#define GPDMA_SYNC_DMACSYNC3_Msk (0x8UL) /*!< DMACSYNC3 (Bitfield-Mask: 0x01) */ +#define GPDMA_SYNC_DMACSYNC4_Pos (4UL) /*!< DMACSYNC4 (Bit 4) */ +#define GPDMA_SYNC_DMACSYNC4_Msk (0x10UL) /*!< DMACSYNC4 (Bitfield-Mask: 0x01) */ +#define GPDMA_SYNC_DMACSYNC5_Pos (5UL) /*!< DMACSYNC5 (Bit 5) */ +#define GPDMA_SYNC_DMACSYNC5_Msk (0x20UL) /*!< DMACSYNC5 (Bitfield-Mask: 0x01) */ +#define GPDMA_SYNC_DMACSYNC6_Pos (6UL) /*!< DMACSYNC6 (Bit 6) */ +#define GPDMA_SYNC_DMACSYNC6_Msk (0x40UL) /*!< DMACSYNC6 (Bitfield-Mask: 0x01) */ +#define GPDMA_SYNC_DMACSYNC7_Pos (7UL) /*!< DMACSYNC7 (Bit 7) */ +#define GPDMA_SYNC_DMACSYNC7_Msk (0x80UL) /*!< DMACSYNC7 (Bitfield-Mask: 0x01) */ +#define GPDMA_SYNC_DMACSYNC8_Pos (8UL) /*!< DMACSYNC8 (Bit 8) */ +#define GPDMA_SYNC_DMACSYNC8_Msk (0x100UL) /*!< DMACSYNC8 (Bitfield-Mask: 0x01) */ +#define GPDMA_SYNC_DMACSYNC9_Pos (9UL) /*!< DMACSYNC9 (Bit 9) */ +#define GPDMA_SYNC_DMACSYNC9_Msk (0x200UL) /*!< DMACSYNC9 (Bitfield-Mask: 0x01) */ +#define GPDMA_SYNC_DMACSYNC10_Pos (10UL) /*!< DMACSYNC10 (Bit 10) */ +#define GPDMA_SYNC_DMACSYNC10_Msk (0x400UL) /*!< DMACSYNC10 (Bitfield-Mask: 0x01) */ +#define GPDMA_SYNC_DMACSYNC11_Pos (11UL) /*!< DMACSYNC11 (Bit 11) */ +#define GPDMA_SYNC_DMACSYNC11_Msk (0x800UL) /*!< DMACSYNC11 (Bitfield-Mask: 0x01) */ +#define GPDMA_SYNC_DMACSYNC12_Pos (12UL) /*!< DMACSYNC12 (Bit 12) */ +#define GPDMA_SYNC_DMACSYNC12_Msk (0x1000UL) /*!< DMACSYNC12 (Bitfield-Mask: 0x01) */ +#define GPDMA_SYNC_DMACSYNC13_Pos (13UL) /*!< DMACSYNC13 (Bit 13) */ +#define GPDMA_SYNC_DMACSYNC13_Msk (0x2000UL) /*!< DMACSYNC13 (Bitfield-Mask: 0x01) */ +#define GPDMA_SYNC_DMACSYNC14_Pos (14UL) /*!< DMACSYNC14 (Bit 14) */ +#define GPDMA_SYNC_DMACSYNC14_Msk (0x4000UL) /*!< DMACSYNC14 (Bitfield-Mask: 0x01) */ +#define GPDMA_SYNC_DMACSYNC15_Pos (15UL) /*!< DMACSYNC15 (Bit 15) */ +#define GPDMA_SYNC_DMACSYNC15_Msk (0x8000UL) /*!< DMACSYNC15 (Bitfield-Mask: 0x01) */ +/* ======================================================= SRCADDR0 ======================================================== */ +#define GPDMA_SRCADDR0_SRCADDR_Pos (0UL) /*!< SRCADDR (Bit 0) */ +#define GPDMA_SRCADDR0_SRCADDR_Msk (0xffffffffUL) /*!< SRCADDR (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= SRCADDR1 ======================================================== */ +#define GPDMA_SRCADDR1_SRCADDR_Pos (0UL) /*!< SRCADDR (Bit 0) */ +#define GPDMA_SRCADDR1_SRCADDR_Msk (0xffffffffUL) /*!< SRCADDR (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= SRCADDR2 ======================================================== */ +#define GPDMA_SRCADDR2_SRCADDR_Pos (0UL) /*!< SRCADDR (Bit 0) */ +#define GPDMA_SRCADDR2_SRCADDR_Msk (0xffffffffUL) /*!< SRCADDR (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= SRCADDR3 ======================================================== */ +#define GPDMA_SRCADDR3_SRCADDR_Pos (0UL) /*!< SRCADDR (Bit 0) */ +#define GPDMA_SRCADDR3_SRCADDR_Msk (0xffffffffUL) /*!< SRCADDR (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= SRCADDR4 ======================================================== */ +#define GPDMA_SRCADDR4_SRCADDR_Pos (0UL) /*!< SRCADDR (Bit 0) */ +#define GPDMA_SRCADDR4_SRCADDR_Msk (0xffffffffUL) /*!< SRCADDR (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= SRCADDR5 ======================================================== */ +#define GPDMA_SRCADDR5_SRCADDR_Pos (0UL) /*!< SRCADDR (Bit 0) */ +#define GPDMA_SRCADDR5_SRCADDR_Msk (0xffffffffUL) /*!< SRCADDR (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= SRCADDR6 ======================================================== */ +#define GPDMA_SRCADDR6_SRCADDR_Pos (0UL) /*!< SRCADDR (Bit 0) */ +#define GPDMA_SRCADDR6_SRCADDR_Msk (0xffffffffUL) /*!< SRCADDR (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= SRCADDR7 ======================================================== */ +#define GPDMA_SRCADDR7_SRCADDR_Pos (0UL) /*!< SRCADDR (Bit 0) */ +#define GPDMA_SRCADDR7_SRCADDR_Msk (0xffffffffUL) /*!< SRCADDR (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= DESTADDR0 ======================================================= */ +#define GPDMA_DESTADDR0_DESTADDR_Pos (0UL) /*!< DESTADDR (Bit 0) */ +#define GPDMA_DESTADDR0_DESTADDR_Msk (0xffffffffUL) /*!< DESTADDR (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= DESTADDR1 ======================================================= */ +#define GPDMA_DESTADDR1_DESTADDR_Pos (0UL) /*!< DESTADDR (Bit 0) */ +#define GPDMA_DESTADDR1_DESTADDR_Msk (0xffffffffUL) /*!< DESTADDR (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= DESTADDR2 ======================================================= */ +#define GPDMA_DESTADDR2_DESTADDR_Pos (0UL) /*!< DESTADDR (Bit 0) */ +#define GPDMA_DESTADDR2_DESTADDR_Msk (0xffffffffUL) /*!< DESTADDR (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= DESTADDR3 ======================================================= */ +#define GPDMA_DESTADDR3_DESTADDR_Pos (0UL) /*!< DESTADDR (Bit 0) */ +#define GPDMA_DESTADDR3_DESTADDR_Msk (0xffffffffUL) /*!< DESTADDR (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= DESTADDR4 ======================================================= */ +#define GPDMA_DESTADDR4_DESTADDR_Pos (0UL) /*!< DESTADDR (Bit 0) */ +#define GPDMA_DESTADDR4_DESTADDR_Msk (0xffffffffUL) /*!< DESTADDR (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= DESTADDR5 ======================================================= */ +#define GPDMA_DESTADDR5_DESTADDR_Pos (0UL) /*!< DESTADDR (Bit 0) */ +#define GPDMA_DESTADDR5_DESTADDR_Msk (0xffffffffUL) /*!< DESTADDR (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= DESTADDR6 ======================================================= */ +#define GPDMA_DESTADDR6_DESTADDR_Pos (0UL) /*!< DESTADDR (Bit 0) */ +#define GPDMA_DESTADDR6_DESTADDR_Msk (0xffffffffUL) /*!< DESTADDR (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= DESTADDR7 ======================================================= */ +#define GPDMA_DESTADDR7_DESTADDR_Pos (0UL) /*!< DESTADDR (Bit 0) */ +#define GPDMA_DESTADDR7_DESTADDR_Msk (0xffffffffUL) /*!< DESTADDR (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= LLI0 ========================================================== */ +#define GPDMA_LLI0_LLI_Pos (2UL) /*!< LLI (Bit 2) */ +#define GPDMA_LLI0_LLI_Msk (0xfffffffcUL) /*!< LLI (Bitfield-Mask: 0x3fffffff) */ +/* ========================================================= LLI1 ========================================================== */ +#define GPDMA_LLI1_LLI_Pos (2UL) /*!< LLI (Bit 2) */ +#define GPDMA_LLI1_LLI_Msk (0xfffffffcUL) /*!< LLI (Bitfield-Mask: 0x3fffffff) */ +/* ========================================================= LLI2 ========================================================== */ +#define GPDMA_LLI2_LLI_Pos (2UL) /*!< LLI (Bit 2) */ +#define GPDMA_LLI2_LLI_Msk (0xfffffffcUL) /*!< LLI (Bitfield-Mask: 0x3fffffff) */ +/* ========================================================= LLI3 ========================================================== */ +#define GPDMA_LLI3_LLI_Pos (2UL) /*!< LLI (Bit 2) */ +#define GPDMA_LLI3_LLI_Msk (0xfffffffcUL) /*!< LLI (Bitfield-Mask: 0x3fffffff) */ +/* ========================================================= LLI4 ========================================================== */ +#define GPDMA_LLI4_LLI_Pos (2UL) /*!< LLI (Bit 2) */ +#define GPDMA_LLI4_LLI_Msk (0xfffffffcUL) /*!< LLI (Bitfield-Mask: 0x3fffffff) */ +/* ========================================================= LLI5 ========================================================== */ +#define GPDMA_LLI5_LLI_Pos (2UL) /*!< LLI (Bit 2) */ +#define GPDMA_LLI5_LLI_Msk (0xfffffffcUL) /*!< LLI (Bitfield-Mask: 0x3fffffff) */ +/* ========================================================= LLI6 ========================================================== */ +#define GPDMA_LLI6_LLI_Pos (2UL) /*!< LLI (Bit 2) */ +#define GPDMA_LLI6_LLI_Msk (0xfffffffcUL) /*!< LLI (Bitfield-Mask: 0x3fffffff) */ +/* ========================================================= LLI7 ========================================================== */ +#define GPDMA_LLI7_LLI_Pos (2UL) /*!< LLI (Bit 2) */ +#define GPDMA_LLI7_LLI_Msk (0xfffffffcUL) /*!< LLI (Bitfield-Mask: 0x3fffffff) */ +/* ======================================================= CONTROL0 ======================================================== */ +#define GPDMA_CONTROL0_TRANSFERSIZE_Pos (0UL) /*!< TRANSFERSIZE (Bit 0) */ +#define GPDMA_CONTROL0_TRANSFERSIZE_Msk (0xfffUL) /*!< TRANSFERSIZE (Bitfield-Mask: 0xfff) */ +#define GPDMA_CONTROL0_SBSIZE_Pos (12UL) /*!< SBSIZE (Bit 12) */ +#define GPDMA_CONTROL0_SBSIZE_Msk (0x7000UL) /*!< SBSIZE (Bitfield-Mask: 0x07) */ +#define GPDMA_CONTROL0_DBSIZE_Pos (15UL) /*!< DBSIZE (Bit 15) */ +#define GPDMA_CONTROL0_DBSIZE_Msk (0x38000UL) /*!< DBSIZE (Bitfield-Mask: 0x07) */ +#define GPDMA_CONTROL0_SWIDTH_Pos (18UL) /*!< SWIDTH (Bit 18) */ +#define GPDMA_CONTROL0_SWIDTH_Msk (0x1c0000UL) /*!< SWIDTH (Bitfield-Mask: 0x07) */ +#define GPDMA_CONTROL0_DWIDTH_Pos (21UL) /*!< DWIDTH (Bit 21) */ +#define GPDMA_CONTROL0_DWIDTH_Msk (0xe00000UL) /*!< DWIDTH (Bitfield-Mask: 0x07) */ +#define GPDMA_CONTROL0_SI_Pos (26UL) /*!< SI (Bit 26) */ +#define GPDMA_CONTROL0_SI_Msk (0x4000000UL) /*!< SI (Bitfield-Mask: 0x01) */ +#define GPDMA_CONTROL0_DI_Pos (27UL) /*!< DI (Bit 27) */ +#define GPDMA_CONTROL0_DI_Msk (0x8000000UL) /*!< DI (Bitfield-Mask: 0x01) */ +#define GPDMA_CONTROL0_PROT1_Pos (28UL) /*!< PROT1 (Bit 28) */ +#define GPDMA_CONTROL0_PROT1_Msk (0x10000000UL) /*!< PROT1 (Bitfield-Mask: 0x01) */ +#define GPDMA_CONTROL0_PROT2_Pos (29UL) /*!< PROT2 (Bit 29) */ +#define GPDMA_CONTROL0_PROT2_Msk (0x20000000UL) /*!< PROT2 (Bitfield-Mask: 0x01) */ +#define GPDMA_CONTROL0_PROT3_Pos (30UL) /*!< PROT3 (Bit 30) */ +#define GPDMA_CONTROL0_PROT3_Msk (0x40000000UL) /*!< PROT3 (Bitfield-Mask: 0x01) */ +#define GPDMA_CONTROL0_I_Pos (31UL) /*!< I (Bit 31) */ +#define GPDMA_CONTROL0_I_Msk (0x80000000UL) /*!< I (Bitfield-Mask: 0x01) */ +/* ======================================================= CONTROL1 ======================================================== */ +#define GPDMA_CONTROL1_TRANSFERSIZE_Pos (0UL) /*!< TRANSFERSIZE (Bit 0) */ +#define GPDMA_CONTROL1_TRANSFERSIZE_Msk (0xfffUL) /*!< TRANSFERSIZE (Bitfield-Mask: 0xfff) */ +#define GPDMA_CONTROL1_SBSIZE_Pos (12UL) /*!< SBSIZE (Bit 12) */ +#define GPDMA_CONTROL1_SBSIZE_Msk (0x7000UL) /*!< SBSIZE (Bitfield-Mask: 0x07) */ +#define GPDMA_CONTROL1_DBSIZE_Pos (15UL) /*!< DBSIZE (Bit 15) */ +#define GPDMA_CONTROL1_DBSIZE_Msk (0x38000UL) /*!< DBSIZE (Bitfield-Mask: 0x07) */ +#define GPDMA_CONTROL1_SWIDTH_Pos (18UL) /*!< SWIDTH (Bit 18) */ +#define GPDMA_CONTROL1_SWIDTH_Msk (0x1c0000UL) /*!< SWIDTH (Bitfield-Mask: 0x07) */ +#define GPDMA_CONTROL1_DWIDTH_Pos (21UL) /*!< DWIDTH (Bit 21) */ +#define GPDMA_CONTROL1_DWIDTH_Msk (0xe00000UL) /*!< DWIDTH (Bitfield-Mask: 0x07) */ +#define GPDMA_CONTROL1_SI_Pos (26UL) /*!< SI (Bit 26) */ +#define GPDMA_CONTROL1_SI_Msk (0x4000000UL) /*!< SI (Bitfield-Mask: 0x01) */ +#define GPDMA_CONTROL1_DI_Pos (27UL) /*!< DI (Bit 27) */ +#define GPDMA_CONTROL1_DI_Msk (0x8000000UL) /*!< DI (Bitfield-Mask: 0x01) */ +#define GPDMA_CONTROL1_PROT1_Pos (28UL) /*!< PROT1 (Bit 28) */ +#define GPDMA_CONTROL1_PROT1_Msk (0x10000000UL) /*!< PROT1 (Bitfield-Mask: 0x01) */ +#define GPDMA_CONTROL1_PROT2_Pos (29UL) /*!< PROT2 (Bit 29) */ +#define GPDMA_CONTROL1_PROT2_Msk (0x20000000UL) /*!< PROT2 (Bitfield-Mask: 0x01) */ +#define GPDMA_CONTROL1_PROT3_Pos (30UL) /*!< PROT3 (Bit 30) */ +#define GPDMA_CONTROL1_PROT3_Msk (0x40000000UL) /*!< PROT3 (Bitfield-Mask: 0x01) */ +#define GPDMA_CONTROL1_I_Pos (31UL) /*!< I (Bit 31) */ +#define GPDMA_CONTROL1_I_Msk (0x80000000UL) /*!< I (Bitfield-Mask: 0x01) */ +/* ======================================================= CONTROL2 ======================================================== */ +#define GPDMA_CONTROL2_TRANSFERSIZE_Pos (0UL) /*!< TRANSFERSIZE (Bit 0) */ +#define GPDMA_CONTROL2_TRANSFERSIZE_Msk (0xfffUL) /*!< TRANSFERSIZE (Bitfield-Mask: 0xfff) */ +#define GPDMA_CONTROL2_SBSIZE_Pos (12UL) /*!< SBSIZE (Bit 12) */ +#define GPDMA_CONTROL2_SBSIZE_Msk (0x7000UL) /*!< SBSIZE (Bitfield-Mask: 0x07) */ +#define GPDMA_CONTROL2_DBSIZE_Pos (15UL) /*!< DBSIZE (Bit 15) */ +#define GPDMA_CONTROL2_DBSIZE_Msk (0x38000UL) /*!< DBSIZE (Bitfield-Mask: 0x07) */ +#define GPDMA_CONTROL2_SWIDTH_Pos (18UL) /*!< SWIDTH (Bit 18) */ +#define GPDMA_CONTROL2_SWIDTH_Msk (0x1c0000UL) /*!< SWIDTH (Bitfield-Mask: 0x07) */ +#define GPDMA_CONTROL2_DWIDTH_Pos (21UL) /*!< DWIDTH (Bit 21) */ +#define GPDMA_CONTROL2_DWIDTH_Msk (0xe00000UL) /*!< DWIDTH (Bitfield-Mask: 0x07) */ +#define GPDMA_CONTROL2_SI_Pos (26UL) /*!< SI (Bit 26) */ +#define GPDMA_CONTROL2_SI_Msk (0x4000000UL) /*!< SI (Bitfield-Mask: 0x01) */ +#define GPDMA_CONTROL2_DI_Pos (27UL) /*!< DI (Bit 27) */ +#define GPDMA_CONTROL2_DI_Msk (0x8000000UL) /*!< DI (Bitfield-Mask: 0x01) */ +#define GPDMA_CONTROL2_PROT1_Pos (28UL) /*!< PROT1 (Bit 28) */ +#define GPDMA_CONTROL2_PROT1_Msk (0x10000000UL) /*!< PROT1 (Bitfield-Mask: 0x01) */ +#define GPDMA_CONTROL2_PROT2_Pos (29UL) /*!< PROT2 (Bit 29) */ +#define GPDMA_CONTROL2_PROT2_Msk (0x20000000UL) /*!< PROT2 (Bitfield-Mask: 0x01) */ +#define GPDMA_CONTROL2_PROT3_Pos (30UL) /*!< PROT3 (Bit 30) */ +#define GPDMA_CONTROL2_PROT3_Msk (0x40000000UL) /*!< PROT3 (Bitfield-Mask: 0x01) */ +#define GPDMA_CONTROL2_I_Pos (31UL) /*!< I (Bit 31) */ +#define GPDMA_CONTROL2_I_Msk (0x80000000UL) /*!< I (Bitfield-Mask: 0x01) */ +/* ======================================================= CONTROL3 ======================================================== */ +#define GPDMA_CONTROL3_TRANSFERSIZE_Pos (0UL) /*!< TRANSFERSIZE (Bit 0) */ +#define GPDMA_CONTROL3_TRANSFERSIZE_Msk (0xfffUL) /*!< TRANSFERSIZE (Bitfield-Mask: 0xfff) */ +#define GPDMA_CONTROL3_SBSIZE_Pos (12UL) /*!< SBSIZE (Bit 12) */ +#define GPDMA_CONTROL3_SBSIZE_Msk (0x7000UL) /*!< SBSIZE (Bitfield-Mask: 0x07) */ +#define GPDMA_CONTROL3_DBSIZE_Pos (15UL) /*!< DBSIZE (Bit 15) */ +#define GPDMA_CONTROL3_DBSIZE_Msk (0x38000UL) /*!< DBSIZE (Bitfield-Mask: 0x07) */ +#define GPDMA_CONTROL3_SWIDTH_Pos (18UL) /*!< SWIDTH (Bit 18) */ +#define GPDMA_CONTROL3_SWIDTH_Msk (0x1c0000UL) /*!< SWIDTH (Bitfield-Mask: 0x07) */ +#define GPDMA_CONTROL3_DWIDTH_Pos (21UL) /*!< DWIDTH (Bit 21) */ +#define GPDMA_CONTROL3_DWIDTH_Msk (0xe00000UL) /*!< DWIDTH (Bitfield-Mask: 0x07) */ +#define GPDMA_CONTROL3_SI_Pos (26UL) /*!< SI (Bit 26) */ +#define GPDMA_CONTROL3_SI_Msk (0x4000000UL) /*!< SI (Bitfield-Mask: 0x01) */ +#define GPDMA_CONTROL3_DI_Pos (27UL) /*!< DI (Bit 27) */ +#define GPDMA_CONTROL3_DI_Msk (0x8000000UL) /*!< DI (Bitfield-Mask: 0x01) */ +#define GPDMA_CONTROL3_PROT1_Pos (28UL) /*!< PROT1 (Bit 28) */ +#define GPDMA_CONTROL3_PROT1_Msk (0x10000000UL) /*!< PROT1 (Bitfield-Mask: 0x01) */ +#define GPDMA_CONTROL3_PROT2_Pos (29UL) /*!< PROT2 (Bit 29) */ +#define GPDMA_CONTROL3_PROT2_Msk (0x20000000UL) /*!< PROT2 (Bitfield-Mask: 0x01) */ +#define GPDMA_CONTROL3_PROT3_Pos (30UL) /*!< PROT3 (Bit 30) */ +#define GPDMA_CONTROL3_PROT3_Msk (0x40000000UL) /*!< PROT3 (Bitfield-Mask: 0x01) */ +#define GPDMA_CONTROL3_I_Pos (31UL) /*!< I (Bit 31) */ +#define GPDMA_CONTROL3_I_Msk (0x80000000UL) /*!< I (Bitfield-Mask: 0x01) */ +/* ======================================================= CONTROL4 ======================================================== */ +#define GPDMA_CONTROL4_TRANSFERSIZE_Pos (0UL) /*!< TRANSFERSIZE (Bit 0) */ +#define GPDMA_CONTROL4_TRANSFERSIZE_Msk (0xfffUL) /*!< TRANSFERSIZE (Bitfield-Mask: 0xfff) */ +#define GPDMA_CONTROL4_SBSIZE_Pos (12UL) /*!< SBSIZE (Bit 12) */ +#define GPDMA_CONTROL4_SBSIZE_Msk (0x7000UL) /*!< SBSIZE (Bitfield-Mask: 0x07) */ +#define GPDMA_CONTROL4_DBSIZE_Pos (15UL) /*!< DBSIZE (Bit 15) */ +#define GPDMA_CONTROL4_DBSIZE_Msk (0x38000UL) /*!< DBSIZE (Bitfield-Mask: 0x07) */ +#define GPDMA_CONTROL4_SWIDTH_Pos (18UL) /*!< SWIDTH (Bit 18) */ +#define GPDMA_CONTROL4_SWIDTH_Msk (0x1c0000UL) /*!< SWIDTH (Bitfield-Mask: 0x07) */ +#define GPDMA_CONTROL4_DWIDTH_Pos (21UL) /*!< DWIDTH (Bit 21) */ +#define GPDMA_CONTROL4_DWIDTH_Msk (0xe00000UL) /*!< DWIDTH (Bitfield-Mask: 0x07) */ +#define GPDMA_CONTROL4_SI_Pos (26UL) /*!< SI (Bit 26) */ +#define GPDMA_CONTROL4_SI_Msk (0x4000000UL) /*!< SI (Bitfield-Mask: 0x01) */ +#define GPDMA_CONTROL4_DI_Pos (27UL) /*!< DI (Bit 27) */ +#define GPDMA_CONTROL4_DI_Msk (0x8000000UL) /*!< DI (Bitfield-Mask: 0x01) */ +#define GPDMA_CONTROL4_PROT1_Pos (28UL) /*!< PROT1 (Bit 28) */ +#define GPDMA_CONTROL4_PROT1_Msk (0x10000000UL) /*!< PROT1 (Bitfield-Mask: 0x01) */ +#define GPDMA_CONTROL4_PROT2_Pos (29UL) /*!< PROT2 (Bit 29) */ +#define GPDMA_CONTROL4_PROT2_Msk (0x20000000UL) /*!< PROT2 (Bitfield-Mask: 0x01) */ +#define GPDMA_CONTROL4_PROT3_Pos (30UL) /*!< PROT3 (Bit 30) */ +#define GPDMA_CONTROL4_PROT3_Msk (0x40000000UL) /*!< PROT3 (Bitfield-Mask: 0x01) */ +#define GPDMA_CONTROL4_I_Pos (31UL) /*!< I (Bit 31) */ +#define GPDMA_CONTROL4_I_Msk (0x80000000UL) /*!< I (Bitfield-Mask: 0x01) */ +/* ======================================================= CONTROL5 ======================================================== */ +#define GPDMA_CONTROL5_TRANSFERSIZE_Pos (0UL) /*!< TRANSFERSIZE (Bit 0) */ +#define GPDMA_CONTROL5_TRANSFERSIZE_Msk (0xfffUL) /*!< TRANSFERSIZE (Bitfield-Mask: 0xfff) */ +#define GPDMA_CONTROL5_SBSIZE_Pos (12UL) /*!< SBSIZE (Bit 12) */ +#define GPDMA_CONTROL5_SBSIZE_Msk (0x7000UL) /*!< SBSIZE (Bitfield-Mask: 0x07) */ +#define GPDMA_CONTROL5_DBSIZE_Pos (15UL) /*!< DBSIZE (Bit 15) */ +#define GPDMA_CONTROL5_DBSIZE_Msk (0x38000UL) /*!< DBSIZE (Bitfield-Mask: 0x07) */ +#define GPDMA_CONTROL5_SWIDTH_Pos (18UL) /*!< SWIDTH (Bit 18) */ +#define GPDMA_CONTROL5_SWIDTH_Msk (0x1c0000UL) /*!< SWIDTH (Bitfield-Mask: 0x07) */ +#define GPDMA_CONTROL5_DWIDTH_Pos (21UL) /*!< DWIDTH (Bit 21) */ +#define GPDMA_CONTROL5_DWIDTH_Msk (0xe00000UL) /*!< DWIDTH (Bitfield-Mask: 0x07) */ +#define GPDMA_CONTROL5_SI_Pos (26UL) /*!< SI (Bit 26) */ +#define GPDMA_CONTROL5_SI_Msk (0x4000000UL) /*!< SI (Bitfield-Mask: 0x01) */ +#define GPDMA_CONTROL5_DI_Pos (27UL) /*!< DI (Bit 27) */ +#define GPDMA_CONTROL5_DI_Msk (0x8000000UL) /*!< DI (Bitfield-Mask: 0x01) */ +#define GPDMA_CONTROL5_PROT1_Pos (28UL) /*!< PROT1 (Bit 28) */ +#define GPDMA_CONTROL5_PROT1_Msk (0x10000000UL) /*!< PROT1 (Bitfield-Mask: 0x01) */ +#define GPDMA_CONTROL5_PROT2_Pos (29UL) /*!< PROT2 (Bit 29) */ +#define GPDMA_CONTROL5_PROT2_Msk (0x20000000UL) /*!< PROT2 (Bitfield-Mask: 0x01) */ +#define GPDMA_CONTROL5_PROT3_Pos (30UL) /*!< PROT3 (Bit 30) */ +#define GPDMA_CONTROL5_PROT3_Msk (0x40000000UL) /*!< PROT3 (Bitfield-Mask: 0x01) */ +#define GPDMA_CONTROL5_I_Pos (31UL) /*!< I (Bit 31) */ +#define GPDMA_CONTROL5_I_Msk (0x80000000UL) /*!< I (Bitfield-Mask: 0x01) */ +/* ======================================================= CONTROL6 ======================================================== */ +#define GPDMA_CONTROL6_TRANSFERSIZE_Pos (0UL) /*!< TRANSFERSIZE (Bit 0) */ +#define GPDMA_CONTROL6_TRANSFERSIZE_Msk (0xfffUL) /*!< TRANSFERSIZE (Bitfield-Mask: 0xfff) */ +#define GPDMA_CONTROL6_SBSIZE_Pos (12UL) /*!< SBSIZE (Bit 12) */ +#define GPDMA_CONTROL6_SBSIZE_Msk (0x7000UL) /*!< SBSIZE (Bitfield-Mask: 0x07) */ +#define GPDMA_CONTROL6_DBSIZE_Pos (15UL) /*!< DBSIZE (Bit 15) */ +#define GPDMA_CONTROL6_DBSIZE_Msk (0x38000UL) /*!< DBSIZE (Bitfield-Mask: 0x07) */ +#define GPDMA_CONTROL6_SWIDTH_Pos (18UL) /*!< SWIDTH (Bit 18) */ +#define GPDMA_CONTROL6_SWIDTH_Msk (0x1c0000UL) /*!< SWIDTH (Bitfield-Mask: 0x07) */ +#define GPDMA_CONTROL6_DWIDTH_Pos (21UL) /*!< DWIDTH (Bit 21) */ +#define GPDMA_CONTROL6_DWIDTH_Msk (0xe00000UL) /*!< DWIDTH (Bitfield-Mask: 0x07) */ +#define GPDMA_CONTROL6_SI_Pos (26UL) /*!< SI (Bit 26) */ +#define GPDMA_CONTROL6_SI_Msk (0x4000000UL) /*!< SI (Bitfield-Mask: 0x01) */ +#define GPDMA_CONTROL6_DI_Pos (27UL) /*!< DI (Bit 27) */ +#define GPDMA_CONTROL6_DI_Msk (0x8000000UL) /*!< DI (Bitfield-Mask: 0x01) */ +#define GPDMA_CONTROL6_PROT1_Pos (28UL) /*!< PROT1 (Bit 28) */ +#define GPDMA_CONTROL6_PROT1_Msk (0x10000000UL) /*!< PROT1 (Bitfield-Mask: 0x01) */ +#define GPDMA_CONTROL6_PROT2_Pos (29UL) /*!< PROT2 (Bit 29) */ +#define GPDMA_CONTROL6_PROT2_Msk (0x20000000UL) /*!< PROT2 (Bitfield-Mask: 0x01) */ +#define GPDMA_CONTROL6_PROT3_Pos (30UL) /*!< PROT3 (Bit 30) */ +#define GPDMA_CONTROL6_PROT3_Msk (0x40000000UL) /*!< PROT3 (Bitfield-Mask: 0x01) */ +#define GPDMA_CONTROL6_I_Pos (31UL) /*!< I (Bit 31) */ +#define GPDMA_CONTROL6_I_Msk (0x80000000UL) /*!< I (Bitfield-Mask: 0x01) */ +/* ======================================================= CONTROL7 ======================================================== */ +#define GPDMA_CONTROL7_TRANSFERSIZE_Pos (0UL) /*!< TRANSFERSIZE (Bit 0) */ +#define GPDMA_CONTROL7_TRANSFERSIZE_Msk (0xfffUL) /*!< TRANSFERSIZE (Bitfield-Mask: 0xfff) */ +#define GPDMA_CONTROL7_SBSIZE_Pos (12UL) /*!< SBSIZE (Bit 12) */ +#define GPDMA_CONTROL7_SBSIZE_Msk (0x7000UL) /*!< SBSIZE (Bitfield-Mask: 0x07) */ +#define GPDMA_CONTROL7_DBSIZE_Pos (15UL) /*!< DBSIZE (Bit 15) */ +#define GPDMA_CONTROL7_DBSIZE_Msk (0x38000UL) /*!< DBSIZE (Bitfield-Mask: 0x07) */ +#define GPDMA_CONTROL7_SWIDTH_Pos (18UL) /*!< SWIDTH (Bit 18) */ +#define GPDMA_CONTROL7_SWIDTH_Msk (0x1c0000UL) /*!< SWIDTH (Bitfield-Mask: 0x07) */ +#define GPDMA_CONTROL7_DWIDTH_Pos (21UL) /*!< DWIDTH (Bit 21) */ +#define GPDMA_CONTROL7_DWIDTH_Msk (0xe00000UL) /*!< DWIDTH (Bitfield-Mask: 0x07) */ +#define GPDMA_CONTROL7_SI_Pos (26UL) /*!< SI (Bit 26) */ +#define GPDMA_CONTROL7_SI_Msk (0x4000000UL) /*!< SI (Bitfield-Mask: 0x01) */ +#define GPDMA_CONTROL7_DI_Pos (27UL) /*!< DI (Bit 27) */ +#define GPDMA_CONTROL7_DI_Msk (0x8000000UL) /*!< DI (Bitfield-Mask: 0x01) */ +#define GPDMA_CONTROL7_PROT1_Pos (28UL) /*!< PROT1 (Bit 28) */ +#define GPDMA_CONTROL7_PROT1_Msk (0x10000000UL) /*!< PROT1 (Bitfield-Mask: 0x01) */ +#define GPDMA_CONTROL7_PROT2_Pos (29UL) /*!< PROT2 (Bit 29) */ +#define GPDMA_CONTROL7_PROT2_Msk (0x20000000UL) /*!< PROT2 (Bitfield-Mask: 0x01) */ +#define GPDMA_CONTROL7_PROT3_Pos (30UL) /*!< PROT3 (Bit 30) */ +#define GPDMA_CONTROL7_PROT3_Msk (0x40000000UL) /*!< PROT3 (Bitfield-Mask: 0x01) */ +#define GPDMA_CONTROL7_I_Pos (31UL) /*!< I (Bit 31) */ +#define GPDMA_CONTROL7_I_Msk (0x80000000UL) /*!< I (Bitfield-Mask: 0x01) */ +/* ======================================================== CONFIG0 ======================================================== */ +#define GPDMA_CONFIG0_E_Pos (0UL) /*!< E (Bit 0) */ +#define GPDMA_CONFIG0_E_Msk (0x1UL) /*!< E (Bitfield-Mask: 0x01) */ +#define GPDMA_CONFIG0_SRCPERIPHERAL_Pos (1UL) /*!< SRCPERIPHERAL (Bit 1) */ +#define GPDMA_CONFIG0_SRCPERIPHERAL_Msk (0x3eUL) /*!< SRCPERIPHERAL (Bitfield-Mask: 0x1f) */ +#define GPDMA_CONFIG0_DESTPERIPHERAL_Pos (6UL) /*!< DESTPERIPHERAL (Bit 6) */ +#define GPDMA_CONFIG0_DESTPERIPHERAL_Msk (0x7c0UL) /*!< DESTPERIPHERAL (Bitfield-Mask: 0x1f) */ +#define GPDMA_CONFIG0_TRANSFERTYPE_Pos (11UL) /*!< TRANSFERTYPE (Bit 11) */ +#define GPDMA_CONFIG0_TRANSFERTYPE_Msk (0x3800UL) /*!< TRANSFERTYPE (Bitfield-Mask: 0x07) */ +#define GPDMA_CONFIG0_IE_Pos (14UL) /*!< IE (Bit 14) */ +#define GPDMA_CONFIG0_IE_Msk (0x4000UL) /*!< IE (Bitfield-Mask: 0x01) */ +#define GPDMA_CONFIG0_ITC_Pos (15UL) /*!< ITC (Bit 15) */ +#define GPDMA_CONFIG0_ITC_Msk (0x8000UL) /*!< ITC (Bitfield-Mask: 0x01) */ +#define GPDMA_CONFIG0_L_Pos (16UL) /*!< L (Bit 16) */ +#define GPDMA_CONFIG0_L_Msk (0x10000UL) /*!< L (Bitfield-Mask: 0x01) */ +#define GPDMA_CONFIG0_A_Pos (17UL) /*!< A (Bit 17) */ +#define GPDMA_CONFIG0_A_Msk (0x20000UL) /*!< A (Bitfield-Mask: 0x01) */ +#define GPDMA_CONFIG0_H_Pos (18UL) /*!< H (Bit 18) */ +#define GPDMA_CONFIG0_H_Msk (0x40000UL) /*!< H (Bitfield-Mask: 0x01) */ +/* ======================================================== CONFIG1 ======================================================== */ +#define GPDMA_CONFIG1_E_Pos (0UL) /*!< E (Bit 0) */ +#define GPDMA_CONFIG1_E_Msk (0x1UL) /*!< E (Bitfield-Mask: 0x01) */ +#define GPDMA_CONFIG1_SRCPERIPHERAL_Pos (1UL) /*!< SRCPERIPHERAL (Bit 1) */ +#define GPDMA_CONFIG1_SRCPERIPHERAL_Msk (0x3eUL) /*!< SRCPERIPHERAL (Bitfield-Mask: 0x1f) */ +#define GPDMA_CONFIG1_DESTPERIPHERAL_Pos (6UL) /*!< DESTPERIPHERAL (Bit 6) */ +#define GPDMA_CONFIG1_DESTPERIPHERAL_Msk (0x7c0UL) /*!< DESTPERIPHERAL (Bitfield-Mask: 0x1f) */ +#define GPDMA_CONFIG1_TRANSFERTYPE_Pos (11UL) /*!< TRANSFERTYPE (Bit 11) */ +#define GPDMA_CONFIG1_TRANSFERTYPE_Msk (0x3800UL) /*!< TRANSFERTYPE (Bitfield-Mask: 0x07) */ +#define GPDMA_CONFIG1_IE_Pos (14UL) /*!< IE (Bit 14) */ +#define GPDMA_CONFIG1_IE_Msk (0x4000UL) /*!< IE (Bitfield-Mask: 0x01) */ +#define GPDMA_CONFIG1_ITC_Pos (15UL) /*!< ITC (Bit 15) */ +#define GPDMA_CONFIG1_ITC_Msk (0x8000UL) /*!< ITC (Bitfield-Mask: 0x01) */ +#define GPDMA_CONFIG1_L_Pos (16UL) /*!< L (Bit 16) */ +#define GPDMA_CONFIG1_L_Msk (0x10000UL) /*!< L (Bitfield-Mask: 0x01) */ +#define GPDMA_CONFIG1_A_Pos (17UL) /*!< A (Bit 17) */ +#define GPDMA_CONFIG1_A_Msk (0x20000UL) /*!< A (Bitfield-Mask: 0x01) */ +#define GPDMA_CONFIG1_H_Pos (18UL) /*!< H (Bit 18) */ +#define GPDMA_CONFIG1_H_Msk (0x40000UL) /*!< H (Bitfield-Mask: 0x01) */ +/* ======================================================== CONFIG2 ======================================================== */ +#define GPDMA_CONFIG2_E_Pos (0UL) /*!< E (Bit 0) */ +#define GPDMA_CONFIG2_E_Msk (0x1UL) /*!< E (Bitfield-Mask: 0x01) */ +#define GPDMA_CONFIG2_SRCPERIPHERAL_Pos (1UL) /*!< SRCPERIPHERAL (Bit 1) */ +#define GPDMA_CONFIG2_SRCPERIPHERAL_Msk (0x3eUL) /*!< SRCPERIPHERAL (Bitfield-Mask: 0x1f) */ +#define GPDMA_CONFIG2_DESTPERIPHERAL_Pos (6UL) /*!< DESTPERIPHERAL (Bit 6) */ +#define GPDMA_CONFIG2_DESTPERIPHERAL_Msk (0x7c0UL) /*!< DESTPERIPHERAL (Bitfield-Mask: 0x1f) */ +#define GPDMA_CONFIG2_TRANSFERTYPE_Pos (11UL) /*!< TRANSFERTYPE (Bit 11) */ +#define GPDMA_CONFIG2_TRANSFERTYPE_Msk (0x3800UL) /*!< TRANSFERTYPE (Bitfield-Mask: 0x07) */ +#define GPDMA_CONFIG2_IE_Pos (14UL) /*!< IE (Bit 14) */ +#define GPDMA_CONFIG2_IE_Msk (0x4000UL) /*!< IE (Bitfield-Mask: 0x01) */ +#define GPDMA_CONFIG2_ITC_Pos (15UL) /*!< ITC (Bit 15) */ +#define GPDMA_CONFIG2_ITC_Msk (0x8000UL) /*!< ITC (Bitfield-Mask: 0x01) */ +#define GPDMA_CONFIG2_L_Pos (16UL) /*!< L (Bit 16) */ +#define GPDMA_CONFIG2_L_Msk (0x10000UL) /*!< L (Bitfield-Mask: 0x01) */ +#define GPDMA_CONFIG2_A_Pos (17UL) /*!< A (Bit 17) */ +#define GPDMA_CONFIG2_A_Msk (0x20000UL) /*!< A (Bitfield-Mask: 0x01) */ +#define GPDMA_CONFIG2_H_Pos (18UL) /*!< H (Bit 18) */ +#define GPDMA_CONFIG2_H_Msk (0x40000UL) /*!< H (Bitfield-Mask: 0x01) */ +/* ======================================================== CONFIG3 ======================================================== */ +#define GPDMA_CONFIG3_E_Pos (0UL) /*!< E (Bit 0) */ +#define GPDMA_CONFIG3_E_Msk (0x1UL) /*!< E (Bitfield-Mask: 0x01) */ +#define GPDMA_CONFIG3_SRCPERIPHERAL_Pos (1UL) /*!< SRCPERIPHERAL (Bit 1) */ +#define GPDMA_CONFIG3_SRCPERIPHERAL_Msk (0x3eUL) /*!< SRCPERIPHERAL (Bitfield-Mask: 0x1f) */ +#define GPDMA_CONFIG3_DESTPERIPHERAL_Pos (6UL) /*!< DESTPERIPHERAL (Bit 6) */ +#define GPDMA_CONFIG3_DESTPERIPHERAL_Msk (0x7c0UL) /*!< DESTPERIPHERAL (Bitfield-Mask: 0x1f) */ +#define GPDMA_CONFIG3_TRANSFERTYPE_Pos (11UL) /*!< TRANSFERTYPE (Bit 11) */ +#define GPDMA_CONFIG3_TRANSFERTYPE_Msk (0x3800UL) /*!< TRANSFERTYPE (Bitfield-Mask: 0x07) */ +#define GPDMA_CONFIG3_IE_Pos (14UL) /*!< IE (Bit 14) */ +#define GPDMA_CONFIG3_IE_Msk (0x4000UL) /*!< IE (Bitfield-Mask: 0x01) */ +#define GPDMA_CONFIG3_ITC_Pos (15UL) /*!< ITC (Bit 15) */ +#define GPDMA_CONFIG3_ITC_Msk (0x8000UL) /*!< ITC (Bitfield-Mask: 0x01) */ +#define GPDMA_CONFIG3_L_Pos (16UL) /*!< L (Bit 16) */ +#define GPDMA_CONFIG3_L_Msk (0x10000UL) /*!< L (Bitfield-Mask: 0x01) */ +#define GPDMA_CONFIG3_A_Pos (17UL) /*!< A (Bit 17) */ +#define GPDMA_CONFIG3_A_Msk (0x20000UL) /*!< A (Bitfield-Mask: 0x01) */ +#define GPDMA_CONFIG3_H_Pos (18UL) /*!< H (Bit 18) */ +#define GPDMA_CONFIG3_H_Msk (0x40000UL) /*!< H (Bitfield-Mask: 0x01) */ +/* ======================================================== CONFIG4 ======================================================== */ +#define GPDMA_CONFIG4_E_Pos (0UL) /*!< E (Bit 0) */ +#define GPDMA_CONFIG4_E_Msk (0x1UL) /*!< E (Bitfield-Mask: 0x01) */ +#define GPDMA_CONFIG4_SRCPERIPHERAL_Pos (1UL) /*!< SRCPERIPHERAL (Bit 1) */ +#define GPDMA_CONFIG4_SRCPERIPHERAL_Msk (0x3eUL) /*!< SRCPERIPHERAL (Bitfield-Mask: 0x1f) */ +#define GPDMA_CONFIG4_DESTPERIPHERAL_Pos (6UL) /*!< DESTPERIPHERAL (Bit 6) */ +#define GPDMA_CONFIG4_DESTPERIPHERAL_Msk (0x7c0UL) /*!< DESTPERIPHERAL (Bitfield-Mask: 0x1f) */ +#define GPDMA_CONFIG4_TRANSFERTYPE_Pos (11UL) /*!< TRANSFERTYPE (Bit 11) */ +#define GPDMA_CONFIG4_TRANSFERTYPE_Msk (0x3800UL) /*!< TRANSFERTYPE (Bitfield-Mask: 0x07) */ +#define GPDMA_CONFIG4_IE_Pos (14UL) /*!< IE (Bit 14) */ +#define GPDMA_CONFIG4_IE_Msk (0x4000UL) /*!< IE (Bitfield-Mask: 0x01) */ +#define GPDMA_CONFIG4_ITC_Pos (15UL) /*!< ITC (Bit 15) */ +#define GPDMA_CONFIG4_ITC_Msk (0x8000UL) /*!< ITC (Bitfield-Mask: 0x01) */ +#define GPDMA_CONFIG4_L_Pos (16UL) /*!< L (Bit 16) */ +#define GPDMA_CONFIG4_L_Msk (0x10000UL) /*!< L (Bitfield-Mask: 0x01) */ +#define GPDMA_CONFIG4_A_Pos (17UL) /*!< A (Bit 17) */ +#define GPDMA_CONFIG4_A_Msk (0x20000UL) /*!< A (Bitfield-Mask: 0x01) */ +#define GPDMA_CONFIG4_H_Pos (18UL) /*!< H (Bit 18) */ +#define GPDMA_CONFIG4_H_Msk (0x40000UL) /*!< H (Bitfield-Mask: 0x01) */ +/* ======================================================== CONFIG5 ======================================================== */ +#define GPDMA_CONFIG5_E_Pos (0UL) /*!< E (Bit 0) */ +#define GPDMA_CONFIG5_E_Msk (0x1UL) /*!< E (Bitfield-Mask: 0x01) */ +#define GPDMA_CONFIG5_SRCPERIPHERAL_Pos (1UL) /*!< SRCPERIPHERAL (Bit 1) */ +#define GPDMA_CONFIG5_SRCPERIPHERAL_Msk (0x3eUL) /*!< SRCPERIPHERAL (Bitfield-Mask: 0x1f) */ +#define GPDMA_CONFIG5_DESTPERIPHERAL_Pos (6UL) /*!< DESTPERIPHERAL (Bit 6) */ +#define GPDMA_CONFIG5_DESTPERIPHERAL_Msk (0x7c0UL) /*!< DESTPERIPHERAL (Bitfield-Mask: 0x1f) */ +#define GPDMA_CONFIG5_TRANSFERTYPE_Pos (11UL) /*!< TRANSFERTYPE (Bit 11) */ +#define GPDMA_CONFIG5_TRANSFERTYPE_Msk (0x3800UL) /*!< TRANSFERTYPE (Bitfield-Mask: 0x07) */ +#define GPDMA_CONFIG5_IE_Pos (14UL) /*!< IE (Bit 14) */ +#define GPDMA_CONFIG5_IE_Msk (0x4000UL) /*!< IE (Bitfield-Mask: 0x01) */ +#define GPDMA_CONFIG5_ITC_Pos (15UL) /*!< ITC (Bit 15) */ +#define GPDMA_CONFIG5_ITC_Msk (0x8000UL) /*!< ITC (Bitfield-Mask: 0x01) */ +#define GPDMA_CONFIG5_L_Pos (16UL) /*!< L (Bit 16) */ +#define GPDMA_CONFIG5_L_Msk (0x10000UL) /*!< L (Bitfield-Mask: 0x01) */ +#define GPDMA_CONFIG5_A_Pos (17UL) /*!< A (Bit 17) */ +#define GPDMA_CONFIG5_A_Msk (0x20000UL) /*!< A (Bitfield-Mask: 0x01) */ +#define GPDMA_CONFIG5_H_Pos (18UL) /*!< H (Bit 18) */ +#define GPDMA_CONFIG5_H_Msk (0x40000UL) /*!< H (Bitfield-Mask: 0x01) */ +/* ======================================================== CONFIG6 ======================================================== */ +#define GPDMA_CONFIG6_E_Pos (0UL) /*!< E (Bit 0) */ +#define GPDMA_CONFIG6_E_Msk (0x1UL) /*!< E (Bitfield-Mask: 0x01) */ +#define GPDMA_CONFIG6_SRCPERIPHERAL_Pos (1UL) /*!< SRCPERIPHERAL (Bit 1) */ +#define GPDMA_CONFIG6_SRCPERIPHERAL_Msk (0x3eUL) /*!< SRCPERIPHERAL (Bitfield-Mask: 0x1f) */ +#define GPDMA_CONFIG6_DESTPERIPHERAL_Pos (6UL) /*!< DESTPERIPHERAL (Bit 6) */ +#define GPDMA_CONFIG6_DESTPERIPHERAL_Msk (0x7c0UL) /*!< DESTPERIPHERAL (Bitfield-Mask: 0x1f) */ +#define GPDMA_CONFIG6_TRANSFERTYPE_Pos (11UL) /*!< TRANSFERTYPE (Bit 11) */ +#define GPDMA_CONFIG6_TRANSFERTYPE_Msk (0x3800UL) /*!< TRANSFERTYPE (Bitfield-Mask: 0x07) */ +#define GPDMA_CONFIG6_IE_Pos (14UL) /*!< IE (Bit 14) */ +#define GPDMA_CONFIG6_IE_Msk (0x4000UL) /*!< IE (Bitfield-Mask: 0x01) */ +#define GPDMA_CONFIG6_ITC_Pos (15UL) /*!< ITC (Bit 15) */ +#define GPDMA_CONFIG6_ITC_Msk (0x8000UL) /*!< ITC (Bitfield-Mask: 0x01) */ +#define GPDMA_CONFIG6_L_Pos (16UL) /*!< L (Bit 16) */ +#define GPDMA_CONFIG6_L_Msk (0x10000UL) /*!< L (Bitfield-Mask: 0x01) */ +#define GPDMA_CONFIG6_A_Pos (17UL) /*!< A (Bit 17) */ +#define GPDMA_CONFIG6_A_Msk (0x20000UL) /*!< A (Bitfield-Mask: 0x01) */ +#define GPDMA_CONFIG6_H_Pos (18UL) /*!< H (Bit 18) */ +#define GPDMA_CONFIG6_H_Msk (0x40000UL) /*!< H (Bitfield-Mask: 0x01) */ +/* ======================================================== CONFIG7 ======================================================== */ +#define GPDMA_CONFIG7_E_Pos (0UL) /*!< E (Bit 0) */ +#define GPDMA_CONFIG7_E_Msk (0x1UL) /*!< E (Bitfield-Mask: 0x01) */ +#define GPDMA_CONFIG7_SRCPERIPHERAL_Pos (1UL) /*!< SRCPERIPHERAL (Bit 1) */ +#define GPDMA_CONFIG7_SRCPERIPHERAL_Msk (0x3eUL) /*!< SRCPERIPHERAL (Bitfield-Mask: 0x1f) */ +#define GPDMA_CONFIG7_DESTPERIPHERAL_Pos (6UL) /*!< DESTPERIPHERAL (Bit 6) */ +#define GPDMA_CONFIG7_DESTPERIPHERAL_Msk (0x7c0UL) /*!< DESTPERIPHERAL (Bitfield-Mask: 0x1f) */ +#define GPDMA_CONFIG7_TRANSFERTYPE_Pos (11UL) /*!< TRANSFERTYPE (Bit 11) */ +#define GPDMA_CONFIG7_TRANSFERTYPE_Msk (0x3800UL) /*!< TRANSFERTYPE (Bitfield-Mask: 0x07) */ +#define GPDMA_CONFIG7_IE_Pos (14UL) /*!< IE (Bit 14) */ +#define GPDMA_CONFIG7_IE_Msk (0x4000UL) /*!< IE (Bitfield-Mask: 0x01) */ +#define GPDMA_CONFIG7_ITC_Pos (15UL) /*!< ITC (Bit 15) */ +#define GPDMA_CONFIG7_ITC_Msk (0x8000UL) /*!< ITC (Bitfield-Mask: 0x01) */ +#define GPDMA_CONFIG7_L_Pos (16UL) /*!< L (Bit 16) */ +#define GPDMA_CONFIG7_L_Msk (0x10000UL) /*!< L (Bitfield-Mask: 0x01) */ +#define GPDMA_CONFIG7_A_Pos (17UL) /*!< A (Bit 17) */ +#define GPDMA_CONFIG7_A_Msk (0x20000UL) /*!< A (Bitfield-Mask: 0x01) */ +#define GPDMA_CONFIG7_H_Pos (18UL) /*!< H (Bit 18) */ +#define GPDMA_CONFIG7_H_Msk (0x40000UL) /*!< H (Bitfield-Mask: 0x01) */ + + +/* =========================================================================================================================== */ +/* ================ LPC_USB ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= INTST ========================================================= */ +#define USB_INTST_TMR_Pos (0UL) /*!< TMR (Bit 0) */ +#define USB_INTST_TMR_Msk (0x1UL) /*!< TMR (Bitfield-Mask: 0x01) */ +#define USB_INTST_REMOVE_PU_Pos (1UL) /*!< REMOVE_PU (Bit 1) */ +#define USB_INTST_REMOVE_PU_Msk (0x2UL) /*!< REMOVE_PU (Bitfield-Mask: 0x01) */ +#define USB_INTST_HNP_FAILURE_Pos (2UL) /*!< HNP_FAILURE (Bit 2) */ +#define USB_INTST_HNP_FAILURE_Msk (0x4UL) /*!< HNP_FAILURE (Bitfield-Mask: 0x01) */ +#define USB_INTST_HNP_SUCCESS_Pos (3UL) /*!< HNP_SUCCESS (Bit 3) */ +#define USB_INTST_HNP_SUCCESS_Msk (0x8UL) /*!< HNP_SUCCESS (Bitfield-Mask: 0x01) */ +/* ========================================================= INTEN ========================================================= */ +#define USB_INTEN_TMR_EN_Pos (0UL) /*!< TMR_EN (Bit 0) */ +#define USB_INTEN_TMR_EN_Msk (0x1UL) /*!< TMR_EN (Bitfield-Mask: 0x01) */ +#define USB_INTEN_REMOVE_PU_EN_Pos (1UL) /*!< REMOVE_PU_EN (Bit 1) */ +#define USB_INTEN_REMOVE_PU_EN_Msk (0x2UL) /*!< REMOVE_PU_EN (Bitfield-Mask: 0x01) */ +#define USB_INTEN_HNP_FAILURE_EN_Pos (2UL) /*!< HNP_FAILURE_EN (Bit 2) */ +#define USB_INTEN_HNP_FAILURE_EN_Msk (0x4UL) /*!< HNP_FAILURE_EN (Bitfield-Mask: 0x01) */ +#define USB_INTEN_HNP_SUCCES_EN_Pos (3UL) /*!< HNP_SUCCES_EN (Bit 3) */ +#define USB_INTEN_HNP_SUCCES_EN_Msk (0x8UL) /*!< HNP_SUCCES_EN (Bitfield-Mask: 0x01) */ +/* ======================================================== INTSET ========================================================= */ +#define USB_INTSET_TMR_SET_Pos (0UL) /*!< TMR_SET (Bit 0) */ +#define USB_INTSET_TMR_SET_Msk (0x1UL) /*!< TMR_SET (Bitfield-Mask: 0x01) */ +#define USB_INTSET_REMOVE_PU_SET_Pos (1UL) /*!< REMOVE_PU_SET (Bit 1) */ +#define USB_INTSET_REMOVE_PU_SET_Msk (0x2UL) /*!< REMOVE_PU_SET (Bitfield-Mask: 0x01) */ +#define USB_INTSET_HNP_FAILURE_SET_Pos (2UL) /*!< HNP_FAILURE_SET (Bit 2) */ +#define USB_INTSET_HNP_FAILURE_SET_Msk (0x4UL) /*!< HNP_FAILURE_SET (Bitfield-Mask: 0x01) */ +#define USB_INTSET_HNP_SUCCES_SET_Pos (3UL) /*!< HNP_SUCCES_SET (Bit 3) */ +#define USB_INTSET_HNP_SUCCES_SET_Msk (0x8UL) /*!< HNP_SUCCES_SET (Bitfield-Mask: 0x01) */ +/* ======================================================== INTCLR ========================================================= */ +#define USB_INTCLR_TMR_CLR_Pos (0UL) /*!< TMR_CLR (Bit 0) */ +#define USB_INTCLR_TMR_CLR_Msk (0x1UL) /*!< TMR_CLR (Bitfield-Mask: 0x01) */ +#define USB_INTCLR_REMOVE_PU_CLR_Pos (1UL) /*!< REMOVE_PU_CLR (Bit 1) */ +#define USB_INTCLR_REMOVE_PU_CLR_Msk (0x2UL) /*!< REMOVE_PU_CLR (Bitfield-Mask: 0x01) */ +#define USB_INTCLR_HNP_FAILURE_CLR_Pos (2UL) /*!< HNP_FAILURE_CLR (Bit 2) */ +#define USB_INTCLR_HNP_FAILURE_CLR_Msk (0x4UL) /*!< HNP_FAILURE_CLR (Bitfield-Mask: 0x01) */ +#define USB_INTCLR_HNP_SUCCES_CLR_Pos (3UL) /*!< HNP_SUCCES_CLR (Bit 3) */ +#define USB_INTCLR_HNP_SUCCES_CLR_Msk (0x8UL) /*!< HNP_SUCCES_CLR (Bitfield-Mask: 0x01) */ +/* ======================================================== STCTRL ========================================================= */ +#define USB_STCTRL_PORT_FUNC_Pos (0UL) /*!< PORT_FUNC (Bit 0) */ +#define USB_STCTRL_PORT_FUNC_Msk (0x3UL) /*!< PORT_FUNC (Bitfield-Mask: 0x03) */ +#define USB_STCTRL_TMR_SCALE_Pos (2UL) /*!< TMR_SCALE (Bit 2) */ +#define USB_STCTRL_TMR_SCALE_Msk (0xcUL) /*!< TMR_SCALE (Bitfield-Mask: 0x03) */ +#define USB_STCTRL_TMR_MODE_Pos (4UL) /*!< TMR_MODE (Bit 4) */ +#define USB_STCTRL_TMR_MODE_Msk (0x10UL) /*!< TMR_MODE (Bitfield-Mask: 0x01) */ +#define USB_STCTRL_TMR_EN_Pos (5UL) /*!< TMR_EN (Bit 5) */ +#define USB_STCTRL_TMR_EN_Msk (0x20UL) /*!< TMR_EN (Bitfield-Mask: 0x01) */ +#define USB_STCTRL_TMR_RST_Pos (6UL) /*!< TMR_RST (Bit 6) */ +#define USB_STCTRL_TMR_RST_Msk (0x40UL) /*!< TMR_RST (Bitfield-Mask: 0x01) */ +#define USB_STCTRL_B_HNP_TRACK_Pos (8UL) /*!< B_HNP_TRACK (Bit 8) */ +#define USB_STCTRL_B_HNP_TRACK_Msk (0x100UL) /*!< B_HNP_TRACK (Bitfield-Mask: 0x01) */ +#define USB_STCTRL_A_HNP_TRACK_Pos (9UL) /*!< A_HNP_TRACK (Bit 9) */ +#define USB_STCTRL_A_HNP_TRACK_Msk (0x200UL) /*!< A_HNP_TRACK (Bitfield-Mask: 0x01) */ +#define USB_STCTRL_PU_REMOVED_Pos (10UL) /*!< PU_REMOVED (Bit 10) */ +#define USB_STCTRL_PU_REMOVED_Msk (0x400UL) /*!< PU_REMOVED (Bitfield-Mask: 0x01) */ +#define USB_STCTRL_TMR_CNT_Pos (16UL) /*!< TMR_CNT (Bit 16) */ +#define USB_STCTRL_TMR_CNT_Msk (0xffff0000UL) /*!< TMR_CNT (Bitfield-Mask: 0xffff) */ +/* ========================================================== TMR ========================================================== */ +#define USB_TMR_TIMEOUT_CNT_Pos (0UL) /*!< TIMEOUT_CNT (Bit 0) */ +#define USB_TMR_TIMEOUT_CNT_Msk (0xffffUL) /*!< TIMEOUT_CNT (Bitfield-Mask: 0xffff) */ +/* ======================================================= DEVINTST ======================================================== */ +#define USB_DEVINTST_FRAME_Pos (0UL) /*!< FRAME (Bit 0) */ +#define USB_DEVINTST_FRAME_Msk (0x1UL) /*!< FRAME (Bitfield-Mask: 0x01) */ +#define USB_DEVINTST_EP_FAST_Pos (1UL) /*!< EP_FAST (Bit 1) */ +#define USB_DEVINTST_EP_FAST_Msk (0x2UL) /*!< EP_FAST (Bitfield-Mask: 0x01) */ +#define USB_DEVINTST_EP_SLOW_Pos (2UL) /*!< EP_SLOW (Bit 2) */ +#define USB_DEVINTST_EP_SLOW_Msk (0x4UL) /*!< EP_SLOW (Bitfield-Mask: 0x01) */ +#define USB_DEVINTST_DEV_STAT_Pos (3UL) /*!< DEV_STAT (Bit 3) */ +#define USB_DEVINTST_DEV_STAT_Msk (0x8UL) /*!< DEV_STAT (Bitfield-Mask: 0x01) */ +#define USB_DEVINTST_CCEMPTY_Pos (4UL) /*!< CCEMPTY (Bit 4) */ +#define USB_DEVINTST_CCEMPTY_Msk (0x10UL) /*!< CCEMPTY (Bitfield-Mask: 0x01) */ +#define USB_DEVINTST_CDFULL_Pos (5UL) /*!< CDFULL (Bit 5) */ +#define USB_DEVINTST_CDFULL_Msk (0x20UL) /*!< CDFULL (Bitfield-Mask: 0x01) */ +#define USB_DEVINTST_RxENDPKT_Pos (6UL) /*!< RxENDPKT (Bit 6) */ +#define USB_DEVINTST_RxENDPKT_Msk (0x40UL) /*!< RxENDPKT (Bitfield-Mask: 0x01) */ +#define USB_DEVINTST_TxENDPKT_Pos (7UL) /*!< TxENDPKT (Bit 7) */ +#define USB_DEVINTST_TxENDPKT_Msk (0x80UL) /*!< TxENDPKT (Bitfield-Mask: 0x01) */ +#define USB_DEVINTST_EP_RLZED_Pos (8UL) /*!< EP_RLZED (Bit 8) */ +#define USB_DEVINTST_EP_RLZED_Msk (0x100UL) /*!< EP_RLZED (Bitfield-Mask: 0x01) */ +#define USB_DEVINTST_ERR_INT_Pos (9UL) /*!< ERR_INT (Bit 9) */ +#define USB_DEVINTST_ERR_INT_Msk (0x200UL) /*!< ERR_INT (Bitfield-Mask: 0x01) */ +/* ======================================================= DEVINTEN ======================================================== */ +#define USB_DEVINTEN_FRAMEEN_Pos (0UL) /*!< FRAMEEN (Bit 0) */ +#define USB_DEVINTEN_FRAMEEN_Msk (0x1UL) /*!< FRAMEEN (Bitfield-Mask: 0x01) */ +#define USB_DEVINTEN_EP_FASTEN_Pos (1UL) /*!< EP_FASTEN (Bit 1) */ +#define USB_DEVINTEN_EP_FASTEN_Msk (0x2UL) /*!< EP_FASTEN (Bitfield-Mask: 0x01) */ +#define USB_DEVINTEN_EP_SLOWEN_Pos (2UL) /*!< EP_SLOWEN (Bit 2) */ +#define USB_DEVINTEN_EP_SLOWEN_Msk (0x4UL) /*!< EP_SLOWEN (Bitfield-Mask: 0x01) */ +#define USB_DEVINTEN_DEV_STATEN_Pos (3UL) /*!< DEV_STATEN (Bit 3) */ +#define USB_DEVINTEN_DEV_STATEN_Msk (0x8UL) /*!< DEV_STATEN (Bitfield-Mask: 0x01) */ +#define USB_DEVINTEN_CCEMPTYEN_Pos (4UL) /*!< CCEMPTYEN (Bit 4) */ +#define USB_DEVINTEN_CCEMPTYEN_Msk (0x10UL) /*!< CCEMPTYEN (Bitfield-Mask: 0x01) */ +#define USB_DEVINTEN_CDFULLEN_Pos (5UL) /*!< CDFULLEN (Bit 5) */ +#define USB_DEVINTEN_CDFULLEN_Msk (0x20UL) /*!< CDFULLEN (Bitfield-Mask: 0x01) */ +#define USB_DEVINTEN_RxENDPKTEN_Pos (6UL) /*!< RxENDPKTEN (Bit 6) */ +#define USB_DEVINTEN_RxENDPKTEN_Msk (0x40UL) /*!< RxENDPKTEN (Bitfield-Mask: 0x01) */ +#define USB_DEVINTEN_TxENDPKTEN_Pos (7UL) /*!< TxENDPKTEN (Bit 7) */ +#define USB_DEVINTEN_TxENDPKTEN_Msk (0x80UL) /*!< TxENDPKTEN (Bitfield-Mask: 0x01) */ +#define USB_DEVINTEN_EP_RLZEDEN_Pos (8UL) /*!< EP_RLZEDEN (Bit 8) */ +#define USB_DEVINTEN_EP_RLZEDEN_Msk (0x100UL) /*!< EP_RLZEDEN (Bitfield-Mask: 0x01) */ +#define USB_DEVINTEN_ERR_INTEN_Pos (9UL) /*!< ERR_INTEN (Bit 9) */ +#define USB_DEVINTEN_ERR_INTEN_Msk (0x200UL) /*!< ERR_INTEN (Bitfield-Mask: 0x01) */ +/* ======================================================= DEVINTCLR ======================================================= */ +#define USB_DEVINTCLR_FRAMECLR_Pos (0UL) /*!< FRAMECLR (Bit 0) */ +#define USB_DEVINTCLR_FRAMECLR_Msk (0x1UL) /*!< FRAMECLR (Bitfield-Mask: 0x01) */ +#define USB_DEVINTCLR_EP_FASTCLR_Pos (1UL) /*!< EP_FASTCLR (Bit 1) */ +#define USB_DEVINTCLR_EP_FASTCLR_Msk (0x2UL) /*!< EP_FASTCLR (Bitfield-Mask: 0x01) */ +#define USB_DEVINTCLR_EP_SLOWCLR_Pos (2UL) /*!< EP_SLOWCLR (Bit 2) */ +#define USB_DEVINTCLR_EP_SLOWCLR_Msk (0x4UL) /*!< EP_SLOWCLR (Bitfield-Mask: 0x01) */ +#define USB_DEVINTCLR_DEV_STATCLR_Pos (3UL) /*!< DEV_STATCLR (Bit 3) */ +#define USB_DEVINTCLR_DEV_STATCLR_Msk (0x8UL) /*!< DEV_STATCLR (Bitfield-Mask: 0x01) */ +#define USB_DEVINTCLR_CCEMPTYCLR_Pos (4UL) /*!< CCEMPTYCLR (Bit 4) */ +#define USB_DEVINTCLR_CCEMPTYCLR_Msk (0x10UL) /*!< CCEMPTYCLR (Bitfield-Mask: 0x01) */ +#define USB_DEVINTCLR_CDFULLCLR_Pos (5UL) /*!< CDFULLCLR (Bit 5) */ +#define USB_DEVINTCLR_CDFULLCLR_Msk (0x20UL) /*!< CDFULLCLR (Bitfield-Mask: 0x01) */ +#define USB_DEVINTCLR_RxENDPKTCLR_Pos (6UL) /*!< RxENDPKTCLR (Bit 6) */ +#define USB_DEVINTCLR_RxENDPKTCLR_Msk (0x40UL) /*!< RxENDPKTCLR (Bitfield-Mask: 0x01) */ +#define USB_DEVINTCLR_TxENDPKTCLR_Pos (7UL) /*!< TxENDPKTCLR (Bit 7) */ +#define USB_DEVINTCLR_TxENDPKTCLR_Msk (0x80UL) /*!< TxENDPKTCLR (Bitfield-Mask: 0x01) */ +#define USB_DEVINTCLR_EP_RLZEDCLR_Pos (8UL) /*!< EP_RLZEDCLR (Bit 8) */ +#define USB_DEVINTCLR_EP_RLZEDCLR_Msk (0x100UL) /*!< EP_RLZEDCLR (Bitfield-Mask: 0x01) */ +#define USB_DEVINTCLR_ERR_INTCLR_Pos (9UL) /*!< ERR_INTCLR (Bit 9) */ +#define USB_DEVINTCLR_ERR_INTCLR_Msk (0x200UL) /*!< ERR_INTCLR (Bitfield-Mask: 0x01) */ +/* ======================================================= DEVINTSET ======================================================= */ +#define USB_DEVINTSET_FRAMESET_Pos (0UL) /*!< FRAMESET (Bit 0) */ +#define USB_DEVINTSET_FRAMESET_Msk (0x1UL) /*!< FRAMESET (Bitfield-Mask: 0x01) */ +#define USB_DEVINTSET_EP_FASTSET_Pos (1UL) /*!< EP_FASTSET (Bit 1) */ +#define USB_DEVINTSET_EP_FASTSET_Msk (0x2UL) /*!< EP_FASTSET (Bitfield-Mask: 0x01) */ +#define USB_DEVINTSET_EP_SLOWSET_Pos (2UL) /*!< EP_SLOWSET (Bit 2) */ +#define USB_DEVINTSET_EP_SLOWSET_Msk (0x4UL) /*!< EP_SLOWSET (Bitfield-Mask: 0x01) */ +#define USB_DEVINTSET_DEV_STATSET_Pos (3UL) /*!< DEV_STATSET (Bit 3) */ +#define USB_DEVINTSET_DEV_STATSET_Msk (0x8UL) /*!< DEV_STATSET (Bitfield-Mask: 0x01) */ +#define USB_DEVINTSET_CCEMPTYSET_Pos (4UL) /*!< CCEMPTYSET (Bit 4) */ +#define USB_DEVINTSET_CCEMPTYSET_Msk (0x10UL) /*!< CCEMPTYSET (Bitfield-Mask: 0x01) */ +#define USB_DEVINTSET_CDFULLSET_Pos (5UL) /*!< CDFULLSET (Bit 5) */ +#define USB_DEVINTSET_CDFULLSET_Msk (0x20UL) /*!< CDFULLSET (Bitfield-Mask: 0x01) */ +#define USB_DEVINTSET_RxENDPKTSET_Pos (6UL) /*!< RxENDPKTSET (Bit 6) */ +#define USB_DEVINTSET_RxENDPKTSET_Msk (0x40UL) /*!< RxENDPKTSET (Bitfield-Mask: 0x01) */ +#define USB_DEVINTSET_TxENDPKTSET_Pos (7UL) /*!< TxENDPKTSET (Bit 7) */ +#define USB_DEVINTSET_TxENDPKTSET_Msk (0x80UL) /*!< TxENDPKTSET (Bitfield-Mask: 0x01) */ +#define USB_DEVINTSET_EP_RLZEDSET_Pos (8UL) /*!< EP_RLZEDSET (Bit 8) */ +#define USB_DEVINTSET_EP_RLZEDSET_Msk (0x100UL) /*!< EP_RLZEDSET (Bitfield-Mask: 0x01) */ +#define USB_DEVINTSET_ERR_INTSET_Pos (9UL) /*!< ERR_INTSET (Bit 9) */ +#define USB_DEVINTSET_ERR_INTSET_Msk (0x200UL) /*!< ERR_INTSET (Bitfield-Mask: 0x01) */ +/* ======================================================== CMDCODE ======================================================== */ +#define USB_CMDCODE_CMD_PHASE_Pos (8UL) /*!< CMD_PHASE (Bit 8) */ +#define USB_CMDCODE_CMD_PHASE_Msk (0xff00UL) /*!< CMD_PHASE (Bitfield-Mask: 0xff) */ +#define USB_CMDCODE_CMD_CODE_WDATA_Pos (16UL) /*!< CMD_CODE_WDATA (Bit 16) */ +#define USB_CMDCODE_CMD_CODE_WDATA_Msk (0xff0000UL) /*!< CMD_CODE_WDATA (Bitfield-Mask: 0xff) */ +/* ======================================================== CMDDATA ======================================================== */ +#define USB_CMDDATA_CMD_RDATA_Pos (0UL) /*!< CMD_RDATA (Bit 0) */ +#define USB_CMDDATA_CMD_RDATA_Msk (0xffUL) /*!< CMD_RDATA (Bitfield-Mask: 0xff) */ +/* ======================================================== RXDATA ========================================================= */ +#define USB_RXDATA_RX_DATA_Pos (0UL) /*!< RX_DATA (Bit 0) */ +#define USB_RXDATA_RX_DATA_Msk (0xffffffffUL) /*!< RX_DATA (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== TXDATA ========================================================= */ +#define USB_TXDATA_TX_DATA_Pos (0UL) /*!< TX_DATA (Bit 0) */ +#define USB_TXDATA_TX_DATA_Msk (0xffffffffUL) /*!< TX_DATA (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== RXPLEN ========================================================= */ +#define USB_RXPLEN_PKT_LNGTH_Pos (0UL) /*!< PKT_LNGTH (Bit 0) */ +#define USB_RXPLEN_PKT_LNGTH_Msk (0x3ffUL) /*!< PKT_LNGTH (Bitfield-Mask: 0x3ff) */ +#define USB_RXPLEN_DV_Pos (10UL) /*!< DV (Bit 10) */ +#define USB_RXPLEN_DV_Msk (0x400UL) /*!< DV (Bitfield-Mask: 0x01) */ +#define USB_RXPLEN_PKT_RDY_Pos (11UL) /*!< PKT_RDY (Bit 11) */ +#define USB_RXPLEN_PKT_RDY_Msk (0x800UL) /*!< PKT_RDY (Bitfield-Mask: 0x01) */ +/* ======================================================== TXPLEN ========================================================= */ +#define USB_TXPLEN_PKT_LNGTH_Pos (0UL) /*!< PKT_LNGTH (Bit 0) */ +#define USB_TXPLEN_PKT_LNGTH_Msk (0x3ffUL) /*!< PKT_LNGTH (Bitfield-Mask: 0x3ff) */ +/* ========================================================= CTRL ========================================================== */ +#define USB_CTRL_RD_EN_Pos (0UL) /*!< RD_EN (Bit 0) */ +#define USB_CTRL_RD_EN_Msk (0x1UL) /*!< RD_EN (Bitfield-Mask: 0x01) */ +#define USB_CTRL_WR_EN_Pos (1UL) /*!< WR_EN (Bit 1) */ +#define USB_CTRL_WR_EN_Msk (0x2UL) /*!< WR_EN (Bitfield-Mask: 0x01) */ +#define USB_CTRL_LOG_ENDPOINT_Pos (2UL) /*!< LOG_ENDPOINT (Bit 2) */ +#define USB_CTRL_LOG_ENDPOINT_Msk (0x3cUL) /*!< LOG_ENDPOINT (Bitfield-Mask: 0x0f) */ +/* ======================================================= DEVINTPRI ======================================================= */ +#define USB_DEVINTPRI_FRAME_Pos (0UL) /*!< FRAME (Bit 0) */ +#define USB_DEVINTPRI_FRAME_Msk (0x1UL) /*!< FRAME (Bitfield-Mask: 0x01) */ +#define USB_DEVINTPRI_EP_FAST_Pos (1UL) /*!< EP_FAST (Bit 1) */ +#define USB_DEVINTPRI_EP_FAST_Msk (0x2UL) /*!< EP_FAST (Bitfield-Mask: 0x01) */ +/* ======================================================== EPINTST ======================================================== */ +#define USB_EPINTST_EPST0_Pos (0UL) /*!< EPST0 (Bit 0) */ +#define USB_EPINTST_EPST0_Msk (0x1UL) /*!< EPST0 (Bitfield-Mask: 0x01) */ +#define USB_EPINTST_EPST1_Pos (1UL) /*!< EPST1 (Bit 1) */ +#define USB_EPINTST_EPST1_Msk (0x2UL) /*!< EPST1 (Bitfield-Mask: 0x01) */ +#define USB_EPINTST_EPST2_Pos (2UL) /*!< EPST2 (Bit 2) */ +#define USB_EPINTST_EPST2_Msk (0x4UL) /*!< EPST2 (Bitfield-Mask: 0x01) */ +#define USB_EPINTST_EPST3_Pos (3UL) /*!< EPST3 (Bit 3) */ +#define USB_EPINTST_EPST3_Msk (0x8UL) /*!< EPST3 (Bitfield-Mask: 0x01) */ +#define USB_EPINTST_EPST4_Pos (4UL) /*!< EPST4 (Bit 4) */ +#define USB_EPINTST_EPST4_Msk (0x10UL) /*!< EPST4 (Bitfield-Mask: 0x01) */ +#define USB_EPINTST_EPST5_Pos (5UL) /*!< EPST5 (Bit 5) */ +#define USB_EPINTST_EPST5_Msk (0x20UL) /*!< EPST5 (Bitfield-Mask: 0x01) */ +#define USB_EPINTST_EPST6_Pos (6UL) /*!< EPST6 (Bit 6) */ +#define USB_EPINTST_EPST6_Msk (0x40UL) /*!< EPST6 (Bitfield-Mask: 0x01) */ +#define USB_EPINTST_EPST7_Pos (7UL) /*!< EPST7 (Bit 7) */ +#define USB_EPINTST_EPST7_Msk (0x80UL) /*!< EPST7 (Bitfield-Mask: 0x01) */ +#define USB_EPINTST_EPST8_Pos (8UL) /*!< EPST8 (Bit 8) */ +#define USB_EPINTST_EPST8_Msk (0x100UL) /*!< EPST8 (Bitfield-Mask: 0x01) */ +#define USB_EPINTST_EPST9_Pos (9UL) /*!< EPST9 (Bit 9) */ +#define USB_EPINTST_EPST9_Msk (0x200UL) /*!< EPST9 (Bitfield-Mask: 0x01) */ +#define USB_EPINTST_EPST10_Pos (10UL) /*!< EPST10 (Bit 10) */ +#define USB_EPINTST_EPST10_Msk (0x400UL) /*!< EPST10 (Bitfield-Mask: 0x01) */ +#define USB_EPINTST_EPST11_Pos (11UL) /*!< EPST11 (Bit 11) */ +#define USB_EPINTST_EPST11_Msk (0x800UL) /*!< EPST11 (Bitfield-Mask: 0x01) */ +#define USB_EPINTST_EPST12_Pos (12UL) /*!< EPST12 (Bit 12) */ +#define USB_EPINTST_EPST12_Msk (0x1000UL) /*!< EPST12 (Bitfield-Mask: 0x01) */ +#define USB_EPINTST_EPST13_Pos (13UL) /*!< EPST13 (Bit 13) */ +#define USB_EPINTST_EPST13_Msk (0x2000UL) /*!< EPST13 (Bitfield-Mask: 0x01) */ +#define USB_EPINTST_EPST14_Pos (14UL) /*!< EPST14 (Bit 14) */ +#define USB_EPINTST_EPST14_Msk (0x4000UL) /*!< EPST14 (Bitfield-Mask: 0x01) */ +#define USB_EPINTST_EPST15_Pos (15UL) /*!< EPST15 (Bit 15) */ +#define USB_EPINTST_EPST15_Msk (0x8000UL) /*!< EPST15 (Bitfield-Mask: 0x01) */ +#define USB_EPINTST_EPST16_Pos (16UL) /*!< EPST16 (Bit 16) */ +#define USB_EPINTST_EPST16_Msk (0x10000UL) /*!< EPST16 (Bitfield-Mask: 0x01) */ +#define USB_EPINTST_EPST17_Pos (17UL) /*!< EPST17 (Bit 17) */ +#define USB_EPINTST_EPST17_Msk (0x20000UL) /*!< EPST17 (Bitfield-Mask: 0x01) */ +#define USB_EPINTST_EPST18_Pos (18UL) /*!< EPST18 (Bit 18) */ +#define USB_EPINTST_EPST18_Msk (0x40000UL) /*!< EPST18 (Bitfield-Mask: 0x01) */ +#define USB_EPINTST_EPST19_Pos (19UL) /*!< EPST19 (Bit 19) */ +#define USB_EPINTST_EPST19_Msk (0x80000UL) /*!< EPST19 (Bitfield-Mask: 0x01) */ +#define USB_EPINTST_EPST20_Pos (20UL) /*!< EPST20 (Bit 20) */ +#define USB_EPINTST_EPST20_Msk (0x100000UL) /*!< EPST20 (Bitfield-Mask: 0x01) */ +#define USB_EPINTST_EPST21_Pos (21UL) /*!< EPST21 (Bit 21) */ +#define USB_EPINTST_EPST21_Msk (0x200000UL) /*!< EPST21 (Bitfield-Mask: 0x01) */ +#define USB_EPINTST_EPST22_Pos (22UL) /*!< EPST22 (Bit 22) */ +#define USB_EPINTST_EPST22_Msk (0x400000UL) /*!< EPST22 (Bitfield-Mask: 0x01) */ +#define USB_EPINTST_EPST23_Pos (23UL) /*!< EPST23 (Bit 23) */ +#define USB_EPINTST_EPST23_Msk (0x800000UL) /*!< EPST23 (Bitfield-Mask: 0x01) */ +#define USB_EPINTST_EPST24_Pos (24UL) /*!< EPST24 (Bit 24) */ +#define USB_EPINTST_EPST24_Msk (0x1000000UL) /*!< EPST24 (Bitfield-Mask: 0x01) */ +#define USB_EPINTST_EPST25_Pos (25UL) /*!< EPST25 (Bit 25) */ +#define USB_EPINTST_EPST25_Msk (0x2000000UL) /*!< EPST25 (Bitfield-Mask: 0x01) */ +#define USB_EPINTST_EPST26_Pos (26UL) /*!< EPST26 (Bit 26) */ +#define USB_EPINTST_EPST26_Msk (0x4000000UL) /*!< EPST26 (Bitfield-Mask: 0x01) */ +#define USB_EPINTST_EPST27_Pos (27UL) /*!< EPST27 (Bit 27) */ +#define USB_EPINTST_EPST27_Msk (0x8000000UL) /*!< EPST27 (Bitfield-Mask: 0x01) */ +#define USB_EPINTST_EPST28_Pos (28UL) /*!< EPST28 (Bit 28) */ +#define USB_EPINTST_EPST28_Msk (0x10000000UL) /*!< EPST28 (Bitfield-Mask: 0x01) */ +#define USB_EPINTST_EPST29_Pos (29UL) /*!< EPST29 (Bit 29) */ +#define USB_EPINTST_EPST29_Msk (0x20000000UL) /*!< EPST29 (Bitfield-Mask: 0x01) */ +#define USB_EPINTST_EPST30_Pos (30UL) /*!< EPST30 (Bit 30) */ +#define USB_EPINTST_EPST30_Msk (0x40000000UL) /*!< EPST30 (Bitfield-Mask: 0x01) */ +#define USB_EPINTST_EPST31_Pos (31UL) /*!< EPST31 (Bit 31) */ +#define USB_EPINTST_EPST31_Msk (0x80000000UL) /*!< EPST31 (Bitfield-Mask: 0x01) */ +/* ======================================================== EPINTEN ======================================================== */ +#define USB_EPINTEN_EPEN0_Pos (0UL) /*!< EPEN0 (Bit 0) */ +#define USB_EPINTEN_EPEN0_Msk (0x1UL) /*!< EPEN0 (Bitfield-Mask: 0x01) */ +#define USB_EPINTEN_EPEN1_Pos (1UL) /*!< EPEN1 (Bit 1) */ +#define USB_EPINTEN_EPEN1_Msk (0x2UL) /*!< EPEN1 (Bitfield-Mask: 0x01) */ +#define USB_EPINTEN_EPEN2_Pos (2UL) /*!< EPEN2 (Bit 2) */ +#define USB_EPINTEN_EPEN2_Msk (0x4UL) /*!< EPEN2 (Bitfield-Mask: 0x01) */ +#define USB_EPINTEN_EPEN3_Pos (3UL) /*!< EPEN3 (Bit 3) */ +#define USB_EPINTEN_EPEN3_Msk (0x8UL) /*!< EPEN3 (Bitfield-Mask: 0x01) */ +#define USB_EPINTEN_EPEN4_Pos (4UL) /*!< EPEN4 (Bit 4) */ +#define USB_EPINTEN_EPEN4_Msk (0x10UL) /*!< EPEN4 (Bitfield-Mask: 0x01) */ +#define USB_EPINTEN_EPEN5_Pos (5UL) /*!< EPEN5 (Bit 5) */ +#define USB_EPINTEN_EPEN5_Msk (0x20UL) /*!< EPEN5 (Bitfield-Mask: 0x01) */ +#define USB_EPINTEN_EPEN6_Pos (6UL) /*!< EPEN6 (Bit 6) */ +#define USB_EPINTEN_EPEN6_Msk (0x40UL) /*!< EPEN6 (Bitfield-Mask: 0x01) */ +#define USB_EPINTEN_EPEN7_Pos (7UL) /*!< EPEN7 (Bit 7) */ +#define USB_EPINTEN_EPEN7_Msk (0x80UL) /*!< EPEN7 (Bitfield-Mask: 0x01) */ +#define USB_EPINTEN_EPEN8_Pos (8UL) /*!< EPEN8 (Bit 8) */ +#define USB_EPINTEN_EPEN8_Msk (0x100UL) /*!< EPEN8 (Bitfield-Mask: 0x01) */ +#define USB_EPINTEN_EPEN9_Pos (9UL) /*!< EPEN9 (Bit 9) */ +#define USB_EPINTEN_EPEN9_Msk (0x200UL) /*!< EPEN9 (Bitfield-Mask: 0x01) */ +#define USB_EPINTEN_EPEN10_Pos (10UL) /*!< EPEN10 (Bit 10) */ +#define USB_EPINTEN_EPEN10_Msk (0x400UL) /*!< EPEN10 (Bitfield-Mask: 0x01) */ +#define USB_EPINTEN_EPEN11_Pos (11UL) /*!< EPEN11 (Bit 11) */ +#define USB_EPINTEN_EPEN11_Msk (0x800UL) /*!< EPEN11 (Bitfield-Mask: 0x01) */ +#define USB_EPINTEN_EPEN12_Pos (12UL) /*!< EPEN12 (Bit 12) */ +#define USB_EPINTEN_EPEN12_Msk (0x1000UL) /*!< EPEN12 (Bitfield-Mask: 0x01) */ +#define USB_EPINTEN_EPEN13_Pos (13UL) /*!< EPEN13 (Bit 13) */ +#define USB_EPINTEN_EPEN13_Msk (0x2000UL) /*!< EPEN13 (Bitfield-Mask: 0x01) */ +#define USB_EPINTEN_EPEN14_Pos (14UL) /*!< EPEN14 (Bit 14) */ +#define USB_EPINTEN_EPEN14_Msk (0x4000UL) /*!< EPEN14 (Bitfield-Mask: 0x01) */ +#define USB_EPINTEN_EPEN15_Pos (15UL) /*!< EPEN15 (Bit 15) */ +#define USB_EPINTEN_EPEN15_Msk (0x8000UL) /*!< EPEN15 (Bitfield-Mask: 0x01) */ +#define USB_EPINTEN_EPEN16_Pos (16UL) /*!< EPEN16 (Bit 16) */ +#define USB_EPINTEN_EPEN16_Msk (0x10000UL) /*!< EPEN16 (Bitfield-Mask: 0x01) */ +#define USB_EPINTEN_EPEN17_Pos (17UL) /*!< EPEN17 (Bit 17) */ +#define USB_EPINTEN_EPEN17_Msk (0x20000UL) /*!< EPEN17 (Bitfield-Mask: 0x01) */ +#define USB_EPINTEN_EPEN18_Pos (18UL) /*!< EPEN18 (Bit 18) */ +#define USB_EPINTEN_EPEN18_Msk (0x40000UL) /*!< EPEN18 (Bitfield-Mask: 0x01) */ +#define USB_EPINTEN_EPEN19_Pos (19UL) /*!< EPEN19 (Bit 19) */ +#define USB_EPINTEN_EPEN19_Msk (0x80000UL) /*!< EPEN19 (Bitfield-Mask: 0x01) */ +#define USB_EPINTEN_EPEN20_Pos (20UL) /*!< EPEN20 (Bit 20) */ +#define USB_EPINTEN_EPEN20_Msk (0x100000UL) /*!< EPEN20 (Bitfield-Mask: 0x01) */ +#define USB_EPINTEN_EPEN21_Pos (21UL) /*!< EPEN21 (Bit 21) */ +#define USB_EPINTEN_EPEN21_Msk (0x200000UL) /*!< EPEN21 (Bitfield-Mask: 0x01) */ +#define USB_EPINTEN_EPEN22_Pos (22UL) /*!< EPEN22 (Bit 22) */ +#define USB_EPINTEN_EPEN22_Msk (0x400000UL) /*!< EPEN22 (Bitfield-Mask: 0x01) */ +#define USB_EPINTEN_EPEN23_Pos (23UL) /*!< EPEN23 (Bit 23) */ +#define USB_EPINTEN_EPEN23_Msk (0x800000UL) /*!< EPEN23 (Bitfield-Mask: 0x01) */ +#define USB_EPINTEN_EPEN24_Pos (24UL) /*!< EPEN24 (Bit 24) */ +#define USB_EPINTEN_EPEN24_Msk (0x1000000UL) /*!< EPEN24 (Bitfield-Mask: 0x01) */ +#define USB_EPINTEN_EPEN25_Pos (25UL) /*!< EPEN25 (Bit 25) */ +#define USB_EPINTEN_EPEN25_Msk (0x2000000UL) /*!< EPEN25 (Bitfield-Mask: 0x01) */ +#define USB_EPINTEN_EPEN26_Pos (26UL) /*!< EPEN26 (Bit 26) */ +#define USB_EPINTEN_EPEN26_Msk (0x4000000UL) /*!< EPEN26 (Bitfield-Mask: 0x01) */ +#define USB_EPINTEN_EPEN27_Pos (27UL) /*!< EPEN27 (Bit 27) */ +#define USB_EPINTEN_EPEN27_Msk (0x8000000UL) /*!< EPEN27 (Bitfield-Mask: 0x01) */ +#define USB_EPINTEN_EPEN28_Pos (28UL) /*!< EPEN28 (Bit 28) */ +#define USB_EPINTEN_EPEN28_Msk (0x10000000UL) /*!< EPEN28 (Bitfield-Mask: 0x01) */ +#define USB_EPINTEN_EPEN29_Pos (29UL) /*!< EPEN29 (Bit 29) */ +#define USB_EPINTEN_EPEN29_Msk (0x20000000UL) /*!< EPEN29 (Bitfield-Mask: 0x01) */ +#define USB_EPINTEN_EPEN30_Pos (30UL) /*!< EPEN30 (Bit 30) */ +#define USB_EPINTEN_EPEN30_Msk (0x40000000UL) /*!< EPEN30 (Bitfield-Mask: 0x01) */ +#define USB_EPINTEN_EPEN31_Pos (31UL) /*!< EPEN31 (Bit 31) */ +#define USB_EPINTEN_EPEN31_Msk (0x80000000UL) /*!< EPEN31 (Bitfield-Mask: 0x01) */ +/* ======================================================= EPINTCLR ======================================================== */ +#define USB_EPINTCLR_EPCLR0_Pos (0UL) /*!< EPCLR0 (Bit 0) */ +#define USB_EPINTCLR_EPCLR0_Msk (0x1UL) /*!< EPCLR0 (Bitfield-Mask: 0x01) */ +#define USB_EPINTCLR_EPCLR1_Pos (1UL) /*!< EPCLR1 (Bit 1) */ +#define USB_EPINTCLR_EPCLR1_Msk (0x2UL) /*!< EPCLR1 (Bitfield-Mask: 0x01) */ +#define USB_EPINTCLR_EPCLR2_Pos (2UL) /*!< EPCLR2 (Bit 2) */ +#define USB_EPINTCLR_EPCLR2_Msk (0x4UL) /*!< EPCLR2 (Bitfield-Mask: 0x01) */ +#define USB_EPINTCLR_EPCLR3_Pos (3UL) /*!< EPCLR3 (Bit 3) */ +#define USB_EPINTCLR_EPCLR3_Msk (0x8UL) /*!< EPCLR3 (Bitfield-Mask: 0x01) */ +#define USB_EPINTCLR_EPCLR4_Pos (4UL) /*!< EPCLR4 (Bit 4) */ +#define USB_EPINTCLR_EPCLR4_Msk (0x10UL) /*!< EPCLR4 (Bitfield-Mask: 0x01) */ +#define USB_EPINTCLR_EPCLR5_Pos (5UL) /*!< EPCLR5 (Bit 5) */ +#define USB_EPINTCLR_EPCLR5_Msk (0x20UL) /*!< EPCLR5 (Bitfield-Mask: 0x01) */ +#define USB_EPINTCLR_EPCLR6_Pos (6UL) /*!< EPCLR6 (Bit 6) */ +#define USB_EPINTCLR_EPCLR6_Msk (0x40UL) /*!< EPCLR6 (Bitfield-Mask: 0x01) */ +#define USB_EPINTCLR_EPCLR7_Pos (7UL) /*!< EPCLR7 (Bit 7) */ +#define USB_EPINTCLR_EPCLR7_Msk (0x80UL) /*!< EPCLR7 (Bitfield-Mask: 0x01) */ +#define USB_EPINTCLR_EPCLR8_Pos (8UL) /*!< EPCLR8 (Bit 8) */ +#define USB_EPINTCLR_EPCLR8_Msk (0x100UL) /*!< EPCLR8 (Bitfield-Mask: 0x01) */ +#define USB_EPINTCLR_EPCLR9_Pos (9UL) /*!< EPCLR9 (Bit 9) */ +#define USB_EPINTCLR_EPCLR9_Msk (0x200UL) /*!< EPCLR9 (Bitfield-Mask: 0x01) */ +#define USB_EPINTCLR_EPCLR10_Pos (10UL) /*!< EPCLR10 (Bit 10) */ +#define USB_EPINTCLR_EPCLR10_Msk (0x400UL) /*!< EPCLR10 (Bitfield-Mask: 0x01) */ +#define USB_EPINTCLR_EPCLR11_Pos (11UL) /*!< EPCLR11 (Bit 11) */ +#define USB_EPINTCLR_EPCLR11_Msk (0x800UL) /*!< EPCLR11 (Bitfield-Mask: 0x01) */ +#define USB_EPINTCLR_EPCLR12_Pos (12UL) /*!< EPCLR12 (Bit 12) */ +#define USB_EPINTCLR_EPCLR12_Msk (0x1000UL) /*!< EPCLR12 (Bitfield-Mask: 0x01) */ +#define USB_EPINTCLR_EPCLR13_Pos (13UL) /*!< EPCLR13 (Bit 13) */ +#define USB_EPINTCLR_EPCLR13_Msk (0x2000UL) /*!< EPCLR13 (Bitfield-Mask: 0x01) */ +#define USB_EPINTCLR_EPCLR14_Pos (14UL) /*!< EPCLR14 (Bit 14) */ +#define USB_EPINTCLR_EPCLR14_Msk (0x4000UL) /*!< EPCLR14 (Bitfield-Mask: 0x01) */ +#define USB_EPINTCLR_EPCLR15_Pos (15UL) /*!< EPCLR15 (Bit 15) */ +#define USB_EPINTCLR_EPCLR15_Msk (0x8000UL) /*!< EPCLR15 (Bitfield-Mask: 0x01) */ +#define USB_EPINTCLR_EPCLR16_Pos (16UL) /*!< EPCLR16 (Bit 16) */ +#define USB_EPINTCLR_EPCLR16_Msk (0x10000UL) /*!< EPCLR16 (Bitfield-Mask: 0x01) */ +#define USB_EPINTCLR_EPCLR17_Pos (17UL) /*!< EPCLR17 (Bit 17) */ +#define USB_EPINTCLR_EPCLR17_Msk (0x20000UL) /*!< EPCLR17 (Bitfield-Mask: 0x01) */ +#define USB_EPINTCLR_EPCLR18_Pos (18UL) /*!< EPCLR18 (Bit 18) */ +#define USB_EPINTCLR_EPCLR18_Msk (0x40000UL) /*!< EPCLR18 (Bitfield-Mask: 0x01) */ +#define USB_EPINTCLR_EPCLR19_Pos (19UL) /*!< EPCLR19 (Bit 19) */ +#define USB_EPINTCLR_EPCLR19_Msk (0x80000UL) /*!< EPCLR19 (Bitfield-Mask: 0x01) */ +#define USB_EPINTCLR_EPCLR20_Pos (20UL) /*!< EPCLR20 (Bit 20) */ +#define USB_EPINTCLR_EPCLR20_Msk (0x100000UL) /*!< EPCLR20 (Bitfield-Mask: 0x01) */ +#define USB_EPINTCLR_EPCLR21_Pos (21UL) /*!< EPCLR21 (Bit 21) */ +#define USB_EPINTCLR_EPCLR21_Msk (0x200000UL) /*!< EPCLR21 (Bitfield-Mask: 0x01) */ +#define USB_EPINTCLR_EPCLR22_Pos (22UL) /*!< EPCLR22 (Bit 22) */ +#define USB_EPINTCLR_EPCLR22_Msk (0x400000UL) /*!< EPCLR22 (Bitfield-Mask: 0x01) */ +#define USB_EPINTCLR_EPCLR23_Pos (23UL) /*!< EPCLR23 (Bit 23) */ +#define USB_EPINTCLR_EPCLR23_Msk (0x800000UL) /*!< EPCLR23 (Bitfield-Mask: 0x01) */ +#define USB_EPINTCLR_EPCLR24_Pos (24UL) /*!< EPCLR24 (Bit 24) */ +#define USB_EPINTCLR_EPCLR24_Msk (0x1000000UL) /*!< EPCLR24 (Bitfield-Mask: 0x01) */ +#define USB_EPINTCLR_EPCLR25_Pos (25UL) /*!< EPCLR25 (Bit 25) */ +#define USB_EPINTCLR_EPCLR25_Msk (0x2000000UL) /*!< EPCLR25 (Bitfield-Mask: 0x01) */ +#define USB_EPINTCLR_EPCLR26_Pos (26UL) /*!< EPCLR26 (Bit 26) */ +#define USB_EPINTCLR_EPCLR26_Msk (0x4000000UL) /*!< EPCLR26 (Bitfield-Mask: 0x01) */ +#define USB_EPINTCLR_EPCLR27_Pos (27UL) /*!< EPCLR27 (Bit 27) */ +#define USB_EPINTCLR_EPCLR27_Msk (0x8000000UL) /*!< EPCLR27 (Bitfield-Mask: 0x01) */ +#define USB_EPINTCLR_EPCLR28_Pos (28UL) /*!< EPCLR28 (Bit 28) */ +#define USB_EPINTCLR_EPCLR28_Msk (0x10000000UL) /*!< EPCLR28 (Bitfield-Mask: 0x01) */ +#define USB_EPINTCLR_EPCLR29_Pos (29UL) /*!< EPCLR29 (Bit 29) */ +#define USB_EPINTCLR_EPCLR29_Msk (0x20000000UL) /*!< EPCLR29 (Bitfield-Mask: 0x01) */ +#define USB_EPINTCLR_EPCLR30_Pos (30UL) /*!< EPCLR30 (Bit 30) */ +#define USB_EPINTCLR_EPCLR30_Msk (0x40000000UL) /*!< EPCLR30 (Bitfield-Mask: 0x01) */ +#define USB_EPINTCLR_EPCLR31_Pos (31UL) /*!< EPCLR31 (Bit 31) */ +#define USB_EPINTCLR_EPCLR31_Msk (0x80000000UL) /*!< EPCLR31 (Bitfield-Mask: 0x01) */ +/* ======================================================= EPINTSET ======================================================== */ +#define USB_EPINTSET_EPSET0_Pos (0UL) /*!< EPSET0 (Bit 0) */ +#define USB_EPINTSET_EPSET0_Msk (0x1UL) /*!< EPSET0 (Bitfield-Mask: 0x01) */ +#define USB_EPINTSET_EPSET1_Pos (1UL) /*!< EPSET1 (Bit 1) */ +#define USB_EPINTSET_EPSET1_Msk (0x2UL) /*!< EPSET1 (Bitfield-Mask: 0x01) */ +#define USB_EPINTSET_EPSET2_Pos (2UL) /*!< EPSET2 (Bit 2) */ +#define USB_EPINTSET_EPSET2_Msk (0x4UL) /*!< EPSET2 (Bitfield-Mask: 0x01) */ +#define USB_EPINTSET_EPSET3_Pos (3UL) /*!< EPSET3 (Bit 3) */ +#define USB_EPINTSET_EPSET3_Msk (0x8UL) /*!< EPSET3 (Bitfield-Mask: 0x01) */ +#define USB_EPINTSET_EPSET4_Pos (4UL) /*!< EPSET4 (Bit 4) */ +#define USB_EPINTSET_EPSET4_Msk (0x10UL) /*!< EPSET4 (Bitfield-Mask: 0x01) */ +#define USB_EPINTSET_EPSET5_Pos (5UL) /*!< EPSET5 (Bit 5) */ +#define USB_EPINTSET_EPSET5_Msk (0x20UL) /*!< EPSET5 (Bitfield-Mask: 0x01) */ +#define USB_EPINTSET_EPSET6_Pos (6UL) /*!< EPSET6 (Bit 6) */ +#define USB_EPINTSET_EPSET6_Msk (0x40UL) /*!< EPSET6 (Bitfield-Mask: 0x01) */ +#define USB_EPINTSET_EPSET7_Pos (7UL) /*!< EPSET7 (Bit 7) */ +#define USB_EPINTSET_EPSET7_Msk (0x80UL) /*!< EPSET7 (Bitfield-Mask: 0x01) */ +#define USB_EPINTSET_EPSET8_Pos (8UL) /*!< EPSET8 (Bit 8) */ +#define USB_EPINTSET_EPSET8_Msk (0x100UL) /*!< EPSET8 (Bitfield-Mask: 0x01) */ +#define USB_EPINTSET_EPSET9_Pos (9UL) /*!< EPSET9 (Bit 9) */ +#define USB_EPINTSET_EPSET9_Msk (0x200UL) /*!< EPSET9 (Bitfield-Mask: 0x01) */ +#define USB_EPINTSET_EPSET10_Pos (10UL) /*!< EPSET10 (Bit 10) */ +#define USB_EPINTSET_EPSET10_Msk (0x400UL) /*!< EPSET10 (Bitfield-Mask: 0x01) */ +#define USB_EPINTSET_EPSET11_Pos (11UL) /*!< EPSET11 (Bit 11) */ +#define USB_EPINTSET_EPSET11_Msk (0x800UL) /*!< EPSET11 (Bitfield-Mask: 0x01) */ +#define USB_EPINTSET_EPSET12_Pos (12UL) /*!< EPSET12 (Bit 12) */ +#define USB_EPINTSET_EPSET12_Msk (0x1000UL) /*!< EPSET12 (Bitfield-Mask: 0x01) */ +#define USB_EPINTSET_EPSET13_Pos (13UL) /*!< EPSET13 (Bit 13) */ +#define USB_EPINTSET_EPSET13_Msk (0x2000UL) /*!< EPSET13 (Bitfield-Mask: 0x01) */ +#define USB_EPINTSET_EPSET14_Pos (14UL) /*!< EPSET14 (Bit 14) */ +#define USB_EPINTSET_EPSET14_Msk (0x4000UL) /*!< EPSET14 (Bitfield-Mask: 0x01) */ +#define USB_EPINTSET_EPSET15_Pos (15UL) /*!< EPSET15 (Bit 15) */ +#define USB_EPINTSET_EPSET15_Msk (0x8000UL) /*!< EPSET15 (Bitfield-Mask: 0x01) */ +#define USB_EPINTSET_EPSET16_Pos (16UL) /*!< EPSET16 (Bit 16) */ +#define USB_EPINTSET_EPSET16_Msk (0x10000UL) /*!< EPSET16 (Bitfield-Mask: 0x01) */ +#define USB_EPINTSET_EPSET17_Pos (17UL) /*!< EPSET17 (Bit 17) */ +#define USB_EPINTSET_EPSET17_Msk (0x20000UL) /*!< EPSET17 (Bitfield-Mask: 0x01) */ +#define USB_EPINTSET_EPSET18_Pos (18UL) /*!< EPSET18 (Bit 18) */ +#define USB_EPINTSET_EPSET18_Msk (0x40000UL) /*!< EPSET18 (Bitfield-Mask: 0x01) */ +#define USB_EPINTSET_EPSET19_Pos (19UL) /*!< EPSET19 (Bit 19) */ +#define USB_EPINTSET_EPSET19_Msk (0x80000UL) /*!< EPSET19 (Bitfield-Mask: 0x01) */ +#define USB_EPINTSET_EPSET20_Pos (20UL) /*!< EPSET20 (Bit 20) */ +#define USB_EPINTSET_EPSET20_Msk (0x100000UL) /*!< EPSET20 (Bitfield-Mask: 0x01) */ +#define USB_EPINTSET_EPSET21_Pos (21UL) /*!< EPSET21 (Bit 21) */ +#define USB_EPINTSET_EPSET21_Msk (0x200000UL) /*!< EPSET21 (Bitfield-Mask: 0x01) */ +#define USB_EPINTSET_EPSET22_Pos (22UL) /*!< EPSET22 (Bit 22) */ +#define USB_EPINTSET_EPSET22_Msk (0x400000UL) /*!< EPSET22 (Bitfield-Mask: 0x01) */ +#define USB_EPINTSET_EPSET23_Pos (23UL) /*!< EPSET23 (Bit 23) */ +#define USB_EPINTSET_EPSET23_Msk (0x800000UL) /*!< EPSET23 (Bitfield-Mask: 0x01) */ +#define USB_EPINTSET_EPSET24_Pos (24UL) /*!< EPSET24 (Bit 24) */ +#define USB_EPINTSET_EPSET24_Msk (0x1000000UL) /*!< EPSET24 (Bitfield-Mask: 0x01) */ +#define USB_EPINTSET_EPSET25_Pos (25UL) /*!< EPSET25 (Bit 25) */ +#define USB_EPINTSET_EPSET25_Msk (0x2000000UL) /*!< EPSET25 (Bitfield-Mask: 0x01) */ +#define USB_EPINTSET_EPSET26_Pos (26UL) /*!< EPSET26 (Bit 26) */ +#define USB_EPINTSET_EPSET26_Msk (0x4000000UL) /*!< EPSET26 (Bitfield-Mask: 0x01) */ +#define USB_EPINTSET_EPSET27_Pos (27UL) /*!< EPSET27 (Bit 27) */ +#define USB_EPINTSET_EPSET27_Msk (0x8000000UL) /*!< EPSET27 (Bitfield-Mask: 0x01) */ +#define USB_EPINTSET_EPSET28_Pos (28UL) /*!< EPSET28 (Bit 28) */ +#define USB_EPINTSET_EPSET28_Msk (0x10000000UL) /*!< EPSET28 (Bitfield-Mask: 0x01) */ +#define USB_EPINTSET_EPSET29_Pos (29UL) /*!< EPSET29 (Bit 29) */ +#define USB_EPINTSET_EPSET29_Msk (0x20000000UL) /*!< EPSET29 (Bitfield-Mask: 0x01) */ +#define USB_EPINTSET_EPSET30_Pos (30UL) /*!< EPSET30 (Bit 30) */ +#define USB_EPINTSET_EPSET30_Msk (0x40000000UL) /*!< EPSET30 (Bitfield-Mask: 0x01) */ +#define USB_EPINTSET_EPSET31_Pos (31UL) /*!< EPSET31 (Bit 31) */ +#define USB_EPINTSET_EPSET31_Msk (0x80000000UL) /*!< EPSET31 (Bitfield-Mask: 0x01) */ +/* ======================================================= EPINTPRI ======================================================== */ +#define USB_EPINTPRI_EPPRI0_Pos (0UL) /*!< EPPRI0 (Bit 0) */ +#define USB_EPINTPRI_EPPRI0_Msk (0x1UL) /*!< EPPRI0 (Bitfield-Mask: 0x01) */ +#define USB_EPINTPRI_EPPRI1_Pos (1UL) /*!< EPPRI1 (Bit 1) */ +#define USB_EPINTPRI_EPPRI1_Msk (0x2UL) /*!< EPPRI1 (Bitfield-Mask: 0x01) */ +#define USB_EPINTPRI_EPPRI2_Pos (2UL) /*!< EPPRI2 (Bit 2) */ +#define USB_EPINTPRI_EPPRI2_Msk (0x4UL) /*!< EPPRI2 (Bitfield-Mask: 0x01) */ +#define USB_EPINTPRI_EPPRI3_Pos (3UL) /*!< EPPRI3 (Bit 3) */ +#define USB_EPINTPRI_EPPRI3_Msk (0x8UL) /*!< EPPRI3 (Bitfield-Mask: 0x01) */ +#define USB_EPINTPRI_EPPRI4_Pos (4UL) /*!< EPPRI4 (Bit 4) */ +#define USB_EPINTPRI_EPPRI4_Msk (0x10UL) /*!< EPPRI4 (Bitfield-Mask: 0x01) */ +#define USB_EPINTPRI_EPPRI5_Pos (5UL) /*!< EPPRI5 (Bit 5) */ +#define USB_EPINTPRI_EPPRI5_Msk (0x20UL) /*!< EPPRI5 (Bitfield-Mask: 0x01) */ +#define USB_EPINTPRI_EPPRI6_Pos (6UL) /*!< EPPRI6 (Bit 6) */ +#define USB_EPINTPRI_EPPRI6_Msk (0x40UL) /*!< EPPRI6 (Bitfield-Mask: 0x01) */ +#define USB_EPINTPRI_EPPRI7_Pos (7UL) /*!< EPPRI7 (Bit 7) */ +#define USB_EPINTPRI_EPPRI7_Msk (0x80UL) /*!< EPPRI7 (Bitfield-Mask: 0x01) */ +#define USB_EPINTPRI_EPPRI8_Pos (8UL) /*!< EPPRI8 (Bit 8) */ +#define USB_EPINTPRI_EPPRI8_Msk (0x100UL) /*!< EPPRI8 (Bitfield-Mask: 0x01) */ +#define USB_EPINTPRI_EPPRI9_Pos (9UL) /*!< EPPRI9 (Bit 9) */ +#define USB_EPINTPRI_EPPRI9_Msk (0x200UL) /*!< EPPRI9 (Bitfield-Mask: 0x01) */ +#define USB_EPINTPRI_EPPRI10_Pos (10UL) /*!< EPPRI10 (Bit 10) */ +#define USB_EPINTPRI_EPPRI10_Msk (0x400UL) /*!< EPPRI10 (Bitfield-Mask: 0x01) */ +#define USB_EPINTPRI_EPPRI11_Pos (11UL) /*!< EPPRI11 (Bit 11) */ +#define USB_EPINTPRI_EPPRI11_Msk (0x800UL) /*!< EPPRI11 (Bitfield-Mask: 0x01) */ +#define USB_EPINTPRI_EPPRI12_Pos (12UL) /*!< EPPRI12 (Bit 12) */ +#define USB_EPINTPRI_EPPRI12_Msk (0x1000UL) /*!< EPPRI12 (Bitfield-Mask: 0x01) */ +#define USB_EPINTPRI_EPPRI13_Pos (13UL) /*!< EPPRI13 (Bit 13) */ +#define USB_EPINTPRI_EPPRI13_Msk (0x2000UL) /*!< EPPRI13 (Bitfield-Mask: 0x01) */ +#define USB_EPINTPRI_EPPRI14_Pos (14UL) /*!< EPPRI14 (Bit 14) */ +#define USB_EPINTPRI_EPPRI14_Msk (0x4000UL) /*!< EPPRI14 (Bitfield-Mask: 0x01) */ +#define USB_EPINTPRI_EPPRI15_Pos (15UL) /*!< EPPRI15 (Bit 15) */ +#define USB_EPINTPRI_EPPRI15_Msk (0x8000UL) /*!< EPPRI15 (Bitfield-Mask: 0x01) */ +#define USB_EPINTPRI_EPPRI16_Pos (16UL) /*!< EPPRI16 (Bit 16) */ +#define USB_EPINTPRI_EPPRI16_Msk (0x10000UL) /*!< EPPRI16 (Bitfield-Mask: 0x01) */ +#define USB_EPINTPRI_EPPRI17_Pos (17UL) /*!< EPPRI17 (Bit 17) */ +#define USB_EPINTPRI_EPPRI17_Msk (0x20000UL) /*!< EPPRI17 (Bitfield-Mask: 0x01) */ +#define USB_EPINTPRI_EPPRI18_Pos (18UL) /*!< EPPRI18 (Bit 18) */ +#define USB_EPINTPRI_EPPRI18_Msk (0x40000UL) /*!< EPPRI18 (Bitfield-Mask: 0x01) */ +#define USB_EPINTPRI_EPPRI19_Pos (19UL) /*!< EPPRI19 (Bit 19) */ +#define USB_EPINTPRI_EPPRI19_Msk (0x80000UL) /*!< EPPRI19 (Bitfield-Mask: 0x01) */ +#define USB_EPINTPRI_EPPRI20_Pos (20UL) /*!< EPPRI20 (Bit 20) */ +#define USB_EPINTPRI_EPPRI20_Msk (0x100000UL) /*!< EPPRI20 (Bitfield-Mask: 0x01) */ +#define USB_EPINTPRI_EPPRI21_Pos (21UL) /*!< EPPRI21 (Bit 21) */ +#define USB_EPINTPRI_EPPRI21_Msk (0x200000UL) /*!< EPPRI21 (Bitfield-Mask: 0x01) */ +#define USB_EPINTPRI_EPPRI22_Pos (22UL) /*!< EPPRI22 (Bit 22) */ +#define USB_EPINTPRI_EPPRI22_Msk (0x400000UL) /*!< EPPRI22 (Bitfield-Mask: 0x01) */ +#define USB_EPINTPRI_EPPRI23_Pos (23UL) /*!< EPPRI23 (Bit 23) */ +#define USB_EPINTPRI_EPPRI23_Msk (0x800000UL) /*!< EPPRI23 (Bitfield-Mask: 0x01) */ +#define USB_EPINTPRI_EPPRI24_Pos (24UL) /*!< EPPRI24 (Bit 24) */ +#define USB_EPINTPRI_EPPRI24_Msk (0x1000000UL) /*!< EPPRI24 (Bitfield-Mask: 0x01) */ +#define USB_EPINTPRI_EPPRI25_Pos (25UL) /*!< EPPRI25 (Bit 25) */ +#define USB_EPINTPRI_EPPRI25_Msk (0x2000000UL) /*!< EPPRI25 (Bitfield-Mask: 0x01) */ +#define USB_EPINTPRI_EPPRI26_Pos (26UL) /*!< EPPRI26 (Bit 26) */ +#define USB_EPINTPRI_EPPRI26_Msk (0x4000000UL) /*!< EPPRI26 (Bitfield-Mask: 0x01) */ +#define USB_EPINTPRI_EPPRI27_Pos (27UL) /*!< EPPRI27 (Bit 27) */ +#define USB_EPINTPRI_EPPRI27_Msk (0x8000000UL) /*!< EPPRI27 (Bitfield-Mask: 0x01) */ +#define USB_EPINTPRI_EPPRI28_Pos (28UL) /*!< EPPRI28 (Bit 28) */ +#define USB_EPINTPRI_EPPRI28_Msk (0x10000000UL) /*!< EPPRI28 (Bitfield-Mask: 0x01) */ +#define USB_EPINTPRI_EPPRI29_Pos (29UL) /*!< EPPRI29 (Bit 29) */ +#define USB_EPINTPRI_EPPRI29_Msk (0x20000000UL) /*!< EPPRI29 (Bitfield-Mask: 0x01) */ +#define USB_EPINTPRI_EPPRI30_Pos (30UL) /*!< EPPRI30 (Bit 30) */ +#define USB_EPINTPRI_EPPRI30_Msk (0x40000000UL) /*!< EPPRI30 (Bitfield-Mask: 0x01) */ +#define USB_EPINTPRI_EPPRI31_Pos (31UL) /*!< EPPRI31 (Bit 31) */ +#define USB_EPINTPRI_EPPRI31_Msk (0x80000000UL) /*!< EPPRI31 (Bitfield-Mask: 0x01) */ +/* ========================================================= REEP ========================================================== */ +#define USB_REEP_EPR0_Pos (0UL) /*!< EPR0 (Bit 0) */ +#define USB_REEP_EPR0_Msk (0x1UL) /*!< EPR0 (Bitfield-Mask: 0x01) */ +#define USB_REEP_EPR1_Pos (1UL) /*!< EPR1 (Bit 1) */ +#define USB_REEP_EPR1_Msk (0x2UL) /*!< EPR1 (Bitfield-Mask: 0x01) */ +#define USB_REEP_EPR2_Pos (2UL) /*!< EPR2 (Bit 2) */ +#define USB_REEP_EPR2_Msk (0x4UL) /*!< EPR2 (Bitfield-Mask: 0x01) */ +#define USB_REEP_EPR3_Pos (3UL) /*!< EPR3 (Bit 3) */ +#define USB_REEP_EPR3_Msk (0x8UL) /*!< EPR3 (Bitfield-Mask: 0x01) */ +#define USB_REEP_EPR4_Pos (4UL) /*!< EPR4 (Bit 4) */ +#define USB_REEP_EPR4_Msk (0x10UL) /*!< EPR4 (Bitfield-Mask: 0x01) */ +#define USB_REEP_EPR5_Pos (5UL) /*!< EPR5 (Bit 5) */ +#define USB_REEP_EPR5_Msk (0x20UL) /*!< EPR5 (Bitfield-Mask: 0x01) */ +#define USB_REEP_EPR6_Pos (6UL) /*!< EPR6 (Bit 6) */ +#define USB_REEP_EPR6_Msk (0x40UL) /*!< EPR6 (Bitfield-Mask: 0x01) */ +#define USB_REEP_EPR7_Pos (7UL) /*!< EPR7 (Bit 7) */ +#define USB_REEP_EPR7_Msk (0x80UL) /*!< EPR7 (Bitfield-Mask: 0x01) */ +#define USB_REEP_EPR8_Pos (8UL) /*!< EPR8 (Bit 8) */ +#define USB_REEP_EPR8_Msk (0x100UL) /*!< EPR8 (Bitfield-Mask: 0x01) */ +#define USB_REEP_EPR9_Pos (9UL) /*!< EPR9 (Bit 9) */ +#define USB_REEP_EPR9_Msk (0x200UL) /*!< EPR9 (Bitfield-Mask: 0x01) */ +#define USB_REEP_EPR10_Pos (10UL) /*!< EPR10 (Bit 10) */ +#define USB_REEP_EPR10_Msk (0x400UL) /*!< EPR10 (Bitfield-Mask: 0x01) */ +#define USB_REEP_EPR11_Pos (11UL) /*!< EPR11 (Bit 11) */ +#define USB_REEP_EPR11_Msk (0x800UL) /*!< EPR11 (Bitfield-Mask: 0x01) */ +#define USB_REEP_EPR12_Pos (12UL) /*!< EPR12 (Bit 12) */ +#define USB_REEP_EPR12_Msk (0x1000UL) /*!< EPR12 (Bitfield-Mask: 0x01) */ +#define USB_REEP_EPR13_Pos (13UL) /*!< EPR13 (Bit 13) */ +#define USB_REEP_EPR13_Msk (0x2000UL) /*!< EPR13 (Bitfield-Mask: 0x01) */ +#define USB_REEP_EPR14_Pos (14UL) /*!< EPR14 (Bit 14) */ +#define USB_REEP_EPR14_Msk (0x4000UL) /*!< EPR14 (Bitfield-Mask: 0x01) */ +#define USB_REEP_EPR15_Pos (15UL) /*!< EPR15 (Bit 15) */ +#define USB_REEP_EPR15_Msk (0x8000UL) /*!< EPR15 (Bitfield-Mask: 0x01) */ +#define USB_REEP_EPR16_Pos (16UL) /*!< EPR16 (Bit 16) */ +#define USB_REEP_EPR16_Msk (0x10000UL) /*!< EPR16 (Bitfield-Mask: 0x01) */ +#define USB_REEP_EPR17_Pos (17UL) /*!< EPR17 (Bit 17) */ +#define USB_REEP_EPR17_Msk (0x20000UL) /*!< EPR17 (Bitfield-Mask: 0x01) */ +#define USB_REEP_EPR18_Pos (18UL) /*!< EPR18 (Bit 18) */ +#define USB_REEP_EPR18_Msk (0x40000UL) /*!< EPR18 (Bitfield-Mask: 0x01) */ +#define USB_REEP_EPR19_Pos (19UL) /*!< EPR19 (Bit 19) */ +#define USB_REEP_EPR19_Msk (0x80000UL) /*!< EPR19 (Bitfield-Mask: 0x01) */ +#define USB_REEP_EPR20_Pos (20UL) /*!< EPR20 (Bit 20) */ +#define USB_REEP_EPR20_Msk (0x100000UL) /*!< EPR20 (Bitfield-Mask: 0x01) */ +#define USB_REEP_EPR21_Pos (21UL) /*!< EPR21 (Bit 21) */ +#define USB_REEP_EPR21_Msk (0x200000UL) /*!< EPR21 (Bitfield-Mask: 0x01) */ +#define USB_REEP_EPR22_Pos (22UL) /*!< EPR22 (Bit 22) */ +#define USB_REEP_EPR22_Msk (0x400000UL) /*!< EPR22 (Bitfield-Mask: 0x01) */ +#define USB_REEP_EPR23_Pos (23UL) /*!< EPR23 (Bit 23) */ +#define USB_REEP_EPR23_Msk (0x800000UL) /*!< EPR23 (Bitfield-Mask: 0x01) */ +#define USB_REEP_EPR24_Pos (24UL) /*!< EPR24 (Bit 24) */ +#define USB_REEP_EPR24_Msk (0x1000000UL) /*!< EPR24 (Bitfield-Mask: 0x01) */ +#define USB_REEP_EPR25_Pos (25UL) /*!< EPR25 (Bit 25) */ +#define USB_REEP_EPR25_Msk (0x2000000UL) /*!< EPR25 (Bitfield-Mask: 0x01) */ +#define USB_REEP_EPR26_Pos (26UL) /*!< EPR26 (Bit 26) */ +#define USB_REEP_EPR26_Msk (0x4000000UL) /*!< EPR26 (Bitfield-Mask: 0x01) */ +#define USB_REEP_EPR27_Pos (27UL) /*!< EPR27 (Bit 27) */ +#define USB_REEP_EPR27_Msk (0x8000000UL) /*!< EPR27 (Bitfield-Mask: 0x01) */ +#define USB_REEP_EPR28_Pos (28UL) /*!< EPR28 (Bit 28) */ +#define USB_REEP_EPR28_Msk (0x10000000UL) /*!< EPR28 (Bitfield-Mask: 0x01) */ +#define USB_REEP_EPR29_Pos (29UL) /*!< EPR29 (Bit 29) */ +#define USB_REEP_EPR29_Msk (0x20000000UL) /*!< EPR29 (Bitfield-Mask: 0x01) */ +#define USB_REEP_EPR30_Pos (30UL) /*!< EPR30 (Bit 30) */ +#define USB_REEP_EPR30_Msk (0x40000000UL) /*!< EPR30 (Bitfield-Mask: 0x01) */ +#define USB_REEP_EPR31_Pos (31UL) /*!< EPR31 (Bit 31) */ +#define USB_REEP_EPR31_Msk (0x80000000UL) /*!< EPR31 (Bitfield-Mask: 0x01) */ +/* ========================================================= EPIND ========================================================= */ +#define USB_EPIND_PHY_EP_Pos (0UL) /*!< PHY_EP (Bit 0) */ +#define USB_EPIND_PHY_EP_Msk (0x1fUL) /*!< PHY_EP (Bitfield-Mask: 0x1f) */ +/* ======================================================= MAXPSIZE ======================================================== */ +#define USB_MAXPSIZE_MPS_Pos (0UL) /*!< MPS (Bit 0) */ +#define USB_MAXPSIZE_MPS_Msk (0x3ffUL) /*!< MPS (Bitfield-Mask: 0x3ff) */ +/* ======================================================== DMARST ========================================================= */ +#define USB_DMARST_EPRST0_Pos (0UL) /*!< EPRST0 (Bit 0) */ +#define USB_DMARST_EPRST0_Msk (0x1UL) /*!< EPRST0 (Bitfield-Mask: 0x01) */ +#define USB_DMARST_EPRST1_Pos (1UL) /*!< EPRST1 (Bit 1) */ +#define USB_DMARST_EPRST1_Msk (0x2UL) /*!< EPRST1 (Bitfield-Mask: 0x01) */ +#define USB_DMARST_EPRST2_Pos (2UL) /*!< EPRST2 (Bit 2) */ +#define USB_DMARST_EPRST2_Msk (0x4UL) /*!< EPRST2 (Bitfield-Mask: 0x01) */ +#define USB_DMARST_EPRST3_Pos (3UL) /*!< EPRST3 (Bit 3) */ +#define USB_DMARST_EPRST3_Msk (0x8UL) /*!< EPRST3 (Bitfield-Mask: 0x01) */ +#define USB_DMARST_EPRST4_Pos (4UL) /*!< EPRST4 (Bit 4) */ +#define USB_DMARST_EPRST4_Msk (0x10UL) /*!< EPRST4 (Bitfield-Mask: 0x01) */ +#define USB_DMARST_EPRST5_Pos (5UL) /*!< EPRST5 (Bit 5) */ +#define USB_DMARST_EPRST5_Msk (0x20UL) /*!< EPRST5 (Bitfield-Mask: 0x01) */ +#define USB_DMARST_EPRST6_Pos (6UL) /*!< EPRST6 (Bit 6) */ +#define USB_DMARST_EPRST6_Msk (0x40UL) /*!< EPRST6 (Bitfield-Mask: 0x01) */ +#define USB_DMARST_EPRST7_Pos (7UL) /*!< EPRST7 (Bit 7) */ +#define USB_DMARST_EPRST7_Msk (0x80UL) /*!< EPRST7 (Bitfield-Mask: 0x01) */ +#define USB_DMARST_EPRST8_Pos (8UL) /*!< EPRST8 (Bit 8) */ +#define USB_DMARST_EPRST8_Msk (0x100UL) /*!< EPRST8 (Bitfield-Mask: 0x01) */ +#define USB_DMARST_EPRST9_Pos (9UL) /*!< EPRST9 (Bit 9) */ +#define USB_DMARST_EPRST9_Msk (0x200UL) /*!< EPRST9 (Bitfield-Mask: 0x01) */ +#define USB_DMARST_EPRST10_Pos (10UL) /*!< EPRST10 (Bit 10) */ +#define USB_DMARST_EPRST10_Msk (0x400UL) /*!< EPRST10 (Bitfield-Mask: 0x01) */ +#define USB_DMARST_EPRST11_Pos (11UL) /*!< EPRST11 (Bit 11) */ +#define USB_DMARST_EPRST11_Msk (0x800UL) /*!< EPRST11 (Bitfield-Mask: 0x01) */ +#define USB_DMARST_EPRST12_Pos (12UL) /*!< EPRST12 (Bit 12) */ +#define USB_DMARST_EPRST12_Msk (0x1000UL) /*!< EPRST12 (Bitfield-Mask: 0x01) */ +#define USB_DMARST_EPRST13_Pos (13UL) /*!< EPRST13 (Bit 13) */ +#define USB_DMARST_EPRST13_Msk (0x2000UL) /*!< EPRST13 (Bitfield-Mask: 0x01) */ +#define USB_DMARST_EPRST14_Pos (14UL) /*!< EPRST14 (Bit 14) */ +#define USB_DMARST_EPRST14_Msk (0x4000UL) /*!< EPRST14 (Bitfield-Mask: 0x01) */ +#define USB_DMARST_EPRST15_Pos (15UL) /*!< EPRST15 (Bit 15) */ +#define USB_DMARST_EPRST15_Msk (0x8000UL) /*!< EPRST15 (Bitfield-Mask: 0x01) */ +#define USB_DMARST_EPRST16_Pos (16UL) /*!< EPRST16 (Bit 16) */ +#define USB_DMARST_EPRST16_Msk (0x10000UL) /*!< EPRST16 (Bitfield-Mask: 0x01) */ +#define USB_DMARST_EPRST17_Pos (17UL) /*!< EPRST17 (Bit 17) */ +#define USB_DMARST_EPRST17_Msk (0x20000UL) /*!< EPRST17 (Bitfield-Mask: 0x01) */ +#define USB_DMARST_EPRST18_Pos (18UL) /*!< EPRST18 (Bit 18) */ +#define USB_DMARST_EPRST18_Msk (0x40000UL) /*!< EPRST18 (Bitfield-Mask: 0x01) */ +#define USB_DMARST_EPRST19_Pos (19UL) /*!< EPRST19 (Bit 19) */ +#define USB_DMARST_EPRST19_Msk (0x80000UL) /*!< EPRST19 (Bitfield-Mask: 0x01) */ +#define USB_DMARST_EPRST20_Pos (20UL) /*!< EPRST20 (Bit 20) */ +#define USB_DMARST_EPRST20_Msk (0x100000UL) /*!< EPRST20 (Bitfield-Mask: 0x01) */ +#define USB_DMARST_EPRST21_Pos (21UL) /*!< EPRST21 (Bit 21) */ +#define USB_DMARST_EPRST21_Msk (0x200000UL) /*!< EPRST21 (Bitfield-Mask: 0x01) */ +#define USB_DMARST_EPRST22_Pos (22UL) /*!< EPRST22 (Bit 22) */ +#define USB_DMARST_EPRST22_Msk (0x400000UL) /*!< EPRST22 (Bitfield-Mask: 0x01) */ +#define USB_DMARST_EPRST23_Pos (23UL) /*!< EPRST23 (Bit 23) */ +#define USB_DMARST_EPRST23_Msk (0x800000UL) /*!< EPRST23 (Bitfield-Mask: 0x01) */ +#define USB_DMARST_EPRST24_Pos (24UL) /*!< EPRST24 (Bit 24) */ +#define USB_DMARST_EPRST24_Msk (0x1000000UL) /*!< EPRST24 (Bitfield-Mask: 0x01) */ +#define USB_DMARST_EPRST25_Pos (25UL) /*!< EPRST25 (Bit 25) */ +#define USB_DMARST_EPRST25_Msk (0x2000000UL) /*!< EPRST25 (Bitfield-Mask: 0x01) */ +#define USB_DMARST_EPRST26_Pos (26UL) /*!< EPRST26 (Bit 26) */ +#define USB_DMARST_EPRST26_Msk (0x4000000UL) /*!< EPRST26 (Bitfield-Mask: 0x01) */ +#define USB_DMARST_EPRST27_Pos (27UL) /*!< EPRST27 (Bit 27) */ +#define USB_DMARST_EPRST27_Msk (0x8000000UL) /*!< EPRST27 (Bitfield-Mask: 0x01) */ +#define USB_DMARST_EPRST28_Pos (28UL) /*!< EPRST28 (Bit 28) */ +#define USB_DMARST_EPRST28_Msk (0x10000000UL) /*!< EPRST28 (Bitfield-Mask: 0x01) */ +#define USB_DMARST_EPRST29_Pos (29UL) /*!< EPRST29 (Bit 29) */ +#define USB_DMARST_EPRST29_Msk (0x20000000UL) /*!< EPRST29 (Bitfield-Mask: 0x01) */ +#define USB_DMARST_EPRST30_Pos (30UL) /*!< EPRST30 (Bit 30) */ +#define USB_DMARST_EPRST30_Msk (0x40000000UL) /*!< EPRST30 (Bitfield-Mask: 0x01) */ +#define USB_DMARST_EPRST31_Pos (31UL) /*!< EPRST31 (Bit 31) */ +#define USB_DMARST_EPRST31_Msk (0x80000000UL) /*!< EPRST31 (Bitfield-Mask: 0x01) */ +/* ======================================================== DMARCLR ======================================================== */ +#define USB_DMARCLR_EPRCLR0_Pos (0UL) /*!< EPRCLR0 (Bit 0) */ +#define USB_DMARCLR_EPRCLR0_Msk (0x1UL) /*!< EPRCLR0 (Bitfield-Mask: 0x01) */ +#define USB_DMARCLR_EPRCLR1_Pos (1UL) /*!< EPRCLR1 (Bit 1) */ +#define USB_DMARCLR_EPRCLR1_Msk (0x2UL) /*!< EPRCLR1 (Bitfield-Mask: 0x01) */ +#define USB_DMARCLR_EPRCLR2_Pos (2UL) /*!< EPRCLR2 (Bit 2) */ +#define USB_DMARCLR_EPRCLR2_Msk (0x4UL) /*!< EPRCLR2 (Bitfield-Mask: 0x01) */ +#define USB_DMARCLR_EPRCLR3_Pos (3UL) /*!< EPRCLR3 (Bit 3) */ +#define USB_DMARCLR_EPRCLR3_Msk (0x8UL) /*!< EPRCLR3 (Bitfield-Mask: 0x01) */ +#define USB_DMARCLR_EPRCLR4_Pos (4UL) /*!< EPRCLR4 (Bit 4) */ +#define USB_DMARCLR_EPRCLR4_Msk (0x10UL) /*!< EPRCLR4 (Bitfield-Mask: 0x01) */ +#define USB_DMARCLR_EPRCLR5_Pos (5UL) /*!< EPRCLR5 (Bit 5) */ +#define USB_DMARCLR_EPRCLR5_Msk (0x20UL) /*!< EPRCLR5 (Bitfield-Mask: 0x01) */ +#define USB_DMARCLR_EPRCLR6_Pos (6UL) /*!< EPRCLR6 (Bit 6) */ +#define USB_DMARCLR_EPRCLR6_Msk (0x40UL) /*!< EPRCLR6 (Bitfield-Mask: 0x01) */ +#define USB_DMARCLR_EPRCLR7_Pos (7UL) /*!< EPRCLR7 (Bit 7) */ +#define USB_DMARCLR_EPRCLR7_Msk (0x80UL) /*!< EPRCLR7 (Bitfield-Mask: 0x01) */ +#define USB_DMARCLR_EPRCLR8_Pos (8UL) /*!< EPRCLR8 (Bit 8) */ +#define USB_DMARCLR_EPRCLR8_Msk (0x100UL) /*!< EPRCLR8 (Bitfield-Mask: 0x01) */ +#define USB_DMARCLR_EPRCLR9_Pos (9UL) /*!< EPRCLR9 (Bit 9) */ +#define USB_DMARCLR_EPRCLR9_Msk (0x200UL) /*!< EPRCLR9 (Bitfield-Mask: 0x01) */ +#define USB_DMARCLR_EPRCLR10_Pos (10UL) /*!< EPRCLR10 (Bit 10) */ +#define USB_DMARCLR_EPRCLR10_Msk (0x400UL) /*!< EPRCLR10 (Bitfield-Mask: 0x01) */ +#define USB_DMARCLR_EPRCLR11_Pos (11UL) /*!< EPRCLR11 (Bit 11) */ +#define USB_DMARCLR_EPRCLR11_Msk (0x800UL) /*!< EPRCLR11 (Bitfield-Mask: 0x01) */ +#define USB_DMARCLR_EPRCLR12_Pos (12UL) /*!< EPRCLR12 (Bit 12) */ +#define USB_DMARCLR_EPRCLR12_Msk (0x1000UL) /*!< EPRCLR12 (Bitfield-Mask: 0x01) */ +#define USB_DMARCLR_EPRCLR13_Pos (13UL) /*!< EPRCLR13 (Bit 13) */ +#define USB_DMARCLR_EPRCLR13_Msk (0x2000UL) /*!< EPRCLR13 (Bitfield-Mask: 0x01) */ +#define USB_DMARCLR_EPRCLR14_Pos (14UL) /*!< EPRCLR14 (Bit 14) */ +#define USB_DMARCLR_EPRCLR14_Msk (0x4000UL) /*!< EPRCLR14 (Bitfield-Mask: 0x01) */ +#define USB_DMARCLR_EPRCLR15_Pos (15UL) /*!< EPRCLR15 (Bit 15) */ +#define USB_DMARCLR_EPRCLR15_Msk (0x8000UL) /*!< EPRCLR15 (Bitfield-Mask: 0x01) */ +#define USB_DMARCLR_EPRCLR16_Pos (16UL) /*!< EPRCLR16 (Bit 16) */ +#define USB_DMARCLR_EPRCLR16_Msk (0x10000UL) /*!< EPRCLR16 (Bitfield-Mask: 0x01) */ +#define USB_DMARCLR_EPRCLR17_Pos (17UL) /*!< EPRCLR17 (Bit 17) */ +#define USB_DMARCLR_EPRCLR17_Msk (0x20000UL) /*!< EPRCLR17 (Bitfield-Mask: 0x01) */ +#define USB_DMARCLR_EPRCLR18_Pos (18UL) /*!< EPRCLR18 (Bit 18) */ +#define USB_DMARCLR_EPRCLR18_Msk (0x40000UL) /*!< EPRCLR18 (Bitfield-Mask: 0x01) */ +#define USB_DMARCLR_EPRCLR19_Pos (19UL) /*!< EPRCLR19 (Bit 19) */ +#define USB_DMARCLR_EPRCLR19_Msk (0x80000UL) /*!< EPRCLR19 (Bitfield-Mask: 0x01) */ +#define USB_DMARCLR_EPRCLR20_Pos (20UL) /*!< EPRCLR20 (Bit 20) */ +#define USB_DMARCLR_EPRCLR20_Msk (0x100000UL) /*!< EPRCLR20 (Bitfield-Mask: 0x01) */ +#define USB_DMARCLR_EPRCLR21_Pos (21UL) /*!< EPRCLR21 (Bit 21) */ +#define USB_DMARCLR_EPRCLR21_Msk (0x200000UL) /*!< EPRCLR21 (Bitfield-Mask: 0x01) */ +#define USB_DMARCLR_EPRCLR22_Pos (22UL) /*!< EPRCLR22 (Bit 22) */ +#define USB_DMARCLR_EPRCLR22_Msk (0x400000UL) /*!< EPRCLR22 (Bitfield-Mask: 0x01) */ +#define USB_DMARCLR_EPRCLR23_Pos (23UL) /*!< EPRCLR23 (Bit 23) */ +#define USB_DMARCLR_EPRCLR23_Msk (0x800000UL) /*!< EPRCLR23 (Bitfield-Mask: 0x01) */ +#define USB_DMARCLR_EPRCLR24_Pos (24UL) /*!< EPRCLR24 (Bit 24) */ +#define USB_DMARCLR_EPRCLR24_Msk (0x1000000UL) /*!< EPRCLR24 (Bitfield-Mask: 0x01) */ +#define USB_DMARCLR_EPRCLR25_Pos (25UL) /*!< EPRCLR25 (Bit 25) */ +#define USB_DMARCLR_EPRCLR25_Msk (0x2000000UL) /*!< EPRCLR25 (Bitfield-Mask: 0x01) */ +#define USB_DMARCLR_EPRCLR26_Pos (26UL) /*!< EPRCLR26 (Bit 26) */ +#define USB_DMARCLR_EPRCLR26_Msk (0x4000000UL) /*!< EPRCLR26 (Bitfield-Mask: 0x01) */ +#define USB_DMARCLR_EPRCLR27_Pos (27UL) /*!< EPRCLR27 (Bit 27) */ +#define USB_DMARCLR_EPRCLR27_Msk (0x8000000UL) /*!< EPRCLR27 (Bitfield-Mask: 0x01) */ +#define USB_DMARCLR_EPRCLR28_Pos (28UL) /*!< EPRCLR28 (Bit 28) */ +#define USB_DMARCLR_EPRCLR28_Msk (0x10000000UL) /*!< EPRCLR28 (Bitfield-Mask: 0x01) */ +#define USB_DMARCLR_EPRCLR29_Pos (29UL) /*!< EPRCLR29 (Bit 29) */ +#define USB_DMARCLR_EPRCLR29_Msk (0x20000000UL) /*!< EPRCLR29 (Bitfield-Mask: 0x01) */ +#define USB_DMARCLR_EPRCLR30_Pos (30UL) /*!< EPRCLR30 (Bit 30) */ +#define USB_DMARCLR_EPRCLR30_Msk (0x40000000UL) /*!< EPRCLR30 (Bitfield-Mask: 0x01) */ +#define USB_DMARCLR_EPRCLR31_Pos (31UL) /*!< EPRCLR31 (Bit 31) */ +#define USB_DMARCLR_EPRCLR31_Msk (0x80000000UL) /*!< EPRCLR31 (Bitfield-Mask: 0x01) */ +/* ======================================================== DMARSET ======================================================== */ +#define USB_DMARSET_EPRSET0_Pos (0UL) /*!< EPRSET0 (Bit 0) */ +#define USB_DMARSET_EPRSET0_Msk (0x1UL) /*!< EPRSET0 (Bitfield-Mask: 0x01) */ +#define USB_DMARSET_EPRSET1_Pos (1UL) /*!< EPRSET1 (Bit 1) */ +#define USB_DMARSET_EPRSET1_Msk (0x2UL) /*!< EPRSET1 (Bitfield-Mask: 0x01) */ +#define USB_DMARSET_EPRSET2_Pos (2UL) /*!< EPRSET2 (Bit 2) */ +#define USB_DMARSET_EPRSET2_Msk (0x4UL) /*!< EPRSET2 (Bitfield-Mask: 0x01) */ +#define USB_DMARSET_EPRSET3_Pos (3UL) /*!< EPRSET3 (Bit 3) */ +#define USB_DMARSET_EPRSET3_Msk (0x8UL) /*!< EPRSET3 (Bitfield-Mask: 0x01) */ +#define USB_DMARSET_EPRSET4_Pos (4UL) /*!< EPRSET4 (Bit 4) */ +#define USB_DMARSET_EPRSET4_Msk (0x10UL) /*!< EPRSET4 (Bitfield-Mask: 0x01) */ +#define USB_DMARSET_EPRSET5_Pos (5UL) /*!< EPRSET5 (Bit 5) */ +#define USB_DMARSET_EPRSET5_Msk (0x20UL) /*!< EPRSET5 (Bitfield-Mask: 0x01) */ +#define USB_DMARSET_EPRSET6_Pos (6UL) /*!< EPRSET6 (Bit 6) */ +#define USB_DMARSET_EPRSET6_Msk (0x40UL) /*!< EPRSET6 (Bitfield-Mask: 0x01) */ +#define USB_DMARSET_EPRSET7_Pos (7UL) /*!< EPRSET7 (Bit 7) */ +#define USB_DMARSET_EPRSET7_Msk (0x80UL) /*!< EPRSET7 (Bitfield-Mask: 0x01) */ +#define USB_DMARSET_EPRSET8_Pos (8UL) /*!< EPRSET8 (Bit 8) */ +#define USB_DMARSET_EPRSET8_Msk (0x100UL) /*!< EPRSET8 (Bitfield-Mask: 0x01) */ +#define USB_DMARSET_EPRSET9_Pos (9UL) /*!< EPRSET9 (Bit 9) */ +#define USB_DMARSET_EPRSET9_Msk (0x200UL) /*!< EPRSET9 (Bitfield-Mask: 0x01) */ +#define USB_DMARSET_EPRSET10_Pos (10UL) /*!< EPRSET10 (Bit 10) */ +#define USB_DMARSET_EPRSET10_Msk (0x400UL) /*!< EPRSET10 (Bitfield-Mask: 0x01) */ +#define USB_DMARSET_EPRSET11_Pos (11UL) /*!< EPRSET11 (Bit 11) */ +#define USB_DMARSET_EPRSET11_Msk (0x800UL) /*!< EPRSET11 (Bitfield-Mask: 0x01) */ +#define USB_DMARSET_EPRSET12_Pos (12UL) /*!< EPRSET12 (Bit 12) */ +#define USB_DMARSET_EPRSET12_Msk (0x1000UL) /*!< EPRSET12 (Bitfield-Mask: 0x01) */ +#define USB_DMARSET_EPRSET13_Pos (13UL) /*!< EPRSET13 (Bit 13) */ +#define USB_DMARSET_EPRSET13_Msk (0x2000UL) /*!< EPRSET13 (Bitfield-Mask: 0x01) */ +#define USB_DMARSET_EPRSET14_Pos (14UL) /*!< EPRSET14 (Bit 14) */ +#define USB_DMARSET_EPRSET14_Msk (0x4000UL) /*!< EPRSET14 (Bitfield-Mask: 0x01) */ +#define USB_DMARSET_EPRSET15_Pos (15UL) /*!< EPRSET15 (Bit 15) */ +#define USB_DMARSET_EPRSET15_Msk (0x8000UL) /*!< EPRSET15 (Bitfield-Mask: 0x01) */ +#define USB_DMARSET_EPRSET16_Pos (16UL) /*!< EPRSET16 (Bit 16) */ +#define USB_DMARSET_EPRSET16_Msk (0x10000UL) /*!< EPRSET16 (Bitfield-Mask: 0x01) */ +#define USB_DMARSET_EPRSET17_Pos (17UL) /*!< EPRSET17 (Bit 17) */ +#define USB_DMARSET_EPRSET17_Msk (0x20000UL) /*!< EPRSET17 (Bitfield-Mask: 0x01) */ +#define USB_DMARSET_EPRSET18_Pos (18UL) /*!< EPRSET18 (Bit 18) */ +#define USB_DMARSET_EPRSET18_Msk (0x40000UL) /*!< EPRSET18 (Bitfield-Mask: 0x01) */ +#define USB_DMARSET_EPRSET19_Pos (19UL) /*!< EPRSET19 (Bit 19) */ +#define USB_DMARSET_EPRSET19_Msk (0x80000UL) /*!< EPRSET19 (Bitfield-Mask: 0x01) */ +#define USB_DMARSET_EPRSET20_Pos (20UL) /*!< EPRSET20 (Bit 20) */ +#define USB_DMARSET_EPRSET20_Msk (0x100000UL) /*!< EPRSET20 (Bitfield-Mask: 0x01) */ +#define USB_DMARSET_EPRSET21_Pos (21UL) /*!< EPRSET21 (Bit 21) */ +#define USB_DMARSET_EPRSET21_Msk (0x200000UL) /*!< EPRSET21 (Bitfield-Mask: 0x01) */ +#define USB_DMARSET_EPRSET22_Pos (22UL) /*!< EPRSET22 (Bit 22) */ +#define USB_DMARSET_EPRSET22_Msk (0x400000UL) /*!< EPRSET22 (Bitfield-Mask: 0x01) */ +#define USB_DMARSET_EPRSET23_Pos (23UL) /*!< EPRSET23 (Bit 23) */ +#define USB_DMARSET_EPRSET23_Msk (0x800000UL) /*!< EPRSET23 (Bitfield-Mask: 0x01) */ +#define USB_DMARSET_EPRSET24_Pos (24UL) /*!< EPRSET24 (Bit 24) */ +#define USB_DMARSET_EPRSET24_Msk (0x1000000UL) /*!< EPRSET24 (Bitfield-Mask: 0x01) */ +#define USB_DMARSET_EPRSET25_Pos (25UL) /*!< EPRSET25 (Bit 25) */ +#define USB_DMARSET_EPRSET25_Msk (0x2000000UL) /*!< EPRSET25 (Bitfield-Mask: 0x01) */ +#define USB_DMARSET_EPRSET26_Pos (26UL) /*!< EPRSET26 (Bit 26) */ +#define USB_DMARSET_EPRSET26_Msk (0x4000000UL) /*!< EPRSET26 (Bitfield-Mask: 0x01) */ +#define USB_DMARSET_EPRSET27_Pos (27UL) /*!< EPRSET27 (Bit 27) */ +#define USB_DMARSET_EPRSET27_Msk (0x8000000UL) /*!< EPRSET27 (Bitfield-Mask: 0x01) */ +#define USB_DMARSET_EPRSET28_Pos (28UL) /*!< EPRSET28 (Bit 28) */ +#define USB_DMARSET_EPRSET28_Msk (0x10000000UL) /*!< EPRSET28 (Bitfield-Mask: 0x01) */ +#define USB_DMARSET_EPRSET29_Pos (29UL) /*!< EPRSET29 (Bit 29) */ +#define USB_DMARSET_EPRSET29_Msk (0x20000000UL) /*!< EPRSET29 (Bitfield-Mask: 0x01) */ +#define USB_DMARSET_EPRSET30_Pos (30UL) /*!< EPRSET30 (Bit 30) */ +#define USB_DMARSET_EPRSET30_Msk (0x40000000UL) /*!< EPRSET30 (Bitfield-Mask: 0x01) */ +#define USB_DMARSET_EPRSET31_Pos (31UL) /*!< EPRSET31 (Bit 31) */ +#define USB_DMARSET_EPRSET31_Msk (0x80000000UL) /*!< EPRSET31 (Bitfield-Mask: 0x01) */ +/* ========================================================= UDCAH ========================================================= */ +#define USB_UDCAH_UDCA_ADDR_Pos (7UL) /*!< UDCA_ADDR (Bit 7) */ +#define USB_UDCAH_UDCA_ADDR_Msk (0xffffff80UL) /*!< UDCA_ADDR (Bitfield-Mask: 0x1ffffff) */ +/* ======================================================== EPDMAST ======================================================== */ +#define USB_EPDMAST_EP_DMA_ST0_Pos (0UL) /*!< EP_DMA_ST0 (Bit 0) */ +#define USB_EPDMAST_EP_DMA_ST0_Msk (0x1UL) /*!< EP_DMA_ST0 (Bitfield-Mask: 0x01) */ +#define USB_EPDMAST_EP_DMA_ST1_Pos (1UL) /*!< EP_DMA_ST1 (Bit 1) */ +#define USB_EPDMAST_EP_DMA_ST1_Msk (0x2UL) /*!< EP_DMA_ST1 (Bitfield-Mask: 0x01) */ +#define USB_EPDMAST_EP_DMA_ST2_Pos (2UL) /*!< EP_DMA_ST2 (Bit 2) */ +#define USB_EPDMAST_EP_DMA_ST2_Msk (0x4UL) /*!< EP_DMA_ST2 (Bitfield-Mask: 0x01) */ +#define USB_EPDMAST_EP_DMA_ST3_Pos (3UL) /*!< EP_DMA_ST3 (Bit 3) */ +#define USB_EPDMAST_EP_DMA_ST3_Msk (0x8UL) /*!< EP_DMA_ST3 (Bitfield-Mask: 0x01) */ +#define USB_EPDMAST_EP_DMA_ST4_Pos (4UL) /*!< EP_DMA_ST4 (Bit 4) */ +#define USB_EPDMAST_EP_DMA_ST4_Msk (0x10UL) /*!< EP_DMA_ST4 (Bitfield-Mask: 0x01) */ +#define USB_EPDMAST_EP_DMA_ST5_Pos (5UL) /*!< EP_DMA_ST5 (Bit 5) */ +#define USB_EPDMAST_EP_DMA_ST5_Msk (0x20UL) /*!< EP_DMA_ST5 (Bitfield-Mask: 0x01) */ +#define USB_EPDMAST_EP_DMA_ST6_Pos (6UL) /*!< EP_DMA_ST6 (Bit 6) */ +#define USB_EPDMAST_EP_DMA_ST6_Msk (0x40UL) /*!< EP_DMA_ST6 (Bitfield-Mask: 0x01) */ +#define USB_EPDMAST_EP_DMA_ST7_Pos (7UL) /*!< EP_DMA_ST7 (Bit 7) */ +#define USB_EPDMAST_EP_DMA_ST7_Msk (0x80UL) /*!< EP_DMA_ST7 (Bitfield-Mask: 0x01) */ +#define USB_EPDMAST_EP_DMA_ST8_Pos (8UL) /*!< EP_DMA_ST8 (Bit 8) */ +#define USB_EPDMAST_EP_DMA_ST8_Msk (0x100UL) /*!< EP_DMA_ST8 (Bitfield-Mask: 0x01) */ +#define USB_EPDMAST_EP_DMA_ST9_Pos (9UL) /*!< EP_DMA_ST9 (Bit 9) */ +#define USB_EPDMAST_EP_DMA_ST9_Msk (0x200UL) /*!< EP_DMA_ST9 (Bitfield-Mask: 0x01) */ +#define USB_EPDMAST_EP_DMA_ST10_Pos (10UL) /*!< EP_DMA_ST10 (Bit 10) */ +#define USB_EPDMAST_EP_DMA_ST10_Msk (0x400UL) /*!< EP_DMA_ST10 (Bitfield-Mask: 0x01) */ +#define USB_EPDMAST_EP_DMA_ST11_Pos (11UL) /*!< EP_DMA_ST11 (Bit 11) */ +#define USB_EPDMAST_EP_DMA_ST11_Msk (0x800UL) /*!< EP_DMA_ST11 (Bitfield-Mask: 0x01) */ +#define USB_EPDMAST_EP_DMA_ST12_Pos (12UL) /*!< EP_DMA_ST12 (Bit 12) */ +#define USB_EPDMAST_EP_DMA_ST12_Msk (0x1000UL) /*!< EP_DMA_ST12 (Bitfield-Mask: 0x01) */ +#define USB_EPDMAST_EP_DMA_ST13_Pos (13UL) /*!< EP_DMA_ST13 (Bit 13) */ +#define USB_EPDMAST_EP_DMA_ST13_Msk (0x2000UL) /*!< EP_DMA_ST13 (Bitfield-Mask: 0x01) */ +#define USB_EPDMAST_EP_DMA_ST14_Pos (14UL) /*!< EP_DMA_ST14 (Bit 14) */ +#define USB_EPDMAST_EP_DMA_ST14_Msk (0x4000UL) /*!< EP_DMA_ST14 (Bitfield-Mask: 0x01) */ +#define USB_EPDMAST_EP_DMA_ST15_Pos (15UL) /*!< EP_DMA_ST15 (Bit 15) */ +#define USB_EPDMAST_EP_DMA_ST15_Msk (0x8000UL) /*!< EP_DMA_ST15 (Bitfield-Mask: 0x01) */ +#define USB_EPDMAST_EP_DMA_ST16_Pos (16UL) /*!< EP_DMA_ST16 (Bit 16) */ +#define USB_EPDMAST_EP_DMA_ST16_Msk (0x10000UL) /*!< EP_DMA_ST16 (Bitfield-Mask: 0x01) */ +#define USB_EPDMAST_EP_DMA_ST17_Pos (17UL) /*!< EP_DMA_ST17 (Bit 17) */ +#define USB_EPDMAST_EP_DMA_ST17_Msk (0x20000UL) /*!< EP_DMA_ST17 (Bitfield-Mask: 0x01) */ +#define USB_EPDMAST_EP_DMA_ST18_Pos (18UL) /*!< EP_DMA_ST18 (Bit 18) */ +#define USB_EPDMAST_EP_DMA_ST18_Msk (0x40000UL) /*!< EP_DMA_ST18 (Bitfield-Mask: 0x01) */ +#define USB_EPDMAST_EP_DMA_ST19_Pos (19UL) /*!< EP_DMA_ST19 (Bit 19) */ +#define USB_EPDMAST_EP_DMA_ST19_Msk (0x80000UL) /*!< EP_DMA_ST19 (Bitfield-Mask: 0x01) */ +#define USB_EPDMAST_EP_DMA_ST20_Pos (20UL) /*!< EP_DMA_ST20 (Bit 20) */ +#define USB_EPDMAST_EP_DMA_ST20_Msk (0x100000UL) /*!< EP_DMA_ST20 (Bitfield-Mask: 0x01) */ +#define USB_EPDMAST_EP_DMA_ST21_Pos (21UL) /*!< EP_DMA_ST21 (Bit 21) */ +#define USB_EPDMAST_EP_DMA_ST21_Msk (0x200000UL) /*!< EP_DMA_ST21 (Bitfield-Mask: 0x01) */ +#define USB_EPDMAST_EP_DMA_ST22_Pos (22UL) /*!< EP_DMA_ST22 (Bit 22) */ +#define USB_EPDMAST_EP_DMA_ST22_Msk (0x400000UL) /*!< EP_DMA_ST22 (Bitfield-Mask: 0x01) */ +#define USB_EPDMAST_EP_DMA_ST23_Pos (23UL) /*!< EP_DMA_ST23 (Bit 23) */ +#define USB_EPDMAST_EP_DMA_ST23_Msk (0x800000UL) /*!< EP_DMA_ST23 (Bitfield-Mask: 0x01) */ +#define USB_EPDMAST_EP_DMA_ST24_Pos (24UL) /*!< EP_DMA_ST24 (Bit 24) */ +#define USB_EPDMAST_EP_DMA_ST24_Msk (0x1000000UL) /*!< EP_DMA_ST24 (Bitfield-Mask: 0x01) */ +#define USB_EPDMAST_EP_DMA_ST25_Pos (25UL) /*!< EP_DMA_ST25 (Bit 25) */ +#define USB_EPDMAST_EP_DMA_ST25_Msk (0x2000000UL) /*!< EP_DMA_ST25 (Bitfield-Mask: 0x01) */ +#define USB_EPDMAST_EP_DMA_ST26_Pos (26UL) /*!< EP_DMA_ST26 (Bit 26) */ +#define USB_EPDMAST_EP_DMA_ST26_Msk (0x4000000UL) /*!< EP_DMA_ST26 (Bitfield-Mask: 0x01) */ +#define USB_EPDMAST_EP_DMA_ST27_Pos (27UL) /*!< EP_DMA_ST27 (Bit 27) */ +#define USB_EPDMAST_EP_DMA_ST27_Msk (0x8000000UL) /*!< EP_DMA_ST27 (Bitfield-Mask: 0x01) */ +#define USB_EPDMAST_EP_DMA_ST28_Pos (28UL) /*!< EP_DMA_ST28 (Bit 28) */ +#define USB_EPDMAST_EP_DMA_ST28_Msk (0x10000000UL) /*!< EP_DMA_ST28 (Bitfield-Mask: 0x01) */ +#define USB_EPDMAST_EP_DMA_ST29_Pos (29UL) /*!< EP_DMA_ST29 (Bit 29) */ +#define USB_EPDMAST_EP_DMA_ST29_Msk (0x20000000UL) /*!< EP_DMA_ST29 (Bitfield-Mask: 0x01) */ +#define USB_EPDMAST_EP_DMA_ST30_Pos (30UL) /*!< EP_DMA_ST30 (Bit 30) */ +#define USB_EPDMAST_EP_DMA_ST30_Msk (0x40000000UL) /*!< EP_DMA_ST30 (Bitfield-Mask: 0x01) */ +#define USB_EPDMAST_EP_DMA_ST31_Pos (31UL) /*!< EP_DMA_ST31 (Bit 31) */ +#define USB_EPDMAST_EP_DMA_ST31_Msk (0x80000000UL) /*!< EP_DMA_ST31 (Bitfield-Mask: 0x01) */ +/* ======================================================== EPDMAEN ======================================================== */ +#define USB_EPDMAEN_EP_DMA_EN0_Pos (0UL) /*!< EP_DMA_EN0 (Bit 0) */ +#define USB_EPDMAEN_EP_DMA_EN0_Msk (0x1UL) /*!< EP_DMA_EN0 (Bitfield-Mask: 0x01) */ +#define USB_EPDMAEN_EP_DMA_EN1_Pos (1UL) /*!< EP_DMA_EN1 (Bit 1) */ +#define USB_EPDMAEN_EP_DMA_EN1_Msk (0x2UL) /*!< EP_DMA_EN1 (Bitfield-Mask: 0x01) */ +#define USB_EPDMAEN_EP_DMA_EN_Pos (2UL) /*!< EP_DMA_EN (Bit 2) */ +#define USB_EPDMAEN_EP_DMA_EN_Msk (0xfffffffcUL) /*!< EP_DMA_EN (Bitfield-Mask: 0x3fffffff) */ +/* ======================================================= EPDMADIS ======================================================== */ +#define USB_EPDMADIS_EP_DMA_DIS0_Pos (0UL) /*!< EP_DMA_DIS0 (Bit 0) */ +#define USB_EPDMADIS_EP_DMA_DIS0_Msk (0x1UL) /*!< EP_DMA_DIS0 (Bitfield-Mask: 0x01) */ +#define USB_EPDMADIS_EP_DMA_DIS1_Pos (1UL) /*!< EP_DMA_DIS1 (Bit 1) */ +#define USB_EPDMADIS_EP_DMA_DIS1_Msk (0x2UL) /*!< EP_DMA_DIS1 (Bitfield-Mask: 0x01) */ +#define USB_EPDMADIS_EP_DMA_DIS2_Pos (2UL) /*!< EP_DMA_DIS2 (Bit 2) */ +#define USB_EPDMADIS_EP_DMA_DIS2_Msk (0x4UL) /*!< EP_DMA_DIS2 (Bitfield-Mask: 0x01) */ +#define USB_EPDMADIS_EP_DMA_DIS3_Pos (3UL) /*!< EP_DMA_DIS3 (Bit 3) */ +#define USB_EPDMADIS_EP_DMA_DIS3_Msk (0x8UL) /*!< EP_DMA_DIS3 (Bitfield-Mask: 0x01) */ +#define USB_EPDMADIS_EP_DMA_DIS4_Pos (4UL) /*!< EP_DMA_DIS4 (Bit 4) */ +#define USB_EPDMADIS_EP_DMA_DIS4_Msk (0x10UL) /*!< EP_DMA_DIS4 (Bitfield-Mask: 0x01) */ +#define USB_EPDMADIS_EP_DMA_DIS5_Pos (5UL) /*!< EP_DMA_DIS5 (Bit 5) */ +#define USB_EPDMADIS_EP_DMA_DIS5_Msk (0x20UL) /*!< EP_DMA_DIS5 (Bitfield-Mask: 0x01) */ +#define USB_EPDMADIS_EP_DMA_DIS6_Pos (6UL) /*!< EP_DMA_DIS6 (Bit 6) */ +#define USB_EPDMADIS_EP_DMA_DIS6_Msk (0x40UL) /*!< EP_DMA_DIS6 (Bitfield-Mask: 0x01) */ +#define USB_EPDMADIS_EP_DMA_DIS7_Pos (7UL) /*!< EP_DMA_DIS7 (Bit 7) */ +#define USB_EPDMADIS_EP_DMA_DIS7_Msk (0x80UL) /*!< EP_DMA_DIS7 (Bitfield-Mask: 0x01) */ +#define USB_EPDMADIS_EP_DMA_DIS8_Pos (8UL) /*!< EP_DMA_DIS8 (Bit 8) */ +#define USB_EPDMADIS_EP_DMA_DIS8_Msk (0x100UL) /*!< EP_DMA_DIS8 (Bitfield-Mask: 0x01) */ +#define USB_EPDMADIS_EP_DMA_DIS9_Pos (9UL) /*!< EP_DMA_DIS9 (Bit 9) */ +#define USB_EPDMADIS_EP_DMA_DIS9_Msk (0x200UL) /*!< EP_DMA_DIS9 (Bitfield-Mask: 0x01) */ +#define USB_EPDMADIS_EP_DMA_DIS10_Pos (10UL) /*!< EP_DMA_DIS10 (Bit 10) */ +#define USB_EPDMADIS_EP_DMA_DIS10_Msk (0x400UL) /*!< EP_DMA_DIS10 (Bitfield-Mask: 0x01) */ +#define USB_EPDMADIS_EP_DMA_DIS11_Pos (11UL) /*!< EP_DMA_DIS11 (Bit 11) */ +#define USB_EPDMADIS_EP_DMA_DIS11_Msk (0x800UL) /*!< EP_DMA_DIS11 (Bitfield-Mask: 0x01) */ +#define USB_EPDMADIS_EP_DMA_DIS12_Pos (12UL) /*!< EP_DMA_DIS12 (Bit 12) */ +#define USB_EPDMADIS_EP_DMA_DIS12_Msk (0x1000UL) /*!< EP_DMA_DIS12 (Bitfield-Mask: 0x01) */ +#define USB_EPDMADIS_EP_DMA_DIS13_Pos (13UL) /*!< EP_DMA_DIS13 (Bit 13) */ +#define USB_EPDMADIS_EP_DMA_DIS13_Msk (0x2000UL) /*!< EP_DMA_DIS13 (Bitfield-Mask: 0x01) */ +#define USB_EPDMADIS_EP_DMA_DIS14_Pos (14UL) /*!< EP_DMA_DIS14 (Bit 14) */ +#define USB_EPDMADIS_EP_DMA_DIS14_Msk (0x4000UL) /*!< EP_DMA_DIS14 (Bitfield-Mask: 0x01) */ +#define USB_EPDMADIS_EP_DMA_DIS15_Pos (15UL) /*!< EP_DMA_DIS15 (Bit 15) */ +#define USB_EPDMADIS_EP_DMA_DIS15_Msk (0x8000UL) /*!< EP_DMA_DIS15 (Bitfield-Mask: 0x01) */ +#define USB_EPDMADIS_EP_DMA_DIS16_Pos (16UL) /*!< EP_DMA_DIS16 (Bit 16) */ +#define USB_EPDMADIS_EP_DMA_DIS16_Msk (0x10000UL) /*!< EP_DMA_DIS16 (Bitfield-Mask: 0x01) */ +#define USB_EPDMADIS_EP_DMA_DIS17_Pos (17UL) /*!< EP_DMA_DIS17 (Bit 17) */ +#define USB_EPDMADIS_EP_DMA_DIS17_Msk (0x20000UL) /*!< EP_DMA_DIS17 (Bitfield-Mask: 0x01) */ +#define USB_EPDMADIS_EP_DMA_DIS18_Pos (18UL) /*!< EP_DMA_DIS18 (Bit 18) */ +#define USB_EPDMADIS_EP_DMA_DIS18_Msk (0x40000UL) /*!< EP_DMA_DIS18 (Bitfield-Mask: 0x01) */ +#define USB_EPDMADIS_EP_DMA_DIS19_Pos (19UL) /*!< EP_DMA_DIS19 (Bit 19) */ +#define USB_EPDMADIS_EP_DMA_DIS19_Msk (0x80000UL) /*!< EP_DMA_DIS19 (Bitfield-Mask: 0x01) */ +#define USB_EPDMADIS_EP_DMA_DIS20_Pos (20UL) /*!< EP_DMA_DIS20 (Bit 20) */ +#define USB_EPDMADIS_EP_DMA_DIS20_Msk (0x100000UL) /*!< EP_DMA_DIS20 (Bitfield-Mask: 0x01) */ +#define USB_EPDMADIS_EP_DMA_DIS21_Pos (21UL) /*!< EP_DMA_DIS21 (Bit 21) */ +#define USB_EPDMADIS_EP_DMA_DIS21_Msk (0x200000UL) /*!< EP_DMA_DIS21 (Bitfield-Mask: 0x01) */ +#define USB_EPDMADIS_EP_DMA_DIS22_Pos (22UL) /*!< EP_DMA_DIS22 (Bit 22) */ +#define USB_EPDMADIS_EP_DMA_DIS22_Msk (0x400000UL) /*!< EP_DMA_DIS22 (Bitfield-Mask: 0x01) */ +#define USB_EPDMADIS_EP_DMA_DIS23_Pos (23UL) /*!< EP_DMA_DIS23 (Bit 23) */ +#define USB_EPDMADIS_EP_DMA_DIS23_Msk (0x800000UL) /*!< EP_DMA_DIS23 (Bitfield-Mask: 0x01) */ +#define USB_EPDMADIS_EP_DMA_DIS24_Pos (24UL) /*!< EP_DMA_DIS24 (Bit 24) */ +#define USB_EPDMADIS_EP_DMA_DIS24_Msk (0x1000000UL) /*!< EP_DMA_DIS24 (Bitfield-Mask: 0x01) */ +#define USB_EPDMADIS_EP_DMA_DIS25_Pos (25UL) /*!< EP_DMA_DIS25 (Bit 25) */ +#define USB_EPDMADIS_EP_DMA_DIS25_Msk (0x2000000UL) /*!< EP_DMA_DIS25 (Bitfield-Mask: 0x01) */ +#define USB_EPDMADIS_EP_DMA_DIS26_Pos (26UL) /*!< EP_DMA_DIS26 (Bit 26) */ +#define USB_EPDMADIS_EP_DMA_DIS26_Msk (0x4000000UL) /*!< EP_DMA_DIS26 (Bitfield-Mask: 0x01) */ +#define USB_EPDMADIS_EP_DMA_DIS27_Pos (27UL) /*!< EP_DMA_DIS27 (Bit 27) */ +#define USB_EPDMADIS_EP_DMA_DIS27_Msk (0x8000000UL) /*!< EP_DMA_DIS27 (Bitfield-Mask: 0x01) */ +#define USB_EPDMADIS_EP_DMA_DIS28_Pos (28UL) /*!< EP_DMA_DIS28 (Bit 28) */ +#define USB_EPDMADIS_EP_DMA_DIS28_Msk (0x10000000UL) /*!< EP_DMA_DIS28 (Bitfield-Mask: 0x01) */ +#define USB_EPDMADIS_EP_DMA_DIS29_Pos (29UL) /*!< EP_DMA_DIS29 (Bit 29) */ +#define USB_EPDMADIS_EP_DMA_DIS29_Msk (0x20000000UL) /*!< EP_DMA_DIS29 (Bitfield-Mask: 0x01) */ +#define USB_EPDMADIS_EP_DMA_DIS30_Pos (30UL) /*!< EP_DMA_DIS30 (Bit 30) */ +#define USB_EPDMADIS_EP_DMA_DIS30_Msk (0x40000000UL) /*!< EP_DMA_DIS30 (Bitfield-Mask: 0x01) */ +#define USB_EPDMADIS_EP_DMA_DIS31_Pos (31UL) /*!< EP_DMA_DIS31 (Bit 31) */ +#define USB_EPDMADIS_EP_DMA_DIS31_Msk (0x80000000UL) /*!< EP_DMA_DIS31 (Bitfield-Mask: 0x01) */ +/* ======================================================= DMAINTST ======================================================== */ +#define USB_DMAINTST_EOT_Pos (0UL) /*!< EOT (Bit 0) */ +#define USB_DMAINTST_EOT_Msk (0x1UL) /*!< EOT (Bitfield-Mask: 0x01) */ +#define USB_DMAINTST_NDDR_Pos (1UL) /*!< NDDR (Bit 1) */ +#define USB_DMAINTST_NDDR_Msk (0x2UL) /*!< NDDR (Bitfield-Mask: 0x01) */ +#define USB_DMAINTST_ERR_Pos (2UL) /*!< ERR (Bit 2) */ +#define USB_DMAINTST_ERR_Msk (0x4UL) /*!< ERR (Bitfield-Mask: 0x01) */ +/* ======================================================= DMAINTEN ======================================================== */ +#define USB_DMAINTEN_EOT_Pos (0UL) /*!< EOT (Bit 0) */ +#define USB_DMAINTEN_EOT_Msk (0x1UL) /*!< EOT (Bitfield-Mask: 0x01) */ +#define USB_DMAINTEN_NDDR_Pos (1UL) /*!< NDDR (Bit 1) */ +#define USB_DMAINTEN_NDDR_Msk (0x2UL) /*!< NDDR (Bitfield-Mask: 0x01) */ +#define USB_DMAINTEN_ERR_Pos (2UL) /*!< ERR (Bit 2) */ +#define USB_DMAINTEN_ERR_Msk (0x4UL) /*!< ERR (Bitfield-Mask: 0x01) */ +/* ======================================================= EOTINTST ======================================================== */ +#define USB_EOTINTST_EPTXINTST0_Pos (0UL) /*!< EPTXINTST0 (Bit 0) */ +#define USB_EOTINTST_EPTXINTST0_Msk (0x1UL) /*!< EPTXINTST0 (Bitfield-Mask: 0x01) */ +#define USB_EOTINTST_EPTXINTST1_Pos (1UL) /*!< EPTXINTST1 (Bit 1) */ +#define USB_EOTINTST_EPTXINTST1_Msk (0x2UL) /*!< EPTXINTST1 (Bitfield-Mask: 0x01) */ +#define USB_EOTINTST_EPTXINTST2_Pos (2UL) /*!< EPTXINTST2 (Bit 2) */ +#define USB_EOTINTST_EPTXINTST2_Msk (0x4UL) /*!< EPTXINTST2 (Bitfield-Mask: 0x01) */ +#define USB_EOTINTST_EPTXINTST3_Pos (3UL) /*!< EPTXINTST3 (Bit 3) */ +#define USB_EOTINTST_EPTXINTST3_Msk (0x8UL) /*!< EPTXINTST3 (Bitfield-Mask: 0x01) */ +#define USB_EOTINTST_EPTXINTST4_Pos (4UL) /*!< EPTXINTST4 (Bit 4) */ +#define USB_EOTINTST_EPTXINTST4_Msk (0x10UL) /*!< EPTXINTST4 (Bitfield-Mask: 0x01) */ +#define USB_EOTINTST_EPTXINTST5_Pos (5UL) /*!< EPTXINTST5 (Bit 5) */ +#define USB_EOTINTST_EPTXINTST5_Msk (0x20UL) /*!< EPTXINTST5 (Bitfield-Mask: 0x01) */ +#define USB_EOTINTST_EPTXINTST6_Pos (6UL) /*!< EPTXINTST6 (Bit 6) */ +#define USB_EOTINTST_EPTXINTST6_Msk (0x40UL) /*!< EPTXINTST6 (Bitfield-Mask: 0x01) */ +#define USB_EOTINTST_EPTXINTST7_Pos (7UL) /*!< EPTXINTST7 (Bit 7) */ +#define USB_EOTINTST_EPTXINTST7_Msk (0x80UL) /*!< EPTXINTST7 (Bitfield-Mask: 0x01) */ +#define USB_EOTINTST_EPTXINTST8_Pos (8UL) /*!< EPTXINTST8 (Bit 8) */ +#define USB_EOTINTST_EPTXINTST8_Msk (0x100UL) /*!< EPTXINTST8 (Bitfield-Mask: 0x01) */ +#define USB_EOTINTST_EPTXINTST9_Pos (9UL) /*!< EPTXINTST9 (Bit 9) */ +#define USB_EOTINTST_EPTXINTST9_Msk (0x200UL) /*!< EPTXINTST9 (Bitfield-Mask: 0x01) */ +#define USB_EOTINTST_EPTXINTST10_Pos (10UL) /*!< EPTXINTST10 (Bit 10) */ +#define USB_EOTINTST_EPTXINTST10_Msk (0x400UL) /*!< EPTXINTST10 (Bitfield-Mask: 0x01) */ +#define USB_EOTINTST_EPTXINTST11_Pos (11UL) /*!< EPTXINTST11 (Bit 11) */ +#define USB_EOTINTST_EPTXINTST11_Msk (0x800UL) /*!< EPTXINTST11 (Bitfield-Mask: 0x01) */ +#define USB_EOTINTST_EPTXINTST12_Pos (12UL) /*!< EPTXINTST12 (Bit 12) */ +#define USB_EOTINTST_EPTXINTST12_Msk (0x1000UL) /*!< EPTXINTST12 (Bitfield-Mask: 0x01) */ +#define USB_EOTINTST_EPTXINTST13_Pos (13UL) /*!< EPTXINTST13 (Bit 13) */ +#define USB_EOTINTST_EPTXINTST13_Msk (0x2000UL) /*!< EPTXINTST13 (Bitfield-Mask: 0x01) */ +#define USB_EOTINTST_EPTXINTST14_Pos (14UL) /*!< EPTXINTST14 (Bit 14) */ +#define USB_EOTINTST_EPTXINTST14_Msk (0x4000UL) /*!< EPTXINTST14 (Bitfield-Mask: 0x01) */ +#define USB_EOTINTST_EPTXINTST15_Pos (15UL) /*!< EPTXINTST15 (Bit 15) */ +#define USB_EOTINTST_EPTXINTST15_Msk (0x8000UL) /*!< EPTXINTST15 (Bitfield-Mask: 0x01) */ +#define USB_EOTINTST_EPTXINTST16_Pos (16UL) /*!< EPTXINTST16 (Bit 16) */ +#define USB_EOTINTST_EPTXINTST16_Msk (0x10000UL) /*!< EPTXINTST16 (Bitfield-Mask: 0x01) */ +#define USB_EOTINTST_EPTXINTST17_Pos (17UL) /*!< EPTXINTST17 (Bit 17) */ +#define USB_EOTINTST_EPTXINTST17_Msk (0x20000UL) /*!< EPTXINTST17 (Bitfield-Mask: 0x01) */ +#define USB_EOTINTST_EPTXINTST18_Pos (18UL) /*!< EPTXINTST18 (Bit 18) */ +#define USB_EOTINTST_EPTXINTST18_Msk (0x40000UL) /*!< EPTXINTST18 (Bitfield-Mask: 0x01) */ +#define USB_EOTINTST_EPTXINTST19_Pos (19UL) /*!< EPTXINTST19 (Bit 19) */ +#define USB_EOTINTST_EPTXINTST19_Msk (0x80000UL) /*!< EPTXINTST19 (Bitfield-Mask: 0x01) */ +#define USB_EOTINTST_EPTXINTST20_Pos (20UL) /*!< EPTXINTST20 (Bit 20) */ +#define USB_EOTINTST_EPTXINTST20_Msk (0x100000UL) /*!< EPTXINTST20 (Bitfield-Mask: 0x01) */ +#define USB_EOTINTST_EPTXINTST21_Pos (21UL) /*!< EPTXINTST21 (Bit 21) */ +#define USB_EOTINTST_EPTXINTST21_Msk (0x200000UL) /*!< EPTXINTST21 (Bitfield-Mask: 0x01) */ +#define USB_EOTINTST_EPTXINTST22_Pos (22UL) /*!< EPTXINTST22 (Bit 22) */ +#define USB_EOTINTST_EPTXINTST22_Msk (0x400000UL) /*!< EPTXINTST22 (Bitfield-Mask: 0x01) */ +#define USB_EOTINTST_EPTXINTST23_Pos (23UL) /*!< EPTXINTST23 (Bit 23) */ +#define USB_EOTINTST_EPTXINTST23_Msk (0x800000UL) /*!< EPTXINTST23 (Bitfield-Mask: 0x01) */ +#define USB_EOTINTST_EPTXINTST24_Pos (24UL) /*!< EPTXINTST24 (Bit 24) */ +#define USB_EOTINTST_EPTXINTST24_Msk (0x1000000UL) /*!< EPTXINTST24 (Bitfield-Mask: 0x01) */ +#define USB_EOTINTST_EPTXINTST25_Pos (25UL) /*!< EPTXINTST25 (Bit 25) */ +#define USB_EOTINTST_EPTXINTST25_Msk (0x2000000UL) /*!< EPTXINTST25 (Bitfield-Mask: 0x01) */ +#define USB_EOTINTST_EPTXINTST26_Pos (26UL) /*!< EPTXINTST26 (Bit 26) */ +#define USB_EOTINTST_EPTXINTST26_Msk (0x4000000UL) /*!< EPTXINTST26 (Bitfield-Mask: 0x01) */ +#define USB_EOTINTST_EPTXINTST27_Pos (27UL) /*!< EPTXINTST27 (Bit 27) */ +#define USB_EOTINTST_EPTXINTST27_Msk (0x8000000UL) /*!< EPTXINTST27 (Bitfield-Mask: 0x01) */ +#define USB_EOTINTST_EPTXINTST28_Pos (28UL) /*!< EPTXINTST28 (Bit 28) */ +#define USB_EOTINTST_EPTXINTST28_Msk (0x10000000UL) /*!< EPTXINTST28 (Bitfield-Mask: 0x01) */ +#define USB_EOTINTST_EPTXINTST29_Pos (29UL) /*!< EPTXINTST29 (Bit 29) */ +#define USB_EOTINTST_EPTXINTST29_Msk (0x20000000UL) /*!< EPTXINTST29 (Bitfield-Mask: 0x01) */ +#define USB_EOTINTST_EPTXINTST30_Pos (30UL) /*!< EPTXINTST30 (Bit 30) */ +#define USB_EOTINTST_EPTXINTST30_Msk (0x40000000UL) /*!< EPTXINTST30 (Bitfield-Mask: 0x01) */ +#define USB_EOTINTST_EPTXINTST31_Pos (31UL) /*!< EPTXINTST31 (Bit 31) */ +#define USB_EOTINTST_EPTXINTST31_Msk (0x80000000UL) /*!< EPTXINTST31 (Bitfield-Mask: 0x01) */ +/* ======================================================= EOTINTCLR ======================================================= */ +#define USB_EOTINTCLR_EPTXINTCLR0_Pos (0UL) /*!< EPTXINTCLR0 (Bit 0) */ +#define USB_EOTINTCLR_EPTXINTCLR0_Msk (0x1UL) /*!< EPTXINTCLR0 (Bitfield-Mask: 0x01) */ +#define USB_EOTINTCLR_EPTXINTCLR1_Pos (1UL) /*!< EPTXINTCLR1 (Bit 1) */ +#define USB_EOTINTCLR_EPTXINTCLR1_Msk (0x2UL) /*!< EPTXINTCLR1 (Bitfield-Mask: 0x01) */ +#define USB_EOTINTCLR_EPTXINTCLR2_Pos (2UL) /*!< EPTXINTCLR2 (Bit 2) */ +#define USB_EOTINTCLR_EPTXINTCLR2_Msk (0x4UL) /*!< EPTXINTCLR2 (Bitfield-Mask: 0x01) */ +#define USB_EOTINTCLR_EPTXINTCLR3_Pos (3UL) /*!< EPTXINTCLR3 (Bit 3) */ +#define USB_EOTINTCLR_EPTXINTCLR3_Msk (0x8UL) /*!< EPTXINTCLR3 (Bitfield-Mask: 0x01) */ +#define USB_EOTINTCLR_EPTXINTCLR4_Pos (4UL) /*!< EPTXINTCLR4 (Bit 4) */ +#define USB_EOTINTCLR_EPTXINTCLR4_Msk (0x10UL) /*!< EPTXINTCLR4 (Bitfield-Mask: 0x01) */ +#define USB_EOTINTCLR_EPTXINTCLR5_Pos (5UL) /*!< EPTXINTCLR5 (Bit 5) */ +#define USB_EOTINTCLR_EPTXINTCLR5_Msk (0x20UL) /*!< EPTXINTCLR5 (Bitfield-Mask: 0x01) */ +#define USB_EOTINTCLR_EPTXINTCLR6_Pos (6UL) /*!< EPTXINTCLR6 (Bit 6) */ +#define USB_EOTINTCLR_EPTXINTCLR6_Msk (0x40UL) /*!< EPTXINTCLR6 (Bitfield-Mask: 0x01) */ +#define USB_EOTINTCLR_EPTXINTCLR7_Pos (7UL) /*!< EPTXINTCLR7 (Bit 7) */ +#define USB_EOTINTCLR_EPTXINTCLR7_Msk (0x80UL) /*!< EPTXINTCLR7 (Bitfield-Mask: 0x01) */ +#define USB_EOTINTCLR_EPTXINTCLR8_Pos (8UL) /*!< EPTXINTCLR8 (Bit 8) */ +#define USB_EOTINTCLR_EPTXINTCLR8_Msk (0x100UL) /*!< EPTXINTCLR8 (Bitfield-Mask: 0x01) */ +#define USB_EOTINTCLR_EPTXINTCLR9_Pos (9UL) /*!< EPTXINTCLR9 (Bit 9) */ +#define USB_EOTINTCLR_EPTXINTCLR9_Msk (0x200UL) /*!< EPTXINTCLR9 (Bitfield-Mask: 0x01) */ +#define USB_EOTINTCLR_EPTXINTCLR10_Pos (10UL) /*!< EPTXINTCLR10 (Bit 10) */ +#define USB_EOTINTCLR_EPTXINTCLR10_Msk (0x400UL) /*!< EPTXINTCLR10 (Bitfield-Mask: 0x01) */ +#define USB_EOTINTCLR_EPTXINTCLR11_Pos (11UL) /*!< EPTXINTCLR11 (Bit 11) */ +#define USB_EOTINTCLR_EPTXINTCLR11_Msk (0x800UL) /*!< EPTXINTCLR11 (Bitfield-Mask: 0x01) */ +#define USB_EOTINTCLR_EPTXINTCLR12_Pos (12UL) /*!< EPTXINTCLR12 (Bit 12) */ +#define USB_EOTINTCLR_EPTXINTCLR12_Msk (0x1000UL) /*!< EPTXINTCLR12 (Bitfield-Mask: 0x01) */ +#define USB_EOTINTCLR_EPTXINTCLR13_Pos (13UL) /*!< EPTXINTCLR13 (Bit 13) */ +#define USB_EOTINTCLR_EPTXINTCLR13_Msk (0x2000UL) /*!< EPTXINTCLR13 (Bitfield-Mask: 0x01) */ +#define USB_EOTINTCLR_EPTXINTCLR14_Pos (14UL) /*!< EPTXINTCLR14 (Bit 14) */ +#define USB_EOTINTCLR_EPTXINTCLR14_Msk (0x4000UL) /*!< EPTXINTCLR14 (Bitfield-Mask: 0x01) */ +#define USB_EOTINTCLR_EPTXINTCLR15_Pos (15UL) /*!< EPTXINTCLR15 (Bit 15) */ +#define USB_EOTINTCLR_EPTXINTCLR15_Msk (0x8000UL) /*!< EPTXINTCLR15 (Bitfield-Mask: 0x01) */ +#define USB_EOTINTCLR_EPTXINTCLR16_Pos (16UL) /*!< EPTXINTCLR16 (Bit 16) */ +#define USB_EOTINTCLR_EPTXINTCLR16_Msk (0x10000UL) /*!< EPTXINTCLR16 (Bitfield-Mask: 0x01) */ +#define USB_EOTINTCLR_EPTXINTCLR17_Pos (17UL) /*!< EPTXINTCLR17 (Bit 17) */ +#define USB_EOTINTCLR_EPTXINTCLR17_Msk (0x20000UL) /*!< EPTXINTCLR17 (Bitfield-Mask: 0x01) */ +#define USB_EOTINTCLR_EPTXINTCLR18_Pos (18UL) /*!< EPTXINTCLR18 (Bit 18) */ +#define USB_EOTINTCLR_EPTXINTCLR18_Msk (0x40000UL) /*!< EPTXINTCLR18 (Bitfield-Mask: 0x01) */ +#define USB_EOTINTCLR_EPTXINTCLR19_Pos (19UL) /*!< EPTXINTCLR19 (Bit 19) */ +#define USB_EOTINTCLR_EPTXINTCLR19_Msk (0x80000UL) /*!< EPTXINTCLR19 (Bitfield-Mask: 0x01) */ +#define USB_EOTINTCLR_EPTXINTCLR20_Pos (20UL) /*!< EPTXINTCLR20 (Bit 20) */ +#define USB_EOTINTCLR_EPTXINTCLR20_Msk (0x100000UL) /*!< EPTXINTCLR20 (Bitfield-Mask: 0x01) */ +#define USB_EOTINTCLR_EPTXINTCLR21_Pos (21UL) /*!< EPTXINTCLR21 (Bit 21) */ +#define USB_EOTINTCLR_EPTXINTCLR21_Msk (0x200000UL) /*!< EPTXINTCLR21 (Bitfield-Mask: 0x01) */ +#define USB_EOTINTCLR_EPTXINTCLR22_Pos (22UL) /*!< EPTXINTCLR22 (Bit 22) */ +#define USB_EOTINTCLR_EPTXINTCLR22_Msk (0x400000UL) /*!< EPTXINTCLR22 (Bitfield-Mask: 0x01) */ +#define USB_EOTINTCLR_EPTXINTCLR23_Pos (23UL) /*!< EPTXINTCLR23 (Bit 23) */ +#define USB_EOTINTCLR_EPTXINTCLR23_Msk (0x800000UL) /*!< EPTXINTCLR23 (Bitfield-Mask: 0x01) */ +#define USB_EOTINTCLR_EPTXINTCLR24_Pos (24UL) /*!< EPTXINTCLR24 (Bit 24) */ +#define USB_EOTINTCLR_EPTXINTCLR24_Msk (0x1000000UL) /*!< EPTXINTCLR24 (Bitfield-Mask: 0x01) */ +#define USB_EOTINTCLR_EPTXINTCLR25_Pos (25UL) /*!< EPTXINTCLR25 (Bit 25) */ +#define USB_EOTINTCLR_EPTXINTCLR25_Msk (0x2000000UL) /*!< EPTXINTCLR25 (Bitfield-Mask: 0x01) */ +#define USB_EOTINTCLR_EPTXINTCLR26_Pos (26UL) /*!< EPTXINTCLR26 (Bit 26) */ +#define USB_EOTINTCLR_EPTXINTCLR26_Msk (0x4000000UL) /*!< EPTXINTCLR26 (Bitfield-Mask: 0x01) */ +#define USB_EOTINTCLR_EPTXINTCLR27_Pos (27UL) /*!< EPTXINTCLR27 (Bit 27) */ +#define USB_EOTINTCLR_EPTXINTCLR27_Msk (0x8000000UL) /*!< EPTXINTCLR27 (Bitfield-Mask: 0x01) */ +#define USB_EOTINTCLR_EPTXINTCLR28_Pos (28UL) /*!< EPTXINTCLR28 (Bit 28) */ +#define USB_EOTINTCLR_EPTXINTCLR28_Msk (0x10000000UL) /*!< EPTXINTCLR28 (Bitfield-Mask: 0x01) */ +#define USB_EOTINTCLR_EPTXINTCLR29_Pos (29UL) /*!< EPTXINTCLR29 (Bit 29) */ +#define USB_EOTINTCLR_EPTXINTCLR29_Msk (0x20000000UL) /*!< EPTXINTCLR29 (Bitfield-Mask: 0x01) */ +#define USB_EOTINTCLR_EPTXINTCLR30_Pos (30UL) /*!< EPTXINTCLR30 (Bit 30) */ +#define USB_EOTINTCLR_EPTXINTCLR30_Msk (0x40000000UL) /*!< EPTXINTCLR30 (Bitfield-Mask: 0x01) */ +#define USB_EOTINTCLR_EPTXINTCLR31_Pos (31UL) /*!< EPTXINTCLR31 (Bit 31) */ +#define USB_EOTINTCLR_EPTXINTCLR31_Msk (0x80000000UL) /*!< EPTXINTCLR31 (Bitfield-Mask: 0x01) */ +/* ======================================================= EOTINTSET ======================================================= */ +#define USB_EOTINTSET_EPTXINTSET0_Pos (0UL) /*!< EPTXINTSET0 (Bit 0) */ +#define USB_EOTINTSET_EPTXINTSET0_Msk (0x1UL) /*!< EPTXINTSET0 (Bitfield-Mask: 0x01) */ +#define USB_EOTINTSET_EPTXINTSET1_Pos (1UL) /*!< EPTXINTSET1 (Bit 1) */ +#define USB_EOTINTSET_EPTXINTSET1_Msk (0x2UL) /*!< EPTXINTSET1 (Bitfield-Mask: 0x01) */ +#define USB_EOTINTSET_EPTXINTSET2_Pos (2UL) /*!< EPTXINTSET2 (Bit 2) */ +#define USB_EOTINTSET_EPTXINTSET2_Msk (0x4UL) /*!< EPTXINTSET2 (Bitfield-Mask: 0x01) */ +#define USB_EOTINTSET_EPTXINTSET3_Pos (3UL) /*!< EPTXINTSET3 (Bit 3) */ +#define USB_EOTINTSET_EPTXINTSET3_Msk (0x8UL) /*!< EPTXINTSET3 (Bitfield-Mask: 0x01) */ +#define USB_EOTINTSET_EPTXINTSET4_Pos (4UL) /*!< EPTXINTSET4 (Bit 4) */ +#define USB_EOTINTSET_EPTXINTSET4_Msk (0x10UL) /*!< EPTXINTSET4 (Bitfield-Mask: 0x01) */ +#define USB_EOTINTSET_EPTXINTSET5_Pos (5UL) /*!< EPTXINTSET5 (Bit 5) */ +#define USB_EOTINTSET_EPTXINTSET5_Msk (0x20UL) /*!< EPTXINTSET5 (Bitfield-Mask: 0x01) */ +#define USB_EOTINTSET_EPTXINTSET6_Pos (6UL) /*!< EPTXINTSET6 (Bit 6) */ +#define USB_EOTINTSET_EPTXINTSET6_Msk (0x40UL) /*!< EPTXINTSET6 (Bitfield-Mask: 0x01) */ +#define USB_EOTINTSET_EPTXINTSET7_Pos (7UL) /*!< EPTXINTSET7 (Bit 7) */ +#define USB_EOTINTSET_EPTXINTSET7_Msk (0x80UL) /*!< EPTXINTSET7 (Bitfield-Mask: 0x01) */ +#define USB_EOTINTSET_EPTXINTSET8_Pos (8UL) /*!< EPTXINTSET8 (Bit 8) */ +#define USB_EOTINTSET_EPTXINTSET8_Msk (0x100UL) /*!< EPTXINTSET8 (Bitfield-Mask: 0x01) */ +#define USB_EOTINTSET_EPTXINTSET9_Pos (9UL) /*!< EPTXINTSET9 (Bit 9) */ +#define USB_EOTINTSET_EPTXINTSET9_Msk (0x200UL) /*!< EPTXINTSET9 (Bitfield-Mask: 0x01) */ +#define USB_EOTINTSET_EPTXINTSET10_Pos (10UL) /*!< EPTXINTSET10 (Bit 10) */ +#define USB_EOTINTSET_EPTXINTSET10_Msk (0x400UL) /*!< EPTXINTSET10 (Bitfield-Mask: 0x01) */ +#define USB_EOTINTSET_EPTXINTSET11_Pos (11UL) /*!< EPTXINTSET11 (Bit 11) */ +#define USB_EOTINTSET_EPTXINTSET11_Msk (0x800UL) /*!< EPTXINTSET11 (Bitfield-Mask: 0x01) */ +#define USB_EOTINTSET_EPTXINTSET12_Pos (12UL) /*!< EPTXINTSET12 (Bit 12) */ +#define USB_EOTINTSET_EPTXINTSET12_Msk (0x1000UL) /*!< EPTXINTSET12 (Bitfield-Mask: 0x01) */ +#define USB_EOTINTSET_EPTXINTSET13_Pos (13UL) /*!< EPTXINTSET13 (Bit 13) */ +#define USB_EOTINTSET_EPTXINTSET13_Msk (0x2000UL) /*!< EPTXINTSET13 (Bitfield-Mask: 0x01) */ +#define USB_EOTINTSET_EPTXINTSET14_Pos (14UL) /*!< EPTXINTSET14 (Bit 14) */ +#define USB_EOTINTSET_EPTXINTSET14_Msk (0x4000UL) /*!< EPTXINTSET14 (Bitfield-Mask: 0x01) */ +#define USB_EOTINTSET_EPTXINTSET15_Pos (15UL) /*!< EPTXINTSET15 (Bit 15) */ +#define USB_EOTINTSET_EPTXINTSET15_Msk (0x8000UL) /*!< EPTXINTSET15 (Bitfield-Mask: 0x01) */ +#define USB_EOTINTSET_EPTXINTSET16_Pos (16UL) /*!< EPTXINTSET16 (Bit 16) */ +#define USB_EOTINTSET_EPTXINTSET16_Msk (0x10000UL) /*!< EPTXINTSET16 (Bitfield-Mask: 0x01) */ +#define USB_EOTINTSET_EPTXINTSET17_Pos (17UL) /*!< EPTXINTSET17 (Bit 17) */ +#define USB_EOTINTSET_EPTXINTSET17_Msk (0x20000UL) /*!< EPTXINTSET17 (Bitfield-Mask: 0x01) */ +#define USB_EOTINTSET_EPTXINTSET18_Pos (18UL) /*!< EPTXINTSET18 (Bit 18) */ +#define USB_EOTINTSET_EPTXINTSET18_Msk (0x40000UL) /*!< EPTXINTSET18 (Bitfield-Mask: 0x01) */ +#define USB_EOTINTSET_EPTXINTSET19_Pos (19UL) /*!< EPTXINTSET19 (Bit 19) */ +#define USB_EOTINTSET_EPTXINTSET19_Msk (0x80000UL) /*!< EPTXINTSET19 (Bitfield-Mask: 0x01) */ +#define USB_EOTINTSET_EPTXINTSET20_Pos (20UL) /*!< EPTXINTSET20 (Bit 20) */ +#define USB_EOTINTSET_EPTXINTSET20_Msk (0x100000UL) /*!< EPTXINTSET20 (Bitfield-Mask: 0x01) */ +#define USB_EOTINTSET_EPTXINTSET21_Pos (21UL) /*!< EPTXINTSET21 (Bit 21) */ +#define USB_EOTINTSET_EPTXINTSET21_Msk (0x200000UL) /*!< EPTXINTSET21 (Bitfield-Mask: 0x01) */ +#define USB_EOTINTSET_EPTXINTSET22_Pos (22UL) /*!< EPTXINTSET22 (Bit 22) */ +#define USB_EOTINTSET_EPTXINTSET22_Msk (0x400000UL) /*!< EPTXINTSET22 (Bitfield-Mask: 0x01) */ +#define USB_EOTINTSET_EPTXINTSET23_Pos (23UL) /*!< EPTXINTSET23 (Bit 23) */ +#define USB_EOTINTSET_EPTXINTSET23_Msk (0x800000UL) /*!< EPTXINTSET23 (Bitfield-Mask: 0x01) */ +#define USB_EOTINTSET_EPTXINTSET24_Pos (24UL) /*!< EPTXINTSET24 (Bit 24) */ +#define USB_EOTINTSET_EPTXINTSET24_Msk (0x1000000UL) /*!< EPTXINTSET24 (Bitfield-Mask: 0x01) */ +#define USB_EOTINTSET_EPTXINTSET25_Pos (25UL) /*!< EPTXINTSET25 (Bit 25) */ +#define USB_EOTINTSET_EPTXINTSET25_Msk (0x2000000UL) /*!< EPTXINTSET25 (Bitfield-Mask: 0x01) */ +#define USB_EOTINTSET_EPTXINTSET26_Pos (26UL) /*!< EPTXINTSET26 (Bit 26) */ +#define USB_EOTINTSET_EPTXINTSET26_Msk (0x4000000UL) /*!< EPTXINTSET26 (Bitfield-Mask: 0x01) */ +#define USB_EOTINTSET_EPTXINTSET27_Pos (27UL) /*!< EPTXINTSET27 (Bit 27) */ +#define USB_EOTINTSET_EPTXINTSET27_Msk (0x8000000UL) /*!< EPTXINTSET27 (Bitfield-Mask: 0x01) */ +#define USB_EOTINTSET_EPTXINTSET28_Pos (28UL) /*!< EPTXINTSET28 (Bit 28) */ +#define USB_EOTINTSET_EPTXINTSET28_Msk (0x10000000UL) /*!< EPTXINTSET28 (Bitfield-Mask: 0x01) */ +#define USB_EOTINTSET_EPTXINTSET29_Pos (29UL) /*!< EPTXINTSET29 (Bit 29) */ +#define USB_EOTINTSET_EPTXINTSET29_Msk (0x20000000UL) /*!< EPTXINTSET29 (Bitfield-Mask: 0x01) */ +#define USB_EOTINTSET_EPTXINTSET30_Pos (30UL) /*!< EPTXINTSET30 (Bit 30) */ +#define USB_EOTINTSET_EPTXINTSET30_Msk (0x40000000UL) /*!< EPTXINTSET30 (Bitfield-Mask: 0x01) */ +#define USB_EOTINTSET_EPTXINTSET31_Pos (31UL) /*!< EPTXINTSET31 (Bit 31) */ +#define USB_EOTINTSET_EPTXINTSET31_Msk (0x80000000UL) /*!< EPTXINTSET31 (Bitfield-Mask: 0x01) */ +/* ======================================================= NDDRINTST ======================================================= */ +#define USB_NDDRINTST_EPNDDINTST0_Pos (0UL) /*!< EPNDDINTST0 (Bit 0) */ +#define USB_NDDRINTST_EPNDDINTST0_Msk (0x1UL) /*!< EPNDDINTST0 (Bitfield-Mask: 0x01) */ +#define USB_NDDRINTST_EPNDDINTST1_Pos (1UL) /*!< EPNDDINTST1 (Bit 1) */ +#define USB_NDDRINTST_EPNDDINTST1_Msk (0x2UL) /*!< EPNDDINTST1 (Bitfield-Mask: 0x01) */ +#define USB_NDDRINTST_EPNDDINTST2_Pos (2UL) /*!< EPNDDINTST2 (Bit 2) */ +#define USB_NDDRINTST_EPNDDINTST2_Msk (0x4UL) /*!< EPNDDINTST2 (Bitfield-Mask: 0x01) */ +#define USB_NDDRINTST_EPNDDINTST3_Pos (3UL) /*!< EPNDDINTST3 (Bit 3) */ +#define USB_NDDRINTST_EPNDDINTST3_Msk (0x8UL) /*!< EPNDDINTST3 (Bitfield-Mask: 0x01) */ +#define USB_NDDRINTST_EPNDDINTST4_Pos (4UL) /*!< EPNDDINTST4 (Bit 4) */ +#define USB_NDDRINTST_EPNDDINTST4_Msk (0x10UL) /*!< EPNDDINTST4 (Bitfield-Mask: 0x01) */ +#define USB_NDDRINTST_EPNDDINTST5_Pos (5UL) /*!< EPNDDINTST5 (Bit 5) */ +#define USB_NDDRINTST_EPNDDINTST5_Msk (0x20UL) /*!< EPNDDINTST5 (Bitfield-Mask: 0x01) */ +#define USB_NDDRINTST_EPNDDINTST6_Pos (6UL) /*!< EPNDDINTST6 (Bit 6) */ +#define USB_NDDRINTST_EPNDDINTST6_Msk (0x40UL) /*!< EPNDDINTST6 (Bitfield-Mask: 0x01) */ +#define USB_NDDRINTST_EPNDDINTST7_Pos (7UL) /*!< EPNDDINTST7 (Bit 7) */ +#define USB_NDDRINTST_EPNDDINTST7_Msk (0x80UL) /*!< EPNDDINTST7 (Bitfield-Mask: 0x01) */ +#define USB_NDDRINTST_EPNDDINTST8_Pos (8UL) /*!< EPNDDINTST8 (Bit 8) */ +#define USB_NDDRINTST_EPNDDINTST8_Msk (0x100UL) /*!< EPNDDINTST8 (Bitfield-Mask: 0x01) */ +#define USB_NDDRINTST_EPNDDINTST9_Pos (9UL) /*!< EPNDDINTST9 (Bit 9) */ +#define USB_NDDRINTST_EPNDDINTST9_Msk (0x200UL) /*!< EPNDDINTST9 (Bitfield-Mask: 0x01) */ +#define USB_NDDRINTST_EPNDDINTST10_Pos (10UL) /*!< EPNDDINTST10 (Bit 10) */ +#define USB_NDDRINTST_EPNDDINTST10_Msk (0x400UL) /*!< EPNDDINTST10 (Bitfield-Mask: 0x01) */ +#define USB_NDDRINTST_EPNDDINTST11_Pos (11UL) /*!< EPNDDINTST11 (Bit 11) */ +#define USB_NDDRINTST_EPNDDINTST11_Msk (0x800UL) /*!< EPNDDINTST11 (Bitfield-Mask: 0x01) */ +#define USB_NDDRINTST_EPNDDINTST12_Pos (12UL) /*!< EPNDDINTST12 (Bit 12) */ +#define USB_NDDRINTST_EPNDDINTST12_Msk (0x1000UL) /*!< EPNDDINTST12 (Bitfield-Mask: 0x01) */ +#define USB_NDDRINTST_EPNDDINTST13_Pos (13UL) /*!< EPNDDINTST13 (Bit 13) */ +#define USB_NDDRINTST_EPNDDINTST13_Msk (0x2000UL) /*!< EPNDDINTST13 (Bitfield-Mask: 0x01) */ +#define USB_NDDRINTST_EPNDDINTST14_Pos (14UL) /*!< EPNDDINTST14 (Bit 14) */ +#define USB_NDDRINTST_EPNDDINTST14_Msk (0x4000UL) /*!< EPNDDINTST14 (Bitfield-Mask: 0x01) */ +#define USB_NDDRINTST_EPNDDINTST15_Pos (15UL) /*!< EPNDDINTST15 (Bit 15) */ +#define USB_NDDRINTST_EPNDDINTST15_Msk (0x8000UL) /*!< EPNDDINTST15 (Bitfield-Mask: 0x01) */ +#define USB_NDDRINTST_EPNDDINTST16_Pos (16UL) /*!< EPNDDINTST16 (Bit 16) */ +#define USB_NDDRINTST_EPNDDINTST16_Msk (0x10000UL) /*!< EPNDDINTST16 (Bitfield-Mask: 0x01) */ +#define USB_NDDRINTST_EPNDDINTST17_Pos (17UL) /*!< EPNDDINTST17 (Bit 17) */ +#define USB_NDDRINTST_EPNDDINTST17_Msk (0x20000UL) /*!< EPNDDINTST17 (Bitfield-Mask: 0x01) */ +#define USB_NDDRINTST_EPNDDINTST18_Pos (18UL) /*!< EPNDDINTST18 (Bit 18) */ +#define USB_NDDRINTST_EPNDDINTST18_Msk (0x40000UL) /*!< EPNDDINTST18 (Bitfield-Mask: 0x01) */ +#define USB_NDDRINTST_EPNDDINTST19_Pos (19UL) /*!< EPNDDINTST19 (Bit 19) */ +#define USB_NDDRINTST_EPNDDINTST19_Msk (0x80000UL) /*!< EPNDDINTST19 (Bitfield-Mask: 0x01) */ +#define USB_NDDRINTST_EPNDDINTST20_Pos (20UL) /*!< EPNDDINTST20 (Bit 20) */ +#define USB_NDDRINTST_EPNDDINTST20_Msk (0x100000UL) /*!< EPNDDINTST20 (Bitfield-Mask: 0x01) */ +#define USB_NDDRINTST_EPNDDINTST21_Pos (21UL) /*!< EPNDDINTST21 (Bit 21) */ +#define USB_NDDRINTST_EPNDDINTST21_Msk (0x200000UL) /*!< EPNDDINTST21 (Bitfield-Mask: 0x01) */ +#define USB_NDDRINTST_EPNDDINTST22_Pos (22UL) /*!< EPNDDINTST22 (Bit 22) */ +#define USB_NDDRINTST_EPNDDINTST22_Msk (0x400000UL) /*!< EPNDDINTST22 (Bitfield-Mask: 0x01) */ +#define USB_NDDRINTST_EPNDDINTST23_Pos (23UL) /*!< EPNDDINTST23 (Bit 23) */ +#define USB_NDDRINTST_EPNDDINTST23_Msk (0x800000UL) /*!< EPNDDINTST23 (Bitfield-Mask: 0x01) */ +#define USB_NDDRINTST_EPNDDINTST24_Pos (24UL) /*!< EPNDDINTST24 (Bit 24) */ +#define USB_NDDRINTST_EPNDDINTST24_Msk (0x1000000UL) /*!< EPNDDINTST24 (Bitfield-Mask: 0x01) */ +#define USB_NDDRINTST_EPNDDINTST25_Pos (25UL) /*!< EPNDDINTST25 (Bit 25) */ +#define USB_NDDRINTST_EPNDDINTST25_Msk (0x2000000UL) /*!< EPNDDINTST25 (Bitfield-Mask: 0x01) */ +#define USB_NDDRINTST_EPNDDINTST26_Pos (26UL) /*!< EPNDDINTST26 (Bit 26) */ +#define USB_NDDRINTST_EPNDDINTST26_Msk (0x4000000UL) /*!< EPNDDINTST26 (Bitfield-Mask: 0x01) */ +#define USB_NDDRINTST_EPNDDINTST27_Pos (27UL) /*!< EPNDDINTST27 (Bit 27) */ +#define USB_NDDRINTST_EPNDDINTST27_Msk (0x8000000UL) /*!< EPNDDINTST27 (Bitfield-Mask: 0x01) */ +#define USB_NDDRINTST_EPNDDINTST28_Pos (28UL) /*!< EPNDDINTST28 (Bit 28) */ +#define USB_NDDRINTST_EPNDDINTST28_Msk (0x10000000UL) /*!< EPNDDINTST28 (Bitfield-Mask: 0x01) */ +#define USB_NDDRINTST_EPNDDINTST29_Pos (29UL) /*!< EPNDDINTST29 (Bit 29) */ +#define USB_NDDRINTST_EPNDDINTST29_Msk (0x20000000UL) /*!< EPNDDINTST29 (Bitfield-Mask: 0x01) */ +#define USB_NDDRINTST_EPNDDINTST30_Pos (30UL) /*!< EPNDDINTST30 (Bit 30) */ +#define USB_NDDRINTST_EPNDDINTST30_Msk (0x40000000UL) /*!< EPNDDINTST30 (Bitfield-Mask: 0x01) */ +#define USB_NDDRINTST_EPNDDINTST31_Pos (31UL) /*!< EPNDDINTST31 (Bit 31) */ +#define USB_NDDRINTST_EPNDDINTST31_Msk (0x80000000UL) /*!< EPNDDINTST31 (Bitfield-Mask: 0x01) */ +/* ====================================================== NDDRINTCLR ======================================================= */ +#define USB_NDDRINTCLR_EPNDDINTCLR0_Pos (0UL) /*!< EPNDDINTCLR0 (Bit 0) */ +#define USB_NDDRINTCLR_EPNDDINTCLR0_Msk (0x1UL) /*!< EPNDDINTCLR0 (Bitfield-Mask: 0x01) */ +#define USB_NDDRINTCLR_EPNDDINTCLR1_Pos (1UL) /*!< EPNDDINTCLR1 (Bit 1) */ +#define USB_NDDRINTCLR_EPNDDINTCLR1_Msk (0x2UL) /*!< EPNDDINTCLR1 (Bitfield-Mask: 0x01) */ +#define USB_NDDRINTCLR_EPNDDINTCLR2_Pos (2UL) /*!< EPNDDINTCLR2 (Bit 2) */ +#define USB_NDDRINTCLR_EPNDDINTCLR2_Msk (0x4UL) /*!< EPNDDINTCLR2 (Bitfield-Mask: 0x01) */ +#define USB_NDDRINTCLR_EPNDDINTCLR3_Pos (3UL) /*!< EPNDDINTCLR3 (Bit 3) */ +#define USB_NDDRINTCLR_EPNDDINTCLR3_Msk (0x8UL) /*!< EPNDDINTCLR3 (Bitfield-Mask: 0x01) */ +#define USB_NDDRINTCLR_EPNDDINTCLR4_Pos (4UL) /*!< EPNDDINTCLR4 (Bit 4) */ +#define USB_NDDRINTCLR_EPNDDINTCLR4_Msk (0x10UL) /*!< EPNDDINTCLR4 (Bitfield-Mask: 0x01) */ +#define USB_NDDRINTCLR_EPNDDINTCLR5_Pos (5UL) /*!< EPNDDINTCLR5 (Bit 5) */ +#define USB_NDDRINTCLR_EPNDDINTCLR5_Msk (0x20UL) /*!< EPNDDINTCLR5 (Bitfield-Mask: 0x01) */ +#define USB_NDDRINTCLR_EPNDDINTCLR6_Pos (6UL) /*!< EPNDDINTCLR6 (Bit 6) */ +#define USB_NDDRINTCLR_EPNDDINTCLR6_Msk (0x40UL) /*!< EPNDDINTCLR6 (Bitfield-Mask: 0x01) */ +#define USB_NDDRINTCLR_EPNDDINTCLR7_Pos (7UL) /*!< EPNDDINTCLR7 (Bit 7) */ +#define USB_NDDRINTCLR_EPNDDINTCLR7_Msk (0x80UL) /*!< EPNDDINTCLR7 (Bitfield-Mask: 0x01) */ +#define USB_NDDRINTCLR_EPNDDINTCLR8_Pos (8UL) /*!< EPNDDINTCLR8 (Bit 8) */ +#define USB_NDDRINTCLR_EPNDDINTCLR8_Msk (0x100UL) /*!< EPNDDINTCLR8 (Bitfield-Mask: 0x01) */ +#define USB_NDDRINTCLR_EPNDDINTCLR9_Pos (9UL) /*!< EPNDDINTCLR9 (Bit 9) */ +#define USB_NDDRINTCLR_EPNDDINTCLR9_Msk (0x200UL) /*!< EPNDDINTCLR9 (Bitfield-Mask: 0x01) */ +#define USB_NDDRINTCLR_EPNDDINTCLR10_Pos (10UL) /*!< EPNDDINTCLR10 (Bit 10) */ +#define USB_NDDRINTCLR_EPNDDINTCLR10_Msk (0x400UL) /*!< EPNDDINTCLR10 (Bitfield-Mask: 0x01) */ +#define USB_NDDRINTCLR_EPNDDINTCLR11_Pos (11UL) /*!< EPNDDINTCLR11 (Bit 11) */ +#define USB_NDDRINTCLR_EPNDDINTCLR11_Msk (0x800UL) /*!< EPNDDINTCLR11 (Bitfield-Mask: 0x01) */ +#define USB_NDDRINTCLR_EPNDDINTCLR12_Pos (12UL) /*!< EPNDDINTCLR12 (Bit 12) */ +#define USB_NDDRINTCLR_EPNDDINTCLR12_Msk (0x1000UL) /*!< EPNDDINTCLR12 (Bitfield-Mask: 0x01) */ +#define USB_NDDRINTCLR_EPNDDINTCLR13_Pos (13UL) /*!< EPNDDINTCLR13 (Bit 13) */ +#define USB_NDDRINTCLR_EPNDDINTCLR13_Msk (0x2000UL) /*!< EPNDDINTCLR13 (Bitfield-Mask: 0x01) */ +#define USB_NDDRINTCLR_EPNDDINTCLR14_Pos (14UL) /*!< EPNDDINTCLR14 (Bit 14) */ +#define USB_NDDRINTCLR_EPNDDINTCLR14_Msk (0x4000UL) /*!< EPNDDINTCLR14 (Bitfield-Mask: 0x01) */ +#define USB_NDDRINTCLR_EPNDDINTCLR15_Pos (15UL) /*!< EPNDDINTCLR15 (Bit 15) */ +#define USB_NDDRINTCLR_EPNDDINTCLR15_Msk (0x8000UL) /*!< EPNDDINTCLR15 (Bitfield-Mask: 0x01) */ +#define USB_NDDRINTCLR_EPNDDINTCLR16_Pos (16UL) /*!< EPNDDINTCLR16 (Bit 16) */ +#define USB_NDDRINTCLR_EPNDDINTCLR16_Msk (0x10000UL) /*!< EPNDDINTCLR16 (Bitfield-Mask: 0x01) */ +#define USB_NDDRINTCLR_EPNDDINTCLR17_Pos (17UL) /*!< EPNDDINTCLR17 (Bit 17) */ +#define USB_NDDRINTCLR_EPNDDINTCLR17_Msk (0x20000UL) /*!< EPNDDINTCLR17 (Bitfield-Mask: 0x01) */ +#define USB_NDDRINTCLR_EPNDDINTCLR18_Pos (18UL) /*!< EPNDDINTCLR18 (Bit 18) */ +#define USB_NDDRINTCLR_EPNDDINTCLR18_Msk (0x40000UL) /*!< EPNDDINTCLR18 (Bitfield-Mask: 0x01) */ +#define USB_NDDRINTCLR_EPNDDINTCLR19_Pos (19UL) /*!< EPNDDINTCLR19 (Bit 19) */ +#define USB_NDDRINTCLR_EPNDDINTCLR19_Msk (0x80000UL) /*!< EPNDDINTCLR19 (Bitfield-Mask: 0x01) */ +#define USB_NDDRINTCLR_EPNDDINTCLR20_Pos (20UL) /*!< EPNDDINTCLR20 (Bit 20) */ +#define USB_NDDRINTCLR_EPNDDINTCLR20_Msk (0x100000UL) /*!< EPNDDINTCLR20 (Bitfield-Mask: 0x01) */ +#define USB_NDDRINTCLR_EPNDDINTCLR21_Pos (21UL) /*!< EPNDDINTCLR21 (Bit 21) */ +#define USB_NDDRINTCLR_EPNDDINTCLR21_Msk (0x200000UL) /*!< EPNDDINTCLR21 (Bitfield-Mask: 0x01) */ +#define USB_NDDRINTCLR_EPNDDINTCLR22_Pos (22UL) /*!< EPNDDINTCLR22 (Bit 22) */ +#define USB_NDDRINTCLR_EPNDDINTCLR22_Msk (0x400000UL) /*!< EPNDDINTCLR22 (Bitfield-Mask: 0x01) */ +#define USB_NDDRINTCLR_EPNDDINTCLR23_Pos (23UL) /*!< EPNDDINTCLR23 (Bit 23) */ +#define USB_NDDRINTCLR_EPNDDINTCLR23_Msk (0x800000UL) /*!< EPNDDINTCLR23 (Bitfield-Mask: 0x01) */ +#define USB_NDDRINTCLR_EPNDDINTCLR24_Pos (24UL) /*!< EPNDDINTCLR24 (Bit 24) */ +#define USB_NDDRINTCLR_EPNDDINTCLR24_Msk (0x1000000UL) /*!< EPNDDINTCLR24 (Bitfield-Mask: 0x01) */ +#define USB_NDDRINTCLR_EPNDDINTCLR25_Pos (25UL) /*!< EPNDDINTCLR25 (Bit 25) */ +#define USB_NDDRINTCLR_EPNDDINTCLR25_Msk (0x2000000UL) /*!< EPNDDINTCLR25 (Bitfield-Mask: 0x01) */ +#define USB_NDDRINTCLR_EPNDDINTCLR26_Pos (26UL) /*!< EPNDDINTCLR26 (Bit 26) */ +#define USB_NDDRINTCLR_EPNDDINTCLR26_Msk (0x4000000UL) /*!< EPNDDINTCLR26 (Bitfield-Mask: 0x01) */ +#define USB_NDDRINTCLR_EPNDDINTCLR27_Pos (27UL) /*!< EPNDDINTCLR27 (Bit 27) */ +#define USB_NDDRINTCLR_EPNDDINTCLR27_Msk (0x8000000UL) /*!< EPNDDINTCLR27 (Bitfield-Mask: 0x01) */ +#define USB_NDDRINTCLR_EPNDDINTCLR28_Pos (28UL) /*!< EPNDDINTCLR28 (Bit 28) */ +#define USB_NDDRINTCLR_EPNDDINTCLR28_Msk (0x10000000UL) /*!< EPNDDINTCLR28 (Bitfield-Mask: 0x01) */ +#define USB_NDDRINTCLR_EPNDDINTCLR29_Pos (29UL) /*!< EPNDDINTCLR29 (Bit 29) */ +#define USB_NDDRINTCLR_EPNDDINTCLR29_Msk (0x20000000UL) /*!< EPNDDINTCLR29 (Bitfield-Mask: 0x01) */ +#define USB_NDDRINTCLR_EPNDDINTCLR30_Pos (30UL) /*!< EPNDDINTCLR30 (Bit 30) */ +#define USB_NDDRINTCLR_EPNDDINTCLR30_Msk (0x40000000UL) /*!< EPNDDINTCLR30 (Bitfield-Mask: 0x01) */ +#define USB_NDDRINTCLR_EPNDDINTCLR31_Pos (31UL) /*!< EPNDDINTCLR31 (Bit 31) */ +#define USB_NDDRINTCLR_EPNDDINTCLR31_Msk (0x80000000UL) /*!< EPNDDINTCLR31 (Bitfield-Mask: 0x01) */ +/* ====================================================== NDDRINTSET ======================================================= */ +#define USB_NDDRINTSET_EPNDDINTSET0_Pos (0UL) /*!< EPNDDINTSET0 (Bit 0) */ +#define USB_NDDRINTSET_EPNDDINTSET0_Msk (0x1UL) /*!< EPNDDINTSET0 (Bitfield-Mask: 0x01) */ +#define USB_NDDRINTSET_EPNDDINTSET1_Pos (1UL) /*!< EPNDDINTSET1 (Bit 1) */ +#define USB_NDDRINTSET_EPNDDINTSET1_Msk (0x2UL) /*!< EPNDDINTSET1 (Bitfield-Mask: 0x01) */ +#define USB_NDDRINTSET_EPNDDINTSET2_Pos (2UL) /*!< EPNDDINTSET2 (Bit 2) */ +#define USB_NDDRINTSET_EPNDDINTSET2_Msk (0x4UL) /*!< EPNDDINTSET2 (Bitfield-Mask: 0x01) */ +#define USB_NDDRINTSET_EPNDDINTSET3_Pos (3UL) /*!< EPNDDINTSET3 (Bit 3) */ +#define USB_NDDRINTSET_EPNDDINTSET3_Msk (0x8UL) /*!< EPNDDINTSET3 (Bitfield-Mask: 0x01) */ +#define USB_NDDRINTSET_EPNDDINTSET4_Pos (4UL) /*!< EPNDDINTSET4 (Bit 4) */ +#define USB_NDDRINTSET_EPNDDINTSET4_Msk (0x10UL) /*!< EPNDDINTSET4 (Bitfield-Mask: 0x01) */ +#define USB_NDDRINTSET_EPNDDINTSET5_Pos (5UL) /*!< EPNDDINTSET5 (Bit 5) */ +#define USB_NDDRINTSET_EPNDDINTSET5_Msk (0x20UL) /*!< EPNDDINTSET5 (Bitfield-Mask: 0x01) */ +#define USB_NDDRINTSET_EPNDDINTSET6_Pos (6UL) /*!< EPNDDINTSET6 (Bit 6) */ +#define USB_NDDRINTSET_EPNDDINTSET6_Msk (0x40UL) /*!< EPNDDINTSET6 (Bitfield-Mask: 0x01) */ +#define USB_NDDRINTSET_EPNDDINTSET7_Pos (7UL) /*!< EPNDDINTSET7 (Bit 7) */ +#define USB_NDDRINTSET_EPNDDINTSET7_Msk (0x80UL) /*!< EPNDDINTSET7 (Bitfield-Mask: 0x01) */ +#define USB_NDDRINTSET_EPNDDINTSET8_Pos (8UL) /*!< EPNDDINTSET8 (Bit 8) */ +#define USB_NDDRINTSET_EPNDDINTSET8_Msk (0x100UL) /*!< EPNDDINTSET8 (Bitfield-Mask: 0x01) */ +#define USB_NDDRINTSET_EPNDDINTSET9_Pos (9UL) /*!< EPNDDINTSET9 (Bit 9) */ +#define USB_NDDRINTSET_EPNDDINTSET9_Msk (0x200UL) /*!< EPNDDINTSET9 (Bitfield-Mask: 0x01) */ +#define USB_NDDRINTSET_EPNDDINTSET10_Pos (10UL) /*!< EPNDDINTSET10 (Bit 10) */ +#define USB_NDDRINTSET_EPNDDINTSET10_Msk (0x400UL) /*!< EPNDDINTSET10 (Bitfield-Mask: 0x01) */ +#define USB_NDDRINTSET_EPNDDINTSET11_Pos (11UL) /*!< EPNDDINTSET11 (Bit 11) */ +#define USB_NDDRINTSET_EPNDDINTSET11_Msk (0x800UL) /*!< EPNDDINTSET11 (Bitfield-Mask: 0x01) */ +#define USB_NDDRINTSET_EPNDDINTSET12_Pos (12UL) /*!< EPNDDINTSET12 (Bit 12) */ +#define USB_NDDRINTSET_EPNDDINTSET12_Msk (0x1000UL) /*!< EPNDDINTSET12 (Bitfield-Mask: 0x01) */ +#define USB_NDDRINTSET_EPNDDINTSET13_Pos (13UL) /*!< EPNDDINTSET13 (Bit 13) */ +#define USB_NDDRINTSET_EPNDDINTSET13_Msk (0x2000UL) /*!< EPNDDINTSET13 (Bitfield-Mask: 0x01) */ +#define USB_NDDRINTSET_EPNDDINTSET14_Pos (14UL) /*!< EPNDDINTSET14 (Bit 14) */ +#define USB_NDDRINTSET_EPNDDINTSET14_Msk (0x4000UL) /*!< EPNDDINTSET14 (Bitfield-Mask: 0x01) */ +#define USB_NDDRINTSET_EPNDDINTSET15_Pos (15UL) /*!< EPNDDINTSET15 (Bit 15) */ +#define USB_NDDRINTSET_EPNDDINTSET15_Msk (0x8000UL) /*!< EPNDDINTSET15 (Bitfield-Mask: 0x01) */ +#define USB_NDDRINTSET_EPNDDINTSET16_Pos (16UL) /*!< EPNDDINTSET16 (Bit 16) */ +#define USB_NDDRINTSET_EPNDDINTSET16_Msk (0x10000UL) /*!< EPNDDINTSET16 (Bitfield-Mask: 0x01) */ +#define USB_NDDRINTSET_EPNDDINTSET17_Pos (17UL) /*!< EPNDDINTSET17 (Bit 17) */ +#define USB_NDDRINTSET_EPNDDINTSET17_Msk (0x20000UL) /*!< EPNDDINTSET17 (Bitfield-Mask: 0x01) */ +#define USB_NDDRINTSET_EPNDDINTSET18_Pos (18UL) /*!< EPNDDINTSET18 (Bit 18) */ +#define USB_NDDRINTSET_EPNDDINTSET18_Msk (0x40000UL) /*!< EPNDDINTSET18 (Bitfield-Mask: 0x01) */ +#define USB_NDDRINTSET_EPNDDINTSET19_Pos (19UL) /*!< EPNDDINTSET19 (Bit 19) */ +#define USB_NDDRINTSET_EPNDDINTSET19_Msk (0x80000UL) /*!< EPNDDINTSET19 (Bitfield-Mask: 0x01) */ +#define USB_NDDRINTSET_EPNDDINTSET20_Pos (20UL) /*!< EPNDDINTSET20 (Bit 20) */ +#define USB_NDDRINTSET_EPNDDINTSET20_Msk (0x100000UL) /*!< EPNDDINTSET20 (Bitfield-Mask: 0x01) */ +#define USB_NDDRINTSET_EPNDDINTSET21_Pos (21UL) /*!< EPNDDINTSET21 (Bit 21) */ +#define USB_NDDRINTSET_EPNDDINTSET21_Msk (0x200000UL) /*!< EPNDDINTSET21 (Bitfield-Mask: 0x01) */ +#define USB_NDDRINTSET_EPNDDINTSET22_Pos (22UL) /*!< EPNDDINTSET22 (Bit 22) */ +#define USB_NDDRINTSET_EPNDDINTSET22_Msk (0x400000UL) /*!< EPNDDINTSET22 (Bitfield-Mask: 0x01) */ +#define USB_NDDRINTSET_EPNDDINTSET23_Pos (23UL) /*!< EPNDDINTSET23 (Bit 23) */ +#define USB_NDDRINTSET_EPNDDINTSET23_Msk (0x800000UL) /*!< EPNDDINTSET23 (Bitfield-Mask: 0x01) */ +#define USB_NDDRINTSET_EPNDDINTSET24_Pos (24UL) /*!< EPNDDINTSET24 (Bit 24) */ +#define USB_NDDRINTSET_EPNDDINTSET24_Msk (0x1000000UL) /*!< EPNDDINTSET24 (Bitfield-Mask: 0x01) */ +#define USB_NDDRINTSET_EPNDDINTSET25_Pos (25UL) /*!< EPNDDINTSET25 (Bit 25) */ +#define USB_NDDRINTSET_EPNDDINTSET25_Msk (0x2000000UL) /*!< EPNDDINTSET25 (Bitfield-Mask: 0x01) */ +#define USB_NDDRINTSET_EPNDDINTSET26_Pos (26UL) /*!< EPNDDINTSET26 (Bit 26) */ +#define USB_NDDRINTSET_EPNDDINTSET26_Msk (0x4000000UL) /*!< EPNDDINTSET26 (Bitfield-Mask: 0x01) */ +#define USB_NDDRINTSET_EPNDDINTSET27_Pos (27UL) /*!< EPNDDINTSET27 (Bit 27) */ +#define USB_NDDRINTSET_EPNDDINTSET27_Msk (0x8000000UL) /*!< EPNDDINTSET27 (Bitfield-Mask: 0x01) */ +#define USB_NDDRINTSET_EPNDDINTSET28_Pos (28UL) /*!< EPNDDINTSET28 (Bit 28) */ +#define USB_NDDRINTSET_EPNDDINTSET28_Msk (0x10000000UL) /*!< EPNDDINTSET28 (Bitfield-Mask: 0x01) */ +#define USB_NDDRINTSET_EPNDDINTSET29_Pos (29UL) /*!< EPNDDINTSET29 (Bit 29) */ +#define USB_NDDRINTSET_EPNDDINTSET29_Msk (0x20000000UL) /*!< EPNDDINTSET29 (Bitfield-Mask: 0x01) */ +#define USB_NDDRINTSET_EPNDDINTSET30_Pos (30UL) /*!< EPNDDINTSET30 (Bit 30) */ +#define USB_NDDRINTSET_EPNDDINTSET30_Msk (0x40000000UL) /*!< EPNDDINTSET30 (Bitfield-Mask: 0x01) */ +#define USB_NDDRINTSET_EPNDDINTSET31_Pos (31UL) /*!< EPNDDINTSET31 (Bit 31) */ +#define USB_NDDRINTSET_EPNDDINTSET31_Msk (0x80000000UL) /*!< EPNDDINTSET31 (Bitfield-Mask: 0x01) */ +/* ====================================================== SYSERRINTST ====================================================== */ +#define USB_SYSERRINTST_EPERRINTST0_Pos (0UL) /*!< EPERRINTST0 (Bit 0) */ +#define USB_SYSERRINTST_EPERRINTST0_Msk (0x1UL) /*!< EPERRINTST0 (Bitfield-Mask: 0x01) */ +#define USB_SYSERRINTST_EPERRINTST1_Pos (1UL) /*!< EPERRINTST1 (Bit 1) */ +#define USB_SYSERRINTST_EPERRINTST1_Msk (0x2UL) /*!< EPERRINTST1 (Bitfield-Mask: 0x01) */ +#define USB_SYSERRINTST_EPERRINTST2_Pos (2UL) /*!< EPERRINTST2 (Bit 2) */ +#define USB_SYSERRINTST_EPERRINTST2_Msk (0x4UL) /*!< EPERRINTST2 (Bitfield-Mask: 0x01) */ +#define USB_SYSERRINTST_EPERRINTST3_Pos (3UL) /*!< EPERRINTST3 (Bit 3) */ +#define USB_SYSERRINTST_EPERRINTST3_Msk (0x8UL) /*!< EPERRINTST3 (Bitfield-Mask: 0x01) */ +#define USB_SYSERRINTST_EPERRINTST4_Pos (4UL) /*!< EPERRINTST4 (Bit 4) */ +#define USB_SYSERRINTST_EPERRINTST4_Msk (0x10UL) /*!< EPERRINTST4 (Bitfield-Mask: 0x01) */ +#define USB_SYSERRINTST_EPERRINTST5_Pos (5UL) /*!< EPERRINTST5 (Bit 5) */ +#define USB_SYSERRINTST_EPERRINTST5_Msk (0x20UL) /*!< EPERRINTST5 (Bitfield-Mask: 0x01) */ +#define USB_SYSERRINTST_EPERRINTST6_Pos (6UL) /*!< EPERRINTST6 (Bit 6) */ +#define USB_SYSERRINTST_EPERRINTST6_Msk (0x40UL) /*!< EPERRINTST6 (Bitfield-Mask: 0x01) */ +#define USB_SYSERRINTST_EPERRINTST7_Pos (7UL) /*!< EPERRINTST7 (Bit 7) */ +#define USB_SYSERRINTST_EPERRINTST7_Msk (0x80UL) /*!< EPERRINTST7 (Bitfield-Mask: 0x01) */ +#define USB_SYSERRINTST_EPERRINTST8_Pos (8UL) /*!< EPERRINTST8 (Bit 8) */ +#define USB_SYSERRINTST_EPERRINTST8_Msk (0x100UL) /*!< EPERRINTST8 (Bitfield-Mask: 0x01) */ +#define USB_SYSERRINTST_EPERRINTST9_Pos (9UL) /*!< EPERRINTST9 (Bit 9) */ +#define USB_SYSERRINTST_EPERRINTST9_Msk (0x200UL) /*!< EPERRINTST9 (Bitfield-Mask: 0x01) */ +#define USB_SYSERRINTST_EPERRINTST10_Pos (10UL) /*!< EPERRINTST10 (Bit 10) */ +#define USB_SYSERRINTST_EPERRINTST10_Msk (0x400UL) /*!< EPERRINTST10 (Bitfield-Mask: 0x01) */ +#define USB_SYSERRINTST_EPERRINTST11_Pos (11UL) /*!< EPERRINTST11 (Bit 11) */ +#define USB_SYSERRINTST_EPERRINTST11_Msk (0x800UL) /*!< EPERRINTST11 (Bitfield-Mask: 0x01) */ +#define USB_SYSERRINTST_EPERRINTST12_Pos (12UL) /*!< EPERRINTST12 (Bit 12) */ +#define USB_SYSERRINTST_EPERRINTST12_Msk (0x1000UL) /*!< EPERRINTST12 (Bitfield-Mask: 0x01) */ +#define USB_SYSERRINTST_EPERRINTST13_Pos (13UL) /*!< EPERRINTST13 (Bit 13) */ +#define USB_SYSERRINTST_EPERRINTST13_Msk (0x2000UL) /*!< EPERRINTST13 (Bitfield-Mask: 0x01) */ +#define USB_SYSERRINTST_EPERRINTST14_Pos (14UL) /*!< EPERRINTST14 (Bit 14) */ +#define USB_SYSERRINTST_EPERRINTST14_Msk (0x4000UL) /*!< EPERRINTST14 (Bitfield-Mask: 0x01) */ +#define USB_SYSERRINTST_EPERRINTST15_Pos (15UL) /*!< EPERRINTST15 (Bit 15) */ +#define USB_SYSERRINTST_EPERRINTST15_Msk (0x8000UL) /*!< EPERRINTST15 (Bitfield-Mask: 0x01) */ +#define USB_SYSERRINTST_EPERRINTST16_Pos (16UL) /*!< EPERRINTST16 (Bit 16) */ +#define USB_SYSERRINTST_EPERRINTST16_Msk (0x10000UL) /*!< EPERRINTST16 (Bitfield-Mask: 0x01) */ +#define USB_SYSERRINTST_EPERRINTST17_Pos (17UL) /*!< EPERRINTST17 (Bit 17) */ +#define USB_SYSERRINTST_EPERRINTST17_Msk (0x20000UL) /*!< EPERRINTST17 (Bitfield-Mask: 0x01) */ +#define USB_SYSERRINTST_EPERRINTST18_Pos (18UL) /*!< EPERRINTST18 (Bit 18) */ +#define USB_SYSERRINTST_EPERRINTST18_Msk (0x40000UL) /*!< EPERRINTST18 (Bitfield-Mask: 0x01) */ +#define USB_SYSERRINTST_EPERRINTST19_Pos (19UL) /*!< EPERRINTST19 (Bit 19) */ +#define USB_SYSERRINTST_EPERRINTST19_Msk (0x80000UL) /*!< EPERRINTST19 (Bitfield-Mask: 0x01) */ +#define USB_SYSERRINTST_EPERRINTST20_Pos (20UL) /*!< EPERRINTST20 (Bit 20) */ +#define USB_SYSERRINTST_EPERRINTST20_Msk (0x100000UL) /*!< EPERRINTST20 (Bitfield-Mask: 0x01) */ +#define USB_SYSERRINTST_EPERRINTST21_Pos (21UL) /*!< EPERRINTST21 (Bit 21) */ +#define USB_SYSERRINTST_EPERRINTST21_Msk (0x200000UL) /*!< EPERRINTST21 (Bitfield-Mask: 0x01) */ +#define USB_SYSERRINTST_EPERRINTST22_Pos (22UL) /*!< EPERRINTST22 (Bit 22) */ +#define USB_SYSERRINTST_EPERRINTST22_Msk (0x400000UL) /*!< EPERRINTST22 (Bitfield-Mask: 0x01) */ +#define USB_SYSERRINTST_EPERRINTST23_Pos (23UL) /*!< EPERRINTST23 (Bit 23) */ +#define USB_SYSERRINTST_EPERRINTST23_Msk (0x800000UL) /*!< EPERRINTST23 (Bitfield-Mask: 0x01) */ +#define USB_SYSERRINTST_EPERRINTST24_Pos (24UL) /*!< EPERRINTST24 (Bit 24) */ +#define USB_SYSERRINTST_EPERRINTST24_Msk (0x1000000UL) /*!< EPERRINTST24 (Bitfield-Mask: 0x01) */ +#define USB_SYSERRINTST_EPERRINTST25_Pos (25UL) /*!< EPERRINTST25 (Bit 25) */ +#define USB_SYSERRINTST_EPERRINTST25_Msk (0x2000000UL) /*!< EPERRINTST25 (Bitfield-Mask: 0x01) */ +#define USB_SYSERRINTST_EPERRINTST26_Pos (26UL) /*!< EPERRINTST26 (Bit 26) */ +#define USB_SYSERRINTST_EPERRINTST26_Msk (0x4000000UL) /*!< EPERRINTST26 (Bitfield-Mask: 0x01) */ +#define USB_SYSERRINTST_EPERRINTST27_Pos (27UL) /*!< EPERRINTST27 (Bit 27) */ +#define USB_SYSERRINTST_EPERRINTST27_Msk (0x8000000UL) /*!< EPERRINTST27 (Bitfield-Mask: 0x01) */ +#define USB_SYSERRINTST_EPERRINTST28_Pos (28UL) /*!< EPERRINTST28 (Bit 28) */ +#define USB_SYSERRINTST_EPERRINTST28_Msk (0x10000000UL) /*!< EPERRINTST28 (Bitfield-Mask: 0x01) */ +#define USB_SYSERRINTST_EPERRINTST29_Pos (29UL) /*!< EPERRINTST29 (Bit 29) */ +#define USB_SYSERRINTST_EPERRINTST29_Msk (0x20000000UL) /*!< EPERRINTST29 (Bitfield-Mask: 0x01) */ +#define USB_SYSERRINTST_EPERRINTST30_Pos (30UL) /*!< EPERRINTST30 (Bit 30) */ +#define USB_SYSERRINTST_EPERRINTST30_Msk (0x40000000UL) /*!< EPERRINTST30 (Bitfield-Mask: 0x01) */ +#define USB_SYSERRINTST_EPERRINTST31_Pos (31UL) /*!< EPERRINTST31 (Bit 31) */ +#define USB_SYSERRINTST_EPERRINTST31_Msk (0x80000000UL) /*!< EPERRINTST31 (Bitfield-Mask: 0x01) */ +/* ===================================================== SYSERRINTCLR ====================================================== */ +#define USB_SYSERRINTCLR_EPERRINTCLR0_Pos (0UL) /*!< EPERRINTCLR0 (Bit 0) */ +#define USB_SYSERRINTCLR_EPERRINTCLR0_Msk (0x1UL) /*!< EPERRINTCLR0 (Bitfield-Mask: 0x01) */ +#define USB_SYSERRINTCLR_EPERRINTCLR1_Pos (1UL) /*!< EPERRINTCLR1 (Bit 1) */ +#define USB_SYSERRINTCLR_EPERRINTCLR1_Msk (0x2UL) /*!< EPERRINTCLR1 (Bitfield-Mask: 0x01) */ +#define USB_SYSERRINTCLR_EPERRINTCLR2_Pos (2UL) /*!< EPERRINTCLR2 (Bit 2) */ +#define USB_SYSERRINTCLR_EPERRINTCLR2_Msk (0x4UL) /*!< EPERRINTCLR2 (Bitfield-Mask: 0x01) */ +#define USB_SYSERRINTCLR_EPERRINTCLR3_Pos (3UL) /*!< EPERRINTCLR3 (Bit 3) */ +#define USB_SYSERRINTCLR_EPERRINTCLR3_Msk (0x8UL) /*!< EPERRINTCLR3 (Bitfield-Mask: 0x01) */ +#define USB_SYSERRINTCLR_EPERRINTCLR4_Pos (4UL) /*!< EPERRINTCLR4 (Bit 4) */ +#define USB_SYSERRINTCLR_EPERRINTCLR4_Msk (0x10UL) /*!< EPERRINTCLR4 (Bitfield-Mask: 0x01) */ +#define USB_SYSERRINTCLR_EPERRINTCLR5_Pos (5UL) /*!< EPERRINTCLR5 (Bit 5) */ +#define USB_SYSERRINTCLR_EPERRINTCLR5_Msk (0x20UL) /*!< EPERRINTCLR5 (Bitfield-Mask: 0x01) */ +#define USB_SYSERRINTCLR_EPERRINTCLR6_Pos (6UL) /*!< EPERRINTCLR6 (Bit 6) */ +#define USB_SYSERRINTCLR_EPERRINTCLR6_Msk (0x40UL) /*!< EPERRINTCLR6 (Bitfield-Mask: 0x01) */ +#define USB_SYSERRINTCLR_EPERRINTCLR7_Pos (7UL) /*!< EPERRINTCLR7 (Bit 7) */ +#define USB_SYSERRINTCLR_EPERRINTCLR7_Msk (0x80UL) /*!< EPERRINTCLR7 (Bitfield-Mask: 0x01) */ +#define USB_SYSERRINTCLR_EPERRINTCLR8_Pos (8UL) /*!< EPERRINTCLR8 (Bit 8) */ +#define USB_SYSERRINTCLR_EPERRINTCLR8_Msk (0x100UL) /*!< EPERRINTCLR8 (Bitfield-Mask: 0x01) */ +#define USB_SYSERRINTCLR_EPERRINTCLR9_Pos (9UL) /*!< EPERRINTCLR9 (Bit 9) */ +#define USB_SYSERRINTCLR_EPERRINTCLR9_Msk (0x200UL) /*!< EPERRINTCLR9 (Bitfield-Mask: 0x01) */ +#define USB_SYSERRINTCLR_EPERRINTCLR10_Pos (10UL) /*!< EPERRINTCLR10 (Bit 10) */ +#define USB_SYSERRINTCLR_EPERRINTCLR10_Msk (0x400UL) /*!< EPERRINTCLR10 (Bitfield-Mask: 0x01) */ +#define USB_SYSERRINTCLR_EPERRINTCLR11_Pos (11UL) /*!< EPERRINTCLR11 (Bit 11) */ +#define USB_SYSERRINTCLR_EPERRINTCLR11_Msk (0x800UL) /*!< EPERRINTCLR11 (Bitfield-Mask: 0x01) */ +#define USB_SYSERRINTCLR_EPERRINTCLR12_Pos (12UL) /*!< EPERRINTCLR12 (Bit 12) */ +#define USB_SYSERRINTCLR_EPERRINTCLR12_Msk (0x1000UL) /*!< EPERRINTCLR12 (Bitfield-Mask: 0x01) */ +#define USB_SYSERRINTCLR_EPERRINTCLR13_Pos (13UL) /*!< EPERRINTCLR13 (Bit 13) */ +#define USB_SYSERRINTCLR_EPERRINTCLR13_Msk (0x2000UL) /*!< EPERRINTCLR13 (Bitfield-Mask: 0x01) */ +#define USB_SYSERRINTCLR_EPERRINTCLR14_Pos (14UL) /*!< EPERRINTCLR14 (Bit 14) */ +#define USB_SYSERRINTCLR_EPERRINTCLR14_Msk (0x4000UL) /*!< EPERRINTCLR14 (Bitfield-Mask: 0x01) */ +#define USB_SYSERRINTCLR_EPERRINTCLR15_Pos (15UL) /*!< EPERRINTCLR15 (Bit 15) */ +#define USB_SYSERRINTCLR_EPERRINTCLR15_Msk (0x8000UL) /*!< EPERRINTCLR15 (Bitfield-Mask: 0x01) */ +#define USB_SYSERRINTCLR_EPERRINTCLR16_Pos (16UL) /*!< EPERRINTCLR16 (Bit 16) */ +#define USB_SYSERRINTCLR_EPERRINTCLR16_Msk (0x10000UL) /*!< EPERRINTCLR16 (Bitfield-Mask: 0x01) */ +#define USB_SYSERRINTCLR_EPERRINTCLR17_Pos (17UL) /*!< EPERRINTCLR17 (Bit 17) */ +#define USB_SYSERRINTCLR_EPERRINTCLR17_Msk (0x20000UL) /*!< EPERRINTCLR17 (Bitfield-Mask: 0x01) */ +#define USB_SYSERRINTCLR_EPERRINTCLR18_Pos (18UL) /*!< EPERRINTCLR18 (Bit 18) */ +#define USB_SYSERRINTCLR_EPERRINTCLR18_Msk (0x40000UL) /*!< EPERRINTCLR18 (Bitfield-Mask: 0x01) */ +#define USB_SYSERRINTCLR_EPERRINTCLR19_Pos (19UL) /*!< EPERRINTCLR19 (Bit 19) */ +#define USB_SYSERRINTCLR_EPERRINTCLR19_Msk (0x80000UL) /*!< EPERRINTCLR19 (Bitfield-Mask: 0x01) */ +#define USB_SYSERRINTCLR_EPERRINTCLR20_Pos (20UL) /*!< EPERRINTCLR20 (Bit 20) */ +#define USB_SYSERRINTCLR_EPERRINTCLR20_Msk (0x100000UL) /*!< EPERRINTCLR20 (Bitfield-Mask: 0x01) */ +#define USB_SYSERRINTCLR_EPERRINTCLR21_Pos (21UL) /*!< EPERRINTCLR21 (Bit 21) */ +#define USB_SYSERRINTCLR_EPERRINTCLR21_Msk (0x200000UL) /*!< EPERRINTCLR21 (Bitfield-Mask: 0x01) */ +#define USB_SYSERRINTCLR_EPERRINTCLR22_Pos (22UL) /*!< EPERRINTCLR22 (Bit 22) */ +#define USB_SYSERRINTCLR_EPERRINTCLR22_Msk (0x400000UL) /*!< EPERRINTCLR22 (Bitfield-Mask: 0x01) */ +#define USB_SYSERRINTCLR_EPERRINTCLR23_Pos (23UL) /*!< EPERRINTCLR23 (Bit 23) */ +#define USB_SYSERRINTCLR_EPERRINTCLR23_Msk (0x800000UL) /*!< EPERRINTCLR23 (Bitfield-Mask: 0x01) */ +#define USB_SYSERRINTCLR_EPERRINTCLR24_Pos (24UL) /*!< EPERRINTCLR24 (Bit 24) */ +#define USB_SYSERRINTCLR_EPERRINTCLR24_Msk (0x1000000UL) /*!< EPERRINTCLR24 (Bitfield-Mask: 0x01) */ +#define USB_SYSERRINTCLR_EPERRINTCLR25_Pos (25UL) /*!< EPERRINTCLR25 (Bit 25) */ +#define USB_SYSERRINTCLR_EPERRINTCLR25_Msk (0x2000000UL) /*!< EPERRINTCLR25 (Bitfield-Mask: 0x01) */ +#define USB_SYSERRINTCLR_EPERRINTCLR26_Pos (26UL) /*!< EPERRINTCLR26 (Bit 26) */ +#define USB_SYSERRINTCLR_EPERRINTCLR26_Msk (0x4000000UL) /*!< EPERRINTCLR26 (Bitfield-Mask: 0x01) */ +#define USB_SYSERRINTCLR_EPERRINTCLR27_Pos (27UL) /*!< EPERRINTCLR27 (Bit 27) */ +#define USB_SYSERRINTCLR_EPERRINTCLR27_Msk (0x8000000UL) /*!< EPERRINTCLR27 (Bitfield-Mask: 0x01) */ +#define USB_SYSERRINTCLR_EPERRINTCLR28_Pos (28UL) /*!< EPERRINTCLR28 (Bit 28) */ +#define USB_SYSERRINTCLR_EPERRINTCLR28_Msk (0x10000000UL) /*!< EPERRINTCLR28 (Bitfield-Mask: 0x01) */ +#define USB_SYSERRINTCLR_EPERRINTCLR29_Pos (29UL) /*!< EPERRINTCLR29 (Bit 29) */ +#define USB_SYSERRINTCLR_EPERRINTCLR29_Msk (0x20000000UL) /*!< EPERRINTCLR29 (Bitfield-Mask: 0x01) */ +#define USB_SYSERRINTCLR_EPERRINTCLR30_Pos (30UL) /*!< EPERRINTCLR30 (Bit 30) */ +#define USB_SYSERRINTCLR_EPERRINTCLR30_Msk (0x40000000UL) /*!< EPERRINTCLR30 (Bitfield-Mask: 0x01) */ +#define USB_SYSERRINTCLR_EPERRINTCLR31_Pos (31UL) /*!< EPERRINTCLR31 (Bit 31) */ +#define USB_SYSERRINTCLR_EPERRINTCLR31_Msk (0x80000000UL) /*!< EPERRINTCLR31 (Bitfield-Mask: 0x01) */ +/* ===================================================== SYSERRINTSET ====================================================== */ +#define USB_SYSERRINTSET_EPERRINTSET0_Pos (0UL) /*!< EPERRINTSET0 (Bit 0) */ +#define USB_SYSERRINTSET_EPERRINTSET0_Msk (0x1UL) /*!< EPERRINTSET0 (Bitfield-Mask: 0x01) */ +#define USB_SYSERRINTSET_EPERRINTSET1_Pos (1UL) /*!< EPERRINTSET1 (Bit 1) */ +#define USB_SYSERRINTSET_EPERRINTSET1_Msk (0x2UL) /*!< EPERRINTSET1 (Bitfield-Mask: 0x01) */ +#define USB_SYSERRINTSET_EPERRINTSET2_Pos (2UL) /*!< EPERRINTSET2 (Bit 2) */ +#define USB_SYSERRINTSET_EPERRINTSET2_Msk (0x4UL) /*!< EPERRINTSET2 (Bitfield-Mask: 0x01) */ +#define USB_SYSERRINTSET_EPERRINTSET3_Pos (3UL) /*!< EPERRINTSET3 (Bit 3) */ +#define USB_SYSERRINTSET_EPERRINTSET3_Msk (0x8UL) /*!< EPERRINTSET3 (Bitfield-Mask: 0x01) */ +#define USB_SYSERRINTSET_EPERRINTSET4_Pos (4UL) /*!< EPERRINTSET4 (Bit 4) */ +#define USB_SYSERRINTSET_EPERRINTSET4_Msk (0x10UL) /*!< EPERRINTSET4 (Bitfield-Mask: 0x01) */ +#define USB_SYSERRINTSET_EPERRINTSET5_Pos (5UL) /*!< EPERRINTSET5 (Bit 5) */ +#define USB_SYSERRINTSET_EPERRINTSET5_Msk (0x20UL) /*!< EPERRINTSET5 (Bitfield-Mask: 0x01) */ +#define USB_SYSERRINTSET_EPERRINTSET6_Pos (6UL) /*!< EPERRINTSET6 (Bit 6) */ +#define USB_SYSERRINTSET_EPERRINTSET6_Msk (0x40UL) /*!< EPERRINTSET6 (Bitfield-Mask: 0x01) */ +#define USB_SYSERRINTSET_EPERRINTSET7_Pos (7UL) /*!< EPERRINTSET7 (Bit 7) */ +#define USB_SYSERRINTSET_EPERRINTSET7_Msk (0x80UL) /*!< EPERRINTSET7 (Bitfield-Mask: 0x01) */ +#define USB_SYSERRINTSET_EPERRINTSET8_Pos (8UL) /*!< EPERRINTSET8 (Bit 8) */ +#define USB_SYSERRINTSET_EPERRINTSET8_Msk (0x100UL) /*!< EPERRINTSET8 (Bitfield-Mask: 0x01) */ +#define USB_SYSERRINTSET_EPERRINTSET9_Pos (9UL) /*!< EPERRINTSET9 (Bit 9) */ +#define USB_SYSERRINTSET_EPERRINTSET9_Msk (0x200UL) /*!< EPERRINTSET9 (Bitfield-Mask: 0x01) */ +#define USB_SYSERRINTSET_EPERRINTSET10_Pos (10UL) /*!< EPERRINTSET10 (Bit 10) */ +#define USB_SYSERRINTSET_EPERRINTSET10_Msk (0x400UL) /*!< EPERRINTSET10 (Bitfield-Mask: 0x01) */ +#define USB_SYSERRINTSET_EPERRINTSET11_Pos (11UL) /*!< EPERRINTSET11 (Bit 11) */ +#define USB_SYSERRINTSET_EPERRINTSET11_Msk (0x800UL) /*!< EPERRINTSET11 (Bitfield-Mask: 0x01) */ +#define USB_SYSERRINTSET_EPERRINTSET12_Pos (12UL) /*!< EPERRINTSET12 (Bit 12) */ +#define USB_SYSERRINTSET_EPERRINTSET12_Msk (0x1000UL) /*!< EPERRINTSET12 (Bitfield-Mask: 0x01) */ +#define USB_SYSERRINTSET_EPERRINTSET13_Pos (13UL) /*!< EPERRINTSET13 (Bit 13) */ +#define USB_SYSERRINTSET_EPERRINTSET13_Msk (0x2000UL) /*!< EPERRINTSET13 (Bitfield-Mask: 0x01) */ +#define USB_SYSERRINTSET_EPERRINTSET14_Pos (14UL) /*!< EPERRINTSET14 (Bit 14) */ +#define USB_SYSERRINTSET_EPERRINTSET14_Msk (0x4000UL) /*!< EPERRINTSET14 (Bitfield-Mask: 0x01) */ +#define USB_SYSERRINTSET_EPERRINTSET15_Pos (15UL) /*!< EPERRINTSET15 (Bit 15) */ +#define USB_SYSERRINTSET_EPERRINTSET15_Msk (0x8000UL) /*!< EPERRINTSET15 (Bitfield-Mask: 0x01) */ +#define USB_SYSERRINTSET_EPERRINTSET16_Pos (16UL) /*!< EPERRINTSET16 (Bit 16) */ +#define USB_SYSERRINTSET_EPERRINTSET16_Msk (0x10000UL) /*!< EPERRINTSET16 (Bitfield-Mask: 0x01) */ +#define USB_SYSERRINTSET_EPERRINTSET17_Pos (17UL) /*!< EPERRINTSET17 (Bit 17) */ +#define USB_SYSERRINTSET_EPERRINTSET17_Msk (0x20000UL) /*!< EPERRINTSET17 (Bitfield-Mask: 0x01) */ +#define USB_SYSERRINTSET_EPERRINTSET18_Pos (18UL) /*!< EPERRINTSET18 (Bit 18) */ +#define USB_SYSERRINTSET_EPERRINTSET18_Msk (0x40000UL) /*!< EPERRINTSET18 (Bitfield-Mask: 0x01) */ +#define USB_SYSERRINTSET_EPERRINTSET19_Pos (19UL) /*!< EPERRINTSET19 (Bit 19) */ +#define USB_SYSERRINTSET_EPERRINTSET19_Msk (0x80000UL) /*!< EPERRINTSET19 (Bitfield-Mask: 0x01) */ +#define USB_SYSERRINTSET_EPERRINTSET20_Pos (20UL) /*!< EPERRINTSET20 (Bit 20) */ +#define USB_SYSERRINTSET_EPERRINTSET20_Msk (0x100000UL) /*!< EPERRINTSET20 (Bitfield-Mask: 0x01) */ +#define USB_SYSERRINTSET_EPERRINTSET21_Pos (21UL) /*!< EPERRINTSET21 (Bit 21) */ +#define USB_SYSERRINTSET_EPERRINTSET21_Msk (0x200000UL) /*!< EPERRINTSET21 (Bitfield-Mask: 0x01) */ +#define USB_SYSERRINTSET_EPERRINTSET22_Pos (22UL) /*!< EPERRINTSET22 (Bit 22) */ +#define USB_SYSERRINTSET_EPERRINTSET22_Msk (0x400000UL) /*!< EPERRINTSET22 (Bitfield-Mask: 0x01) */ +#define USB_SYSERRINTSET_EPERRINTSET23_Pos (23UL) /*!< EPERRINTSET23 (Bit 23) */ +#define USB_SYSERRINTSET_EPERRINTSET23_Msk (0x800000UL) /*!< EPERRINTSET23 (Bitfield-Mask: 0x01) */ +#define USB_SYSERRINTSET_EPERRINTSET24_Pos (24UL) /*!< EPERRINTSET24 (Bit 24) */ +#define USB_SYSERRINTSET_EPERRINTSET24_Msk (0x1000000UL) /*!< EPERRINTSET24 (Bitfield-Mask: 0x01) */ +#define USB_SYSERRINTSET_EPERRINTSET25_Pos (25UL) /*!< EPERRINTSET25 (Bit 25) */ +#define USB_SYSERRINTSET_EPERRINTSET25_Msk (0x2000000UL) /*!< EPERRINTSET25 (Bitfield-Mask: 0x01) */ +#define USB_SYSERRINTSET_EPERRINTSET26_Pos (26UL) /*!< EPERRINTSET26 (Bit 26) */ +#define USB_SYSERRINTSET_EPERRINTSET26_Msk (0x4000000UL) /*!< EPERRINTSET26 (Bitfield-Mask: 0x01) */ +#define USB_SYSERRINTSET_EPERRINTSET27_Pos (27UL) /*!< EPERRINTSET27 (Bit 27) */ +#define USB_SYSERRINTSET_EPERRINTSET27_Msk (0x8000000UL) /*!< EPERRINTSET27 (Bitfield-Mask: 0x01) */ +#define USB_SYSERRINTSET_EPERRINTSET28_Pos (28UL) /*!< EPERRINTSET28 (Bit 28) */ +#define USB_SYSERRINTSET_EPERRINTSET28_Msk (0x10000000UL) /*!< EPERRINTSET28 (Bitfield-Mask: 0x01) */ +#define USB_SYSERRINTSET_EPERRINTSET29_Pos (29UL) /*!< EPERRINTSET29 (Bit 29) */ +#define USB_SYSERRINTSET_EPERRINTSET29_Msk (0x20000000UL) /*!< EPERRINTSET29 (Bitfield-Mask: 0x01) */ +#define USB_SYSERRINTSET_EPERRINTSET30_Pos (30UL) /*!< EPERRINTSET30 (Bit 30) */ +#define USB_SYSERRINTSET_EPERRINTSET30_Msk (0x40000000UL) /*!< EPERRINTSET30 (Bitfield-Mask: 0x01) */ +#define USB_SYSERRINTSET_EPERRINTSET31_Pos (31UL) /*!< EPERRINTSET31 (Bit 31) */ +#define USB_SYSERRINTSET_EPERRINTSET31_Msk (0x80000000UL) /*!< EPERRINTSET31 (Bitfield-Mask: 0x01) */ +/* ======================================================== I2C_RX ========================================================= */ +#define USB_I2C_RX_RXDATA_Pos (0UL) /*!< RXDATA (Bit 0) */ +#define USB_I2C_RX_RXDATA_Msk (0xffUL) /*!< RXDATA (Bitfield-Mask: 0xff) */ +/* ======================================================== I2C_WO ========================================================= */ +#define USB_I2C_WO_TXDATA_Pos (0UL) /*!< TXDATA (Bit 0) */ +#define USB_I2C_WO_TXDATA_Msk (0xffUL) /*!< TXDATA (Bitfield-Mask: 0xff) */ +#define USB_I2C_WO_START_Pos (8UL) /*!< START (Bit 8) */ +#define USB_I2C_WO_START_Msk (0x100UL) /*!< START (Bitfield-Mask: 0x01) */ +#define USB_I2C_WO_STOP_Pos (9UL) /*!< STOP (Bit 9) */ +#define USB_I2C_WO_STOP_Msk (0x200UL) /*!< STOP (Bitfield-Mask: 0x01) */ +/* ======================================================== I2C_STS ======================================================== */ +#define USB_I2C_STS_TDI_Pos (0UL) /*!< TDI (Bit 0) */ +#define USB_I2C_STS_TDI_Msk (0x1UL) /*!< TDI (Bitfield-Mask: 0x01) */ +#define USB_I2C_STS_AFI_Pos (1UL) /*!< AFI (Bit 1) */ +#define USB_I2C_STS_AFI_Msk (0x2UL) /*!< AFI (Bitfield-Mask: 0x01) */ +#define USB_I2C_STS_NAI_Pos (2UL) /*!< NAI (Bit 2) */ +#define USB_I2C_STS_NAI_Msk (0x4UL) /*!< NAI (Bitfield-Mask: 0x01) */ +#define USB_I2C_STS_DRMI_Pos (3UL) /*!< DRMI (Bit 3) */ +#define USB_I2C_STS_DRMI_Msk (0x8UL) /*!< DRMI (Bitfield-Mask: 0x01) */ +#define USB_I2C_STS_DRSI_Pos (4UL) /*!< DRSI (Bit 4) */ +#define USB_I2C_STS_DRSI_Msk (0x10UL) /*!< DRSI (Bitfield-Mask: 0x01) */ +#define USB_I2C_STS_Active_Pos (5UL) /*!< Active (Bit 5) */ +#define USB_I2C_STS_Active_Msk (0x20UL) /*!< Active (Bitfield-Mask: 0x01) */ +#define USB_I2C_STS_SCL_Pos (6UL) /*!< SCL (Bit 6) */ +#define USB_I2C_STS_SCL_Msk (0x40UL) /*!< SCL (Bitfield-Mask: 0x01) */ +#define USB_I2C_STS_SDA_Pos (7UL) /*!< SDA (Bit 7) */ +#define USB_I2C_STS_SDA_Msk (0x80UL) /*!< SDA (Bitfield-Mask: 0x01) */ +#define USB_I2C_STS_RFF_Pos (8UL) /*!< RFF (Bit 8) */ +#define USB_I2C_STS_RFF_Msk (0x100UL) /*!< RFF (Bitfield-Mask: 0x01) */ +#define USB_I2C_STS_RFE_Pos (9UL) /*!< RFE (Bit 9) */ +#define USB_I2C_STS_RFE_Msk (0x200UL) /*!< RFE (Bitfield-Mask: 0x01) */ +#define USB_I2C_STS_TFF_Pos (10UL) /*!< TFF (Bit 10) */ +#define USB_I2C_STS_TFF_Msk (0x400UL) /*!< TFF (Bitfield-Mask: 0x01) */ +#define USB_I2C_STS_TFE_Pos (11UL) /*!< TFE (Bit 11) */ +#define USB_I2C_STS_TFE_Msk (0x800UL) /*!< TFE (Bitfield-Mask: 0x01) */ +/* ======================================================== I2C_CTL ======================================================== */ +#define USB_I2C_CTL_TDIE_Pos (0UL) /*!< TDIE (Bit 0) */ +#define USB_I2C_CTL_TDIE_Msk (0x1UL) /*!< TDIE (Bitfield-Mask: 0x01) */ +#define USB_I2C_CTL_AFIE_Pos (1UL) /*!< AFIE (Bit 1) */ +#define USB_I2C_CTL_AFIE_Msk (0x2UL) /*!< AFIE (Bitfield-Mask: 0x01) */ +#define USB_I2C_CTL_NAIE_Pos (2UL) /*!< NAIE (Bit 2) */ +#define USB_I2C_CTL_NAIE_Msk (0x4UL) /*!< NAIE (Bitfield-Mask: 0x01) */ +#define USB_I2C_CTL_DRMIE_Pos (3UL) /*!< DRMIE (Bit 3) */ +#define USB_I2C_CTL_DRMIE_Msk (0x8UL) /*!< DRMIE (Bitfield-Mask: 0x01) */ +#define USB_I2C_CTL_DRSIE_Pos (4UL) /*!< DRSIE (Bit 4) */ +#define USB_I2C_CTL_DRSIE_Msk (0x10UL) /*!< DRSIE (Bitfield-Mask: 0x01) */ +#define USB_I2C_CTL_REFIE_Pos (5UL) /*!< REFIE (Bit 5) */ +#define USB_I2C_CTL_REFIE_Msk (0x20UL) /*!< REFIE (Bitfield-Mask: 0x01) */ +#define USB_I2C_CTL_RFDAIE_Pos (6UL) /*!< RFDAIE (Bit 6) */ +#define USB_I2C_CTL_RFDAIE_Msk (0x40UL) /*!< RFDAIE (Bitfield-Mask: 0x01) */ +#define USB_I2C_CTL_TFFIE_Pos (7UL) /*!< TFFIE (Bit 7) */ +#define USB_I2C_CTL_TFFIE_Msk (0x80UL) /*!< TFFIE (Bitfield-Mask: 0x01) */ +#define USB_I2C_CTL_SRST_Pos (8UL) /*!< SRST (Bit 8) */ +#define USB_I2C_CTL_SRST_Msk (0x100UL) /*!< SRST (Bitfield-Mask: 0x01) */ +/* ======================================================= I2C_CLKHI ======================================================= */ +#define USB_I2C_CLKHI_CDHI_Pos (0UL) /*!< CDHI (Bit 0) */ +#define USB_I2C_CLKHI_CDHI_Msk (0xffUL) /*!< CDHI (Bitfield-Mask: 0xff) */ +/* ======================================================= I2C_CLKLO ======================================================= */ +#define USB_I2C_CLKLO_CDLO_Pos (0UL) /*!< CDLO (Bit 0) */ +#define USB_I2C_CLKLO_CDLO_Msk (0xffUL) /*!< CDLO (Bitfield-Mask: 0xff) */ +/* ====================================================== USBCLKCTRL ======================================================= */ +#define USB_USBCLKCTRL_DEV_CLK_EN_Pos (1UL) /*!< DEV_CLK_EN (Bit 1) */ +#define USB_USBCLKCTRL_DEV_CLK_EN_Msk (0x2UL) /*!< DEV_CLK_EN (Bitfield-Mask: 0x01) */ +#define USB_USBCLKCTRL_PORTSEL_CLK_EN_Pos (3UL) /*!< PORTSEL_CLK_EN (Bit 3) */ +#define USB_USBCLKCTRL_PORTSEL_CLK_EN_Msk (0x8UL) /*!< PORTSEL_CLK_EN (Bitfield-Mask: 0x01) */ +#define USB_USBCLKCTRL_AHB_CLK_EN_Pos (4UL) /*!< AHB_CLK_EN (Bit 4) */ +#define USB_USBCLKCTRL_AHB_CLK_EN_Msk (0x10UL) /*!< AHB_CLK_EN (Bitfield-Mask: 0x01) */ +/* ====================================================== OTGCLKCTRL ======================================================= */ +#define USB_OTGCLKCTRL_HOST_CLK_EN_Pos (0UL) /*!< HOST_CLK_EN (Bit 0) */ +#define USB_OTGCLKCTRL_HOST_CLK_EN_Msk (0x1UL) /*!< HOST_CLK_EN (Bitfield-Mask: 0x01) */ +#define USB_OTGCLKCTRL_DEV_CLK_EN_Pos (1UL) /*!< DEV_CLK_EN (Bit 1) */ +#define USB_OTGCLKCTRL_DEV_CLK_EN_Msk (0x2UL) /*!< DEV_CLK_EN (Bitfield-Mask: 0x01) */ +#define USB_OTGCLKCTRL_I2C_CLK_EN_Pos (2UL) /*!< I2C_CLK_EN (Bit 2) */ +#define USB_OTGCLKCTRL_I2C_CLK_EN_Msk (0x4UL) /*!< I2C_CLK_EN (Bitfield-Mask: 0x01) */ +#define USB_OTGCLKCTRL_OTG_CLK_EN_Pos (3UL) /*!< OTG_CLK_EN (Bit 3) */ +#define USB_OTGCLKCTRL_OTG_CLK_EN_Msk (0x8UL) /*!< OTG_CLK_EN (Bitfield-Mask: 0x01) */ +#define USB_OTGCLKCTRL_AHB_CLK_EN_Pos (4UL) /*!< AHB_CLK_EN (Bit 4) */ +#define USB_OTGCLKCTRL_AHB_CLK_EN_Msk (0x10UL) /*!< AHB_CLK_EN (Bitfield-Mask: 0x01) */ +/* ======================================================= USBCLKST ======================================================== */ +#define USB_USBCLKST_DEV_CLK_ON_Pos (1UL) /*!< DEV_CLK_ON (Bit 1) */ +#define USB_USBCLKST_DEV_CLK_ON_Msk (0x2UL) /*!< DEV_CLK_ON (Bitfield-Mask: 0x01) */ +#define USB_USBCLKST_PORTSEL_CLK_ON_Pos (3UL) /*!< PORTSEL_CLK_ON (Bit 3) */ +#define USB_USBCLKST_PORTSEL_CLK_ON_Msk (0x8UL) /*!< PORTSEL_CLK_ON (Bitfield-Mask: 0x01) */ +#define USB_USBCLKST_AHB_CLK_ON_Pos (4UL) /*!< AHB_CLK_ON (Bit 4) */ +#define USB_USBCLKST_AHB_CLK_ON_Msk (0x10UL) /*!< AHB_CLK_ON (Bitfield-Mask: 0x01) */ +/* ======================================================= OTGCLKST ======================================================== */ +#define USB_OTGCLKST_HOST_CLK_ON_Pos (0UL) /*!< HOST_CLK_ON (Bit 0) */ +#define USB_OTGCLKST_HOST_CLK_ON_Msk (0x1UL) /*!< HOST_CLK_ON (Bitfield-Mask: 0x01) */ +#define USB_OTGCLKST_DEV_CLK_ON_Pos (1UL) /*!< DEV_CLK_ON (Bit 1) */ +#define USB_OTGCLKST_DEV_CLK_ON_Msk (0x2UL) /*!< DEV_CLK_ON (Bitfield-Mask: 0x01) */ +#define USB_OTGCLKST_I2C_CLK_ON_Pos (2UL) /*!< I2C_CLK_ON (Bit 2) */ +#define USB_OTGCLKST_I2C_CLK_ON_Msk (0x4UL) /*!< I2C_CLK_ON (Bitfield-Mask: 0x01) */ +#define USB_OTGCLKST_OTG_CLK_ON_Pos (3UL) /*!< OTG_CLK_ON (Bit 3) */ +#define USB_OTGCLKST_OTG_CLK_ON_Msk (0x8UL) /*!< OTG_CLK_ON (Bitfield-Mask: 0x01) */ +#define USB_OTGCLKST_AHB_CLK_ON_Pos (4UL) /*!< AHB_CLK_ON (Bit 4) */ +#define USB_OTGCLKST_AHB_CLK_ON_Msk (0x10UL) /*!< AHB_CLK_ON (Bitfield-Mask: 0x01) */ + + +/* =========================================================================================================================== */ +/* ================ LPC_GPIO ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= DIR0 ========================================================== */ +#define GPIO_DIR0_PINDIR0_Pos (0UL) /*!< PINDIR0 (Bit 0) */ +#define GPIO_DIR0_PINDIR0_Msk (0x1UL) /*!< PINDIR0 (Bitfield-Mask: 0x01) */ +#define GPIO_DIR0_PINDIR1_Pos (1UL) /*!< PINDIR1 (Bit 1) */ +#define GPIO_DIR0_PINDIR1_Msk (0x2UL) /*!< PINDIR1 (Bitfield-Mask: 0x01) */ +#define GPIO_DIR0_PINDIR2_Pos (2UL) /*!< PINDIR2 (Bit 2) */ +#define GPIO_DIR0_PINDIR2_Msk (0x4UL) /*!< PINDIR2 (Bitfield-Mask: 0x01) */ +#define GPIO_DIR0_PINDIR3_Pos (3UL) /*!< PINDIR3 (Bit 3) */ +#define GPIO_DIR0_PINDIR3_Msk (0x8UL) /*!< PINDIR3 (Bitfield-Mask: 0x01) */ +#define GPIO_DIR0_PINDIR4_Pos (4UL) /*!< PINDIR4 (Bit 4) */ +#define GPIO_DIR0_PINDIR4_Msk (0x10UL) /*!< PINDIR4 (Bitfield-Mask: 0x01) */ +#define GPIO_DIR0_PINDIR5_Pos (5UL) /*!< PINDIR5 (Bit 5) */ +#define GPIO_DIR0_PINDIR5_Msk (0x20UL) /*!< PINDIR5 (Bitfield-Mask: 0x01) */ +#define GPIO_DIR0_PINDIR6_Pos (6UL) /*!< PINDIR6 (Bit 6) */ +#define GPIO_DIR0_PINDIR6_Msk (0x40UL) /*!< PINDIR6 (Bitfield-Mask: 0x01) */ +#define GPIO_DIR0_PINDIR7_Pos (7UL) /*!< PINDIR7 (Bit 7) */ +#define GPIO_DIR0_PINDIR7_Msk (0x80UL) /*!< PINDIR7 (Bitfield-Mask: 0x01) */ +#define GPIO_DIR0_PINDIR8_Pos (8UL) /*!< PINDIR8 (Bit 8) */ +#define GPIO_DIR0_PINDIR8_Msk (0x100UL) /*!< PINDIR8 (Bitfield-Mask: 0x01) */ +#define GPIO_DIR0_PINDIR9_Pos (9UL) /*!< PINDIR9 (Bit 9) */ +#define GPIO_DIR0_PINDIR9_Msk (0x200UL) /*!< PINDIR9 (Bitfield-Mask: 0x01) */ +#define GPIO_DIR0_PINDIR10_Pos (10UL) /*!< PINDIR10 (Bit 10) */ +#define GPIO_DIR0_PINDIR10_Msk (0x400UL) /*!< PINDIR10 (Bitfield-Mask: 0x01) */ +#define GPIO_DIR0_PINDIR11_Pos (11UL) /*!< PINDIR11 (Bit 11) */ +#define GPIO_DIR0_PINDIR11_Msk (0x800UL) /*!< PINDIR11 (Bitfield-Mask: 0x01) */ +#define GPIO_DIR0_PINDIR12_Pos (12UL) /*!< PINDIR12 (Bit 12) */ +#define GPIO_DIR0_PINDIR12_Msk (0x1000UL) /*!< PINDIR12 (Bitfield-Mask: 0x01) */ +#define GPIO_DIR0_PINDIR13_Pos (13UL) /*!< PINDIR13 (Bit 13) */ +#define GPIO_DIR0_PINDIR13_Msk (0x2000UL) /*!< PINDIR13 (Bitfield-Mask: 0x01) */ +#define GPIO_DIR0_PINDIR14_Pos (14UL) /*!< PINDIR14 (Bit 14) */ +#define GPIO_DIR0_PINDIR14_Msk (0x4000UL) /*!< PINDIR14 (Bitfield-Mask: 0x01) */ +#define GPIO_DIR0_PINDIR15_Pos (15UL) /*!< PINDIR15 (Bit 15) */ +#define GPIO_DIR0_PINDIR15_Msk (0x8000UL) /*!< PINDIR15 (Bitfield-Mask: 0x01) */ +#define GPIO_DIR0_PINDIR16_Pos (16UL) /*!< PINDIR16 (Bit 16) */ +#define GPIO_DIR0_PINDIR16_Msk (0x10000UL) /*!< PINDIR16 (Bitfield-Mask: 0x01) */ +#define GPIO_DIR0_PINDIR17_Pos (17UL) /*!< PINDIR17 (Bit 17) */ +#define GPIO_DIR0_PINDIR17_Msk (0x20000UL) /*!< PINDIR17 (Bitfield-Mask: 0x01) */ +#define GPIO_DIR0_PINDIR18_Pos (18UL) /*!< PINDIR18 (Bit 18) */ +#define GPIO_DIR0_PINDIR18_Msk (0x40000UL) /*!< PINDIR18 (Bitfield-Mask: 0x01) */ +#define GPIO_DIR0_PINDIR19_Pos (19UL) /*!< PINDIR19 (Bit 19) */ +#define GPIO_DIR0_PINDIR19_Msk (0x80000UL) /*!< PINDIR19 (Bitfield-Mask: 0x01) */ +#define GPIO_DIR0_PINDIR20_Pos (20UL) /*!< PINDIR20 (Bit 20) */ +#define GPIO_DIR0_PINDIR20_Msk (0x100000UL) /*!< PINDIR20 (Bitfield-Mask: 0x01) */ +#define GPIO_DIR0_PINDIR21_Pos (21UL) /*!< PINDIR21 (Bit 21) */ +#define GPIO_DIR0_PINDIR21_Msk (0x200000UL) /*!< PINDIR21 (Bitfield-Mask: 0x01) */ +#define GPIO_DIR0_PINDIR22_Pos (22UL) /*!< PINDIR22 (Bit 22) */ +#define GPIO_DIR0_PINDIR22_Msk (0x400000UL) /*!< PINDIR22 (Bitfield-Mask: 0x01) */ +#define GPIO_DIR0_PINDIR23_Pos (23UL) /*!< PINDIR23 (Bit 23) */ +#define GPIO_DIR0_PINDIR23_Msk (0x800000UL) /*!< PINDIR23 (Bitfield-Mask: 0x01) */ +#define GPIO_DIR0_PINDIR24_Pos (24UL) /*!< PINDIR24 (Bit 24) */ +#define GPIO_DIR0_PINDIR24_Msk (0x1000000UL) /*!< PINDIR24 (Bitfield-Mask: 0x01) */ +#define GPIO_DIR0_PINDIR25_Pos (25UL) /*!< PINDIR25 (Bit 25) */ +#define GPIO_DIR0_PINDIR25_Msk (0x2000000UL) /*!< PINDIR25 (Bitfield-Mask: 0x01) */ +#define GPIO_DIR0_PINDIR26_Pos (26UL) /*!< PINDIR26 (Bit 26) */ +#define GPIO_DIR0_PINDIR26_Msk (0x4000000UL) /*!< PINDIR26 (Bitfield-Mask: 0x01) */ +#define GPIO_DIR0_PINDIR27_Pos (27UL) /*!< PINDIR27 (Bit 27) */ +#define GPIO_DIR0_PINDIR27_Msk (0x8000000UL) /*!< PINDIR27 (Bitfield-Mask: 0x01) */ +#define GPIO_DIR0_PINDIR28_Pos (28UL) /*!< PINDIR28 (Bit 28) */ +#define GPIO_DIR0_PINDIR28_Msk (0x10000000UL) /*!< PINDIR28 (Bitfield-Mask: 0x01) */ +#define GPIO_DIR0_PINDIR29_Pos (29UL) /*!< PINDIR29 (Bit 29) */ +#define GPIO_DIR0_PINDIR29_Msk (0x20000000UL) /*!< PINDIR29 (Bitfield-Mask: 0x01) */ +#define GPIO_DIR0_PINDIR30_Pos (30UL) /*!< PINDIR30 (Bit 30) */ +#define GPIO_DIR0_PINDIR30_Msk (0x40000000UL) /*!< PINDIR30 (Bitfield-Mask: 0x01) */ +#define GPIO_DIR0_PINDIR31_Pos (31UL) /*!< PINDIR31 (Bit 31) */ +#define GPIO_DIR0_PINDIR31_Msk (0x80000000UL) /*!< PINDIR31 (Bitfield-Mask: 0x01) */ +/* ========================================================= DIR1 ========================================================== */ +#define GPIO_DIR1_PINDIR0_Pos (0UL) /*!< PINDIR0 (Bit 0) */ +#define GPIO_DIR1_PINDIR0_Msk (0x1UL) /*!< PINDIR0 (Bitfield-Mask: 0x01) */ +#define GPIO_DIR1_PINDIR1_Pos (1UL) /*!< PINDIR1 (Bit 1) */ +#define GPIO_DIR1_PINDIR1_Msk (0x2UL) /*!< PINDIR1 (Bitfield-Mask: 0x01) */ +#define GPIO_DIR1_PINDIR2_Pos (2UL) /*!< PINDIR2 (Bit 2) */ +#define GPIO_DIR1_PINDIR2_Msk (0x4UL) /*!< PINDIR2 (Bitfield-Mask: 0x01) */ +#define GPIO_DIR1_PINDIR3_Pos (3UL) /*!< PINDIR3 (Bit 3) */ +#define GPIO_DIR1_PINDIR3_Msk (0x8UL) /*!< PINDIR3 (Bitfield-Mask: 0x01) */ +#define GPIO_DIR1_PINDIR4_Pos (4UL) /*!< PINDIR4 (Bit 4) */ +#define GPIO_DIR1_PINDIR4_Msk (0x10UL) /*!< PINDIR4 (Bitfield-Mask: 0x01) */ +#define GPIO_DIR1_PINDIR5_Pos (5UL) /*!< PINDIR5 (Bit 5) */ +#define GPIO_DIR1_PINDIR5_Msk (0x20UL) /*!< PINDIR5 (Bitfield-Mask: 0x01) */ +#define GPIO_DIR1_PINDIR6_Pos (6UL) /*!< PINDIR6 (Bit 6) */ +#define GPIO_DIR1_PINDIR6_Msk (0x40UL) /*!< PINDIR6 (Bitfield-Mask: 0x01) */ +#define GPIO_DIR1_PINDIR7_Pos (7UL) /*!< PINDIR7 (Bit 7) */ +#define GPIO_DIR1_PINDIR7_Msk (0x80UL) /*!< PINDIR7 (Bitfield-Mask: 0x01) */ +#define GPIO_DIR1_PINDIR8_Pos (8UL) /*!< PINDIR8 (Bit 8) */ +#define GPIO_DIR1_PINDIR8_Msk (0x100UL) /*!< PINDIR8 (Bitfield-Mask: 0x01) */ +#define GPIO_DIR1_PINDIR9_Pos (9UL) /*!< PINDIR9 (Bit 9) */ +#define GPIO_DIR1_PINDIR9_Msk (0x200UL) /*!< PINDIR9 (Bitfield-Mask: 0x01) */ +#define GPIO_DIR1_PINDIR10_Pos (10UL) /*!< PINDIR10 (Bit 10) */ +#define GPIO_DIR1_PINDIR10_Msk (0x400UL) /*!< PINDIR10 (Bitfield-Mask: 0x01) */ +#define GPIO_DIR1_PINDIR11_Pos (11UL) /*!< PINDIR11 (Bit 11) */ +#define GPIO_DIR1_PINDIR11_Msk (0x800UL) /*!< PINDIR11 (Bitfield-Mask: 0x01) */ +#define GPIO_DIR1_PINDIR12_Pos (12UL) /*!< PINDIR12 (Bit 12) */ +#define GPIO_DIR1_PINDIR12_Msk (0x1000UL) /*!< PINDIR12 (Bitfield-Mask: 0x01) */ +#define GPIO_DIR1_PINDIR13_Pos (13UL) /*!< PINDIR13 (Bit 13) */ +#define GPIO_DIR1_PINDIR13_Msk (0x2000UL) /*!< PINDIR13 (Bitfield-Mask: 0x01) */ +#define GPIO_DIR1_PINDIR14_Pos (14UL) /*!< PINDIR14 (Bit 14) */ +#define GPIO_DIR1_PINDIR14_Msk (0x4000UL) /*!< PINDIR14 (Bitfield-Mask: 0x01) */ +#define GPIO_DIR1_PINDIR15_Pos (15UL) /*!< PINDIR15 (Bit 15) */ +#define GPIO_DIR1_PINDIR15_Msk (0x8000UL) /*!< PINDIR15 (Bitfield-Mask: 0x01) */ +#define GPIO_DIR1_PINDIR16_Pos (16UL) /*!< PINDIR16 (Bit 16) */ +#define GPIO_DIR1_PINDIR16_Msk (0x10000UL) /*!< PINDIR16 (Bitfield-Mask: 0x01) */ +#define GPIO_DIR1_PINDIR17_Pos (17UL) /*!< PINDIR17 (Bit 17) */ +#define GPIO_DIR1_PINDIR17_Msk (0x20000UL) /*!< PINDIR17 (Bitfield-Mask: 0x01) */ +#define GPIO_DIR1_PINDIR18_Pos (18UL) /*!< PINDIR18 (Bit 18) */ +#define GPIO_DIR1_PINDIR18_Msk (0x40000UL) /*!< PINDIR18 (Bitfield-Mask: 0x01) */ +#define GPIO_DIR1_PINDIR19_Pos (19UL) /*!< PINDIR19 (Bit 19) */ +#define GPIO_DIR1_PINDIR19_Msk (0x80000UL) /*!< PINDIR19 (Bitfield-Mask: 0x01) */ +#define GPIO_DIR1_PINDIR20_Pos (20UL) /*!< PINDIR20 (Bit 20) */ +#define GPIO_DIR1_PINDIR20_Msk (0x100000UL) /*!< PINDIR20 (Bitfield-Mask: 0x01) */ +#define GPIO_DIR1_PINDIR21_Pos (21UL) /*!< PINDIR21 (Bit 21) */ +#define GPIO_DIR1_PINDIR21_Msk (0x200000UL) /*!< PINDIR21 (Bitfield-Mask: 0x01) */ +#define GPIO_DIR1_PINDIR22_Pos (22UL) /*!< PINDIR22 (Bit 22) */ +#define GPIO_DIR1_PINDIR22_Msk (0x400000UL) /*!< PINDIR22 (Bitfield-Mask: 0x01) */ +#define GPIO_DIR1_PINDIR23_Pos (23UL) /*!< PINDIR23 (Bit 23) */ +#define GPIO_DIR1_PINDIR23_Msk (0x800000UL) /*!< PINDIR23 (Bitfield-Mask: 0x01) */ +#define GPIO_DIR1_PINDIR24_Pos (24UL) /*!< PINDIR24 (Bit 24) */ +#define GPIO_DIR1_PINDIR24_Msk (0x1000000UL) /*!< PINDIR24 (Bitfield-Mask: 0x01) */ +#define GPIO_DIR1_PINDIR25_Pos (25UL) /*!< PINDIR25 (Bit 25) */ +#define GPIO_DIR1_PINDIR25_Msk (0x2000000UL) /*!< PINDIR25 (Bitfield-Mask: 0x01) */ +#define GPIO_DIR1_PINDIR26_Pos (26UL) /*!< PINDIR26 (Bit 26) */ +#define GPIO_DIR1_PINDIR26_Msk (0x4000000UL) /*!< PINDIR26 (Bitfield-Mask: 0x01) */ +#define GPIO_DIR1_PINDIR27_Pos (27UL) /*!< PINDIR27 (Bit 27) */ +#define GPIO_DIR1_PINDIR27_Msk (0x8000000UL) /*!< PINDIR27 (Bitfield-Mask: 0x01) */ +#define GPIO_DIR1_PINDIR28_Pos (28UL) /*!< PINDIR28 (Bit 28) */ +#define GPIO_DIR1_PINDIR28_Msk (0x10000000UL) /*!< PINDIR28 (Bitfield-Mask: 0x01) */ +#define GPIO_DIR1_PINDIR29_Pos (29UL) /*!< PINDIR29 (Bit 29) */ +#define GPIO_DIR1_PINDIR29_Msk (0x20000000UL) /*!< PINDIR29 (Bitfield-Mask: 0x01) */ +#define GPIO_DIR1_PINDIR30_Pos (30UL) /*!< PINDIR30 (Bit 30) */ +#define GPIO_DIR1_PINDIR30_Msk (0x40000000UL) /*!< PINDIR30 (Bitfield-Mask: 0x01) */ +#define GPIO_DIR1_PINDIR31_Pos (31UL) /*!< PINDIR31 (Bit 31) */ +#define GPIO_DIR1_PINDIR31_Msk (0x80000000UL) /*!< PINDIR31 (Bitfield-Mask: 0x01) */ +/* ========================================================= DIR2 ========================================================== */ +#define GPIO_DIR2_PINDIR0_Pos (0UL) /*!< PINDIR0 (Bit 0) */ +#define GPIO_DIR2_PINDIR0_Msk (0x1UL) /*!< PINDIR0 (Bitfield-Mask: 0x01) */ +#define GPIO_DIR2_PINDIR1_Pos (1UL) /*!< PINDIR1 (Bit 1) */ +#define GPIO_DIR2_PINDIR1_Msk (0x2UL) /*!< PINDIR1 (Bitfield-Mask: 0x01) */ +#define GPIO_DIR2_PINDIR2_Pos (2UL) /*!< PINDIR2 (Bit 2) */ +#define GPIO_DIR2_PINDIR2_Msk (0x4UL) /*!< PINDIR2 (Bitfield-Mask: 0x01) */ +#define GPIO_DIR2_PINDIR3_Pos (3UL) /*!< PINDIR3 (Bit 3) */ +#define GPIO_DIR2_PINDIR3_Msk (0x8UL) /*!< PINDIR3 (Bitfield-Mask: 0x01) */ +#define GPIO_DIR2_PINDIR4_Pos (4UL) /*!< PINDIR4 (Bit 4) */ +#define GPIO_DIR2_PINDIR4_Msk (0x10UL) /*!< PINDIR4 (Bitfield-Mask: 0x01) */ +#define GPIO_DIR2_PINDIR5_Pos (5UL) /*!< PINDIR5 (Bit 5) */ +#define GPIO_DIR2_PINDIR5_Msk (0x20UL) /*!< PINDIR5 (Bitfield-Mask: 0x01) */ +#define GPIO_DIR2_PINDIR6_Pos (6UL) /*!< PINDIR6 (Bit 6) */ +#define GPIO_DIR2_PINDIR6_Msk (0x40UL) /*!< PINDIR6 (Bitfield-Mask: 0x01) */ +#define GPIO_DIR2_PINDIR7_Pos (7UL) /*!< PINDIR7 (Bit 7) */ +#define GPIO_DIR2_PINDIR7_Msk (0x80UL) /*!< PINDIR7 (Bitfield-Mask: 0x01) */ +#define GPIO_DIR2_PINDIR8_Pos (8UL) /*!< PINDIR8 (Bit 8) */ +#define GPIO_DIR2_PINDIR8_Msk (0x100UL) /*!< PINDIR8 (Bitfield-Mask: 0x01) */ +#define GPIO_DIR2_PINDIR9_Pos (9UL) /*!< PINDIR9 (Bit 9) */ +#define GPIO_DIR2_PINDIR9_Msk (0x200UL) /*!< PINDIR9 (Bitfield-Mask: 0x01) */ +#define GPIO_DIR2_PINDIR10_Pos (10UL) /*!< PINDIR10 (Bit 10) */ +#define GPIO_DIR2_PINDIR10_Msk (0x400UL) /*!< PINDIR10 (Bitfield-Mask: 0x01) */ +#define GPIO_DIR2_PINDIR11_Pos (11UL) /*!< PINDIR11 (Bit 11) */ +#define GPIO_DIR2_PINDIR11_Msk (0x800UL) /*!< PINDIR11 (Bitfield-Mask: 0x01) */ +#define GPIO_DIR2_PINDIR12_Pos (12UL) /*!< PINDIR12 (Bit 12) */ +#define GPIO_DIR2_PINDIR12_Msk (0x1000UL) /*!< PINDIR12 (Bitfield-Mask: 0x01) */ +#define GPIO_DIR2_PINDIR13_Pos (13UL) /*!< PINDIR13 (Bit 13) */ +#define GPIO_DIR2_PINDIR13_Msk (0x2000UL) /*!< PINDIR13 (Bitfield-Mask: 0x01) */ +#define GPIO_DIR2_PINDIR14_Pos (14UL) /*!< PINDIR14 (Bit 14) */ +#define GPIO_DIR2_PINDIR14_Msk (0x4000UL) /*!< PINDIR14 (Bitfield-Mask: 0x01) */ +#define GPIO_DIR2_PINDIR15_Pos (15UL) /*!< PINDIR15 (Bit 15) */ +#define GPIO_DIR2_PINDIR15_Msk (0x8000UL) /*!< PINDIR15 (Bitfield-Mask: 0x01) */ +#define GPIO_DIR2_PINDIR16_Pos (16UL) /*!< PINDIR16 (Bit 16) */ +#define GPIO_DIR2_PINDIR16_Msk (0x10000UL) /*!< PINDIR16 (Bitfield-Mask: 0x01) */ +#define GPIO_DIR2_PINDIR17_Pos (17UL) /*!< PINDIR17 (Bit 17) */ +#define GPIO_DIR2_PINDIR17_Msk (0x20000UL) /*!< PINDIR17 (Bitfield-Mask: 0x01) */ +#define GPIO_DIR2_PINDIR18_Pos (18UL) /*!< PINDIR18 (Bit 18) */ +#define GPIO_DIR2_PINDIR18_Msk (0x40000UL) /*!< PINDIR18 (Bitfield-Mask: 0x01) */ +#define GPIO_DIR2_PINDIR19_Pos (19UL) /*!< PINDIR19 (Bit 19) */ +#define GPIO_DIR2_PINDIR19_Msk (0x80000UL) /*!< PINDIR19 (Bitfield-Mask: 0x01) */ +#define GPIO_DIR2_PINDIR20_Pos (20UL) /*!< PINDIR20 (Bit 20) */ +#define GPIO_DIR2_PINDIR20_Msk (0x100000UL) /*!< PINDIR20 (Bitfield-Mask: 0x01) */ +#define GPIO_DIR2_PINDIR21_Pos (21UL) /*!< PINDIR21 (Bit 21) */ +#define GPIO_DIR2_PINDIR21_Msk (0x200000UL) /*!< PINDIR21 (Bitfield-Mask: 0x01) */ +#define GPIO_DIR2_PINDIR22_Pos (22UL) /*!< PINDIR22 (Bit 22) */ +#define GPIO_DIR2_PINDIR22_Msk (0x400000UL) /*!< PINDIR22 (Bitfield-Mask: 0x01) */ +#define GPIO_DIR2_PINDIR23_Pos (23UL) /*!< PINDIR23 (Bit 23) */ +#define GPIO_DIR2_PINDIR23_Msk (0x800000UL) /*!< PINDIR23 (Bitfield-Mask: 0x01) */ +#define GPIO_DIR2_PINDIR24_Pos (24UL) /*!< PINDIR24 (Bit 24) */ +#define GPIO_DIR2_PINDIR24_Msk (0x1000000UL) /*!< PINDIR24 (Bitfield-Mask: 0x01) */ +#define GPIO_DIR2_PINDIR25_Pos (25UL) /*!< PINDIR25 (Bit 25) */ +#define GPIO_DIR2_PINDIR25_Msk (0x2000000UL) /*!< PINDIR25 (Bitfield-Mask: 0x01) */ +#define GPIO_DIR2_PINDIR26_Pos (26UL) /*!< PINDIR26 (Bit 26) */ +#define GPIO_DIR2_PINDIR26_Msk (0x4000000UL) /*!< PINDIR26 (Bitfield-Mask: 0x01) */ +#define GPIO_DIR2_PINDIR27_Pos (27UL) /*!< PINDIR27 (Bit 27) */ +#define GPIO_DIR2_PINDIR27_Msk (0x8000000UL) /*!< PINDIR27 (Bitfield-Mask: 0x01) */ +#define GPIO_DIR2_PINDIR28_Pos (28UL) /*!< PINDIR28 (Bit 28) */ +#define GPIO_DIR2_PINDIR28_Msk (0x10000000UL) /*!< PINDIR28 (Bitfield-Mask: 0x01) */ +#define GPIO_DIR2_PINDIR29_Pos (29UL) /*!< PINDIR29 (Bit 29) */ +#define GPIO_DIR2_PINDIR29_Msk (0x20000000UL) /*!< PINDIR29 (Bitfield-Mask: 0x01) */ +#define GPIO_DIR2_PINDIR30_Pos (30UL) /*!< PINDIR30 (Bit 30) */ +#define GPIO_DIR2_PINDIR30_Msk (0x40000000UL) /*!< PINDIR30 (Bitfield-Mask: 0x01) */ +#define GPIO_DIR2_PINDIR31_Pos (31UL) /*!< PINDIR31 (Bit 31) */ +#define GPIO_DIR2_PINDIR31_Msk (0x80000000UL) /*!< PINDIR31 (Bitfield-Mask: 0x01) */ +/* ========================================================= DIR3 ========================================================== */ +#define GPIO_DIR3_PINDIR0_Pos (0UL) /*!< PINDIR0 (Bit 0) */ +#define GPIO_DIR3_PINDIR0_Msk (0x1UL) /*!< PINDIR0 (Bitfield-Mask: 0x01) */ +#define GPIO_DIR3_PINDIR1_Pos (1UL) /*!< PINDIR1 (Bit 1) */ +#define GPIO_DIR3_PINDIR1_Msk (0x2UL) /*!< PINDIR1 (Bitfield-Mask: 0x01) */ +#define GPIO_DIR3_PINDIR2_Pos (2UL) /*!< PINDIR2 (Bit 2) */ +#define GPIO_DIR3_PINDIR2_Msk (0x4UL) /*!< PINDIR2 (Bitfield-Mask: 0x01) */ +#define GPIO_DIR3_PINDIR3_Pos (3UL) /*!< PINDIR3 (Bit 3) */ +#define GPIO_DIR3_PINDIR3_Msk (0x8UL) /*!< PINDIR3 (Bitfield-Mask: 0x01) */ +#define GPIO_DIR3_PINDIR4_Pos (4UL) /*!< PINDIR4 (Bit 4) */ +#define GPIO_DIR3_PINDIR4_Msk (0x10UL) /*!< PINDIR4 (Bitfield-Mask: 0x01) */ +#define GPIO_DIR3_PINDIR5_Pos (5UL) /*!< PINDIR5 (Bit 5) */ +#define GPIO_DIR3_PINDIR5_Msk (0x20UL) /*!< PINDIR5 (Bitfield-Mask: 0x01) */ +#define GPIO_DIR3_PINDIR6_Pos (6UL) /*!< PINDIR6 (Bit 6) */ +#define GPIO_DIR3_PINDIR6_Msk (0x40UL) /*!< PINDIR6 (Bitfield-Mask: 0x01) */ +#define GPIO_DIR3_PINDIR7_Pos (7UL) /*!< PINDIR7 (Bit 7) */ +#define GPIO_DIR3_PINDIR7_Msk (0x80UL) /*!< PINDIR7 (Bitfield-Mask: 0x01) */ +#define GPIO_DIR3_PINDIR8_Pos (8UL) /*!< PINDIR8 (Bit 8) */ +#define GPIO_DIR3_PINDIR8_Msk (0x100UL) /*!< PINDIR8 (Bitfield-Mask: 0x01) */ +#define GPIO_DIR3_PINDIR9_Pos (9UL) /*!< PINDIR9 (Bit 9) */ +#define GPIO_DIR3_PINDIR9_Msk (0x200UL) /*!< PINDIR9 (Bitfield-Mask: 0x01) */ +#define GPIO_DIR3_PINDIR10_Pos (10UL) /*!< PINDIR10 (Bit 10) */ +#define GPIO_DIR3_PINDIR10_Msk (0x400UL) /*!< PINDIR10 (Bitfield-Mask: 0x01) */ +#define GPIO_DIR3_PINDIR11_Pos (11UL) /*!< PINDIR11 (Bit 11) */ +#define GPIO_DIR3_PINDIR11_Msk (0x800UL) /*!< PINDIR11 (Bitfield-Mask: 0x01) */ +#define GPIO_DIR3_PINDIR12_Pos (12UL) /*!< PINDIR12 (Bit 12) */ +#define GPIO_DIR3_PINDIR12_Msk (0x1000UL) /*!< PINDIR12 (Bitfield-Mask: 0x01) */ +#define GPIO_DIR3_PINDIR13_Pos (13UL) /*!< PINDIR13 (Bit 13) */ +#define GPIO_DIR3_PINDIR13_Msk (0x2000UL) /*!< PINDIR13 (Bitfield-Mask: 0x01) */ +#define GPIO_DIR3_PINDIR14_Pos (14UL) /*!< PINDIR14 (Bit 14) */ +#define GPIO_DIR3_PINDIR14_Msk (0x4000UL) /*!< PINDIR14 (Bitfield-Mask: 0x01) */ +#define GPIO_DIR3_PINDIR15_Pos (15UL) /*!< PINDIR15 (Bit 15) */ +#define GPIO_DIR3_PINDIR15_Msk (0x8000UL) /*!< PINDIR15 (Bitfield-Mask: 0x01) */ +#define GPIO_DIR3_PINDIR16_Pos (16UL) /*!< PINDIR16 (Bit 16) */ +#define GPIO_DIR3_PINDIR16_Msk (0x10000UL) /*!< PINDIR16 (Bitfield-Mask: 0x01) */ +#define GPIO_DIR3_PINDIR17_Pos (17UL) /*!< PINDIR17 (Bit 17) */ +#define GPIO_DIR3_PINDIR17_Msk (0x20000UL) /*!< PINDIR17 (Bitfield-Mask: 0x01) */ +#define GPIO_DIR3_PINDIR18_Pos (18UL) /*!< PINDIR18 (Bit 18) */ +#define GPIO_DIR3_PINDIR18_Msk (0x40000UL) /*!< PINDIR18 (Bitfield-Mask: 0x01) */ +#define GPIO_DIR3_PINDIR19_Pos (19UL) /*!< PINDIR19 (Bit 19) */ +#define GPIO_DIR3_PINDIR19_Msk (0x80000UL) /*!< PINDIR19 (Bitfield-Mask: 0x01) */ +#define GPIO_DIR3_PINDIR20_Pos (20UL) /*!< PINDIR20 (Bit 20) */ +#define GPIO_DIR3_PINDIR20_Msk (0x100000UL) /*!< PINDIR20 (Bitfield-Mask: 0x01) */ +#define GPIO_DIR3_PINDIR21_Pos (21UL) /*!< PINDIR21 (Bit 21) */ +#define GPIO_DIR3_PINDIR21_Msk (0x200000UL) /*!< PINDIR21 (Bitfield-Mask: 0x01) */ +#define GPIO_DIR3_PINDIR22_Pos (22UL) /*!< PINDIR22 (Bit 22) */ +#define GPIO_DIR3_PINDIR22_Msk (0x400000UL) /*!< PINDIR22 (Bitfield-Mask: 0x01) */ +#define GPIO_DIR3_PINDIR23_Pos (23UL) /*!< PINDIR23 (Bit 23) */ +#define GPIO_DIR3_PINDIR23_Msk (0x800000UL) /*!< PINDIR23 (Bitfield-Mask: 0x01) */ +#define GPIO_DIR3_PINDIR24_Pos (24UL) /*!< PINDIR24 (Bit 24) */ +#define GPIO_DIR3_PINDIR24_Msk (0x1000000UL) /*!< PINDIR24 (Bitfield-Mask: 0x01) */ +#define GPIO_DIR3_PINDIR25_Pos (25UL) /*!< PINDIR25 (Bit 25) */ +#define GPIO_DIR3_PINDIR25_Msk (0x2000000UL) /*!< PINDIR25 (Bitfield-Mask: 0x01) */ +#define GPIO_DIR3_PINDIR26_Pos (26UL) /*!< PINDIR26 (Bit 26) */ +#define GPIO_DIR3_PINDIR26_Msk (0x4000000UL) /*!< PINDIR26 (Bitfield-Mask: 0x01) */ +#define GPIO_DIR3_PINDIR27_Pos (27UL) /*!< PINDIR27 (Bit 27) */ +#define GPIO_DIR3_PINDIR27_Msk (0x8000000UL) /*!< PINDIR27 (Bitfield-Mask: 0x01) */ +#define GPIO_DIR3_PINDIR28_Pos (28UL) /*!< PINDIR28 (Bit 28) */ +#define GPIO_DIR3_PINDIR28_Msk (0x10000000UL) /*!< PINDIR28 (Bitfield-Mask: 0x01) */ +#define GPIO_DIR3_PINDIR29_Pos (29UL) /*!< PINDIR29 (Bit 29) */ +#define GPIO_DIR3_PINDIR29_Msk (0x20000000UL) /*!< PINDIR29 (Bitfield-Mask: 0x01) */ +#define GPIO_DIR3_PINDIR30_Pos (30UL) /*!< PINDIR30 (Bit 30) */ +#define GPIO_DIR3_PINDIR30_Msk (0x40000000UL) /*!< PINDIR30 (Bitfield-Mask: 0x01) */ +#define GPIO_DIR3_PINDIR31_Pos (31UL) /*!< PINDIR31 (Bit 31) */ +#define GPIO_DIR3_PINDIR31_Msk (0x80000000UL) /*!< PINDIR31 (Bitfield-Mask: 0x01) */ +/* ========================================================= DIR4 ========================================================== */ +#define GPIO_DIR4_PINDIR0_Pos (0UL) /*!< PINDIR0 (Bit 0) */ +#define GPIO_DIR4_PINDIR0_Msk (0x1UL) /*!< PINDIR0 (Bitfield-Mask: 0x01) */ +#define GPIO_DIR4_PINDIR1_Pos (1UL) /*!< PINDIR1 (Bit 1) */ +#define GPIO_DIR4_PINDIR1_Msk (0x2UL) /*!< PINDIR1 (Bitfield-Mask: 0x01) */ +#define GPIO_DIR4_PINDIR2_Pos (2UL) /*!< PINDIR2 (Bit 2) */ +#define GPIO_DIR4_PINDIR2_Msk (0x4UL) /*!< PINDIR2 (Bitfield-Mask: 0x01) */ +#define GPIO_DIR4_PINDIR3_Pos (3UL) /*!< PINDIR3 (Bit 3) */ +#define GPIO_DIR4_PINDIR3_Msk (0x8UL) /*!< PINDIR3 (Bitfield-Mask: 0x01) */ +#define GPIO_DIR4_PINDIR4_Pos (4UL) /*!< PINDIR4 (Bit 4) */ +#define GPIO_DIR4_PINDIR4_Msk (0x10UL) /*!< PINDIR4 (Bitfield-Mask: 0x01) */ +#define GPIO_DIR4_PINDIR5_Pos (5UL) /*!< PINDIR5 (Bit 5) */ +#define GPIO_DIR4_PINDIR5_Msk (0x20UL) /*!< PINDIR5 (Bitfield-Mask: 0x01) */ +#define GPIO_DIR4_PINDIR6_Pos (6UL) /*!< PINDIR6 (Bit 6) */ +#define GPIO_DIR4_PINDIR6_Msk (0x40UL) /*!< PINDIR6 (Bitfield-Mask: 0x01) */ +#define GPIO_DIR4_PINDIR7_Pos (7UL) /*!< PINDIR7 (Bit 7) */ +#define GPIO_DIR4_PINDIR7_Msk (0x80UL) /*!< PINDIR7 (Bitfield-Mask: 0x01) */ +#define GPIO_DIR4_PINDIR8_Pos (8UL) /*!< PINDIR8 (Bit 8) */ +#define GPIO_DIR4_PINDIR8_Msk (0x100UL) /*!< PINDIR8 (Bitfield-Mask: 0x01) */ +#define GPIO_DIR4_PINDIR9_Pos (9UL) /*!< PINDIR9 (Bit 9) */ +#define GPIO_DIR4_PINDIR9_Msk (0x200UL) /*!< PINDIR9 (Bitfield-Mask: 0x01) */ +#define GPIO_DIR4_PINDIR10_Pos (10UL) /*!< PINDIR10 (Bit 10) */ +#define GPIO_DIR4_PINDIR10_Msk (0x400UL) /*!< PINDIR10 (Bitfield-Mask: 0x01) */ +#define GPIO_DIR4_PINDIR11_Pos (11UL) /*!< PINDIR11 (Bit 11) */ +#define GPIO_DIR4_PINDIR11_Msk (0x800UL) /*!< PINDIR11 (Bitfield-Mask: 0x01) */ +#define GPIO_DIR4_PINDIR12_Pos (12UL) /*!< PINDIR12 (Bit 12) */ +#define GPIO_DIR4_PINDIR12_Msk (0x1000UL) /*!< PINDIR12 (Bitfield-Mask: 0x01) */ +#define GPIO_DIR4_PINDIR13_Pos (13UL) /*!< PINDIR13 (Bit 13) */ +#define GPIO_DIR4_PINDIR13_Msk (0x2000UL) /*!< PINDIR13 (Bitfield-Mask: 0x01) */ +#define GPIO_DIR4_PINDIR14_Pos (14UL) /*!< PINDIR14 (Bit 14) */ +#define GPIO_DIR4_PINDIR14_Msk (0x4000UL) /*!< PINDIR14 (Bitfield-Mask: 0x01) */ +#define GPIO_DIR4_PINDIR15_Pos (15UL) /*!< PINDIR15 (Bit 15) */ +#define GPIO_DIR4_PINDIR15_Msk (0x8000UL) /*!< PINDIR15 (Bitfield-Mask: 0x01) */ +#define GPIO_DIR4_PINDIR16_Pos (16UL) /*!< PINDIR16 (Bit 16) */ +#define GPIO_DIR4_PINDIR16_Msk (0x10000UL) /*!< PINDIR16 (Bitfield-Mask: 0x01) */ +#define GPIO_DIR4_PINDIR17_Pos (17UL) /*!< PINDIR17 (Bit 17) */ +#define GPIO_DIR4_PINDIR17_Msk (0x20000UL) /*!< PINDIR17 (Bitfield-Mask: 0x01) */ +#define GPIO_DIR4_PINDIR18_Pos (18UL) /*!< PINDIR18 (Bit 18) */ +#define GPIO_DIR4_PINDIR18_Msk (0x40000UL) /*!< PINDIR18 (Bitfield-Mask: 0x01) */ +#define GPIO_DIR4_PINDIR19_Pos (19UL) /*!< PINDIR19 (Bit 19) */ +#define GPIO_DIR4_PINDIR19_Msk (0x80000UL) /*!< PINDIR19 (Bitfield-Mask: 0x01) */ +#define GPIO_DIR4_PINDIR20_Pos (20UL) /*!< PINDIR20 (Bit 20) */ +#define GPIO_DIR4_PINDIR20_Msk (0x100000UL) /*!< PINDIR20 (Bitfield-Mask: 0x01) */ +#define GPIO_DIR4_PINDIR21_Pos (21UL) /*!< PINDIR21 (Bit 21) */ +#define GPIO_DIR4_PINDIR21_Msk (0x200000UL) /*!< PINDIR21 (Bitfield-Mask: 0x01) */ +#define GPIO_DIR4_PINDIR22_Pos (22UL) /*!< PINDIR22 (Bit 22) */ +#define GPIO_DIR4_PINDIR22_Msk (0x400000UL) /*!< PINDIR22 (Bitfield-Mask: 0x01) */ +#define GPIO_DIR4_PINDIR23_Pos (23UL) /*!< PINDIR23 (Bit 23) */ +#define GPIO_DIR4_PINDIR23_Msk (0x800000UL) /*!< PINDIR23 (Bitfield-Mask: 0x01) */ +#define GPIO_DIR4_PINDIR24_Pos (24UL) /*!< PINDIR24 (Bit 24) */ +#define GPIO_DIR4_PINDIR24_Msk (0x1000000UL) /*!< PINDIR24 (Bitfield-Mask: 0x01) */ +#define GPIO_DIR4_PINDIR25_Pos (25UL) /*!< PINDIR25 (Bit 25) */ +#define GPIO_DIR4_PINDIR25_Msk (0x2000000UL) /*!< PINDIR25 (Bitfield-Mask: 0x01) */ +#define GPIO_DIR4_PINDIR26_Pos (26UL) /*!< PINDIR26 (Bit 26) */ +#define GPIO_DIR4_PINDIR26_Msk (0x4000000UL) /*!< PINDIR26 (Bitfield-Mask: 0x01) */ +#define GPIO_DIR4_PINDIR27_Pos (27UL) /*!< PINDIR27 (Bit 27) */ +#define GPIO_DIR4_PINDIR27_Msk (0x8000000UL) /*!< PINDIR27 (Bitfield-Mask: 0x01) */ +#define GPIO_DIR4_PINDIR28_Pos (28UL) /*!< PINDIR28 (Bit 28) */ +#define GPIO_DIR4_PINDIR28_Msk (0x10000000UL) /*!< PINDIR28 (Bitfield-Mask: 0x01) */ +#define GPIO_DIR4_PINDIR29_Pos (29UL) /*!< PINDIR29 (Bit 29) */ +#define GPIO_DIR4_PINDIR29_Msk (0x20000000UL) /*!< PINDIR29 (Bitfield-Mask: 0x01) */ +#define GPIO_DIR4_PINDIR30_Pos (30UL) /*!< PINDIR30 (Bit 30) */ +#define GPIO_DIR4_PINDIR30_Msk (0x40000000UL) /*!< PINDIR30 (Bitfield-Mask: 0x01) */ +#define GPIO_DIR4_PINDIR31_Pos (31UL) /*!< PINDIR31 (Bit 31) */ +#define GPIO_DIR4_PINDIR31_Msk (0x80000000UL) /*!< PINDIR31 (Bitfield-Mask: 0x01) */ +/* ========================================================= MASK0 ========================================================= */ +#define GPIO_MASK0_PINMASK0_Pos (0UL) /*!< PINMASK0 (Bit 0) */ +#define GPIO_MASK0_PINMASK0_Msk (0x1UL) /*!< PINMASK0 (Bitfield-Mask: 0x01) */ +#define GPIO_MASK0_PINMASK1_Pos (1UL) /*!< PINMASK1 (Bit 1) */ +#define GPIO_MASK0_PINMASK1_Msk (0x2UL) /*!< PINMASK1 (Bitfield-Mask: 0x01) */ +#define GPIO_MASK0_PINMASK2_Pos (2UL) /*!< PINMASK2 (Bit 2) */ +#define GPIO_MASK0_PINMASK2_Msk (0x4UL) /*!< PINMASK2 (Bitfield-Mask: 0x01) */ +#define GPIO_MASK0_PINMASK3_Pos (3UL) /*!< PINMASK3 (Bit 3) */ +#define GPIO_MASK0_PINMASK3_Msk (0x8UL) /*!< PINMASK3 (Bitfield-Mask: 0x01) */ +#define GPIO_MASK0_PINMASK4_Pos (4UL) /*!< PINMASK4 (Bit 4) */ +#define GPIO_MASK0_PINMASK4_Msk (0x10UL) /*!< PINMASK4 (Bitfield-Mask: 0x01) */ +#define GPIO_MASK0_PINMASK5_Pos (5UL) /*!< PINMASK5 (Bit 5) */ +#define GPIO_MASK0_PINMASK5_Msk (0x20UL) /*!< PINMASK5 (Bitfield-Mask: 0x01) */ +#define GPIO_MASK0_PINMASK6_Pos (6UL) /*!< PINMASK6 (Bit 6) */ +#define GPIO_MASK0_PINMASK6_Msk (0x40UL) /*!< PINMASK6 (Bitfield-Mask: 0x01) */ +#define GPIO_MASK0_PINMASK7_Pos (7UL) /*!< PINMASK7 (Bit 7) */ +#define GPIO_MASK0_PINMASK7_Msk (0x80UL) /*!< PINMASK7 (Bitfield-Mask: 0x01) */ +#define GPIO_MASK0_PINMASK8_Pos (8UL) /*!< PINMASK8 (Bit 8) */ +#define GPIO_MASK0_PINMASK8_Msk (0x100UL) /*!< PINMASK8 (Bitfield-Mask: 0x01) */ +#define GPIO_MASK0_PINMASK9_Pos (9UL) /*!< PINMASK9 (Bit 9) */ +#define GPIO_MASK0_PINMASK9_Msk (0x200UL) /*!< PINMASK9 (Bitfield-Mask: 0x01) */ +#define GPIO_MASK0_PINMASK10_Pos (10UL) /*!< PINMASK10 (Bit 10) */ +#define GPIO_MASK0_PINMASK10_Msk (0x400UL) /*!< PINMASK10 (Bitfield-Mask: 0x01) */ +#define GPIO_MASK0_PINMASK11_Pos (11UL) /*!< PINMASK11 (Bit 11) */ +#define GPIO_MASK0_PINMASK11_Msk (0x800UL) /*!< PINMASK11 (Bitfield-Mask: 0x01) */ +#define GPIO_MASK0_PINMASK12_Pos (12UL) /*!< PINMASK12 (Bit 12) */ +#define GPIO_MASK0_PINMASK12_Msk (0x1000UL) /*!< PINMASK12 (Bitfield-Mask: 0x01) */ +#define GPIO_MASK0_PINMASK13_Pos (13UL) /*!< PINMASK13 (Bit 13) */ +#define GPIO_MASK0_PINMASK13_Msk (0x2000UL) /*!< PINMASK13 (Bitfield-Mask: 0x01) */ +#define GPIO_MASK0_PINMASK14_Pos (14UL) /*!< PINMASK14 (Bit 14) */ +#define GPIO_MASK0_PINMASK14_Msk (0x4000UL) /*!< PINMASK14 (Bitfield-Mask: 0x01) */ +#define GPIO_MASK0_PINMASK15_Pos (15UL) /*!< PINMASK15 (Bit 15) */ +#define GPIO_MASK0_PINMASK15_Msk (0x8000UL) /*!< PINMASK15 (Bitfield-Mask: 0x01) */ +#define GPIO_MASK0_PINMASK16_Pos (16UL) /*!< PINMASK16 (Bit 16) */ +#define GPIO_MASK0_PINMASK16_Msk (0x10000UL) /*!< PINMASK16 (Bitfield-Mask: 0x01) */ +#define GPIO_MASK0_PINMASK17_Pos (17UL) /*!< PINMASK17 (Bit 17) */ +#define GPIO_MASK0_PINMASK17_Msk (0x20000UL) /*!< PINMASK17 (Bitfield-Mask: 0x01) */ +#define GPIO_MASK0_PINMASK18_Pos (18UL) /*!< PINMASK18 (Bit 18) */ +#define GPIO_MASK0_PINMASK18_Msk (0x40000UL) /*!< PINMASK18 (Bitfield-Mask: 0x01) */ +#define GPIO_MASK0_PINMASK19_Pos (19UL) /*!< PINMASK19 (Bit 19) */ +#define GPIO_MASK0_PINMASK19_Msk (0x80000UL) /*!< PINMASK19 (Bitfield-Mask: 0x01) */ +#define GPIO_MASK0_PINMASK20_Pos (20UL) /*!< PINMASK20 (Bit 20) */ +#define GPIO_MASK0_PINMASK20_Msk (0x100000UL) /*!< PINMASK20 (Bitfield-Mask: 0x01) */ +#define GPIO_MASK0_PINMASK21_Pos (21UL) /*!< PINMASK21 (Bit 21) */ +#define GPIO_MASK0_PINMASK21_Msk (0x200000UL) /*!< PINMASK21 (Bitfield-Mask: 0x01) */ +#define GPIO_MASK0_PINMASK22_Pos (22UL) /*!< PINMASK22 (Bit 22) */ +#define GPIO_MASK0_PINMASK22_Msk (0x400000UL) /*!< PINMASK22 (Bitfield-Mask: 0x01) */ +#define GPIO_MASK0_PINMASK23_Pos (23UL) /*!< PINMASK23 (Bit 23) */ +#define GPIO_MASK0_PINMASK23_Msk (0x800000UL) /*!< PINMASK23 (Bitfield-Mask: 0x01) */ +#define GPIO_MASK0_PINMASK24_Pos (24UL) /*!< PINMASK24 (Bit 24) */ +#define GPIO_MASK0_PINMASK24_Msk (0x1000000UL) /*!< PINMASK24 (Bitfield-Mask: 0x01) */ +#define GPIO_MASK0_PINMASK25_Pos (25UL) /*!< PINMASK25 (Bit 25) */ +#define GPIO_MASK0_PINMASK25_Msk (0x2000000UL) /*!< PINMASK25 (Bitfield-Mask: 0x01) */ +#define GPIO_MASK0_PINMASK26_Pos (26UL) /*!< PINMASK26 (Bit 26) */ +#define GPIO_MASK0_PINMASK26_Msk (0x4000000UL) /*!< PINMASK26 (Bitfield-Mask: 0x01) */ +#define GPIO_MASK0_PINMASK27_Pos (27UL) /*!< PINMASK27 (Bit 27) */ +#define GPIO_MASK0_PINMASK27_Msk (0x8000000UL) /*!< PINMASK27 (Bitfield-Mask: 0x01) */ +#define GPIO_MASK0_PINMASK28_Pos (28UL) /*!< PINMASK28 (Bit 28) */ +#define GPIO_MASK0_PINMASK28_Msk (0x10000000UL) /*!< PINMASK28 (Bitfield-Mask: 0x01) */ +#define GPIO_MASK0_PINMASK29_Pos (29UL) /*!< PINMASK29 (Bit 29) */ +#define GPIO_MASK0_PINMASK29_Msk (0x20000000UL) /*!< PINMASK29 (Bitfield-Mask: 0x01) */ +#define GPIO_MASK0_PINMASK30_Pos (30UL) /*!< PINMASK30 (Bit 30) */ +#define GPIO_MASK0_PINMASK30_Msk (0x40000000UL) /*!< PINMASK30 (Bitfield-Mask: 0x01) */ +#define GPIO_MASK0_PINMASK31_Pos (31UL) /*!< PINMASK31 (Bit 31) */ +#define GPIO_MASK0_PINMASK31_Msk (0x80000000UL) /*!< PINMASK31 (Bitfield-Mask: 0x01) */ +/* ========================================================= MASK1 ========================================================= */ +#define GPIO_MASK1_PINMASK0_Pos (0UL) /*!< PINMASK0 (Bit 0) */ +#define GPIO_MASK1_PINMASK0_Msk (0x1UL) /*!< PINMASK0 (Bitfield-Mask: 0x01) */ +#define GPIO_MASK1_PINMASK1_Pos (1UL) /*!< PINMASK1 (Bit 1) */ +#define GPIO_MASK1_PINMASK1_Msk (0x2UL) /*!< PINMASK1 (Bitfield-Mask: 0x01) */ +#define GPIO_MASK1_PINMASK2_Pos (2UL) /*!< PINMASK2 (Bit 2) */ +#define GPIO_MASK1_PINMASK2_Msk (0x4UL) /*!< PINMASK2 (Bitfield-Mask: 0x01) */ +#define GPIO_MASK1_PINMASK3_Pos (3UL) /*!< PINMASK3 (Bit 3) */ +#define GPIO_MASK1_PINMASK3_Msk (0x8UL) /*!< PINMASK3 (Bitfield-Mask: 0x01) */ +#define GPIO_MASK1_PINMASK4_Pos (4UL) /*!< PINMASK4 (Bit 4) */ +#define GPIO_MASK1_PINMASK4_Msk (0x10UL) /*!< PINMASK4 (Bitfield-Mask: 0x01) */ +#define GPIO_MASK1_PINMASK5_Pos (5UL) /*!< PINMASK5 (Bit 5) */ +#define GPIO_MASK1_PINMASK5_Msk (0x20UL) /*!< PINMASK5 (Bitfield-Mask: 0x01) */ +#define GPIO_MASK1_PINMASK6_Pos (6UL) /*!< PINMASK6 (Bit 6) */ +#define GPIO_MASK1_PINMASK6_Msk (0x40UL) /*!< PINMASK6 (Bitfield-Mask: 0x01) */ +#define GPIO_MASK1_PINMASK7_Pos (7UL) /*!< PINMASK7 (Bit 7) */ +#define GPIO_MASK1_PINMASK7_Msk (0x80UL) /*!< PINMASK7 (Bitfield-Mask: 0x01) */ +#define GPIO_MASK1_PINMASK8_Pos (8UL) /*!< PINMASK8 (Bit 8) */ +#define GPIO_MASK1_PINMASK8_Msk (0x100UL) /*!< PINMASK8 (Bitfield-Mask: 0x01) */ +#define GPIO_MASK1_PINMASK9_Pos (9UL) /*!< PINMASK9 (Bit 9) */ +#define GPIO_MASK1_PINMASK9_Msk (0x200UL) /*!< PINMASK9 (Bitfield-Mask: 0x01) */ +#define GPIO_MASK1_PINMASK10_Pos (10UL) /*!< PINMASK10 (Bit 10) */ +#define GPIO_MASK1_PINMASK10_Msk (0x400UL) /*!< PINMASK10 (Bitfield-Mask: 0x01) */ +#define GPIO_MASK1_PINMASK11_Pos (11UL) /*!< PINMASK11 (Bit 11) */ +#define GPIO_MASK1_PINMASK11_Msk (0x800UL) /*!< PINMASK11 (Bitfield-Mask: 0x01) */ +#define GPIO_MASK1_PINMASK12_Pos (12UL) /*!< PINMASK12 (Bit 12) */ +#define GPIO_MASK1_PINMASK12_Msk (0x1000UL) /*!< PINMASK12 (Bitfield-Mask: 0x01) */ +#define GPIO_MASK1_PINMASK13_Pos (13UL) /*!< PINMASK13 (Bit 13) */ +#define GPIO_MASK1_PINMASK13_Msk (0x2000UL) /*!< PINMASK13 (Bitfield-Mask: 0x01) */ +#define GPIO_MASK1_PINMASK14_Pos (14UL) /*!< PINMASK14 (Bit 14) */ +#define GPIO_MASK1_PINMASK14_Msk (0x4000UL) /*!< PINMASK14 (Bitfield-Mask: 0x01) */ +#define GPIO_MASK1_PINMASK15_Pos (15UL) /*!< PINMASK15 (Bit 15) */ +#define GPIO_MASK1_PINMASK15_Msk (0x8000UL) /*!< PINMASK15 (Bitfield-Mask: 0x01) */ +#define GPIO_MASK1_PINMASK16_Pos (16UL) /*!< PINMASK16 (Bit 16) */ +#define GPIO_MASK1_PINMASK16_Msk (0x10000UL) /*!< PINMASK16 (Bitfield-Mask: 0x01) */ +#define GPIO_MASK1_PINMASK17_Pos (17UL) /*!< PINMASK17 (Bit 17) */ +#define GPIO_MASK1_PINMASK17_Msk (0x20000UL) /*!< PINMASK17 (Bitfield-Mask: 0x01) */ +#define GPIO_MASK1_PINMASK18_Pos (18UL) /*!< PINMASK18 (Bit 18) */ +#define GPIO_MASK1_PINMASK18_Msk (0x40000UL) /*!< PINMASK18 (Bitfield-Mask: 0x01) */ +#define GPIO_MASK1_PINMASK19_Pos (19UL) /*!< PINMASK19 (Bit 19) */ +#define GPIO_MASK1_PINMASK19_Msk (0x80000UL) /*!< PINMASK19 (Bitfield-Mask: 0x01) */ +#define GPIO_MASK1_PINMASK20_Pos (20UL) /*!< PINMASK20 (Bit 20) */ +#define GPIO_MASK1_PINMASK20_Msk (0x100000UL) /*!< PINMASK20 (Bitfield-Mask: 0x01) */ +#define GPIO_MASK1_PINMASK21_Pos (21UL) /*!< PINMASK21 (Bit 21) */ +#define GPIO_MASK1_PINMASK21_Msk (0x200000UL) /*!< PINMASK21 (Bitfield-Mask: 0x01) */ +#define GPIO_MASK1_PINMASK22_Pos (22UL) /*!< PINMASK22 (Bit 22) */ +#define GPIO_MASK1_PINMASK22_Msk (0x400000UL) /*!< PINMASK22 (Bitfield-Mask: 0x01) */ +#define GPIO_MASK1_PINMASK23_Pos (23UL) /*!< PINMASK23 (Bit 23) */ +#define GPIO_MASK1_PINMASK23_Msk (0x800000UL) /*!< PINMASK23 (Bitfield-Mask: 0x01) */ +#define GPIO_MASK1_PINMASK24_Pos (24UL) /*!< PINMASK24 (Bit 24) */ +#define GPIO_MASK1_PINMASK24_Msk (0x1000000UL) /*!< PINMASK24 (Bitfield-Mask: 0x01) */ +#define GPIO_MASK1_PINMASK25_Pos (25UL) /*!< PINMASK25 (Bit 25) */ +#define GPIO_MASK1_PINMASK25_Msk (0x2000000UL) /*!< PINMASK25 (Bitfield-Mask: 0x01) */ +#define GPIO_MASK1_PINMASK26_Pos (26UL) /*!< PINMASK26 (Bit 26) */ +#define GPIO_MASK1_PINMASK26_Msk (0x4000000UL) /*!< PINMASK26 (Bitfield-Mask: 0x01) */ +#define GPIO_MASK1_PINMASK27_Pos (27UL) /*!< PINMASK27 (Bit 27) */ +#define GPIO_MASK1_PINMASK27_Msk (0x8000000UL) /*!< PINMASK27 (Bitfield-Mask: 0x01) */ +#define GPIO_MASK1_PINMASK28_Pos (28UL) /*!< PINMASK28 (Bit 28) */ +#define GPIO_MASK1_PINMASK28_Msk (0x10000000UL) /*!< PINMASK28 (Bitfield-Mask: 0x01) */ +#define GPIO_MASK1_PINMASK29_Pos (29UL) /*!< PINMASK29 (Bit 29) */ +#define GPIO_MASK1_PINMASK29_Msk (0x20000000UL) /*!< PINMASK29 (Bitfield-Mask: 0x01) */ +#define GPIO_MASK1_PINMASK30_Pos (30UL) /*!< PINMASK30 (Bit 30) */ +#define GPIO_MASK1_PINMASK30_Msk (0x40000000UL) /*!< PINMASK30 (Bitfield-Mask: 0x01) */ +#define GPIO_MASK1_PINMASK31_Pos (31UL) /*!< PINMASK31 (Bit 31) */ +#define GPIO_MASK1_PINMASK31_Msk (0x80000000UL) /*!< PINMASK31 (Bitfield-Mask: 0x01) */ +/* ========================================================= MASK2 ========================================================= */ +#define GPIO_MASK2_PINMASK0_Pos (0UL) /*!< PINMASK0 (Bit 0) */ +#define GPIO_MASK2_PINMASK0_Msk (0x1UL) /*!< PINMASK0 (Bitfield-Mask: 0x01) */ +#define GPIO_MASK2_PINMASK1_Pos (1UL) /*!< PINMASK1 (Bit 1) */ +#define GPIO_MASK2_PINMASK1_Msk (0x2UL) /*!< PINMASK1 (Bitfield-Mask: 0x01) */ +#define GPIO_MASK2_PINMASK2_Pos (2UL) /*!< PINMASK2 (Bit 2) */ +#define GPIO_MASK2_PINMASK2_Msk (0x4UL) /*!< PINMASK2 (Bitfield-Mask: 0x01) */ +#define GPIO_MASK2_PINMASK3_Pos (3UL) /*!< PINMASK3 (Bit 3) */ +#define GPIO_MASK2_PINMASK3_Msk (0x8UL) /*!< PINMASK3 (Bitfield-Mask: 0x01) */ +#define GPIO_MASK2_PINMASK4_Pos (4UL) /*!< PINMASK4 (Bit 4) */ +#define GPIO_MASK2_PINMASK4_Msk (0x10UL) /*!< PINMASK4 (Bitfield-Mask: 0x01) */ +#define GPIO_MASK2_PINMASK5_Pos (5UL) /*!< PINMASK5 (Bit 5) */ +#define GPIO_MASK2_PINMASK5_Msk (0x20UL) /*!< PINMASK5 (Bitfield-Mask: 0x01) */ +#define GPIO_MASK2_PINMASK6_Pos (6UL) /*!< PINMASK6 (Bit 6) */ +#define GPIO_MASK2_PINMASK6_Msk (0x40UL) /*!< PINMASK6 (Bitfield-Mask: 0x01) */ +#define GPIO_MASK2_PINMASK7_Pos (7UL) /*!< PINMASK7 (Bit 7) */ +#define GPIO_MASK2_PINMASK7_Msk (0x80UL) /*!< PINMASK7 (Bitfield-Mask: 0x01) */ +#define GPIO_MASK2_PINMASK8_Pos (8UL) /*!< PINMASK8 (Bit 8) */ +#define GPIO_MASK2_PINMASK8_Msk (0x100UL) /*!< PINMASK8 (Bitfield-Mask: 0x01) */ +#define GPIO_MASK2_PINMASK9_Pos (9UL) /*!< PINMASK9 (Bit 9) */ +#define GPIO_MASK2_PINMASK9_Msk (0x200UL) /*!< PINMASK9 (Bitfield-Mask: 0x01) */ +#define GPIO_MASK2_PINMASK10_Pos (10UL) /*!< PINMASK10 (Bit 10) */ +#define GPIO_MASK2_PINMASK10_Msk (0x400UL) /*!< PINMASK10 (Bitfield-Mask: 0x01) */ +#define GPIO_MASK2_PINMASK11_Pos (11UL) /*!< PINMASK11 (Bit 11) */ +#define GPIO_MASK2_PINMASK11_Msk (0x800UL) /*!< PINMASK11 (Bitfield-Mask: 0x01) */ +#define GPIO_MASK2_PINMASK12_Pos (12UL) /*!< PINMASK12 (Bit 12) */ +#define GPIO_MASK2_PINMASK12_Msk (0x1000UL) /*!< PINMASK12 (Bitfield-Mask: 0x01) */ +#define GPIO_MASK2_PINMASK13_Pos (13UL) /*!< PINMASK13 (Bit 13) */ +#define GPIO_MASK2_PINMASK13_Msk (0x2000UL) /*!< PINMASK13 (Bitfield-Mask: 0x01) */ +#define GPIO_MASK2_PINMASK14_Pos (14UL) /*!< PINMASK14 (Bit 14) */ +#define GPIO_MASK2_PINMASK14_Msk (0x4000UL) /*!< PINMASK14 (Bitfield-Mask: 0x01) */ +#define GPIO_MASK2_PINMASK15_Pos (15UL) /*!< PINMASK15 (Bit 15) */ +#define GPIO_MASK2_PINMASK15_Msk (0x8000UL) /*!< PINMASK15 (Bitfield-Mask: 0x01) */ +#define GPIO_MASK2_PINMASK16_Pos (16UL) /*!< PINMASK16 (Bit 16) */ +#define GPIO_MASK2_PINMASK16_Msk (0x10000UL) /*!< PINMASK16 (Bitfield-Mask: 0x01) */ +#define GPIO_MASK2_PINMASK17_Pos (17UL) /*!< PINMASK17 (Bit 17) */ +#define GPIO_MASK2_PINMASK17_Msk (0x20000UL) /*!< PINMASK17 (Bitfield-Mask: 0x01) */ +#define GPIO_MASK2_PINMASK18_Pos (18UL) /*!< PINMASK18 (Bit 18) */ +#define GPIO_MASK2_PINMASK18_Msk (0x40000UL) /*!< PINMASK18 (Bitfield-Mask: 0x01) */ +#define GPIO_MASK2_PINMASK19_Pos (19UL) /*!< PINMASK19 (Bit 19) */ +#define GPIO_MASK2_PINMASK19_Msk (0x80000UL) /*!< PINMASK19 (Bitfield-Mask: 0x01) */ +#define GPIO_MASK2_PINMASK20_Pos (20UL) /*!< PINMASK20 (Bit 20) */ +#define GPIO_MASK2_PINMASK20_Msk (0x100000UL) /*!< PINMASK20 (Bitfield-Mask: 0x01) */ +#define GPIO_MASK2_PINMASK21_Pos (21UL) /*!< PINMASK21 (Bit 21) */ +#define GPIO_MASK2_PINMASK21_Msk (0x200000UL) /*!< PINMASK21 (Bitfield-Mask: 0x01) */ +#define GPIO_MASK2_PINMASK22_Pos (22UL) /*!< PINMASK22 (Bit 22) */ +#define GPIO_MASK2_PINMASK22_Msk (0x400000UL) /*!< PINMASK22 (Bitfield-Mask: 0x01) */ +#define GPIO_MASK2_PINMASK23_Pos (23UL) /*!< PINMASK23 (Bit 23) */ +#define GPIO_MASK2_PINMASK23_Msk (0x800000UL) /*!< PINMASK23 (Bitfield-Mask: 0x01) */ +#define GPIO_MASK2_PINMASK24_Pos (24UL) /*!< PINMASK24 (Bit 24) */ +#define GPIO_MASK2_PINMASK24_Msk (0x1000000UL) /*!< PINMASK24 (Bitfield-Mask: 0x01) */ +#define GPIO_MASK2_PINMASK25_Pos (25UL) /*!< PINMASK25 (Bit 25) */ +#define GPIO_MASK2_PINMASK25_Msk (0x2000000UL) /*!< PINMASK25 (Bitfield-Mask: 0x01) */ +#define GPIO_MASK2_PINMASK26_Pos (26UL) /*!< PINMASK26 (Bit 26) */ +#define GPIO_MASK2_PINMASK26_Msk (0x4000000UL) /*!< PINMASK26 (Bitfield-Mask: 0x01) */ +#define GPIO_MASK2_PINMASK27_Pos (27UL) /*!< PINMASK27 (Bit 27) */ +#define GPIO_MASK2_PINMASK27_Msk (0x8000000UL) /*!< PINMASK27 (Bitfield-Mask: 0x01) */ +#define GPIO_MASK2_PINMASK28_Pos (28UL) /*!< PINMASK28 (Bit 28) */ +#define GPIO_MASK2_PINMASK28_Msk (0x10000000UL) /*!< PINMASK28 (Bitfield-Mask: 0x01) */ +#define GPIO_MASK2_PINMASK29_Pos (29UL) /*!< PINMASK29 (Bit 29) */ +#define GPIO_MASK2_PINMASK29_Msk (0x20000000UL) /*!< PINMASK29 (Bitfield-Mask: 0x01) */ +#define GPIO_MASK2_PINMASK30_Pos (30UL) /*!< PINMASK30 (Bit 30) */ +#define GPIO_MASK2_PINMASK30_Msk (0x40000000UL) /*!< PINMASK30 (Bitfield-Mask: 0x01) */ +#define GPIO_MASK2_PINMASK31_Pos (31UL) /*!< PINMASK31 (Bit 31) */ +#define GPIO_MASK2_PINMASK31_Msk (0x80000000UL) /*!< PINMASK31 (Bitfield-Mask: 0x01) */ +/* ========================================================= MASK3 ========================================================= */ +#define GPIO_MASK3_PINMASK0_Pos (0UL) /*!< PINMASK0 (Bit 0) */ +#define GPIO_MASK3_PINMASK0_Msk (0x1UL) /*!< PINMASK0 (Bitfield-Mask: 0x01) */ +#define GPIO_MASK3_PINMASK1_Pos (1UL) /*!< PINMASK1 (Bit 1) */ +#define GPIO_MASK3_PINMASK1_Msk (0x2UL) /*!< PINMASK1 (Bitfield-Mask: 0x01) */ +#define GPIO_MASK3_PINMASK2_Pos (2UL) /*!< PINMASK2 (Bit 2) */ +#define GPIO_MASK3_PINMASK2_Msk (0x4UL) /*!< PINMASK2 (Bitfield-Mask: 0x01) */ +#define GPIO_MASK3_PINMASK3_Pos (3UL) /*!< PINMASK3 (Bit 3) */ +#define GPIO_MASK3_PINMASK3_Msk (0x8UL) /*!< PINMASK3 (Bitfield-Mask: 0x01) */ +#define GPIO_MASK3_PINMASK4_Pos (4UL) /*!< PINMASK4 (Bit 4) */ +#define GPIO_MASK3_PINMASK4_Msk (0x10UL) /*!< PINMASK4 (Bitfield-Mask: 0x01) */ +#define GPIO_MASK3_PINMASK5_Pos (5UL) /*!< PINMASK5 (Bit 5) */ +#define GPIO_MASK3_PINMASK5_Msk (0x20UL) /*!< PINMASK5 (Bitfield-Mask: 0x01) */ +#define GPIO_MASK3_PINMASK6_Pos (6UL) /*!< PINMASK6 (Bit 6) */ +#define GPIO_MASK3_PINMASK6_Msk (0x40UL) /*!< PINMASK6 (Bitfield-Mask: 0x01) */ +#define GPIO_MASK3_PINMASK7_Pos (7UL) /*!< PINMASK7 (Bit 7) */ +#define GPIO_MASK3_PINMASK7_Msk (0x80UL) /*!< PINMASK7 (Bitfield-Mask: 0x01) */ +#define GPIO_MASK3_PINMASK8_Pos (8UL) /*!< PINMASK8 (Bit 8) */ +#define GPIO_MASK3_PINMASK8_Msk (0x100UL) /*!< PINMASK8 (Bitfield-Mask: 0x01) */ +#define GPIO_MASK3_PINMASK9_Pos (9UL) /*!< PINMASK9 (Bit 9) */ +#define GPIO_MASK3_PINMASK9_Msk (0x200UL) /*!< PINMASK9 (Bitfield-Mask: 0x01) */ +#define GPIO_MASK3_PINMASK10_Pos (10UL) /*!< PINMASK10 (Bit 10) */ +#define GPIO_MASK3_PINMASK10_Msk (0x400UL) /*!< PINMASK10 (Bitfield-Mask: 0x01) */ +#define GPIO_MASK3_PINMASK11_Pos (11UL) /*!< PINMASK11 (Bit 11) */ +#define GPIO_MASK3_PINMASK11_Msk (0x800UL) /*!< PINMASK11 (Bitfield-Mask: 0x01) */ +#define GPIO_MASK3_PINMASK12_Pos (12UL) /*!< PINMASK12 (Bit 12) */ +#define GPIO_MASK3_PINMASK12_Msk (0x1000UL) /*!< PINMASK12 (Bitfield-Mask: 0x01) */ +#define GPIO_MASK3_PINMASK13_Pos (13UL) /*!< PINMASK13 (Bit 13) */ +#define GPIO_MASK3_PINMASK13_Msk (0x2000UL) /*!< PINMASK13 (Bitfield-Mask: 0x01) */ +#define GPIO_MASK3_PINMASK14_Pos (14UL) /*!< PINMASK14 (Bit 14) */ +#define GPIO_MASK3_PINMASK14_Msk (0x4000UL) /*!< PINMASK14 (Bitfield-Mask: 0x01) */ +#define GPIO_MASK3_PINMASK15_Pos (15UL) /*!< PINMASK15 (Bit 15) */ +#define GPIO_MASK3_PINMASK15_Msk (0x8000UL) /*!< PINMASK15 (Bitfield-Mask: 0x01) */ +#define GPIO_MASK3_PINMASK16_Pos (16UL) /*!< PINMASK16 (Bit 16) */ +#define GPIO_MASK3_PINMASK16_Msk (0x10000UL) /*!< PINMASK16 (Bitfield-Mask: 0x01) */ +#define GPIO_MASK3_PINMASK17_Pos (17UL) /*!< PINMASK17 (Bit 17) */ +#define GPIO_MASK3_PINMASK17_Msk (0x20000UL) /*!< PINMASK17 (Bitfield-Mask: 0x01) */ +#define GPIO_MASK3_PINMASK18_Pos (18UL) /*!< PINMASK18 (Bit 18) */ +#define GPIO_MASK3_PINMASK18_Msk (0x40000UL) /*!< PINMASK18 (Bitfield-Mask: 0x01) */ +#define GPIO_MASK3_PINMASK19_Pos (19UL) /*!< PINMASK19 (Bit 19) */ +#define GPIO_MASK3_PINMASK19_Msk (0x80000UL) /*!< PINMASK19 (Bitfield-Mask: 0x01) */ +#define GPIO_MASK3_PINMASK20_Pos (20UL) /*!< PINMASK20 (Bit 20) */ +#define GPIO_MASK3_PINMASK20_Msk (0x100000UL) /*!< PINMASK20 (Bitfield-Mask: 0x01) */ +#define GPIO_MASK3_PINMASK21_Pos (21UL) /*!< PINMASK21 (Bit 21) */ +#define GPIO_MASK3_PINMASK21_Msk (0x200000UL) /*!< PINMASK21 (Bitfield-Mask: 0x01) */ +#define GPIO_MASK3_PINMASK22_Pos (22UL) /*!< PINMASK22 (Bit 22) */ +#define GPIO_MASK3_PINMASK22_Msk (0x400000UL) /*!< PINMASK22 (Bitfield-Mask: 0x01) */ +#define GPIO_MASK3_PINMASK23_Pos (23UL) /*!< PINMASK23 (Bit 23) */ +#define GPIO_MASK3_PINMASK23_Msk (0x800000UL) /*!< PINMASK23 (Bitfield-Mask: 0x01) */ +#define GPIO_MASK3_PINMASK24_Pos (24UL) /*!< PINMASK24 (Bit 24) */ +#define GPIO_MASK3_PINMASK24_Msk (0x1000000UL) /*!< PINMASK24 (Bitfield-Mask: 0x01) */ +#define GPIO_MASK3_PINMASK25_Pos (25UL) /*!< PINMASK25 (Bit 25) */ +#define GPIO_MASK3_PINMASK25_Msk (0x2000000UL) /*!< PINMASK25 (Bitfield-Mask: 0x01) */ +#define GPIO_MASK3_PINMASK26_Pos (26UL) /*!< PINMASK26 (Bit 26) */ +#define GPIO_MASK3_PINMASK26_Msk (0x4000000UL) /*!< PINMASK26 (Bitfield-Mask: 0x01) */ +#define GPIO_MASK3_PINMASK27_Pos (27UL) /*!< PINMASK27 (Bit 27) */ +#define GPIO_MASK3_PINMASK27_Msk (0x8000000UL) /*!< PINMASK27 (Bitfield-Mask: 0x01) */ +#define GPIO_MASK3_PINMASK28_Pos (28UL) /*!< PINMASK28 (Bit 28) */ +#define GPIO_MASK3_PINMASK28_Msk (0x10000000UL) /*!< PINMASK28 (Bitfield-Mask: 0x01) */ +#define GPIO_MASK3_PINMASK29_Pos (29UL) /*!< PINMASK29 (Bit 29) */ +#define GPIO_MASK3_PINMASK29_Msk (0x20000000UL) /*!< PINMASK29 (Bitfield-Mask: 0x01) */ +#define GPIO_MASK3_PINMASK30_Pos (30UL) /*!< PINMASK30 (Bit 30) */ +#define GPIO_MASK3_PINMASK30_Msk (0x40000000UL) /*!< PINMASK30 (Bitfield-Mask: 0x01) */ +#define GPIO_MASK3_PINMASK31_Pos (31UL) /*!< PINMASK31 (Bit 31) */ +#define GPIO_MASK3_PINMASK31_Msk (0x80000000UL) /*!< PINMASK31 (Bitfield-Mask: 0x01) */ +/* ========================================================= MASK4 ========================================================= */ +#define GPIO_MASK4_PINMASK0_Pos (0UL) /*!< PINMASK0 (Bit 0) */ +#define GPIO_MASK4_PINMASK0_Msk (0x1UL) /*!< PINMASK0 (Bitfield-Mask: 0x01) */ +#define GPIO_MASK4_PINMASK1_Pos (1UL) /*!< PINMASK1 (Bit 1) */ +#define GPIO_MASK4_PINMASK1_Msk (0x2UL) /*!< PINMASK1 (Bitfield-Mask: 0x01) */ +#define GPIO_MASK4_PINMASK2_Pos (2UL) /*!< PINMASK2 (Bit 2) */ +#define GPIO_MASK4_PINMASK2_Msk (0x4UL) /*!< PINMASK2 (Bitfield-Mask: 0x01) */ +#define GPIO_MASK4_PINMASK3_Pos (3UL) /*!< PINMASK3 (Bit 3) */ +#define GPIO_MASK4_PINMASK3_Msk (0x8UL) /*!< PINMASK3 (Bitfield-Mask: 0x01) */ +#define GPIO_MASK4_PINMASK4_Pos (4UL) /*!< PINMASK4 (Bit 4) */ +#define GPIO_MASK4_PINMASK4_Msk (0x10UL) /*!< PINMASK4 (Bitfield-Mask: 0x01) */ +#define GPIO_MASK4_PINMASK5_Pos (5UL) /*!< PINMASK5 (Bit 5) */ +#define GPIO_MASK4_PINMASK5_Msk (0x20UL) /*!< PINMASK5 (Bitfield-Mask: 0x01) */ +#define GPIO_MASK4_PINMASK6_Pos (6UL) /*!< PINMASK6 (Bit 6) */ +#define GPIO_MASK4_PINMASK6_Msk (0x40UL) /*!< PINMASK6 (Bitfield-Mask: 0x01) */ +#define GPIO_MASK4_PINMASK7_Pos (7UL) /*!< PINMASK7 (Bit 7) */ +#define GPIO_MASK4_PINMASK7_Msk (0x80UL) /*!< PINMASK7 (Bitfield-Mask: 0x01) */ +#define GPIO_MASK4_PINMASK8_Pos (8UL) /*!< PINMASK8 (Bit 8) */ +#define GPIO_MASK4_PINMASK8_Msk (0x100UL) /*!< PINMASK8 (Bitfield-Mask: 0x01) */ +#define GPIO_MASK4_PINMASK9_Pos (9UL) /*!< PINMASK9 (Bit 9) */ +#define GPIO_MASK4_PINMASK9_Msk (0x200UL) /*!< PINMASK9 (Bitfield-Mask: 0x01) */ +#define GPIO_MASK4_PINMASK10_Pos (10UL) /*!< PINMASK10 (Bit 10) */ +#define GPIO_MASK4_PINMASK10_Msk (0x400UL) /*!< PINMASK10 (Bitfield-Mask: 0x01) */ +#define GPIO_MASK4_PINMASK11_Pos (11UL) /*!< PINMASK11 (Bit 11) */ +#define GPIO_MASK4_PINMASK11_Msk (0x800UL) /*!< PINMASK11 (Bitfield-Mask: 0x01) */ +#define GPIO_MASK4_PINMASK12_Pos (12UL) /*!< PINMASK12 (Bit 12) */ +#define GPIO_MASK4_PINMASK12_Msk (0x1000UL) /*!< PINMASK12 (Bitfield-Mask: 0x01) */ +#define GPIO_MASK4_PINMASK13_Pos (13UL) /*!< PINMASK13 (Bit 13) */ +#define GPIO_MASK4_PINMASK13_Msk (0x2000UL) /*!< PINMASK13 (Bitfield-Mask: 0x01) */ +#define GPIO_MASK4_PINMASK14_Pos (14UL) /*!< PINMASK14 (Bit 14) */ +#define GPIO_MASK4_PINMASK14_Msk (0x4000UL) /*!< PINMASK14 (Bitfield-Mask: 0x01) */ +#define GPIO_MASK4_PINMASK15_Pos (15UL) /*!< PINMASK15 (Bit 15) */ +#define GPIO_MASK4_PINMASK15_Msk (0x8000UL) /*!< PINMASK15 (Bitfield-Mask: 0x01) */ +#define GPIO_MASK4_PINMASK16_Pos (16UL) /*!< PINMASK16 (Bit 16) */ +#define GPIO_MASK4_PINMASK16_Msk (0x10000UL) /*!< PINMASK16 (Bitfield-Mask: 0x01) */ +#define GPIO_MASK4_PINMASK17_Pos (17UL) /*!< PINMASK17 (Bit 17) */ +#define GPIO_MASK4_PINMASK17_Msk (0x20000UL) /*!< PINMASK17 (Bitfield-Mask: 0x01) */ +#define GPIO_MASK4_PINMASK18_Pos (18UL) /*!< PINMASK18 (Bit 18) */ +#define GPIO_MASK4_PINMASK18_Msk (0x40000UL) /*!< PINMASK18 (Bitfield-Mask: 0x01) */ +#define GPIO_MASK4_PINMASK19_Pos (19UL) /*!< PINMASK19 (Bit 19) */ +#define GPIO_MASK4_PINMASK19_Msk (0x80000UL) /*!< PINMASK19 (Bitfield-Mask: 0x01) */ +#define GPIO_MASK4_PINMASK20_Pos (20UL) /*!< PINMASK20 (Bit 20) */ +#define GPIO_MASK4_PINMASK20_Msk (0x100000UL) /*!< PINMASK20 (Bitfield-Mask: 0x01) */ +#define GPIO_MASK4_PINMASK21_Pos (21UL) /*!< PINMASK21 (Bit 21) */ +#define GPIO_MASK4_PINMASK21_Msk (0x200000UL) /*!< PINMASK21 (Bitfield-Mask: 0x01) */ +#define GPIO_MASK4_PINMASK22_Pos (22UL) /*!< PINMASK22 (Bit 22) */ +#define GPIO_MASK4_PINMASK22_Msk (0x400000UL) /*!< PINMASK22 (Bitfield-Mask: 0x01) */ +#define GPIO_MASK4_PINMASK23_Pos (23UL) /*!< PINMASK23 (Bit 23) */ +#define GPIO_MASK4_PINMASK23_Msk (0x800000UL) /*!< PINMASK23 (Bitfield-Mask: 0x01) */ +#define GPIO_MASK4_PINMASK24_Pos (24UL) /*!< PINMASK24 (Bit 24) */ +#define GPIO_MASK4_PINMASK24_Msk (0x1000000UL) /*!< PINMASK24 (Bitfield-Mask: 0x01) */ +#define GPIO_MASK4_PINMASK25_Pos (25UL) /*!< PINMASK25 (Bit 25) */ +#define GPIO_MASK4_PINMASK25_Msk (0x2000000UL) /*!< PINMASK25 (Bitfield-Mask: 0x01) */ +#define GPIO_MASK4_PINMASK26_Pos (26UL) /*!< PINMASK26 (Bit 26) */ +#define GPIO_MASK4_PINMASK26_Msk (0x4000000UL) /*!< PINMASK26 (Bitfield-Mask: 0x01) */ +#define GPIO_MASK4_PINMASK27_Pos (27UL) /*!< PINMASK27 (Bit 27) */ +#define GPIO_MASK4_PINMASK27_Msk (0x8000000UL) /*!< PINMASK27 (Bitfield-Mask: 0x01) */ +#define GPIO_MASK4_PINMASK28_Pos (28UL) /*!< PINMASK28 (Bit 28) */ +#define GPIO_MASK4_PINMASK28_Msk (0x10000000UL) /*!< PINMASK28 (Bitfield-Mask: 0x01) */ +#define GPIO_MASK4_PINMASK29_Pos (29UL) /*!< PINMASK29 (Bit 29) */ +#define GPIO_MASK4_PINMASK29_Msk (0x20000000UL) /*!< PINMASK29 (Bitfield-Mask: 0x01) */ +#define GPIO_MASK4_PINMASK30_Pos (30UL) /*!< PINMASK30 (Bit 30) */ +#define GPIO_MASK4_PINMASK30_Msk (0x40000000UL) /*!< PINMASK30 (Bitfield-Mask: 0x01) */ +#define GPIO_MASK4_PINMASK31_Pos (31UL) /*!< PINMASK31 (Bit 31) */ +#define GPIO_MASK4_PINMASK31_Msk (0x80000000UL) /*!< PINMASK31 (Bitfield-Mask: 0x01) */ +/* ========================================================= PIN0 ========================================================== */ +#define GPIO_PIN0_PINVAL0_Pos (0UL) /*!< PINVAL0 (Bit 0) */ +#define GPIO_PIN0_PINVAL0_Msk (0x1UL) /*!< PINVAL0 (Bitfield-Mask: 0x01) */ +#define GPIO_PIN0_PINVAL1_Pos (1UL) /*!< PINVAL1 (Bit 1) */ +#define GPIO_PIN0_PINVAL1_Msk (0x2UL) /*!< PINVAL1 (Bitfield-Mask: 0x01) */ +#define GPIO_PIN0_PINVAL2_Pos (2UL) /*!< PINVAL2 (Bit 2) */ +#define GPIO_PIN0_PINVAL2_Msk (0x4UL) /*!< PINVAL2 (Bitfield-Mask: 0x01) */ +#define GPIO_PIN0_PINVAL3_Pos (3UL) /*!< PINVAL3 (Bit 3) */ +#define GPIO_PIN0_PINVAL3_Msk (0x8UL) /*!< PINVAL3 (Bitfield-Mask: 0x01) */ +#define GPIO_PIN0_PINVAL4_Pos (4UL) /*!< PINVAL4 (Bit 4) */ +#define GPIO_PIN0_PINVAL4_Msk (0x10UL) /*!< PINVAL4 (Bitfield-Mask: 0x01) */ +#define GPIO_PIN0_PINVAL5_Pos (5UL) /*!< PINVAL5 (Bit 5) */ +#define GPIO_PIN0_PINVAL5_Msk (0x20UL) /*!< PINVAL5 (Bitfield-Mask: 0x01) */ +#define GPIO_PIN0_PINVAL6_Pos (6UL) /*!< PINVAL6 (Bit 6) */ +#define GPIO_PIN0_PINVAL6_Msk (0x40UL) /*!< PINVAL6 (Bitfield-Mask: 0x01) */ +#define GPIO_PIN0_PINVAL7_Pos (7UL) /*!< PINVAL7 (Bit 7) */ +#define GPIO_PIN0_PINVAL7_Msk (0x80UL) /*!< PINVAL7 (Bitfield-Mask: 0x01) */ +#define GPIO_PIN0_PINVAL8_Pos (8UL) /*!< PINVAL8 (Bit 8) */ +#define GPIO_PIN0_PINVAL8_Msk (0x100UL) /*!< PINVAL8 (Bitfield-Mask: 0x01) */ +#define GPIO_PIN0_PINVAL9_Pos (9UL) /*!< PINVAL9 (Bit 9) */ +#define GPIO_PIN0_PINVAL9_Msk (0x200UL) /*!< PINVAL9 (Bitfield-Mask: 0x01) */ +#define GPIO_PIN0_PINVAL10_Pos (10UL) /*!< PINVAL10 (Bit 10) */ +#define GPIO_PIN0_PINVAL10_Msk (0x400UL) /*!< PINVAL10 (Bitfield-Mask: 0x01) */ +#define GPIO_PIN0_PINVAL11_Pos (11UL) /*!< PINVAL11 (Bit 11) */ +#define GPIO_PIN0_PINVAL11_Msk (0x800UL) /*!< PINVAL11 (Bitfield-Mask: 0x01) */ +#define GPIO_PIN0_PINVAL12_Pos (12UL) /*!< PINVAL12 (Bit 12) */ +#define GPIO_PIN0_PINVAL12_Msk (0x1000UL) /*!< PINVAL12 (Bitfield-Mask: 0x01) */ +#define GPIO_PIN0_PINVAL13_Pos (13UL) /*!< PINVAL13 (Bit 13) */ +#define GPIO_PIN0_PINVAL13_Msk (0x2000UL) /*!< PINVAL13 (Bitfield-Mask: 0x01) */ +#define GPIO_PIN0_PINVAL14_Pos (14UL) /*!< PINVAL14 (Bit 14) */ +#define GPIO_PIN0_PINVAL14_Msk (0x4000UL) /*!< PINVAL14 (Bitfield-Mask: 0x01) */ +#define GPIO_PIN0_PINVAL15_Pos (15UL) /*!< PINVAL15 (Bit 15) */ +#define GPIO_PIN0_PINVAL15_Msk (0x8000UL) /*!< PINVAL15 (Bitfield-Mask: 0x01) */ +#define GPIO_PIN0_PINVAL16_Pos (16UL) /*!< PINVAL16 (Bit 16) */ +#define GPIO_PIN0_PINVAL16_Msk (0x10000UL) /*!< PINVAL16 (Bitfield-Mask: 0x01) */ +#define GPIO_PIN0_PINVAL17_Pos (17UL) /*!< PINVAL17 (Bit 17) */ +#define GPIO_PIN0_PINVAL17_Msk (0x20000UL) /*!< PINVAL17 (Bitfield-Mask: 0x01) */ +#define GPIO_PIN0_PINVAL18_Pos (18UL) /*!< PINVAL18 (Bit 18) */ +#define GPIO_PIN0_PINVAL18_Msk (0x40000UL) /*!< PINVAL18 (Bitfield-Mask: 0x01) */ +#define GPIO_PIN0_PINVAL19_Pos (19UL) /*!< PINVAL19 (Bit 19) */ +#define GPIO_PIN0_PINVAL19_Msk (0x80000UL) /*!< PINVAL19 (Bitfield-Mask: 0x01) */ +#define GPIO_PIN0_PINVAL20_Pos (20UL) /*!< PINVAL20 (Bit 20) */ +#define GPIO_PIN0_PINVAL20_Msk (0x100000UL) /*!< PINVAL20 (Bitfield-Mask: 0x01) */ +#define GPIO_PIN0_PINVAL21_Pos (21UL) /*!< PINVAL21 (Bit 21) */ +#define GPIO_PIN0_PINVAL21_Msk (0x200000UL) /*!< PINVAL21 (Bitfield-Mask: 0x01) */ +#define GPIO_PIN0_PINVAL22_Pos (22UL) /*!< PINVAL22 (Bit 22) */ +#define GPIO_PIN0_PINVAL22_Msk (0x400000UL) /*!< PINVAL22 (Bitfield-Mask: 0x01) */ +#define GPIO_PIN0_PINVAL23_Pos (23UL) /*!< PINVAL23 (Bit 23) */ +#define GPIO_PIN0_PINVAL23_Msk (0x800000UL) /*!< PINVAL23 (Bitfield-Mask: 0x01) */ +#define GPIO_PIN0_PINVAL24_Pos (24UL) /*!< PINVAL24 (Bit 24) */ +#define GPIO_PIN0_PINVAL24_Msk (0x1000000UL) /*!< PINVAL24 (Bitfield-Mask: 0x01) */ +#define GPIO_PIN0_PINVAL25_Pos (25UL) /*!< PINVAL25 (Bit 25) */ +#define GPIO_PIN0_PINVAL25_Msk (0x2000000UL) /*!< PINVAL25 (Bitfield-Mask: 0x01) */ +#define GPIO_PIN0_PINVAL26_Pos (26UL) /*!< PINVAL26 (Bit 26) */ +#define GPIO_PIN0_PINVAL26_Msk (0x4000000UL) /*!< PINVAL26 (Bitfield-Mask: 0x01) */ +#define GPIO_PIN0_PINVAL27_Pos (27UL) /*!< PINVAL27 (Bit 27) */ +#define GPIO_PIN0_PINVAL27_Msk (0x8000000UL) /*!< PINVAL27 (Bitfield-Mask: 0x01) */ +#define GPIO_PIN0_PINVAL28_Pos (28UL) /*!< PINVAL28 (Bit 28) */ +#define GPIO_PIN0_PINVAL28_Msk (0x10000000UL) /*!< PINVAL28 (Bitfield-Mask: 0x01) */ +#define GPIO_PIN0_PINVAL29_Pos (29UL) /*!< PINVAL29 (Bit 29) */ +#define GPIO_PIN0_PINVAL29_Msk (0x20000000UL) /*!< PINVAL29 (Bitfield-Mask: 0x01) */ +#define GPIO_PIN0_PINVAL30_Pos (30UL) /*!< PINVAL30 (Bit 30) */ +#define GPIO_PIN0_PINVAL30_Msk (0x40000000UL) /*!< PINVAL30 (Bitfield-Mask: 0x01) */ +#define GPIO_PIN0_PINVAL31_Pos (31UL) /*!< PINVAL31 (Bit 31) */ +#define GPIO_PIN0_PINVAL31_Msk (0x80000000UL) /*!< PINVAL31 (Bitfield-Mask: 0x01) */ +/* ========================================================= PIN1 ========================================================== */ +#define GPIO_PIN1_PINVAL0_Pos (0UL) /*!< PINVAL0 (Bit 0) */ +#define GPIO_PIN1_PINVAL0_Msk (0x1UL) /*!< PINVAL0 (Bitfield-Mask: 0x01) */ +#define GPIO_PIN1_PINVAL1_Pos (1UL) /*!< PINVAL1 (Bit 1) */ +#define GPIO_PIN1_PINVAL1_Msk (0x2UL) /*!< PINVAL1 (Bitfield-Mask: 0x01) */ +#define GPIO_PIN1_PINVAL2_Pos (2UL) /*!< PINVAL2 (Bit 2) */ +#define GPIO_PIN1_PINVAL2_Msk (0x4UL) /*!< PINVAL2 (Bitfield-Mask: 0x01) */ +#define GPIO_PIN1_PINVAL3_Pos (3UL) /*!< PINVAL3 (Bit 3) */ +#define GPIO_PIN1_PINVAL3_Msk (0x8UL) /*!< PINVAL3 (Bitfield-Mask: 0x01) */ +#define GPIO_PIN1_PINVAL4_Pos (4UL) /*!< PINVAL4 (Bit 4) */ +#define GPIO_PIN1_PINVAL4_Msk (0x10UL) /*!< PINVAL4 (Bitfield-Mask: 0x01) */ +#define GPIO_PIN1_PINVAL5_Pos (5UL) /*!< PINVAL5 (Bit 5) */ +#define GPIO_PIN1_PINVAL5_Msk (0x20UL) /*!< PINVAL5 (Bitfield-Mask: 0x01) */ +#define GPIO_PIN1_PINVAL6_Pos (6UL) /*!< PINVAL6 (Bit 6) */ +#define GPIO_PIN1_PINVAL6_Msk (0x40UL) /*!< PINVAL6 (Bitfield-Mask: 0x01) */ +#define GPIO_PIN1_PINVAL7_Pos (7UL) /*!< PINVAL7 (Bit 7) */ +#define GPIO_PIN1_PINVAL7_Msk (0x80UL) /*!< PINVAL7 (Bitfield-Mask: 0x01) */ +#define GPIO_PIN1_PINVAL8_Pos (8UL) /*!< PINVAL8 (Bit 8) */ +#define GPIO_PIN1_PINVAL8_Msk (0x100UL) /*!< PINVAL8 (Bitfield-Mask: 0x01) */ +#define GPIO_PIN1_PINVAL9_Pos (9UL) /*!< PINVAL9 (Bit 9) */ +#define GPIO_PIN1_PINVAL9_Msk (0x200UL) /*!< PINVAL9 (Bitfield-Mask: 0x01) */ +#define GPIO_PIN1_PINVAL10_Pos (10UL) /*!< PINVAL10 (Bit 10) */ +#define GPIO_PIN1_PINVAL10_Msk (0x400UL) /*!< PINVAL10 (Bitfield-Mask: 0x01) */ +#define GPIO_PIN1_PINVAL11_Pos (11UL) /*!< PINVAL11 (Bit 11) */ +#define GPIO_PIN1_PINVAL11_Msk (0x800UL) /*!< PINVAL11 (Bitfield-Mask: 0x01) */ +#define GPIO_PIN1_PINVAL12_Pos (12UL) /*!< PINVAL12 (Bit 12) */ +#define GPIO_PIN1_PINVAL12_Msk (0x1000UL) /*!< PINVAL12 (Bitfield-Mask: 0x01) */ +#define GPIO_PIN1_PINVAL13_Pos (13UL) /*!< PINVAL13 (Bit 13) */ +#define GPIO_PIN1_PINVAL13_Msk (0x2000UL) /*!< PINVAL13 (Bitfield-Mask: 0x01) */ +#define GPIO_PIN1_PINVAL14_Pos (14UL) /*!< PINVAL14 (Bit 14) */ +#define GPIO_PIN1_PINVAL14_Msk (0x4000UL) /*!< PINVAL14 (Bitfield-Mask: 0x01) */ +#define GPIO_PIN1_PINVAL15_Pos (15UL) /*!< PINVAL15 (Bit 15) */ +#define GPIO_PIN1_PINVAL15_Msk (0x8000UL) /*!< PINVAL15 (Bitfield-Mask: 0x01) */ +#define GPIO_PIN1_PINVAL16_Pos (16UL) /*!< PINVAL16 (Bit 16) */ +#define GPIO_PIN1_PINVAL16_Msk (0x10000UL) /*!< PINVAL16 (Bitfield-Mask: 0x01) */ +#define GPIO_PIN1_PINVAL17_Pos (17UL) /*!< PINVAL17 (Bit 17) */ +#define GPIO_PIN1_PINVAL17_Msk (0x20000UL) /*!< PINVAL17 (Bitfield-Mask: 0x01) */ +#define GPIO_PIN1_PINVAL18_Pos (18UL) /*!< PINVAL18 (Bit 18) */ +#define GPIO_PIN1_PINVAL18_Msk (0x40000UL) /*!< PINVAL18 (Bitfield-Mask: 0x01) */ +#define GPIO_PIN1_PINVAL19_Pos (19UL) /*!< PINVAL19 (Bit 19) */ +#define GPIO_PIN1_PINVAL19_Msk (0x80000UL) /*!< PINVAL19 (Bitfield-Mask: 0x01) */ +#define GPIO_PIN1_PINVAL20_Pos (20UL) /*!< PINVAL20 (Bit 20) */ +#define GPIO_PIN1_PINVAL20_Msk (0x100000UL) /*!< PINVAL20 (Bitfield-Mask: 0x01) */ +#define GPIO_PIN1_PINVAL21_Pos (21UL) /*!< PINVAL21 (Bit 21) */ +#define GPIO_PIN1_PINVAL21_Msk (0x200000UL) /*!< PINVAL21 (Bitfield-Mask: 0x01) */ +#define GPIO_PIN1_PINVAL22_Pos (22UL) /*!< PINVAL22 (Bit 22) */ +#define GPIO_PIN1_PINVAL22_Msk (0x400000UL) /*!< PINVAL22 (Bitfield-Mask: 0x01) */ +#define GPIO_PIN1_PINVAL23_Pos (23UL) /*!< PINVAL23 (Bit 23) */ +#define GPIO_PIN1_PINVAL23_Msk (0x800000UL) /*!< PINVAL23 (Bitfield-Mask: 0x01) */ +#define GPIO_PIN1_PINVAL24_Pos (24UL) /*!< PINVAL24 (Bit 24) */ +#define GPIO_PIN1_PINVAL24_Msk (0x1000000UL) /*!< PINVAL24 (Bitfield-Mask: 0x01) */ +#define GPIO_PIN1_PINVAL25_Pos (25UL) /*!< PINVAL25 (Bit 25) */ +#define GPIO_PIN1_PINVAL25_Msk (0x2000000UL) /*!< PINVAL25 (Bitfield-Mask: 0x01) */ +#define GPIO_PIN1_PINVAL26_Pos (26UL) /*!< PINVAL26 (Bit 26) */ +#define GPIO_PIN1_PINVAL26_Msk (0x4000000UL) /*!< PINVAL26 (Bitfield-Mask: 0x01) */ +#define GPIO_PIN1_PINVAL27_Pos (27UL) /*!< PINVAL27 (Bit 27) */ +#define GPIO_PIN1_PINVAL27_Msk (0x8000000UL) /*!< PINVAL27 (Bitfield-Mask: 0x01) */ +#define GPIO_PIN1_PINVAL28_Pos (28UL) /*!< PINVAL28 (Bit 28) */ +#define GPIO_PIN1_PINVAL28_Msk (0x10000000UL) /*!< PINVAL28 (Bitfield-Mask: 0x01) */ +#define GPIO_PIN1_PINVAL29_Pos (29UL) /*!< PINVAL29 (Bit 29) */ +#define GPIO_PIN1_PINVAL29_Msk (0x20000000UL) /*!< PINVAL29 (Bitfield-Mask: 0x01) */ +#define GPIO_PIN1_PINVAL30_Pos (30UL) /*!< PINVAL30 (Bit 30) */ +#define GPIO_PIN1_PINVAL30_Msk (0x40000000UL) /*!< PINVAL30 (Bitfield-Mask: 0x01) */ +#define GPIO_PIN1_PINVAL31_Pos (31UL) /*!< PINVAL31 (Bit 31) */ +#define GPIO_PIN1_PINVAL31_Msk (0x80000000UL) /*!< PINVAL31 (Bitfield-Mask: 0x01) */ +/* ========================================================= PIN2 ========================================================== */ +#define GPIO_PIN2_PINVAL0_Pos (0UL) /*!< PINVAL0 (Bit 0) */ +#define GPIO_PIN2_PINVAL0_Msk (0x1UL) /*!< PINVAL0 (Bitfield-Mask: 0x01) */ +#define GPIO_PIN2_PINVAL1_Pos (1UL) /*!< PINVAL1 (Bit 1) */ +#define GPIO_PIN2_PINVAL1_Msk (0x2UL) /*!< PINVAL1 (Bitfield-Mask: 0x01) */ +#define GPIO_PIN2_PINVAL2_Pos (2UL) /*!< PINVAL2 (Bit 2) */ +#define GPIO_PIN2_PINVAL2_Msk (0x4UL) /*!< PINVAL2 (Bitfield-Mask: 0x01) */ +#define GPIO_PIN2_PINVAL3_Pos (3UL) /*!< PINVAL3 (Bit 3) */ +#define GPIO_PIN2_PINVAL3_Msk (0x8UL) /*!< PINVAL3 (Bitfield-Mask: 0x01) */ +#define GPIO_PIN2_PINVAL4_Pos (4UL) /*!< PINVAL4 (Bit 4) */ +#define GPIO_PIN2_PINVAL4_Msk (0x10UL) /*!< PINVAL4 (Bitfield-Mask: 0x01) */ +#define GPIO_PIN2_PINVAL5_Pos (5UL) /*!< PINVAL5 (Bit 5) */ +#define GPIO_PIN2_PINVAL5_Msk (0x20UL) /*!< PINVAL5 (Bitfield-Mask: 0x01) */ +#define GPIO_PIN2_PINVAL6_Pos (6UL) /*!< PINVAL6 (Bit 6) */ +#define GPIO_PIN2_PINVAL6_Msk (0x40UL) /*!< PINVAL6 (Bitfield-Mask: 0x01) */ +#define GPIO_PIN2_PINVAL7_Pos (7UL) /*!< PINVAL7 (Bit 7) */ +#define GPIO_PIN2_PINVAL7_Msk (0x80UL) /*!< PINVAL7 (Bitfield-Mask: 0x01) */ +#define GPIO_PIN2_PINVAL8_Pos (8UL) /*!< PINVAL8 (Bit 8) */ +#define GPIO_PIN2_PINVAL8_Msk (0x100UL) /*!< PINVAL8 (Bitfield-Mask: 0x01) */ +#define GPIO_PIN2_PINVAL9_Pos (9UL) /*!< PINVAL9 (Bit 9) */ +#define GPIO_PIN2_PINVAL9_Msk (0x200UL) /*!< PINVAL9 (Bitfield-Mask: 0x01) */ +#define GPIO_PIN2_PINVAL10_Pos (10UL) /*!< PINVAL10 (Bit 10) */ +#define GPIO_PIN2_PINVAL10_Msk (0x400UL) /*!< PINVAL10 (Bitfield-Mask: 0x01) */ +#define GPIO_PIN2_PINVAL11_Pos (11UL) /*!< PINVAL11 (Bit 11) */ +#define GPIO_PIN2_PINVAL11_Msk (0x800UL) /*!< PINVAL11 (Bitfield-Mask: 0x01) */ +#define GPIO_PIN2_PINVAL12_Pos (12UL) /*!< PINVAL12 (Bit 12) */ +#define GPIO_PIN2_PINVAL12_Msk (0x1000UL) /*!< PINVAL12 (Bitfield-Mask: 0x01) */ +#define GPIO_PIN2_PINVAL13_Pos (13UL) /*!< PINVAL13 (Bit 13) */ +#define GPIO_PIN2_PINVAL13_Msk (0x2000UL) /*!< PINVAL13 (Bitfield-Mask: 0x01) */ +#define GPIO_PIN2_PINVAL14_Pos (14UL) /*!< PINVAL14 (Bit 14) */ +#define GPIO_PIN2_PINVAL14_Msk (0x4000UL) /*!< PINVAL14 (Bitfield-Mask: 0x01) */ +#define GPIO_PIN2_PINVAL15_Pos (15UL) /*!< PINVAL15 (Bit 15) */ +#define GPIO_PIN2_PINVAL15_Msk (0x8000UL) /*!< PINVAL15 (Bitfield-Mask: 0x01) */ +#define GPIO_PIN2_PINVAL16_Pos (16UL) /*!< PINVAL16 (Bit 16) */ +#define GPIO_PIN2_PINVAL16_Msk (0x10000UL) /*!< PINVAL16 (Bitfield-Mask: 0x01) */ +#define GPIO_PIN2_PINVAL17_Pos (17UL) /*!< PINVAL17 (Bit 17) */ +#define GPIO_PIN2_PINVAL17_Msk (0x20000UL) /*!< PINVAL17 (Bitfield-Mask: 0x01) */ +#define GPIO_PIN2_PINVAL18_Pos (18UL) /*!< PINVAL18 (Bit 18) */ +#define GPIO_PIN2_PINVAL18_Msk (0x40000UL) /*!< PINVAL18 (Bitfield-Mask: 0x01) */ +#define GPIO_PIN2_PINVAL19_Pos (19UL) /*!< PINVAL19 (Bit 19) */ +#define GPIO_PIN2_PINVAL19_Msk (0x80000UL) /*!< PINVAL19 (Bitfield-Mask: 0x01) */ +#define GPIO_PIN2_PINVAL20_Pos (20UL) /*!< PINVAL20 (Bit 20) */ +#define GPIO_PIN2_PINVAL20_Msk (0x100000UL) /*!< PINVAL20 (Bitfield-Mask: 0x01) */ +#define GPIO_PIN2_PINVAL21_Pos (21UL) /*!< PINVAL21 (Bit 21) */ +#define GPIO_PIN2_PINVAL21_Msk (0x200000UL) /*!< PINVAL21 (Bitfield-Mask: 0x01) */ +#define GPIO_PIN2_PINVAL22_Pos (22UL) /*!< PINVAL22 (Bit 22) */ +#define GPIO_PIN2_PINVAL22_Msk (0x400000UL) /*!< PINVAL22 (Bitfield-Mask: 0x01) */ +#define GPIO_PIN2_PINVAL23_Pos (23UL) /*!< PINVAL23 (Bit 23) */ +#define GPIO_PIN2_PINVAL23_Msk (0x800000UL) /*!< PINVAL23 (Bitfield-Mask: 0x01) */ +#define GPIO_PIN2_PINVAL24_Pos (24UL) /*!< PINVAL24 (Bit 24) */ +#define GPIO_PIN2_PINVAL24_Msk (0x1000000UL) /*!< PINVAL24 (Bitfield-Mask: 0x01) */ +#define GPIO_PIN2_PINVAL25_Pos (25UL) /*!< PINVAL25 (Bit 25) */ +#define GPIO_PIN2_PINVAL25_Msk (0x2000000UL) /*!< PINVAL25 (Bitfield-Mask: 0x01) */ +#define GPIO_PIN2_PINVAL26_Pos (26UL) /*!< PINVAL26 (Bit 26) */ +#define GPIO_PIN2_PINVAL26_Msk (0x4000000UL) /*!< PINVAL26 (Bitfield-Mask: 0x01) */ +#define GPIO_PIN2_PINVAL27_Pos (27UL) /*!< PINVAL27 (Bit 27) */ +#define GPIO_PIN2_PINVAL27_Msk (0x8000000UL) /*!< PINVAL27 (Bitfield-Mask: 0x01) */ +#define GPIO_PIN2_PINVAL28_Pos (28UL) /*!< PINVAL28 (Bit 28) */ +#define GPIO_PIN2_PINVAL28_Msk (0x10000000UL) /*!< PINVAL28 (Bitfield-Mask: 0x01) */ +#define GPIO_PIN2_PINVAL29_Pos (29UL) /*!< PINVAL29 (Bit 29) */ +#define GPIO_PIN2_PINVAL29_Msk (0x20000000UL) /*!< PINVAL29 (Bitfield-Mask: 0x01) */ +#define GPIO_PIN2_PINVAL30_Pos (30UL) /*!< PINVAL30 (Bit 30) */ +#define GPIO_PIN2_PINVAL30_Msk (0x40000000UL) /*!< PINVAL30 (Bitfield-Mask: 0x01) */ +#define GPIO_PIN2_PINVAL31_Pos (31UL) /*!< PINVAL31 (Bit 31) */ +#define GPIO_PIN2_PINVAL31_Msk (0x80000000UL) /*!< PINVAL31 (Bitfield-Mask: 0x01) */ +/* ========================================================= PIN3 ========================================================== */ +#define GPIO_PIN3_PINVAL0_Pos (0UL) /*!< PINVAL0 (Bit 0) */ +#define GPIO_PIN3_PINVAL0_Msk (0x1UL) /*!< PINVAL0 (Bitfield-Mask: 0x01) */ +#define GPIO_PIN3_PINVAL1_Pos (1UL) /*!< PINVAL1 (Bit 1) */ +#define GPIO_PIN3_PINVAL1_Msk (0x2UL) /*!< PINVAL1 (Bitfield-Mask: 0x01) */ +#define GPIO_PIN3_PINVAL2_Pos (2UL) /*!< PINVAL2 (Bit 2) */ +#define GPIO_PIN3_PINVAL2_Msk (0x4UL) /*!< PINVAL2 (Bitfield-Mask: 0x01) */ +#define GPIO_PIN3_PINVAL3_Pos (3UL) /*!< PINVAL3 (Bit 3) */ +#define GPIO_PIN3_PINVAL3_Msk (0x8UL) /*!< PINVAL3 (Bitfield-Mask: 0x01) */ +#define GPIO_PIN3_PINVAL4_Pos (4UL) /*!< PINVAL4 (Bit 4) */ +#define GPIO_PIN3_PINVAL4_Msk (0x10UL) /*!< PINVAL4 (Bitfield-Mask: 0x01) */ +#define GPIO_PIN3_PINVAL5_Pos (5UL) /*!< PINVAL5 (Bit 5) */ +#define GPIO_PIN3_PINVAL5_Msk (0x20UL) /*!< PINVAL5 (Bitfield-Mask: 0x01) */ +#define GPIO_PIN3_PINVAL6_Pos (6UL) /*!< PINVAL6 (Bit 6) */ +#define GPIO_PIN3_PINVAL6_Msk (0x40UL) /*!< PINVAL6 (Bitfield-Mask: 0x01) */ +#define GPIO_PIN3_PINVAL7_Pos (7UL) /*!< PINVAL7 (Bit 7) */ +#define GPIO_PIN3_PINVAL7_Msk (0x80UL) /*!< PINVAL7 (Bitfield-Mask: 0x01) */ +#define GPIO_PIN3_PINVAL8_Pos (8UL) /*!< PINVAL8 (Bit 8) */ +#define GPIO_PIN3_PINVAL8_Msk (0x100UL) /*!< PINVAL8 (Bitfield-Mask: 0x01) */ +#define GPIO_PIN3_PINVAL9_Pos (9UL) /*!< PINVAL9 (Bit 9) */ +#define GPIO_PIN3_PINVAL9_Msk (0x200UL) /*!< PINVAL9 (Bitfield-Mask: 0x01) */ +#define GPIO_PIN3_PINVAL10_Pos (10UL) /*!< PINVAL10 (Bit 10) */ +#define GPIO_PIN3_PINVAL10_Msk (0x400UL) /*!< PINVAL10 (Bitfield-Mask: 0x01) */ +#define GPIO_PIN3_PINVAL11_Pos (11UL) /*!< PINVAL11 (Bit 11) */ +#define GPIO_PIN3_PINVAL11_Msk (0x800UL) /*!< PINVAL11 (Bitfield-Mask: 0x01) */ +#define GPIO_PIN3_PINVAL12_Pos (12UL) /*!< PINVAL12 (Bit 12) */ +#define GPIO_PIN3_PINVAL12_Msk (0x1000UL) /*!< PINVAL12 (Bitfield-Mask: 0x01) */ +#define GPIO_PIN3_PINVAL13_Pos (13UL) /*!< PINVAL13 (Bit 13) */ +#define GPIO_PIN3_PINVAL13_Msk (0x2000UL) /*!< PINVAL13 (Bitfield-Mask: 0x01) */ +#define GPIO_PIN3_PINVAL14_Pos (14UL) /*!< PINVAL14 (Bit 14) */ +#define GPIO_PIN3_PINVAL14_Msk (0x4000UL) /*!< PINVAL14 (Bitfield-Mask: 0x01) */ +#define GPIO_PIN3_PINVAL15_Pos (15UL) /*!< PINVAL15 (Bit 15) */ +#define GPIO_PIN3_PINVAL15_Msk (0x8000UL) /*!< PINVAL15 (Bitfield-Mask: 0x01) */ +#define GPIO_PIN3_PINVAL16_Pos (16UL) /*!< PINVAL16 (Bit 16) */ +#define GPIO_PIN3_PINVAL16_Msk (0x10000UL) /*!< PINVAL16 (Bitfield-Mask: 0x01) */ +#define GPIO_PIN3_PINVAL17_Pos (17UL) /*!< PINVAL17 (Bit 17) */ +#define GPIO_PIN3_PINVAL17_Msk (0x20000UL) /*!< PINVAL17 (Bitfield-Mask: 0x01) */ +#define GPIO_PIN3_PINVAL18_Pos (18UL) /*!< PINVAL18 (Bit 18) */ +#define GPIO_PIN3_PINVAL18_Msk (0x40000UL) /*!< PINVAL18 (Bitfield-Mask: 0x01) */ +#define GPIO_PIN3_PINVAL19_Pos (19UL) /*!< PINVAL19 (Bit 19) */ +#define GPIO_PIN3_PINVAL19_Msk (0x80000UL) /*!< PINVAL19 (Bitfield-Mask: 0x01) */ +#define GPIO_PIN3_PINVAL20_Pos (20UL) /*!< PINVAL20 (Bit 20) */ +#define GPIO_PIN3_PINVAL20_Msk (0x100000UL) /*!< PINVAL20 (Bitfield-Mask: 0x01) */ +#define GPIO_PIN3_PINVAL21_Pos (21UL) /*!< PINVAL21 (Bit 21) */ +#define GPIO_PIN3_PINVAL21_Msk (0x200000UL) /*!< PINVAL21 (Bitfield-Mask: 0x01) */ +#define GPIO_PIN3_PINVAL22_Pos (22UL) /*!< PINVAL22 (Bit 22) */ +#define GPIO_PIN3_PINVAL22_Msk (0x400000UL) /*!< PINVAL22 (Bitfield-Mask: 0x01) */ +#define GPIO_PIN3_PINVAL23_Pos (23UL) /*!< PINVAL23 (Bit 23) */ +#define GPIO_PIN3_PINVAL23_Msk (0x800000UL) /*!< PINVAL23 (Bitfield-Mask: 0x01) */ +#define GPIO_PIN3_PINVAL24_Pos (24UL) /*!< PINVAL24 (Bit 24) */ +#define GPIO_PIN3_PINVAL24_Msk (0x1000000UL) /*!< PINVAL24 (Bitfield-Mask: 0x01) */ +#define GPIO_PIN3_PINVAL25_Pos (25UL) /*!< PINVAL25 (Bit 25) */ +#define GPIO_PIN3_PINVAL25_Msk (0x2000000UL) /*!< PINVAL25 (Bitfield-Mask: 0x01) */ +#define GPIO_PIN3_PINVAL26_Pos (26UL) /*!< PINVAL26 (Bit 26) */ +#define GPIO_PIN3_PINVAL26_Msk (0x4000000UL) /*!< PINVAL26 (Bitfield-Mask: 0x01) */ +#define GPIO_PIN3_PINVAL27_Pos (27UL) /*!< PINVAL27 (Bit 27) */ +#define GPIO_PIN3_PINVAL27_Msk (0x8000000UL) /*!< PINVAL27 (Bitfield-Mask: 0x01) */ +#define GPIO_PIN3_PINVAL28_Pos (28UL) /*!< PINVAL28 (Bit 28) */ +#define GPIO_PIN3_PINVAL28_Msk (0x10000000UL) /*!< PINVAL28 (Bitfield-Mask: 0x01) */ +#define GPIO_PIN3_PINVAL29_Pos (29UL) /*!< PINVAL29 (Bit 29) */ +#define GPIO_PIN3_PINVAL29_Msk (0x20000000UL) /*!< PINVAL29 (Bitfield-Mask: 0x01) */ +#define GPIO_PIN3_PINVAL30_Pos (30UL) /*!< PINVAL30 (Bit 30) */ +#define GPIO_PIN3_PINVAL30_Msk (0x40000000UL) /*!< PINVAL30 (Bitfield-Mask: 0x01) */ +#define GPIO_PIN3_PINVAL31_Pos (31UL) /*!< PINVAL31 (Bit 31) */ +#define GPIO_PIN3_PINVAL31_Msk (0x80000000UL) /*!< PINVAL31 (Bitfield-Mask: 0x01) */ +/* ========================================================= PIN4 ========================================================== */ +#define GPIO_PIN4_PINVAL0_Pos (0UL) /*!< PINVAL0 (Bit 0) */ +#define GPIO_PIN4_PINVAL0_Msk (0x1UL) /*!< PINVAL0 (Bitfield-Mask: 0x01) */ +#define GPIO_PIN4_PINVAL1_Pos (1UL) /*!< PINVAL1 (Bit 1) */ +#define GPIO_PIN4_PINVAL1_Msk (0x2UL) /*!< PINVAL1 (Bitfield-Mask: 0x01) */ +#define GPIO_PIN4_PINVAL2_Pos (2UL) /*!< PINVAL2 (Bit 2) */ +#define GPIO_PIN4_PINVAL2_Msk (0x4UL) /*!< PINVAL2 (Bitfield-Mask: 0x01) */ +#define GPIO_PIN4_PINVAL3_Pos (3UL) /*!< PINVAL3 (Bit 3) */ +#define GPIO_PIN4_PINVAL3_Msk (0x8UL) /*!< PINVAL3 (Bitfield-Mask: 0x01) */ +#define GPIO_PIN4_PINVAL4_Pos (4UL) /*!< PINVAL4 (Bit 4) */ +#define GPIO_PIN4_PINVAL4_Msk (0x10UL) /*!< PINVAL4 (Bitfield-Mask: 0x01) */ +#define GPIO_PIN4_PINVAL5_Pos (5UL) /*!< PINVAL5 (Bit 5) */ +#define GPIO_PIN4_PINVAL5_Msk (0x20UL) /*!< PINVAL5 (Bitfield-Mask: 0x01) */ +#define GPIO_PIN4_PINVAL6_Pos (6UL) /*!< PINVAL6 (Bit 6) */ +#define GPIO_PIN4_PINVAL6_Msk (0x40UL) /*!< PINVAL6 (Bitfield-Mask: 0x01) */ +#define GPIO_PIN4_PINVAL7_Pos (7UL) /*!< PINVAL7 (Bit 7) */ +#define GPIO_PIN4_PINVAL7_Msk (0x80UL) /*!< PINVAL7 (Bitfield-Mask: 0x01) */ +#define GPIO_PIN4_PINVAL8_Pos (8UL) /*!< PINVAL8 (Bit 8) */ +#define GPIO_PIN4_PINVAL8_Msk (0x100UL) /*!< PINVAL8 (Bitfield-Mask: 0x01) */ +#define GPIO_PIN4_PINVAL9_Pos (9UL) /*!< PINVAL9 (Bit 9) */ +#define GPIO_PIN4_PINVAL9_Msk (0x200UL) /*!< PINVAL9 (Bitfield-Mask: 0x01) */ +#define GPIO_PIN4_PINVAL10_Pos (10UL) /*!< PINVAL10 (Bit 10) */ +#define GPIO_PIN4_PINVAL10_Msk (0x400UL) /*!< PINVAL10 (Bitfield-Mask: 0x01) */ +#define GPIO_PIN4_PINVAL11_Pos (11UL) /*!< PINVAL11 (Bit 11) */ +#define GPIO_PIN4_PINVAL11_Msk (0x800UL) /*!< PINVAL11 (Bitfield-Mask: 0x01) */ +#define GPIO_PIN4_PINVAL12_Pos (12UL) /*!< PINVAL12 (Bit 12) */ +#define GPIO_PIN4_PINVAL12_Msk (0x1000UL) /*!< PINVAL12 (Bitfield-Mask: 0x01) */ +#define GPIO_PIN4_PINVAL13_Pos (13UL) /*!< PINVAL13 (Bit 13) */ +#define GPIO_PIN4_PINVAL13_Msk (0x2000UL) /*!< PINVAL13 (Bitfield-Mask: 0x01) */ +#define GPIO_PIN4_PINVAL14_Pos (14UL) /*!< PINVAL14 (Bit 14) */ +#define GPIO_PIN4_PINVAL14_Msk (0x4000UL) /*!< PINVAL14 (Bitfield-Mask: 0x01) */ +#define GPIO_PIN4_PINVAL15_Pos (15UL) /*!< PINVAL15 (Bit 15) */ +#define GPIO_PIN4_PINVAL15_Msk (0x8000UL) /*!< PINVAL15 (Bitfield-Mask: 0x01) */ +#define GPIO_PIN4_PINVAL16_Pos (16UL) /*!< PINVAL16 (Bit 16) */ +#define GPIO_PIN4_PINVAL16_Msk (0x10000UL) /*!< PINVAL16 (Bitfield-Mask: 0x01) */ +#define GPIO_PIN4_PINVAL17_Pos (17UL) /*!< PINVAL17 (Bit 17) */ +#define GPIO_PIN4_PINVAL17_Msk (0x20000UL) /*!< PINVAL17 (Bitfield-Mask: 0x01) */ +#define GPIO_PIN4_PINVAL18_Pos (18UL) /*!< PINVAL18 (Bit 18) */ +#define GPIO_PIN4_PINVAL18_Msk (0x40000UL) /*!< PINVAL18 (Bitfield-Mask: 0x01) */ +#define GPIO_PIN4_PINVAL19_Pos (19UL) /*!< PINVAL19 (Bit 19) */ +#define GPIO_PIN4_PINVAL19_Msk (0x80000UL) /*!< PINVAL19 (Bitfield-Mask: 0x01) */ +#define GPIO_PIN4_PINVAL20_Pos (20UL) /*!< PINVAL20 (Bit 20) */ +#define GPIO_PIN4_PINVAL20_Msk (0x100000UL) /*!< PINVAL20 (Bitfield-Mask: 0x01) */ +#define GPIO_PIN4_PINVAL21_Pos (21UL) /*!< PINVAL21 (Bit 21) */ +#define GPIO_PIN4_PINVAL21_Msk (0x200000UL) /*!< PINVAL21 (Bitfield-Mask: 0x01) */ +#define GPIO_PIN4_PINVAL22_Pos (22UL) /*!< PINVAL22 (Bit 22) */ +#define GPIO_PIN4_PINVAL22_Msk (0x400000UL) /*!< PINVAL22 (Bitfield-Mask: 0x01) */ +#define GPIO_PIN4_PINVAL23_Pos (23UL) /*!< PINVAL23 (Bit 23) */ +#define GPIO_PIN4_PINVAL23_Msk (0x800000UL) /*!< PINVAL23 (Bitfield-Mask: 0x01) */ +#define GPIO_PIN4_PINVAL24_Pos (24UL) /*!< PINVAL24 (Bit 24) */ +#define GPIO_PIN4_PINVAL24_Msk (0x1000000UL) /*!< PINVAL24 (Bitfield-Mask: 0x01) */ +#define GPIO_PIN4_PINVAL25_Pos (25UL) /*!< PINVAL25 (Bit 25) */ +#define GPIO_PIN4_PINVAL25_Msk (0x2000000UL) /*!< PINVAL25 (Bitfield-Mask: 0x01) */ +#define GPIO_PIN4_PINVAL26_Pos (26UL) /*!< PINVAL26 (Bit 26) */ +#define GPIO_PIN4_PINVAL26_Msk (0x4000000UL) /*!< PINVAL26 (Bitfield-Mask: 0x01) */ +#define GPIO_PIN4_PINVAL27_Pos (27UL) /*!< PINVAL27 (Bit 27) */ +#define GPIO_PIN4_PINVAL27_Msk (0x8000000UL) /*!< PINVAL27 (Bitfield-Mask: 0x01) */ +#define GPIO_PIN4_PINVAL28_Pos (28UL) /*!< PINVAL28 (Bit 28) */ +#define GPIO_PIN4_PINVAL28_Msk (0x10000000UL) /*!< PINVAL28 (Bitfield-Mask: 0x01) */ +#define GPIO_PIN4_PINVAL29_Pos (29UL) /*!< PINVAL29 (Bit 29) */ +#define GPIO_PIN4_PINVAL29_Msk (0x20000000UL) /*!< PINVAL29 (Bitfield-Mask: 0x01) */ +#define GPIO_PIN4_PINVAL30_Pos (30UL) /*!< PINVAL30 (Bit 30) */ +#define GPIO_PIN4_PINVAL30_Msk (0x40000000UL) /*!< PINVAL30 (Bitfield-Mask: 0x01) */ +#define GPIO_PIN4_PINVAL31_Pos (31UL) /*!< PINVAL31 (Bit 31) */ +#define GPIO_PIN4_PINVAL31_Msk (0x80000000UL) /*!< PINVAL31 (Bitfield-Mask: 0x01) */ +/* ========================================================= SET0 ========================================================== */ +#define GPIO_SET0_PINSET0_Pos (0UL) /*!< PINSET0 (Bit 0) */ +#define GPIO_SET0_PINSET0_Msk (0x1UL) /*!< PINSET0 (Bitfield-Mask: 0x01) */ +#define GPIO_SET0_PINSET1_Pos (1UL) /*!< PINSET1 (Bit 1) */ +#define GPIO_SET0_PINSET1_Msk (0x2UL) /*!< PINSET1 (Bitfield-Mask: 0x01) */ +#define GPIO_SET0_PINSET2_Pos (2UL) /*!< PINSET2 (Bit 2) */ +#define GPIO_SET0_PINSET2_Msk (0x4UL) /*!< PINSET2 (Bitfield-Mask: 0x01) */ +#define GPIO_SET0_PINSET3_Pos (3UL) /*!< PINSET3 (Bit 3) */ +#define GPIO_SET0_PINSET3_Msk (0x8UL) /*!< PINSET3 (Bitfield-Mask: 0x01) */ +#define GPIO_SET0_PINSET4_Pos (4UL) /*!< PINSET4 (Bit 4) */ +#define GPIO_SET0_PINSET4_Msk (0x10UL) /*!< PINSET4 (Bitfield-Mask: 0x01) */ +#define GPIO_SET0_PINSET5_Pos (5UL) /*!< PINSET5 (Bit 5) */ +#define GPIO_SET0_PINSET5_Msk (0x20UL) /*!< PINSET5 (Bitfield-Mask: 0x01) */ +#define GPIO_SET0_PINSET6_Pos (6UL) /*!< PINSET6 (Bit 6) */ +#define GPIO_SET0_PINSET6_Msk (0x40UL) /*!< PINSET6 (Bitfield-Mask: 0x01) */ +#define GPIO_SET0_PINSET7_Pos (7UL) /*!< PINSET7 (Bit 7) */ +#define GPIO_SET0_PINSET7_Msk (0x80UL) /*!< PINSET7 (Bitfield-Mask: 0x01) */ +#define GPIO_SET0_PINSET8_Pos (8UL) /*!< PINSET8 (Bit 8) */ +#define GPIO_SET0_PINSET8_Msk (0x100UL) /*!< PINSET8 (Bitfield-Mask: 0x01) */ +#define GPIO_SET0_PINSET9_Pos (9UL) /*!< PINSET9 (Bit 9) */ +#define GPIO_SET0_PINSET9_Msk (0x200UL) /*!< PINSET9 (Bitfield-Mask: 0x01) */ +#define GPIO_SET0_PINSET10_Pos (10UL) /*!< PINSET10 (Bit 10) */ +#define GPIO_SET0_PINSET10_Msk (0x400UL) /*!< PINSET10 (Bitfield-Mask: 0x01) */ +#define GPIO_SET0_PINSET11_Pos (11UL) /*!< PINSET11 (Bit 11) */ +#define GPIO_SET0_PINSET11_Msk (0x800UL) /*!< PINSET11 (Bitfield-Mask: 0x01) */ +#define GPIO_SET0_PINSET12_Pos (12UL) /*!< PINSET12 (Bit 12) */ +#define GPIO_SET0_PINSET12_Msk (0x1000UL) /*!< PINSET12 (Bitfield-Mask: 0x01) */ +#define GPIO_SET0_PINSET13_Pos (13UL) /*!< PINSET13 (Bit 13) */ +#define GPIO_SET0_PINSET13_Msk (0x2000UL) /*!< PINSET13 (Bitfield-Mask: 0x01) */ +#define GPIO_SET0_PINSET14_Pos (14UL) /*!< PINSET14 (Bit 14) */ +#define GPIO_SET0_PINSET14_Msk (0x4000UL) /*!< PINSET14 (Bitfield-Mask: 0x01) */ +#define GPIO_SET0_PINSET15_Pos (15UL) /*!< PINSET15 (Bit 15) */ +#define GPIO_SET0_PINSET15_Msk (0x8000UL) /*!< PINSET15 (Bitfield-Mask: 0x01) */ +#define GPIO_SET0_PINSET16_Pos (16UL) /*!< PINSET16 (Bit 16) */ +#define GPIO_SET0_PINSET16_Msk (0x10000UL) /*!< PINSET16 (Bitfield-Mask: 0x01) */ +#define GPIO_SET0_PINSET17_Pos (17UL) /*!< PINSET17 (Bit 17) */ +#define GPIO_SET0_PINSET17_Msk (0x20000UL) /*!< PINSET17 (Bitfield-Mask: 0x01) */ +#define GPIO_SET0_PINSET18_Pos (18UL) /*!< PINSET18 (Bit 18) */ +#define GPIO_SET0_PINSET18_Msk (0x40000UL) /*!< PINSET18 (Bitfield-Mask: 0x01) */ +#define GPIO_SET0_PINSET19_Pos (19UL) /*!< PINSET19 (Bit 19) */ +#define GPIO_SET0_PINSET19_Msk (0x80000UL) /*!< PINSET19 (Bitfield-Mask: 0x01) */ +#define GPIO_SET0_PINSET20_Pos (20UL) /*!< PINSET20 (Bit 20) */ +#define GPIO_SET0_PINSET20_Msk (0x100000UL) /*!< PINSET20 (Bitfield-Mask: 0x01) */ +#define GPIO_SET0_PINSET21_Pos (21UL) /*!< PINSET21 (Bit 21) */ +#define GPIO_SET0_PINSET21_Msk (0x200000UL) /*!< PINSET21 (Bitfield-Mask: 0x01) */ +#define GPIO_SET0_PINSET22_Pos (22UL) /*!< PINSET22 (Bit 22) */ +#define GPIO_SET0_PINSET22_Msk (0x400000UL) /*!< PINSET22 (Bitfield-Mask: 0x01) */ +#define GPIO_SET0_PINSET23_Pos (23UL) /*!< PINSET23 (Bit 23) */ +#define GPIO_SET0_PINSET23_Msk (0x800000UL) /*!< PINSET23 (Bitfield-Mask: 0x01) */ +#define GPIO_SET0_PINSET24_Pos (24UL) /*!< PINSET24 (Bit 24) */ +#define GPIO_SET0_PINSET24_Msk (0x1000000UL) /*!< PINSET24 (Bitfield-Mask: 0x01) */ +#define GPIO_SET0_PINSET25_Pos (25UL) /*!< PINSET25 (Bit 25) */ +#define GPIO_SET0_PINSET25_Msk (0x2000000UL) /*!< PINSET25 (Bitfield-Mask: 0x01) */ +#define GPIO_SET0_PINSET26_Pos (26UL) /*!< PINSET26 (Bit 26) */ +#define GPIO_SET0_PINSET26_Msk (0x4000000UL) /*!< PINSET26 (Bitfield-Mask: 0x01) */ +#define GPIO_SET0_PINSET27_Pos (27UL) /*!< PINSET27 (Bit 27) */ +#define GPIO_SET0_PINSET27_Msk (0x8000000UL) /*!< PINSET27 (Bitfield-Mask: 0x01) */ +#define GPIO_SET0_PINSET28_Pos (28UL) /*!< PINSET28 (Bit 28) */ +#define GPIO_SET0_PINSET28_Msk (0x10000000UL) /*!< PINSET28 (Bitfield-Mask: 0x01) */ +#define GPIO_SET0_PINSET29_Pos (29UL) /*!< PINSET29 (Bit 29) */ +#define GPIO_SET0_PINSET29_Msk (0x20000000UL) /*!< PINSET29 (Bitfield-Mask: 0x01) */ +#define GPIO_SET0_PINSET30_Pos (30UL) /*!< PINSET30 (Bit 30) */ +#define GPIO_SET0_PINSET30_Msk (0x40000000UL) /*!< PINSET30 (Bitfield-Mask: 0x01) */ +#define GPIO_SET0_PINSET31_Pos (31UL) /*!< PINSET31 (Bit 31) */ +#define GPIO_SET0_PINSET31_Msk (0x80000000UL) /*!< PINSET31 (Bitfield-Mask: 0x01) */ +/* ========================================================= SET1 ========================================================== */ +#define GPIO_SET1_PINSET0_Pos (0UL) /*!< PINSET0 (Bit 0) */ +#define GPIO_SET1_PINSET0_Msk (0x1UL) /*!< PINSET0 (Bitfield-Mask: 0x01) */ +#define GPIO_SET1_PINSET1_Pos (1UL) /*!< PINSET1 (Bit 1) */ +#define GPIO_SET1_PINSET1_Msk (0x2UL) /*!< PINSET1 (Bitfield-Mask: 0x01) */ +#define GPIO_SET1_PINSET2_Pos (2UL) /*!< PINSET2 (Bit 2) */ +#define GPIO_SET1_PINSET2_Msk (0x4UL) /*!< PINSET2 (Bitfield-Mask: 0x01) */ +#define GPIO_SET1_PINSET3_Pos (3UL) /*!< PINSET3 (Bit 3) */ +#define GPIO_SET1_PINSET3_Msk (0x8UL) /*!< PINSET3 (Bitfield-Mask: 0x01) */ +#define GPIO_SET1_PINSET4_Pos (4UL) /*!< PINSET4 (Bit 4) */ +#define GPIO_SET1_PINSET4_Msk (0x10UL) /*!< PINSET4 (Bitfield-Mask: 0x01) */ +#define GPIO_SET1_PINSET5_Pos (5UL) /*!< PINSET5 (Bit 5) */ +#define GPIO_SET1_PINSET5_Msk (0x20UL) /*!< PINSET5 (Bitfield-Mask: 0x01) */ +#define GPIO_SET1_PINSET6_Pos (6UL) /*!< PINSET6 (Bit 6) */ +#define GPIO_SET1_PINSET6_Msk (0x40UL) /*!< PINSET6 (Bitfield-Mask: 0x01) */ +#define GPIO_SET1_PINSET7_Pos (7UL) /*!< PINSET7 (Bit 7) */ +#define GPIO_SET1_PINSET7_Msk (0x80UL) /*!< PINSET7 (Bitfield-Mask: 0x01) */ +#define GPIO_SET1_PINSET8_Pos (8UL) /*!< PINSET8 (Bit 8) */ +#define GPIO_SET1_PINSET8_Msk (0x100UL) /*!< PINSET8 (Bitfield-Mask: 0x01) */ +#define GPIO_SET1_PINSET9_Pos (9UL) /*!< PINSET9 (Bit 9) */ +#define GPIO_SET1_PINSET9_Msk (0x200UL) /*!< PINSET9 (Bitfield-Mask: 0x01) */ +#define GPIO_SET1_PINSET10_Pos (10UL) /*!< PINSET10 (Bit 10) */ +#define GPIO_SET1_PINSET10_Msk (0x400UL) /*!< PINSET10 (Bitfield-Mask: 0x01) */ +#define GPIO_SET1_PINSET11_Pos (11UL) /*!< PINSET11 (Bit 11) */ +#define GPIO_SET1_PINSET11_Msk (0x800UL) /*!< PINSET11 (Bitfield-Mask: 0x01) */ +#define GPIO_SET1_PINSET12_Pos (12UL) /*!< PINSET12 (Bit 12) */ +#define GPIO_SET1_PINSET12_Msk (0x1000UL) /*!< PINSET12 (Bitfield-Mask: 0x01) */ +#define GPIO_SET1_PINSET13_Pos (13UL) /*!< PINSET13 (Bit 13) */ +#define GPIO_SET1_PINSET13_Msk (0x2000UL) /*!< PINSET13 (Bitfield-Mask: 0x01) */ +#define GPIO_SET1_PINSET14_Pos (14UL) /*!< PINSET14 (Bit 14) */ +#define GPIO_SET1_PINSET14_Msk (0x4000UL) /*!< PINSET14 (Bitfield-Mask: 0x01) */ +#define GPIO_SET1_PINSET15_Pos (15UL) /*!< PINSET15 (Bit 15) */ +#define GPIO_SET1_PINSET15_Msk (0x8000UL) /*!< PINSET15 (Bitfield-Mask: 0x01) */ +#define GPIO_SET1_PINSET16_Pos (16UL) /*!< PINSET16 (Bit 16) */ +#define GPIO_SET1_PINSET16_Msk (0x10000UL) /*!< PINSET16 (Bitfield-Mask: 0x01) */ +#define GPIO_SET1_PINSET17_Pos (17UL) /*!< PINSET17 (Bit 17) */ +#define GPIO_SET1_PINSET17_Msk (0x20000UL) /*!< PINSET17 (Bitfield-Mask: 0x01) */ +#define GPIO_SET1_PINSET18_Pos (18UL) /*!< PINSET18 (Bit 18) */ +#define GPIO_SET1_PINSET18_Msk (0x40000UL) /*!< PINSET18 (Bitfield-Mask: 0x01) */ +#define GPIO_SET1_PINSET19_Pos (19UL) /*!< PINSET19 (Bit 19) */ +#define GPIO_SET1_PINSET19_Msk (0x80000UL) /*!< PINSET19 (Bitfield-Mask: 0x01) */ +#define GPIO_SET1_PINSET20_Pos (20UL) /*!< PINSET20 (Bit 20) */ +#define GPIO_SET1_PINSET20_Msk (0x100000UL) /*!< PINSET20 (Bitfield-Mask: 0x01) */ +#define GPIO_SET1_PINSET21_Pos (21UL) /*!< PINSET21 (Bit 21) */ +#define GPIO_SET1_PINSET21_Msk (0x200000UL) /*!< PINSET21 (Bitfield-Mask: 0x01) */ +#define GPIO_SET1_PINSET22_Pos (22UL) /*!< PINSET22 (Bit 22) */ +#define GPIO_SET1_PINSET22_Msk (0x400000UL) /*!< PINSET22 (Bitfield-Mask: 0x01) */ +#define GPIO_SET1_PINSET23_Pos (23UL) /*!< PINSET23 (Bit 23) */ +#define GPIO_SET1_PINSET23_Msk (0x800000UL) /*!< PINSET23 (Bitfield-Mask: 0x01) */ +#define GPIO_SET1_PINSET24_Pos (24UL) /*!< PINSET24 (Bit 24) */ +#define GPIO_SET1_PINSET24_Msk (0x1000000UL) /*!< PINSET24 (Bitfield-Mask: 0x01) */ +#define GPIO_SET1_PINSET25_Pos (25UL) /*!< PINSET25 (Bit 25) */ +#define GPIO_SET1_PINSET25_Msk (0x2000000UL) /*!< PINSET25 (Bitfield-Mask: 0x01) */ +#define GPIO_SET1_PINSET26_Pos (26UL) /*!< PINSET26 (Bit 26) */ +#define GPIO_SET1_PINSET26_Msk (0x4000000UL) /*!< PINSET26 (Bitfield-Mask: 0x01) */ +#define GPIO_SET1_PINSET27_Pos (27UL) /*!< PINSET27 (Bit 27) */ +#define GPIO_SET1_PINSET27_Msk (0x8000000UL) /*!< PINSET27 (Bitfield-Mask: 0x01) */ +#define GPIO_SET1_PINSET28_Pos (28UL) /*!< PINSET28 (Bit 28) */ +#define GPIO_SET1_PINSET28_Msk (0x10000000UL) /*!< PINSET28 (Bitfield-Mask: 0x01) */ +#define GPIO_SET1_PINSET29_Pos (29UL) /*!< PINSET29 (Bit 29) */ +#define GPIO_SET1_PINSET29_Msk (0x20000000UL) /*!< PINSET29 (Bitfield-Mask: 0x01) */ +#define GPIO_SET1_PINSET30_Pos (30UL) /*!< PINSET30 (Bit 30) */ +#define GPIO_SET1_PINSET30_Msk (0x40000000UL) /*!< PINSET30 (Bitfield-Mask: 0x01) */ +#define GPIO_SET1_PINSET31_Pos (31UL) /*!< PINSET31 (Bit 31) */ +#define GPIO_SET1_PINSET31_Msk (0x80000000UL) /*!< PINSET31 (Bitfield-Mask: 0x01) */ +/* ========================================================= SET2 ========================================================== */ +#define GPIO_SET2_PINSET0_Pos (0UL) /*!< PINSET0 (Bit 0) */ +#define GPIO_SET2_PINSET0_Msk (0x1UL) /*!< PINSET0 (Bitfield-Mask: 0x01) */ +#define GPIO_SET2_PINSET1_Pos (1UL) /*!< PINSET1 (Bit 1) */ +#define GPIO_SET2_PINSET1_Msk (0x2UL) /*!< PINSET1 (Bitfield-Mask: 0x01) */ +#define GPIO_SET2_PINSET2_Pos (2UL) /*!< PINSET2 (Bit 2) */ +#define GPIO_SET2_PINSET2_Msk (0x4UL) /*!< PINSET2 (Bitfield-Mask: 0x01) */ +#define GPIO_SET2_PINSET3_Pos (3UL) /*!< PINSET3 (Bit 3) */ +#define GPIO_SET2_PINSET3_Msk (0x8UL) /*!< PINSET3 (Bitfield-Mask: 0x01) */ +#define GPIO_SET2_PINSET4_Pos (4UL) /*!< PINSET4 (Bit 4) */ +#define GPIO_SET2_PINSET4_Msk (0x10UL) /*!< PINSET4 (Bitfield-Mask: 0x01) */ +#define GPIO_SET2_PINSET5_Pos (5UL) /*!< PINSET5 (Bit 5) */ +#define GPIO_SET2_PINSET5_Msk (0x20UL) /*!< PINSET5 (Bitfield-Mask: 0x01) */ +#define GPIO_SET2_PINSET6_Pos (6UL) /*!< PINSET6 (Bit 6) */ +#define GPIO_SET2_PINSET6_Msk (0x40UL) /*!< PINSET6 (Bitfield-Mask: 0x01) */ +#define GPIO_SET2_PINSET7_Pos (7UL) /*!< PINSET7 (Bit 7) */ +#define GPIO_SET2_PINSET7_Msk (0x80UL) /*!< PINSET7 (Bitfield-Mask: 0x01) */ +#define GPIO_SET2_PINSET8_Pos (8UL) /*!< PINSET8 (Bit 8) */ +#define GPIO_SET2_PINSET8_Msk (0x100UL) /*!< PINSET8 (Bitfield-Mask: 0x01) */ +#define GPIO_SET2_PINSET9_Pos (9UL) /*!< PINSET9 (Bit 9) */ +#define GPIO_SET2_PINSET9_Msk (0x200UL) /*!< PINSET9 (Bitfield-Mask: 0x01) */ +#define GPIO_SET2_PINSET10_Pos (10UL) /*!< PINSET10 (Bit 10) */ +#define GPIO_SET2_PINSET10_Msk (0x400UL) /*!< PINSET10 (Bitfield-Mask: 0x01) */ +#define GPIO_SET2_PINSET11_Pos (11UL) /*!< PINSET11 (Bit 11) */ +#define GPIO_SET2_PINSET11_Msk (0x800UL) /*!< PINSET11 (Bitfield-Mask: 0x01) */ +#define GPIO_SET2_PINSET12_Pos (12UL) /*!< PINSET12 (Bit 12) */ +#define GPIO_SET2_PINSET12_Msk (0x1000UL) /*!< PINSET12 (Bitfield-Mask: 0x01) */ +#define GPIO_SET2_PINSET13_Pos (13UL) /*!< PINSET13 (Bit 13) */ +#define GPIO_SET2_PINSET13_Msk (0x2000UL) /*!< PINSET13 (Bitfield-Mask: 0x01) */ +#define GPIO_SET2_PINSET14_Pos (14UL) /*!< PINSET14 (Bit 14) */ +#define GPIO_SET2_PINSET14_Msk (0x4000UL) /*!< PINSET14 (Bitfield-Mask: 0x01) */ +#define GPIO_SET2_PINSET15_Pos (15UL) /*!< PINSET15 (Bit 15) */ +#define GPIO_SET2_PINSET15_Msk (0x8000UL) /*!< PINSET15 (Bitfield-Mask: 0x01) */ +#define GPIO_SET2_PINSET16_Pos (16UL) /*!< PINSET16 (Bit 16) */ +#define GPIO_SET2_PINSET16_Msk (0x10000UL) /*!< PINSET16 (Bitfield-Mask: 0x01) */ +#define GPIO_SET2_PINSET17_Pos (17UL) /*!< PINSET17 (Bit 17) */ +#define GPIO_SET2_PINSET17_Msk (0x20000UL) /*!< PINSET17 (Bitfield-Mask: 0x01) */ +#define GPIO_SET2_PINSET18_Pos (18UL) /*!< PINSET18 (Bit 18) */ +#define GPIO_SET2_PINSET18_Msk (0x40000UL) /*!< PINSET18 (Bitfield-Mask: 0x01) */ +#define GPIO_SET2_PINSET19_Pos (19UL) /*!< PINSET19 (Bit 19) */ +#define GPIO_SET2_PINSET19_Msk (0x80000UL) /*!< PINSET19 (Bitfield-Mask: 0x01) */ +#define GPIO_SET2_PINSET20_Pos (20UL) /*!< PINSET20 (Bit 20) */ +#define GPIO_SET2_PINSET20_Msk (0x100000UL) /*!< PINSET20 (Bitfield-Mask: 0x01) */ +#define GPIO_SET2_PINSET21_Pos (21UL) /*!< PINSET21 (Bit 21) */ +#define GPIO_SET2_PINSET21_Msk (0x200000UL) /*!< PINSET21 (Bitfield-Mask: 0x01) */ +#define GPIO_SET2_PINSET22_Pos (22UL) /*!< PINSET22 (Bit 22) */ +#define GPIO_SET2_PINSET22_Msk (0x400000UL) /*!< PINSET22 (Bitfield-Mask: 0x01) */ +#define GPIO_SET2_PINSET23_Pos (23UL) /*!< PINSET23 (Bit 23) */ +#define GPIO_SET2_PINSET23_Msk (0x800000UL) /*!< PINSET23 (Bitfield-Mask: 0x01) */ +#define GPIO_SET2_PINSET24_Pos (24UL) /*!< PINSET24 (Bit 24) */ +#define GPIO_SET2_PINSET24_Msk (0x1000000UL) /*!< PINSET24 (Bitfield-Mask: 0x01) */ +#define GPIO_SET2_PINSET25_Pos (25UL) /*!< PINSET25 (Bit 25) */ +#define GPIO_SET2_PINSET25_Msk (0x2000000UL) /*!< PINSET25 (Bitfield-Mask: 0x01) */ +#define GPIO_SET2_PINSET26_Pos (26UL) /*!< PINSET26 (Bit 26) */ +#define GPIO_SET2_PINSET26_Msk (0x4000000UL) /*!< PINSET26 (Bitfield-Mask: 0x01) */ +#define GPIO_SET2_PINSET27_Pos (27UL) /*!< PINSET27 (Bit 27) */ +#define GPIO_SET2_PINSET27_Msk (0x8000000UL) /*!< PINSET27 (Bitfield-Mask: 0x01) */ +#define GPIO_SET2_PINSET28_Pos (28UL) /*!< PINSET28 (Bit 28) */ +#define GPIO_SET2_PINSET28_Msk (0x10000000UL) /*!< PINSET28 (Bitfield-Mask: 0x01) */ +#define GPIO_SET2_PINSET29_Pos (29UL) /*!< PINSET29 (Bit 29) */ +#define GPIO_SET2_PINSET29_Msk (0x20000000UL) /*!< PINSET29 (Bitfield-Mask: 0x01) */ +#define GPIO_SET2_PINSET30_Pos (30UL) /*!< PINSET30 (Bit 30) */ +#define GPIO_SET2_PINSET30_Msk (0x40000000UL) /*!< PINSET30 (Bitfield-Mask: 0x01) */ +#define GPIO_SET2_PINSET31_Pos (31UL) /*!< PINSET31 (Bit 31) */ +#define GPIO_SET2_PINSET31_Msk (0x80000000UL) /*!< PINSET31 (Bitfield-Mask: 0x01) */ +/* ========================================================= SET3 ========================================================== */ +#define GPIO_SET3_PINSET0_Pos (0UL) /*!< PINSET0 (Bit 0) */ +#define GPIO_SET3_PINSET0_Msk (0x1UL) /*!< PINSET0 (Bitfield-Mask: 0x01) */ +#define GPIO_SET3_PINSET1_Pos (1UL) /*!< PINSET1 (Bit 1) */ +#define GPIO_SET3_PINSET1_Msk (0x2UL) /*!< PINSET1 (Bitfield-Mask: 0x01) */ +#define GPIO_SET3_PINSET2_Pos (2UL) /*!< PINSET2 (Bit 2) */ +#define GPIO_SET3_PINSET2_Msk (0x4UL) /*!< PINSET2 (Bitfield-Mask: 0x01) */ +#define GPIO_SET3_PINSET3_Pos (3UL) /*!< PINSET3 (Bit 3) */ +#define GPIO_SET3_PINSET3_Msk (0x8UL) /*!< PINSET3 (Bitfield-Mask: 0x01) */ +#define GPIO_SET3_PINSET4_Pos (4UL) /*!< PINSET4 (Bit 4) */ +#define GPIO_SET3_PINSET4_Msk (0x10UL) /*!< PINSET4 (Bitfield-Mask: 0x01) */ +#define GPIO_SET3_PINSET5_Pos (5UL) /*!< PINSET5 (Bit 5) */ +#define GPIO_SET3_PINSET5_Msk (0x20UL) /*!< PINSET5 (Bitfield-Mask: 0x01) */ +#define GPIO_SET3_PINSET6_Pos (6UL) /*!< PINSET6 (Bit 6) */ +#define GPIO_SET3_PINSET6_Msk (0x40UL) /*!< PINSET6 (Bitfield-Mask: 0x01) */ +#define GPIO_SET3_PINSET7_Pos (7UL) /*!< PINSET7 (Bit 7) */ +#define GPIO_SET3_PINSET7_Msk (0x80UL) /*!< PINSET7 (Bitfield-Mask: 0x01) */ +#define GPIO_SET3_PINSET8_Pos (8UL) /*!< PINSET8 (Bit 8) */ +#define GPIO_SET3_PINSET8_Msk (0x100UL) /*!< PINSET8 (Bitfield-Mask: 0x01) */ +#define GPIO_SET3_PINSET9_Pos (9UL) /*!< PINSET9 (Bit 9) */ +#define GPIO_SET3_PINSET9_Msk (0x200UL) /*!< PINSET9 (Bitfield-Mask: 0x01) */ +#define GPIO_SET3_PINSET10_Pos (10UL) /*!< PINSET10 (Bit 10) */ +#define GPIO_SET3_PINSET10_Msk (0x400UL) /*!< PINSET10 (Bitfield-Mask: 0x01) */ +#define GPIO_SET3_PINSET11_Pos (11UL) /*!< PINSET11 (Bit 11) */ +#define GPIO_SET3_PINSET11_Msk (0x800UL) /*!< PINSET11 (Bitfield-Mask: 0x01) */ +#define GPIO_SET3_PINSET12_Pos (12UL) /*!< PINSET12 (Bit 12) */ +#define GPIO_SET3_PINSET12_Msk (0x1000UL) /*!< PINSET12 (Bitfield-Mask: 0x01) */ +#define GPIO_SET3_PINSET13_Pos (13UL) /*!< PINSET13 (Bit 13) */ +#define GPIO_SET3_PINSET13_Msk (0x2000UL) /*!< PINSET13 (Bitfield-Mask: 0x01) */ +#define GPIO_SET3_PINSET14_Pos (14UL) /*!< PINSET14 (Bit 14) */ +#define GPIO_SET3_PINSET14_Msk (0x4000UL) /*!< PINSET14 (Bitfield-Mask: 0x01) */ +#define GPIO_SET3_PINSET15_Pos (15UL) /*!< PINSET15 (Bit 15) */ +#define GPIO_SET3_PINSET15_Msk (0x8000UL) /*!< PINSET15 (Bitfield-Mask: 0x01) */ +#define GPIO_SET3_PINSET16_Pos (16UL) /*!< PINSET16 (Bit 16) */ +#define GPIO_SET3_PINSET16_Msk (0x10000UL) /*!< PINSET16 (Bitfield-Mask: 0x01) */ +#define GPIO_SET3_PINSET17_Pos (17UL) /*!< PINSET17 (Bit 17) */ +#define GPIO_SET3_PINSET17_Msk (0x20000UL) /*!< PINSET17 (Bitfield-Mask: 0x01) */ +#define GPIO_SET3_PINSET18_Pos (18UL) /*!< PINSET18 (Bit 18) */ +#define GPIO_SET3_PINSET18_Msk (0x40000UL) /*!< PINSET18 (Bitfield-Mask: 0x01) */ +#define GPIO_SET3_PINSET19_Pos (19UL) /*!< PINSET19 (Bit 19) */ +#define GPIO_SET3_PINSET19_Msk (0x80000UL) /*!< PINSET19 (Bitfield-Mask: 0x01) */ +#define GPIO_SET3_PINSET20_Pos (20UL) /*!< PINSET20 (Bit 20) */ +#define GPIO_SET3_PINSET20_Msk (0x100000UL) /*!< PINSET20 (Bitfield-Mask: 0x01) */ +#define GPIO_SET3_PINSET21_Pos (21UL) /*!< PINSET21 (Bit 21) */ +#define GPIO_SET3_PINSET21_Msk (0x200000UL) /*!< PINSET21 (Bitfield-Mask: 0x01) */ +#define GPIO_SET3_PINSET22_Pos (22UL) /*!< PINSET22 (Bit 22) */ +#define GPIO_SET3_PINSET22_Msk (0x400000UL) /*!< PINSET22 (Bitfield-Mask: 0x01) */ +#define GPIO_SET3_PINSET23_Pos (23UL) /*!< PINSET23 (Bit 23) */ +#define GPIO_SET3_PINSET23_Msk (0x800000UL) /*!< PINSET23 (Bitfield-Mask: 0x01) */ +#define GPIO_SET3_PINSET24_Pos (24UL) /*!< PINSET24 (Bit 24) */ +#define GPIO_SET3_PINSET24_Msk (0x1000000UL) /*!< PINSET24 (Bitfield-Mask: 0x01) */ +#define GPIO_SET3_PINSET25_Pos (25UL) /*!< PINSET25 (Bit 25) */ +#define GPIO_SET3_PINSET25_Msk (0x2000000UL) /*!< PINSET25 (Bitfield-Mask: 0x01) */ +#define GPIO_SET3_PINSET26_Pos (26UL) /*!< PINSET26 (Bit 26) */ +#define GPIO_SET3_PINSET26_Msk (0x4000000UL) /*!< PINSET26 (Bitfield-Mask: 0x01) */ +#define GPIO_SET3_PINSET27_Pos (27UL) /*!< PINSET27 (Bit 27) */ +#define GPIO_SET3_PINSET27_Msk (0x8000000UL) /*!< PINSET27 (Bitfield-Mask: 0x01) */ +#define GPIO_SET3_PINSET28_Pos (28UL) /*!< PINSET28 (Bit 28) */ +#define GPIO_SET3_PINSET28_Msk (0x10000000UL) /*!< PINSET28 (Bitfield-Mask: 0x01) */ +#define GPIO_SET3_PINSET29_Pos (29UL) /*!< PINSET29 (Bit 29) */ +#define GPIO_SET3_PINSET29_Msk (0x20000000UL) /*!< PINSET29 (Bitfield-Mask: 0x01) */ +#define GPIO_SET3_PINSET30_Pos (30UL) /*!< PINSET30 (Bit 30) */ +#define GPIO_SET3_PINSET30_Msk (0x40000000UL) /*!< PINSET30 (Bitfield-Mask: 0x01) */ +#define GPIO_SET3_PINSET31_Pos (31UL) /*!< PINSET31 (Bit 31) */ +#define GPIO_SET3_PINSET31_Msk (0x80000000UL) /*!< PINSET31 (Bitfield-Mask: 0x01) */ +/* ========================================================= SET4 ========================================================== */ +#define GPIO_SET4_PINSET0_Pos (0UL) /*!< PINSET0 (Bit 0) */ +#define GPIO_SET4_PINSET0_Msk (0x1UL) /*!< PINSET0 (Bitfield-Mask: 0x01) */ +#define GPIO_SET4_PINSET1_Pos (1UL) /*!< PINSET1 (Bit 1) */ +#define GPIO_SET4_PINSET1_Msk (0x2UL) /*!< PINSET1 (Bitfield-Mask: 0x01) */ +#define GPIO_SET4_PINSET2_Pos (2UL) /*!< PINSET2 (Bit 2) */ +#define GPIO_SET4_PINSET2_Msk (0x4UL) /*!< PINSET2 (Bitfield-Mask: 0x01) */ +#define GPIO_SET4_PINSET3_Pos (3UL) /*!< PINSET3 (Bit 3) */ +#define GPIO_SET4_PINSET3_Msk (0x8UL) /*!< PINSET3 (Bitfield-Mask: 0x01) */ +#define GPIO_SET4_PINSET4_Pos (4UL) /*!< PINSET4 (Bit 4) */ +#define GPIO_SET4_PINSET4_Msk (0x10UL) /*!< PINSET4 (Bitfield-Mask: 0x01) */ +#define GPIO_SET4_PINSET5_Pos (5UL) /*!< PINSET5 (Bit 5) */ +#define GPIO_SET4_PINSET5_Msk (0x20UL) /*!< PINSET5 (Bitfield-Mask: 0x01) */ +#define GPIO_SET4_PINSET6_Pos (6UL) /*!< PINSET6 (Bit 6) */ +#define GPIO_SET4_PINSET6_Msk (0x40UL) /*!< PINSET6 (Bitfield-Mask: 0x01) */ +#define GPIO_SET4_PINSET7_Pos (7UL) /*!< PINSET7 (Bit 7) */ +#define GPIO_SET4_PINSET7_Msk (0x80UL) /*!< PINSET7 (Bitfield-Mask: 0x01) */ +#define GPIO_SET4_PINSET8_Pos (8UL) /*!< PINSET8 (Bit 8) */ +#define GPIO_SET4_PINSET8_Msk (0x100UL) /*!< PINSET8 (Bitfield-Mask: 0x01) */ +#define GPIO_SET4_PINSET9_Pos (9UL) /*!< PINSET9 (Bit 9) */ +#define GPIO_SET4_PINSET9_Msk (0x200UL) /*!< PINSET9 (Bitfield-Mask: 0x01) */ +#define GPIO_SET4_PINSET10_Pos (10UL) /*!< PINSET10 (Bit 10) */ +#define GPIO_SET4_PINSET10_Msk (0x400UL) /*!< PINSET10 (Bitfield-Mask: 0x01) */ +#define GPIO_SET4_PINSET11_Pos (11UL) /*!< PINSET11 (Bit 11) */ +#define GPIO_SET4_PINSET11_Msk (0x800UL) /*!< PINSET11 (Bitfield-Mask: 0x01) */ +#define GPIO_SET4_PINSET12_Pos (12UL) /*!< PINSET12 (Bit 12) */ +#define GPIO_SET4_PINSET12_Msk (0x1000UL) /*!< PINSET12 (Bitfield-Mask: 0x01) */ +#define GPIO_SET4_PINSET13_Pos (13UL) /*!< PINSET13 (Bit 13) */ +#define GPIO_SET4_PINSET13_Msk (0x2000UL) /*!< PINSET13 (Bitfield-Mask: 0x01) */ +#define GPIO_SET4_PINSET14_Pos (14UL) /*!< PINSET14 (Bit 14) */ +#define GPIO_SET4_PINSET14_Msk (0x4000UL) /*!< PINSET14 (Bitfield-Mask: 0x01) */ +#define GPIO_SET4_PINSET15_Pos (15UL) /*!< PINSET15 (Bit 15) */ +#define GPIO_SET4_PINSET15_Msk (0x8000UL) /*!< PINSET15 (Bitfield-Mask: 0x01) */ +#define GPIO_SET4_PINSET16_Pos (16UL) /*!< PINSET16 (Bit 16) */ +#define GPIO_SET4_PINSET16_Msk (0x10000UL) /*!< PINSET16 (Bitfield-Mask: 0x01) */ +#define GPIO_SET4_PINSET17_Pos (17UL) /*!< PINSET17 (Bit 17) */ +#define GPIO_SET4_PINSET17_Msk (0x20000UL) /*!< PINSET17 (Bitfield-Mask: 0x01) */ +#define GPIO_SET4_PINSET18_Pos (18UL) /*!< PINSET18 (Bit 18) */ +#define GPIO_SET4_PINSET18_Msk (0x40000UL) /*!< PINSET18 (Bitfield-Mask: 0x01) */ +#define GPIO_SET4_PINSET19_Pos (19UL) /*!< PINSET19 (Bit 19) */ +#define GPIO_SET4_PINSET19_Msk (0x80000UL) /*!< PINSET19 (Bitfield-Mask: 0x01) */ +#define GPIO_SET4_PINSET20_Pos (20UL) /*!< PINSET20 (Bit 20) */ +#define GPIO_SET4_PINSET20_Msk (0x100000UL) /*!< PINSET20 (Bitfield-Mask: 0x01) */ +#define GPIO_SET4_PINSET21_Pos (21UL) /*!< PINSET21 (Bit 21) */ +#define GPIO_SET4_PINSET21_Msk (0x200000UL) /*!< PINSET21 (Bitfield-Mask: 0x01) */ +#define GPIO_SET4_PINSET22_Pos (22UL) /*!< PINSET22 (Bit 22) */ +#define GPIO_SET4_PINSET22_Msk (0x400000UL) /*!< PINSET22 (Bitfield-Mask: 0x01) */ +#define GPIO_SET4_PINSET23_Pos (23UL) /*!< PINSET23 (Bit 23) */ +#define GPIO_SET4_PINSET23_Msk (0x800000UL) /*!< PINSET23 (Bitfield-Mask: 0x01) */ +#define GPIO_SET4_PINSET24_Pos (24UL) /*!< PINSET24 (Bit 24) */ +#define GPIO_SET4_PINSET24_Msk (0x1000000UL) /*!< PINSET24 (Bitfield-Mask: 0x01) */ +#define GPIO_SET4_PINSET25_Pos (25UL) /*!< PINSET25 (Bit 25) */ +#define GPIO_SET4_PINSET25_Msk (0x2000000UL) /*!< PINSET25 (Bitfield-Mask: 0x01) */ +#define GPIO_SET4_PINSET26_Pos (26UL) /*!< PINSET26 (Bit 26) */ +#define GPIO_SET4_PINSET26_Msk (0x4000000UL) /*!< PINSET26 (Bitfield-Mask: 0x01) */ +#define GPIO_SET4_PINSET27_Pos (27UL) /*!< PINSET27 (Bit 27) */ +#define GPIO_SET4_PINSET27_Msk (0x8000000UL) /*!< PINSET27 (Bitfield-Mask: 0x01) */ +#define GPIO_SET4_PINSET28_Pos (28UL) /*!< PINSET28 (Bit 28) */ +#define GPIO_SET4_PINSET28_Msk (0x10000000UL) /*!< PINSET28 (Bitfield-Mask: 0x01) */ +#define GPIO_SET4_PINSET29_Pos (29UL) /*!< PINSET29 (Bit 29) */ +#define GPIO_SET4_PINSET29_Msk (0x20000000UL) /*!< PINSET29 (Bitfield-Mask: 0x01) */ +#define GPIO_SET4_PINSET30_Pos (30UL) /*!< PINSET30 (Bit 30) */ +#define GPIO_SET4_PINSET30_Msk (0x40000000UL) /*!< PINSET30 (Bitfield-Mask: 0x01) */ +#define GPIO_SET4_PINSET31_Pos (31UL) /*!< PINSET31 (Bit 31) */ +#define GPIO_SET4_PINSET31_Msk (0x80000000UL) /*!< PINSET31 (Bitfield-Mask: 0x01) */ +/* ========================================================= CLR0 ========================================================== */ +#define GPIO_CLR0_PINCLR0_Pos (0UL) /*!< PINCLR0 (Bit 0) */ +#define GPIO_CLR0_PINCLR0_Msk (0x1UL) /*!< PINCLR0 (Bitfield-Mask: 0x01) */ +#define GPIO_CLR0_PINCLR1_Pos (1UL) /*!< PINCLR1 (Bit 1) */ +#define GPIO_CLR0_PINCLR1_Msk (0x2UL) /*!< PINCLR1 (Bitfield-Mask: 0x01) */ +#define GPIO_CLR0_PINCLR2_Pos (2UL) /*!< PINCLR2 (Bit 2) */ +#define GPIO_CLR0_PINCLR2_Msk (0x4UL) /*!< PINCLR2 (Bitfield-Mask: 0x01) */ +#define GPIO_CLR0_PINCLR3_Pos (3UL) /*!< PINCLR3 (Bit 3) */ +#define GPIO_CLR0_PINCLR3_Msk (0x8UL) /*!< PINCLR3 (Bitfield-Mask: 0x01) */ +#define GPIO_CLR0_PINCLR4_Pos (4UL) /*!< PINCLR4 (Bit 4) */ +#define GPIO_CLR0_PINCLR4_Msk (0x10UL) /*!< PINCLR4 (Bitfield-Mask: 0x01) */ +#define GPIO_CLR0_PINCLR5_Pos (5UL) /*!< PINCLR5 (Bit 5) */ +#define GPIO_CLR0_PINCLR5_Msk (0x20UL) /*!< PINCLR5 (Bitfield-Mask: 0x01) */ +#define GPIO_CLR0_PINCLR6_Pos (6UL) /*!< PINCLR6 (Bit 6) */ +#define GPIO_CLR0_PINCLR6_Msk (0x40UL) /*!< PINCLR6 (Bitfield-Mask: 0x01) */ +#define GPIO_CLR0_PINCLR7_Pos (7UL) /*!< PINCLR7 (Bit 7) */ +#define GPIO_CLR0_PINCLR7_Msk (0x80UL) /*!< PINCLR7 (Bitfield-Mask: 0x01) */ +#define GPIO_CLR0_PINCLR8_Pos (8UL) /*!< PINCLR8 (Bit 8) */ +#define GPIO_CLR0_PINCLR8_Msk (0x100UL) /*!< PINCLR8 (Bitfield-Mask: 0x01) */ +#define GPIO_CLR0_PINCLR9_Pos (9UL) /*!< PINCLR9 (Bit 9) */ +#define GPIO_CLR0_PINCLR9_Msk (0x200UL) /*!< PINCLR9 (Bitfield-Mask: 0x01) */ +#define GPIO_CLR0_PINCLR10_Pos (10UL) /*!< PINCLR10 (Bit 10) */ +#define GPIO_CLR0_PINCLR10_Msk (0x400UL) /*!< PINCLR10 (Bitfield-Mask: 0x01) */ +#define GPIO_CLR0_PINCLR11_Pos (11UL) /*!< PINCLR11 (Bit 11) */ +#define GPIO_CLR0_PINCLR11_Msk (0x800UL) /*!< PINCLR11 (Bitfield-Mask: 0x01) */ +#define GPIO_CLR0_PINCLR12_Pos (12UL) /*!< PINCLR12 (Bit 12) */ +#define GPIO_CLR0_PINCLR12_Msk (0x1000UL) /*!< PINCLR12 (Bitfield-Mask: 0x01) */ +#define GPIO_CLR0_PINCLR13_Pos (13UL) /*!< PINCLR13 (Bit 13) */ +#define GPIO_CLR0_PINCLR13_Msk (0x2000UL) /*!< PINCLR13 (Bitfield-Mask: 0x01) */ +#define GPIO_CLR0_PINCLR14_Pos (14UL) /*!< PINCLR14 (Bit 14) */ +#define GPIO_CLR0_PINCLR14_Msk (0x4000UL) /*!< PINCLR14 (Bitfield-Mask: 0x01) */ +#define GPIO_CLR0_PINCLR15_Pos (15UL) /*!< PINCLR15 (Bit 15) */ +#define GPIO_CLR0_PINCLR15_Msk (0x8000UL) /*!< PINCLR15 (Bitfield-Mask: 0x01) */ +#define GPIO_CLR0_PINCLR16_Pos (16UL) /*!< PINCLR16 (Bit 16) */ +#define GPIO_CLR0_PINCLR16_Msk (0x10000UL) /*!< PINCLR16 (Bitfield-Mask: 0x01) */ +#define GPIO_CLR0_PINCLR17_Pos (17UL) /*!< PINCLR17 (Bit 17) */ +#define GPIO_CLR0_PINCLR17_Msk (0x20000UL) /*!< PINCLR17 (Bitfield-Mask: 0x01) */ +#define GPIO_CLR0_PINCLR18_Pos (18UL) /*!< PINCLR18 (Bit 18) */ +#define GPIO_CLR0_PINCLR18_Msk (0x40000UL) /*!< PINCLR18 (Bitfield-Mask: 0x01) */ +#define GPIO_CLR0_PINCLR19_Pos (19UL) /*!< PINCLR19 (Bit 19) */ +#define GPIO_CLR0_PINCLR19_Msk (0x80000UL) /*!< PINCLR19 (Bitfield-Mask: 0x01) */ +#define GPIO_CLR0_PINCLR20_Pos (20UL) /*!< PINCLR20 (Bit 20) */ +#define GPIO_CLR0_PINCLR20_Msk (0x100000UL) /*!< PINCLR20 (Bitfield-Mask: 0x01) */ +#define GPIO_CLR0_PINCLR21_Pos (21UL) /*!< PINCLR21 (Bit 21) */ +#define GPIO_CLR0_PINCLR21_Msk (0x200000UL) /*!< PINCLR21 (Bitfield-Mask: 0x01) */ +#define GPIO_CLR0_PINCLR22_Pos (22UL) /*!< PINCLR22 (Bit 22) */ +#define GPIO_CLR0_PINCLR22_Msk (0x400000UL) /*!< PINCLR22 (Bitfield-Mask: 0x01) */ +#define GPIO_CLR0_PINCLR23_Pos (23UL) /*!< PINCLR23 (Bit 23) */ +#define GPIO_CLR0_PINCLR23_Msk (0x800000UL) /*!< PINCLR23 (Bitfield-Mask: 0x01) */ +#define GPIO_CLR0_PINCLR24_Pos (24UL) /*!< PINCLR24 (Bit 24) */ +#define GPIO_CLR0_PINCLR24_Msk (0x1000000UL) /*!< PINCLR24 (Bitfield-Mask: 0x01) */ +#define GPIO_CLR0_PINCLR25_Pos (25UL) /*!< PINCLR25 (Bit 25) */ +#define GPIO_CLR0_PINCLR25_Msk (0x2000000UL) /*!< PINCLR25 (Bitfield-Mask: 0x01) */ +#define GPIO_CLR0_PINCLR26_Pos (26UL) /*!< PINCLR26 (Bit 26) */ +#define GPIO_CLR0_PINCLR26_Msk (0x4000000UL) /*!< PINCLR26 (Bitfield-Mask: 0x01) */ +#define GPIO_CLR0_PINCLR27_Pos (27UL) /*!< PINCLR27 (Bit 27) */ +#define GPIO_CLR0_PINCLR27_Msk (0x8000000UL) /*!< PINCLR27 (Bitfield-Mask: 0x01) */ +#define GPIO_CLR0_PINCLR28_Pos (28UL) /*!< PINCLR28 (Bit 28) */ +#define GPIO_CLR0_PINCLR28_Msk (0x10000000UL) /*!< PINCLR28 (Bitfield-Mask: 0x01) */ +#define GPIO_CLR0_PINCLR29_Pos (29UL) /*!< PINCLR29 (Bit 29) */ +#define GPIO_CLR0_PINCLR29_Msk (0x20000000UL) /*!< PINCLR29 (Bitfield-Mask: 0x01) */ +#define GPIO_CLR0_PINCLR30_Pos (30UL) /*!< PINCLR30 (Bit 30) */ +#define GPIO_CLR0_PINCLR30_Msk (0x40000000UL) /*!< PINCLR30 (Bitfield-Mask: 0x01) */ +#define GPIO_CLR0_PINCLR31_Pos (31UL) /*!< PINCLR31 (Bit 31) */ +#define GPIO_CLR0_PINCLR31_Msk (0x80000000UL) /*!< PINCLR31 (Bitfield-Mask: 0x01) */ +/* ========================================================= CLR1 ========================================================== */ +#define GPIO_CLR1_PINCLR0_Pos (0UL) /*!< PINCLR0 (Bit 0) */ +#define GPIO_CLR1_PINCLR0_Msk (0x1UL) /*!< PINCLR0 (Bitfield-Mask: 0x01) */ +#define GPIO_CLR1_PINCLR1_Pos (1UL) /*!< PINCLR1 (Bit 1) */ +#define GPIO_CLR1_PINCLR1_Msk (0x2UL) /*!< PINCLR1 (Bitfield-Mask: 0x01) */ +#define GPIO_CLR1_PINCLR2_Pos (2UL) /*!< PINCLR2 (Bit 2) */ +#define GPIO_CLR1_PINCLR2_Msk (0x4UL) /*!< PINCLR2 (Bitfield-Mask: 0x01) */ +#define GPIO_CLR1_PINCLR3_Pos (3UL) /*!< PINCLR3 (Bit 3) */ +#define GPIO_CLR1_PINCLR3_Msk (0x8UL) /*!< PINCLR3 (Bitfield-Mask: 0x01) */ +#define GPIO_CLR1_PINCLR4_Pos (4UL) /*!< PINCLR4 (Bit 4) */ +#define GPIO_CLR1_PINCLR4_Msk (0x10UL) /*!< PINCLR4 (Bitfield-Mask: 0x01) */ +#define GPIO_CLR1_PINCLR5_Pos (5UL) /*!< PINCLR5 (Bit 5) */ +#define GPIO_CLR1_PINCLR5_Msk (0x20UL) /*!< PINCLR5 (Bitfield-Mask: 0x01) */ +#define GPIO_CLR1_PINCLR6_Pos (6UL) /*!< PINCLR6 (Bit 6) */ +#define GPIO_CLR1_PINCLR6_Msk (0x40UL) /*!< PINCLR6 (Bitfield-Mask: 0x01) */ +#define GPIO_CLR1_PINCLR7_Pos (7UL) /*!< PINCLR7 (Bit 7) */ +#define GPIO_CLR1_PINCLR7_Msk (0x80UL) /*!< PINCLR7 (Bitfield-Mask: 0x01) */ +#define GPIO_CLR1_PINCLR8_Pos (8UL) /*!< PINCLR8 (Bit 8) */ +#define GPIO_CLR1_PINCLR8_Msk (0x100UL) /*!< PINCLR8 (Bitfield-Mask: 0x01) */ +#define GPIO_CLR1_PINCLR9_Pos (9UL) /*!< PINCLR9 (Bit 9) */ +#define GPIO_CLR1_PINCLR9_Msk (0x200UL) /*!< PINCLR9 (Bitfield-Mask: 0x01) */ +#define GPIO_CLR1_PINCLR10_Pos (10UL) /*!< PINCLR10 (Bit 10) */ +#define GPIO_CLR1_PINCLR10_Msk (0x400UL) /*!< PINCLR10 (Bitfield-Mask: 0x01) */ +#define GPIO_CLR1_PINCLR11_Pos (11UL) /*!< PINCLR11 (Bit 11) */ +#define GPIO_CLR1_PINCLR11_Msk (0x800UL) /*!< PINCLR11 (Bitfield-Mask: 0x01) */ +#define GPIO_CLR1_PINCLR12_Pos (12UL) /*!< PINCLR12 (Bit 12) */ +#define GPIO_CLR1_PINCLR12_Msk (0x1000UL) /*!< PINCLR12 (Bitfield-Mask: 0x01) */ +#define GPIO_CLR1_PINCLR13_Pos (13UL) /*!< PINCLR13 (Bit 13) */ +#define GPIO_CLR1_PINCLR13_Msk (0x2000UL) /*!< PINCLR13 (Bitfield-Mask: 0x01) */ +#define GPIO_CLR1_PINCLR14_Pos (14UL) /*!< PINCLR14 (Bit 14) */ +#define GPIO_CLR1_PINCLR14_Msk (0x4000UL) /*!< PINCLR14 (Bitfield-Mask: 0x01) */ +#define GPIO_CLR1_PINCLR15_Pos (15UL) /*!< PINCLR15 (Bit 15) */ +#define GPIO_CLR1_PINCLR15_Msk (0x8000UL) /*!< PINCLR15 (Bitfield-Mask: 0x01) */ +#define GPIO_CLR1_PINCLR16_Pos (16UL) /*!< PINCLR16 (Bit 16) */ +#define GPIO_CLR1_PINCLR16_Msk (0x10000UL) /*!< PINCLR16 (Bitfield-Mask: 0x01) */ +#define GPIO_CLR1_PINCLR17_Pos (17UL) /*!< PINCLR17 (Bit 17) */ +#define GPIO_CLR1_PINCLR17_Msk (0x20000UL) /*!< PINCLR17 (Bitfield-Mask: 0x01) */ +#define GPIO_CLR1_PINCLR18_Pos (18UL) /*!< PINCLR18 (Bit 18) */ +#define GPIO_CLR1_PINCLR18_Msk (0x40000UL) /*!< PINCLR18 (Bitfield-Mask: 0x01) */ +#define GPIO_CLR1_PINCLR19_Pos (19UL) /*!< PINCLR19 (Bit 19) */ +#define GPIO_CLR1_PINCLR19_Msk (0x80000UL) /*!< PINCLR19 (Bitfield-Mask: 0x01) */ +#define GPIO_CLR1_PINCLR20_Pos (20UL) /*!< PINCLR20 (Bit 20) */ +#define GPIO_CLR1_PINCLR20_Msk (0x100000UL) /*!< PINCLR20 (Bitfield-Mask: 0x01) */ +#define GPIO_CLR1_PINCLR21_Pos (21UL) /*!< PINCLR21 (Bit 21) */ +#define GPIO_CLR1_PINCLR21_Msk (0x200000UL) /*!< PINCLR21 (Bitfield-Mask: 0x01) */ +#define GPIO_CLR1_PINCLR22_Pos (22UL) /*!< PINCLR22 (Bit 22) */ +#define GPIO_CLR1_PINCLR22_Msk (0x400000UL) /*!< PINCLR22 (Bitfield-Mask: 0x01) */ +#define GPIO_CLR1_PINCLR23_Pos (23UL) /*!< PINCLR23 (Bit 23) */ +#define GPIO_CLR1_PINCLR23_Msk (0x800000UL) /*!< PINCLR23 (Bitfield-Mask: 0x01) */ +#define GPIO_CLR1_PINCLR24_Pos (24UL) /*!< PINCLR24 (Bit 24) */ +#define GPIO_CLR1_PINCLR24_Msk (0x1000000UL) /*!< PINCLR24 (Bitfield-Mask: 0x01) */ +#define GPIO_CLR1_PINCLR25_Pos (25UL) /*!< PINCLR25 (Bit 25) */ +#define GPIO_CLR1_PINCLR25_Msk (0x2000000UL) /*!< PINCLR25 (Bitfield-Mask: 0x01) */ +#define GPIO_CLR1_PINCLR26_Pos (26UL) /*!< PINCLR26 (Bit 26) */ +#define GPIO_CLR1_PINCLR26_Msk (0x4000000UL) /*!< PINCLR26 (Bitfield-Mask: 0x01) */ +#define GPIO_CLR1_PINCLR27_Pos (27UL) /*!< PINCLR27 (Bit 27) */ +#define GPIO_CLR1_PINCLR27_Msk (0x8000000UL) /*!< PINCLR27 (Bitfield-Mask: 0x01) */ +#define GPIO_CLR1_PINCLR28_Pos (28UL) /*!< PINCLR28 (Bit 28) */ +#define GPIO_CLR1_PINCLR28_Msk (0x10000000UL) /*!< PINCLR28 (Bitfield-Mask: 0x01) */ +#define GPIO_CLR1_PINCLR29_Pos (29UL) /*!< PINCLR29 (Bit 29) */ +#define GPIO_CLR1_PINCLR29_Msk (0x20000000UL) /*!< PINCLR29 (Bitfield-Mask: 0x01) */ +#define GPIO_CLR1_PINCLR30_Pos (30UL) /*!< PINCLR30 (Bit 30) */ +#define GPIO_CLR1_PINCLR30_Msk (0x40000000UL) /*!< PINCLR30 (Bitfield-Mask: 0x01) */ +#define GPIO_CLR1_PINCLR31_Pos (31UL) /*!< PINCLR31 (Bit 31) */ +#define GPIO_CLR1_PINCLR31_Msk (0x80000000UL) /*!< PINCLR31 (Bitfield-Mask: 0x01) */ +/* ========================================================= CLR2 ========================================================== */ +#define GPIO_CLR2_PINCLR0_Pos (0UL) /*!< PINCLR0 (Bit 0) */ +#define GPIO_CLR2_PINCLR0_Msk (0x1UL) /*!< PINCLR0 (Bitfield-Mask: 0x01) */ +#define GPIO_CLR2_PINCLR1_Pos (1UL) /*!< PINCLR1 (Bit 1) */ +#define GPIO_CLR2_PINCLR1_Msk (0x2UL) /*!< PINCLR1 (Bitfield-Mask: 0x01) */ +#define GPIO_CLR2_PINCLR2_Pos (2UL) /*!< PINCLR2 (Bit 2) */ +#define GPIO_CLR2_PINCLR2_Msk (0x4UL) /*!< PINCLR2 (Bitfield-Mask: 0x01) */ +#define GPIO_CLR2_PINCLR3_Pos (3UL) /*!< PINCLR3 (Bit 3) */ +#define GPIO_CLR2_PINCLR3_Msk (0x8UL) /*!< PINCLR3 (Bitfield-Mask: 0x01) */ +#define GPIO_CLR2_PINCLR4_Pos (4UL) /*!< PINCLR4 (Bit 4) */ +#define GPIO_CLR2_PINCLR4_Msk (0x10UL) /*!< PINCLR4 (Bitfield-Mask: 0x01) */ +#define GPIO_CLR2_PINCLR5_Pos (5UL) /*!< PINCLR5 (Bit 5) */ +#define GPIO_CLR2_PINCLR5_Msk (0x20UL) /*!< PINCLR5 (Bitfield-Mask: 0x01) */ +#define GPIO_CLR2_PINCLR6_Pos (6UL) /*!< PINCLR6 (Bit 6) */ +#define GPIO_CLR2_PINCLR6_Msk (0x40UL) /*!< PINCLR6 (Bitfield-Mask: 0x01) */ +#define GPIO_CLR2_PINCLR7_Pos (7UL) /*!< PINCLR7 (Bit 7) */ +#define GPIO_CLR2_PINCLR7_Msk (0x80UL) /*!< PINCLR7 (Bitfield-Mask: 0x01) */ +#define GPIO_CLR2_PINCLR8_Pos (8UL) /*!< PINCLR8 (Bit 8) */ +#define GPIO_CLR2_PINCLR8_Msk (0x100UL) /*!< PINCLR8 (Bitfield-Mask: 0x01) */ +#define GPIO_CLR2_PINCLR9_Pos (9UL) /*!< PINCLR9 (Bit 9) */ +#define GPIO_CLR2_PINCLR9_Msk (0x200UL) /*!< PINCLR9 (Bitfield-Mask: 0x01) */ +#define GPIO_CLR2_PINCLR10_Pos (10UL) /*!< PINCLR10 (Bit 10) */ +#define GPIO_CLR2_PINCLR10_Msk (0x400UL) /*!< PINCLR10 (Bitfield-Mask: 0x01) */ +#define GPIO_CLR2_PINCLR11_Pos (11UL) /*!< PINCLR11 (Bit 11) */ +#define GPIO_CLR2_PINCLR11_Msk (0x800UL) /*!< PINCLR11 (Bitfield-Mask: 0x01) */ +#define GPIO_CLR2_PINCLR12_Pos (12UL) /*!< PINCLR12 (Bit 12) */ +#define GPIO_CLR2_PINCLR12_Msk (0x1000UL) /*!< PINCLR12 (Bitfield-Mask: 0x01) */ +#define GPIO_CLR2_PINCLR13_Pos (13UL) /*!< PINCLR13 (Bit 13) */ +#define GPIO_CLR2_PINCLR13_Msk (0x2000UL) /*!< PINCLR13 (Bitfield-Mask: 0x01) */ +#define GPIO_CLR2_PINCLR14_Pos (14UL) /*!< PINCLR14 (Bit 14) */ +#define GPIO_CLR2_PINCLR14_Msk (0x4000UL) /*!< PINCLR14 (Bitfield-Mask: 0x01) */ +#define GPIO_CLR2_PINCLR15_Pos (15UL) /*!< PINCLR15 (Bit 15) */ +#define GPIO_CLR2_PINCLR15_Msk (0x8000UL) /*!< PINCLR15 (Bitfield-Mask: 0x01) */ +#define GPIO_CLR2_PINCLR16_Pos (16UL) /*!< PINCLR16 (Bit 16) */ +#define GPIO_CLR2_PINCLR16_Msk (0x10000UL) /*!< PINCLR16 (Bitfield-Mask: 0x01) */ +#define GPIO_CLR2_PINCLR17_Pos (17UL) /*!< PINCLR17 (Bit 17) */ +#define GPIO_CLR2_PINCLR17_Msk (0x20000UL) /*!< PINCLR17 (Bitfield-Mask: 0x01) */ +#define GPIO_CLR2_PINCLR18_Pos (18UL) /*!< PINCLR18 (Bit 18) */ +#define GPIO_CLR2_PINCLR18_Msk (0x40000UL) /*!< PINCLR18 (Bitfield-Mask: 0x01) */ +#define GPIO_CLR2_PINCLR19_Pos (19UL) /*!< PINCLR19 (Bit 19) */ +#define GPIO_CLR2_PINCLR19_Msk (0x80000UL) /*!< PINCLR19 (Bitfield-Mask: 0x01) */ +#define GPIO_CLR2_PINCLR20_Pos (20UL) /*!< PINCLR20 (Bit 20) */ +#define GPIO_CLR2_PINCLR20_Msk (0x100000UL) /*!< PINCLR20 (Bitfield-Mask: 0x01) */ +#define GPIO_CLR2_PINCLR21_Pos (21UL) /*!< PINCLR21 (Bit 21) */ +#define GPIO_CLR2_PINCLR21_Msk (0x200000UL) /*!< PINCLR21 (Bitfield-Mask: 0x01) */ +#define GPIO_CLR2_PINCLR22_Pos (22UL) /*!< PINCLR22 (Bit 22) */ +#define GPIO_CLR2_PINCLR22_Msk (0x400000UL) /*!< PINCLR22 (Bitfield-Mask: 0x01) */ +#define GPIO_CLR2_PINCLR23_Pos (23UL) /*!< PINCLR23 (Bit 23) */ +#define GPIO_CLR2_PINCLR23_Msk (0x800000UL) /*!< PINCLR23 (Bitfield-Mask: 0x01) */ +#define GPIO_CLR2_PINCLR24_Pos (24UL) /*!< PINCLR24 (Bit 24) */ +#define GPIO_CLR2_PINCLR24_Msk (0x1000000UL) /*!< PINCLR24 (Bitfield-Mask: 0x01) */ +#define GPIO_CLR2_PINCLR25_Pos (25UL) /*!< PINCLR25 (Bit 25) */ +#define GPIO_CLR2_PINCLR25_Msk (0x2000000UL) /*!< PINCLR25 (Bitfield-Mask: 0x01) */ +#define GPIO_CLR2_PINCLR26_Pos (26UL) /*!< PINCLR26 (Bit 26) */ +#define GPIO_CLR2_PINCLR26_Msk (0x4000000UL) /*!< PINCLR26 (Bitfield-Mask: 0x01) */ +#define GPIO_CLR2_PINCLR27_Pos (27UL) /*!< PINCLR27 (Bit 27) */ +#define GPIO_CLR2_PINCLR27_Msk (0x8000000UL) /*!< PINCLR27 (Bitfield-Mask: 0x01) */ +#define GPIO_CLR2_PINCLR28_Pos (28UL) /*!< PINCLR28 (Bit 28) */ +#define GPIO_CLR2_PINCLR28_Msk (0x10000000UL) /*!< PINCLR28 (Bitfield-Mask: 0x01) */ +#define GPIO_CLR2_PINCLR29_Pos (29UL) /*!< PINCLR29 (Bit 29) */ +#define GPIO_CLR2_PINCLR29_Msk (0x20000000UL) /*!< PINCLR29 (Bitfield-Mask: 0x01) */ +#define GPIO_CLR2_PINCLR30_Pos (30UL) /*!< PINCLR30 (Bit 30) */ +#define GPIO_CLR2_PINCLR30_Msk (0x40000000UL) /*!< PINCLR30 (Bitfield-Mask: 0x01) */ +#define GPIO_CLR2_PINCLR31_Pos (31UL) /*!< PINCLR31 (Bit 31) */ +#define GPIO_CLR2_PINCLR31_Msk (0x80000000UL) /*!< PINCLR31 (Bitfield-Mask: 0x01) */ +/* ========================================================= CLR3 ========================================================== */ +#define GPIO_CLR3_PINCLR0_Pos (0UL) /*!< PINCLR0 (Bit 0) */ +#define GPIO_CLR3_PINCLR0_Msk (0x1UL) /*!< PINCLR0 (Bitfield-Mask: 0x01) */ +#define GPIO_CLR3_PINCLR1_Pos (1UL) /*!< PINCLR1 (Bit 1) */ +#define GPIO_CLR3_PINCLR1_Msk (0x2UL) /*!< PINCLR1 (Bitfield-Mask: 0x01) */ +#define GPIO_CLR3_PINCLR2_Pos (2UL) /*!< PINCLR2 (Bit 2) */ +#define GPIO_CLR3_PINCLR2_Msk (0x4UL) /*!< PINCLR2 (Bitfield-Mask: 0x01) */ +#define GPIO_CLR3_PINCLR3_Pos (3UL) /*!< PINCLR3 (Bit 3) */ +#define GPIO_CLR3_PINCLR3_Msk (0x8UL) /*!< PINCLR3 (Bitfield-Mask: 0x01) */ +#define GPIO_CLR3_PINCLR4_Pos (4UL) /*!< PINCLR4 (Bit 4) */ +#define GPIO_CLR3_PINCLR4_Msk (0x10UL) /*!< PINCLR4 (Bitfield-Mask: 0x01) */ +#define GPIO_CLR3_PINCLR5_Pos (5UL) /*!< PINCLR5 (Bit 5) */ +#define GPIO_CLR3_PINCLR5_Msk (0x20UL) /*!< PINCLR5 (Bitfield-Mask: 0x01) */ +#define GPIO_CLR3_PINCLR6_Pos (6UL) /*!< PINCLR6 (Bit 6) */ +#define GPIO_CLR3_PINCLR6_Msk (0x40UL) /*!< PINCLR6 (Bitfield-Mask: 0x01) */ +#define GPIO_CLR3_PINCLR7_Pos (7UL) /*!< PINCLR7 (Bit 7) */ +#define GPIO_CLR3_PINCLR7_Msk (0x80UL) /*!< PINCLR7 (Bitfield-Mask: 0x01) */ +#define GPIO_CLR3_PINCLR8_Pos (8UL) /*!< PINCLR8 (Bit 8) */ +#define GPIO_CLR3_PINCLR8_Msk (0x100UL) /*!< PINCLR8 (Bitfield-Mask: 0x01) */ +#define GPIO_CLR3_PINCLR9_Pos (9UL) /*!< PINCLR9 (Bit 9) */ +#define GPIO_CLR3_PINCLR9_Msk (0x200UL) /*!< PINCLR9 (Bitfield-Mask: 0x01) */ +#define GPIO_CLR3_PINCLR10_Pos (10UL) /*!< PINCLR10 (Bit 10) */ +#define GPIO_CLR3_PINCLR10_Msk (0x400UL) /*!< PINCLR10 (Bitfield-Mask: 0x01) */ +#define GPIO_CLR3_PINCLR11_Pos (11UL) /*!< PINCLR11 (Bit 11) */ +#define GPIO_CLR3_PINCLR11_Msk (0x800UL) /*!< PINCLR11 (Bitfield-Mask: 0x01) */ +#define GPIO_CLR3_PINCLR12_Pos (12UL) /*!< PINCLR12 (Bit 12) */ +#define GPIO_CLR3_PINCLR12_Msk (0x1000UL) /*!< PINCLR12 (Bitfield-Mask: 0x01) */ +#define GPIO_CLR3_PINCLR13_Pos (13UL) /*!< PINCLR13 (Bit 13) */ +#define GPIO_CLR3_PINCLR13_Msk (0x2000UL) /*!< PINCLR13 (Bitfield-Mask: 0x01) */ +#define GPIO_CLR3_PINCLR14_Pos (14UL) /*!< PINCLR14 (Bit 14) */ +#define GPIO_CLR3_PINCLR14_Msk (0x4000UL) /*!< PINCLR14 (Bitfield-Mask: 0x01) */ +#define GPIO_CLR3_PINCLR15_Pos (15UL) /*!< PINCLR15 (Bit 15) */ +#define GPIO_CLR3_PINCLR15_Msk (0x8000UL) /*!< PINCLR15 (Bitfield-Mask: 0x01) */ +#define GPIO_CLR3_PINCLR16_Pos (16UL) /*!< PINCLR16 (Bit 16) */ +#define GPIO_CLR3_PINCLR16_Msk (0x10000UL) /*!< PINCLR16 (Bitfield-Mask: 0x01) */ +#define GPIO_CLR3_PINCLR17_Pos (17UL) /*!< PINCLR17 (Bit 17) */ +#define GPIO_CLR3_PINCLR17_Msk (0x20000UL) /*!< PINCLR17 (Bitfield-Mask: 0x01) */ +#define GPIO_CLR3_PINCLR18_Pos (18UL) /*!< PINCLR18 (Bit 18) */ +#define GPIO_CLR3_PINCLR18_Msk (0x40000UL) /*!< PINCLR18 (Bitfield-Mask: 0x01) */ +#define GPIO_CLR3_PINCLR19_Pos (19UL) /*!< PINCLR19 (Bit 19) */ +#define GPIO_CLR3_PINCLR19_Msk (0x80000UL) /*!< PINCLR19 (Bitfield-Mask: 0x01) */ +#define GPIO_CLR3_PINCLR20_Pos (20UL) /*!< PINCLR20 (Bit 20) */ +#define GPIO_CLR3_PINCLR20_Msk (0x100000UL) /*!< PINCLR20 (Bitfield-Mask: 0x01) */ +#define GPIO_CLR3_PINCLR21_Pos (21UL) /*!< PINCLR21 (Bit 21) */ +#define GPIO_CLR3_PINCLR21_Msk (0x200000UL) /*!< PINCLR21 (Bitfield-Mask: 0x01) */ +#define GPIO_CLR3_PINCLR22_Pos (22UL) /*!< PINCLR22 (Bit 22) */ +#define GPIO_CLR3_PINCLR22_Msk (0x400000UL) /*!< PINCLR22 (Bitfield-Mask: 0x01) */ +#define GPIO_CLR3_PINCLR23_Pos (23UL) /*!< PINCLR23 (Bit 23) */ +#define GPIO_CLR3_PINCLR23_Msk (0x800000UL) /*!< PINCLR23 (Bitfield-Mask: 0x01) */ +#define GPIO_CLR3_PINCLR24_Pos (24UL) /*!< PINCLR24 (Bit 24) */ +#define GPIO_CLR3_PINCLR24_Msk (0x1000000UL) /*!< PINCLR24 (Bitfield-Mask: 0x01) */ +#define GPIO_CLR3_PINCLR25_Pos (25UL) /*!< PINCLR25 (Bit 25) */ +#define GPIO_CLR3_PINCLR25_Msk (0x2000000UL) /*!< PINCLR25 (Bitfield-Mask: 0x01) */ +#define GPIO_CLR3_PINCLR26_Pos (26UL) /*!< PINCLR26 (Bit 26) */ +#define GPIO_CLR3_PINCLR26_Msk (0x4000000UL) /*!< PINCLR26 (Bitfield-Mask: 0x01) */ +#define GPIO_CLR3_PINCLR27_Pos (27UL) /*!< PINCLR27 (Bit 27) */ +#define GPIO_CLR3_PINCLR27_Msk (0x8000000UL) /*!< PINCLR27 (Bitfield-Mask: 0x01) */ +#define GPIO_CLR3_PINCLR28_Pos (28UL) /*!< PINCLR28 (Bit 28) */ +#define GPIO_CLR3_PINCLR28_Msk (0x10000000UL) /*!< PINCLR28 (Bitfield-Mask: 0x01) */ +#define GPIO_CLR3_PINCLR29_Pos (29UL) /*!< PINCLR29 (Bit 29) */ +#define GPIO_CLR3_PINCLR29_Msk (0x20000000UL) /*!< PINCLR29 (Bitfield-Mask: 0x01) */ +#define GPIO_CLR3_PINCLR30_Pos (30UL) /*!< PINCLR30 (Bit 30) */ +#define GPIO_CLR3_PINCLR30_Msk (0x40000000UL) /*!< PINCLR30 (Bitfield-Mask: 0x01) */ +#define GPIO_CLR3_PINCLR31_Pos (31UL) /*!< PINCLR31 (Bit 31) */ +#define GPIO_CLR3_PINCLR31_Msk (0x80000000UL) /*!< PINCLR31 (Bitfield-Mask: 0x01) */ +/* ========================================================= CLR4 ========================================================== */ +#define GPIO_CLR4_PINCLR0_Pos (0UL) /*!< PINCLR0 (Bit 0) */ +#define GPIO_CLR4_PINCLR0_Msk (0x1UL) /*!< PINCLR0 (Bitfield-Mask: 0x01) */ +#define GPIO_CLR4_PINCLR1_Pos (1UL) /*!< PINCLR1 (Bit 1) */ +#define GPIO_CLR4_PINCLR1_Msk (0x2UL) /*!< PINCLR1 (Bitfield-Mask: 0x01) */ +#define GPIO_CLR4_PINCLR2_Pos (2UL) /*!< PINCLR2 (Bit 2) */ +#define GPIO_CLR4_PINCLR2_Msk (0x4UL) /*!< PINCLR2 (Bitfield-Mask: 0x01) */ +#define GPIO_CLR4_PINCLR3_Pos (3UL) /*!< PINCLR3 (Bit 3) */ +#define GPIO_CLR4_PINCLR3_Msk (0x8UL) /*!< PINCLR3 (Bitfield-Mask: 0x01) */ +#define GPIO_CLR4_PINCLR4_Pos (4UL) /*!< PINCLR4 (Bit 4) */ +#define GPIO_CLR4_PINCLR4_Msk (0x10UL) /*!< PINCLR4 (Bitfield-Mask: 0x01) */ +#define GPIO_CLR4_PINCLR5_Pos (5UL) /*!< PINCLR5 (Bit 5) */ +#define GPIO_CLR4_PINCLR5_Msk (0x20UL) /*!< PINCLR5 (Bitfield-Mask: 0x01) */ +#define GPIO_CLR4_PINCLR6_Pos (6UL) /*!< PINCLR6 (Bit 6) */ +#define GPIO_CLR4_PINCLR6_Msk (0x40UL) /*!< PINCLR6 (Bitfield-Mask: 0x01) */ +#define GPIO_CLR4_PINCLR7_Pos (7UL) /*!< PINCLR7 (Bit 7) */ +#define GPIO_CLR4_PINCLR7_Msk (0x80UL) /*!< PINCLR7 (Bitfield-Mask: 0x01) */ +#define GPIO_CLR4_PINCLR8_Pos (8UL) /*!< PINCLR8 (Bit 8) */ +#define GPIO_CLR4_PINCLR8_Msk (0x100UL) /*!< PINCLR8 (Bitfield-Mask: 0x01) */ +#define GPIO_CLR4_PINCLR9_Pos (9UL) /*!< PINCLR9 (Bit 9) */ +#define GPIO_CLR4_PINCLR9_Msk (0x200UL) /*!< PINCLR9 (Bitfield-Mask: 0x01) */ +#define GPIO_CLR4_PINCLR10_Pos (10UL) /*!< PINCLR10 (Bit 10) */ +#define GPIO_CLR4_PINCLR10_Msk (0x400UL) /*!< PINCLR10 (Bitfield-Mask: 0x01) */ +#define GPIO_CLR4_PINCLR11_Pos (11UL) /*!< PINCLR11 (Bit 11) */ +#define GPIO_CLR4_PINCLR11_Msk (0x800UL) /*!< PINCLR11 (Bitfield-Mask: 0x01) */ +#define GPIO_CLR4_PINCLR12_Pos (12UL) /*!< PINCLR12 (Bit 12) */ +#define GPIO_CLR4_PINCLR12_Msk (0x1000UL) /*!< PINCLR12 (Bitfield-Mask: 0x01) */ +#define GPIO_CLR4_PINCLR13_Pos (13UL) /*!< PINCLR13 (Bit 13) */ +#define GPIO_CLR4_PINCLR13_Msk (0x2000UL) /*!< PINCLR13 (Bitfield-Mask: 0x01) */ +#define GPIO_CLR4_PINCLR14_Pos (14UL) /*!< PINCLR14 (Bit 14) */ +#define GPIO_CLR4_PINCLR14_Msk (0x4000UL) /*!< PINCLR14 (Bitfield-Mask: 0x01) */ +#define GPIO_CLR4_PINCLR15_Pos (15UL) /*!< PINCLR15 (Bit 15) */ +#define GPIO_CLR4_PINCLR15_Msk (0x8000UL) /*!< PINCLR15 (Bitfield-Mask: 0x01) */ +#define GPIO_CLR4_PINCLR16_Pos (16UL) /*!< PINCLR16 (Bit 16) */ +#define GPIO_CLR4_PINCLR16_Msk (0x10000UL) /*!< PINCLR16 (Bitfield-Mask: 0x01) */ +#define GPIO_CLR4_PINCLR17_Pos (17UL) /*!< PINCLR17 (Bit 17) */ +#define GPIO_CLR4_PINCLR17_Msk (0x20000UL) /*!< PINCLR17 (Bitfield-Mask: 0x01) */ +#define GPIO_CLR4_PINCLR18_Pos (18UL) /*!< PINCLR18 (Bit 18) */ +#define GPIO_CLR4_PINCLR18_Msk (0x40000UL) /*!< PINCLR18 (Bitfield-Mask: 0x01) */ +#define GPIO_CLR4_PINCLR19_Pos (19UL) /*!< PINCLR19 (Bit 19) */ +#define GPIO_CLR4_PINCLR19_Msk (0x80000UL) /*!< PINCLR19 (Bitfield-Mask: 0x01) */ +#define GPIO_CLR4_PINCLR20_Pos (20UL) /*!< PINCLR20 (Bit 20) */ +#define GPIO_CLR4_PINCLR20_Msk (0x100000UL) /*!< PINCLR20 (Bitfield-Mask: 0x01) */ +#define GPIO_CLR4_PINCLR21_Pos (21UL) /*!< PINCLR21 (Bit 21) */ +#define GPIO_CLR4_PINCLR21_Msk (0x200000UL) /*!< PINCLR21 (Bitfield-Mask: 0x01) */ +#define GPIO_CLR4_PINCLR22_Pos (22UL) /*!< PINCLR22 (Bit 22) */ +#define GPIO_CLR4_PINCLR22_Msk (0x400000UL) /*!< PINCLR22 (Bitfield-Mask: 0x01) */ +#define GPIO_CLR4_PINCLR23_Pos (23UL) /*!< PINCLR23 (Bit 23) */ +#define GPIO_CLR4_PINCLR23_Msk (0x800000UL) /*!< PINCLR23 (Bitfield-Mask: 0x01) */ +#define GPIO_CLR4_PINCLR24_Pos (24UL) /*!< PINCLR24 (Bit 24) */ +#define GPIO_CLR4_PINCLR24_Msk (0x1000000UL) /*!< PINCLR24 (Bitfield-Mask: 0x01) */ +#define GPIO_CLR4_PINCLR25_Pos (25UL) /*!< PINCLR25 (Bit 25) */ +#define GPIO_CLR4_PINCLR25_Msk (0x2000000UL) /*!< PINCLR25 (Bitfield-Mask: 0x01) */ +#define GPIO_CLR4_PINCLR26_Pos (26UL) /*!< PINCLR26 (Bit 26) */ +#define GPIO_CLR4_PINCLR26_Msk (0x4000000UL) /*!< PINCLR26 (Bitfield-Mask: 0x01) */ +#define GPIO_CLR4_PINCLR27_Pos (27UL) /*!< PINCLR27 (Bit 27) */ +#define GPIO_CLR4_PINCLR27_Msk (0x8000000UL) /*!< PINCLR27 (Bitfield-Mask: 0x01) */ +#define GPIO_CLR4_PINCLR28_Pos (28UL) /*!< PINCLR28 (Bit 28) */ +#define GPIO_CLR4_PINCLR28_Msk (0x10000000UL) /*!< PINCLR28 (Bitfield-Mask: 0x01) */ +#define GPIO_CLR4_PINCLR29_Pos (29UL) /*!< PINCLR29 (Bit 29) */ +#define GPIO_CLR4_PINCLR29_Msk (0x20000000UL) /*!< PINCLR29 (Bitfield-Mask: 0x01) */ +#define GPIO_CLR4_PINCLR30_Pos (30UL) /*!< PINCLR30 (Bit 30) */ +#define GPIO_CLR4_PINCLR30_Msk (0x40000000UL) /*!< PINCLR30 (Bitfield-Mask: 0x01) */ +#define GPIO_CLR4_PINCLR31_Pos (31UL) /*!< PINCLR31 (Bit 31) */ +#define GPIO_CLR4_PINCLR31_Msk (0x80000000UL) /*!< PINCLR31 (Bitfield-Mask: 0x01) */ + +/** @} */ /* End of group PosMask_peripherals */ + + +#ifdef __cplusplus +} +#endif + +#endif /* LPC176X5X_H */ + + +/** @} */ /* End of group LPC176x5x */ + +/** @} */ /* End of group */ diff --git a/bootloader/inc/cmsis_armcc.h b/bootloader/inc/cmsis_armcc.h new file mode 100644 index 0000000..cecc361 --- /dev/null +++ b/bootloader/inc/cmsis_armcc.h @@ -0,0 +1,884 @@ +/**************************************************************************//** + * @file cmsis_armcc.h + * @brief CMSIS compiler ARMCC (Arm Compiler 5) header file + * @version V5.2.0 + * @date 28. January 2020 + ******************************************************************************/ +/* + * Copyright (c) 2009-2019 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __CMSIS_ARMCC_H +#define __CMSIS_ARMCC_H + + +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 400677) + #error "Please use Arm Compiler Toolchain V4.0.677 or later!" +#endif + +/* CMSIS compiler control architecture macros */ +#if ((defined (__TARGET_ARCH_6_M ) && (__TARGET_ARCH_6_M == 1)) || \ + (defined (__TARGET_ARCH_6S_M ) && (__TARGET_ARCH_6S_M == 1)) ) + #define __ARM_ARCH_6M__ 1 +#endif + +#if (defined (__TARGET_ARCH_7_M ) && (__TARGET_ARCH_7_M == 1)) + #define __ARM_ARCH_7M__ 1 +#endif + +#if (defined (__TARGET_ARCH_7E_M) && (__TARGET_ARCH_7E_M == 1)) + #define __ARM_ARCH_7EM__ 1 +#endif + + /* __ARM_ARCH_8M_BASE__ not applicable */ + /* __ARM_ARCH_8M_MAIN__ not applicable */ + +/* CMSIS compiler control DSP macros */ +#if ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) + #define __ARM_FEATURE_DSP 1 +#endif + +/* CMSIS compiler specific defines */ +#ifndef __ASM + #define __ASM __asm +#endif +#ifndef __INLINE + #define __INLINE __inline +#endif +#ifndef __STATIC_INLINE + #define __STATIC_INLINE static __inline +#endif +#ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE static __forceinline +#endif +#ifndef __NO_RETURN + #define __NO_RETURN __declspec(noreturn) +#endif +#ifndef __USED + #define __USED __attribute__((used)) +#endif +#ifndef __WEAK + #define __WEAK __attribute__((weak)) +#endif +#ifndef __PACKED + #define __PACKED __attribute__((packed)) +#endif +#ifndef __PACKED_STRUCT + #define __PACKED_STRUCT __packed struct +#endif +#ifndef __PACKED_UNION + #define __PACKED_UNION __packed union +#endif +#ifndef __UNALIGNED_UINT32 /* deprecated */ + #define __UNALIGNED_UINT32(x) (*((__packed uint32_t *)(x))) +#endif +#ifndef __UNALIGNED_UINT16_WRITE + #define __UNALIGNED_UINT16_WRITE(addr, val) ((*((__packed uint16_t *)(addr))) = (val)) +#endif +#ifndef __UNALIGNED_UINT16_READ + #define __UNALIGNED_UINT16_READ(addr) (*((const __packed uint16_t *)(addr))) +#endif +#ifndef __UNALIGNED_UINT32_WRITE + #define __UNALIGNED_UINT32_WRITE(addr, val) ((*((__packed uint32_t *)(addr))) = (val)) +#endif +#ifndef __UNALIGNED_UINT32_READ + #define __UNALIGNED_UINT32_READ(addr) (*((const __packed uint32_t *)(addr))) +#endif +#ifndef __ALIGNED + #define __ALIGNED(x) __attribute__((aligned(x))) +#endif +#ifndef __RESTRICT + #define __RESTRICT __restrict +#endif +#ifndef __COMPILER_BARRIER + #define __COMPILER_BARRIER() __memory_changed() +#endif + +/* ######################### Startup and Lowlevel Init ######################## */ + +#ifndef __PROGRAM_START +#define __PROGRAM_START __main +#endif + +#ifndef __INITIAL_SP +#define __INITIAL_SP Image$$ARM_LIB_STACK$$ZI$$Limit +#endif + +#ifndef __STACK_LIMIT +#define __STACK_LIMIT Image$$ARM_LIB_STACK$$ZI$$Base +#endif + +#ifndef __VECTOR_TABLE +#define __VECTOR_TABLE __Vectors +#endif + +#ifndef __VECTOR_TABLE_ATTRIBUTE +#define __VECTOR_TABLE_ATTRIBUTE __attribute((used, section("RESET"))) +#endif + +/* ########################### Core Function Access ########################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions + @{ + */ + +/** + \brief Enable IRQ Interrupts + \details Enables IRQ interrupts by clearing the I-bit in the CPSR. + Can only be executed in Privileged modes. + */ +/* intrinsic void __enable_irq(); */ + + +/** + \brief Disable IRQ Interrupts + \details Disables IRQ interrupts by setting the I-bit in the CPSR. + Can only be executed in Privileged modes. + */ +/* intrinsic void __disable_irq(); */ + +/** + \brief Get Control Register + \details Returns the content of the Control Register. + \return Control Register value + */ +__STATIC_INLINE uint32_t __get_CONTROL(void) +{ + register uint32_t __regControl __ASM("control"); + return(__regControl); +} + + +/** + \brief Set Control Register + \details Writes the given value to the Control Register. + \param [in] control Control Register value to set + */ +__STATIC_INLINE void __set_CONTROL(uint32_t control) +{ + register uint32_t __regControl __ASM("control"); + __regControl = control; +} + + +/** + \brief Get IPSR Register + \details Returns the content of the IPSR Register. + \return IPSR Register value + */ +__STATIC_INLINE uint32_t __get_IPSR(void) +{ + register uint32_t __regIPSR __ASM("ipsr"); + return(__regIPSR); +} + + +/** + \brief Get APSR Register + \details Returns the content of the APSR Register. + \return APSR Register value + */ +__STATIC_INLINE uint32_t __get_APSR(void) +{ + register uint32_t __regAPSR __ASM("apsr"); + return(__regAPSR); +} + + +/** + \brief Get xPSR Register + \details Returns the content of the xPSR Register. + \return xPSR Register value + */ +__STATIC_INLINE uint32_t __get_xPSR(void) +{ + register uint32_t __regXPSR __ASM("xpsr"); + return(__regXPSR); +} + + +/** + \brief Get Process Stack Pointer + \details Returns the current value of the Process Stack Pointer (PSP). + \return PSP Register value + */ +__STATIC_INLINE uint32_t __get_PSP(void) +{ + register uint32_t __regProcessStackPointer __ASM("psp"); + return(__regProcessStackPointer); +} + + +/** + \brief Set Process Stack Pointer + \details Assigns the given value to the Process Stack Pointer (PSP). + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__STATIC_INLINE void __set_PSP(uint32_t topOfProcStack) +{ + register uint32_t __regProcessStackPointer __ASM("psp"); + __regProcessStackPointer = topOfProcStack; +} + + +/** + \brief Get Main Stack Pointer + \details Returns the current value of the Main Stack Pointer (MSP). + \return MSP Register value + */ +__STATIC_INLINE uint32_t __get_MSP(void) +{ + register uint32_t __regMainStackPointer __ASM("msp"); + return(__regMainStackPointer); +} + + +/** + \brief Set Main Stack Pointer + \details Assigns the given value to the Main Stack Pointer (MSP). + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__STATIC_INLINE void __set_MSP(uint32_t topOfMainStack) +{ + register uint32_t __regMainStackPointer __ASM("msp"); + __regMainStackPointer = topOfMainStack; +} + + +/** + \brief Get Priority Mask + \details Returns the current state of the priority mask bit from the Priority Mask Register. + \return Priority Mask value + */ +__STATIC_INLINE uint32_t __get_PRIMASK(void) +{ + register uint32_t __regPriMask __ASM("primask"); + return(__regPriMask); +} + + +/** + \brief Set Priority Mask + \details Assigns the given value to the Priority Mask Register. + \param [in] priMask Priority Mask + */ +__STATIC_INLINE void __set_PRIMASK(uint32_t priMask) +{ + register uint32_t __regPriMask __ASM("primask"); + __regPriMask = (priMask); +} + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) + +/** + \brief Enable FIQ + \details Enables FIQ interrupts by clearing the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +#define __enable_fault_irq __enable_fiq + + +/** + \brief Disable FIQ + \details Disables FIQ interrupts by setting the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +#define __disable_fault_irq __disable_fiq + + +/** + \brief Get Base Priority + \details Returns the current value of the Base Priority register. + \return Base Priority register value + */ +__STATIC_INLINE uint32_t __get_BASEPRI(void) +{ + register uint32_t __regBasePri __ASM("basepri"); + return(__regBasePri); +} + + +/** + \brief Set Base Priority + \details Assigns the given value to the Base Priority register. + \param [in] basePri Base Priority value to set + */ +__STATIC_INLINE void __set_BASEPRI(uint32_t basePri) +{ + register uint32_t __regBasePri __ASM("basepri"); + __regBasePri = (basePri & 0xFFU); +} + + +/** + \brief Set Base Priority with condition + \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled, + or the new value increases the BASEPRI priority level. + \param [in] basePri Base Priority value to set + */ +__STATIC_INLINE void __set_BASEPRI_MAX(uint32_t basePri) +{ + register uint32_t __regBasePriMax __ASM("basepri_max"); + __regBasePriMax = (basePri & 0xFFU); +} + + +/** + \brief Get Fault Mask + \details Returns the current value of the Fault Mask register. + \return Fault Mask register value + */ +__STATIC_INLINE uint32_t __get_FAULTMASK(void) +{ + register uint32_t __regFaultMask __ASM("faultmask"); + return(__regFaultMask); +} + + +/** + \brief Set Fault Mask + \details Assigns the given value to the Fault Mask register. + \param [in] faultMask Fault Mask value to set + */ +__STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask) +{ + register uint32_t __regFaultMask __ASM("faultmask"); + __regFaultMask = (faultMask & (uint32_t)1U); +} + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */ + + +/** + \brief Get FPSCR + \details Returns the current value of the Floating Point Status/Control register. + \return Floating Point Status/Control register value + */ +__STATIC_INLINE uint32_t __get_FPSCR(void) +{ +#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) + register uint32_t __regfpscr __ASM("fpscr"); + return(__regfpscr); +#else + return(0U); +#endif +} + + +/** + \brief Set FPSCR + \details Assigns the given value to the Floating Point Status/Control register. + \param [in] fpscr Floating Point Status/Control value to set + */ +__STATIC_INLINE void __set_FPSCR(uint32_t fpscr) +{ +#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) + register uint32_t __regfpscr __ASM("fpscr"); + __regfpscr = (fpscr); +#else + (void)fpscr; +#endif +} + + +/*@} end of CMSIS_Core_RegAccFunctions */ + + +/* ########################## Core Instruction Access ######################### */ +/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface + Access to dedicated instructions + @{ +*/ + +/** + \brief No Operation + \details No Operation does nothing. This instruction can be used for code alignment purposes. + */ +#define __NOP __nop + + +/** + \brief Wait For Interrupt + \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs. + */ +#define __WFI __wfi + + +/** + \brief Wait For Event + \details Wait For Event is a hint instruction that permits the processor to enter + a low-power state until one of a number of events occurs. + */ +#define __WFE __wfe + + +/** + \brief Send Event + \details Send Event is a hint instruction. It causes an event to be signaled to the CPU. + */ +#define __SEV __sev + + +/** + \brief Instruction Synchronization Barrier + \details Instruction Synchronization Barrier flushes the pipeline in the processor, + so that all instructions following the ISB are fetched from cache or memory, + after the instruction has been completed. + */ +#define __ISB() __isb(0xF) + +/** + \brief Data Synchronization Barrier + \details Acts as a special kind of Data Memory Barrier. + It completes when all explicit memory accesses before this instruction complete. + */ +#define __DSB() __dsb(0xF) + +/** + \brief Data Memory Barrier + \details Ensures the apparent order of the explicit memory operations before + and after the instruction, without ensuring their completion. + */ +#define __DMB() __dmb(0xF) + + +/** + \brief Reverse byte order (32 bit) + \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412. + \param [in] value Value to reverse + \return Reversed value + */ +#define __REV __rev + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856. + \param [in] value Value to reverse + \return Reversed value + */ +#ifndef __NO_EMBEDDED_ASM +__attribute__((section(".rev16_text"))) __STATIC_INLINE __ASM uint32_t __REV16(uint32_t value) +{ + rev16 r0, r0 + bx lr +} +#endif + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000. + \param [in] value Value to reverse + \return Reversed value + */ +#ifndef __NO_EMBEDDED_ASM +__attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int16_t __REVSH(int16_t value) +{ + revsh r0, r0 + bx lr +} +#endif + + +/** + \brief Rotate Right in unsigned value (32 bit) + \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. + \param [in] op1 Value to rotate + \param [in] op2 Number of Bits to rotate + \return Rotated value + */ +#define __ROR __ror + + +/** + \brief Breakpoint + \details Causes the processor to enter Debug state. + Debug tools can use this to investigate system state when the instruction at a particular address is reached. + \param [in] value is ignored by the processor. + If required, a debugger can use it to store additional information about the breakpoint. + */ +#define __BKPT(value) __breakpoint(value) + + +/** + \brief Reverse bit order of value + \details Reverses the bit order of the given value. + \param [in] value Value to reverse + \return Reversed value + */ +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) + #define __RBIT __rbit +#else +__attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value) +{ + uint32_t result; + uint32_t s = (4U /*sizeof(v)*/ * 8U) - 1U; /* extra shift needed at end */ + + result = value; /* r will be reversed bits of v; first get LSB of v */ + for (value >>= 1U; value != 0U; value >>= 1U) + { + result <<= 1U; + result |= value & 1U; + s--; + } + result <<= s; /* shift when v's highest bits are zero */ + return result; +} +#endif + + +/** + \brief Count leading zeros + \details Counts the number of leading zeros of a data value. + \param [in] value Value to count the leading zeros + \return number of leading zeros in value + */ +#define __CLZ __clz + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) + +/** + \brief LDR Exclusive (8 bit) + \details Executes a exclusive LDR instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) + #define __LDREXB(ptr) ((uint8_t ) __ldrex(ptr)) +#else + #define __LDREXB(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint8_t ) __ldrex(ptr)) _Pragma("pop") +#endif + + +/** + \brief LDR Exclusive (16 bit) + \details Executes a exclusive LDR instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) + #define __LDREXH(ptr) ((uint16_t) __ldrex(ptr)) +#else + #define __LDREXH(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint16_t) __ldrex(ptr)) _Pragma("pop") +#endif + + +/** + \brief LDR Exclusive (32 bit) + \details Executes a exclusive LDR instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) + #define __LDREXW(ptr) ((uint32_t ) __ldrex(ptr)) +#else + #define __LDREXW(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint32_t ) __ldrex(ptr)) _Pragma("pop") +#endif + + +/** + \brief STR Exclusive (8 bit) + \details Executes a exclusive STR instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) + #define __STREXB(value, ptr) __strex(value, ptr) +#else + #define __STREXB(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop") +#endif + + +/** + \brief STR Exclusive (16 bit) + \details Executes a exclusive STR instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) + #define __STREXH(value, ptr) __strex(value, ptr) +#else + #define __STREXH(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop") +#endif + + +/** + \brief STR Exclusive (32 bit) + \details Executes a exclusive STR instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) + #define __STREXW(value, ptr) __strex(value, ptr) +#else + #define __STREXW(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop") +#endif + + +/** + \brief Remove the exclusive lock + \details Removes the exclusive lock which is created by LDREX. + */ +#define __CLREX __clrex + + +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +#define __SSAT __ssat + + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +#define __USAT __usat + + +/** + \brief Rotate Right with Extend (32 bit) + \details Moves each bit of a bitstring right by one bit. + The carry input is shifted in at the left end of the bitstring. + \param [in] value Value to rotate + \return Rotated value + */ +#ifndef __NO_EMBEDDED_ASM +__attribute__((section(".rrx_text"))) __STATIC_INLINE __ASM uint32_t __RRX(uint32_t value) +{ + rrx r0, r0 + bx lr +} +#endif + + +/** + \brief LDRT Unprivileged (8 bit) + \details Executes a Unprivileged LDRT instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +#define __LDRBT(ptr) ((uint8_t ) __ldrt(ptr)) + + +/** + \brief LDRT Unprivileged (16 bit) + \details Executes a Unprivileged LDRT instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +#define __LDRHT(ptr) ((uint16_t) __ldrt(ptr)) + + +/** + \brief LDRT Unprivileged (32 bit) + \details Executes a Unprivileged LDRT instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +#define __LDRT(ptr) ((uint32_t ) __ldrt(ptr)) + + +/** + \brief STRT Unprivileged (8 bit) + \details Executes a Unprivileged STRT instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +#define __STRBT(value, ptr) __strt(value, ptr) + + +/** + \brief STRT Unprivileged (16 bit) + \details Executes a Unprivileged STRT instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +#define __STRHT(value, ptr) __strt(value, ptr) + + +/** + \brief STRT Unprivileged (32 bit) + \details Executes a Unprivileged STRT instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +#define __STRT(value, ptr) __strt(value, ptr) + +#else /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */ + +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +__attribute__((always_inline)) __STATIC_INLINE int32_t __SSAT(int32_t val, uint32_t sat) +{ + if ((sat >= 1U) && (sat <= 32U)) + { + const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U); + const int32_t min = -1 - max ; + if (val > max) + { + return max; + } + else if (val < min) + { + return min; + } + } + return val; +} + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __USAT(int32_t val, uint32_t sat) +{ + if (sat <= 31U) + { + const uint32_t max = ((1U << sat) - 1U); + if (val > (int32_t)max) + { + return max; + } + else if (val < 0) + { + return 0U; + } + } + return (uint32_t)val; +} + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */ + +/*@}*/ /* end of group CMSIS_Core_InstructionInterface */ + + +/* ################### Compiler specific Intrinsics ########################### */ +/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics + Access to dedicated SIMD instructions + @{ +*/ + +#if ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) + +#define __SADD8 __sadd8 +#define __QADD8 __qadd8 +#define __SHADD8 __shadd8 +#define __UADD8 __uadd8 +#define __UQADD8 __uqadd8 +#define __UHADD8 __uhadd8 +#define __SSUB8 __ssub8 +#define __QSUB8 __qsub8 +#define __SHSUB8 __shsub8 +#define __USUB8 __usub8 +#define __UQSUB8 __uqsub8 +#define __UHSUB8 __uhsub8 +#define __SADD16 __sadd16 +#define __QADD16 __qadd16 +#define __SHADD16 __shadd16 +#define __UADD16 __uadd16 +#define __UQADD16 __uqadd16 +#define __UHADD16 __uhadd16 +#define __SSUB16 __ssub16 +#define __QSUB16 __qsub16 +#define __SHSUB16 __shsub16 +#define __USUB16 __usub16 +#define __UQSUB16 __uqsub16 +#define __UHSUB16 __uhsub16 +#define __SASX __sasx +#define __QASX __qasx +#define __SHASX __shasx +#define __UASX __uasx +#define __UQASX __uqasx +#define __UHASX __uhasx +#define __SSAX __ssax +#define __QSAX __qsax +#define __SHSAX __shsax +#define __USAX __usax +#define __UQSAX __uqsax +#define __UHSAX __uhsax +#define __USAD8 __usad8 +#define __USADA8 __usada8 +#define __SSAT16 __ssat16 +#define __USAT16 __usat16 +#define __UXTB16 __uxtb16 +#define __UXTAB16 __uxtab16 +#define __SXTB16 __sxtb16 +#define __SXTAB16 __sxtab16 +#define __SMUAD __smuad +#define __SMUADX __smuadx +#define __SMLAD __smlad +#define __SMLADX __smladx +#define __SMLALD __smlald +#define __SMLALDX __smlaldx +#define __SMUSD __smusd +#define __SMUSDX __smusdx +#define __SMLSD __smlsd +#define __SMLSDX __smlsdx +#define __SMLSLD __smlsld +#define __SMLSLDX __smlsldx +#define __SEL __sel +#define __QADD __qadd +#define __QSUB __qsub + +#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \ + ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) ) + +#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \ + ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) ) + +#define __SMMLA(ARG1,ARG2,ARG3) ( (int32_t)((((int64_t)(ARG1) * (ARG2)) + \ + ((int64_t)(ARG3) << 32U) ) >> 32U)) + +#define __SXTB16_RORn(ARG1, ARG2) __SXTB16(__ROR(ARG1, ARG2)) + +#endif /* ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */ +/*@} end of group CMSIS_SIMD_intrinsics */ + + +#endif /* __CMSIS_ARMCC_H */ diff --git a/bootloader/inc/cmsis_armclang.h b/bootloader/inc/cmsis_armclang.h new file mode 100644 index 0000000..6bb8a4f --- /dev/null +++ b/bootloader/inc/cmsis_armclang.h @@ -0,0 +1,1446 @@ +/**************************************************************************//** + * @file cmsis_armclang.h + * @brief CMSIS compiler armclang (Arm Compiler 6) header file + * @version V5.3.0 + * @date 28. January 2020 + ******************************************************************************/ +/* + * Copyright (c) 2009-2019 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/*lint -esym(9058, IRQn)*/ /* disable MISRA 2012 Rule 2.4 for IRQn */ + +#ifndef __CMSIS_ARMCLANG_H +#define __CMSIS_ARMCLANG_H + +#pragma clang system_header /* treat file as system include file */ + +#ifndef __ARM_COMPAT_H +#include /* Compatibility header for Arm Compiler 5 intrinsics */ +#endif + +/* CMSIS compiler specific defines */ +#ifndef __ASM + #define __ASM __asm +#endif +#ifndef __INLINE + #define __INLINE __inline +#endif +#ifndef __STATIC_INLINE + #define __STATIC_INLINE static __inline +#endif +#ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __attribute__((always_inline)) static __inline +#endif +#ifndef __NO_RETURN + #define __NO_RETURN __attribute__((__noreturn__)) +#endif +#ifndef __USED + #define __USED __attribute__((used)) +#endif +#ifndef __WEAK + #define __WEAK __attribute__((weak)) +#endif +#ifndef __PACKED + #define __PACKED __attribute__((packed, aligned(1))) +#endif +#ifndef __PACKED_STRUCT + #define __PACKED_STRUCT struct __attribute__((packed, aligned(1))) +#endif +#ifndef __PACKED_UNION + #define __PACKED_UNION union __attribute__((packed, aligned(1))) +#endif +#ifndef __UNALIGNED_UINT32 /* deprecated */ + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT32)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32 */ + struct __attribute__((packed)) T_UINT32 { uint32_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) +#endif +#ifndef __UNALIGNED_UINT16_WRITE + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT16_WRITE)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT16_WRITE */ + __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val)) +#endif +#ifndef __UNALIGNED_UINT16_READ + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT16_READ)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT16_READ */ + __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) +#endif +#ifndef __UNALIGNED_UINT32_WRITE + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT32_WRITE)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32_WRITE */ + __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) +#endif +#ifndef __UNALIGNED_UINT32_READ + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT32_READ)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32_READ */ + __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) +#endif +#ifndef __ALIGNED + #define __ALIGNED(x) __attribute__((aligned(x))) +#endif +#ifndef __RESTRICT + #define __RESTRICT __restrict +#endif +#ifndef __COMPILER_BARRIER + #define __COMPILER_BARRIER() __ASM volatile("":::"memory") +#endif + +/* ######################### Startup and Lowlevel Init ######################## */ + +#ifndef __PROGRAM_START +#define __PROGRAM_START __main +#endif + +#ifndef __INITIAL_SP +#define __INITIAL_SP Image$$ARM_LIB_STACK$$ZI$$Limit +#endif + +#ifndef __STACK_LIMIT +#define __STACK_LIMIT Image$$ARM_LIB_STACK$$ZI$$Base +#endif + +#ifndef __VECTOR_TABLE +#define __VECTOR_TABLE __Vectors +#endif + +#ifndef __VECTOR_TABLE_ATTRIBUTE +#define __VECTOR_TABLE_ATTRIBUTE __attribute((used, section("RESET"))) +#endif + +/* ########################### Core Function Access ########################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions + @{ + */ + +/** + \brief Enable IRQ Interrupts + \details Enables IRQ interrupts by clearing the I-bit in the CPSR. + Can only be executed in Privileged modes. + */ +/* intrinsic void __enable_irq(); see arm_compat.h */ + + +/** + \brief Disable IRQ Interrupts + \details Disables IRQ interrupts by setting the I-bit in the CPSR. + Can only be executed in Privileged modes. + */ +/* intrinsic void __disable_irq(); see arm_compat.h */ + + +/** + \brief Get Control Register + \details Returns the content of the Control Register. + \return Control Register value + */ +__STATIC_FORCEINLINE uint32_t __get_CONTROL(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, control" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Control Register (non-secure) + \details Returns the content of the non-secure Control Register when in secure mode. + \return non-secure Control Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_CONTROL_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, control_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Control Register + \details Writes the given value to the Control Register. + \param [in] control Control Register value to set + */ +__STATIC_FORCEINLINE void __set_CONTROL(uint32_t control) +{ + __ASM volatile ("MSR control, %0" : : "r" (control) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Control Register (non-secure) + \details Writes the given value to the non-secure Control Register when in secure state. + \param [in] control Control Register value to set + */ +__STATIC_FORCEINLINE void __TZ_set_CONTROL_NS(uint32_t control) +{ + __ASM volatile ("MSR control_ns, %0" : : "r" (control) : "memory"); +} +#endif + + +/** + \brief Get IPSR Register + \details Returns the content of the IPSR Register. + \return IPSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_IPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, ipsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get APSR Register + \details Returns the content of the APSR Register. + \return APSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_APSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, apsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get xPSR Register + \details Returns the content of the xPSR Register. + \return xPSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_xPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, xpsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get Process Stack Pointer + \details Returns the current value of the Process Stack Pointer (PSP). + \return PSP Register value + */ +__STATIC_FORCEINLINE uint32_t __get_PSP(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, psp" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Process Stack Pointer (non-secure) + \details Returns the current value of the non-secure Process Stack Pointer (PSP) when in secure state. + \return PSP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PSP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, psp_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Process Stack Pointer + \details Assigns the given value to the Process Stack Pointer (PSP). + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __set_PSP(uint32_t topOfProcStack) +{ + __ASM volatile ("MSR psp, %0" : : "r" (topOfProcStack) : ); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Process Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Process Stack Pointer (PSP) when in secure state. + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_PSP_NS(uint32_t topOfProcStack) +{ + __ASM volatile ("MSR psp_ns, %0" : : "r" (topOfProcStack) : ); +} +#endif + + +/** + \brief Get Main Stack Pointer + \details Returns the current value of the Main Stack Pointer (MSP). + \return MSP Register value + */ +__STATIC_FORCEINLINE uint32_t __get_MSP(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, msp" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Main Stack Pointer (non-secure) + \details Returns the current value of the non-secure Main Stack Pointer (MSP) when in secure state. + \return MSP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_MSP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, msp_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Main Stack Pointer + \details Assigns the given value to the Main Stack Pointer (MSP). + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __set_MSP(uint32_t topOfMainStack) +{ + __ASM volatile ("MSR msp, %0" : : "r" (topOfMainStack) : ); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Main Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Main Stack Pointer (MSP) when in secure state. + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_MSP_NS(uint32_t topOfMainStack) +{ + __ASM volatile ("MSR msp_ns, %0" : : "r" (topOfMainStack) : ); +} +#endif + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Stack Pointer (non-secure) + \details Returns the current value of the non-secure Stack Pointer (SP) when in secure state. + \return SP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_SP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, sp_ns" : "=r" (result) ); + return(result); +} + + +/** + \brief Set Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Stack Pointer (SP) when in secure state. + \param [in] topOfStack Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_SP_NS(uint32_t topOfStack) +{ + __ASM volatile ("MSR sp_ns, %0" : : "r" (topOfStack) : ); +} +#endif + + +/** + \brief Get Priority Mask + \details Returns the current state of the priority mask bit from the Priority Mask Register. + \return Priority Mask value + */ +__STATIC_FORCEINLINE uint32_t __get_PRIMASK(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, primask" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Priority Mask (non-secure) + \details Returns the current state of the non-secure priority mask bit from the Priority Mask Register when in secure state. + \return Priority Mask value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PRIMASK_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, primask_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Priority Mask + \details Assigns the given value to the Priority Mask Register. + \param [in] priMask Priority Mask + */ +__STATIC_FORCEINLINE void __set_PRIMASK(uint32_t priMask) +{ + __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Priority Mask (non-secure) + \details Assigns the given value to the non-secure Priority Mask Register when in secure state. + \param [in] priMask Priority Mask + */ +__STATIC_FORCEINLINE void __TZ_set_PRIMASK_NS(uint32_t priMask) +{ + __ASM volatile ("MSR primask_ns, %0" : : "r" (priMask) : "memory"); +} +#endif + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) +/** + \brief Enable FIQ + \details Enables FIQ interrupts by clearing the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +#define __enable_fault_irq __enable_fiq /* see arm_compat.h */ + + +/** + \brief Disable FIQ + \details Disables FIQ interrupts by setting the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +#define __disable_fault_irq __disable_fiq /* see arm_compat.h */ + + +/** + \brief Get Base Priority + \details Returns the current value of the Base Priority register. + \return Base Priority register value + */ +__STATIC_FORCEINLINE uint32_t __get_BASEPRI(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, basepri" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Base Priority (non-secure) + \details Returns the current value of the non-secure Base Priority register when in secure state. + \return Base Priority register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_BASEPRI_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, basepri_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Base Priority + \details Assigns the given value to the Base Priority register. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __set_BASEPRI(uint32_t basePri) +{ + __ASM volatile ("MSR basepri, %0" : : "r" (basePri) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Base Priority (non-secure) + \details Assigns the given value to the non-secure Base Priority register when in secure state. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __TZ_set_BASEPRI_NS(uint32_t basePri) +{ + __ASM volatile ("MSR basepri_ns, %0" : : "r" (basePri) : "memory"); +} +#endif + + +/** + \brief Set Base Priority with condition + \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled, + or the new value increases the BASEPRI priority level. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __set_BASEPRI_MAX(uint32_t basePri) +{ + __ASM volatile ("MSR basepri_max, %0" : : "r" (basePri) : "memory"); +} + + +/** + \brief Get Fault Mask + \details Returns the current value of the Fault Mask register. + \return Fault Mask register value + */ +__STATIC_FORCEINLINE uint32_t __get_FAULTMASK(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, faultmask" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Fault Mask (non-secure) + \details Returns the current value of the non-secure Fault Mask register when in secure state. + \return Fault Mask register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_FAULTMASK_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, faultmask_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Fault Mask + \details Assigns the given value to the Fault Mask register. + \param [in] faultMask Fault Mask value to set + */ +__STATIC_FORCEINLINE void __set_FAULTMASK(uint32_t faultMask) +{ + __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Fault Mask (non-secure) + \details Assigns the given value to the non-secure Fault Mask register when in secure state. + \param [in] faultMask Fault Mask value to set + */ +__STATIC_FORCEINLINE void __TZ_set_FAULTMASK_NS(uint32_t faultMask) +{ + __ASM volatile ("MSR faultmask_ns, %0" : : "r" (faultMask) : "memory"); +} +#endif + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) + +/** + \brief Get Process Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always in non-secure + mode. + + \details Returns the current value of the Process Stack Pointer Limit (PSPLIM). + \return PSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __get_PSPLIM(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, psplim" : "=r" (result) ); + return result; +#endif +} + +#if (defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Process Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always in non-secure + mode. + + \details Returns the current value of the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. + \return PSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PSPLIM_NS(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, psplim_ns" : "=r" (result) ); + return result; +#endif +} +#endif + + +/** + \brief Set Process Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored in non-secure + mode. + + \details Assigns the given value to the Process Stack Pointer Limit (PSPLIM). + \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __set_PSPLIM(uint32_t ProcStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + (void)ProcStackPtrLimit; +#else + __ASM volatile ("MSR psplim, %0" : : "r" (ProcStackPtrLimit)); +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Process Stack Pointer (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored in non-secure + mode. + + \details Assigns the given value to the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. + \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __TZ_set_PSPLIM_NS(uint32_t ProcStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + (void)ProcStackPtrLimit; +#else + __ASM volatile ("MSR psplim_ns, %0\n" : : "r" (ProcStackPtrLimit)); +#endif +} +#endif + + +/** + \brief Get Main Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always. + + \details Returns the current value of the Main Stack Pointer Limit (MSPLIM). + \return MSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __get_MSPLIM(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, msplim" : "=r" (result) ); + return result; +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Main Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always. + + \details Returns the current value of the non-secure Main Stack Pointer Limit(MSPLIM) when in secure state. + \return MSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_MSPLIM_NS(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, msplim_ns" : "=r" (result) ); + return result; +#endif +} +#endif + + +/** + \brief Set Main Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored. + + \details Assigns the given value to the Main Stack Pointer Limit (MSPLIM). + \param [in] MainStackPtrLimit Main Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __set_MSPLIM(uint32_t MainStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + (void)MainStackPtrLimit; +#else + __ASM volatile ("MSR msplim, %0" : : "r" (MainStackPtrLimit)); +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Main Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored. + + \details Assigns the given value to the non-secure Main Stack Pointer Limit (MSPLIM) when in secure state. + \param [in] MainStackPtrLimit Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + (void)MainStackPtrLimit; +#else + __ASM volatile ("MSR msplim_ns, %0" : : "r" (MainStackPtrLimit)); +#endif +} +#endif + +#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ + +/** + \brief Get FPSCR + \details Returns the current value of the Floating Point Status/Control register. + \return Floating Point Status/Control register value + */ +#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) +#define __get_FPSCR (uint32_t)__builtin_arm_get_fpscr +#else +#define __get_FPSCR() ((uint32_t)0U) +#endif + +/** + \brief Set FPSCR + \details Assigns the given value to the Floating Point Status/Control register. + \param [in] fpscr Floating Point Status/Control value to set + */ +#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) +#define __set_FPSCR __builtin_arm_set_fpscr +#else +#define __set_FPSCR(x) ((void)(x)) +#endif + + +/*@} end of CMSIS_Core_RegAccFunctions */ + + +/* ########################## Core Instruction Access ######################### */ +/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface + Access to dedicated instructions + @{ +*/ + +/* Define macros for porting to both thumb1 and thumb2. + * For thumb1, use low register (r0-r7), specified by constraint "l" + * Otherwise, use general registers, specified by constraint "r" */ +#if defined (__thumb__) && !defined (__thumb2__) +#define __CMSIS_GCC_OUT_REG(r) "=l" (r) +#define __CMSIS_GCC_RW_REG(r) "+l" (r) +#define __CMSIS_GCC_USE_REG(r) "l" (r) +#else +#define __CMSIS_GCC_OUT_REG(r) "=r" (r) +#define __CMSIS_GCC_RW_REG(r) "+r" (r) +#define __CMSIS_GCC_USE_REG(r) "r" (r) +#endif + +/** + \brief No Operation + \details No Operation does nothing. This instruction can be used for code alignment purposes. + */ +#define __NOP __builtin_arm_nop + +/** + \brief Wait For Interrupt + \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs. + */ +#define __WFI __builtin_arm_wfi + + +/** + \brief Wait For Event + \details Wait For Event is a hint instruction that permits the processor to enter + a low-power state until one of a number of events occurs. + */ +#define __WFE __builtin_arm_wfe + + +/** + \brief Send Event + \details Send Event is a hint instruction. It causes an event to be signaled to the CPU. + */ +#define __SEV __builtin_arm_sev + + +/** + \brief Instruction Synchronization Barrier + \details Instruction Synchronization Barrier flushes the pipeline in the processor, + so that all instructions following the ISB are fetched from cache or memory, + after the instruction has been completed. + */ +#define __ISB() __builtin_arm_isb(0xF) + +/** + \brief Data Synchronization Barrier + \details Acts as a special kind of Data Memory Barrier. + It completes when all explicit memory accesses before this instruction complete. + */ +#define __DSB() __builtin_arm_dsb(0xF) + + +/** + \brief Data Memory Barrier + \details Ensures the apparent order of the explicit memory operations before + and after the instruction, without ensuring their completion. + */ +#define __DMB() __builtin_arm_dmb(0xF) + + +/** + \brief Reverse byte order (32 bit) + \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412. + \param [in] value Value to reverse + \return Reversed value + */ +#define __REV(value) __builtin_bswap32(value) + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856. + \param [in] value Value to reverse + \return Reversed value + */ +#define __REV16(value) __ROR(__REV(value), 16) + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000. + \param [in] value Value to reverse + \return Reversed value + */ +#define __REVSH(value) (int16_t)__builtin_bswap16(value) + + +/** + \brief Rotate Right in unsigned value (32 bit) + \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. + \param [in] op1 Value to rotate + \param [in] op2 Number of Bits to rotate + \return Rotated value + */ +__STATIC_FORCEINLINE uint32_t __ROR(uint32_t op1, uint32_t op2) +{ + op2 %= 32U; + if (op2 == 0U) + { + return op1; + } + return (op1 >> op2) | (op1 << (32U - op2)); +} + + +/** + \brief Breakpoint + \details Causes the processor to enter Debug state. + Debug tools can use this to investigate system state when the instruction at a particular address is reached. + \param [in] value is ignored by the processor. + If required, a debugger can use it to store additional information about the breakpoint. + */ +#define __BKPT(value) __ASM volatile ("bkpt "#value) + + +/** + \brief Reverse bit order of value + \details Reverses the bit order of the given value. + \param [in] value Value to reverse + \return Reversed value + */ +#define __RBIT __builtin_arm_rbit + +/** + \brief Count leading zeros + \details Counts the number of leading zeros of a data value. + \param [in] value Value to count the leading zeros + \return number of leading zeros in value + */ +__STATIC_FORCEINLINE uint8_t __CLZ(uint32_t value) +{ + /* Even though __builtin_clz produces a CLZ instruction on ARM, formally + __builtin_clz(0) is undefined behaviour, so handle this case specially. + This guarantees ARM-compatible results if happening to compile on a non-ARM + target, and ensures the compiler doesn't decide to activate any + optimisations using the logic "value was passed to __builtin_clz, so it + is non-zero". + ARM Compiler 6.10 and possibly earlier will optimise this test away, leaving a + single CLZ instruction. + */ + if (value == 0U) + { + return 32U; + } + return __builtin_clz(value); +} + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) +/** + \brief LDR Exclusive (8 bit) + \details Executes a exclusive LDR instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +#define __LDREXB (uint8_t)__builtin_arm_ldrex + + +/** + \brief LDR Exclusive (16 bit) + \details Executes a exclusive LDR instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +#define __LDREXH (uint16_t)__builtin_arm_ldrex + + +/** + \brief LDR Exclusive (32 bit) + \details Executes a exclusive LDR instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +#define __LDREXW (uint32_t)__builtin_arm_ldrex + + +/** + \brief STR Exclusive (8 bit) + \details Executes a exclusive STR instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STREXB (uint32_t)__builtin_arm_strex + + +/** + \brief STR Exclusive (16 bit) + \details Executes a exclusive STR instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STREXH (uint32_t)__builtin_arm_strex + + +/** + \brief STR Exclusive (32 bit) + \details Executes a exclusive STR instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STREXW (uint32_t)__builtin_arm_strex + + +/** + \brief Remove the exclusive lock + \details Removes the exclusive lock which is created by LDREX. + */ +#define __CLREX __builtin_arm_clrex + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) + +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +#define __SSAT __builtin_arm_ssat + + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +#define __USAT __builtin_arm_usat + + +/** + \brief Rotate Right with Extend (32 bit) + \details Moves each bit of a bitstring right by one bit. + The carry input is shifted in at the left end of the bitstring. + \param [in] value Value to rotate + \return Rotated value + */ +__STATIC_FORCEINLINE uint32_t __RRX(uint32_t value) +{ + uint32_t result; + + __ASM volatile ("rrx %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return(result); +} + + +/** + \brief LDRT Unprivileged (8 bit) + \details Executes a Unprivileged LDRT instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDRBT(volatile uint8_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint8_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDRT Unprivileged (16 bit) + \details Executes a Unprivileged LDRT instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDRHT(volatile uint16_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint16_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDRT Unprivileged (32 bit) + \details Executes a Unprivileged LDRT instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDRT(volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*ptr) ); + return(result); +} + + +/** + \brief STRT Unprivileged (8 bit) + \details Executes a Unprivileged STRT instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRBT(uint8_t value, volatile uint8_t *ptr) +{ + __ASM volatile ("strbt %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief STRT Unprivileged (16 bit) + \details Executes a Unprivileged STRT instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRHT(uint16_t value, volatile uint16_t *ptr) +{ + __ASM volatile ("strht %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief STRT Unprivileged (32 bit) + \details Executes a Unprivileged STRT instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRT(uint32_t value, volatile uint32_t *ptr) +{ + __ASM volatile ("strt %1, %0" : "=Q" (*ptr) : "r" (value) ); +} + +#else /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +__STATIC_FORCEINLINE int32_t __SSAT(int32_t val, uint32_t sat) +{ + if ((sat >= 1U) && (sat <= 32U)) + { + const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U); + const int32_t min = -1 - max ; + if (val > max) + { + return max; + } + else if (val < min) + { + return min; + } + } + return val; +} + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +__STATIC_FORCEINLINE uint32_t __USAT(int32_t val, uint32_t sat) +{ + if (sat <= 31U) + { + const uint32_t max = ((1U << sat) - 1U); + if (val > (int32_t)max) + { + return max; + } + else if (val < 0) + { + return 0U; + } + } + return (uint32_t)val; +} + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) +/** + \brief Load-Acquire (8 bit) + \details Executes a LDAB instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDAB(volatile uint8_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldab %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); + return ((uint8_t) result); +} + + +/** + \brief Load-Acquire (16 bit) + \details Executes a LDAH instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDAH(volatile uint16_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldah %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); + return ((uint16_t) result); +} + + +/** + \brief Load-Acquire (32 bit) + \details Executes a LDA instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDA(volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("lda %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); + return(result); +} + + +/** + \brief Store-Release (8 bit) + \details Executes a STLB instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STLB(uint8_t value, volatile uint8_t *ptr) +{ + __ASM volatile ("stlb %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); +} + + +/** + \brief Store-Release (16 bit) + \details Executes a STLH instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STLH(uint16_t value, volatile uint16_t *ptr) +{ + __ASM volatile ("stlh %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); +} + + +/** + \brief Store-Release (32 bit) + \details Executes a STL instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STL(uint32_t value, volatile uint32_t *ptr) +{ + __ASM volatile ("stl %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); +} + + +/** + \brief Load-Acquire Exclusive (8 bit) + \details Executes a LDAB exclusive instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +#define __LDAEXB (uint8_t)__builtin_arm_ldaex + + +/** + \brief Load-Acquire Exclusive (16 bit) + \details Executes a LDAH exclusive instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +#define __LDAEXH (uint16_t)__builtin_arm_ldaex + + +/** + \brief Load-Acquire Exclusive (32 bit) + \details Executes a LDA exclusive instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +#define __LDAEX (uint32_t)__builtin_arm_ldaex + + +/** + \brief Store-Release Exclusive (8 bit) + \details Executes a STLB exclusive instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STLEXB (uint32_t)__builtin_arm_stlex + + +/** + \brief Store-Release Exclusive (16 bit) + \details Executes a STLH exclusive instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STLEXH (uint32_t)__builtin_arm_stlex + + +/** + \brief Store-Release Exclusive (32 bit) + \details Executes a STL exclusive instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STLEX (uint32_t)__builtin_arm_stlex + +#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ + +/*@}*/ /* end of group CMSIS_Core_InstructionInterface */ + + +/* ################### Compiler specific Intrinsics ########################### */ +/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics + Access to dedicated SIMD instructions + @{ +*/ + +#if (defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1)) + +#define __SADD8 __builtin_arm_sadd8 +#define __QADD8 __builtin_arm_qadd8 +#define __SHADD8 __builtin_arm_shadd8 +#define __UADD8 __builtin_arm_uadd8 +#define __UQADD8 __builtin_arm_uqadd8 +#define __UHADD8 __builtin_arm_uhadd8 +#define __SSUB8 __builtin_arm_ssub8 +#define __QSUB8 __builtin_arm_qsub8 +#define __SHSUB8 __builtin_arm_shsub8 +#define __USUB8 __builtin_arm_usub8 +#define __UQSUB8 __builtin_arm_uqsub8 +#define __UHSUB8 __builtin_arm_uhsub8 +#define __SADD16 __builtin_arm_sadd16 +#define __QADD16 __builtin_arm_qadd16 +#define __SHADD16 __builtin_arm_shadd16 +#define __UADD16 __builtin_arm_uadd16 +#define __UQADD16 __builtin_arm_uqadd16 +#define __UHADD16 __builtin_arm_uhadd16 +#define __SSUB16 __builtin_arm_ssub16 +#define __QSUB16 __builtin_arm_qsub16 +#define __SHSUB16 __builtin_arm_shsub16 +#define __USUB16 __builtin_arm_usub16 +#define __UQSUB16 __builtin_arm_uqsub16 +#define __UHSUB16 __builtin_arm_uhsub16 +#define __SASX __builtin_arm_sasx +#define __QASX __builtin_arm_qasx +#define __SHASX __builtin_arm_shasx +#define __UASX __builtin_arm_uasx +#define __UQASX __builtin_arm_uqasx +#define __UHASX __builtin_arm_uhasx +#define __SSAX __builtin_arm_ssax +#define __QSAX __builtin_arm_qsax +#define __SHSAX __builtin_arm_shsax +#define __USAX __builtin_arm_usax +#define __UQSAX __builtin_arm_uqsax +#define __UHSAX __builtin_arm_uhsax +#define __USAD8 __builtin_arm_usad8 +#define __USADA8 __builtin_arm_usada8 +#define __SSAT16 __builtin_arm_ssat16 +#define __USAT16 __builtin_arm_usat16 +#define __UXTB16 __builtin_arm_uxtb16 +#define __UXTAB16 __builtin_arm_uxtab16 +#define __SXTB16 __builtin_arm_sxtb16 +#define __SXTAB16 __builtin_arm_sxtab16 +#define __SMUAD __builtin_arm_smuad +#define __SMUADX __builtin_arm_smuadx +#define __SMLAD __builtin_arm_smlad +#define __SMLADX __builtin_arm_smladx +#define __SMLALD __builtin_arm_smlald +#define __SMLALDX __builtin_arm_smlaldx +#define __SMUSD __builtin_arm_smusd +#define __SMUSDX __builtin_arm_smusdx +#define __SMLSD __builtin_arm_smlsd +#define __SMLSDX __builtin_arm_smlsdx +#define __SMLSLD __builtin_arm_smlsld +#define __SMLSLDX __builtin_arm_smlsldx +#define __SEL __builtin_arm_sel +#define __QADD __builtin_arm_qadd +#define __QSUB __builtin_arm_qsub + +#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \ + ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) ) + +#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \ + ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) ) + +#define __SXTB16_RORn(ARG1, ARG2) __SXTB16(__ROR(ARG1, ARG2)) + +__STATIC_FORCEINLINE int32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3) +{ + int32_t result; + + __ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +#endif /* (__ARM_FEATURE_DSP == 1) */ +/*@} end of group CMSIS_SIMD_intrinsics */ + + +#endif /* __CMSIS_ARMCLANG_H */ diff --git a/bootloader/inc/cmsis_armclang_ltm.h b/bootloader/inc/cmsis_armclang_ltm.h new file mode 100644 index 0000000..45ed905 --- /dev/null +++ b/bootloader/inc/cmsis_armclang_ltm.h @@ -0,0 +1,1893 @@ +/**************************************************************************//** + * @file cmsis_armclang_ltm.h + * @brief CMSIS compiler armclang (Arm Compiler 6) header file + * @version V1.3.0 + * @date 28. January 2020 + ******************************************************************************/ +/* + * Copyright (c) 2018-2019 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/*lint -esym(9058, IRQn)*/ /* disable MISRA 2012 Rule 2.4 for IRQn */ + +#ifndef __CMSIS_ARMCLANG_H +#define __CMSIS_ARMCLANG_H + +#pragma clang system_header /* treat file as system include file */ + +#ifndef __ARM_COMPAT_H +#include /* Compatibility header for Arm Compiler 5 intrinsics */ +#endif + +/* CMSIS compiler specific defines */ +#ifndef __ASM + #define __ASM __asm +#endif +#ifndef __INLINE + #define __INLINE __inline +#endif +#ifndef __STATIC_INLINE + #define __STATIC_INLINE static __inline +#endif +#ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __attribute__((always_inline)) static __inline +#endif +#ifndef __NO_RETURN + #define __NO_RETURN __attribute__((__noreturn__)) +#endif +#ifndef __USED + #define __USED __attribute__((used)) +#endif +#ifndef __WEAK + #define __WEAK __attribute__((weak)) +#endif +#ifndef __PACKED + #define __PACKED __attribute__((packed, aligned(1))) +#endif +#ifndef __PACKED_STRUCT + #define __PACKED_STRUCT struct __attribute__((packed, aligned(1))) +#endif +#ifndef __PACKED_UNION + #define __PACKED_UNION union __attribute__((packed, aligned(1))) +#endif +#ifndef __UNALIGNED_UINT32 /* deprecated */ + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT32)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32 */ + struct __attribute__((packed)) T_UINT32 { uint32_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) +#endif +#ifndef __UNALIGNED_UINT16_WRITE + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT16_WRITE)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT16_WRITE */ + __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val)) +#endif +#ifndef __UNALIGNED_UINT16_READ + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT16_READ)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT16_READ */ + __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) +#endif +#ifndef __UNALIGNED_UINT32_WRITE + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT32_WRITE)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32_WRITE */ + __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) +#endif +#ifndef __UNALIGNED_UINT32_READ + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT32_READ)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32_READ */ + __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) +#endif +#ifndef __ALIGNED + #define __ALIGNED(x) __attribute__((aligned(x))) +#endif +#ifndef __RESTRICT + #define __RESTRICT __restrict +#endif +#ifndef __COMPILER_BARRIER + #define __COMPILER_BARRIER() __ASM volatile("":::"memory") +#endif + +/* ######################### Startup and Lowlevel Init ######################## */ + +#ifndef __PROGRAM_START +#define __PROGRAM_START __main +#endif + +#ifndef __INITIAL_SP +#define __INITIAL_SP Image$$ARM_LIB_STACK$$ZI$$Limit +#endif + +#ifndef __STACK_LIMIT +#define __STACK_LIMIT Image$$ARM_LIB_STACK$$ZI$$Base +#endif + +#ifndef __VECTOR_TABLE +#define __VECTOR_TABLE __Vectors +#endif + +#ifndef __VECTOR_TABLE_ATTRIBUTE +#define __VECTOR_TABLE_ATTRIBUTE __attribute((used, section("RESET"))) +#endif + + +/* ########################### Core Function Access ########################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions + @{ + */ + +/** + \brief Enable IRQ Interrupts + \details Enables IRQ interrupts by clearing the I-bit in the CPSR. + Can only be executed in Privileged modes. + */ +/* intrinsic void __enable_irq(); see arm_compat.h */ + + +/** + \brief Disable IRQ Interrupts + \details Disables IRQ interrupts by setting the I-bit in the CPSR. + Can only be executed in Privileged modes. + */ +/* intrinsic void __disable_irq(); see arm_compat.h */ + + +/** + \brief Get Control Register + \details Returns the content of the Control Register. + \return Control Register value + */ +__STATIC_FORCEINLINE uint32_t __get_CONTROL(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, control" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Control Register (non-secure) + \details Returns the content of the non-secure Control Register when in secure mode. + \return non-secure Control Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_CONTROL_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, control_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Control Register + \details Writes the given value to the Control Register. + \param [in] control Control Register value to set + */ +__STATIC_FORCEINLINE void __set_CONTROL(uint32_t control) +{ + __ASM volatile ("MSR control, %0" : : "r" (control) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Control Register (non-secure) + \details Writes the given value to the non-secure Control Register when in secure state. + \param [in] control Control Register value to set + */ +__STATIC_FORCEINLINE void __TZ_set_CONTROL_NS(uint32_t control) +{ + __ASM volatile ("MSR control_ns, %0" : : "r" (control) : "memory"); +} +#endif + + +/** + \brief Get IPSR Register + \details Returns the content of the IPSR Register. + \return IPSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_IPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, ipsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get APSR Register + \details Returns the content of the APSR Register. + \return APSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_APSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, apsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get xPSR Register + \details Returns the content of the xPSR Register. + \return xPSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_xPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, xpsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get Process Stack Pointer + \details Returns the current value of the Process Stack Pointer (PSP). + \return PSP Register value + */ +__STATIC_FORCEINLINE uint32_t __get_PSP(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, psp" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Process Stack Pointer (non-secure) + \details Returns the current value of the non-secure Process Stack Pointer (PSP) when in secure state. + \return PSP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PSP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, psp_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Process Stack Pointer + \details Assigns the given value to the Process Stack Pointer (PSP). + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __set_PSP(uint32_t topOfProcStack) +{ + __ASM volatile ("MSR psp, %0" : : "r" (topOfProcStack) : ); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Process Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Process Stack Pointer (PSP) when in secure state. + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_PSP_NS(uint32_t topOfProcStack) +{ + __ASM volatile ("MSR psp_ns, %0" : : "r" (topOfProcStack) : ); +} +#endif + + +/** + \brief Get Main Stack Pointer + \details Returns the current value of the Main Stack Pointer (MSP). + \return MSP Register value + */ +__STATIC_FORCEINLINE uint32_t __get_MSP(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, msp" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Main Stack Pointer (non-secure) + \details Returns the current value of the non-secure Main Stack Pointer (MSP) when in secure state. + \return MSP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_MSP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, msp_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Main Stack Pointer + \details Assigns the given value to the Main Stack Pointer (MSP). + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __set_MSP(uint32_t topOfMainStack) +{ + __ASM volatile ("MSR msp, %0" : : "r" (topOfMainStack) : ); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Main Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Main Stack Pointer (MSP) when in secure state. + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_MSP_NS(uint32_t topOfMainStack) +{ + __ASM volatile ("MSR msp_ns, %0" : : "r" (topOfMainStack) : ); +} +#endif + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Stack Pointer (non-secure) + \details Returns the current value of the non-secure Stack Pointer (SP) when in secure state. + \return SP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_SP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, sp_ns" : "=r" (result) ); + return(result); +} + + +/** + \brief Set Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Stack Pointer (SP) when in secure state. + \param [in] topOfStack Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_SP_NS(uint32_t topOfStack) +{ + __ASM volatile ("MSR sp_ns, %0" : : "r" (topOfStack) : ); +} +#endif + + +/** + \brief Get Priority Mask + \details Returns the current state of the priority mask bit from the Priority Mask Register. + \return Priority Mask value + */ +__STATIC_FORCEINLINE uint32_t __get_PRIMASK(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, primask" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Priority Mask (non-secure) + \details Returns the current state of the non-secure priority mask bit from the Priority Mask Register when in secure state. + \return Priority Mask value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PRIMASK_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, primask_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Priority Mask + \details Assigns the given value to the Priority Mask Register. + \param [in] priMask Priority Mask + */ +__STATIC_FORCEINLINE void __set_PRIMASK(uint32_t priMask) +{ + __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Priority Mask (non-secure) + \details Assigns the given value to the non-secure Priority Mask Register when in secure state. + \param [in] priMask Priority Mask + */ +__STATIC_FORCEINLINE void __TZ_set_PRIMASK_NS(uint32_t priMask) +{ + __ASM volatile ("MSR primask_ns, %0" : : "r" (priMask) : "memory"); +} +#endif + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) +/** + \brief Enable FIQ + \details Enables FIQ interrupts by clearing the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +#define __enable_fault_irq __enable_fiq /* see arm_compat.h */ + + +/** + \brief Disable FIQ + \details Disables FIQ interrupts by setting the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +#define __disable_fault_irq __disable_fiq /* see arm_compat.h */ + + +/** + \brief Get Base Priority + \details Returns the current value of the Base Priority register. + \return Base Priority register value + */ +__STATIC_FORCEINLINE uint32_t __get_BASEPRI(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, basepri" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Base Priority (non-secure) + \details Returns the current value of the non-secure Base Priority register when in secure state. + \return Base Priority register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_BASEPRI_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, basepri_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Base Priority + \details Assigns the given value to the Base Priority register. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __set_BASEPRI(uint32_t basePri) +{ + __ASM volatile ("MSR basepri, %0" : : "r" (basePri) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Base Priority (non-secure) + \details Assigns the given value to the non-secure Base Priority register when in secure state. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __TZ_set_BASEPRI_NS(uint32_t basePri) +{ + __ASM volatile ("MSR basepri_ns, %0" : : "r" (basePri) : "memory"); +} +#endif + + +/** + \brief Set Base Priority with condition + \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled, + or the new value increases the BASEPRI priority level. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __set_BASEPRI_MAX(uint32_t basePri) +{ + __ASM volatile ("MSR basepri_max, %0" : : "r" (basePri) : "memory"); +} + + +/** + \brief Get Fault Mask + \details Returns the current value of the Fault Mask register. + \return Fault Mask register value + */ +__STATIC_FORCEINLINE uint32_t __get_FAULTMASK(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, faultmask" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Fault Mask (non-secure) + \details Returns the current value of the non-secure Fault Mask register when in secure state. + \return Fault Mask register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_FAULTMASK_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, faultmask_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Fault Mask + \details Assigns the given value to the Fault Mask register. + \param [in] faultMask Fault Mask value to set + */ +__STATIC_FORCEINLINE void __set_FAULTMASK(uint32_t faultMask) +{ + __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Fault Mask (non-secure) + \details Assigns the given value to the non-secure Fault Mask register when in secure state. + \param [in] faultMask Fault Mask value to set + */ +__STATIC_FORCEINLINE void __TZ_set_FAULTMASK_NS(uint32_t faultMask) +{ + __ASM volatile ("MSR faultmask_ns, %0" : : "r" (faultMask) : "memory"); +} +#endif + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) + +/** + \brief Get Process Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always in non-secure + mode. + + \details Returns the current value of the Process Stack Pointer Limit (PSPLIM). + \return PSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __get_PSPLIM(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, psplim" : "=r" (result) ); + return result; +#endif +} + +#if (defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Process Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always in non-secure + mode. + + \details Returns the current value of the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. + \return PSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PSPLIM_NS(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, psplim_ns" : "=r" (result) ); + return result; +#endif +} +#endif + + +/** + \brief Set Process Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored in non-secure + mode. + + \details Assigns the given value to the Process Stack Pointer Limit (PSPLIM). + \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __set_PSPLIM(uint32_t ProcStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + (void)ProcStackPtrLimit; +#else + __ASM volatile ("MSR psplim, %0" : : "r" (ProcStackPtrLimit)); +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Process Stack Pointer (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored in non-secure + mode. + + \details Assigns the given value to the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. + \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __TZ_set_PSPLIM_NS(uint32_t ProcStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + (void)ProcStackPtrLimit; +#else + __ASM volatile ("MSR psplim_ns, %0\n" : : "r" (ProcStackPtrLimit)); +#endif +} +#endif + + +/** + \brief Get Main Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always. + + \details Returns the current value of the Main Stack Pointer Limit (MSPLIM). + \return MSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __get_MSPLIM(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, msplim" : "=r" (result) ); + return result; +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Main Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always. + + \details Returns the current value of the non-secure Main Stack Pointer Limit(MSPLIM) when in secure state. + \return MSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_MSPLIM_NS(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, msplim_ns" : "=r" (result) ); + return result; +#endif +} +#endif + + +/** + \brief Set Main Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored. + + \details Assigns the given value to the Main Stack Pointer Limit (MSPLIM). + \param [in] MainStackPtrLimit Main Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __set_MSPLIM(uint32_t MainStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + (void)MainStackPtrLimit; +#else + __ASM volatile ("MSR msplim, %0" : : "r" (MainStackPtrLimit)); +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Main Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored. + + \details Assigns the given value to the non-secure Main Stack Pointer Limit (MSPLIM) when in secure state. + \param [in] MainStackPtrLimit Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + (void)MainStackPtrLimit; +#else + __ASM volatile ("MSR msplim_ns, %0" : : "r" (MainStackPtrLimit)); +#endif +} +#endif + +#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ + +/** + \brief Get FPSCR + \details Returns the current value of the Floating Point Status/Control register. + \return Floating Point Status/Control register value + */ +#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) +#define __get_FPSCR (uint32_t)__builtin_arm_get_fpscr +#else +#define __get_FPSCR() ((uint32_t)0U) +#endif + +/** + \brief Set FPSCR + \details Assigns the given value to the Floating Point Status/Control register. + \param [in] fpscr Floating Point Status/Control value to set + */ +#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) +#define __set_FPSCR __builtin_arm_set_fpscr +#else +#define __set_FPSCR(x) ((void)(x)) +#endif + + +/*@} end of CMSIS_Core_RegAccFunctions */ + + +/* ########################## Core Instruction Access ######################### */ +/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface + Access to dedicated instructions + @{ +*/ + +/* Define macros for porting to both thumb1 and thumb2. + * For thumb1, use low register (r0-r7), specified by constraint "l" + * Otherwise, use general registers, specified by constraint "r" */ +#if defined (__thumb__) && !defined (__thumb2__) +#define __CMSIS_GCC_OUT_REG(r) "=l" (r) +#define __CMSIS_GCC_USE_REG(r) "l" (r) +#else +#define __CMSIS_GCC_OUT_REG(r) "=r" (r) +#define __CMSIS_GCC_USE_REG(r) "r" (r) +#endif + +/** + \brief No Operation + \details No Operation does nothing. This instruction can be used for code alignment purposes. + */ +#define __NOP __builtin_arm_nop + +/** + \brief Wait For Interrupt + \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs. + */ +#define __WFI __builtin_arm_wfi + + +/** + \brief Wait For Event + \details Wait For Event is a hint instruction that permits the processor to enter + a low-power state until one of a number of events occurs. + */ +#define __WFE __builtin_arm_wfe + + +/** + \brief Send Event + \details Send Event is a hint instruction. It causes an event to be signaled to the CPU. + */ +#define __SEV __builtin_arm_sev + + +/** + \brief Instruction Synchronization Barrier + \details Instruction Synchronization Barrier flushes the pipeline in the processor, + so that all instructions following the ISB are fetched from cache or memory, + after the instruction has been completed. + */ +#define __ISB() __builtin_arm_isb(0xF) + +/** + \brief Data Synchronization Barrier + \details Acts as a special kind of Data Memory Barrier. + It completes when all explicit memory accesses before this instruction complete. + */ +#define __DSB() __builtin_arm_dsb(0xF) + + +/** + \brief Data Memory Barrier + \details Ensures the apparent order of the explicit memory operations before + and after the instruction, without ensuring their completion. + */ +#define __DMB() __builtin_arm_dmb(0xF) + + +/** + \brief Reverse byte order (32 bit) + \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412. + \param [in] value Value to reverse + \return Reversed value + */ +#define __REV(value) __builtin_bswap32(value) + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856. + \param [in] value Value to reverse + \return Reversed value + */ +#define __REV16(value) __ROR(__REV(value), 16) + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000. + \param [in] value Value to reverse + \return Reversed value + */ +#define __REVSH(value) (int16_t)__builtin_bswap16(value) + + +/** + \brief Rotate Right in unsigned value (32 bit) + \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. + \param [in] op1 Value to rotate + \param [in] op2 Number of Bits to rotate + \return Rotated value + */ +__STATIC_FORCEINLINE uint32_t __ROR(uint32_t op1, uint32_t op2) +{ + op2 %= 32U; + if (op2 == 0U) + { + return op1; + } + return (op1 >> op2) | (op1 << (32U - op2)); +} + + +/** + \brief Breakpoint + \details Causes the processor to enter Debug state. + Debug tools can use this to investigate system state when the instruction at a particular address is reached. + \param [in] value is ignored by the processor. + If required, a debugger can use it to store additional information about the breakpoint. + */ +#define __BKPT(value) __ASM volatile ("bkpt "#value) + + +/** + \brief Reverse bit order of value + \details Reverses the bit order of the given value. + \param [in] value Value to reverse + \return Reversed value + */ +#define __RBIT __builtin_arm_rbit + +/** + \brief Count leading zeros + \details Counts the number of leading zeros of a data value. + \param [in] value Value to count the leading zeros + \return number of leading zeros in value + */ +__STATIC_FORCEINLINE uint8_t __CLZ(uint32_t value) +{ + /* Even though __builtin_clz produces a CLZ instruction on ARM, formally + __builtin_clz(0) is undefined behaviour, so handle this case specially. + This guarantees ARM-compatible results if happening to compile on a non-ARM + target, and ensures the compiler doesn't decide to activate any + optimisations using the logic "value was passed to __builtin_clz, so it + is non-zero". + ARM Compiler 6.10 and possibly earlier will optimise this test away, leaving a + single CLZ instruction. + */ + if (value == 0U) + { + return 32U; + } + return __builtin_clz(value); +} + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) +/** + \brief LDR Exclusive (8 bit) + \details Executes a exclusive LDR instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +#define __LDREXB (uint8_t)__builtin_arm_ldrex + + +/** + \brief LDR Exclusive (16 bit) + \details Executes a exclusive LDR instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +#define __LDREXH (uint16_t)__builtin_arm_ldrex + + +/** + \brief LDR Exclusive (32 bit) + \details Executes a exclusive LDR instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +#define __LDREXW (uint32_t)__builtin_arm_ldrex + + +/** + \brief STR Exclusive (8 bit) + \details Executes a exclusive STR instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STREXB (uint32_t)__builtin_arm_strex + + +/** + \brief STR Exclusive (16 bit) + \details Executes a exclusive STR instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STREXH (uint32_t)__builtin_arm_strex + + +/** + \brief STR Exclusive (32 bit) + \details Executes a exclusive STR instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STREXW (uint32_t)__builtin_arm_strex + + +/** + \brief Remove the exclusive lock + \details Removes the exclusive lock which is created by LDREX. + */ +#define __CLREX __builtin_arm_clrex + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) + +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +#define __SSAT __builtin_arm_ssat + + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +#define __USAT __builtin_arm_usat + + +/** + \brief Rotate Right with Extend (32 bit) + \details Moves each bit of a bitstring right by one bit. + The carry input is shifted in at the left end of the bitstring. + \param [in] value Value to rotate + \return Rotated value + */ +__STATIC_FORCEINLINE uint32_t __RRX(uint32_t value) +{ + uint32_t result; + + __ASM volatile ("rrx %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return(result); +} + + +/** + \brief LDRT Unprivileged (8 bit) + \details Executes a Unprivileged LDRT instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDRBT(volatile uint8_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint8_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDRT Unprivileged (16 bit) + \details Executes a Unprivileged LDRT instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDRHT(volatile uint16_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint16_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDRT Unprivileged (32 bit) + \details Executes a Unprivileged LDRT instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDRT(volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*ptr) ); + return(result); +} + + +/** + \brief STRT Unprivileged (8 bit) + \details Executes a Unprivileged STRT instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRBT(uint8_t value, volatile uint8_t *ptr) +{ + __ASM volatile ("strbt %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief STRT Unprivileged (16 bit) + \details Executes a Unprivileged STRT instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRHT(uint16_t value, volatile uint16_t *ptr) +{ + __ASM volatile ("strht %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief STRT Unprivileged (32 bit) + \details Executes a Unprivileged STRT instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRT(uint32_t value, volatile uint32_t *ptr) +{ + __ASM volatile ("strt %1, %0" : "=Q" (*ptr) : "r" (value) ); +} + +#else /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +__STATIC_FORCEINLINE int32_t __SSAT(int32_t val, uint32_t sat) +{ + if ((sat >= 1U) && (sat <= 32U)) + { + const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U); + const int32_t min = -1 - max ; + if (val > max) + { + return max; + } + else if (val < min) + { + return min; + } + } + return val; +} + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +__STATIC_FORCEINLINE uint32_t __USAT(int32_t val, uint32_t sat) +{ + if (sat <= 31U) + { + const uint32_t max = ((1U << sat) - 1U); + if (val > (int32_t)max) + { + return max; + } + else if (val < 0) + { + return 0U; + } + } + return (uint32_t)val; +} + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) +/** + \brief Load-Acquire (8 bit) + \details Executes a LDAB instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDAB(volatile uint8_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldab %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); + return ((uint8_t) result); +} + + +/** + \brief Load-Acquire (16 bit) + \details Executes a LDAH instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDAH(volatile uint16_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldah %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); + return ((uint16_t) result); +} + + +/** + \brief Load-Acquire (32 bit) + \details Executes a LDA instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDA(volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("lda %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); + return(result); +} + + +/** + \brief Store-Release (8 bit) + \details Executes a STLB instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STLB(uint8_t value, volatile uint8_t *ptr) +{ + __ASM volatile ("stlb %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); +} + + +/** + \brief Store-Release (16 bit) + \details Executes a STLH instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STLH(uint16_t value, volatile uint16_t *ptr) +{ + __ASM volatile ("stlh %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); +} + + +/** + \brief Store-Release (32 bit) + \details Executes a STL instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STL(uint32_t value, volatile uint32_t *ptr) +{ + __ASM volatile ("stl %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); +} + + +/** + \brief Load-Acquire Exclusive (8 bit) + \details Executes a LDAB exclusive instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +#define __LDAEXB (uint8_t)__builtin_arm_ldaex + + +/** + \brief Load-Acquire Exclusive (16 bit) + \details Executes a LDAH exclusive instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +#define __LDAEXH (uint16_t)__builtin_arm_ldaex + + +/** + \brief Load-Acquire Exclusive (32 bit) + \details Executes a LDA exclusive instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +#define __LDAEX (uint32_t)__builtin_arm_ldaex + + +/** + \brief Store-Release Exclusive (8 bit) + \details Executes a STLB exclusive instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STLEXB (uint32_t)__builtin_arm_stlex + + +/** + \brief Store-Release Exclusive (16 bit) + \details Executes a STLH exclusive instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STLEXH (uint32_t)__builtin_arm_stlex + + +/** + \brief Store-Release Exclusive (32 bit) + \details Executes a STL exclusive instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STLEX (uint32_t)__builtin_arm_stlex + +#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ + +/*@}*/ /* end of group CMSIS_Core_InstructionInterface */ + + +/* ################### Compiler specific Intrinsics ########################### */ +/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics + Access to dedicated SIMD instructions + @{ +*/ + +#if (defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1)) + +__STATIC_FORCEINLINE uint32_t __SADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + + +__STATIC_FORCEINLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + + +__STATIC_FORCEINLINE uint32_t __SADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USAD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usad8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("usada8 %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +#define __SSAT16(ARG1,ARG2) \ +({ \ + int32_t __RES, __ARG1 = (ARG1); \ + __ASM ("ssat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + +#define __USAT16(ARG1,ARG2) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1); \ + __ASM ("usat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + +__STATIC_FORCEINLINE uint32_t __UXTB16(uint32_t op1) +{ + uint32_t result; + + __ASM volatile ("uxtb16 %0, %1" : "=r" (result) : "r" (op1)); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SXTB16(uint32_t op1) +{ + uint32_t result; + + __ASM volatile ("sxtb16 %0, %1" : "=r" (result) : "r" (op1)); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMUAD (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smuad %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smuadx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlad %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smladx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint64_t __SMLALD (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint64_t __SMLALDX (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint32_t __SMUSD (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smusd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smusdx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlsd %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlsdx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint64_t __SMLSLD (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint64_t __SMLSLDX (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint32_t __SEL (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sel %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE int32_t __QADD( int32_t op1, int32_t op2) +{ + int32_t result; + + __ASM volatile ("qadd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE int32_t __QSUB( int32_t op1, int32_t op2) +{ + int32_t result; + + __ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \ + ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) ) + +#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \ + ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) ) + +#define __SXTB16_RORn(ARG1, ARG2) __SXTB16(__ROR(ARG1, ARG2)) + +__STATIC_FORCEINLINE int32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3) +{ + int32_t result; + + __ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +#endif /* (__ARM_FEATURE_DSP == 1) */ +/*@} end of group CMSIS_SIMD_intrinsics */ + + +#endif /* __CMSIS_ARMCLANG_H */ diff --git a/bootloader/inc/cmsis_compiler.h b/bootloader/inc/cmsis_compiler.h new file mode 100644 index 0000000..adbf296 --- /dev/null +++ b/bootloader/inc/cmsis_compiler.h @@ -0,0 +1,283 @@ +/**************************************************************************//** + * @file cmsis_compiler.h + * @brief CMSIS compiler generic header file + * @version V5.1.0 + * @date 09. October 2018 + ******************************************************************************/ +/* + * Copyright (c) 2009-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __CMSIS_COMPILER_H +#define __CMSIS_COMPILER_H + +#include + +/* + * Arm Compiler 4/5 + */ +#if defined ( __CC_ARM ) + #include "cmsis_armcc.h" + + +/* + * Arm Compiler 6.6 LTM (armclang) + */ +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) && (__ARMCC_VERSION < 6100100) + #include "cmsis_armclang_ltm.h" + + /* + * Arm Compiler above 6.10.1 (armclang) + */ +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6100100) + #include "cmsis_armclang.h" + + +/* + * GNU Compiler + */ +#elif defined ( __GNUC__ ) + #include "cmsis_gcc.h" + + +/* + * IAR Compiler + */ +#elif defined ( __ICCARM__ ) + #include + + +/* + * TI Arm Compiler + */ +#elif defined ( __TI_ARM__ ) + #include + + #ifndef __ASM + #define __ASM __asm + #endif + #ifndef __INLINE + #define __INLINE inline + #endif + #ifndef __STATIC_INLINE + #define __STATIC_INLINE static inline + #endif + #ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __STATIC_INLINE + #endif + #ifndef __NO_RETURN + #define __NO_RETURN __attribute__((noreturn)) + #endif + #ifndef __USED + #define __USED __attribute__((used)) + #endif + #ifndef __WEAK + #define __WEAK __attribute__((weak)) + #endif + #ifndef __PACKED + #define __PACKED __attribute__((packed)) + #endif + #ifndef __PACKED_STRUCT + #define __PACKED_STRUCT struct __attribute__((packed)) + #endif + #ifndef __PACKED_UNION + #define __PACKED_UNION union __attribute__((packed)) + #endif + #ifndef __UNALIGNED_UINT32 /* deprecated */ + struct __attribute__((packed)) T_UINT32 { uint32_t v; }; + #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) + #endif + #ifndef __UNALIGNED_UINT16_WRITE + __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; + #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void*)(addr))->v) = (val)) + #endif + #ifndef __UNALIGNED_UINT16_READ + __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; + #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) + #endif + #ifndef __UNALIGNED_UINT32_WRITE + __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; + #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) + #endif + #ifndef __UNALIGNED_UINT32_READ + __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; + #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) + #endif + #ifndef __ALIGNED + #define __ALIGNED(x) __attribute__((aligned(x))) + #endif + #ifndef __RESTRICT + #define __RESTRICT __restrict + #endif + #ifndef __COMPILER_BARRIER + #warning No compiler specific solution for __COMPILER_BARRIER. __COMPILER_BARRIER is ignored. + #define __COMPILER_BARRIER() (void)0 + #endif + + +/* + * TASKING Compiler + */ +#elif defined ( __TASKING__ ) + /* + * The CMSIS functions have been implemented as intrinsics in the compiler. + * Please use "carm -?i" to get an up to date list of all intrinsics, + * Including the CMSIS ones. + */ + + #ifndef __ASM + #define __ASM __asm + #endif + #ifndef __INLINE + #define __INLINE inline + #endif + #ifndef __STATIC_INLINE + #define __STATIC_INLINE static inline + #endif + #ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __STATIC_INLINE + #endif + #ifndef __NO_RETURN + #define __NO_RETURN __attribute__((noreturn)) + #endif + #ifndef __USED + #define __USED __attribute__((used)) + #endif + #ifndef __WEAK + #define __WEAK __attribute__((weak)) + #endif + #ifndef __PACKED + #define __PACKED __packed__ + #endif + #ifndef __PACKED_STRUCT + #define __PACKED_STRUCT struct __packed__ + #endif + #ifndef __PACKED_UNION + #define __PACKED_UNION union __packed__ + #endif + #ifndef __UNALIGNED_UINT32 /* deprecated */ + struct __packed__ T_UINT32 { uint32_t v; }; + #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) + #endif + #ifndef __UNALIGNED_UINT16_WRITE + __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; + #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val)) + #endif + #ifndef __UNALIGNED_UINT16_READ + __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; + #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) + #endif + #ifndef __UNALIGNED_UINT32_WRITE + __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; + #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) + #endif + #ifndef __UNALIGNED_UINT32_READ + __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; + #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) + #endif + #ifndef __ALIGNED + #define __ALIGNED(x) __align(x) + #endif + #ifndef __RESTRICT + #warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored. + #define __RESTRICT + #endif + #ifndef __COMPILER_BARRIER + #warning No compiler specific solution for __COMPILER_BARRIER. __COMPILER_BARRIER is ignored. + #define __COMPILER_BARRIER() (void)0 + #endif + + +/* + * COSMIC Compiler + */ +#elif defined ( __CSMC__ ) + #include + + #ifndef __ASM + #define __ASM _asm + #endif + #ifndef __INLINE + #define __INLINE inline + #endif + #ifndef __STATIC_INLINE + #define __STATIC_INLINE static inline + #endif + #ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __STATIC_INLINE + #endif + #ifndef __NO_RETURN + // NO RETURN is automatically detected hence no warning here + #define __NO_RETURN + #endif + #ifndef __USED + #warning No compiler specific solution for __USED. __USED is ignored. + #define __USED + #endif + #ifndef __WEAK + #define __WEAK __weak + #endif + #ifndef __PACKED + #define __PACKED @packed + #endif + #ifndef __PACKED_STRUCT + #define __PACKED_STRUCT @packed struct + #endif + #ifndef __PACKED_UNION + #define __PACKED_UNION @packed union + #endif + #ifndef __UNALIGNED_UINT32 /* deprecated */ + @packed struct T_UINT32 { uint32_t v; }; + #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) + #endif + #ifndef __UNALIGNED_UINT16_WRITE + __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; + #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val)) + #endif + #ifndef __UNALIGNED_UINT16_READ + __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; + #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) + #endif + #ifndef __UNALIGNED_UINT32_WRITE + __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; + #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) + #endif + #ifndef __UNALIGNED_UINT32_READ + __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; + #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) + #endif + #ifndef __ALIGNED + #warning No compiler specific solution for __ALIGNED. __ALIGNED is ignored. + #define __ALIGNED(x) + #endif + #ifndef __RESTRICT + #warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored. + #define __RESTRICT + #endif + #ifndef __COMPILER_BARRIER + #warning No compiler specific solution for __COMPILER_BARRIER. __COMPILER_BARRIER is ignored. + #define __COMPILER_BARRIER() (void)0 + #endif + + +#else + #error Unknown compiler. +#endif + + +#endif /* __CMSIS_COMPILER_H */ + diff --git a/bootloader/inc/cmsis_gcc.h b/bootloader/inc/cmsis_gcc.h new file mode 100644 index 0000000..570a8db --- /dev/null +++ b/bootloader/inc/cmsis_gcc.h @@ -0,0 +1,2177 @@ +/**************************************************************************//** + * @file cmsis_gcc.h + * @brief CMSIS compiler GCC header file + * @version V5.3.0 + * @date 28. January 2020 + ******************************************************************************/ +/* + * Copyright (c) 2009-2019 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __CMSIS_GCC_H +#define __CMSIS_GCC_H + +/* ignore some GCC warnings */ +#pragma GCC diagnostic push +#pragma GCC diagnostic ignored "-Wsign-conversion" +#pragma GCC diagnostic ignored "-Wconversion" +#pragma GCC diagnostic ignored "-Wunused-parameter" + +/* Fallback for __has_builtin */ +#ifndef __has_builtin + #define __has_builtin(x) (0) +#endif + +/* CMSIS compiler specific defines */ +#ifndef __ASM + #define __ASM __asm +#endif +#ifndef __INLINE + #define __INLINE inline +#endif +#ifndef __STATIC_INLINE + #define __STATIC_INLINE static inline +#endif +#ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __attribute__((always_inline)) static inline +#endif +#ifndef __NO_RETURN + #define __NO_RETURN __attribute__((__noreturn__)) +#endif +#ifndef __USED + #define __USED __attribute__((used)) +#endif +#ifndef __WEAK + #define __WEAK __attribute__((weak)) +#endif +#ifndef __PACKED + #define __PACKED __attribute__((packed, aligned(1))) +#endif +#ifndef __PACKED_STRUCT + #define __PACKED_STRUCT struct __attribute__((packed, aligned(1))) +#endif +#ifndef __PACKED_UNION + #define __PACKED_UNION union __attribute__((packed, aligned(1))) +#endif +#ifndef __UNALIGNED_UINT32 /* deprecated */ + #pragma GCC diagnostic push + #pragma GCC diagnostic ignored "-Wpacked" + #pragma GCC diagnostic ignored "-Wattributes" + struct __attribute__((packed)) T_UINT32 { uint32_t v; }; + #pragma GCC diagnostic pop + #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) +#endif +#ifndef __UNALIGNED_UINT16_WRITE + #pragma GCC diagnostic push + #pragma GCC diagnostic ignored "-Wpacked" + #pragma GCC diagnostic ignored "-Wattributes" + __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; + #pragma GCC diagnostic pop + #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val)) +#endif +#ifndef __UNALIGNED_UINT16_READ + #pragma GCC diagnostic push + #pragma GCC diagnostic ignored "-Wpacked" + #pragma GCC diagnostic ignored "-Wattributes" + __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; + #pragma GCC diagnostic pop + #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) +#endif +#ifndef __UNALIGNED_UINT32_WRITE + #pragma GCC diagnostic push + #pragma GCC diagnostic ignored "-Wpacked" + #pragma GCC diagnostic ignored "-Wattributes" + __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; + #pragma GCC diagnostic pop + #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) +#endif +#ifndef __UNALIGNED_UINT32_READ + #pragma GCC diagnostic push + #pragma GCC diagnostic ignored "-Wpacked" + #pragma GCC diagnostic ignored "-Wattributes" + __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; + #pragma GCC diagnostic pop + #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) +#endif +#ifndef __ALIGNED + #define __ALIGNED(x) __attribute__((aligned(x))) +#endif +#ifndef __RESTRICT + #define __RESTRICT __restrict +#endif +#ifndef __COMPILER_BARRIER + #define __COMPILER_BARRIER() __ASM volatile("":::"memory") +#endif + +/* ######################### Startup and Lowlevel Init ######################## */ + +#ifndef __PROGRAM_START + +/** + \brief Initializes data and bss sections + \details This default implementations initialized all data and additional bss + sections relying on .copy.table and .zero.table specified properly + in the used linker script. + + */ +__STATIC_FORCEINLINE __NO_RETURN void __cmsis_start(void) +{ + extern void _start(void) __NO_RETURN; + + typedef struct { + uint32_t const* src; + uint32_t* dest; + uint32_t wlen; + } __copy_table_t; + + typedef struct { + uint32_t* dest; + uint32_t wlen; + } __zero_table_t; + + extern const __copy_table_t __copy_table_start__; + extern const __copy_table_t __copy_table_end__; + extern const __zero_table_t __zero_table_start__; + extern const __zero_table_t __zero_table_end__; + + for (__copy_table_t const* pTable = &__copy_table_start__; pTable < &__copy_table_end__; ++pTable) { + for(uint32_t i=0u; iwlen; ++i) { + pTable->dest[i] = pTable->src[i]; + } + } + + for (__zero_table_t const* pTable = &__zero_table_start__; pTable < &__zero_table_end__; ++pTable) { + for(uint32_t i=0u; iwlen; ++i) { + pTable->dest[i] = 0u; + } + } + + _start(); +} + +#define __PROGRAM_START __cmsis_start +#endif + +#ifndef __INITIAL_SP +#define __INITIAL_SP __StackTop +#endif + +#ifndef __STACK_LIMIT +#define __STACK_LIMIT __StackLimit +#endif + +#ifndef __VECTOR_TABLE +#define __VECTOR_TABLE __Vectors +#endif + +#ifndef __VECTOR_TABLE_ATTRIBUTE +#define __VECTOR_TABLE_ATTRIBUTE __attribute((used, section(".vectors"))) +#endif + +/* ########################### Core Function Access ########################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions + @{ + */ + +/** + \brief Enable IRQ Interrupts + \details Enables IRQ interrupts by clearing the I-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__STATIC_FORCEINLINE void __enable_irq(void) +{ + __ASM volatile ("cpsie i" : : : "memory"); +} + + +/** + \brief Disable IRQ Interrupts + \details Disables IRQ interrupts by setting the I-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__STATIC_FORCEINLINE void __disable_irq(void) +{ + __ASM volatile ("cpsid i" : : : "memory"); +} + + +/** + \brief Get Control Register + \details Returns the content of the Control Register. + \return Control Register value + */ +__STATIC_FORCEINLINE uint32_t __get_CONTROL(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, control" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Control Register (non-secure) + \details Returns the content of the non-secure Control Register when in secure mode. + \return non-secure Control Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_CONTROL_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, control_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Control Register + \details Writes the given value to the Control Register. + \param [in] control Control Register value to set + */ +__STATIC_FORCEINLINE void __set_CONTROL(uint32_t control) +{ + __ASM volatile ("MSR control, %0" : : "r" (control) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Control Register (non-secure) + \details Writes the given value to the non-secure Control Register when in secure state. + \param [in] control Control Register value to set + */ +__STATIC_FORCEINLINE void __TZ_set_CONTROL_NS(uint32_t control) +{ + __ASM volatile ("MSR control_ns, %0" : : "r" (control) : "memory"); +} +#endif + + +/** + \brief Get IPSR Register + \details Returns the content of the IPSR Register. + \return IPSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_IPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, ipsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get APSR Register + \details Returns the content of the APSR Register. + \return APSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_APSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, apsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get xPSR Register + \details Returns the content of the xPSR Register. + \return xPSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_xPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, xpsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get Process Stack Pointer + \details Returns the current value of the Process Stack Pointer (PSP). + \return PSP Register value + */ +__STATIC_FORCEINLINE uint32_t __get_PSP(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, psp" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Process Stack Pointer (non-secure) + \details Returns the current value of the non-secure Process Stack Pointer (PSP) when in secure state. + \return PSP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PSP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, psp_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Process Stack Pointer + \details Assigns the given value to the Process Stack Pointer (PSP). + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __set_PSP(uint32_t topOfProcStack) +{ + __ASM volatile ("MSR psp, %0" : : "r" (topOfProcStack) : ); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Process Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Process Stack Pointer (PSP) when in secure state. + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_PSP_NS(uint32_t topOfProcStack) +{ + __ASM volatile ("MSR psp_ns, %0" : : "r" (topOfProcStack) : ); +} +#endif + + +/** + \brief Get Main Stack Pointer + \details Returns the current value of the Main Stack Pointer (MSP). + \return MSP Register value + */ +__STATIC_FORCEINLINE uint32_t __get_MSP(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, msp" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Main Stack Pointer (non-secure) + \details Returns the current value of the non-secure Main Stack Pointer (MSP) when in secure state. + \return MSP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_MSP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, msp_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Main Stack Pointer + \details Assigns the given value to the Main Stack Pointer (MSP). + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __set_MSP(uint32_t topOfMainStack) +{ + __ASM volatile ("MSR msp, %0" : : "r" (topOfMainStack) : ); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Main Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Main Stack Pointer (MSP) when in secure state. + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_MSP_NS(uint32_t topOfMainStack) +{ + __ASM volatile ("MSR msp_ns, %0" : : "r" (topOfMainStack) : ); +} +#endif + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Stack Pointer (non-secure) + \details Returns the current value of the non-secure Stack Pointer (SP) when in secure state. + \return SP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_SP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, sp_ns" : "=r" (result) ); + return(result); +} + + +/** + \brief Set Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Stack Pointer (SP) when in secure state. + \param [in] topOfStack Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_SP_NS(uint32_t topOfStack) +{ + __ASM volatile ("MSR sp_ns, %0" : : "r" (topOfStack) : ); +} +#endif + + +/** + \brief Get Priority Mask + \details Returns the current state of the priority mask bit from the Priority Mask Register. + \return Priority Mask value + */ +__STATIC_FORCEINLINE uint32_t __get_PRIMASK(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, primask" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Priority Mask (non-secure) + \details Returns the current state of the non-secure priority mask bit from the Priority Mask Register when in secure state. + \return Priority Mask value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PRIMASK_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, primask_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Priority Mask + \details Assigns the given value to the Priority Mask Register. + \param [in] priMask Priority Mask + */ +__STATIC_FORCEINLINE void __set_PRIMASK(uint32_t priMask) +{ + __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Priority Mask (non-secure) + \details Assigns the given value to the non-secure Priority Mask Register when in secure state. + \param [in] priMask Priority Mask + */ +__STATIC_FORCEINLINE void __TZ_set_PRIMASK_NS(uint32_t priMask) +{ + __ASM volatile ("MSR primask_ns, %0" : : "r" (priMask) : "memory"); +} +#endif + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) +/** + \brief Enable FIQ + \details Enables FIQ interrupts by clearing the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__STATIC_FORCEINLINE void __enable_fault_irq(void) +{ + __ASM volatile ("cpsie f" : : : "memory"); +} + + +/** + \brief Disable FIQ + \details Disables FIQ interrupts by setting the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__STATIC_FORCEINLINE void __disable_fault_irq(void) +{ + __ASM volatile ("cpsid f" : : : "memory"); +} + + +/** + \brief Get Base Priority + \details Returns the current value of the Base Priority register. + \return Base Priority register value + */ +__STATIC_FORCEINLINE uint32_t __get_BASEPRI(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, basepri" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Base Priority (non-secure) + \details Returns the current value of the non-secure Base Priority register when in secure state. + \return Base Priority register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_BASEPRI_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, basepri_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Base Priority + \details Assigns the given value to the Base Priority register. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __set_BASEPRI(uint32_t basePri) +{ + __ASM volatile ("MSR basepri, %0" : : "r" (basePri) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Base Priority (non-secure) + \details Assigns the given value to the non-secure Base Priority register when in secure state. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __TZ_set_BASEPRI_NS(uint32_t basePri) +{ + __ASM volatile ("MSR basepri_ns, %0" : : "r" (basePri) : "memory"); +} +#endif + + +/** + \brief Set Base Priority with condition + \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled, + or the new value increases the BASEPRI priority level. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __set_BASEPRI_MAX(uint32_t basePri) +{ + __ASM volatile ("MSR basepri_max, %0" : : "r" (basePri) : "memory"); +} + + +/** + \brief Get Fault Mask + \details Returns the current value of the Fault Mask register. + \return Fault Mask register value + */ +__STATIC_FORCEINLINE uint32_t __get_FAULTMASK(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, faultmask" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Fault Mask (non-secure) + \details Returns the current value of the non-secure Fault Mask register when in secure state. + \return Fault Mask register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_FAULTMASK_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, faultmask_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Fault Mask + \details Assigns the given value to the Fault Mask register. + \param [in] faultMask Fault Mask value to set + */ +__STATIC_FORCEINLINE void __set_FAULTMASK(uint32_t faultMask) +{ + __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Fault Mask (non-secure) + \details Assigns the given value to the non-secure Fault Mask register when in secure state. + \param [in] faultMask Fault Mask value to set + */ +__STATIC_FORCEINLINE void __TZ_set_FAULTMASK_NS(uint32_t faultMask) +{ + __ASM volatile ("MSR faultmask_ns, %0" : : "r" (faultMask) : "memory"); +} +#endif + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) + +/** + \brief Get Process Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always in non-secure + mode. + + \details Returns the current value of the Process Stack Pointer Limit (PSPLIM). + \return PSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __get_PSPLIM(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, psplim" : "=r" (result) ); + return result; +#endif +} + +#if (defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Process Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always. + + \details Returns the current value of the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. + \return PSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PSPLIM_NS(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, psplim_ns" : "=r" (result) ); + return result; +#endif +} +#endif + + +/** + \brief Set Process Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored in non-secure + mode. + + \details Assigns the given value to the Process Stack Pointer Limit (PSPLIM). + \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __set_PSPLIM(uint32_t ProcStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + (void)ProcStackPtrLimit; +#else + __ASM volatile ("MSR psplim, %0" : : "r" (ProcStackPtrLimit)); +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Process Stack Pointer (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored. + + \details Assigns the given value to the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. + \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __TZ_set_PSPLIM_NS(uint32_t ProcStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + (void)ProcStackPtrLimit; +#else + __ASM volatile ("MSR psplim_ns, %0\n" : : "r" (ProcStackPtrLimit)); +#endif +} +#endif + + +/** + \brief Get Main Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always in non-secure + mode. + + \details Returns the current value of the Main Stack Pointer Limit (MSPLIM). + \return MSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __get_MSPLIM(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, msplim" : "=r" (result) ); + return result; +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Main Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always. + + \details Returns the current value of the non-secure Main Stack Pointer Limit(MSPLIM) when in secure state. + \return MSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_MSPLIM_NS(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, msplim_ns" : "=r" (result) ); + return result; +#endif +} +#endif + + +/** + \brief Set Main Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored in non-secure + mode. + + \details Assigns the given value to the Main Stack Pointer Limit (MSPLIM). + \param [in] MainStackPtrLimit Main Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __set_MSPLIM(uint32_t MainStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + (void)MainStackPtrLimit; +#else + __ASM volatile ("MSR msplim, %0" : : "r" (MainStackPtrLimit)); +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Main Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored. + + \details Assigns the given value to the non-secure Main Stack Pointer Limit (MSPLIM) when in secure state. + \param [in] MainStackPtrLimit Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + (void)MainStackPtrLimit; +#else + __ASM volatile ("MSR msplim_ns, %0" : : "r" (MainStackPtrLimit)); +#endif +} +#endif + +#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ + + +/** + \brief Get FPSCR + \details Returns the current value of the Floating Point Status/Control register. + \return Floating Point Status/Control register value + */ +__STATIC_FORCEINLINE uint32_t __get_FPSCR(void) +{ +#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) +#if __has_builtin(__builtin_arm_get_fpscr) +// Re-enable using built-in when GCC has been fixed +// || (__GNUC__ > 7) || (__GNUC__ == 7 && __GNUC_MINOR__ >= 2) + /* see https://gcc.gnu.org/ml/gcc-patches/2017-04/msg00443.html */ + return __builtin_arm_get_fpscr(); +#else + uint32_t result; + + __ASM volatile ("VMRS %0, fpscr" : "=r" (result) ); + return(result); +#endif +#else + return(0U); +#endif +} + + +/** + \brief Set FPSCR + \details Assigns the given value to the Floating Point Status/Control register. + \param [in] fpscr Floating Point Status/Control value to set + */ +__STATIC_FORCEINLINE void __set_FPSCR(uint32_t fpscr) +{ +#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) +#if __has_builtin(__builtin_arm_set_fpscr) +// Re-enable using built-in when GCC has been fixed +// || (__GNUC__ > 7) || (__GNUC__ == 7 && __GNUC_MINOR__ >= 2) + /* see https://gcc.gnu.org/ml/gcc-patches/2017-04/msg00443.html */ + __builtin_arm_set_fpscr(fpscr); +#else + __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) : "vfpcc", "memory"); +#endif +#else + (void)fpscr; +#endif +} + + +/*@} end of CMSIS_Core_RegAccFunctions */ + + +/* ########################## Core Instruction Access ######################### */ +/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface + Access to dedicated instructions + @{ +*/ + +/* Define macros for porting to both thumb1 and thumb2. + * For thumb1, use low register (r0-r7), specified by constraint "l" + * Otherwise, use general registers, specified by constraint "r" */ +#if defined (__thumb__) && !defined (__thumb2__) +#define __CMSIS_GCC_OUT_REG(r) "=l" (r) +#define __CMSIS_GCC_RW_REG(r) "+l" (r) +#define __CMSIS_GCC_USE_REG(r) "l" (r) +#else +#define __CMSIS_GCC_OUT_REG(r) "=r" (r) +#define __CMSIS_GCC_RW_REG(r) "+r" (r) +#define __CMSIS_GCC_USE_REG(r) "r" (r) +#endif + +/** + \brief No Operation + \details No Operation does nothing. This instruction can be used for code alignment purposes. + */ +#define __NOP() __ASM volatile ("nop") + +/** + \brief Wait For Interrupt + \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs. + */ +#define __WFI() __ASM volatile ("wfi":::"memory") + + +/** + \brief Wait For Event + \details Wait For Event is a hint instruction that permits the processor to enter + a low-power state until one of a number of events occurs. + */ +#define __WFE() __ASM volatile ("wfe":::"memory") + + +/** + \brief Send Event + \details Send Event is a hint instruction. It causes an event to be signaled to the CPU. + */ +#define __SEV() __ASM volatile ("sev") + + +/** + \brief Instruction Synchronization Barrier + \details Instruction Synchronization Barrier flushes the pipeline in the processor, + so that all instructions following the ISB are fetched from cache or memory, + after the instruction has been completed. + */ +__STATIC_FORCEINLINE void __ISB(void) +{ + __ASM volatile ("isb 0xF":::"memory"); +} + + +/** + \brief Data Synchronization Barrier + \details Acts as a special kind of Data Memory Barrier. + It completes when all explicit memory accesses before this instruction complete. + */ +__STATIC_FORCEINLINE void __DSB(void) +{ + __ASM volatile ("dsb 0xF":::"memory"); +} + + +/** + \brief Data Memory Barrier + \details Ensures the apparent order of the explicit memory operations before + and after the instruction, without ensuring their completion. + */ +__STATIC_FORCEINLINE void __DMB(void) +{ + __ASM volatile ("dmb 0xF":::"memory"); +} + + +/** + \brief Reverse byte order (32 bit) + \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412. + \param [in] value Value to reverse + \return Reversed value + */ +__STATIC_FORCEINLINE uint32_t __REV(uint32_t value) +{ +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 5) + return __builtin_bswap32(value); +#else + uint32_t result; + + __ASM ("rev %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return result; +#endif +} + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856. + \param [in] value Value to reverse + \return Reversed value + */ +__STATIC_FORCEINLINE uint32_t __REV16(uint32_t value) +{ + uint32_t result; + + __ASM ("rev16 %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return result; +} + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000. + \param [in] value Value to reverse + \return Reversed value + */ +__STATIC_FORCEINLINE int16_t __REVSH(int16_t value) +{ +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + return (int16_t)__builtin_bswap16(value); +#else + int16_t result; + + __ASM ("revsh %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return result; +#endif +} + + +/** + \brief Rotate Right in unsigned value (32 bit) + \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. + \param [in] op1 Value to rotate + \param [in] op2 Number of Bits to rotate + \return Rotated value + */ +__STATIC_FORCEINLINE uint32_t __ROR(uint32_t op1, uint32_t op2) +{ + op2 %= 32U; + if (op2 == 0U) + { + return op1; + } + return (op1 >> op2) | (op1 << (32U - op2)); +} + + +/** + \brief Breakpoint + \details Causes the processor to enter Debug state. + Debug tools can use this to investigate system state when the instruction at a particular address is reached. + \param [in] value is ignored by the processor. + If required, a debugger can use it to store additional information about the breakpoint. + */ +#define __BKPT(value) __ASM volatile ("bkpt "#value) + + +/** + \brief Reverse bit order of value + \details Reverses the bit order of the given value. + \param [in] value Value to reverse + \return Reversed value + */ +__STATIC_FORCEINLINE uint32_t __RBIT(uint32_t value) +{ + uint32_t result; + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) + __ASM ("rbit %0, %1" : "=r" (result) : "r" (value) ); +#else + uint32_t s = (4U /*sizeof(v)*/ * 8U) - 1U; /* extra shift needed at end */ + + result = value; /* r will be reversed bits of v; first get LSB of v */ + for (value >>= 1U; value != 0U; value >>= 1U) + { + result <<= 1U; + result |= value & 1U; + s--; + } + result <<= s; /* shift when v's highest bits are zero */ +#endif + return result; +} + + +/** + \brief Count leading zeros + \details Counts the number of leading zeros of a data value. + \param [in] value Value to count the leading zeros + \return number of leading zeros in value + */ +__STATIC_FORCEINLINE uint8_t __CLZ(uint32_t value) +{ + /* Even though __builtin_clz produces a CLZ instruction on ARM, formally + __builtin_clz(0) is undefined behaviour, so handle this case specially. + This guarantees ARM-compatible results if happening to compile on a non-ARM + target, and ensures the compiler doesn't decide to activate any + optimisations using the logic "value was passed to __builtin_clz, so it + is non-zero". + ARM GCC 7.3 and possibly earlier will optimise this test away, leaving a + single CLZ instruction. + */ + if (value == 0U) + { + return 32U; + } + return __builtin_clz(value); +} + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) +/** + \brief LDR Exclusive (8 bit) + \details Executes a exclusive LDR instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDREXB(volatile uint8_t *addr) +{ + uint32_t result; + +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + __ASM volatile ("ldrexb %0, %1" : "=r" (result) : "Q" (*addr) ); +#else + /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not + accepted by assembler. So has to use following less efficient pattern. + */ + __ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) : "memory" ); +#endif + return ((uint8_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDR Exclusive (16 bit) + \details Executes a exclusive LDR instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDREXH(volatile uint16_t *addr) +{ + uint32_t result; + +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + __ASM volatile ("ldrexh %0, %1" : "=r" (result) : "Q" (*addr) ); +#else + /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not + accepted by assembler. So has to use following less efficient pattern. + */ + __ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) : "memory" ); +#endif + return ((uint16_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDR Exclusive (32 bit) + \details Executes a exclusive LDR instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDREXW(volatile uint32_t *addr) +{ + uint32_t result; + + __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); + return(result); +} + + +/** + \brief STR Exclusive (8 bit) + \details Executes a exclusive STR instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__STATIC_FORCEINLINE uint32_t __STREXB(uint8_t value, volatile uint8_t *addr) +{ + uint32_t result; + + __ASM volatile ("strexb %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) ); + return(result); +} + + +/** + \brief STR Exclusive (16 bit) + \details Executes a exclusive STR instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__STATIC_FORCEINLINE uint32_t __STREXH(uint16_t value, volatile uint16_t *addr) +{ + uint32_t result; + + __ASM volatile ("strexh %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) ); + return(result); +} + + +/** + \brief STR Exclusive (32 bit) + \details Executes a exclusive STR instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__STATIC_FORCEINLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr) +{ + uint32_t result; + + __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); + return(result); +} + + +/** + \brief Remove the exclusive lock + \details Removes the exclusive lock which is created by LDREX. + */ +__STATIC_FORCEINLINE void __CLREX(void) +{ + __ASM volatile ("clrex" ::: "memory"); +} + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] ARG1 Value to be saturated + \param [in] ARG2 Bit position to saturate to (1..32) + \return Saturated value + */ +#define __SSAT(ARG1, ARG2) \ +__extension__ \ +({ \ + int32_t __RES, __ARG1 = (ARG1); \ + __ASM volatile ("ssat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) : "cc" ); \ + __RES; \ + }) + + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] ARG1 Value to be saturated + \param [in] ARG2 Bit position to saturate to (0..31) + \return Saturated value + */ +#define __USAT(ARG1, ARG2) \ + __extension__ \ +({ \ + uint32_t __RES, __ARG1 = (ARG1); \ + __ASM volatile ("usat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) : "cc" ); \ + __RES; \ + }) + + +/** + \brief Rotate Right with Extend (32 bit) + \details Moves each bit of a bitstring right by one bit. + The carry input is shifted in at the left end of the bitstring. + \param [in] value Value to rotate + \return Rotated value + */ +__STATIC_FORCEINLINE uint32_t __RRX(uint32_t value) +{ + uint32_t result; + + __ASM volatile ("rrx %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return(result); +} + + +/** + \brief LDRT Unprivileged (8 bit) + \details Executes a Unprivileged LDRT instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDRBT(volatile uint8_t *ptr) +{ + uint32_t result; + +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*ptr) ); +#else + /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not + accepted by assembler. So has to use following less efficient pattern. + */ + __ASM volatile ("ldrbt %0, [%1]" : "=r" (result) : "r" (ptr) : "memory" ); +#endif + return ((uint8_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDRT Unprivileged (16 bit) + \details Executes a Unprivileged LDRT instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDRHT(volatile uint16_t *ptr) +{ + uint32_t result; + +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*ptr) ); +#else + /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not + accepted by assembler. So has to use following less efficient pattern. + */ + __ASM volatile ("ldrht %0, [%1]" : "=r" (result) : "r" (ptr) : "memory" ); +#endif + return ((uint16_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDRT Unprivileged (32 bit) + \details Executes a Unprivileged LDRT instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDRT(volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*ptr) ); + return(result); +} + + +/** + \brief STRT Unprivileged (8 bit) + \details Executes a Unprivileged STRT instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRBT(uint8_t value, volatile uint8_t *ptr) +{ + __ASM volatile ("strbt %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief STRT Unprivileged (16 bit) + \details Executes a Unprivileged STRT instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRHT(uint16_t value, volatile uint16_t *ptr) +{ + __ASM volatile ("strht %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief STRT Unprivileged (32 bit) + \details Executes a Unprivileged STRT instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRT(uint32_t value, volatile uint32_t *ptr) +{ + __ASM volatile ("strt %1, %0" : "=Q" (*ptr) : "r" (value) ); +} + +#else /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +__STATIC_FORCEINLINE int32_t __SSAT(int32_t val, uint32_t sat) +{ + if ((sat >= 1U) && (sat <= 32U)) + { + const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U); + const int32_t min = -1 - max ; + if (val > max) + { + return max; + } + else if (val < min) + { + return min; + } + } + return val; +} + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +__STATIC_FORCEINLINE uint32_t __USAT(int32_t val, uint32_t sat) +{ + if (sat <= 31U) + { + const uint32_t max = ((1U << sat) - 1U); + if (val > (int32_t)max) + { + return max; + } + else if (val < 0) + { + return 0U; + } + } + return (uint32_t)val; +} + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) +/** + \brief Load-Acquire (8 bit) + \details Executes a LDAB instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDAB(volatile uint8_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldab %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); + return ((uint8_t) result); +} + + +/** + \brief Load-Acquire (16 bit) + \details Executes a LDAH instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDAH(volatile uint16_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldah %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); + return ((uint16_t) result); +} + + +/** + \brief Load-Acquire (32 bit) + \details Executes a LDA instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDA(volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("lda %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); + return(result); +} + + +/** + \brief Store-Release (8 bit) + \details Executes a STLB instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STLB(uint8_t value, volatile uint8_t *ptr) +{ + __ASM volatile ("stlb %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); +} + + +/** + \brief Store-Release (16 bit) + \details Executes a STLH instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STLH(uint16_t value, volatile uint16_t *ptr) +{ + __ASM volatile ("stlh %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); +} + + +/** + \brief Store-Release (32 bit) + \details Executes a STL instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STL(uint32_t value, volatile uint32_t *ptr) +{ + __ASM volatile ("stl %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); +} + + +/** + \brief Load-Acquire Exclusive (8 bit) + \details Executes a LDAB exclusive instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDAEXB(volatile uint8_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldaexb %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); + return ((uint8_t) result); +} + + +/** + \brief Load-Acquire Exclusive (16 bit) + \details Executes a LDAH exclusive instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDAEXH(volatile uint16_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldaexh %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); + return ((uint16_t) result); +} + + +/** + \brief Load-Acquire Exclusive (32 bit) + \details Executes a LDA exclusive instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDAEX(volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldaex %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); + return(result); +} + + +/** + \brief Store-Release Exclusive (8 bit) + \details Executes a STLB exclusive instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__STATIC_FORCEINLINE uint32_t __STLEXB(uint8_t value, volatile uint8_t *ptr) +{ + uint32_t result; + + __ASM volatile ("stlexb %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); + return(result); +} + + +/** + \brief Store-Release Exclusive (16 bit) + \details Executes a STLH exclusive instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__STATIC_FORCEINLINE uint32_t __STLEXH(uint16_t value, volatile uint16_t *ptr) +{ + uint32_t result; + + __ASM volatile ("stlexh %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); + return(result); +} + + +/** + \brief Store-Release Exclusive (32 bit) + \details Executes a STL exclusive instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__STATIC_FORCEINLINE uint32_t __STLEX(uint32_t value, volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("stlex %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); + return(result); +} + +#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ + +/*@}*/ /* end of group CMSIS_Core_InstructionInterface */ + + +/* ################### Compiler specific Intrinsics ########################### */ +/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics + Access to dedicated SIMD instructions + @{ +*/ + +#if (defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1)) + +__STATIC_FORCEINLINE uint32_t __SADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("shadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("uqadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("uhadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + + +__STATIC_FORCEINLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("qsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("shsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("uqsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("uhsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + + +__STATIC_FORCEINLINE uint32_t __SADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("qadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("shadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("uqadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("uhadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("qsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("shsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("uqsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("uhsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("qasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("shasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("uqasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("uhasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("qsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("shsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("uqsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("uhsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USAD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("usad8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM ("usada8 %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +#define __SSAT16(ARG1, ARG2) \ +({ \ + int32_t __RES, __ARG1 = (ARG1); \ + __ASM volatile ("ssat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) : "cc" ); \ + __RES; \ + }) + +#define __USAT16(ARG1, ARG2) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1); \ + __ASM volatile ("usat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) : "cc" ); \ + __RES; \ + }) + +__STATIC_FORCEINLINE uint32_t __UXTB16(uint32_t op1) +{ + uint32_t result; + + __ASM ("uxtb16 %0, %1" : "=r" (result) : "r" (op1)); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("uxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SXTB16(uint32_t op1) +{ + uint32_t result; + + __ASM ("sxtb16 %0, %1" : "=r" (result) : "r" (op1)); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SXTB16_RORn(uint32_t op1, uint32_t rotate) +{ + uint32_t result; + + __ASM ("sxtb16 %0, %1, ROR %2" : "=r" (result) : "r" (op1), "i" (rotate) ); + + return result; +} + +__STATIC_FORCEINLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("sxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMUAD (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smuad %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smuadx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlad %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smladx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint64_t __SMLALD (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint64_t __SMLALDX (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint32_t __SMUSD (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smusd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smusdx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlsd %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlsdx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint64_t __SMLSLD (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint64_t __SMLSLDX (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint32_t __SEL (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sel %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE int32_t __QADD( int32_t op1, int32_t op2) +{ + int32_t result; + + __ASM volatile ("qadd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE int32_t __QSUB( int32_t op1, int32_t op2) +{ + int32_t result; + + __ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +#if 0 +#define __PKHBT(ARG1,ARG2,ARG3) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \ + __ASM ("pkhbt %0, %1, %2, lsl %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \ + __RES; \ + }) + +#define __PKHTB(ARG1,ARG2,ARG3) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \ + if (ARG3 == 0) \ + __ASM ("pkhtb %0, %1, %2" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2) ); \ + else \ + __ASM ("pkhtb %0, %1, %2, asr %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \ + __RES; \ + }) +#endif + +#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \ + ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) ) + +#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \ + ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) ) + +__STATIC_FORCEINLINE int32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3) +{ + int32_t result; + + __ASM ("smmla %0, %1, %2, %3" : "=r" (result): "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +#endif /* (__ARM_FEATURE_DSP == 1) */ +/*@} end of group CMSIS_SIMD_intrinsics */ + + +#pragma GCC diagnostic pop + +#endif /* __CMSIS_GCC_H */ diff --git a/bootloader/inc/cmsis_iccarm.h b/bootloader/inc/cmsis_iccarm.h new file mode 100644 index 0000000..fe2d6de --- /dev/null +++ b/bootloader/inc/cmsis_iccarm.h @@ -0,0 +1,966 @@ +/**************************************************************************//** + * @file cmsis_iccarm.h + * @brief CMSIS compiler ICCARM (IAR Compiler for Arm) header file + * @version V5.2.0 + * @date 28. January 2020 + ******************************************************************************/ + +//------------------------------------------------------------------------------ +// +// Copyright (c) 2017-2019 IAR Systems +// Copyright (c) 2017-2019 Arm Limited. All rights reserved. +// +// Licensed under the Apache License, Version 2.0 (the "License") +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// +//------------------------------------------------------------------------------ + + +#ifndef __CMSIS_ICCARM_H__ +#define __CMSIS_ICCARM_H__ + +#ifndef __ICCARM__ + #error This file should only be compiled by ICCARM +#endif + +#pragma system_include + +#define __IAR_FT _Pragma("inline=forced") __intrinsic + +#if (__VER__ >= 8000000) + #define __ICCARM_V8 1 +#else + #define __ICCARM_V8 0 +#endif + +#ifndef __ALIGNED + #if __ICCARM_V8 + #define __ALIGNED(x) __attribute__((aligned(x))) + #elif (__VER__ >= 7080000) + /* Needs IAR language extensions */ + #define __ALIGNED(x) __attribute__((aligned(x))) + #else + #warning No compiler specific solution for __ALIGNED.__ALIGNED is ignored. + #define __ALIGNED(x) + #endif +#endif + + +/* Define compiler macros for CPU architecture, used in CMSIS 5. + */ +#if __ARM_ARCH_6M__ || __ARM_ARCH_7M__ || __ARM_ARCH_7EM__ || __ARM_ARCH_8M_BASE__ || __ARM_ARCH_8M_MAIN__ +/* Macros already defined */ +#else + #if defined(__ARM8M_MAINLINE__) || defined(__ARM8EM_MAINLINE__) + #define __ARM_ARCH_8M_MAIN__ 1 + #elif defined(__ARM8M_BASELINE__) + #define __ARM_ARCH_8M_BASE__ 1 + #elif defined(__ARM_ARCH_PROFILE) && __ARM_ARCH_PROFILE == 'M' + #if __ARM_ARCH == 6 + #define __ARM_ARCH_6M__ 1 + #elif __ARM_ARCH == 7 + #if __ARM_FEATURE_DSP + #define __ARM_ARCH_7EM__ 1 + #else + #define __ARM_ARCH_7M__ 1 + #endif + #endif /* __ARM_ARCH */ + #endif /* __ARM_ARCH_PROFILE == 'M' */ +#endif + +/* Alternativ core deduction for older ICCARM's */ +#if !defined(__ARM_ARCH_6M__) && !defined(__ARM_ARCH_7M__) && !defined(__ARM_ARCH_7EM__) && \ + !defined(__ARM_ARCH_8M_BASE__) && !defined(__ARM_ARCH_8M_MAIN__) + #if defined(__ARM6M__) && (__CORE__ == __ARM6M__) + #define __ARM_ARCH_6M__ 1 + #elif defined(__ARM7M__) && (__CORE__ == __ARM7M__) + #define __ARM_ARCH_7M__ 1 + #elif defined(__ARM7EM__) && (__CORE__ == __ARM7EM__) + #define __ARM_ARCH_7EM__ 1 + #elif defined(__ARM8M_BASELINE__) && (__CORE == __ARM8M_BASELINE__) + #define __ARM_ARCH_8M_BASE__ 1 + #elif defined(__ARM8M_MAINLINE__) && (__CORE == __ARM8M_MAINLINE__) + #define __ARM_ARCH_8M_MAIN__ 1 + #elif defined(__ARM8EM_MAINLINE__) && (__CORE == __ARM8EM_MAINLINE__) + #define __ARM_ARCH_8M_MAIN__ 1 + #else + #error "Unknown target." + #endif +#endif + + + +#if defined(__ARM_ARCH_6M__) && __ARM_ARCH_6M__==1 + #define __IAR_M0_FAMILY 1 +#elif defined(__ARM_ARCH_8M_BASE__) && __ARM_ARCH_8M_BASE__==1 + #define __IAR_M0_FAMILY 1 +#else + #define __IAR_M0_FAMILY 0 +#endif + + +#ifndef __ASM + #define __ASM __asm +#endif + +#ifndef __COMPILER_BARRIER + #define __COMPILER_BARRIER() __ASM volatile("":::"memory") +#endif + +#ifndef __INLINE + #define __INLINE inline +#endif + +#ifndef __NO_RETURN + #if __ICCARM_V8 + #define __NO_RETURN __attribute__((__noreturn__)) + #else + #define __NO_RETURN _Pragma("object_attribute=__noreturn") + #endif +#endif + +#ifndef __PACKED + #if __ICCARM_V8 + #define __PACKED __attribute__((packed, aligned(1))) + #else + /* Needs IAR language extensions */ + #define __PACKED __packed + #endif +#endif + +#ifndef __PACKED_STRUCT + #if __ICCARM_V8 + #define __PACKED_STRUCT struct __attribute__((packed, aligned(1))) + #else + /* Needs IAR language extensions */ + #define __PACKED_STRUCT __packed struct + #endif +#endif + +#ifndef __PACKED_UNION + #if __ICCARM_V8 + #define __PACKED_UNION union __attribute__((packed, aligned(1))) + #else + /* Needs IAR language extensions */ + #define __PACKED_UNION __packed union + #endif +#endif + +#ifndef __RESTRICT + #if __ICCARM_V8 + #define __RESTRICT __restrict + #else + /* Needs IAR language extensions */ + #define __RESTRICT restrict + #endif +#endif + +#ifndef __STATIC_INLINE + #define __STATIC_INLINE static inline +#endif + +#ifndef __FORCEINLINE + #define __FORCEINLINE _Pragma("inline=forced") +#endif + +#ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __FORCEINLINE __STATIC_INLINE +#endif + +#ifndef __UNALIGNED_UINT16_READ +#pragma language=save +#pragma language=extended +__IAR_FT uint16_t __iar_uint16_read(void const *ptr) +{ + return *(__packed uint16_t*)(ptr); +} +#pragma language=restore +#define __UNALIGNED_UINT16_READ(PTR) __iar_uint16_read(PTR) +#endif + + +#ifndef __UNALIGNED_UINT16_WRITE +#pragma language=save +#pragma language=extended +__IAR_FT void __iar_uint16_write(void const *ptr, uint16_t val) +{ + *(__packed uint16_t*)(ptr) = val;; +} +#pragma language=restore +#define __UNALIGNED_UINT16_WRITE(PTR,VAL) __iar_uint16_write(PTR,VAL) +#endif + +#ifndef __UNALIGNED_UINT32_READ +#pragma language=save +#pragma language=extended +__IAR_FT uint32_t __iar_uint32_read(void const *ptr) +{ + return *(__packed uint32_t*)(ptr); +} +#pragma language=restore +#define __UNALIGNED_UINT32_READ(PTR) __iar_uint32_read(PTR) +#endif + +#ifndef __UNALIGNED_UINT32_WRITE +#pragma language=save +#pragma language=extended +__IAR_FT void __iar_uint32_write(void const *ptr, uint32_t val) +{ + *(__packed uint32_t*)(ptr) = val;; +} +#pragma language=restore +#define __UNALIGNED_UINT32_WRITE(PTR,VAL) __iar_uint32_write(PTR,VAL) +#endif + +#ifndef __UNALIGNED_UINT32 /* deprecated */ +#pragma language=save +#pragma language=extended +__packed struct __iar_u32 { uint32_t v; }; +#pragma language=restore +#define __UNALIGNED_UINT32(PTR) (((struct __iar_u32 *)(PTR))->v) +#endif + +#ifndef __USED + #if __ICCARM_V8 + #define __USED __attribute__((used)) + #else + #define __USED _Pragma("__root") + #endif +#endif + +#ifndef __WEAK + #if __ICCARM_V8 + #define __WEAK __attribute__((weak)) + #else + #define __WEAK _Pragma("__weak") + #endif +#endif + +#ifndef __PROGRAM_START +#define __PROGRAM_START __iar_program_start +#endif + +#ifndef __INITIAL_SP +#define __INITIAL_SP CSTACK$$Limit +#endif + +#ifndef __STACK_LIMIT +#define __STACK_LIMIT CSTACK$$Base +#endif + +#ifndef __VECTOR_TABLE +#define __VECTOR_TABLE __vector_table +#endif + +#ifndef __VECTOR_TABLE_ATTRIBUTE +#define __VECTOR_TABLE_ATTRIBUTE @".intvec" +#endif + +#ifndef __ICCARM_INTRINSICS_VERSION__ + #define __ICCARM_INTRINSICS_VERSION__ 0 +#endif + +#if __ICCARM_INTRINSICS_VERSION__ == 2 + + #if defined(__CLZ) + #undef __CLZ + #endif + #if defined(__REVSH) + #undef __REVSH + #endif + #if defined(__RBIT) + #undef __RBIT + #endif + #if defined(__SSAT) + #undef __SSAT + #endif + #if defined(__USAT) + #undef __USAT + #endif + + #include "iccarm_builtin.h" + + #define __disable_fault_irq __iar_builtin_disable_fiq + #define __disable_irq __iar_builtin_disable_interrupt + #define __enable_fault_irq __iar_builtin_enable_fiq + #define __enable_irq __iar_builtin_enable_interrupt + #define __arm_rsr __iar_builtin_rsr + #define __arm_wsr __iar_builtin_wsr + + + #define __get_APSR() (__arm_rsr("APSR")) + #define __get_BASEPRI() (__arm_rsr("BASEPRI")) + #define __get_CONTROL() (__arm_rsr("CONTROL")) + #define __get_FAULTMASK() (__arm_rsr("FAULTMASK")) + + #if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) + #define __get_FPSCR() (__arm_rsr("FPSCR")) + #define __set_FPSCR(VALUE) (__arm_wsr("FPSCR", (VALUE))) + #else + #define __get_FPSCR() ( 0 ) + #define __set_FPSCR(VALUE) ((void)VALUE) + #endif + + #define __get_IPSR() (__arm_rsr("IPSR")) + #define __get_MSP() (__arm_rsr("MSP")) + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + #define __get_MSPLIM() (0U) + #else + #define __get_MSPLIM() (__arm_rsr("MSPLIM")) + #endif + #define __get_PRIMASK() (__arm_rsr("PRIMASK")) + #define __get_PSP() (__arm_rsr("PSP")) + + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + #define __get_PSPLIM() (0U) + #else + #define __get_PSPLIM() (__arm_rsr("PSPLIM")) + #endif + + #define __get_xPSR() (__arm_rsr("xPSR")) + + #define __set_BASEPRI(VALUE) (__arm_wsr("BASEPRI", (VALUE))) + #define __set_BASEPRI_MAX(VALUE) (__arm_wsr("BASEPRI_MAX", (VALUE))) + #define __set_CONTROL(VALUE) (__arm_wsr("CONTROL", (VALUE))) + #define __set_FAULTMASK(VALUE) (__arm_wsr("FAULTMASK", (VALUE))) + #define __set_MSP(VALUE) (__arm_wsr("MSP", (VALUE))) + + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + #define __set_MSPLIM(VALUE) ((void)(VALUE)) + #else + #define __set_MSPLIM(VALUE) (__arm_wsr("MSPLIM", (VALUE))) + #endif + #define __set_PRIMASK(VALUE) (__arm_wsr("PRIMASK", (VALUE))) + #define __set_PSP(VALUE) (__arm_wsr("PSP", (VALUE))) + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + #define __set_PSPLIM(VALUE) ((void)(VALUE)) + #else + #define __set_PSPLIM(VALUE) (__arm_wsr("PSPLIM", (VALUE))) + #endif + + #define __TZ_get_CONTROL_NS() (__arm_rsr("CONTROL_NS")) + #define __TZ_set_CONTROL_NS(VALUE) (__arm_wsr("CONTROL_NS", (VALUE))) + #define __TZ_get_PSP_NS() (__arm_rsr("PSP_NS")) + #define __TZ_set_PSP_NS(VALUE) (__arm_wsr("PSP_NS", (VALUE))) + #define __TZ_get_MSP_NS() (__arm_rsr("MSP_NS")) + #define __TZ_set_MSP_NS(VALUE) (__arm_wsr("MSP_NS", (VALUE))) + #define __TZ_get_SP_NS() (__arm_rsr("SP_NS")) + #define __TZ_set_SP_NS(VALUE) (__arm_wsr("SP_NS", (VALUE))) + #define __TZ_get_PRIMASK_NS() (__arm_rsr("PRIMASK_NS")) + #define __TZ_set_PRIMASK_NS(VALUE) (__arm_wsr("PRIMASK_NS", (VALUE))) + #define __TZ_get_BASEPRI_NS() (__arm_rsr("BASEPRI_NS")) + #define __TZ_set_BASEPRI_NS(VALUE) (__arm_wsr("BASEPRI_NS", (VALUE))) + #define __TZ_get_FAULTMASK_NS() (__arm_rsr("FAULTMASK_NS")) + #define __TZ_set_FAULTMASK_NS(VALUE)(__arm_wsr("FAULTMASK_NS", (VALUE))) + + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + #define __TZ_get_PSPLIM_NS() (0U) + #define __TZ_set_PSPLIM_NS(VALUE) ((void)(VALUE)) + #else + #define __TZ_get_PSPLIM_NS() (__arm_rsr("PSPLIM_NS")) + #define __TZ_set_PSPLIM_NS(VALUE) (__arm_wsr("PSPLIM_NS", (VALUE))) + #endif + + #define __TZ_get_MSPLIM_NS() (__arm_rsr("MSPLIM_NS")) + #define __TZ_set_MSPLIM_NS(VALUE) (__arm_wsr("MSPLIM_NS", (VALUE))) + + #define __NOP __iar_builtin_no_operation + + #define __CLZ __iar_builtin_CLZ + #define __CLREX __iar_builtin_CLREX + + #define __DMB __iar_builtin_DMB + #define __DSB __iar_builtin_DSB + #define __ISB __iar_builtin_ISB + + #define __LDREXB __iar_builtin_LDREXB + #define __LDREXH __iar_builtin_LDREXH + #define __LDREXW __iar_builtin_LDREX + + #define __RBIT __iar_builtin_RBIT + #define __REV __iar_builtin_REV + #define __REV16 __iar_builtin_REV16 + + __IAR_FT int16_t __REVSH(int16_t val) + { + return (int16_t) __iar_builtin_REVSH(val); + } + + #define __ROR __iar_builtin_ROR + #define __RRX __iar_builtin_RRX + + #define __SEV __iar_builtin_SEV + + #if !__IAR_M0_FAMILY + #define __SSAT __iar_builtin_SSAT + #endif + + #define __STREXB __iar_builtin_STREXB + #define __STREXH __iar_builtin_STREXH + #define __STREXW __iar_builtin_STREX + + #if !__IAR_M0_FAMILY + #define __USAT __iar_builtin_USAT + #endif + + #define __WFE __iar_builtin_WFE + #define __WFI __iar_builtin_WFI + + #if __ARM_MEDIA__ + #define __SADD8 __iar_builtin_SADD8 + #define __QADD8 __iar_builtin_QADD8 + #define __SHADD8 __iar_builtin_SHADD8 + #define __UADD8 __iar_builtin_UADD8 + #define __UQADD8 __iar_builtin_UQADD8 + #define __UHADD8 __iar_builtin_UHADD8 + #define __SSUB8 __iar_builtin_SSUB8 + #define __QSUB8 __iar_builtin_QSUB8 + #define __SHSUB8 __iar_builtin_SHSUB8 + #define __USUB8 __iar_builtin_USUB8 + #define __UQSUB8 __iar_builtin_UQSUB8 + #define __UHSUB8 __iar_builtin_UHSUB8 + #define __SADD16 __iar_builtin_SADD16 + #define __QADD16 __iar_builtin_QADD16 + #define __SHADD16 __iar_builtin_SHADD16 + #define __UADD16 __iar_builtin_UADD16 + #define __UQADD16 __iar_builtin_UQADD16 + #define __UHADD16 __iar_builtin_UHADD16 + #define __SSUB16 __iar_builtin_SSUB16 + #define __QSUB16 __iar_builtin_QSUB16 + #define __SHSUB16 __iar_builtin_SHSUB16 + #define __USUB16 __iar_builtin_USUB16 + #define __UQSUB16 __iar_builtin_UQSUB16 + #define __UHSUB16 __iar_builtin_UHSUB16 + #define __SASX __iar_builtin_SASX + #define __QASX __iar_builtin_QASX + #define __SHASX __iar_builtin_SHASX + #define __UASX __iar_builtin_UASX + #define __UQASX __iar_builtin_UQASX + #define __UHASX __iar_builtin_UHASX + #define __SSAX __iar_builtin_SSAX + #define __QSAX __iar_builtin_QSAX + #define __SHSAX __iar_builtin_SHSAX + #define __USAX __iar_builtin_USAX + #define __UQSAX __iar_builtin_UQSAX + #define __UHSAX __iar_builtin_UHSAX + #define __USAD8 __iar_builtin_USAD8 + #define __USADA8 __iar_builtin_USADA8 + #define __SSAT16 __iar_builtin_SSAT16 + #define __USAT16 __iar_builtin_USAT16 + #define __UXTB16 __iar_builtin_UXTB16 + #define __UXTAB16 __iar_builtin_UXTAB16 + #define __SXTB16 __iar_builtin_SXTB16 + #define __SXTAB16 __iar_builtin_SXTAB16 + #define __SMUAD __iar_builtin_SMUAD + #define __SMUADX __iar_builtin_SMUADX + #define __SMMLA __iar_builtin_SMMLA + #define __SMLAD __iar_builtin_SMLAD + #define __SMLADX __iar_builtin_SMLADX + #define __SMLALD __iar_builtin_SMLALD + #define __SMLALDX __iar_builtin_SMLALDX + #define __SMUSD __iar_builtin_SMUSD + #define __SMUSDX __iar_builtin_SMUSDX + #define __SMLSD __iar_builtin_SMLSD + #define __SMLSDX __iar_builtin_SMLSDX + #define __SMLSLD __iar_builtin_SMLSLD + #define __SMLSLDX __iar_builtin_SMLSLDX + #define __SEL __iar_builtin_SEL + #define __QADD __iar_builtin_QADD + #define __QSUB __iar_builtin_QSUB + #define __PKHBT __iar_builtin_PKHBT + #define __PKHTB __iar_builtin_PKHTB + #endif + +#else /* __ICCARM_INTRINSICS_VERSION__ == 2 */ + + #if __IAR_M0_FAMILY + /* Avoid clash between intrinsics.h and arm_math.h when compiling for Cortex-M0. */ + #define __CLZ __cmsis_iar_clz_not_active + #define __SSAT __cmsis_iar_ssat_not_active + #define __USAT __cmsis_iar_usat_not_active + #define __RBIT __cmsis_iar_rbit_not_active + #define __get_APSR __cmsis_iar_get_APSR_not_active + #endif + + + #if (!((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) )) + #define __get_FPSCR __cmsis_iar_get_FPSR_not_active + #define __set_FPSCR __cmsis_iar_set_FPSR_not_active + #endif + + #ifdef __INTRINSICS_INCLUDED + #error intrinsics.h is already included previously! + #endif + + #include + + #if __IAR_M0_FAMILY + /* Avoid clash between intrinsics.h and arm_math.h when compiling for Cortex-M0. */ + #undef __CLZ + #undef __SSAT + #undef __USAT + #undef __RBIT + #undef __get_APSR + + __STATIC_INLINE uint8_t __CLZ(uint32_t data) + { + if (data == 0U) { return 32U; } + + uint32_t count = 0U; + uint32_t mask = 0x80000000U; + + while ((data & mask) == 0U) + { + count += 1U; + mask = mask >> 1U; + } + return count; + } + + __STATIC_INLINE uint32_t __RBIT(uint32_t v) + { + uint8_t sc = 31U; + uint32_t r = v; + for (v >>= 1U; v; v >>= 1U) + { + r <<= 1U; + r |= v & 1U; + sc--; + } + return (r << sc); + } + + __STATIC_INLINE uint32_t __get_APSR(void) + { + uint32_t res; + __asm("MRS %0,APSR" : "=r" (res)); + return res; + } + + #endif + + #if (!((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) )) + #undef __get_FPSCR + #undef __set_FPSCR + #define __get_FPSCR() (0) + #define __set_FPSCR(VALUE) ((void)VALUE) + #endif + + #pragma diag_suppress=Pe940 + #pragma diag_suppress=Pe177 + + #define __enable_irq __enable_interrupt + #define __disable_irq __disable_interrupt + #define __NOP __no_operation + + #define __get_xPSR __get_PSR + + #if (!defined(__ARM_ARCH_6M__) || __ARM_ARCH_6M__==0) + + __IAR_FT uint32_t __LDREXW(uint32_t volatile *ptr) + { + return __LDREX((unsigned long *)ptr); + } + + __IAR_FT uint32_t __STREXW(uint32_t value, uint32_t volatile *ptr) + { + return __STREX(value, (unsigned long *)ptr); + } + #endif + + + /* __CORTEX_M is defined in core_cm0.h, core_cm3.h and core_cm4.h. */ + #if (__CORTEX_M >= 0x03) + + __IAR_FT uint32_t __RRX(uint32_t value) + { + uint32_t result; + __ASM volatile("RRX %0, %1" : "=r"(result) : "r" (value)); + return(result); + } + + __IAR_FT void __set_BASEPRI_MAX(uint32_t value) + { + __asm volatile("MSR BASEPRI_MAX,%0"::"r" (value)); + } + + + #define __enable_fault_irq __enable_fiq + #define __disable_fault_irq __disable_fiq + + + #endif /* (__CORTEX_M >= 0x03) */ + + __IAR_FT uint32_t __ROR(uint32_t op1, uint32_t op2) + { + return (op1 >> op2) | (op1 << ((sizeof(op1)*8)-op2)); + } + + #if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) + + __IAR_FT uint32_t __get_MSPLIM(void) + { + uint32_t res; + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + res = 0U; + #else + __asm volatile("MRS %0,MSPLIM" : "=r" (res)); + #endif + return res; + } + + __IAR_FT void __set_MSPLIM(uint32_t value) + { + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + (void)value; + #else + __asm volatile("MSR MSPLIM,%0" :: "r" (value)); + #endif + } + + __IAR_FT uint32_t __get_PSPLIM(void) + { + uint32_t res; + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + res = 0U; + #else + __asm volatile("MRS %0,PSPLIM" : "=r" (res)); + #endif + return res; + } + + __IAR_FT void __set_PSPLIM(uint32_t value) + { + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + (void)value; + #else + __asm volatile("MSR PSPLIM,%0" :: "r" (value)); + #endif + } + + __IAR_FT uint32_t __TZ_get_CONTROL_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,CONTROL_NS" : "=r" (res)); + return res; + } + + __IAR_FT void __TZ_set_CONTROL_NS(uint32_t value) + { + __asm volatile("MSR CONTROL_NS,%0" :: "r" (value)); + } + + __IAR_FT uint32_t __TZ_get_PSP_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,PSP_NS" : "=r" (res)); + return res; + } + + __IAR_FT void __TZ_set_PSP_NS(uint32_t value) + { + __asm volatile("MSR PSP_NS,%0" :: "r" (value)); + } + + __IAR_FT uint32_t __TZ_get_MSP_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,MSP_NS" : "=r" (res)); + return res; + } + + __IAR_FT void __TZ_set_MSP_NS(uint32_t value) + { + __asm volatile("MSR MSP_NS,%0" :: "r" (value)); + } + + __IAR_FT uint32_t __TZ_get_SP_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,SP_NS" : "=r" (res)); + return res; + } + __IAR_FT void __TZ_set_SP_NS(uint32_t value) + { + __asm volatile("MSR SP_NS,%0" :: "r" (value)); + } + + __IAR_FT uint32_t __TZ_get_PRIMASK_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,PRIMASK_NS" : "=r" (res)); + return res; + } + + __IAR_FT void __TZ_set_PRIMASK_NS(uint32_t value) + { + __asm volatile("MSR PRIMASK_NS,%0" :: "r" (value)); + } + + __IAR_FT uint32_t __TZ_get_BASEPRI_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,BASEPRI_NS" : "=r" (res)); + return res; + } + + __IAR_FT void __TZ_set_BASEPRI_NS(uint32_t value) + { + __asm volatile("MSR BASEPRI_NS,%0" :: "r" (value)); + } + + __IAR_FT uint32_t __TZ_get_FAULTMASK_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,FAULTMASK_NS" : "=r" (res)); + return res; + } + + __IAR_FT void __TZ_set_FAULTMASK_NS(uint32_t value) + { + __asm volatile("MSR FAULTMASK_NS,%0" :: "r" (value)); + } + + __IAR_FT uint32_t __TZ_get_PSPLIM_NS(void) + { + uint32_t res; + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + res = 0U; + #else + __asm volatile("MRS %0,PSPLIM_NS" : "=r" (res)); + #endif + return res; + } + + __IAR_FT void __TZ_set_PSPLIM_NS(uint32_t value) + { + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + (void)value; + #else + __asm volatile("MSR PSPLIM_NS,%0" :: "r" (value)); + #endif + } + + __IAR_FT uint32_t __TZ_get_MSPLIM_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,MSPLIM_NS" : "=r" (res)); + return res; + } + + __IAR_FT void __TZ_set_MSPLIM_NS(uint32_t value) + { + __asm volatile("MSR MSPLIM_NS,%0" :: "r" (value)); + } + + #endif /* __ARM_ARCH_8M_MAIN__ or __ARM_ARCH_8M_BASE__ */ + +#endif /* __ICCARM_INTRINSICS_VERSION__ == 2 */ + +#define __BKPT(value) __asm volatile ("BKPT %0" : : "i"(value)) + +#if __IAR_M0_FAMILY + __STATIC_INLINE int32_t __SSAT(int32_t val, uint32_t sat) + { + if ((sat >= 1U) && (sat <= 32U)) + { + const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U); + const int32_t min = -1 - max ; + if (val > max) + { + return max; + } + else if (val < min) + { + return min; + } + } + return val; + } + + __STATIC_INLINE uint32_t __USAT(int32_t val, uint32_t sat) + { + if (sat <= 31U) + { + const uint32_t max = ((1U << sat) - 1U); + if (val > (int32_t)max) + { + return max; + } + else if (val < 0) + { + return 0U; + } + } + return (uint32_t)val; + } +#endif + +#if (__CORTEX_M >= 0x03) /* __CORTEX_M is defined in core_cm0.h, core_cm3.h and core_cm4.h. */ + + __IAR_FT uint8_t __LDRBT(volatile uint8_t *addr) + { + uint32_t res; + __ASM volatile ("LDRBT %0, [%1]" : "=r" (res) : "r" (addr) : "memory"); + return ((uint8_t)res); + } + + __IAR_FT uint16_t __LDRHT(volatile uint16_t *addr) + { + uint32_t res; + __ASM volatile ("LDRHT %0, [%1]" : "=r" (res) : "r" (addr) : "memory"); + return ((uint16_t)res); + } + + __IAR_FT uint32_t __LDRT(volatile uint32_t *addr) + { + uint32_t res; + __ASM volatile ("LDRT %0, [%1]" : "=r" (res) : "r" (addr) : "memory"); + return res; + } + + __IAR_FT void __STRBT(uint8_t value, volatile uint8_t *addr) + { + __ASM volatile ("STRBT %1, [%0]" : : "r" (addr), "r" ((uint32_t)value) : "memory"); + } + + __IAR_FT void __STRHT(uint16_t value, volatile uint16_t *addr) + { + __ASM volatile ("STRHT %1, [%0]" : : "r" (addr), "r" ((uint32_t)value) : "memory"); + } + + __IAR_FT void __STRT(uint32_t value, volatile uint32_t *addr) + { + __ASM volatile ("STRT %1, [%0]" : : "r" (addr), "r" (value) : "memory"); + } + +#endif /* (__CORTEX_M >= 0x03) */ + +#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) + + + __IAR_FT uint8_t __LDAB(volatile uint8_t *ptr) + { + uint32_t res; + __ASM volatile ("LDAB %0, [%1]" : "=r" (res) : "r" (ptr) : "memory"); + return ((uint8_t)res); + } + + __IAR_FT uint16_t __LDAH(volatile uint16_t *ptr) + { + uint32_t res; + __ASM volatile ("LDAH %0, [%1]" : "=r" (res) : "r" (ptr) : "memory"); + return ((uint16_t)res); + } + + __IAR_FT uint32_t __LDA(volatile uint32_t *ptr) + { + uint32_t res; + __ASM volatile ("LDA %0, [%1]" : "=r" (res) : "r" (ptr) : "memory"); + return res; + } + + __IAR_FT void __STLB(uint8_t value, volatile uint8_t *ptr) + { + __ASM volatile ("STLB %1, [%0]" :: "r" (ptr), "r" (value) : "memory"); + } + + __IAR_FT void __STLH(uint16_t value, volatile uint16_t *ptr) + { + __ASM volatile ("STLH %1, [%0]" :: "r" (ptr), "r" (value) : "memory"); + } + + __IAR_FT void __STL(uint32_t value, volatile uint32_t *ptr) + { + __ASM volatile ("STL %1, [%0]" :: "r" (ptr), "r" (value) : "memory"); + } + + __IAR_FT uint8_t __LDAEXB(volatile uint8_t *ptr) + { + uint32_t res; + __ASM volatile ("LDAEXB %0, [%1]" : "=r" (res) : "r" (ptr) : "memory"); + return ((uint8_t)res); + } + + __IAR_FT uint16_t __LDAEXH(volatile uint16_t *ptr) + { + uint32_t res; + __ASM volatile ("LDAEXH %0, [%1]" : "=r" (res) : "r" (ptr) : "memory"); + return ((uint16_t)res); + } + + __IAR_FT uint32_t __LDAEX(volatile uint32_t *ptr) + { + uint32_t res; + __ASM volatile ("LDAEX %0, [%1]" : "=r" (res) : "r" (ptr) : "memory"); + return res; + } + + __IAR_FT uint32_t __STLEXB(uint8_t value, volatile uint8_t *ptr) + { + uint32_t res; + __ASM volatile ("STLEXB %0, %2, [%1]" : "=r" (res) : "r" (ptr), "r" (value) : "memory"); + return res; + } + + __IAR_FT uint32_t __STLEXH(uint16_t value, volatile uint16_t *ptr) + { + uint32_t res; + __ASM volatile ("STLEXH %0, %2, [%1]" : "=r" (res) : "r" (ptr), "r" (value) : "memory"); + return res; + } + + __IAR_FT uint32_t __STLEX(uint32_t value, volatile uint32_t *ptr) + { + uint32_t res; + __ASM volatile ("STLEX %0, %2, [%1]" : "=r" (res) : "r" (ptr), "r" (value) : "memory"); + return res; + } + +#endif /* __ARM_ARCH_8M_MAIN__ or __ARM_ARCH_8M_BASE__ */ + +#undef __IAR_FT +#undef __IAR_M0_FAMILY +#undef __ICCARM_V8 + +#pragma diag_default=Pe940 +#pragma diag_default=Pe177 + +#define __SXTB16_RORn(ARG1, ARG2) __SXTB16(__ROR(ARG1, ARG2)) + +#endif /* __CMSIS_ICCARM_H__ */ diff --git a/bootloader/inc/cmsis_version.h b/bootloader/inc/cmsis_version.h new file mode 100644 index 0000000..2f048e4 --- /dev/null +++ b/bootloader/inc/cmsis_version.h @@ -0,0 +1,39 @@ +/**************************************************************************//** + * @file cmsis_version.h + * @brief CMSIS Core(M) Version definitions + * @version V5.0.4 + * @date 23. July 2019 + ******************************************************************************/ +/* + * Copyright (c) 2009-2019 ARM Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CMSIS_VERSION_H +#define __CMSIS_VERSION_H + +/* CMSIS Version definitions */ +#define __CM_CMSIS_VERSION_MAIN ( 5U) /*!< [31:16] CMSIS Core(M) main version */ +#define __CM_CMSIS_VERSION_SUB ( 4U) /*!< [15:0] CMSIS Core(M) sub version */ +#define __CM_CMSIS_VERSION ((__CM_CMSIS_VERSION_MAIN << 16U) | \ + __CM_CMSIS_VERSION_SUB ) /*!< CMSIS Core(M) version number */ +#endif diff --git a/bootloader/inc/core_cm3.h b/bootloader/inc/core_cm3.h new file mode 100644 index 0000000..e568fa3 --- /dev/null +++ b/bootloader/inc/core_cm3.h @@ -0,0 +1,1938 @@ +/**************************************************************************//** + * @file core_cm3.h + * @brief CMSIS Cortex-M3 Core Peripheral Access Layer Header File + * @version V5.1.1 + * @date 19. August 2019 + ******************************************************************************/ +/* + * Copyright (c) 2009-2019 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_CM3_H_GENERIC +#define __CORE_CM3_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_M3 + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS CM3 definitions */ +#define __CM3_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __CM3_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __CM3_CMSIS_VERSION ((__CM3_CMSIS_VERSION_MAIN << 16U) | \ + __CM3_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M (3U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + This core does not support an FPU at all +*/ +#define __FPU_USED 0U + +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_FP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM3_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM3_H_DEPENDANT +#define __CORE_CM3_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM3_REV + #define __CM3_REV 0x0200U + #warning "__CM3_REV not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 3U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group Cortex_M3 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + +#define APSR_Q_Pos 27U /*!< APSR: Q Position */ +#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:1; /*!< bit: 9 Reserved */ + uint32_t ICI_IT_1:6; /*!< bit: 10..15 ICI/IT part 1 */ + uint32_t _reserved1:8; /*!< bit: 16..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit */ + uint32_t ICI_IT_2:2; /*!< bit: 25..26 ICI/IT part 2 */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ +#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ + +#define xPSR_ICI_IT_2_Pos 25U /*!< xPSR: ICI/IT part 2 Position */ +#define xPSR_ICI_IT_2_Msk (3UL << xPSR_ICI_IT_2_Pos) /*!< xPSR: ICI/IT part 2 Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_ICI_IT_1_Pos 10U /*!< xPSR: ICI/IT part 1 Position */ +#define xPSR_ICI_IT_1_Msk (0x3FUL << xPSR_ICI_IT_1_Pos) /*!< xPSR: ICI/IT part 1 Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[8U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[24U]; + __IOM uint32_t ICER[8U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RESERVED1[24U]; + __IOM uint32_t ISPR[8U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[24U]; + __IOM uint32_t ICPR[8U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[24U]; + __IOM uint32_t IABR[8U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[56U]; + __IOM uint8_t IP[240U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED5[644U]; + __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ +} NVIC_Type; + +/* Software Triggered Interrupt Register Definitions */ +#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ +#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + __IOM uint8_t SHP[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ + __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ + __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ + __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ + __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ + __IM uint32_t PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + __IM uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + __IM uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + __IM uint32_t MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + __IM uint32_t ISAR[5U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ + uint32_t RESERVED0[5U]; + __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Vector Table Offset Register Definitions */ +#if defined (__CM3_REV) && (__CM3_REV < 0x0201U) /* core r2p1 */ +#define SCB_VTOR_TBLBASE_Pos 29U /*!< SCB VTOR: TBLBASE Position */ +#define SCB_VTOR_TBLBASE_Msk (1UL << SCB_VTOR_TBLBASE_Pos) /*!< SCB VTOR: TBLBASE Mask */ + +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x3FFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ +#else +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ +#endif + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +#define SCB_AIRCR_VECTRESET_Pos 0U /*!< SCB AIRCR: VECTRESET Position */ +#define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) /*!< SCB AIRCR: VECTRESET Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +#define SCB_CCR_NONBASETHRDENA_Pos 0U /*!< SCB CCR: NONBASETHRDENA Position */ +#define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) /*!< SCB CCR: NONBASETHRDENA Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/* SCB Configurable Fault Status Register Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ +#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ + +#define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ +#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ + +#define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ +#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ + +#define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ +#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ + +#define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ +#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ + +/* BusFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ +#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ + +#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ +#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ + +#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ +#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ + +#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ +#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ + +#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ +#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ + +#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ +#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ + +/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ +#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ + +#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ +#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ + +#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ +#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ + +#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ +#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ + +#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ +#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ + +#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ +#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ + +/* SCB Hard Fault Status Register Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/* SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** + \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ +#if defined (__CM3_REV) && (__CM3_REV >= 0x200U) + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ +#else + uint32_t RESERVED1[1U]; +#endif +} SCnSCB_Type; + +/* Interrupt Controller Type Register Definitions */ +#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ +#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ + +/* Auxiliary Control Register Definitions */ +#if defined (__CM3_REV) && (__CM3_REV >= 0x200U) +#define SCnSCB_ACTLR_DISOOFP_Pos 9U /*!< ACTLR: DISOOFP Position */ +#define SCnSCB_ACTLR_DISOOFP_Msk (1UL << SCnSCB_ACTLR_DISOOFP_Pos) /*!< ACTLR: DISOOFP Mask */ + +#define SCnSCB_ACTLR_DISFPCA_Pos 8U /*!< ACTLR: DISFPCA Position */ +#define SCnSCB_ACTLR_DISFPCA_Msk (1UL << SCnSCB_ACTLR_DISFPCA_Pos) /*!< ACTLR: DISFPCA Mask */ + +#define SCnSCB_ACTLR_DISFOLD_Pos 2U /*!< ACTLR: DISFOLD Position */ +#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */ + +#define SCnSCB_ACTLR_DISDEFWBUF_Pos 1U /*!< ACTLR: DISDEFWBUF Position */ +#define SCnSCB_ACTLR_DISDEFWBUF_Msk (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos) /*!< ACTLR: DISDEFWBUF Mask */ + +#define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /*!< ACTLR: DISMCYCINT Position */ +#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */ +#endif + +/*@} end of group CMSIS_SCnotSCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) + \brief Type definitions for the Instrumentation Trace Macrocell (ITM) + @{ + */ + +/** + \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). + */ +typedef struct +{ + __OM union + { + __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ + __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ + __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ + } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ + uint32_t RESERVED0[864U]; + __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ + uint32_t RESERVED1[15U]; + __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ + uint32_t RESERVED2[15U]; + __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ + uint32_t RESERVED3[32U]; + uint32_t RESERVED4[43U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ + uint32_t RESERVED5[6U]; + __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ + __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ + __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ + __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ + __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ + __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ + __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ + __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ + __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ + __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ + __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ + __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ +} ITM_Type; + +/* ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFFFFFFFFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ + +/* ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_TraceBusID_Pos 16U /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ +#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ + +#define ITM_TCR_TSPrescale_Pos 8U /*!< ITM TCR: TSPrescale Position */ +#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */ + +#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ + +/* ITM Lock Status Register Definitions */ +#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ +#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ + +#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ +#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ + +#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ +#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ + +/*@}*/ /* end of group CMSIS_ITM */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ + __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ + __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ + __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ + __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ + __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + __IOM uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */ + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED0[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + __IOM uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */ + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + __IOM uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */ + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + __IOM uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */ + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ +#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ + +#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ +#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ + +#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ +#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ + +#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ +#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ + +#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ +#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ + +#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ +#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ + +#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ +#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ + +#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ +#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ + +#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ +#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ + +#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ +#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ + +#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ +#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ + +#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ +#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ + +#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ +#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ + +/* DWT CPI Count Register Definitions */ +#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ +#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ + +/* DWT Exception Overhead Count Register Definitions */ +#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ +#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ + +/* DWT Sleep Count Register Definitions */ +#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ +#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ + +/* DWT LSU Count Register Definitions */ +#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ +#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ + +/* DWT Folded-instruction Count Register Definitions */ +#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ +#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ + +/* DWT Comparator Mask Register Definitions */ +#define DWT_MASK_MASK_Pos 0U /*!< DWT MASK: MASK Position */ +#define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/) /*!< DWT MASK: MASK Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVADDR1_Pos 16U /*!< DWT FUNCTION: DATAVADDR1 Position */ +#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */ + +#define DWT_FUNCTION_DATAVADDR0_Pos 12U /*!< DWT FUNCTION: DATAVADDR0 Position */ +#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_LNK1ENA_Pos 9U /*!< DWT FUNCTION: LNK1ENA Position */ +#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */ + +#define DWT_FUNCTION_DATAVMATCH_Pos 8U /*!< DWT FUNCTION: DATAVMATCH Position */ +#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */ + +#define DWT_FUNCTION_CYCMATCH_Pos 7U /*!< DWT FUNCTION: CYCMATCH Position */ +#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */ + +#define DWT_FUNCTION_EMITRANGE_Pos 5U /*!< DWT FUNCTION: EMITRANGE Position */ +#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */ + +#define DWT_FUNCTION_FUNCTION_Pos 0U /*!< DWT FUNCTION: FUNCTION Position */ +#define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/) /*!< DWT FUNCTION: FUNCTION Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */ + uint32_t RESERVED3[759U]; + __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER Register */ + __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ + __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ + uint32_t RESERVED4[1U]; + __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */ + __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */ + __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ + uint32_t RESERVED5[39U]; + __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ + __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ + uint32_t RESERVED7[8U]; + __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */ +#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI TRIGGER Register Definitions */ +#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ +#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ + +/* TPI Integration ETM Data Register Definitions (FIFO0) */ +#define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */ +#define TPI_FIFO0_ITM_ATVALID_Msk (0x1UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */ + +#define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */ +#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */ + +#define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */ +#define TPI_FIFO0_ETM_ATVALID_Msk (0x1UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */ + +#define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */ +#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */ + +#define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */ +#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */ + +#define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */ +#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */ + +#define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */ +#define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */ + +/* TPI ITATBCTR2 Register Definitions */ +#define TPI_ITATBCTR2_ATREADY2_Pos 0U /*!< TPI ITATBCTR2: ATREADY2 Position */ +#define TPI_ITATBCTR2_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY2_Pos*/) /*!< TPI ITATBCTR2: ATREADY2 Mask */ + +#define TPI_ITATBCTR2_ATREADY1_Pos 0U /*!< TPI ITATBCTR2: ATREADY1 Position */ +#define TPI_ITATBCTR2_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY1_Pos*/) /*!< TPI ITATBCTR2: ATREADY1 Mask */ + +/* TPI Integration ITM Data Register Definitions (FIFO1) */ +#define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */ +#define TPI_FIFO1_ITM_ATVALID_Msk (0x1UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */ + +#define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */ +#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */ + +#define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */ +#define TPI_FIFO1_ETM_ATVALID_Msk (0x1UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */ + +#define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */ +#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */ + +#define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */ +#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */ + +#define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */ +#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */ + +#define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */ +#define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */ + +/* TPI ITATBCTR0 Register Definitions */ +#define TPI_ITATBCTR0_ATREADY2_Pos 0U /*!< TPI ITATBCTR0: ATREADY2 Position */ +#define TPI_ITATBCTR0_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY2_Pos*/) /*!< TPI ITATBCTR0: ATREADY2 Mask */ + +#define TPI_ITATBCTR0_ATREADY1_Pos 0U /*!< TPI ITATBCTR0: ATREADY1 Position */ +#define TPI_ITATBCTR0_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY1_Pos*/) /*!< TPI ITATBCTR0: ATREADY1 Mask */ + +/* TPI Integration Mode Control Register Definitions */ +#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ +#define TPI_ITCTRL_Mode_Msk (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */ +#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */ + +#define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */ +#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */ + +#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ +#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ + +#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ + __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */ + __IOM uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */ + __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */ + __IOM uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */ + __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */ + __IOM uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */ +} MPU_Type; + +#define MPU_TYPE_RALIASES 4U + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_ADDR_Pos 5U /*!< MPU RBAR: ADDR Position */ +#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ + +#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */ +#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ + +#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */ +#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */ + +/* MPU Region Attribute and Size Register Definitions */ +#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */ +#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ + +#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */ +#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ + +#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */ +#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ + +#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */ +#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ + +#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */ +#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ + +#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */ +#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ + +#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */ +#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ + +#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */ +#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ + +#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */ +#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ + +#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */ +#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** + \brief Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ +#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register Definitions */ +#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */ +#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ + +#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */ +#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ + +#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */ +#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ + +#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */ +#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ + +#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */ +#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */ +#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ + +#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */ +#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ + +#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */ +#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ + +#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */ +#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ + +#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */ +#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ + +#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */ +#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ +#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ +#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ +#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ +#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ +#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ +#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ +#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ +#endif + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ + #define NVIC_GetActive __NVIC_GetActive + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* The following EXC_RETURN values are saved the LR on exception entry */ +#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */ +#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */ +#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */ + + +/** + \brief Set Priority Grouping + \details Sets the priority grouping field using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping + \details Reads the priority grouping field from the NVIC Interrupt Controller. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) +{ + return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + __COMPILER_BARRIER(); + NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __COMPILER_BARRIER(); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IP[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC->IP[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; + /* ARM Application Note 321 states that the M3 does not require the architectural barrier */ +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +/*@} end of CMSIS_Core_NVICFunctions */ + + +/* ########################## MPU functions #################################### */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + +#include "mpu_armv7.h" + +#endif + + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + return 0U; /* No FPU */ +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + +/* ##################################### Debug In/Output function ########################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_core_DebugFunctions ITM Functions + \brief Functions that access the ITM debug interface. + @{ + */ + +extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ +#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ + + +/** + \brief ITM Send Character + \details Transmits a character via the ITM channel 0, and + \li Just returns when no debugger is connected that has booked the output. + \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. + \param [in] ch Character to transmit. + \returns Character to transmit. + */ +__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) +{ + if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ + ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ + { + while (ITM->PORT[0U].u32 == 0UL) + { + __NOP(); + } + ITM->PORT[0U].u8 = (uint8_t)ch; + } + return (ch); +} + + +/** + \brief ITM Receive Character + \details Inputs a character via the external variable \ref ITM_RxBuffer. + \return Received character. + \return -1 No character pending. + */ +__STATIC_INLINE int32_t ITM_ReceiveChar (void) +{ + int32_t ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) + { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** + \brief ITM Check Character + \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. + \return 0 No character available. + \return 1 Character available. + */ +__STATIC_INLINE int32_t ITM_CheckChar (void) +{ + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) + { + return (0); /* no character available */ + } + else + { + return (1); /* character available */ + } +} + +/*@} end of CMSIS_core_DebugFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM3_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/bootloader/inc/mpu_armv7.h b/bootloader/inc/mpu_armv7.h new file mode 100644 index 0000000..786bed7 --- /dev/null +++ b/bootloader/inc/mpu_armv7.h @@ -0,0 +1,272 @@ +/****************************************************************************** + * @file mpu_armv7.h + * @brief CMSIS MPU API for Armv7-M MPU + * @version V5.1.0 + * @date 08. March 2019 + ******************************************************************************/ +/* + * Copyright (c) 2017-2019 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef ARM_MPU_ARMV7_H +#define ARM_MPU_ARMV7_H + +#define ARM_MPU_REGION_SIZE_32B ((uint8_t)0x04U) ///!< MPU Region Size 32 Bytes +#define ARM_MPU_REGION_SIZE_64B ((uint8_t)0x05U) ///!< MPU Region Size 64 Bytes +#define ARM_MPU_REGION_SIZE_128B ((uint8_t)0x06U) ///!< MPU Region Size 128 Bytes +#define ARM_MPU_REGION_SIZE_256B ((uint8_t)0x07U) ///!< MPU Region Size 256 Bytes +#define ARM_MPU_REGION_SIZE_512B ((uint8_t)0x08U) ///!< MPU Region Size 512 Bytes +#define ARM_MPU_REGION_SIZE_1KB ((uint8_t)0x09U) ///!< MPU Region Size 1 KByte +#define ARM_MPU_REGION_SIZE_2KB ((uint8_t)0x0AU) ///!< MPU Region Size 2 KBytes +#define ARM_MPU_REGION_SIZE_4KB ((uint8_t)0x0BU) ///!< MPU Region Size 4 KBytes +#define ARM_MPU_REGION_SIZE_8KB ((uint8_t)0x0CU) ///!< MPU Region Size 8 KBytes +#define ARM_MPU_REGION_SIZE_16KB ((uint8_t)0x0DU) ///!< MPU Region Size 16 KBytes +#define ARM_MPU_REGION_SIZE_32KB ((uint8_t)0x0EU) ///!< MPU Region Size 32 KBytes +#define ARM_MPU_REGION_SIZE_64KB ((uint8_t)0x0FU) ///!< MPU Region Size 64 KBytes +#define ARM_MPU_REGION_SIZE_128KB ((uint8_t)0x10U) ///!< MPU Region Size 128 KBytes +#define ARM_MPU_REGION_SIZE_256KB ((uint8_t)0x11U) ///!< MPU Region Size 256 KBytes +#define ARM_MPU_REGION_SIZE_512KB ((uint8_t)0x12U) ///!< MPU Region Size 512 KBytes +#define ARM_MPU_REGION_SIZE_1MB ((uint8_t)0x13U) ///!< MPU Region Size 1 MByte +#define ARM_MPU_REGION_SIZE_2MB ((uint8_t)0x14U) ///!< MPU Region Size 2 MBytes +#define ARM_MPU_REGION_SIZE_4MB ((uint8_t)0x15U) ///!< MPU Region Size 4 MBytes +#define ARM_MPU_REGION_SIZE_8MB ((uint8_t)0x16U) ///!< MPU Region Size 8 MBytes +#define ARM_MPU_REGION_SIZE_16MB ((uint8_t)0x17U) ///!< MPU Region Size 16 MBytes +#define ARM_MPU_REGION_SIZE_32MB ((uint8_t)0x18U) ///!< MPU Region Size 32 MBytes +#define ARM_MPU_REGION_SIZE_64MB ((uint8_t)0x19U) ///!< MPU Region Size 64 MBytes +#define ARM_MPU_REGION_SIZE_128MB ((uint8_t)0x1AU) ///!< MPU Region Size 128 MBytes +#define ARM_MPU_REGION_SIZE_256MB ((uint8_t)0x1BU) ///!< MPU Region Size 256 MBytes +#define ARM_MPU_REGION_SIZE_512MB ((uint8_t)0x1CU) ///!< MPU Region Size 512 MBytes +#define ARM_MPU_REGION_SIZE_1GB ((uint8_t)0x1DU) ///!< MPU Region Size 1 GByte +#define ARM_MPU_REGION_SIZE_2GB ((uint8_t)0x1EU) ///!< MPU Region Size 2 GBytes +#define ARM_MPU_REGION_SIZE_4GB ((uint8_t)0x1FU) ///!< MPU Region Size 4 GBytes + +#define ARM_MPU_AP_NONE 0U ///!< MPU Access Permission no access +#define ARM_MPU_AP_PRIV 1U ///!< MPU Access Permission privileged access only +#define ARM_MPU_AP_URO 2U ///!< MPU Access Permission unprivileged access read-only +#define ARM_MPU_AP_FULL 3U ///!< MPU Access Permission full access +#define ARM_MPU_AP_PRO 5U ///!< MPU Access Permission privileged access read-only +#define ARM_MPU_AP_RO 6U ///!< MPU Access Permission read-only access + +/** MPU Region Base Address Register Value +* +* \param Region The region to be configured, number 0 to 15. +* \param BaseAddress The base address for the region. +*/ +#define ARM_MPU_RBAR(Region, BaseAddress) \ + (((BaseAddress) & MPU_RBAR_ADDR_Msk) | \ + ((Region) & MPU_RBAR_REGION_Msk) | \ + (MPU_RBAR_VALID_Msk)) + +/** +* MPU Memory Access Attributes +* +* \param TypeExtField Type extension field, allows you to configure memory access type, for example strongly ordered, peripheral. +* \param IsShareable Region is shareable between multiple bus masters. +* \param IsCacheable Region is cacheable, i.e. its value may be kept in cache. +* \param IsBufferable Region is bufferable, i.e. using write-back caching. Cacheable but non-bufferable regions use write-through policy. +*/ +#define ARM_MPU_ACCESS_(TypeExtField, IsShareable, IsCacheable, IsBufferable) \ + ((((TypeExtField) << MPU_RASR_TEX_Pos) & MPU_RASR_TEX_Msk) | \ + (((IsShareable) << MPU_RASR_S_Pos) & MPU_RASR_S_Msk) | \ + (((IsCacheable) << MPU_RASR_C_Pos) & MPU_RASR_C_Msk) | \ + (((IsBufferable) << MPU_RASR_B_Pos) & MPU_RASR_B_Msk)) + +/** +* MPU Region Attribute and Size Register Value +* +* \param DisableExec Instruction access disable bit, 1= disable instruction fetches. +* \param AccessPermission Data access permissions, allows you to configure read/write access for User and Privileged mode. +* \param AccessAttributes Memory access attribution, see \ref ARM_MPU_ACCESS_. +* \param SubRegionDisable Sub-region disable field. +* \param Size Region size of the region to be configured, for example 4K, 8K. +*/ +#define ARM_MPU_RASR_EX(DisableExec, AccessPermission, AccessAttributes, SubRegionDisable, Size) \ + ((((DisableExec) << MPU_RASR_XN_Pos) & MPU_RASR_XN_Msk) | \ + (((AccessPermission) << MPU_RASR_AP_Pos) & MPU_RASR_AP_Msk) | \ + (((AccessAttributes) & (MPU_RASR_TEX_Msk | MPU_RASR_S_Msk | MPU_RASR_C_Msk | MPU_RASR_B_Msk))) | \ + (((SubRegionDisable) << MPU_RASR_SRD_Pos) & MPU_RASR_SRD_Msk) | \ + (((Size) << MPU_RASR_SIZE_Pos) & MPU_RASR_SIZE_Msk) | \ + (((MPU_RASR_ENABLE_Msk)))) + +/** +* MPU Region Attribute and Size Register Value +* +* \param DisableExec Instruction access disable bit, 1= disable instruction fetches. +* \param AccessPermission Data access permissions, allows you to configure read/write access for User and Privileged mode. +* \param TypeExtField Type extension field, allows you to configure memory access type, for example strongly ordered, peripheral. +* \param IsShareable Region is shareable between multiple bus masters. +* \param IsCacheable Region is cacheable, i.e. its value may be kept in cache. +* \param IsBufferable Region is bufferable, i.e. using write-back caching. Cacheable but non-bufferable regions use write-through policy. +* \param SubRegionDisable Sub-region disable field. +* \param Size Region size of the region to be configured, for example 4K, 8K. +*/ +#define ARM_MPU_RASR(DisableExec, AccessPermission, TypeExtField, IsShareable, IsCacheable, IsBufferable, SubRegionDisable, Size) \ + ARM_MPU_RASR_EX(DisableExec, AccessPermission, ARM_MPU_ACCESS_(TypeExtField, IsShareable, IsCacheable, IsBufferable), SubRegionDisable, Size) + +/** +* MPU Memory Access Attribute for strongly ordered memory. +* - TEX: 000b +* - Shareable +* - Non-cacheable +* - Non-bufferable +*/ +#define ARM_MPU_ACCESS_ORDERED ARM_MPU_ACCESS_(0U, 1U, 0U, 0U) + +/** +* MPU Memory Access Attribute for device memory. +* - TEX: 000b (if shareable) or 010b (if non-shareable) +* - Shareable or non-shareable +* - Non-cacheable +* - Bufferable (if shareable) or non-bufferable (if non-shareable) +* +* \param IsShareable Configures the device memory as shareable or non-shareable. +*/ +#define ARM_MPU_ACCESS_DEVICE(IsShareable) ((IsShareable) ? ARM_MPU_ACCESS_(0U, 1U, 0U, 1U) : ARM_MPU_ACCESS_(2U, 0U, 0U, 0U)) + +/** +* MPU Memory Access Attribute for normal memory. +* - TEX: 1BBb (reflecting outer cacheability rules) +* - Shareable or non-shareable +* - Cacheable or non-cacheable (reflecting inner cacheability rules) +* - Bufferable or non-bufferable (reflecting inner cacheability rules) +* +* \param OuterCp Configures the outer cache policy. +* \param InnerCp Configures the inner cache policy. +* \param IsShareable Configures the memory as shareable or non-shareable. +*/ +#define ARM_MPU_ACCESS_NORMAL(OuterCp, InnerCp, IsShareable) ARM_MPU_ACCESS_((4U | (OuterCp)), IsShareable, ((InnerCp) >> 1U), ((InnerCp) & 1U)) + +/** +* MPU Memory Access Attribute non-cacheable policy. +*/ +#define ARM_MPU_CACHEP_NOCACHE 0U + +/** +* MPU Memory Access Attribute write-back, write and read allocate policy. +*/ +#define ARM_MPU_CACHEP_WB_WRA 1U + +/** +* MPU Memory Access Attribute write-through, no write allocate policy. +*/ +#define ARM_MPU_CACHEP_WT_NWA 2U + +/** +* MPU Memory Access Attribute write-back, no write allocate policy. +*/ +#define ARM_MPU_CACHEP_WB_NWA 3U + + +/** +* Struct for a single MPU Region +*/ +typedef struct { + uint32_t RBAR; //!< The region base address register value (RBAR) + uint32_t RASR; //!< The region attribute and size register value (RASR) \ref MPU_RASR +} ARM_MPU_Region_t; + +/** Enable the MPU. +* \param MPU_Control Default access permissions for unconfigured regions. +*/ +__STATIC_INLINE void ARM_MPU_Enable(uint32_t MPU_Control) +{ + MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk; +#ifdef SCB_SHCSR_MEMFAULTENA_Msk + SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk; +#endif + __DSB(); + __ISB(); +} + +/** Disable the MPU. +*/ +__STATIC_INLINE void ARM_MPU_Disable(void) +{ + __DMB(); +#ifdef SCB_SHCSR_MEMFAULTENA_Msk + SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk; +#endif + MPU->CTRL &= ~MPU_CTRL_ENABLE_Msk; +} + +/** Clear and disable the given MPU region. +* \param rnr Region number to be cleared. +*/ +__STATIC_INLINE void ARM_MPU_ClrRegion(uint32_t rnr) +{ + MPU->RNR = rnr; + MPU->RASR = 0U; +} + +/** Configure an MPU region. +* \param rbar Value for RBAR register. +* \param rsar Value for RSAR register. +*/ +__STATIC_INLINE void ARM_MPU_SetRegion(uint32_t rbar, uint32_t rasr) +{ + MPU->RBAR = rbar; + MPU->RASR = rasr; +} + +/** Configure the given MPU region. +* \param rnr Region number to be configured. +* \param rbar Value for RBAR register. +* \param rsar Value for RSAR register. +*/ +__STATIC_INLINE void ARM_MPU_SetRegionEx(uint32_t rnr, uint32_t rbar, uint32_t rasr) +{ + MPU->RNR = rnr; + MPU->RBAR = rbar; + MPU->RASR = rasr; +} + +/** Memcopy with strictly ordered memory access, e.g. for register targets. +* \param dst Destination data is copied to. +* \param src Source data is copied from. +* \param len Amount of data words to be copied. +*/ +__STATIC_INLINE void ARM_MPU_OrderedMemcpy(volatile uint32_t* dst, const uint32_t* __RESTRICT src, uint32_t len) +{ + uint32_t i; + for (i = 0U; i < len; ++i) + { + dst[i] = src[i]; + } +} + +/** Load the given number of MPU regions from a table. +* \param table Pointer to the MPU configuration table. +* \param cnt Amount of regions to be configured. +*/ +__STATIC_INLINE void ARM_MPU_Load(ARM_MPU_Region_t const* table, uint32_t cnt) +{ + const uint32_t rowWordSize = sizeof(ARM_MPU_Region_t)/4U; + while (cnt > MPU_TYPE_RALIASES) { + ARM_MPU_OrderedMemcpy(&(MPU->RBAR), &(table->RBAR), MPU_TYPE_RALIASES*rowWordSize); + table += MPU_TYPE_RALIASES; + cnt -= MPU_TYPE_RALIASES; + } + ARM_MPU_OrderedMemcpy(&(MPU->RBAR), &(table->RBAR), cnt*rowWordSize); +} + +#endif diff --git a/bootloader/ld.script b/bootloader/ld.script new file mode 100644 index 0000000..5b5c265 --- /dev/null +++ b/bootloader/ld.script @@ -0,0 +1,302 @@ +/****************************************************************************** + * @file gcc_arm.ld + * @brief GNU Linker Script for Cortex-M based device + * @version V2.0.0 + * @date 21. May 2019 + ******************************************************************************/ +/* + * Copyright (c) 2009-2019 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* + *-------- <<< Use Configuration Wizard in Context Menu >>> ------------------- + */ + +/*---------------------- Flash Configuration ---------------------------------- + Flash Configuration + Flash Base Address <0x0-0xFFFFFFFF:8> + Flash Size (in Bytes) <0x0-0xFFFFFFFF:8> + + -----------------------------------------------------------------------------*/ +__ROM_BASE = 0x00000000; +__ROM_SIZE = 0x00010000; + +/*--------------------- Embedded RAM Configuration ---------------------------- + RAM Configuration + RAM Base Address <0x0-0xFFFFFFFF:8> + RAM Size (in Bytes) <0x0-0xFFFFFFFF:8> + + -----------------------------------------------------------------------------*/ +__RAM_BASE = 0x10000000; +__RAM_SIZE = 0x00008000; + +/*--------------------- Stack / Heap Configuration ---------------------------- + Stack / Heap Configuration + Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> + Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> + + -----------------------------------------------------------------------------*/ +__STACK_SIZE = 0x00000400; +__HEAP_SIZE = 0x00000C00; + +/* + *-------------------- <<< end of configuration section >>> ------------------- + */ + +MEMORY +{ + FLASH (rx) : ORIGIN = __ROM_BASE, LENGTH = __ROM_SIZE + RAM (rwx) : ORIGIN = __RAM_BASE, LENGTH = __RAM_SIZE +} + +/* Linker script to place sections and symbol values. Should be used together + * with other linker script that defines memory regions FLASH and RAM. + * It references following symbols, which must be defined in code: + * Reset_Handler : Entry of reset handler + * + * It defines following symbols, which code can use without definition: + * __exidx_start + * __exidx_end + * __copy_table_start__ + * __copy_table_end__ + * __zero_table_start__ + * __zero_table_end__ + * __etext + * __data_start__ + * __preinit_array_start + * __preinit_array_end + * __init_array_start + * __init_array_end + * __fini_array_start + * __fini_array_end + * __data_end__ + * __bss_start__ + * __bss_end__ + * __end__ + * end + * __HeapLimit + * __StackLimit + * __StackTop + * __stack + */ +ENTRY(Reset_Handler) + +EXTERN(NMI_Handler) +EXTERN(HardFault_Handler) +EXTERN(MemManage_Handler) +EXTERN(BusFault_Handler) +EXTERN(UsageFault_Handler) + +SECTIONS +{ + .text : + { + KEEP(*(.vectors)) + *(.text*) + + KEEP(*(.init)) + KEEP(*(.fini)) + + /* .ctors */ + *crtbegin.o(.ctors) + *crtbegin?.o(.ctors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors) + *(SORT(.ctors.*)) + *(.ctors) + + /* .dtors */ + *crtbegin.o(.dtors) + *crtbegin?.o(.dtors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors) + *(SORT(.dtors.*)) + *(.dtors) + + *(.rodata*) + + KEEP(*(.eh_frame*)) + } > FLASH + + /* + * SG veneers: + * All SG veneers are placed in the special output section .gnu.sgstubs. Its start address + * must be set, either with the command line option ‘--section-start’ or in a linker script, + * to indicate where to place these veneers in memory. + */ +/* + .gnu.sgstubs : + { + . = ALIGN(32); + } > FLASH +*/ + .ARM.extab : + { + *(.ARM.extab* .gnu.linkonce.armextab.*) + } > FLASH + + __exidx_start = .; + .ARM.exidx : + { + *(.ARM.exidx* .gnu.linkonce.armexidx.*) + } > FLASH + __exidx_end = .; + + .copy.table : + { + . = ALIGN(4); + __copy_table_start__ = .; + LONG (__etext) + LONG (__data_start__) + LONG (__data_end__ - __data_start__) + /* Add each additional data section here */ +/* + LONG (__etext2) + LONG (__data2_start__) + LONG (__data2_end__ - __data2_start__) +*/ + __copy_table_end__ = .; + } > FLASH + + .zero.table : + { + . = ALIGN(4); + __zero_table_start__ = .; + /* Add each additional bss section here */ +/* + LONG (__bss2_start__) + LONG (__bss2_end__ - __bss2_start__) +*/ + __zero_table_end__ = .; + } > FLASH + + /** + * Location counter can end up 2byte aligned with narrow Thumb code but + * __etext is assumed by startup code to be the LMA of a section in RAM + * which must be 4byte aligned + */ + __etext = ALIGN (4); + + .data : AT (__etext) + { + __data_start__ = .; + *(vtable) + *(.data) + *(.data.*) + + . = ALIGN(4); + /* preinit data */ + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP(*(.preinit_array)) + PROVIDE_HIDDEN (__preinit_array_end = .); + + . = ALIGN(4); + /* init data */ + PROVIDE_HIDDEN (__init_array_start = .); + KEEP(*(SORT(.init_array.*))) + KEEP(*(.init_array)) + PROVIDE_HIDDEN (__init_array_end = .); + + + . = ALIGN(4); + /* finit data */ + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP(*(SORT(.fini_array.*))) + KEEP(*(.fini_array)) + PROVIDE_HIDDEN (__fini_array_end = .); + + KEEP(*(.jcr*)) + . = ALIGN(4); + /* All data end */ + __data_end__ = .; + + } > RAM + + /* + * Secondary data section, optional + * + * Remember to add each additional data section + * to the .copy.table above to asure proper + * initialization during startup. + */ +/* + __etext2 = ALIGN (4); + + .data2 : AT (__etext2) + { + . = ALIGN(4); + __data2_start__ = .; + *(.data2) + *(.data2.*) + . = ALIGN(4); + __data2_end__ = .; + + } > RAM2 +*/ + + .bss : + { + . = ALIGN(4); + __bss_start__ = .; + *(.bss) + *(.bss.*) + *(COMMON) + . = ALIGN(4); + __bss_end__ = .; + } > RAM AT > RAM + + /* + * Secondary bss section, optional + * + * Remember to add each additional bss section + * to the .zero.table above to asure proper + * initialization during startup. + */ +/* + .bss2 : + { + . = ALIGN(4); + __bss2_start__ = .; + *(.bss2) + *(.bss2.*) + . = ALIGN(4); + __bss2_end__ = .; + } > RAM2 AT > RAM2 +*/ + + .heap (COPY) : + { + . = ALIGN(8); + __end__ = .; + PROVIDE(end = .); + . = . + __HEAP_SIZE; + . = ALIGN(8); + __HeapLimit = .; + } > RAM + + .stack (ORIGIN(RAM) + LENGTH(RAM) - __STACK_SIZE) (COPY) : + { + . = ALIGN(8); + __StackLimit = .; + . = . + __STACK_SIZE; + . = ALIGN(8); + __StackTop = .; + } > RAM + PROVIDE(__stack = __StackTop); + + /* Check if data + heap + stack exceeds RAM limit */ + ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack") + __VectorChecksum = 0 - (__StackTop + Reset_Handler + NMI_Handler + HardFault_Handler + MemManage_Handler + BusFault_Handler + UsageFault_Handler + 6 /* Add 6 to the sum to compensate for the lacking of the less significant bit (thumb mode) */); +} diff --git a/bootloader/src/lpc17_clock.c b/bootloader/src/lpc17_clock.c new file mode 100644 index 0000000..2566726 --- /dev/null +++ b/bootloader/src/lpc17_clock.c @@ -0,0 +1,344 @@ +/**************************************************************************** + * bootloader/src/lpc17_clock.c + * + * Copyright (C) 2020 Augusto Fraga Giachero. All rights reserved. + * Author: Augusto Fraga Giachero + * + * This file is part of the RFFE firmware. + * + * RFFE is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * RFFE is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with RFFE. If not, see . + * + ****************************************************************************/ + +#include "lpc17_clock.h" +#include "LPC176x5x.h" + +static inline void lpc17_pll0_feed() +{ + LPC_SYSCON->PLL0FEED = 0xAA; + LPC_SYSCON->PLL0FEED = 0x55; +} + +/* + * PLL0 output clock Fout = (2 * pll_mul * Fsrc) / pll_div + * CPU clock Fout / cpu_div + */ +int lpc17_set_pll0(uint16_t pll_div, uint16_t pll_mul, uint16_t cpu_div, enum lpc17_pll0_src src) +{ + if (pll_div < 1 || pll_div > 32) return -1; + if (pll_mul < 6 || pll_mul > 24170) return -1; + if (cpu_div < 1 || cpu_div > 256) return -1; + + cpu_div--; + pll_div--; + pll_mul--; + + /* + * Change CPU source to the Internal RC oscillator + */ + LPC_SYSCON->PLL0CON &= ~(SYSCON_PLL0CON_PLLC0_Msk); + lpc17_pll0_feed(); + + /* + * Disable PLL0 + */ + LPC_SYSCON->PLL0CON &= ~(SYSCON_PLL0CON_PLLE0_Msk); + lpc17_pll0_feed(); + + switch (src) + { + case pll0_irc_src: + LPC_SYSCON->CLKSRCSEL = 0; + break; + + case pll0_osc_src: + LPC_SYSCON->CLKSRCSEL = 1; + break; + + case pll0_rtc_src: + LPC_SYSCON->CLKSRCSEL = 2; + break; + + default: + break; + } + + /* + * Set the multiplier and divider values + */ + LPC_SYSCON->PLL0CFG = (pll_div << SYSCON_PLL0CFG_NSEL0_Pos) | + (pll_mul << SYSCON_PLL0CFG_MSEL0_Pos); + + /* + * Enable the PLL0 + */ + LPC_SYSCON->PLL0CON |= (SYSCON_PLL0CON_PLLE0_Msk); + lpc17_pll0_feed(); + + /* + * Set the CPU clock divider + */ + LPC_SYSCON->CCLKCFG = cpu_div; + + /* + * Wait for PLL0 to lock + */ + while (1) + { + volatile uint32_t stat = LPC_SYSCON->PLL0STAT; + volatile uint32_t start_tst = stat & SYSCON_PLL0STAT_PLOCK0_Msk; + if (start_tst) break; + } + + /* + * Change CPU clock source to PLL0 + */ + LPC_SYSCON->PLL0CON |= SYSCON_PLL0CON_PLLC0_Msk; + lpc17_pll0_feed(); + + return 0; +} + +void lpc17_set_pclk(enum lpc17_pclk pclk, enum lpc17_pclk_div div) +{ + uint32_t clk_div = 0; + uint32_t tmp = 0; + + switch (div) + { + case pclk_div1: + clk_div = 1; + break; + + case pclk_div2: + clk_div = 2; + break; + + case pclk_div4: + clk_div = 0; + break; + + case pclk_can_div6: + case pclk_div8: + clk_div = 3; + break; + + default: + break; + } + + switch (pclk) + { + /* PCLKSEL0 */ + case pclk_wdt: + tmp = LPC_SYSCON->PCLKSEL0; + tmp &= ~SYSCON_PCLKSEL0_PCLK_WDT_Msk; + tmp |= clk_div << SYSCON_PCLKSEL0_PCLK_WDT_Pos; + LPC_SYSCON->PCLKSEL0 = tmp; + break; + + case pclk_timer0: + tmp = LPC_SYSCON->PCLKSEL0; + tmp &= ~ SYSCON_PCLKSEL0_PCLK_TIMER0_Msk; + tmp |= clk_div << SYSCON_PCLKSEL0_PCLK_TIMER0_Pos; + LPC_SYSCON->PCLKSEL0 = tmp; + break; + + case pclk_timer1: + tmp = LPC_SYSCON->PCLKSEL0; + tmp &= ~SYSCON_PCLKSEL0_PCLK_TIMER1_Msk; + tmp |= clk_div << SYSCON_PCLKSEL0_PCLK_TIMER1_Pos; + LPC_SYSCON->PCLKSEL0 = tmp; + break; + + case pclk_uart0: + tmp = LPC_SYSCON->PCLKSEL0; + tmp &= ~SYSCON_PCLKSEL0_PCLK_UART0_Msk; + tmp |= clk_div << SYSCON_PCLKSEL0_PCLK_UART0_Pos; + LPC_SYSCON->PCLKSEL0 = tmp; + break; + + case pclk_uart1: + tmp = LPC_SYSCON->PCLKSEL0; + tmp &= ~SYSCON_PCLKSEL0_PCLK_UART1_Msk; + tmp |= clk_div << SYSCON_PCLKSEL0_PCLK_UART1_Pos; + LPC_SYSCON->PCLKSEL0 = tmp; + break; + + case pclk_pwm1: + tmp = LPC_SYSCON->PCLKSEL0; + tmp &= ~SYSCON_PCLKSEL0_PCLK_PWM1_Msk; + tmp |= clk_div << SYSCON_PCLKSEL0_PCLK_PWM1_Pos; + LPC_SYSCON->PCLKSEL0 = tmp; + break; + + case pclk_i2c0: + tmp = LPC_SYSCON->PCLKSEL0; + tmp &= ~SYSCON_PCLKSEL0_PCLK_I2C0_Msk; + tmp |= clk_div << SYSCON_PCLKSEL0_PCLK_I2C0_Pos; + LPC_SYSCON->PCLKSEL0 = tmp; + break; + + case pclk_spi: + tmp = LPC_SYSCON->PCLKSEL0; + tmp &= ~SYSCON_PCLKSEL0_PCLK_SPI_Msk; + tmp |= clk_div << SYSCON_PCLKSEL0_PCLK_SPI_Pos; + LPC_SYSCON->PCLKSEL0 = tmp; + break; + + case pclk_ssp1: + tmp = LPC_SYSCON->PCLKSEL0; + tmp &= ~SYSCON_PCLKSEL0_PCLK_SSP1_Msk; + tmp |= clk_div << SYSCON_PCLKSEL0_PCLK_SSP1_Pos; + LPC_SYSCON->PCLKSEL0 = tmp; + break; + + case pclk_dac: + tmp = LPC_SYSCON->PCLKSEL0; + tmp &= ~SYSCON_PCLKSEL0_PCLK_DAC_Msk; + tmp |= clk_div << SYSCON_PCLKSEL0_PCLK_DAC_Pos; + LPC_SYSCON->PCLKSEL0 = tmp; + break; + + case pclk_adc: + tmp = LPC_SYSCON->PCLKSEL0; + tmp &= ~SYSCON_PCLKSEL0_PCLK_ADC_Msk; + tmp |= clk_div << SYSCON_PCLKSEL0_PCLK_ADC_Pos; + LPC_SYSCON->PCLKSEL0 = tmp; + break; + + case pclk_can1: + tmp = LPC_SYSCON->PCLKSEL0; + tmp &= ~SYSCON_PCLKSEL0_PCLK_CAN1_Msk; + tmp |= clk_div << SYSCON_PCLKSEL0_PCLK_CAN1_Pos; + LPC_SYSCON->PCLKSEL0 = tmp; + break; + + case pclk_can2: + tmp = LPC_SYSCON->PCLKSEL0; + tmp &= ~SYSCON_PCLKSEL0_PCLK_CAN2_Msk; + tmp |= clk_div << SYSCON_PCLKSEL0_PCLK_CAN2_Pos; + LPC_SYSCON->PCLKSEL0 = tmp; + break; + + case pclk_acf: + tmp = LPC_SYSCON->PCLKSEL0; + tmp &= ~SYSCON_PCLKSEL0_PCLK_ACF_Msk; + tmp |= clk_div << SYSCON_PCLKSEL0_PCLK_ACF_Pos; + LPC_SYSCON->PCLKSEL0 = tmp; + break; + + /* PCLKSEL1 */ + case pclk_qei: + tmp = LPC_SYSCON->PCLKSEL1; + tmp &= ~SYSCON_PCLKSEL1_PCLK_QEI_Msk; + tmp |= clk_div << SYSCON_PCLKSEL1_PCLK_QEI_Pos; + LPC_SYSCON->PCLKSEL1 = tmp; + break; + + case pclk_gpioint: + tmp = LPC_SYSCON->PCLKSEL1; + tmp &= ~SYSCON_PCLKSEL1_PCLK_GPIOINT_Msk; + tmp |= clk_div << SYSCON_PCLKSEL1_PCLK_GPIOINT_Pos; + LPC_SYSCON->PCLKSEL1 = tmp; + break; + + case pclk_pcb: + tmp = LPC_SYSCON->PCLKSEL1; + tmp &= ~SYSCON_PCLKSEL1_PCLK_PCB_Msk; + tmp |= clk_div << SYSCON_PCLKSEL1_PCLK_PCB_Pos; + LPC_SYSCON->PCLKSEL1 = tmp; + break; + + case pclk_i2c1: + tmp = LPC_SYSCON->PCLKSEL1; + tmp &= ~SYSCON_PCLKSEL1_PCLK_I2C1_Msk; + tmp |= clk_div << SYSCON_PCLKSEL1_PCLK_I2C1_Pos; + LPC_SYSCON->PCLKSEL1 = tmp; + break; + + case pclk_ssp0: + tmp = LPC_SYSCON->PCLKSEL1; + tmp &= ~SYSCON_PCLKSEL1_PCLK_SSP0_Msk; + tmp |= clk_div << SYSCON_PCLKSEL1_PCLK_SSP0_Pos; + LPC_SYSCON->PCLKSEL1 = tmp; + break; + + case pclk_timer2: + tmp = LPC_SYSCON->PCLKSEL1; + tmp &= ~SYSCON_PCLKSEL1_PCLK_TIMER2_Msk; + tmp |= clk_div << SYSCON_PCLKSEL1_PCLK_TIMER2_Pos; + LPC_SYSCON->PCLKSEL1 = tmp; + break; + + case pclk_timer3: + tmp = LPC_SYSCON->PCLKSEL1; + tmp &= ~SYSCON_PCLKSEL1_PCLK_TIMER3_Msk; + tmp |= clk_div << SYSCON_PCLKSEL1_PCLK_TIMER3_Pos; + LPC_SYSCON->PCLKSEL1 = tmp; + break; + + case pclk_uart2: + tmp = LPC_SYSCON->PCLKSEL1; + tmp &= ~SYSCON_PCLKSEL1_PCLK_UART2_Msk; + tmp |= clk_div << SYSCON_PCLKSEL1_PCLK_UART2_Pos; + LPC_SYSCON->PCLKSEL1 = tmp; + break; + + case pclk_uart3: + tmp = LPC_SYSCON->PCLKSEL1; + tmp &= ~SYSCON_PCLKSEL1_PCLK_UART3_Msk; + tmp |= clk_div << SYSCON_PCLKSEL1_PCLK_UART3_Pos; + LPC_SYSCON->PCLKSEL1 = tmp; + break; + + case pclk_i2c2: + tmp = LPC_SYSCON->PCLKSEL1; + tmp &= ~SYSCON_PCLKSEL1_PCLK_I2C2_Msk; + tmp |= clk_div << SYSCON_PCLKSEL1_PCLK_I2C2_Pos; + LPC_SYSCON->PCLKSEL1 = tmp; + break; + + case pclk_i2s: + tmp = LPC_SYSCON->PCLKSEL1; + tmp &= ~SYSCON_PCLKSEL1_PCLK_I2S_Msk; + tmp |= clk_div << SYSCON_PCLKSEL1_PCLK_I2S_Pos; + LPC_SYSCON->PCLKSEL1 = tmp; + break; + + case pclk_rit: + tmp = LPC_SYSCON->PCLKSEL1; + tmp &= ~SYSCON_PCLKSEL1_PCLK_RIT_Msk; + tmp |= clk_div << SYSCON_PCLKSEL1_PCLK_RIT_Pos; + LPC_SYSCON->PCLKSEL1 = tmp; + break; + + case pclk_syscon: + tmp = LPC_SYSCON->PCLKSEL1; + tmp &= ~SYSCON_PCLKSEL1_PCLK_SYSCON_Msk; + tmp |= clk_div << SYSCON_PCLKSEL1_PCLK_SYSCON_Pos; + LPC_SYSCON->PCLKSEL1 = tmp; + break; + + case pclk_mc: + tmp = LPC_SYSCON->PCLKSEL1; + tmp &= ~SYSCON_PCLKSEL1_PCLK_MC_Msk; + tmp |= clk_div << SYSCON_PCLKSEL1_PCLK_MC_Pos; + LPC_SYSCON->PCLKSEL1 = tmp; + break; + + default: + break; + } +} diff --git a/bootloader/src/lpc17_clock.h b/bootloader/src/lpc17_clock.h new file mode 100644 index 0000000..ccf3800 --- /dev/null +++ b/bootloader/src/lpc17_clock.h @@ -0,0 +1,77 @@ +/**************************************************************************** + * bootloader/src/lpc17_clock.h + * + * Copyright (C) 2020 Augusto Fraga Giachero. All rights reserved. + * Author: Augusto Fraga Giachero + * + * This file is part of the RFFE firmware. + * + * RFFE is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * RFFE is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with RFFE. If not, see . + * + ****************************************************************************/ + +#include + +enum lpc17_pll0_src +{ + pll0_irc_src, + pll0_osc_src, + pll0_rtc_src, +}; + +enum lpc17_pclk +{ + /* PCLKSEL0 */ + pclk_wdt, + pclk_timer0, + pclk_timer1, + pclk_uart0, + pclk_uart1, + pclk_pwm1, + pclk_i2c0, + pclk_spi, + pclk_ssp1, + pclk_dac, + pclk_adc, + pclk_can1, + pclk_can2, + pclk_acf, + /* PCLKSEL1 */ + pclk_qei, + pclk_gpioint, + pclk_pcb, + pclk_i2c1, + pclk_ssp0, + pclk_timer2, + pclk_timer3, + pclk_uart2, + pclk_uart3, + pclk_i2c2, + pclk_i2s, + pclk_rit, + pclk_syscon, + pclk_mc, +}; + +enum lpc17_pclk_div +{ + pclk_div1, + pclk_div2, + pclk_div4, + pclk_can_div6, + pclk_div8, +}; + +int lpc17_set_pll0(uint16_t pll_div, uint16_t pll_mul, uint16_t cpu_div, enum lpc17_pll0_src src); +void lpc17_set_pclk(enum lpc17_pclk pclk, enum lpc17_pclk_div div); diff --git a/bootloader/src/lpc17_iap.c b/bootloader/src/lpc17_iap.c new file mode 100644 index 0000000..274e850 --- /dev/null +++ b/bootloader/src/lpc17_iap.c @@ -0,0 +1,99 @@ +/**************************************************************************** + * bootloader/src/lpc17_iap.c + * + * Copyright (C) 2020 Augusto Fraga Giachero. All rights reserved. + * Author: Augusto Fraga Giachero + * + * This file is part of the RFFE firmware. + * + * RFFE is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * RFFE is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with RFFE. If not, see . + * + ****************************************************************************/ + +#include "LPC176x5x.h" +#include "lpc17_iap.h" + +enum iap_cmds +{ + iap_prepare_sectors_write = 50, + iap_copy_ram_flash, + iap_erase_sectors, + iap_blank_check_sectors, + iap_read_part_id, + iap_read_boot_code_version, + iap_read_device_sn, + iap_compare, + iap_reinvoke, +}; + +static const void (*iap_entry) (uint32_t*, uint32_t*) = (void*) 0x1FFF1FF1; + +__attribute__ ((long_call, noinline, section (".data"))) +enum iap_err lpc17_iap_prepare_sectors(uint8_t start_sector, uint8_t end_sector) +{ + uint32_t inout[5] = { + (uint32_t)iap_prepare_sectors_write, + start_sector, + end_sector, + }; + + iap_entry(inout, inout); + + return (enum iap_err)inout[0]; +} + +__attribute__ ((long_call, noinline, section (".data"))) +enum iap_err lpc17_iap_copy_ram_flash(uint32_t* src_ram, uint32_t* dest_flash, size_t len, uint32_t cpu_clk_khz) +{ + uint32_t inout[5] = { + (uint32_t)iap_copy_ram_flash, + (uint32_t)dest_flash, + (uint32_t)src_ram, + (uint32_t)len, + cpu_clk_khz, + }; + + iap_entry(inout, inout); + + return (enum iap_err)inout[0]; +} + +__attribute__ ((long_call, noinline, section (".data"))) +enum iap_err lpc17_iap_erase_sectors(uint8_t start_sector, uint8_t end_sector, uint32_t cpu_clk_khz) +{ + uint32_t inout[5] = { + (uint32_t)iap_erase_sectors, + start_sector, + end_sector, + cpu_clk_khz, + }; + + iap_entry(inout, inout); + + return (enum iap_err)inout[0]; +} + +__attribute__ ((long_call, noinline, section (".data#"))) +enum iap_err lpc17_iap_blank_check(uint8_t start_sector, uint8_t end_sector) +{ + uint32_t inout[5] = { + (uint32_t)iap_blank_check_sectors, + start_sector, + end_sector, + }; + + iap_entry(inout, inout); + + return (enum iap_err)inout[0]; +} diff --git a/bootloader/src/lpc17_iap.h b/bootloader/src/lpc17_iap.h new file mode 100644 index 0000000..0799387 --- /dev/null +++ b/bootloader/src/lpc17_iap.h @@ -0,0 +1,54 @@ +/**************************************************************************** + * bootloader/src/lpc17_iap.h + * + * Copyright (C) 2020 Augusto Fraga Giachero. All rights reserved. + * Author: Augusto Fraga Giachero + * + * This file is part of the RFFE firmware. + * + * RFFE is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * RFFE is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with RFFE. If not, see . + * + ****************************************************************************/ + +#include +#include + +enum iap_err +{ + iap_cmd_success = 0, + iap_invalid_command, + iap_src_addr_error, + iap_dst_addr_error, + iap_src_addr_not_mapped, + iap_dst_addr_not_mapped, + iap_count_error, + iap_invalid_sector, + iap_sector_not_blank, + iap_sector_not_prepared_for_write, + iap_compare_error, + iap_busy, + iap_param_error, + iap_addr_error, + iap_addr_not_mapped, + iap_cmd_locked, + iap_invalid_code, + iap_invalid_baud_rate, + iap_invalid_stop_bit, + iap_code_read_protection_enabled, +}; + +enum iap_err lpc17_iap_prepare_sectors(uint8_t start_sector, uint8_t end_sector); +enum iap_err lpc17_iap_copy_ram_flash(uint32_t* src_ram, uint32_t* dest_flash, size_t len, uint32_t cpu_clk_khz); +enum iap_err lpc17_iap_erase_sectors(uint8_t start_sector, uint8_t end_sector, uint32_t cpu_clk_khz); +enum iap_err lpc17_iap_blank_check(uint8_t start_sector, uint8_t end_sector); diff --git a/bootloader/src/lpc17_pincfg.c b/bootloader/src/lpc17_pincfg.c new file mode 100644 index 0000000..34ba887 --- /dev/null +++ b/bootloader/src/lpc17_pincfg.c @@ -0,0 +1,106 @@ +/**************************************************************************** + * bootloader/src/lpc17_pincfg.c + * + * Copyright (C) 2020 Augusto Fraga Giachero. All rights reserved. + * Author: Augusto Fraga Giachero + * + * This file is part of the RFFE firmware. + * + * RFFE is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * RFFE is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with RFFE. If not, see . + * + ****************************************************************************/ + +#include + +#include "LPC176x5x.h" +#include "lpc17_pincfg.h" + +void lp17_pincfg(uint8_t port, uint8_t pin, enum pincfg_mode mode, enum pincfg_func func) +{ + volatile uint32_t* pinsel = NULL; + volatile uint32_t* pinmode = NULL; + uint8_t bit_pos = (pin * 2) % 32; + uint32_t sel_mask = (uint32_t)3 << bit_pos; + uint32_t mode_mask = (uint32_t)3 << bit_pos; + uint32_t sel_val = (uint32_t)func << bit_pos; + uint32_t mode_val = (uint32_t)mode << bit_pos; + + if (port == 0) + { + if (pin <= 15) + { + pinsel = &LPC_PINCONNECT->PINSEL0; + pinmode = &LPC_PINCONNECT->PINMODE0; + } + else + { + pinsel = &LPC_PINCONNECT->PINSEL1; + pinmode = &LPC_PINCONNECT->PINMODE1; + } + } + else if (port == 1) + { + if (pin <= 15) + { + pinsel = &LPC_PINCONNECT->PINSEL2; + pinmode = &LPC_PINCONNECT->PINMODE2; + } + else + { + pinsel = &LPC_PINCONNECT->PINSEL3; + pinmode = &LPC_PINCONNECT->PINMODE3; + } + } + else if (port == 2) + { + /* + * PINSEL5 / PINMODE5 not available + */ + if (pin <= 15) + { + pinsel = &LPC_PINCONNECT->PINSEL4; + pinmode = &LPC_PINCONNECT->PINMODE4; + } + } + else if (port == 3) + { + /* + * PINSEL6 / PINMODE6 not available + */ + if (pin >= 16) + { + pinsel = &LPC_PINCONNECT->PINSEL7; + pinmode = &LPC_PINCONNECT->PINMODE7; + } + } + else if (port == 4) + { + /* + * PINSEL8 / PINMODE8 not available + */ + if (pin >= 16) + { + pinsel = &LPC_PINCONNECT->PINSEL9; + pinmode = &LPC_PINCONNECT->PINMODE9; + } + } + + if (pinsel && pinmode) + { + *pinsel &= ~sel_mask; + *pinsel |= sel_val; + *pinmode &= ~mode_mask; + *pinmode |= mode_val; + } +} diff --git a/bootloader/src/lpc17_pincfg.h b/bootloader/src/lpc17_pincfg.h new file mode 100644 index 0000000..fb94802 --- /dev/null +++ b/bootloader/src/lpc17_pincfg.h @@ -0,0 +1,42 @@ +/**************************************************************************** + * bootloader/src/lpc17_pincfg.h + * + * Copyright (C) 2020 Augusto Fraga Giachero. All rights reserved. + * Author: Augusto Fraga Giachero + * + * This file is part of the RFFE firmware. + * + * RFFE is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * RFFE is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with RFFE. If not, see . + * + ****************************************************************************/ + +#include + +enum pincfg_mode +{ + pin_mode_pullup = 0, + pin_mode_repeater = 1, + pin_mode_none = 2, + pin_mode_pulldown = 3, +}; + +enum pincfg_func +{ + pin_func_gpio = 0, + pin_func_alt1 = 1, + pin_func_alt2 = 2, + pin_func_alt3 = 3, +}; + +void lp17_pincfg(uint8_t port, uint8_t pin, enum pincfg_mode mode, enum pincfg_func func); diff --git a/bootloader/src/lpc17_progmem.c b/bootloader/src/lpc17_progmem.c new file mode 100644 index 0000000..512ada6 --- /dev/null +++ b/bootloader/src/lpc17_progmem.c @@ -0,0 +1,27 @@ +/**************************************************************************** + * bootloader/src/lpc17_progmem.c + * + * Copyright (C) 2020 Augusto Fraga Giachero. All rights reserved. + * Author: Augusto Fraga Giachero + * + * This file is part of the RFFE firmware. + * + * RFFE is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * RFFE is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with RFFE. If not, see . + * + ****************************************************************************/ + +#include + +#include "LPC176x5x.h" + diff --git a/bootloader/src/lpc17_uart.c b/bootloader/src/lpc17_uart.c new file mode 100644 index 0000000..6a58215 --- /dev/null +++ b/bootloader/src/lpc17_uart.c @@ -0,0 +1,94 @@ +/**************************************************************************** + * bootloader/src/lpc17_uart.c + * + * Copyright (C) 2020 Augusto Fraga Giachero. All rights reserved. + * Author: Augusto Fraga Giachero + * + * This file is part of the RFFE firmware. + * + * RFFE is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * RFFE is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with RFFE. If not, see . + * + ****************************************************************************/ + +#include "lpc17_clock.h" +#include "lpc17_uart.h" +#include "LPC176x5x.h" + +int lpc17_uart0_init(uint32_t baud, uint32_t cpu_clk) +{ + /* + * Set UART0 clock as the same of CPU + */ + lpc17_set_pclk(pclk_uart0, pclk_div1); + + /* + * Enable the UART0 peripheral + */ + LPC_SYSCON->PCONP |= SYSCON_PCONP_PCUART0_Msk; + + /* + * Disable fractional baudrate generation + */ + LPC_UART0->FDR = (0 << UART0_FDR_DIVADDVAL_Pos) | + (1 << UART0_FDR_MULVAL_Pos); + + /* + * Calculate the baudrate from cpu_clk; + */ + volatile uint32_t uart_div = cpu_clk / (16 * baud); + + if (uart_div < 1 || uart_div > 0xFFFF) return -1; + + /* + * Enable divisor latch access, write the divisor value + */ + LPC_UART0->LCR |= UART0_LCR_DLAB_Msk; + LPC_UART0->DLM = (uart_div >> 8) & 0xFF; + LPC_UART0->DLL = uart_div & 0xFF; + LPC_UART0->LCR &= ~UART0_LCR_DLAB_Msk; + + /* + * Configure UART0: 8N1 + */ + LPC_UART0->LCR = (3 << UART0_LCR_WLS_Pos); + + /* + * Enable the UART0 transmitter + */ + LPC_UART0->TER = UART0_TER_TXEN_Msk; + + return 0; +} + +int lpc17_uart0_write_blocking(const uint8_t* buffer, size_t len) +{ + for (; len > 0; len--) + { + while ((LPC_UART0->LSR & UART0_LSR_THRE_Msk) == 0); + LPC_UART0->THR = *buffer++; + } + return len; +} + +int lpc17_uart0_write_str_blocking(const char* buffer) +{ + int len = 0; + while (*buffer) + { + while ((LPC_UART0->LSR & UART0_LSR_THRE_Msk) == 0); + LPC_UART0->THR = *buffer++; + len++; + } + return len; +} diff --git a/bootloader/src/lpc17_uart.h b/bootloader/src/lpc17_uart.h new file mode 100644 index 0000000..0205c19 --- /dev/null +++ b/bootloader/src/lpc17_uart.h @@ -0,0 +1,29 @@ +/**************************************************************************** + * bootloader/src/lpc17_uart.c + * + * Copyright (C) 2020 Augusto Fraga Giachero. All rights reserved. + * Author: Augusto Fraga Giachero + * + * This file is part of the RFFE firmware. + * + * RFFE is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * RFFE is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with RFFE. If not, see . + * + ****************************************************************************/ + +#include +#include + +int lpc17_uart0_init(uint32_t baud, uint32_t cpu_clk); +int lpc17_uart0_write_blocking(const uint8_t* buffer, size_t len); +int lpc17_uart0_write_str_blocking(const char* buffer); diff --git a/bootloader/src/main.c b/bootloader/src/main.c new file mode 100644 index 0000000..4eb2754 --- /dev/null +++ b/bootloader/src/main.c @@ -0,0 +1,186 @@ +/**************************************************************************** + * bootloader/src/main.c + * + * Copyright (C) 2020 Augusto Fraga Giachero. All rights reserved. + * Author: Augusto Fraga Giachero + * + * This file is part of the RFFE firmware. + * + * RFFE is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * RFFE is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with RFFE. If not, see . + * + ****************************************************************************/ + +#include +#include + +#include "LPC176x5x.h" +#include "lpc17_clock.h" +#include "lpc17_pincfg.h" +#include "lpc17_uart.h" +#include "lpc17_iap.h" +#include "start_app.h" + +uint32_t* const flash_end_addr = (uint32_t*)0x80000; +uint32_t* const app_start_addr = (uint32_t*)0x10000; +uint32_t* const boot_start_addr = (uint32_t*)0x0000; +uint32_t* const update_start_addr = (uint32_t*)0x48000; +const uint32_t app_size = (uint32_t)update_start_addr - (uint32_t)app_start_addr; +const uint32_t boot_size = (uint32_t)app_start_addr; +const uint8_t boot_start_sec = 0; +const uint8_t boot_end_sec = 15; +const uint8_t app_start_sec = 16; +const uint8_t update_start_sec = 23; +const uint8_t magic_word_sec = 29; + +typedef struct +{ + uint8_t version[3]; + uint8_t fw_type; + uint32_t magic; +} fw_info; + +const fw_info* fw_header = (fw_info*)((uint32_t)flash_end_addr - sizeof(fw_info)); + +__attribute__ ((long_call, noinline, section (".data"))) +uint8_t get_sector_number(uint32_t flash) +{ + uint8_t ret = 0; + if (flash < 0x10000) + { + ret = (flash / 0x1000); + } + else + { + ret = ((flash - 0x10000) / 0x8000) + 16; + } + return ret; +} + +__attribute__ ((long_call, noinline, section (".data"))) +void copy_flash_region(uint32_t* src, uint32_t* dest, size_t len, uint32_t cpu_clk_khz) +{ + uint32_t buffer[64]; + + if (len % 256) return; + + for (size_t i = 0; i < len; i += 256, src += 64, dest += 64) + { + for (size_t i = 0; i < 64; i++) + { + buffer[i] = src[i]; + } + + uint8_t sector = get_sector_number((uint32_t)dest); + + lpc17_iap_prepare_sectors(sector, sector); + lpc17_iap_copy_ram_flash(buffer, dest, 256, cpu_clk_khz); + } +} + +__attribute__ ((long_call, noinline, section (".data"))) +void update_app(uint32_t cpu_clk_khz) +{ + lpc17_iap_prepare_sectors(app_start_sec, update_start_sec - 1); + lpc17_iap_erase_sectors(app_start_sec, update_start_sec - 1, cpu_clk_khz); + + copy_flash_region(update_start_addr, app_start_addr, app_size, cpu_clk_khz); + + lpc17_iap_prepare_sectors(magic_word_sec, magic_word_sec); + lpc17_iap_erase_sectors(magic_word_sec, magic_word_sec, cpu_clk_khz); + + /* + * Jump to application code + */ + start_app((uint32_t*)0x10000); +} + +__attribute__ ((long_call, noinline, section (".data"))) +void update_bootloader(uint32_t cpu_clk_khz) +{ + lpc17_iap_prepare_sectors(boot_start_sec, boot_end_sec); + lpc17_iap_erase_sectors(boot_start_sec, boot_end_sec, cpu_clk_khz); + + copy_flash_region(update_start_addr, boot_start_addr, boot_size, cpu_clk_khz); + + lpc17_iap_prepare_sectors(magic_word_sec, magic_word_sec); + lpc17_iap_erase_sectors(magic_word_sec, magic_word_sec, cpu_clk_khz); + + /* + * Jump to application code + */ + start_app((uint32_t*)0x10000); +} + +int main(void) +{ + /* + * Update flash access time to 4 CPU clocks (required when running + * from 60 to 80MHz) + */ + LPC_SYSCON->FLASHCFG &= ~SYSCON_FLASHCFG_FLASHTIM_Msk; + LPC_SYSCON->FLASHCFG |= (3 << SYSCON_FLASHCFG_FLASHTIM_Pos); + + /* + * PLL0 output clock Fout = (2 * pll_mul * Fsrc) / pll_div + * CPU clock Fout / cpu_div + * + * For a 72 MHz cpu clock using the internal RC: + * pll_div = 1; + * pll_mull = 18; + * cpu_div = 2; + */ + lpc17_set_pll0(1, 18, 2, pll0_irc_src); + + /* + * Configure pins P0.2 as TXD0 and P0.3 as RXD0 + */ + lp17_pincfg(0, 2, pin_mode_none, pin_func_alt1); + lp17_pincfg(0, 3, pin_mode_none, pin_func_alt1); + + /* + * Initialize UAR0 (115200bps, 8N1) + */ + lpc17_uart0_init(115200, 72000000); + + if (fw_header->magic == 0xAAAAAAAA) + { + char tmp[128]; + lpc17_uart0_write_str_blocking("[BOOTLOADER] DO NOT TURN OFF WHILE UPDATING!\r\n"); + + if (fw_header->fw_type == 1) + { + snprintf(tmp, 128, "[BOOTLOADER] New app firmware update found!\r\nUpdating to %d.%d.%d ...\r\n", + fw_header->version[0], fw_header->version[1], fw_header->version[2]); + lpc17_uart0_write_str_blocking(tmp); + update_app(72000); + } + else if (fw_header->fw_type == 2) + { + lpc17_uart0_write_str_blocking("[BOOTLOADER] New bootloader firmware update found!\r\n"); + lpc17_uart0_write_str_blocking("[BOOTLOADER] Updating...\r\n"); + update_bootloader(72000); + } + else + { + snprintf(tmp, 128, "[BOOTLOADER] ERROR: Unknown fw_type %d !\r\n Jumping to application code...\r\n", + fw_header->fw_type); + lpc17_uart0_write_str_blocking(tmp); + } + } + + /* + * Jump to application code + */ + start_app((uint32_t*)0x10000); +} diff --git a/bootloader/src/start_app.c b/bootloader/src/start_app.c new file mode 100644 index 0000000..1d2fd24 --- /dev/null +++ b/bootloader/src/start_app.c @@ -0,0 +1,40 @@ +/**************************************************************************** + * bootloader/src/start_app.c + * + * Copyright (C) 2020 Augusto Fraga Giachero. All rights reserved. + * Author: Augusto Fraga Giachero + * + * This file is part of the RFFE firmware. + * + * RFFE is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * RFFE is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with RFFE. If not, see . + * + ****************************************************************************/ + +#include "LPC176x5x.h" + +__attribute__ ((long_call, noinline, section (".data"))) +void start_app(uint32_t* vtor) +{ + __disable_irq(); + SCB->VTOR = (uint32_t)vtor; + uint32_t sp = vtor[0]; + uint32_t pc = vtor[1]; + __asm__ volatile ( + "mov sp, %0 \n" + "bx %1 \n" + : + : "r"(sp), "r"(pc) + : + ); +} diff --git a/bootloader/src/start_app.h b/bootloader/src/start_app.h new file mode 100644 index 0000000..60ebbbd --- /dev/null +++ b/bootloader/src/start_app.h @@ -0,0 +1,26 @@ +/**************************************************************************** + * bootloader/src/start_app.h + * + * Copyright (C) 2020 Augusto Fraga Giachero. All rights reserved. + * Author: Augusto Fraga Giachero + * + * This file is part of the RFFE firmware. + * + * RFFE is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * RFFE is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with RFFE. If not, see . + * + ****************************************************************************/ + +#include + +void start_app(uint32_t* vtor); diff --git a/bootloader/src/startup.s b/bootloader/src/startup.s new file mode 100644 index 0000000..756abe2 --- /dev/null +++ b/bootloader/src/startup.s @@ -0,0 +1,229 @@ +/**************************************************************************//** + * @file startup.s + * @brief CMSIS-Core(M) Device Startup File for Cortex-M3 Device + * @version V2.0.1 + * @date 23. July 2019 + ******************************************************************************/ +/* + * Copyright (c) 2009-2019 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + + .syntax unified + .arch armv7-m + + .section .vectors + .align 2 + .globl __Vectors + .globl __Vectors_End + .globl __Vectors_Size +__Vectors: + .long __StackTop /* Top of Stack */ + .long Reset_Handler /* Reset Handler */ + .long NMI_Handler /* -14 NMI Handler */ + .long HardFault_Handler /* -13 Hard Fault Handler */ + .long MemManage_Handler /* -12 MPU Fault Handler */ + .long BusFault_Handler /* -11 Bus Fault Handler */ + .long UsageFault_Handler /* -10 Usage Fault Handler */ + .long __VectorChecksum /* Checksum (required by the ROM bootloader) */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long SVC_Handler /* -5 SVCall Handler */ + .long DebugMon_Handler /* -4 Debug Monitor Handler */ + .long 0 /* Reserved */ + .long PendSV_Handler /* -2 PendSV Handler */ + .long SysTick_Handler /* -1 SysTick Handler */ + + /* Interrupts */ + .long WDT_Handler + .long TIMER0_Handler + .long TIMER1_Handler + .long TIMER2_Handler + .long TIMER3_Handler + .long UART0_Handler + .long UART1_Handler + .long UART2_Handler + .long UART3_Handler + .long PWM1_Handler + .long I2C0_Handler + .long I2C1_Handler + .long I2C2_Handler + .long SPI_Handler + .long SSP0_Handler + .long SSP1_Handler + .long PLL0_Handler + .long RTC_Handler + .long EINT0_Handler + .long EINT1_Handler + .long EINT2_Handler + .long EINT3_Handler + .long ADC_Handler + .long BOD_Handler + .long USB_Handler + .long CAN_Handler + .long DMA_Handler + .long I2S_Handler + .long ENET_Handler + .long RIT_Handler + .long MCPWM_Handler + .long QEI_Handler + .long PLL1_Handler + .long USBActivity_Handler + .long CANActivity_Handler + +// .space (189 * 4) /* Interrupts 35 .. 224 are left out */ +__Vectors_End: + .equ __Vectors_Size, __Vectors_End - __Vectors + .size __Vectors, . - __Vectors + + + .thumb + .section .text + .align 2 + + .thumb_func + .type Reset_Handler, %function + .globl Reset_Handler + .fnstart +Reset_Handler: + ldr r4, =__copy_table_start__ + ldr r5, =__copy_table_end__ + +.L_loop0: + cmp r4, r5 + bge .L_loop0_done + ldr r1, [r4] + ldr r2, [r4, #4] + ldr r3, [r4, #8] + +.L_loop0_0: + subs r3, #4 + ittt ge + ldrge r0, [r1, r3] + strge r0, [r2, r3] + bge .L_loop0_0 + + adds r4, #12 + b .L_loop0 +.L_loop0_done: + + ldr r3, =__zero_table_start__ + ldr r4, =__zero_table_end__ + +.L_loop2: + cmp r3, r4 + bge .L_loop2_done + ldr r1, [r3] + ldr r2, [r3, #4] + movs r0, 0 + +.L_loop2_0: + subs r2, #4 + itt ge + strge r0, [r1, r2] + bge .L_loop2_0 + + adds r3, #8 + b .L_loop2 +.L_loop2_done: + + bl _start + + .fnend + .size Reset_Handler, . - Reset_Handler + +/* The default macro is not used for HardFault_Handler + * because this results in a poor debug illusion. + */ + .thumb_func + .type HardFault_Handler, %function + .weak HardFault_Handler + .fnstart +HardFault_Handler: + b . + .fnend + .size HardFault_Handler, . - HardFault_Handler + + .thumb_func + .type Default_Handler, %function + .weak Default_Handler + .fnstart +Default_Handler: + b . + .fnend + .size Default_Handler, . - Default_Handler + +/* Macro to define default exception/interrupt handlers. + * Default handler are weak symbols with an endless loop. + * They can be overwritten by real handlers. + */ + .macro Set_Default_Handler Handler_Name + .weak \Handler_Name + .set \Handler_Name, Default_Handler + .endm + + +/* Default exception/interrupt handler */ + + Set_Default_Handler NMI_Handler + Set_Default_Handler MemManage_Handler + Set_Default_Handler BusFault_Handler + Set_Default_Handler UsageFault_Handler + Set_Default_Handler SVC_Handler + Set_Default_Handler DebugMon_Handler + Set_Default_Handler PendSV_Handler + Set_Default_Handler SysTick_Handler + + Set_Default_Handler WDT_Handler + Set_Default_Handler TIMER0_Handler + Set_Default_Handler TIMER1_Handler + Set_Default_Handler TIMER2_Handler + Set_Default_Handler TIMER3_Handler + Set_Default_Handler UART0_Handler + Set_Default_Handler UART1_Handler + Set_Default_Handler UART2_Handler + Set_Default_Handler UART3_Handler + Set_Default_Handler PWM1_Handler + Set_Default_Handler I2C0_Handler + Set_Default_Handler I2C1_Handler + Set_Default_Handler I2C2_Handler + Set_Default_Handler SPI_Handler + Set_Default_Handler SSP0_Handler + Set_Default_Handler SSP1_Handler + Set_Default_Handler PLL0_Handler + Set_Default_Handler RTC_Handler + Set_Default_Handler EINT0_Handler + Set_Default_Handler EINT1_Handler + Set_Default_Handler EINT2_Handler + Set_Default_Handler EINT3_Handler + Set_Default_Handler ADC_Handler + Set_Default_Handler BOD_Handler + Set_Default_Handler USB_Handler + Set_Default_Handler CAN_Handler + Set_Default_Handler DMA_Handler + Set_Default_Handler I2S_Handler + Set_Default_Handler ENET_Handler + Set_Default_Handler RIT_Handler + Set_Default_Handler MCPWM_Handler + Set_Default_Handler QEI_Handler + Set_Default_Handler PLL1_Handler + Set_Default_Handler USBActivity_Handler + Set_Default_Handler CANActivity_Handler + + + + .end From 8ad3966d0b0f2b166f5818ab61627e76fd9ce92c Mon Sep 17 00:00:00 2001 From: Augusto Fraga Giachero Date: Fri, 14 Feb 2020 16:05:34 -0300 Subject: [PATCH 5/8] Remove legacy code No longer necessary, we don't need the legacy bootloader anymore. Good bye mbed-os. --- .gitmodules | 3 - legacy/.gitignore | 25 - legacy/.mbed | 4 - legacy/README.md | 91 --- legacy/app/Drivers/ADT7320.cpp | 76 --- legacy/app/Drivers/ADT7320.h | 33 -- legacy/app/Drivers/CDCE906.cpp | 68 --- legacy/app/Drivers/CDCE906.h | 22 - legacy/app/Drivers/DAC7554.cpp | 33 -- legacy/app/Drivers/DAC7554.h | 25 - legacy/app/Drivers/Drivers.h | 10 - legacy/app/Drivers/LM71.cpp | 87 --- legacy/app/Drivers/LM71.h | 42 -- legacy/app/Drivers/feram.cpp | 182 ------ legacy/app/Drivers/feram.h | 44 -- legacy/app/IAP.cpp | 256 --------- legacy/app/IAP.h | 498 ----------------- legacy/app/PID/PID.cpp | 200 ------- legacy/app/PID/PID.h | 77 --- legacy/app/attenuators.cpp | 54 -- legacy/app/attenuators.h | 16 - legacy/app/bsmp/bsmp.c | 40 -- legacy/app/bsmp/bsmp.h | 232 -------- legacy/app/bsmp/bsmp_priv.h | 77 --- legacy/app/bsmp/md5/md5.c | 275 --------- legacy/app/bsmp/md5/md5.h | 35 -- legacy/app/bsmp/server.c | 228 -------- legacy/app/bsmp/server.h | 191 ------- legacy/app/bsmp/server_priv.c | 737 ------------------------ legacy/app/bsmp/server_priv.h | 84 --- legacy/app/cli.cpp | 171 ------ legacy/app/cli.h | 194 ------- legacy/app/ethernet.cpp | 276 --------- legacy/app/ethernet.h | 36 -- legacy/app/main.cpp | 860 ----------------------------- legacy/app/mbed_app.json | 32 -- legacy/app/pcbnAPI.cpp | 260 --------- legacy/app/pcbnAPI.h | 84 --- legacy/app/util.cpp | 117 ---- legacy/app/util.h | 12 - legacy/app/watchdog.h | 32 -- legacy/bootloader/.mbed | 1 - legacy/bootloader/boot.h | 20 - legacy/bootloader/bootloader.cpp | 89 --- legacy/bootloader/mbed_app.json | 7 - legacy/bootloader/mbed_settings.py | 45 -- legacy/compile.sh | 5 - legacy/mbed-os | 1 - legacy/mbed_app.json | 20 - legacy/mbed_settings.py | 45 -- 50 files changed, 6052 deletions(-) delete mode 100644 legacy/.gitignore delete mode 100644 legacy/.mbed delete mode 100644 legacy/README.md delete mode 100644 legacy/app/Drivers/ADT7320.cpp delete mode 100644 legacy/app/Drivers/ADT7320.h delete mode 100644 legacy/app/Drivers/CDCE906.cpp delete mode 100644 legacy/app/Drivers/CDCE906.h delete mode 100644 legacy/app/Drivers/DAC7554.cpp delete mode 100644 legacy/app/Drivers/DAC7554.h delete mode 100644 legacy/app/Drivers/Drivers.h delete mode 100644 legacy/app/Drivers/LM71.cpp delete mode 100644 legacy/app/Drivers/LM71.h delete mode 100644 legacy/app/Drivers/feram.cpp delete mode 100644 legacy/app/Drivers/feram.h delete mode 100644 legacy/app/IAP.cpp delete mode 100644 legacy/app/IAP.h delete mode 100644 legacy/app/PID/PID.cpp delete mode 100644 legacy/app/PID/PID.h delete mode 100644 legacy/app/attenuators.cpp delete mode 100644 legacy/app/attenuators.h delete mode 100644 legacy/app/bsmp/bsmp.c delete mode 100644 legacy/app/bsmp/bsmp.h delete mode 100644 legacy/app/bsmp/bsmp_priv.h delete mode 100644 legacy/app/bsmp/md5/md5.c delete mode 100644 legacy/app/bsmp/md5/md5.h delete mode 100644 legacy/app/bsmp/server.c delete mode 100644 legacy/app/bsmp/server.h delete mode 100644 legacy/app/bsmp/server_priv.c delete mode 100644 legacy/app/bsmp/server_priv.h delete mode 100644 legacy/app/cli.cpp delete mode 100644 legacy/app/cli.h delete mode 100644 legacy/app/ethernet.cpp delete mode 100644 legacy/app/ethernet.h delete mode 100644 legacy/app/main.cpp delete mode 100644 legacy/app/mbed_app.json delete mode 100644 legacy/app/pcbnAPI.cpp delete mode 100644 legacy/app/pcbnAPI.h delete mode 100644 legacy/app/util.cpp delete mode 100644 legacy/app/util.h delete mode 100644 legacy/app/watchdog.h delete mode 100644 legacy/bootloader/.mbed delete mode 100644 legacy/bootloader/boot.h delete mode 100644 legacy/bootloader/bootloader.cpp delete mode 100644 legacy/bootloader/mbed_app.json delete mode 100644 legacy/bootloader/mbed_settings.py delete mode 100755 legacy/compile.sh delete mode 160000 legacy/mbed-os delete mode 100644 legacy/mbed_app.json delete mode 100644 legacy/mbed_settings.py diff --git a/.gitmodules b/.gitmodules index 641c048..19f2761 100644 --- a/.gitmodules +++ b/.gitmodules @@ -1,6 +1,3 @@ -[submodule "mbed-os"] - path = legacy/mbed-os - url = git://github.com/ARMmbed/mbed-os [submodule "nuttx"] path = nuttx url = https://github.com/lnls-dig/nuttx.git diff --git a/legacy/.gitignore b/legacy/.gitignore deleted file mode 100644 index 018cb3a..0000000 --- a/legacy/.gitignore +++ /dev/null @@ -1,25 +0,0 @@ -BUILD/ -*~ -*.swp -*.orig -*.bak -*.o -*.d -*.pyc -*.a -*.so -*.lib -*.htm -*.hg -*.hg/* -.hgignore -*CMakeFiles* -*CMakeCache.txt -*cmake_install.cmake -*.axf -*.bin -*.map -BUILD/* -.cproject -.project -*.launch \ No newline at end of file diff --git a/legacy/.mbed b/legacy/.mbed deleted file mode 100644 index 3b7a468..0000000 --- a/legacy/.mbed +++ /dev/null @@ -1,4 +0,0 @@ -ROOT=. -MBED_OS_DIR=mbed-os/ -TARGET=LPC1768 -TOOLCHAIN=GCC_ARM diff --git a/legacy/README.md b/legacy/README.md deleted file mode 100644 index 65a7286..0000000 --- a/legacy/README.md +++ /dev/null @@ -1,91 +0,0 @@ -# RFFE Controller Firmware - -Firmware for the RFFE Control Boards, based on MBED, using a Cortex M3 LPC1768 processor. - -## Pre-requisites - -The following packages must be installed on your system in order to compile the firmware: -- **gcc-arm-none-eabi** - -**gcc-arm-none-eabi** can be installed from the pre-compiled files found at: https://launchpad.net/gcc-arm-embedded/+download -or you can run the following command under Ubuntu: - - sudo apt-get install gcc-arm-none-eabi - -Next step is to clone this repository into your workspace. Since we're using the mbed libraries as a submodule, you **MUST** run the git clone command with the `--recursive` option. - - git clone --recursive https://github.com/lnls-dig/rffe-fw - -If you've already cloned the repository without the recursive option, go to the source folder and run: - - cd mbed-os - git submodule update --init --recursive - -## Compilation - -Go to the repository folder - - cd /path/to/repo/ - -Run `make` (you can add the `-j4` flag to speed up the proccess) : - - make -j4 - -A few flags can be set in order to match your hardware setup, which are: - - ETH_INTERFACE= - TEMP_SENSOR= - -If not set, the Makefile will output a warning and use a default value for each. - -Example using fixed IP addressing and ADT7320 temperature sensor: - - make -j4 ETH_INTERFACE=FIX_IP IP=10.2.119.203 GATEWAY=10.2.119.1 TEMP_SENSOR=ADT7320 - -*NOTE: The compiler will print a few warnings, most of them are regarding the mbed libraries, but since they have a stable version on github, we'll just ignore those warnings.* - -Both a `.elf` file and a `.bin` file will be generated in the source folder. You can use any one you prefer to program your processor. - -To clean the compilation files (binaries, objects and dependence files), just run - - make clean - -## Programming - -To program the firmware in the MBED board, just plug in a USB cable in its frontal jack in your computer and a `MBED` drive will be mounted (the MBED will get its power from the USB +5v). - -Copy the generated binary file before into the MBED storage and reset the board (Power Cycle or Reset button). - -**IMPORTANT:** You **MUST NOT** rename the generated binary file, otherwise the firmware will delete its own file upon start. The MBED bootloader will run only the newest binary file found in its drive, therefore, you can have multiple revisions of the firmware stored for backup purposes, but they'll be renamed from `*.bin` to `*.old` automatically on boot. - -## Logging - -A useful procedure if to log the serial messages from the RFFE via serial cable for debugging purposes. In order to do that, one can use the following logrotate configration file, so to keep long-running logs in a machine: - -``` -cat <<-EOF > /etc/logrotate.d/rffe-debug - /var/log/rffe-debug/*.log { - hourly - rotate 20 - size 100K - maxsize 1M - compress - missingok - notifempty - postrotate - /bin/kill -HUP `cat /run/rffe-debug.pid 2>/dev/null` 2> /dev/null || true - (sudo screen -c /var/log/rffe-debug/screenrc -L /dev/ttyACM0 115200) & PID=$(echo $!) && sudo bash -c "touch /run/rffe-debug.pid && echo ${PID} > /run/rffe-debug.pid" - endscript - } -EOF -``` - -Just copy the above commands into a terminal and set logrotate to run at a resonable time, like 1 minute so as to not keep logs too larger than the limit. - -Remember to change the TTY port to the correct one when using this. Most of the time it will by ttyACM0, but it's not guaranteed. - -As a last reminder. The procedure will be more useful if the RFFE is set to use debug flags. Fow now, just define the symbol DEBUG_PRINTF at the beggining of main.cpp file: - -```c -#define DEBUG_PRINTF -``` diff --git a/legacy/app/Drivers/ADT7320.cpp b/legacy/app/Drivers/ADT7320.cpp deleted file mode 100644 index df2586f..0000000 --- a/legacy/app/Drivers/ADT7320.cpp +++ /dev/null @@ -1,76 +0,0 @@ -#include "ADT7320.h" - -double ADT7320::Read() -{ - uint16_t data; - int reference = 0; - double delta = 128; - double temp; - - _cs = 1; - _spi.frequency( _freq ); - _spi.format(16,3); - - _cs = 0; - ThisThread::sleep_for(1); - // Select Temperature value register - _spi.write(0x0050); - data = _spi.write(0x0000); - _cs = 1; - - temp = (float(data)-reference)/delta; - - /* Check if the current read is within range, if not, return the last valid data */ - if ( (temp >= minTemp) && (temp <= maxTemp) ) { - lastTemp = temp; - } else { - temp = lastTemp; - } - - return temp; -} - -void ADT7320::Config( int freq, int res, int cfg ) -{ - int cfg_byte = 0; - - _freq = freq; - - _spi.frequency( _freq ); - _cs = 1; - - /* Reseting SPI interface - Write 32 1's to the IC */ - _spi.format(16,3); - _cs = 0; - ThisThread::sleep_for(1); - _spi.write(0xFFFF); - _spi.write(0xFFFF); - ThisThread::sleep_for(1); - _cs = 1; - - // Configuration process - _spi.format(8,3); - _cs = 0; - ThisThread::sleep_for(1); - - // Select CONFIGURATION REGISTER – 0x01 - _spi.write(0x08); - - // Write data to configuration register ( 16-bits resolution + continuous conversion ) - cfg_byte = (res == ADT7320_CFG_16_BITS)? (1 << 7) : 0; - - // Additional configuration bits - cfg_byte |= cfg; - - _spi.write( cfg_byte ); - - ThisThread::sleep_for(1); - _cs = 1; - ThisThread::sleep_for(1); -} - -void ADT7320::SetRange( double min, double max ) -{ - minTemp = min; - maxTemp = max; -} diff --git a/legacy/app/Drivers/ADT7320.h b/legacy/app/Drivers/ADT7320.h deleted file mode 100644 index d587526..0000000 --- a/legacy/app/Drivers/ADT7320.h +++ /dev/null @@ -1,33 +0,0 @@ -#ifndef ADT7320_H_ -#define ADT7320_H_ - -#include "mbed.h" -#include "rtos.h" - -#define ADT7320_CFG_13_BITS 0 -#define ADT7320_CFG_16_BITS 1 - -class ADT7320 -{ -public: - - ADT7320( mbed::SPI& spi, mbed::DigitalOut& cs, int spi_freq, int resolution, int config, double min, double max ) - : _spi(spi), _cs(cs), _freq(spi_freq) { - ADT7320::Config( _freq, resolution, config ); - ADT7320::SetRange( min, max ); - } - - double Read( void ); - void Config( int freq, int res, int cfg ); - void SetRange( double min, double max ); - -private: - SPI& _spi; - DigitalOut& _cs; - - int _freq; - - double lastTemp; - double minTemp, maxTemp; -}; -#endif diff --git a/legacy/app/Drivers/CDCE906.cpp b/legacy/app/Drivers/CDCE906.cpp deleted file mode 100644 index 7b8fda5..0000000 --- a/legacy/app/Drivers/CDCE906.cpp +++ /dev/null @@ -1,68 +0,0 @@ -#include "CDCE906.h" - -int CDCE906::cfg_eth( void ) -{ - char cfg[26] = {0}; - int err = 0; - - cfg[0] = 0x1; - cfg[1] = 9; /* PLL 1 M */ - cfg[2] = 25; /* PLL 1 N */ - cfg[3] = 0x0; - cfg[4] = 9; /* PLL 2 M */ - cfg[5] = 25; /* PLL 2 N */ - cfg[6] = 0xE0; - cfg[7] = 9; /* PLL 3 M */ - cfg[8] = 25; /* PLL 3 N */ - cfg[9] = (3<<5); - cfg[10] = 0x0; - cfg[11] = 0x0; - cfg[12] = 0x0; - cfg[13] = 0x2; /* P0 div */ - cfg[14] = 0x1; /* P1 div */ - cfg[15] = 0x1; /* P2 div */ - cfg[16] = 0x1; /* P3 div */ - cfg[17] = 0x1; /* P4 div */ - cfg[18] = 0x1; /* P5 div */ - cfg[19] = 0x38; /* Y0 */ - cfg[20] = 0; /* Y1 */ - cfg[21] = 0; /* Y2 */ - cfg[22] = 0; /* Y3 */ - cfg[23] = 0; /* Y4 */ - cfg[24] = 0; /* Y5 */ - cfg[25] = (3<<4)|0xB; - - err = _write(0, cfg, sizeof(cfg)); - - return err; -} - -int CDCE906::_write(uint8_t addr, char *buffer, size_t len) -{ - int err; - char *data = (char *) malloc(len+2); - - data[0] = addr; - data[1] = len; - memcpy(&data[2], buffer, len); - err = _i2c.write(_sladdr, &data[0], len+2); - - free(data); - - return err; -} - -int CDCE906::_read(uint8_t addr, char *buffer, size_t len) -{ - int err; - char data[1]; - - data[0] = addr; - err = _i2c.write(_sladdr, data, 1, true); - - if (err == 0) { - err = _i2c.read(_sladdr, buffer, len); - } - - return err; -} diff --git a/legacy/app/Drivers/CDCE906.h b/legacy/app/Drivers/CDCE906.h deleted file mode 100644 index ad596b5..0000000 --- a/legacy/app/Drivers/CDCE906.h +++ /dev/null @@ -1,22 +0,0 @@ -#ifndef CDCE906_H_ -#define CDCE906_H_ - -#include "mbed.h" -#include "rtos.h" - -class CDCE906 -{ -public: - - CDCE906( mbed::I2C& i2c, uint8_t addr ) - : _i2c(i2c), _sladdr(addr) { - } - - int cfg_eth(); -private: - int _read(uint8_t addr, char *buffer, size_t len); - int _write(uint8_t addr, char *buffer, size_t len); - I2C& _i2c; - int _sladdr; -}; -#endif diff --git a/legacy/app/Drivers/DAC7554.cpp b/legacy/app/Drivers/DAC7554.cpp deleted file mode 100644 index 56b017a..0000000 --- a/legacy/app/Drivers/DAC7554.cpp +++ /dev/null @@ -1,33 +0,0 @@ -#include "DAC7554.h" - -void DAC7554::Write( double vout ) -{ - // Control bits Data bits DAC Function - // 1 0 0 0 (0x8000) 12 bits A Input register and DAC register updated, output updated - // 1 0 0 1 (0x9000) 12 bits B Input register and DAC register updated, output updated - // 1 0 1 0 (0xA000) 12 bits C Input register and DAC register updated, output updated - // 1 0 1 1 (0xB000) 12 bits D Input register and DAC register updated, output updated - // vout = refin * data / 4095 - // data = vout * 4095 / refin - - uint16_t data; - uint16_t cfg; - - // SPI config - _spi.frequency(1000000); - _spi.format(16,2); - _cs = 1; - - // Calculating data to vout - data = (uint16_t)(vout*4095/refin); - cfg = ( channel << 12 ) | ( data & 0x0FFF ); - - // Transmition - _cs = 0; - ThisThread::sleep_for(1); - // control - write data to voutA - _spi.write( cfg ); - ThisThread::sleep_for(1); - _cs = 1; - ThisThread::sleep_for(1); -} diff --git a/legacy/app/Drivers/DAC7554.h b/legacy/app/Drivers/DAC7554.h deleted file mode 100644 index 97c9ef1..0000000 --- a/legacy/app/Drivers/DAC7554.h +++ /dev/null @@ -1,25 +0,0 @@ -#ifndef DAC7554_H_ -#define DAC7554_H_ - -#include "mbed.h" -#include "rtos.h" - -#define DAC_AC_SEL 0xB -#define DAC_BD_SEL 0xA - -class DAC7554 -{ -public: - -DAC7554( mbed::SPI& spi, mbed::DigitalOut& cs, uint8_t dac_channel, float dac_refin ) - : _spi(spi), _cs(cs), channel(dac_channel), refin(dac_refin) {} - - void Write( double vout ); - -private: - SPI& _spi; - DigitalOut& _cs; - uint8_t channel; - float refin; -}; -#endif diff --git a/legacy/app/Drivers/Drivers.h b/legacy/app/Drivers/Drivers.h deleted file mode 100644 index 7d62c1f..0000000 --- a/legacy/app/Drivers/Drivers.h +++ /dev/null @@ -1,10 +0,0 @@ -#ifndef DRIVERS_H_ -#define DRIVERS_H_ - -#include "ADT7320.h" -#include "DAC7554.h" -#include "LM71.h" -#include "CDCE906.h" -#include "feram.h" - -#endif diff --git a/legacy/app/Drivers/LM71.cpp b/legacy/app/Drivers/LM71.cpp deleted file mode 100644 index 9a1d802..0000000 --- a/legacy/app/Drivers/LM71.cpp +++ /dev/null @@ -1,87 +0,0 @@ -#include "LM71.h" - -double LM71::Read() -{ - int16_t data = 0; - double temp = 0; - - if (_mode != LM71_MODE_CONVERSION) { - LM71::Config(_freq, LM71_MODE_CONVERSION); - } - - _spi.format(16,0); - - _cs = 0; - ThisThread::sleep_for(1); - // Select Temperature value register - data = _spi.write(0x0000); - _cs = 1; - - temp = (data >> 2) * LM71_LSB_VALUE; - - /* Check if the current read is within range, if not, return the last valid data */ - if ( (temp >= minTemp) && (temp <= maxTemp) ) { - lastTemp = temp; - } else { - _err++; - //temp = lastTemp; - } - - return temp; -} - -int LM71::Config( int freq, lm71_mode_t mode ) -{ - if (freq > 6250000) { - return -1; - } - - _freq = freq; - _mode = mode; - _spi.frequency( _freq ); - _cs = 1; - - _spi.format(16,0); - - if (_mode == LM71_MODE_CONVERSION) { - _cs = 0; - ThisThread::sleep_for(1); - _spi.write(0x0000); - _spi.write(0x0000); - _cs = 1; - } else if (_mode == LM71_MODE_SHUTDOWN) { - _cs = 0; - ThisThread::sleep_for(1); - _spi.write(0xFFFF); - _spi.write(0xFFFF); - _cs = 1; - } else { - return -2; - } - - return 0; -} - -uint16_t LM71::ReadID( void ) -{ - LM71::Config( _freq, LM71_MODE_SHUTDOWN); - _mode = LM71_MODE_SHUTDOWN; - - _cs = 0; - ThisThread::sleep_for(1); - uint16_t id = _spi.write(0xFFFF); - _cs = 1; - - return (id >> 2); -} - -uint32_t LM71::err_count( void ) -{ - return _err; -} - -void LM71::SetRange( double min, double max ) -{ - minTemp = min; - maxTemp = max; -} diff --git a/legacy/app/Drivers/LM71.h b/legacy/app/Drivers/LM71.h deleted file mode 100644 index 5849996..0000000 --- a/legacy/app/Drivers/LM71.h +++ /dev/null @@ -1,42 +0,0 @@ -#ifndef LM71_H_ -#define LM71_H_ - -#include "mbed.h" -#include "rtos.h" - -#define LM71_LSB_VALUE 0.03125 - -typedef enum { - LM71_MODE_CONVERSION, - LM71_MODE_SHUTDOWN -} lm71_mode_t; - -class LM71 -{ -public: - - LM71( mbed::SPI& spi, mbed::DigitalOut& cs, int spi_freq, lm71_mode_t mode, double min, double max ) - : _spi(spi), _cs(cs), _freq(spi_freq), _mode(mode) { - LM71::Config( _freq, _mode ); - LM71::SetRange( min, max ); - } - - double Read( void ); - int Config( int freq, lm71_mode_t mode ); - void SetRange( double min, double max ); - uint16_t ReadID( void ); - - uint32_t err_count( void ); -private: - SPI& _spi; - DigitalOut& _cs; - - int _freq; - lm71_mode_t _mode; - - uint32_t _err; - - double lastTemp; - double minTemp, maxTemp; -}; -#endif diff --git a/legacy/app/Drivers/feram.cpp b/legacy/app/Drivers/feram.cpp deleted file mode 100644 index c910cd4..0000000 --- a/legacy/app/Drivers/feram.cpp +++ /dev/null @@ -1,182 +0,0 @@ -#include "feram.h" - -int FeRAM::write(uint16_t addr, uint8_t *buffer, size_t len) -{ - int err; - char *data = (char *) malloc(len+1); - - uint8_t page_sladdr = ((_sladdr & 0xF0) | ( ( (addr >> 8) & 0x7) << 1)); - data[0] = (addr & 0xFF); - memcpy(&data[1], buffer, len); - - _wp = 0; - /* Upper 3 bits from addr are the bits [3:1] from the slave address */ - err = _i2c.write(page_sladdr, (char *) &data[0], len+1); - _wp = 1; - - free(data); - - return err; -} - -int FeRAM::read(uint16_t addr, uint8_t *buffer, size_t len) -{ - int err; - char data[1]; - - uint8_t page_sladdr = ((_sladdr & 0xF0) | ( ( (addr >> 8) & 0x7) << 1)); - data[0] = (addr & 0xFF); - - err = _i2c.write(page_sladdr, data, 1, true); - - if (err == 0) { - err = _i2c.read(page_sladdr, (char *) buffer, len); - } - - return err; -} - -int FeRAM::get_eth_addressing(uint8_t *type) -{ - return FeRAM::read(FERAM_ETH_ADDR_OFFSET, type, sizeof(uint8_t)); -} - -int FeRAM::set_eth_addressing(uint8_t type) -{ - return FeRAM::write(FERAM_ETH_ADDR_OFFSET, &type, sizeof(uint8_t)); -} - -int FeRAM::get_mac_addr(char *mac_str, char* mac_buf) -{ - int err; - uint8_t mac[6] = {0}; - - err = FeRAM::read(FERAM_MAC_ADDR_OFFSET, mac, sizeof(mac)); - - snprintf(mac_str, 18, "%02x:%02x:%02x:%02x:%02x:%02x", mac[0], mac[1], mac[2], mac[3], mac[4], mac[5]); - - if (mac_buf) { - memcpy(mac_buf, mac, 6); - } - return err; -} - -int FeRAM::set_mac_addr(char *mac_str) -{ - int err; - uint8_t mac[6] = {0}; - - sscanf(mac_str, "%02hhx:%02hhx:%02hhx:%02hhx:%02hhx:%02hhx", &mac[0], &mac[1], &mac[2], &mac[3], &mac[4], &mac[5]); - - err = FeRAM::write(FERAM_MAC_ADDR_OFFSET, mac, sizeof(mac)); - - return err; -} - -int FeRAM::get_ip_addr(char *ip_str) -{ - int err; - uint8_t ip[4] = {0}; - - err = FeRAM::read(FERAM_IP_ADDR_OFFSET, ip, sizeof(ip)); - - snprintf(ip_str, 16, "%hhu.%hhu.%hhu.%hhu", ip[0], ip[1], ip[2], ip[3]); - - return err; -} - -int FeRAM::set_ip_addr(char *ip_str) -{ - int err; - uint8_t ip[4] = {0}; - - sscanf(ip_str, "%hhu.%hhu.%hhu.%hhu", &ip[0], &ip[1], &ip[2], &ip[3]); - - err = FeRAM::write(FERAM_IP_ADDR_OFFSET, ip, sizeof(ip)); - - return err; -} - -int FeRAM::get_mask_addr(char *mask_str) -{ - int err; - uint8_t mask[4] = {0}; - - err = FeRAM::read(FERAM_MASK_ADDR_OFFSET, mask, sizeof(mask)); - - snprintf(mask_str, 16, "%hhu.%hhu.%hhu.%hhu", mask[0], mask[1], mask[2], mask[3]); - - return err; -} - -int FeRAM::set_mask_addr(char *mask_str) -{ - int err; - uint8_t mask[4] = {0}; - - sscanf(mask_str,"%hhu.%hhu.%hhu.%hhu", &mask[0], &mask[1], &mask[2], &mask[3]); - - err = FeRAM::write(FERAM_MASK_ADDR_OFFSET, mask, sizeof(mask)); - - return err; -} - -int FeRAM::get_gateway_addr(char *gateway_str) -{ - int err; - uint8_t gateway[4] = {0}; - - err = FeRAM::read(FERAM_GATEWAY_ADDR_OFFSET, gateway, sizeof(gateway)); - - snprintf(gateway_str, 16, "%hhu.%hhu.%hhu.%hhu", gateway[0], gateway[1], gateway[2], gateway[3]); - - return err; -} - -int FeRAM::set_gateway_addr(char *gateway_str) -{ - int err; - uint8_t gateway[4] = {0}; - - sscanf(gateway_str, "%hhu.%hhu.%hhu.%hhu", &gateway[0], &gateway[1], &gateway[2], &gateway[3]); - - err = FeRAM::write(FERAM_GATEWAY_ADDR_OFFSET, gateway, sizeof(gateway)); - - return err; -} - -int FeRAM::get_attenuation(double *att) -{ - int err; - uint8_t att_buf[4]; - int att_int; - - err = FeRAM::read(FERAM_ATTENUATION_OFFSET, att_buf, sizeof(att_buf)); - - att_int = (att_buf[0] << 24) | (att_buf[1] << 16) | (att_buf[2] << 8) | att_buf[3]; - - if (att) { - *att = (double) (att_int/2); - } else { - err = -1; - } - - return err; -} - -int FeRAM::set_attenuation(double att) -{ - int err; - uint8_t att_buf[4]; - - int att_int = (int) (att*2); - - att_buf[0] = (att_int >> 24) & 0xFF; - att_buf[1] = (att_int >> 16) & 0xFF; - att_buf[2] = (att_int >> 8) & 0xFF; - att_buf[3] = att_int & 0xFF; - - err = FeRAM::write(FERAM_ATTENUATION_OFFSET, att_buf, sizeof(att_buf)); - - return err; -} diff --git a/legacy/app/Drivers/feram.h b/legacy/app/Drivers/feram.h deleted file mode 100644 index 40cc022..0000000 --- a/legacy/app/Drivers/feram.h +++ /dev/null @@ -1,44 +0,0 @@ -#ifndef FERAM_H_ -#define FERAM_H_ - -#include "mbed.h" -#include "rtos.h" -#include "bsmp.h" - -#define FERAM_MAC_ADDR_OFFSET 0 -#define FERAM_IP_ADDR_OFFSET 0x10 -#define FERAM_MASK_ADDR_OFFSET 0x20 -#define FERAM_GATEWAY_ADDR_OFFSET 0x30 -#define FERAM_ATTENUATION_OFFSET 0x40 -#define FERAM_ETH_ADDR_OFFSET 0x50 -class FeRAM -{ -public: - - FeRAM( mbed::I2C& i2c, mbed::DigitalOut& wp, uint8_t sladdr = 0xA0 ) - : _i2c(i2c), _wp(wp), _sladdr(sladdr) { - } - - int read(uint16_t addr, uint8_t *buffer, size_t len); /* 11bit address */ - int write(uint16_t addr, uint8_t *buffer, size_t len); - - int get_mac_addr(char *mac_str, char *mac_buf); - int set_mac_addr(char *mac_str); - int get_ip_addr(char *ip_str); - int set_ip_addr(char *ip_str); - int get_mask_addr(char *mask_str); - int set_mask_addr(char *mask_str); - int get_gateway_addr(char *gateway_str); - int set_gateway_addr(char *gateway_str); - int get_attenuation(double *att); - int set_attenuation(double att); - int get_eth_addressing(uint8_t *type); - int set_eth_addressing(uint8_t type); - -private: - I2C& _i2c; - mbed::DigitalOut& _wp; - int _sladdr; - -}; -#endif diff --git a/legacy/app/IAP.cpp b/legacy/app/IAP.cpp deleted file mode 100644 index 78ae103..0000000 --- a/legacy/app/IAP.cpp +++ /dev/null @@ -1,256 +0,0 @@ -/** IAP : internal Flash memory access library - * - * The internal Flash memory access is described in the LPC1768 and LPC11U24 usermanual. - * http://www.nxp.com/documents/user_manual/UM10360.pdf - * http://www.nxp.com/documents/user_manual/UM10462.pdf - * - * LPC1768 -- - * Chapter 2: "LPC17xx Memory map" - * Chapter 32: "LPC17xx Flash memory interface and programming" - * refering Rev. 01 - 4 January 2010 - * - * LPC11U24 -- - * Chapter 2: "LPC11Uxx Memory mapping" - * Chapter 20: "LPC11Uxx Flash programming firmware" - * refering Rev. 03 - 16 July 2012 - * - * Released under the MIT License: http://mbed.org/license/mit - * - * revision 1.0 09-Mar-2010 1st release - * revision 1.1 12-Mar-2010 chaged: to make possible to reserve flash area for user - * it can be set by USER_FLASH_AREA_START and USER_FLASH_AREA_SIZE in IAP.h - * revision 2.0 26-Nov-2012 LPC11U24 code added - * revision 2.1 26-Nov-2012 EEPROM access code imported from Suga koubou san's (http://mbed.org/users/okini3939/) library - * http://mbed.org/users/okini3939/code/M0_EEPROM_test/ - * revision 3.0 09-Jan-2015 LPC812 and LPC824 support added - * revision 3.1 13-Jan-2015 LPC1114 support added - * revision 3.1.1 16-Jan-2015 Target MCU name changed for better compatibility across the platforms - */ - -#include "mbed.h" -#include "IAP.h" - -/* - * Reserve of flash area is explained by Igor. Please refer next URL - * http://mbed.org/users/okano/notebook/iap-in-application-programming-internal-flash-eras/?page=1#comment-271 - */ - -//unsigned char user_area[ size ] __attribute__((section(".ARM.__at_0x78000"), zero_init)); - -/* - * IAP command codes - * Table 589. "IAP Command Summary", Chapter 8. "IAP commands", usermanual - */ - -enum command_code { - IAPCommand_Prepare_sector_for_write_operation = 50, - IAPCommand_Copy_RAM_to_Flash, - IAPCommand_Erase_sector, - IAPCommand_Blank_check_sector, - IAPCommand_Read_part_ID, - IAPCommand_Read_Boot_Code_version, - IAPCommand_Compare, - IAPCommand_Reinvoke_ISP, - IAPCommand_Read_device_serial_number, -#if defined(TARGET_LPC11UXX) - IAPCommand_EEPROM_Write = 61, - IAPCommand_EEPROM_Read, -#elif defined(TARGET_LPC81X) || defined(TARGET_LPC82X) - IAPCommand_Erase_page = 59, -#endif -}; - -int IAP::reinvoke_isp( void ) { - __disable_irq(); - - IAP_command[ 0 ] = IAPCommand_Reinvoke_ISP; - - iap_entry( IAP_command, IAP_result ); - - return ( (int)IAP_result[ 0 ] ); -} - -/** Read part identification number - * - * @return device ID - * @see read_serial() - */ -int IAP::read_ID( void ) -{ - IAP_command[ 0 ] = IAPCommand_Read_part_ID; - - iap_entry( IAP_command, IAP_result ); - - return ( (int)IAP_result[ 1 ] ); // to return the number itself (this command always returns CMD_SUCCESS) -} - -int *IAP::read_serial( void ) { - IAP_command[ 0 ] = IAPCommand_Read_device_serial_number; - - iap_entry( IAP_command, IAP_result ); - - return ( (int *)&IAP_result[ 1 ] ); // to return the number itself (this command always returns CMD_SUCCESS) -} - -int IAP::blank_check( int start, int end ) -{ - IAP_command[ 0 ] = IAPCommand_Blank_check_sector; - IAP_command[ 1 ] = (unsigned int)start; // Start Sector Number - IAP_command[ 2 ] = (unsigned int)end; // End Sector Number (should be greater than or equal to start sector number) - - iap_entry( IAP_command, IAP_result ); - - return ( (int)IAP_result[ 0 ] ); -} - -int IAP::erase( uint32_t sector ) -{ - int err = prepare(sector, sector); - - if (err != IAP_CMD_SUCCESS) { - return err; - } - - IAP_command[ 0 ] = IAPCommand_Erase_sector; - IAP_command[ 1 ] = (unsigned int)sector; // Start Sector Number - IAP_command[ 2 ] = (unsigned int)sector; // End Sector Number (should be greater than or equal to start sector number) - IAP_command[ 3 ] = cclk_kHz; // CPU Clock Frequency (CCLK) in kHz - - iap_entry( IAP_command, IAP_result ); - - return ( (int)IAP_result[ 0 ] ); -} - -int IAP::prepare( int start, int end ) -{ - IAP_command[ 0 ] = IAPCommand_Prepare_sector_for_write_operation; - IAP_command[ 1 ] = (unsigned int)start; // Start Sector Number - IAP_command[ 2 ] = (unsigned int)end; // End Sector Number (should be greater than or equal to start sector number). - - iap_entry( IAP_command, IAP_result ); - - return ( (int)IAP_result[ 0 ] ); -} - -int IAP::write( uint32_t *source_addr, uint32_t target_addr, int size ) -{ - uint32_t sector_start = find_sector(target_addr); - uint32_t sector_end = find_sector(target_addr+size-1); - - if (size % 256) { - /* Data should be a 256 byte boundary */ - return IAP_COUNT_ERROR; - } - - int err = prepare(sector_start, sector_end); - - if (err != IAP_CMD_SUCCESS) { - return err; - } - - IAP_command[ 0 ] = IAPCommand_Copy_RAM_to_Flash; - IAP_command[ 1 ] = (unsigned int)target_addr; // Destination flash address where data bytes are to be written. This address should be a 256 byte boundary. - IAP_command[ 2 ] = (unsigned int)source_addr; // Source RAM address from which data bytes are to be read. This address should be a word boundary. - IAP_command[ 3 ] = size; // Number of bytes to be written. Should be 256 | 512 | 1024 | 4096. - IAP_command[ 4 ] = cclk_kHz; // CPU Clock Frequency (CCLK) in kHz. - - iap_entry( IAP_command, IAP_result ); - - return ( (int)IAP_result[ 0 ] ); -} - -int IAP::compare( uint32_t *source_addr, uint32_t *target_addr, int size ) -{ - IAP_command[ 0 ] = IAPCommand_Compare; - IAP_command[ 1 ] = (unsigned int)target_addr; // Starting flash or RAM address of data bytes to be compared. This address should be a word boundary. - IAP_command[ 2 ] = (unsigned int)source_addr; // Starting flash or RAM address of data bytes to be compared. This address should be a word boundary. - IAP_command[ 3 ] = size; // Number of bytes to be compared; should be a multiple of 4. - - iap_entry( IAP_command, IAP_result ); - - return ( (int)IAP_result[ 0 ] ); -} - -int IAP::read_BootVer(void) -{ - IAP_command[0] = IAPCommand_Read_Boot_Code_version; - IAP_result[1] = 0; // not sure if in high or low bits. - iap_entry(IAP_command, IAP_result); - return ((int)IAP_result[1]); -} - -int IAP::find_sector( uint32_t addr ) -{ - unsigned long n; - - n = addr >> 12; // 4kB Sector - if (n >= 0x10) { - n = 0x0E + (n >> 3); // 32kB Sector - } - - return (n); // Sector Number -} - -int IAP::get_sector_size( uint32_t addr ) -{ - if(find_sector(addr)>=0x10) { - return 0x8000; - } else { - return 0x1000; - } -} - -int IAP::get_flash_size( void ) -{ -#if defined(TARGET_LPC176X) - return 0x80000; -#else - return 0; -#endif -} - - -#if defined(TARGET_LPC11UXX) - -int IAP::write_eeprom( uint32_t *source_addr, uint32_t *target_addr, int size ) -{ - IAP_command[ 0 ] = IAPCommand_EEPROM_Write; - IAP_command[ 1 ] = (unsigned int)target_addr; // Destination EEPROM address where data bytes are to be written. This address should be a 256 byte boundary. - IAP_command[ 2 ] = (unsigned int)source_addr; // Source RAM address from which data bytes are to be read. This address should be a word boundary. - IAP_command[ 3 ] = size; // Number of bytes to be written. Should be 256 | 512 | 1024 | 4096. - IAP_command[ 4 ] = cclk_kHz; // CPU Clock Frequency (CCLK) in kHz. - - iap_entry( IAP_command, IAP_result ); - - return ( (int)IAP_result[ 0 ] ); -} - -int IAP::read_eeprom( uint32_t *source_addr, uint32_t *target_addr, int size ) -{ - IAP_command[ 0 ] = IAPCommand_EEPROM_Read; - IAP_command[ 1 ] = (unsigned int)source_addr; // Source EEPROM address from which data bytes are to be read. This address should be a word boundary. - IAP_command[ 2 ] = (unsigned int)target_addr; // Destination RAM address where data bytes are to be written. This address should be a 256 byte boundary. - IAP_command[ 3 ] = size; // Number of bytes to be written. Should be 256 | 512 | 1024 | 4096. - IAP_command[ 4 ] = cclk_kHz; // CPU Clock Frequency (CCLK) in kHz. - - iap_entry( IAP_command, IAP_result ); - - return ( (int)IAP_result[ 0 ] ); -} - -#elif defined(TARGET_LPC81X) || defined(TARGET_LPC82X) - -int IAP::erase_page( int start, int end ) -{ - IAP_command[ 0 ] = IAPCommand_Erase_page; - IAP_command[ 1 ] = (unsigned int)start; // Start Sector Number - IAP_command[ 2 ] = (unsigned int)end; // End Sector Number (should be greater than or equal to start sector number) - IAP_command[ 3 ] = cclk_kHz; // CPU Clock Frequency (CCLK) in kHz - - iap_entry( IAP_command, IAP_result ); - - return ( (int)IAP_result[ 0 ] ); -} - -#endif - diff --git a/legacy/app/IAP.h b/legacy/app/IAP.h deleted file mode 100644 index e0fa739..0000000 --- a/legacy/app/IAP.h +++ /dev/null @@ -1,498 +0,0 @@ -/** IAP : internal Flash memory access library - * - * The internal Flash memory access is described in the LPC1768 and LPC11U24 usermanual. - * http://www.nxp.com/documents/user_manual/UM10360.pdf - * http://www.nxp.com/documents/user_manual/UM10462.pdf - * - * LPC1768 -- - * Chapter 2: "LPC17xx Memory map" - * Chapter 32: "LPC17xx Flash memory interface and programming" - * refering Rev. 01 - 4 January 2010 - * - * LPC11U24 -- - * Chapter 2: "LPC11Uxx Memory mapping" - * Chapter 20: "LPC11Uxx Flash programming firmware" - * refering Rev. 03 - 16 July 2012 - * - * Released under the MIT License: http://mbed.org/license/mit - * - * revision 1.0 09-Mar-2010 1st release - * revision 1.1 12-Mar-2010 chaged: to make possible to reserve flash area for user - * it can be set by USER_FLASH_AREA_START and USER_FLASH_AREA_SIZE in IAP.h - * revision 2.0 26-Nov-2012 LPC11U24 code added - * revision 2.1 26-Nov-2012 EEPROM access code imported from Suga koubou san's (http://mbed.org/users/okini3939/) library - * http://mbed.org/users/okini3939/code/M0_EEPROM_test/ - * revision 3.0 09-Jan-2015 LPC812 and LPC824 support added - * revision 3.1 13-Jan-2015 LPC1114 support added - * revision 3.1.1 16-Jan-2015 Target MCU name changed for better compatibility across the platforms - */ - - -#ifndef MBED_IAP -#define MBED_IAP - -#include "mbed.h" - -#if defined(TARGET_LPC176X) - -/* - * memory map information is available in next URL also. - * http://mbed.org/projects/libraries/svn/mbed/trunk/LPC1768/LPC17xx.h - */ - -/** Table for start adress of sectors - * - * LPC1768 internal flash memory sector numbers and addresses - * - * LPC1768 flash memory are and sector number/size - * Table 568 "Sectors in a LPC17xx device", Section 5. "Sector numbers", usermanual - * - * 0x00000000 - 0x0007FFFF flash (29 sectors) - * - * Sector0: 0x00000000 - 0x00000FFF 4K - * Sector1: 0x00001000 - 0x00001FFF 4K - * Sector2: 0x00002000 - 0x00002FFF 4K - * Sector3: 0x00003000 - 0x00003FFF 4K - * Sector4: 0x00004000 - 0x00004FFF 4K - * Sector5: 0x00005000 - 0x00005FFF 4K - * Sector6: 0x00006000 - 0x00006FFF 4K - * Sector7: 0x00007000 - 0x00007FFF 4K - * Sector8: 0x00008000 - 0x00008FFF 4K - * Sector9: 0x00009000 - 0x00009FFF 4K - * Sector10: 0x0000A000 - 0x0000AFFF 4K - * Sector11: 0x0000B000 - 0x0000BFFF 4K - * Sector12: 0x0000C000 - 0x0000CFFF 4K - * Sector13: 0x0000D000 - 0x0000DFFF 4K - * Sector14: 0x0000E000 - 0x0000EFFF 4K - * Sector15: 0x0000F000 - 0x0000FFFF 4K - * - * Sector16: 0x00010000 - 0x00017FFF 32K - * Sector17: 0x00018000 - 0x0001FFFF 32K - * Sector18: 0x00020000 - 0x00027FFF 32K - * Sector19: 0x00028000 - 0x0002FFFF 32K - * Sector20: 0x00030000 - 0x00037FFF 32K - * Sector21: 0x00038000 - 0x0003FFFF 32K - * Sector22: 0x00040000 - 0x00047FFF 32K - * Sector23: 0x00048000 - 0x0004FFFF 32K - * Sector24: 0x00050000 - 0x00057FFF 32K - * Sector25: 0x00058000 - 0x0005FFFF 32K - * Sector26: 0x00060000 - 0x00067FFF 32K - * Sector27: 0x00068000 - 0x0006FFFF 32K - * Sector28: 0x00070000 - 0x00077FFF 32K - * Sector29: 0x00078000 - 0x0007FFFF 32K - */ - -#define FLASH_SECTOR_0 0x00000000 -#define FLASH_SECTOR_1 0x00001000 -#define FLASH_SECTOR_2 0x00002000 -#define FLASH_SECTOR_3 0x00003000 -#define FLASH_SECTOR_4 0x00004000 -#define FLASH_SECTOR_5 0x00005000 -#define FLASH_SECTOR_6 0x00006000 -#define FLASH_SECTOR_7 0x00007000 -#define FLASH_SECTOR_8 0x00008000 -#define FLASH_SECTOR_9 0x00009000 -#define FLASH_SECTOR_10 0x0000A000 -#define FLASH_SECTOR_11 0x0000B000 -#define FLASH_SECTOR_12 0x0000C000 -#define FLASH_SECTOR_13 0x0000D000 -#define FLASH_SECTOR_14 0x0000E000 -#define FLASH_SECTOR_15 0x0000F000 -#define FLASH_SECTOR_16 0x00010000 -#define FLASH_SECTOR_17 0x00018000 -#define FLASH_SECTOR_18 0x00020000 -#define FLASH_SECTOR_19 0x00028000 -#define FLASH_SECTOR_20 0x00030000 -#define FLASH_SECTOR_21 0x00038000 -#define FLASH_SECTOR_22 0x00040000 -#define FLASH_SECTOR_23 0x00048000 -#define FLASH_SECTOR_24 0x00050000 -#define FLASH_SECTOR_25 0x00058000 -#define FLASH_SECTOR_26 0x00060000 -#define FLASH_SECTOR_27 0x00068000 -#define FLASH_SECTOR_28 0x00070000 -#define FLASH_SECTOR_29 0x00078000 -#define FLASH_SECTOR_SIZE_0_TO_15 ( 4 * 1024) -#define FLASH_SECTOR_SIZE_16_TO_29 (32 * 1024) - -#if 0 -static char * sector_start_adress[] = { - (char *)FLASH_SECTOR_0, - (char *)FLASH_SECTOR_1, - (char *)FLASH_SECTOR_2, - (char *)FLASH_SECTOR_3, - (char *)FLASH_SECTOR_4, - (char *)FLASH_SECTOR_5, - (char *)FLASH_SECTOR_6, - (char *)FLASH_SECTOR_7, - (char *)FLASH_SECTOR_8, - (char *)FLASH_SECTOR_9, - (char *)FLASH_SECTOR_10, - (char *)FLASH_SECTOR_11, - (char *)FLASH_SECTOR_12, - (char *)FLASH_SECTOR_13, - (char *)FLASH_SECTOR_14, - (char *)FLASH_SECTOR_15, - (char *)FLASH_SECTOR_16, - (char *)FLASH_SECTOR_17, - (char *)FLASH_SECTOR_18, - (char *)FLASH_SECTOR_19, - (char *)FLASH_SECTOR_20, - (char *)FLASH_SECTOR_21, - (char *)FLASH_SECTOR_22, - (char *)FLASH_SECTOR_23, - (char *)FLASH_SECTOR_24, - (char *)FLASH_SECTOR_25, - (char *)FLASH_SECTOR_26, - (char *)FLASH_SECTOR_27, - (char *)FLASH_SECTOR_28, - (char *)FLASH_SECTOR_29 -}; -#endif - -#elif defined(TARGET_LPC11UXX) || defined(TARGET_LPC11XX) - -#define USER_FLASH_AREA_START FLASH_SECTOR_7 -#define USER_FLASH_AREA_SIZE (FLASH_SECTOR_SIZE * 1) - -/** Table for start adress of sectors - * - * LPC11U24 internal flash memory sector numbers and addresses - * - * LPC11U24 flash memory are and sector number/size - * Table 334 "LPC11U1x/2x flash sectors", Section 20. "Sector numbers", usermanual - * - * 0x00000000 - 0x00007FFF flash (8 sectors) - * - * Sector0: 0x00000000 - 0x00000FFF 4K - * Sector1: 0x00001000 - 0x00001FFF 4K - * Sector2: 0x00002000 - 0x00002FFF 4K - * Sector3: 0x00003000 - 0x00003FFF 4K - * Sector4: 0x00004000 - 0x00004FFF 4K - * Sector5: 0x00005000 - 0x00005FFF 4K - * Sector6: 0x00006000 - 0x00006FFF 4K - * Sector7: 0x00007000 - 0x00007FFF 4K - */ - -#define FLASH_SECTOR_0 0x00000000 -#define FLASH_SECTOR_1 0x00001000 -#define FLASH_SECTOR_2 0x00002000 -#define FLASH_SECTOR_3 0x00003000 -#define FLASH_SECTOR_4 0x00004000 -#define FLASH_SECTOR_5 0x00005000 -#define FLASH_SECTOR_6 0x00006000 -#define FLASH_SECTOR_7 0x00007000 -#define FLASH_SECTOR_SIZE (4 * 1024) - -static char * sector_start_adress[] = { - (char *)FLASH_SECTOR_0, - (char *)FLASH_SECTOR_1, - (char *)FLASH_SECTOR_2, - (char *)FLASH_SECTOR_3, - (char *)FLASH_SECTOR_4, - (char *)FLASH_SECTOR_5, - (char *)FLASH_SECTOR_6, - (char *)FLASH_SECTOR_7, -}; - -#elif defined(TARGET_LPC81X) || defined(TARGET_LPC82X) - -#define USER_FLASH_AREA_START FLASH_SECTOR_15 -#define USER_FLASH_AREA_SIZE (FLASH_SECTOR_SIZE * 1) - -/** Table for start adress of sectors - * - * LPC812/LPC824 internal flash memory sector numbers and addresses - * - * 0x00000000 - 0x00003FFF flash (16 sectors for LPC812) - * 0x00000000 - 0x00007FFF flash (32 sectors for LPC824) - * - * Sector0: 0x00000000 - 0x000003FF 1K - * Sector1: 0x00000400 - 0x000007FF 1K - * Sector2: 0x00000800 - 0x00000BFF 1K - * Sector3: 0x00000C00 - 0x00000FFF 1K - * Sector4: 0x00001000 - 0x000013FF 1K - * Sector5: 0x00001400 - 0x000017FF 1K - * Sector6: 0x00001800 - 0x00001BFF 1K - * Sector7: 0x00001C00 - 0x00001FFF 1K - * Sector8: 0x00002000 - 0x000023FF 1K - * Sector9: 0x00002400 - 0x000027FF 1K - * Sector10: 0x00002800 - 0x00002BFF 1K - * Sector11: 0x00002C00 - 0x00002FFF 1K - * Sector12: 0x00003000 - 0x000033FF 1K - * Sector13: 0x00003400 - 0x000037FF 1K - * Sector14: 0x00003800 - 0x00003BFF 1K - * Sector15: 0x00003C00 - 0x00003FFF 1K - * Sector16: 0x00004000 - 0x000043FF 1K (LPC824 only) - * Sector17: 0x00004400 - 0x000047FF 1K (LPC824 only) - * Sector18: 0x00004800 - 0x00004BFF 1K (LPC824 only) - * Sector19: 0x00004C00 - 0x00004FFF 1K (LPC824 only) - * Sector20: 0x00005000 - 0x000053FF 1K (LPC824 only) - * Sector21: 0x00005400 - 0x000057FF 1K (LPC824 only) - * Sector22: 0x00005800 - 0x00005BFF 1K (LPC824 only) - * Sector23: 0x00005C00 - 0x00005FFF 1K (LPC824 only) - * Sector24: 0x00006000 - 0x000063FF 1K (LPC824 only) - * Sector25: 0x00006400 - 0x000067FF 1K (LPC824 only) - * Sector26: 0x00006800 - 0x00006BFF 1K (LPC824 only) - * Sector27: 0x00006C00 - 0x00006FFF 1K (LPC824 only) - * Sector28: 0x00007000 - 0x000073FF 1K (LPC824 only) - * Sector29: 0x00007400 - 0x000077FF 1K (LPC824 only) - * Sector30: 0x00007800 - 0x00007BFF 1K (LPC824 only) - * Sector31: 0x00007C00 - 0x00007FFF 1K (LPC824 only) - */ - -#define FLASH_SECTOR_0 0x00000000 -#define FLASH_SECTOR_1 0x00000400 -#define FLASH_SECTOR_2 0x00000800 -#define FLASH_SECTOR_3 0x00000C00 -#define FLASH_SECTOR_4 0x00001000 -#define FLASH_SECTOR_5 0x00001400 -#define FLASH_SECTOR_6 0x00001800 -#define FLASH_SECTOR_7 0x00001C00 -#define FLASH_SECTOR_8 0x00002000 -#define FLASH_SECTOR_9 0x00002400 -#define FLASH_SECTOR_10 0x00002800 -#define FLASH_SECTOR_11 0x00002C00 -#define FLASH_SECTOR_12 0x00003000 -#define FLASH_SECTOR_13 0x00003400 -#define FLASH_SECTOR_14 0x00003800 -#define FLASH_SECTOR_15 0x00003C00 -#define FLASH_SECTOR_16 0x00004000 // for LPC824 only -#define FLASH_SECTOR_17 0x00004400 // for LPC824 only -#define FLASH_SECTOR_18 0x00004800 // for LPC824 only -#define FLASH_SECTOR_19 0x00004C00 // for LPC824 only -#define FLASH_SECTOR_20 0x00005000 // for LPC824 only -#define FLASH_SECTOR_21 0x00005400 // for LPC824 only -#define FLASH_SECTOR_22 0x00005800 // for LPC824 only -#define FLASH_SECTOR_23 0x00005C00 // for LPC824 only -#define FLASH_SECTOR_24 0x00006000 // for LPC824 only -#define FLASH_SECTOR_25 0x00006400 // for LPC824 only -#define FLASH_SECTOR_26 0x00006800 // for LPC824 only -#define FLASH_SECTOR_27 0x00006C00 // for LPC824 only -#define FLASH_SECTOR_28 0x00007000 // for LPC824 only -#define FLASH_SECTOR_29 0x00007400 // for LPC824 only -#define FLASH_SECTOR_30 0x00007800 // for LPC824 only -#define FLASH_SECTOR_31 0x00007C00 // for LPC824 only -#define FLASH_SECTOR_SIZE (1 * 1024) - -static char * sector_start_adress[] = { - (char *)FLASH_SECTOR_0, - (char *)FLASH_SECTOR_1, - (char *)FLASH_SECTOR_2, - (char *)FLASH_SECTOR_3, - (char *)FLASH_SECTOR_4, - (char *)FLASH_SECTOR_5, - (char *)FLASH_SECTOR_6, - (char *)FLASH_SECTOR_7, - (char *)FLASH_SECTOR_8, - (char *)FLASH_SECTOR_9, - (char *)FLASH_SECTOR_10, - (char *)FLASH_SECTOR_11, - (char *)FLASH_SECTOR_12, - (char *)FLASH_SECTOR_13, - (char *)FLASH_SECTOR_14, - (char *)FLASH_SECTOR_15, - (char *)FLASH_SECTOR_16, // for LPC824 only - (char *)FLASH_SECTOR_17, // for LPC824 only - (char *)FLASH_SECTOR_18, // for LPC824 only - (char *)FLASH_SECTOR_19, // for LPC824 only - (char *)FLASH_SECTOR_20, // for LPC824 only - (char *)FLASH_SECTOR_21, // for LPC824 only - (char *)FLASH_SECTOR_22, // for LPC824 only - (char *)FLASH_SECTOR_23, // for LPC824 only - (char *)FLASH_SECTOR_24, // for LPC824 only - (char *)FLASH_SECTOR_25, // for LPC824 only - (char *)FLASH_SECTOR_26, // for LPC824 only - (char *)FLASH_SECTOR_27, // for LPC824 only - (char *)FLASH_SECTOR_28, // for LPC824 only - (char *)FLASH_SECTOR_29, // for LPC824 only - (char *)FLASH_SECTOR_30, // for LPC824 only - (char *)FLASH_SECTOR_31 // for LPC824 only -}; - -#endif - -/** Error code by IAP routine - * - * Table 588 "ISP Return Codes Summary", Section 7.15 "ISP Return Codes", usermanual - */ - -enum error_code { - IAP_CMD_SUCCESS, - IAP_INVALID_COMMAND, - IAP_SRC_ADDR_ERROR, - IAP_DST_ADDR_ERROR, - IAP_SRC_ADDR_NOT_MAPPED, - IAP_DST_ADDR_NOT_MAPPED, - IAP_COUNT_ERROR, - IAP_INVALID_SECTOR, - IAP_SECTOR_NOT_BLANK, - IAP_SECTOR_NOT_PREPARED_FOR_WRITE_OPERATION, - IAP_COMPARE_ERROR, - IAP_BUSY, - IAP_PARAM_ERROR, - IAP_ADDR_ERROR, - IAP_ADDR_NOT_MAPPED, - IAP_CMD_LOCKED, - IAP_INVALID_CODE, - IAP_INVALID_BAUD_RATE, - IAP_INVALID_STOP_BIT, - IAP_CODE_READ_PROTECTION_ENABLED -}; - - -/* - * IAP routine entry - * - * "IAP commands" - */ - -#define IAP_LOCATION 0x1fff1ff1 -typedef void (*IAP_call)(unsigned int [], unsigned int []); - - -/** IAP class - * - * Interface for internal flash memory access - */ - -class IAP -{ -public: - - /** Constructor for IAP - * - */ - IAP() : iap_entry( reinterpret_cast(IAP_LOCATION) ), cclk_kHz( SystemCoreClock / 1000 ) {} - - /** Reinvoke ISP - * - * @return error code - */ - int reinvoke_isp( void ); - - /** Read part identification number - * - * @return device ID - * @see read_serial() - */ - int read_ID( void ); - - /** Read device serial number - * - * @return device serial number - * @see read_ID() - */ - int *read_serial( void ); - - /** Blank check sector(s) - * - * @param start a Start Sector Number - * @param end an End Sector Number (should be greater than or equal to start sector number). - * @return error code: CMD_SUCCESS | BUSY | SECTOR_NOT_BLANK | INVALID_SECTOR - */ - int blank_check( int start, int end ); - - /** Erase Sector(s) - * - * @param sector a Sector Number - * @return error code: CMD_SUCCESS | BUSY | SECTOR_NOT_PREPARED_FOR_WRITE_OPERATION | INVALID_SECTOR - */ - int erase( uint32_t sector ); - - /** Prepare sector(s) for write operation - * - * @param start a Start Sector Number - * @param end an End Sector Number (should be greater than or equal to start sector number). - * @return error code: CMD_SUCCESS | BUSY | INVALID_SECTOR - */ - int prepare( int start, int end ); - - /** Copy RAM to Flash - * - * @param source_addr Source RAM address from which data bytes are to be read. This address should be a word boundary. - * @param target_addr Destination flash address where data bytes are to be written. This address should be a 256 byte boundary. - * @param size Number of bytes to be written. Should be 256 | 512 | 1024 | 4096. - * @return error code: CMD_SUCCESS | SRC_ADDR_ERROR (Address not a word boundary) | DST_ADDR_ERROR (Address not on correct boundary) | SRC_ADDR_NOT_MAPPED | DST_ADDR_NOT_MAPPED | COUNT_ERROR (Byte count is not 256 | 512 | 1024 | 4096) | SECTOR_NOT_PREPARED_FOR_WRITE_OPERATION | BUSY - */ - int write( uint32_t *source_addr, uint32_t target_addr, int size ); - - /** Compare - * - * @param source_addr Starting flash or RAM address of data bytes to be compared. This address should be a word boundary. - * @param target_addr Starting flash or RAM address of data bytes to be compared. This address should be a word boundary. - * @param size Number of bytes to be compared; should be a multiple of 4. - * @return error code: CMD_SUCCESS | COMPARE_ERROR | COUNT_ERROR (Byte count is not a multiple of 4) | ADDR_ERROR | ADDR_NOT_MAPPED - */ - int compare( uint32_t *source_addr, uint32_t *target_addr, int size ); - - /** Read Boot code version number - * - * @return 2 bytes of boot code version number - */ - int read_BootVer( void ); - - /** Get user reserved flash start address - * - * @return start address of user reserved flash memory - * @see reserved_flash_area_size() - */ - - uint32_t *reserved_flash_area_start( void ); - - /** Get user reserved flash size - * - * @return size of user reserved flash memory - * @see reserved_flash_area_start() - */ - int reserved_flash_area_size( void ); - - int find_sector( uint32_t addr ); - - int get_sector_size( uint32_t addr ); - - int get_flash_size( void ); - -#if defined(TARGET_LPC11UXX) - - /** Copy RAM to EEPROM (LPC11U24) - * - * @param source_addr Source RAM address from which data bytes are to be read. - * @param target_addr Destination EEPROM address where data bytes are to be written. - * @param size Number of bytes to be written. - * @return error code: CMD_SUCCESS | SRC_ADDR_NOT_MAPPED | DST_ADDR_NOT_MAPPED - * Remark: The top 64 bytes of the EEPROM memory are reserved and cannot be written to. - */ - int write_eeprom( uint32_t *source_addr, uint32_t *target_addr, int size ); - - /** Copy EEPROM to RAM (LPC11U24) - * - * @param source_addr Source EEPROM address from which data bytes are to be read. - * @param target_addr Destination RAM address where data bytes are to be written. - * @param size Number of bytes to be written. - * @return error code: CMD_SUCCESS | SRC_ADDR_NOT_MAPPED | DST_ADDR_NOT_MAPPED - * Remark: The top 64 bytes of the EEPROM memory are reserved and cannot be written to. - */ - int read_eeprom( uint32_t *source_addr, uint32_t *target_addr, int size ); - -#elif defined(TARGET_LPC81X) || defined(TARGET_LPC82X) - - /** Erase page(s) (LPC812, LPC824) - * - * @param start Start page number. - * @param end End page number (should be greater than or equal to start page). - * @return error code: CMD_SUCCESS | BUSY | SECTOR_NOT_PREPARED_FOR_WRITE_OPERATION | INVALID_SECTOR - */ - int erase_page( int start, int end ); - -#endif - -private: - IAP_call iap_entry; - unsigned int IAP_command[ 5 ]; - unsigned int IAP_result[ 5 ]; - int cclk_kHz; -} -; - -#endif // #ifndef MBED_IAP diff --git a/legacy/app/PID/PID.cpp b/legacy/app/PID/PID.cpp deleted file mode 100644 index 104abf0..0000000 --- a/legacy/app/PID/PID.cpp +++ /dev/null @@ -1,200 +0,0 @@ -/********************************************************************************************** - * Arduino PID Library - Version 1.1.1 - * by Brett Beauregard brettbeauregard.com - * - * This Library is licensed under a GPLv3 License - **********************************************************************************************/ - -#include - -/*Constructor (...)********************************************************* - * The parameters specified here are those for for which we can't set up - * reliable defaults, so we need to have the user set them. - ***************************************************************************/ -PID::PID(double* Input, double* Output, double* Setpoint, - double Kp, double Ki, double Kd, int ControllerDirection) -{ - - myOutput = Output; - myInput = Input; - mySetpoint = Setpoint; - inAuto = false; - - PID::SetOutputLimits(0, 3.3); //default output limit corresponds to - //the arduino pwm limits - - SampleTime = 1000; //default Controller Sample Time is 0.1 seconds - - PID::SetControllerDirection(ControllerDirection); - PID::SetTunings(Kp, Ki, Kd); -} - - -/* Compute() ********************************************************************** - * This, as they say, is where the magic happens. this function should be called - * every time "void loop()" executes. the function will decide for itself whether a new - * pid Output needs to be computed. returns true when the output is computed, - * false when nothing has been done. - **********************************************************************************/ -bool PID::Compute() -{ - if(!inAuto) { - return false; - } - - /*Compute all the working error variables*/ - double input = *myInput; - double error = *mySetpoint - input; - - ITerm+= (ki * error); - - if(ITerm > outMax) { - ITerm= outMax; - } else if(ITerm < outMin) { - ITerm= outMin; - } - - double dInput = (input - lastInput); - - /*Compute PID Output*/ - double output = kp * error + ITerm- kd * dInput; - - if(output > outMax) { - output = outMax; - } else if(output < outMin) { - output = outMin; - } - - *myOutput = output; - - /*Remember some variables for next time*/ - lastInput = input; - return true; -} - - -/* SetTunings(...)************************************************************* - * This function allows the controller's dynamic performance to be adjusted. - * it's called automatically from the constructor, but tunings can also - * be adjusted on the fly during normal operation - ******************************************************************************/ -void PID::SetTunings(double Kp, double Ki, double Kd) -{ - if (Kp<0 || Ki<0 || Kd<0) return; - - dispKp = Kp; dispKi = Ki; dispKd = Kd; - - double SampleTimeInSec = ((double)SampleTime)/1000; - kp = Kp; - ki = Ki * SampleTimeInSec; - kd = Kd / SampleTimeInSec; - - if(controllerDirection ==REVERSE) - { - kp = (0 - kp); - ki = (0 - ki); - kd = (0 - kd); - } -} - -/* SetSampleTime(...) ********************************************************* - * sets the period, in Milliseconds, at which the calculation is performed - ******************************************************************************/ -void PID::SetSampleTime(int NewSampleTime) -{ - if (NewSampleTime > 0) - { - double ratio = (double)NewSampleTime - / (double)SampleTime; - ki *= ratio; - kd /= ratio; - SampleTime = (unsigned long)NewSampleTime; - } -} - -/* SetOutputLimits(...)**************************************************** - * This function will be used far more often than SetInputLimits. while - * the input to the controller will generally be in the 0-1023 range (which is - * the default already,) the output will be a little different. maybe they'll - * be doing a time window and will need 0-8000 or something. or maybe they'll - * want to clamp it from 0-125. who knows. at any rate, that can all be done - * here. - **************************************************************************/ -void PID::SetOutputLimits(double Min, double Max) -{ - if(Min >= Max) return; - outMin = Min; - outMax = Max; - - if(inAuto) { - if(*myOutput > outMax) { - *myOutput = outMax; - } else if(*myOutput < outMin) { - *myOutput = outMin; - } - - if(ITerm > outMax) { - ITerm= outMax; - } else if(ITerm < outMin) { - ITerm= outMin; - } - } -} - -/* SetMode(...)**************************************************************** - * Allows the controller Mode to be set to manual (0) or Automatic (non-zero) - * when the transition from manual to auto occurs, the controller is - * automatically initialized - ******************************************************************************/ -void PID::SetMode(int Mode) -{ - bool newAuto = (Mode == AUTOMATIC); - if(newAuto == !inAuto) - { /*we just went from manual to auto*/ - PID::Initialize(); - } - inAuto = newAuto; -} - -/* Initialize()**************************************************************** - * does all the things that need to happen to ensure a bumpless transfer - * from manual to automatic mode. - ******************************************************************************/ -void PID::Initialize() -{ - ITerm = *myOutput; - lastInput = *myInput; - if(ITerm > outMax) { - ITerm = outMax; - } else if(ITerm < outMin) { - ITerm = outMin; - } -} - -/* SetControllerDirection(...)************************************************* - * The PID will either be connected to a DIRECT acting process (+Output leads - * to +Input) or a REVERSE acting process(+Output leads to -Input.) we need to - * know which one, because otherwise we may increase the output when we should - * be decreasing. This is called from the constructor. - ******************************************************************************/ -void PID::SetControllerDirection(int Direction) -{ - if(inAuto && Direction !=controllerDirection) - { - kp = (0 - kp); - ki = (0 - ki); - kd = (0 - kd); - } - controllerDirection = Direction; -} - -/* Status Funcions************************************************************* - * Just because you set the Kp=-1 doesn't mean it actually happened. these - * functions query the internal state of the PID. they're here for display - * purposes. this are the functions the PID Front-end uses for example - ******************************************************************************/ -double PID::GetKp(){ return dispKp; } -double PID::GetKi(){ return dispKi;} -double PID::GetKd(){ return dispKd;} -int PID::GetMode(){ return inAuto ? AUTOMATIC : MANUAL;} -int PID::GetDirection(){ return controllerDirection;} diff --git a/legacy/app/PID/PID.h b/legacy/app/PID/PID.h deleted file mode 100644 index 045d36b..0000000 --- a/legacy/app/PID/PID.h +++ /dev/null @@ -1,77 +0,0 @@ -#ifndef PID_h -#define PID_h -#define LIBRARY_VERSION 1.1.1 - - //Constants used in some of the functions below -#define AUTOMATIC 1 -#define MANUAL 0 -#define DIRECT 0 -#define REVERSE 1 - -class PID -{ -public: - - //commonly used functions ************************************************************************** - PID(double*, double*, double*, // * constructor. links the PID to the Input, Output, and - double, double, double, int); // Setpoint. Initial tuning parameters are also set here - - void SetMode(int Mode); // * sets PID to either Manual (0) or Auto (non-0) - - bool Compute(); // * performs the PID calculation. it should be - // called every time loop() cycles. ON/OFF and - // calculation frequency can be set using SetMode - // SetSampleTime respectively - - void SetOutputLimits(double, double); //clamps the output to a specific range. 0-255 by default, but - //it's likely the user will want to change this depending on - //the application - - - - //available but not commonly used functions ******************************************************** - void SetTunings(double, double, // * While most users will set the tunings once in the - double); // constructor, this function gives the user the option - // of changing tunings during runtime for Adaptive control - void SetControllerDirection(int); // * Sets the Direction, or "Action" of the controller. DIRECT - // means the output will increase when error is positive. REVERSE - // means the opposite. it's very unlikely that this will be needed - // once it is set in the constructor. - void SetSampleTime(int); // * sets the frequency, in Milliseconds, with which - // the PID calculation is performed. default is 100 - - - - //Display functions **************************************************************** - double GetKp(); // These functions query the pid for interal values. - double GetKi(); // they were created mainly for the pid front-end, - double GetKd(); // where it's important to know what is actually - int GetMode(); // inside the PID. - int GetDirection(); // - -private: - void Initialize(); - - double dispKp; // * we'll hold on to the tuning parameters in user-entered - double dispKi; // format for display purposes - double dispKd; // - - double kp; // * (P)roportional Tuning Parameter - double ki; // * (I)ntegral Tuning Parameter - double kd; // * (D)erivative Tuning Parameter - - int controllerDirection; - - double *myInput; // * Pointers to the Input, Output, and Setpoint variables - double *myOutput; // This creates a hard link between the variables and the - double *mySetpoint; // PID, freeing the user from having to constantly tell us - // what these values are. with pointers we'll just know. - - unsigned long lastTime; - double ITerm, lastInput; - - unsigned long SampleTime; - double outMin, outMax; - bool inAuto; -}; -#endif diff --git a/legacy/app/attenuators.cpp b/legacy/app/attenuators.cpp deleted file mode 100644 index 85fe885..0000000 --- a/legacy/app/attenuators.cpp +++ /dev/null @@ -1,54 +0,0 @@ -#include "attenuators.h" - -DigitalOut dataA(P0_18); // Data line to attenuator. LVTTL, low = reset, init = low.Set first attenuators (Att) -DigitalOut dataC(P0_1); // Data line to attenuator. LVTTL, low = reset, init = low.Set first attenuators (Att) -DigitalOut dataB(P2_0); // Data line to attenuator. LVTTL, low = reset, init = low. Set RF attenuators (Att) -DigitalOut dataD(P0_11); // Data line to attenuator. LVTTL, low = reset, init = low. Set RF attenuators (Att) - -DigitalOut clk(P0_17); // Digital control attenuation. LVTTL, low = reset, init = low.Digital control attenuation -DigitalOut LE(P0_15); // Chip select for RFFE attenuators (all channels). LVTTL, low = reset, init = low.Digital control calibration - -double attenuators_update( double new_att ) -{ - bool attVec[6]; - - /* Check value boundaries */ - if (new_att < MIN_ATTENUATION) { - new_att = MIN_ATTENUATION; - } - - if (new_att > MAX_ATTENUATION) { - new_att = MAX_ATTENUATION; - } - - /* Checking and setting attenuators value to fisable values (0.5 dB step) */ - new_att = (float) (int(new_att*2))/2; - - /* Save new value to FeRAM */ - feram.set_attenuation(new_att); - - /* Convert to binary vector (multiply by 2 because the LSB is 0.5dB) */ - int2bin6(int(new_att*2), attVec); - - LE = 0; - clk = 0; - - /* Send serial data to all attenuators */ - for (int i = 5; i >= 0; i--) { - dataA = attVec[i]; - dataB = attVec[i]; - dataC = attVec[i]; - dataD = attVec[i]; - clk = 1; - wait_us(0.1); - clk = 0; - wait_us(0.1); - } - - /* Falling edge on Latch Enable pin */ - LE = 1; - wait_us(0.1); - LE = 0; - - return new_att; -} diff --git a/legacy/app/attenuators.h b/legacy/app/attenuators.h deleted file mode 100644 index d610e39..0000000 --- a/legacy/app/attenuators.h +++ /dev/null @@ -1,16 +0,0 @@ -#ifndef ATTENUATORS_H -#define ATTENUATORS_H - -#include "mbed.h" -#include "Drivers.h" -#include "pcbnAPI.h" -#include "util.h" - -#define MIN_ATTENUATION 0.0 -#define MAX_ATTENUATION 31.5 - -extern FeRAM feram; - -double attenuators_update( double att ); - -#endif diff --git a/legacy/app/bsmp/bsmp.c b/legacy/app/bsmp/bsmp.c deleted file mode 100644 index 2ec29c0..0000000 --- a/legacy/app/bsmp/bsmp.c +++ /dev/null @@ -1,40 +0,0 @@ -#include "bsmp.h" - -static char* error_str[BSMP_ERR_MAX] = -{ - [BSMP_SUCCESS] = "Success", - [BSMP_ERR_PARAM_INVALID] = "An invalid parameter was passed", - [BSMP_ERR_PARAM_OUT_OF_RANGE] = "A parameter was out of the acceptable" - " range", - [BSMP_ERR_OUT_OF_MEMORY] = "Not enough memory to complete request", - [BSMP_ERR_DUPLICATE] = "Entity already registered", - [BSMP_ERR_COMM] = "Sending or receiving a message failed", - [BSMP_ERR_NOT_INITIALIZED] = "Instance not initialized", -}; - -#define BINOPS_FUNC(name, operation)\ - void binops_##name (uint8_t *data, uint8_t *mask, uint8_t size) {\ - while(size--)\ - data[size] operation mask[size];\ - } - -BINOPS_FUNC(and, &=) -BINOPS_FUNC(or, |=) -BINOPS_FUNC(xor, ^=) -BINOPS_FUNC(clear, &=~) - -bin_op_function bin_op[] = -{ - ['A'] = binops_and, // AND - ['X'] = binops_xor, // XOR - ['O'] = binops_or, // OR - ['C'] = binops_clear, // CLEAR BITS - ['S'] = binops_or, // SET BITS - ['T'] = binops_xor // TOGGLE BITS -}; - -char *bsmp_error_str (enum bsmp_err error) -{ - return error_str[error]; -} - diff --git a/legacy/app/bsmp/bsmp.h b/legacy/app/bsmp/bsmp.h deleted file mode 100644 index 1ac3e9c..0000000 --- a/legacy/app/bsmp/bsmp.h +++ /dev/null @@ -1,232 +0,0 @@ -/* Public definitions for both server and client */ - -#ifndef BSMP_H -#define BSMP_H - -#include -#include - -/* Library-wide limits */ - -#define BSMP_HEADER_SIZE 3 // Command code + 2 bytes for size -#define BSMP_MAX_PAYLOAD 65535 -#define BSMP_MAX_MESSAGE (BSMP_HEADER_SIZE+BSMP_MAX_PAYLOAD) - -#define BSMP_MAX_VARIABLES 30 -#define BSMP_MAX_GROUPS 8 -#define BSMP_MAX_CURVES 128 -#define BSMP_MAX_FUNCTIONS 128 - -/* Version info */ - -#define BSMP_VERSION_STR_MAX_LEN 20 -struct bsmp_version -{ - uint8_t major; - uint8_t minor; - uint8_t revision; - char str[BSMP_VERSION_STR_MAX_LEN]; -}; - -/* Standard group ID */ - -enum group_id -{ - GROUP_ALL_ID, - GROUP_READ_ID, - GROUP_WRITE_ID, - - GROUP_STANDARD_COUNT, -}; - -/* Binary operations */ - -enum bsmp_bin_op -{ - BIN_OP_AND, - BIN_OP_OR, - BIN_OP_XOR, - BIN_OP_SET, - BIN_OP_CLEAR, - BIN_OP_TOGGLE, - - BIN_OP_COUNT, // Number of binary operations -}; - -typedef void (*bin_op_function) (uint8_t *data, uint8_t *mask, uint8_t size); -extern bin_op_function bin_op[]; - -/* Error codes */ - -enum bsmp_err -{ - BSMP_SUCCESS, // Operation executed successfully - BSMP_ERR_PARAM_INVALID, // An invalid parameter was passed - BSMP_ERR_PARAM_OUT_OF_RANGE, // A param not in the acceptable range was - // passed - BSMP_ERR_OUT_OF_MEMORY, // Not enough memory to complete operation - BSMP_ERR_DUPLICATE, // Trying to register an already registered - // object - BSMP_ERR_COMM, // There was a communication error reported - // by one of the communication functions. - BSMP_ERR_NOT_INITIALIZED, // Instance wasn't initialized - BSMP_ERR_MAX -}; - -/**** Entities ****/ - -/* Limits */ - -#define BSMP_VAR_MAX_SIZE 128 - -#define BSMP_CURVE_MAX_BLOCKS 65536 -#define BSMP_CURVE_BLOCK_MAX_SIZE 65520 -#define BSMP_CURVE_LIST_INFO 5 -#define BSMP_CURVE_BLOCK_INFO 3 -#define BSMP_CURVE_CSUM_SIZE 16 - -#define BSMP_FUNC_MAX_INPUT 15 -#define BSMP_FUNC_MAX_OUTPUT 15 - -/**** Structures and lists ****/ - -/* Variable */ - -struct bsmp_var_info -{ - uint8_t id; // ID of the variable, used in the protocol. - bool writable; // Determine if the variable is writable. - uint8_t size; // Indicates how many bytes 'data' contains. -}; - -struct bsmp_var -{ - struct bsmp_var_info info; // Information about the variable identification - bool (*value_ok) (struct bsmp_var *, uint8_t *); // Checker - void *data; // Pointer to the value of the variable. - void *user; // The user can make use of this pointer at - // will. It is not touched by BSMP. -}; - -struct bsmp_var_info_list -{ - uint32_t count; - struct bsmp_var_info list[BSMP_MAX_VARIABLES]; -}; - -struct bsmp_var_info_ptr_list -{ - uint32_t count; - struct bsmp_var_info *list[BSMP_MAX_VARIABLES]; -}; - -struct bsmp_var_ptr_list -{ - uint32_t count; - struct bsmp_var *list[BSMP_MAX_VARIABLES]; -}; - -/* Group */ - -struct bsmp_group -{ - uint8_t id; // ID of the group - bool writable; // Whether all variables in the group are writable - uint16_t size; // Sum of the sizes of all variables in the group - - // List of pointers to the variables of this group - struct bsmp_var_info_ptr_list vars; -}; - -struct bsmp_group_list -{ - uint32_t count; - struct bsmp_group list[BSMP_MAX_GROUPS]; -}; - -/* Curve */ - -struct bsmp_curve_info -{ - uint8_t id; // ID of the curve, used in the protocol. - bool writable; // Determine if the curve is writable. - uint32_t nblocks; // How many blocks the curve contains. - uint16_t block_size; // Maximum number of bytes in a block - uint8_t checksum[16]; // MD5 checksum of the curve -}; - -struct bsmp_curve; - -typedef void (*bsmp_curve_read_t) (struct bsmp_curve *curve, uint16_t block, - uint8_t *data, uint16_t *len); -typedef void (*bsmp_curve_write_t) (struct bsmp_curve *curve, uint16_t block, - uint8_t *data, uint16_t len); -struct bsmp_curve -{ - // Info about the curve identification - struct bsmp_curve_info info; - - // Functions to read/write a block - void (*read_block)(struct bsmp_curve *curve, uint16_t block, uint8_t *data, - uint16_t *len); - - void (*write_block)(struct bsmp_curve *curve, uint16_t block, uint8_t *data, - uint16_t len); - - // The user can make use of this variable as he wishes. It is not touched by - // BSMP - void *user; -}; - -struct bsmp_curve_info_list -{ - uint32_t count; - struct bsmp_curve_info list[BSMP_MAX_CURVES]; -}; - -struct bsmp_curve_ptr_list -{ - uint32_t count; - struct bsmp_curve *list[BSMP_MAX_CURVES]; -}; - -/* Function */ - -struct bsmp_func_info -{ - uint8_t id; // ID of the function, used in the protocol - uint8_t input_size; // How many bytes of input - uint8_t output_size; // How many bytes of output -}; - -typedef uint8_t (*bsmp_func_t) (uint8_t *input, uint8_t *output); -struct bsmp_func -{ - struct bsmp_func_info info; // Information about the function - bsmp_func_t func_p; // Pointer to the function to be executed -}; - - -struct bsmp_func_info_list -{ - uint32_t count; - struct bsmp_func_info list[BSMP_MAX_FUNCTIONS]; -}; - -struct bsmp_func_ptr_list -{ - uint32_t count; - struct bsmp_func *list[BSMP_MAX_FUNCTIONS]; -}; - -/** - * Returns an error string associated with the given error code - * - * @param error [input] The error code - * - * @return A string that describes the error - */ -char * bsmp_error_str (enum bsmp_err error); - -#endif - diff --git a/legacy/app/bsmp/bsmp_priv.h b/legacy/app/bsmp/bsmp_priv.h deleted file mode 100644 index 1ce44de..0000000 --- a/legacy/app/bsmp/bsmp_priv.h +++ /dev/null @@ -1,77 +0,0 @@ -/* Private definitions for server and client */ - -#ifndef BSMP_PRIV_H -#define BSMP_PRIV_H - -#include -#include - -#include "bsmp.h" - -#define WRITABLE_MASK 0x80 -#define SIZE_MASK 0x7F - -#define WRITABLE 0x80 -#define READ_ONLY 0x00 - -enum command_code -{ - // Query commands - CMD_QUERY_VERSION = 0x00, - CMD_VERSION, - CMD_VAR_QUERY_LIST, - CMD_VAR_LIST, - CMD_GROUP_QUERY_LIST, - CMD_GROUP_LIST, - CMD_GROUP_QUERY, - CMD_GROUP, - CMD_CURVE_QUERY_LIST, - CMD_CURVE_LIST, - CMD_CURVE_QUERY_CSUM, - CMD_CURVE_CSUM, - CMD_FUNC_QUERY_LIST, - CMD_FUNC_LIST, - - // Read commands - CMD_VAR_READ = 0x10, - CMD_VAR_VALUE, - CMD_GROUP_READ, - CMD_GROUP_VALUES, - - // Write commands - CMD_VAR_WRITE = 0x20, - CMD_GROUP_WRITE = 0x22, - CMD_VAR_BIN_OP = 0x24, - CMD_GROUP_BIN_OP = 0x26, - CMD_VAR_WRITE_READ = 0x28, - - // Group manipulation commands - CMD_GROUP_CREATE = 0x30, - CMD_GROUP_REMOVE_ALL = 0x32, - - // Curve commands - CMD_CURVE_BLOCK_REQUEST = 0x40, - CMD_CURVE_BLOCK, - CMD_CURVE_RECALC_CSUM, - - // Function commands - CMD_FUNC_EXECUTE = 0x50, - CMD_FUNC_RETURN, - CMD_FUNC_ERROR = 0x53, - - // Error codes - CMD_OK = 0xE0, - CMD_ERR_MALFORMED_MESSAGE, - CMD_ERR_OP_NOT_SUPPORTED, - CMD_ERR_INVALID_ID, - CMD_ERR_INVALID_VALUE, - CMD_ERR_INVALID_PAYLOAD_SIZE, - CMD_ERR_READ_ONLY, - CMD_ERR_INSUFFICIENT_MEMORY, - - CMD_MAX -}; - -#endif /* COMMON_H */ - - diff --git a/legacy/app/bsmp/md5/md5.c b/legacy/app/bsmp/md5/md5.c deleted file mode 100644 index c5708a5..0000000 --- a/legacy/app/bsmp/md5/md5.c +++ /dev/null @@ -1,275 +0,0 @@ -/* MD5C.C - RSA Data Security, Inc., MD5 message-digest algorithm */ - -/* Copyright (C) 1991-2, RSA Data Security, Inc. Created 1991. All -rights reserved. - -License to copy and use this software is granted provided that it -is identified as the "RSA Data Security, Inc. MD5 Message-Digest -Algorithm" in all material mentioning or referencing this software -or this function. - -License is also granted to make and use derivative works provided -that such works are identified as "derived from the RSA Data -Security, Inc. MD5 Message-Digest Algorithm" in all material -mentioning or referencing the derived work. - -RSA Data Security, Inc. makes no representations concerning either -the merchantability of this software or the suitability of this -software for any particular purpose. It is provided "as is" -without express or implied warranty of any kind. - -These notices must be retained in any copies of any part of this -documentation and/or software. - */ - -#include "md5.h" -#include - -/* Constants for MD5Transform routine. */ - -#define S11 7 -#define S12 12 -#define S13 17 -#define S14 22 -#define S21 5 -#define S22 9 -#define S23 14 -#define S24 20 -#define S31 4 -#define S32 11 -#define S33 16 -#define S34 23 -#define S41 6 -#define S42 10 -#define S43 15 -#define S44 21 - -static void MD5Transform (uint32_t [4], uint8_t [64]); -static void Encode (uint8_t *, uint32_t *, unsigned int); -static void Decode (uint32_t *, uint8_t *, unsigned int); - -static unsigned char PADDING[64] = { - 0x80, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 -}; - -/* F, G, H and I are basic MD5 functions. */ -#define F(x, y, z) (((x) & (y)) | ((~x) & (z))) -#define G(x, y, z) (((x) & (z)) | ((y) & (~z))) -#define H(x, y, z) ((x) ^ (y) ^ (z)) -#define I(x, y, z) ((y) ^ ((x) | (~z))) - -/* ROTATE_LEFT rotates x left n bits. */ -#define ROTATE_LEFT(x, n) (((x) << (n)) | ((x) >> (32-(n)))) - -/* FF, GG, HH, and II transformations for rounds 1, 2, 3, and 4. -Rotation is separate from addition to prevent recomputation. */ -#define FF(a, b, c, d, x, s, ac) { \ - (a) += F ((b), (c), (d)) + (x) + (uint32_t)(ac); \ - (a) = ROTATE_LEFT ((a), (s)); \ - (a) += (b); \ - } -#define GG(a, b, c, d, x, s, ac) { \ - (a) += G ((b), (c), (d)) + (x) + (uint32_t)(ac); \ - (a) = ROTATE_LEFT ((a), (s)); \ - (a) += (b); \ - } -#define HH(a, b, c, d, x, s, ac) { \ - (a) += H ((b), (c), (d)) + (x) + (uint32_t)(ac); \ - (a) = ROTATE_LEFT ((a), (s)); \ - (a) += (b); \ - } -#define II(a, b, c, d, x, s, ac) { \ - (a) += I ((b), (c), (d)) + (x) + (uint32_t)(ac); \ - (a) = ROTATE_LEFT ((a), (s)); \ - (a) += (b); \ - } - -/* MD5 initialization. Begins an MD5 operation, writing a new context. */ -void MD5Init(MD5_CTX *context) -{ - context->count[0] = context->count[1] = 0; - /* Load magic initialization constants. */ - context->state[0] = 0x67452301; - context->state[1] = 0xefcdab89; - context->state[2] = 0x98badcfe; - context->state[3] = 0x10325476; -} - -/* MD5 block update operation. Continues an MD5 message-digest - operation, processing another message block, and updating the - context. */ -void MD5Update(MD5_CTX *context, uint8_t *input, unsigned int inputLen) -{ - unsigned int i, index, partLen; - - /* Compute number of bytes mod 64 */ - index = (unsigned int) ((context->count[0] >> 3) & 0x3F); - - /* Update number of bits */ - if ((context->count[0] += ((uint32_t) inputLen << 3)) < ((uint32_t) inputLen << 3)) - context->count[1]++; - context->count[1] += ((uint32_t) inputLen >> 29); - - partLen = 64 - index; - - /* Transform as many times as possible. */ - if (inputLen >= partLen) - { - memcpy((uint8_t*) & context->buffer[index], (uint8_t*) input, partLen); - MD5Transform(context->state, context->buffer); - - for (i = partLen; i + 63 < inputLen; i += 64) - MD5Transform(context->state, &input[i]); - - index = 0; - } - else - i = 0; - - /* Buffer remaining input */ - memcpy((uint8_t*) & context->buffer[index], (uint8_t*) & input[i], - inputLen - i); -} - -/* MD5 finalization. Ends an MD5 message-digest operation, writing the - the message digest and zeroizing the context. - */ -void MD5Final(uint8_t digest[16], MD5_CTX *context) -{ - uint8_t bits[8]; - unsigned int index, padLen; - - /* Save number of bits */ - Encode(bits, context->count, 8); - - /* Pad out to 56 mod 64. - */ - index = (unsigned int) ((context->count[0] >> 3) & 0x3f); - padLen = (index < 56) ? (56 - index) : (120 - index); - MD5Update(context, PADDING, padLen); - - /* Append length (before padding) */ - MD5Update(context, bits, 8); - - /* Store state in digest */ - Encode(digest, context->state, 16); - - /* Zeroize sensitive information. */ - memset((uint8_t*) context, 0, sizeof (*context)); -} - -/* MD5 basic transformation. Transforms state based on block. */ -static void MD5Transform(uint32_t state[4], uint8_t block[64]) -{ - uint32_t a = state[0], b = state[1], c = state[2], d = state[3], x[16]; - - Decode(x, block, 64); - - /* Round 1 */ - FF(a, b, c, d, x[ 0], S11, 0xd76aa478); /* 1 */ - FF(d, a, b, c, x[ 1], S12, 0xe8c7b756); /* 2 */ - FF(c, d, a, b, x[ 2], S13, 0x242070db); /* 3 */ - FF(b, c, d, a, x[ 3], S14, 0xc1bdceee); /* 4 */ - FF(a, b, c, d, x[ 4], S11, 0xf57c0faf); /* 5 */ - FF(d, a, b, c, x[ 5], S12, 0x4787c62a); /* 6 */ - FF(c, d, a, b, x[ 6], S13, 0xa8304613); /* 7 */ - FF(b, c, d, a, x[ 7], S14, 0xfd469501); /* 8 */ - FF(a, b, c, d, x[ 8], S11, 0x698098d8); /* 9 */ - FF(d, a, b, c, x[ 9], S12, 0x8b44f7af); /* 10 */ - FF(c, d, a, b, x[10], S13, 0xffff5bb1); /* 11 */ - FF(b, c, d, a, x[11], S14, 0x895cd7be); /* 12 */ - FF(a, b, c, d, x[12], S11, 0x6b901122); /* 13 */ - FF(d, a, b, c, x[13], S12, 0xfd987193); /* 14 */ - FF(c, d, a, b, x[14], S13, 0xa679438e); /* 15 */ - FF(b, c, d, a, x[15], S14, 0x49b40821); /* 16 */ - - /* Round 2 */ - GG(a, b, c, d, x[ 1], S21, 0xf61e2562); /* 17 */ - GG(d, a, b, c, x[ 6], S22, 0xc040b340); /* 18 */ - GG(c, d, a, b, x[11], S23, 0x265e5a51); /* 19 */ - GG(b, c, d, a, x[ 0], S24, 0xe9b6c7aa); /* 20 */ - GG(a, b, c, d, x[ 5], S21, 0xd62f105d); /* 21 */ - GG(d, a, b, c, x[10], S22, 0x2441453); /* 22 */ - GG(c, d, a, b, x[15], S23, 0xd8a1e681); /* 23 */ - GG(b, c, d, a, x[ 4], S24, 0xe7d3fbc8); /* 24 */ - GG(a, b, c, d, x[ 9], S21, 0x21e1cde6); /* 25 */ - GG(d, a, b, c, x[14], S22, 0xc33707d6); /* 26 */ - GG(c, d, a, b, x[ 3], S23, 0xf4d50d87); /* 27 */ - GG(b, c, d, a, x[ 8], S24, 0x455a14ed); /* 28 */ - GG(a, b, c, d, x[13], S21, 0xa9e3e905); /* 29 */ - GG(d, a, b, c, x[ 2], S22, 0xfcefa3f8); /* 30 */ - GG(c, d, a, b, x[ 7], S23, 0x676f02d9); /* 31 */ - GG(b, c, d, a, x[12], S24, 0x8d2a4c8a); /* 32 */ - - /* Round 3 */ - HH(a, b, c, d, x[ 5], S31, 0xfffa3942); /* 33 */ - HH(d, a, b, c, x[ 8], S32, 0x8771f681); /* 34 */ - HH(c, d, a, b, x[11], S33, 0x6d9d6122); /* 35 */ - HH(b, c, d, a, x[14], S34, 0xfde5380c); /* 36 */ - HH(a, b, c, d, x[ 1], S31, 0xa4beea44); /* 37 */ - HH(d, a, b, c, x[ 4], S32, 0x4bdecfa9); /* 38 */ - HH(c, d, a, b, x[ 7], S33, 0xf6bb4b60); /* 39 */ - HH(b, c, d, a, x[10], S34, 0xbebfbc70); /* 40 */ - HH(a, b, c, d, x[13], S31, 0x289b7ec6); /* 41 */ - HH(d, a, b, c, x[ 0], S32, 0xeaa127fa); /* 42 */ - HH(c, d, a, b, x[ 3], S33, 0xd4ef3085); /* 43 */ - HH(b, c, d, a, x[ 6], S34, 0x4881d05); /* 44 */ - HH(a, b, c, d, x[ 9], S31, 0xd9d4d039); /* 45 */ - HH(d, a, b, c, x[12], S32, 0xe6db99e5); /* 46 */ - HH(c, d, a, b, x[15], S33, 0x1fa27cf8); /* 47 */ - HH(b, c, d, a, x[ 2], S34, 0xc4ac5665); /* 48 */ - - /* Round 4 */ - II(a, b, c, d, x[ 0], S41, 0xf4292244); /* 49 */ - II(d, a, b, c, x[ 7], S42, 0x432aff97); /* 50 */ - II(c, d, a, b, x[14], S43, 0xab9423a7); /* 51 */ - II(b, c, d, a, x[ 5], S44, 0xfc93a039); /* 52 */ - II(a, b, c, d, x[12], S41, 0x655b59c3); /* 53 */ - II(d, a, b, c, x[ 3], S42, 0x8f0ccc92); /* 54 */ - II(c, d, a, b, x[10], S43, 0xffeff47d); /* 55 */ - II(b, c, d, a, x[ 1], S44, 0x85845dd1); /* 56 */ - II(a, b, c, d, x[ 8], S41, 0x6fa87e4f); /* 57 */ - II(d, a, b, c, x[15], S42, 0xfe2ce6e0); /* 58 */ - II(c, d, a, b, x[ 6], S43, 0xa3014314); /* 59 */ - II(b, c, d, a, x[13], S44, 0x4e0811a1); /* 60 */ - II(a, b, c, d, x[ 4], S41, 0xf7537e82); /* 61 */ - II(d, a, b, c, x[11], S42, 0xbd3af235); /* 62 */ - II(c, d, a, b, x[ 2], S43, 0x2ad7d2bb); /* 63 */ - II(b, c, d, a, x[ 9], S44, 0xeb86d391); /* 64 */ - - state[0] += a; - state[1] += b; - state[2] += c; - state[3] += d; - - /* Zeroize sensitive information. */ - memset((uint8_t*) x, 0, sizeof (x)); -} - -/* Encodes input (uint32_t) into output (unsigned char). Assumes len is - a multiple of 4. */ -static void Encode(uint8_t *output, uint32_t *input, unsigned int len) -{ - unsigned int i, j; - - for (i = 0, j = 0; j < len; i++, j += 4) - { - output[j] = (uint8_t) (input[i] & 0xff); - output[j + 1] = (uint8_t) ((input[i] >> 8) & 0xff); - output[j + 2] = (uint8_t) ((input[i] >> 16) & 0xff); - output[j + 3] = (uint8_t) ((input[i] >> 24) & 0xff); - } -} - -/* Decodes input (unsigned char) into output (uint32_t). Assumes len is - a multiple of 4. */ -static void Decode(uint32_t *output, uint8_t *input, unsigned int len) -{ - unsigned int i, j; - - for (i = 0, j = 0; j < len; i++, j += 4) - output[i] = ((uint32_t) input[j]) | (((uint32_t) input[j + 1]) << 8) | - (((uint32_t) input[j + 2]) << 16) | (((uint32_t) input[j + 3]) << 24); -} diff --git a/legacy/app/bsmp/md5/md5.h b/legacy/app/bsmp/md5/md5.h deleted file mode 100644 index 1db068d..0000000 --- a/legacy/app/bsmp/md5/md5.h +++ /dev/null @@ -1,35 +0,0 @@ -/* MD5.H - header file for MD5C.C */ - -/* Copyright (C) 1991-2, RSA Data Security, Inc. Created 1991. All -rights reserved. - -License to copy and use this software is granted provided that it -is identified as the "RSA Data Security, Inc. MD5 Message-Digest -Algorithm" in all material mentioning or referencing this software -or this function. - -License is also granted to make and use derivative works provided -that such works are identified as "derived from the RSA Data -Security, Inc. MD5 Message-Digest Algorithm" in all material -mentioning or referencing the derived work. - -RSA Data Security, Inc. makes no representations concerning either -the merchantability of this software or the suitability of this -software for any particular purpose. It is provided "as is" -without express or implied warranty of any kind. - -These notices must be retained in any copies of any part of this -documentation and/or software. */ - -#include - -/* MD5 context. */ -typedef struct { - uint32_t state[4]; /* state (ABCD) */ - uint32_t count[2]; /* number of bits, modulo 2^64 (lsb first) */ - uint8_t buffer[64]; /* input buffer */ -} MD5_CTX; - -void MD5Init(MD5_CTX *); -void MD5Update(MD5_CTX *, uint8_t *, unsigned int); -void MD5Final(uint8_t [16], MD5_CTX *); diff --git a/legacy/app/bsmp/server.c b/legacy/app/bsmp/server.c deleted file mode 100644 index 8f4c14a..0000000 --- a/legacy/app/bsmp/server.c +++ /dev/null @@ -1,228 +0,0 @@ -#include "server.h" -#include "server_priv.h" -#include "bsmp_priv.h" - -#include -#include -#include - -#define SERVER_POOL_SIZE 1 - -struct -{ - struct bsmp_server list[SERVER_POOL_SIZE]; - unsigned int count; - unsigned int allocated; -}server_pool = { - .list = {}, - .count = 0, - .allocated = 0, -}; - -static int server_pool_index (struct bsmp_server *server) -{ - int i; - for(i = 0; i < SERVER_POOL_SIZE; ++i) - if(server == server_pool.list + i) - return i; - return -1; -} - -static void server_init (struct bsmp_server *server) -{ - memset(server, 0, sizeof(*server)); - - group_init(&server->groups.list[GROUP_ALL_ID], GROUP_ALL_ID); - group_init(&server->groups.list[GROUP_READ_ID], GROUP_READ_ID); - group_init(&server->groups.list[GROUP_WRITE_ID], GROUP_WRITE_ID); - - server->groups.count = GROUP_STANDARD_COUNT; -} - -bsmp_server_t *bsmp_server_new (void) -{ - struct bsmp_server *server = (struct bsmp_server*) malloc(sizeof(*server)); - - if(!server) - return NULL; - - server_init(server); - - return server; -} - -bsmp_server_t *bsmp_server_new_from_pool (void) -{ - if(server_pool.count == SERVER_POOL_SIZE) - return NULL; - - unsigned int i; - for(i = 0; server_pool.allocated & (1 << i); ++i); - - ++server_pool.count; - server_pool.allocated |= (1 << i); - - struct bsmp_server *server = &server_pool.list[i]; - - server_init(server); - - return server; -} - -enum bsmp_err bsmp_server_destroy (bsmp_server_t* server) -{ - if(!server) - return BSMP_ERR_PARAM_INVALID; - - int pool_index = server_pool_index(server); - - if(pool_index < 0) - free(server); - else if(server_pool.allocated & (1 << pool_index)) - { - --server_pool.count; - server_pool.allocated ^= 1 << pool_index; - } - else - return BSMP_ERR_PARAM_INVALID; - - return BSMP_SUCCESS; -} - -#define SERVER_REGISTER(elem, max) \ - do {\ - if(!server) return BSMP_ERR_PARAM_INVALID;\ - enum bsmp_err err;\ - if((err = elem##_check(elem))) return err;\ - if(server->elem##s.count >= max) return BSMP_ERR_OUT_OF_MEMORY;\ - unsigned int i;\ - for(i = 0; i < server->elem##s.count; ++i)\ - if(server->elem##s.list[i] == elem)\ - return BSMP_ERR_DUPLICATE;\ - server->elem##s.list[server->elem##s.count] = elem;\ - elem->info.id = server->elem##s.count++;\ - }while(0) - -enum bsmp_err bsmp_register_variable (bsmp_server_t *server, - struct bsmp_var *var) -{ - SERVER_REGISTER(var, BSMP_MAX_VARIABLES); - - // Add to the group containing all variables - group_add_var(&server->groups.list[GROUP_ALL_ID], var); - - // Add either to the WRITABLE or to the READ_ONLY group - if(var->info.writable) - group_add_var(&server->groups.list[GROUP_WRITE_ID], var); - else - group_add_var(&server->groups.list[GROUP_READ_ID], var); - - return BSMP_SUCCESS; -} - -enum bsmp_err bsmp_register_curve (bsmp_server_t *server, - struct bsmp_curve *curve) -{ - SERVER_REGISTER(curve, BSMP_MAX_CURVES); - return BSMP_SUCCESS; -} - -enum bsmp_err bsmp_register_function (bsmp_server_t *server, - struct bsmp_func *func) -{ - SERVER_REGISTER(func, BSMP_MAX_FUNCTIONS); - return BSMP_SUCCESS; -} - -enum bsmp_err bsmp_register_hook(bsmp_server_t* server, bsmp_hook_t hook) -{ - if(!server || !hook) - return BSMP_ERR_PARAM_INVALID; - - server->hook = hook; - - return BSMP_SUCCESS; -} - -struct raw_message -{ - uint8_t command_code; - uint8_t size[2]; - uint8_t payload[]; -}__attribute__((packed)); - -static command_function_t command[256] = -{ - [CMD_QUERY_VERSION] = query_version, - - // Variable's functions - [CMD_VAR_QUERY_LIST] = var_query_list, - [CMD_VAR_READ] = var_read, - [CMD_VAR_WRITE] = var_write, - [CMD_VAR_BIN_OP] = var_bin_op, - [CMD_VAR_WRITE_READ] = var_write_read, - - // Group's functions - [CMD_GROUP_QUERY_LIST] = group_query_list, - [CMD_GROUP_QUERY] = group_query, - [CMD_GROUP_READ] = group_read, - [CMD_GROUP_WRITE] = group_write, - [CMD_GROUP_BIN_OP] = group_bin_op, - [CMD_GROUP_CREATE] = group_create, - [CMD_GROUP_REMOVE_ALL] = group_remove_all, - - // Curve's functions - [CMD_CURVE_QUERY_LIST] = curve_query_list, - [CMD_CURVE_QUERY_CSUM] = curve_query_csum, - [CMD_CURVE_BLOCK_REQUEST] = curve_block_request, - [CMD_CURVE_BLOCK] = curve_block, - [CMD_CURVE_RECALC_CSUM] = curve_recalc_csum, - - // Function's functions - [CMD_FUNC_QUERY_LIST] = func_query_list, - [CMD_FUNC_EXECUTE] = func_execute -}; - -enum bsmp_err bsmp_process_packet (bsmp_server_t *server, - struct bsmp_raw_packet *request, - struct bsmp_raw_packet *response) -{ - if(!server || !request || !response) - return BSMP_ERR_PARAM_INVALID; - - // Interpret packet payload as a message - struct raw_message *recv_raw_msg = (struct raw_message *) request->data; - struct raw_message *send_raw_msg = (struct raw_message *) response->data; - - // Create proper messages from the raw messages - struct message recv_msg, send_msg; - - recv_msg.command_code = (enum command_code) recv_raw_msg->command_code; - recv_msg.payload = recv_raw_msg->payload; - recv_msg.payload_size = (recv_raw_msg->size[0] << 8)+recv_raw_msg->size[1]; - - send_msg.payload = send_raw_msg->payload; - - server->modified_list[0] = NULL; - - // Check inconsistency between the size of the received data and the size - // specified in the message header - if(request->len < BSMP_HEADER_SIZE || - request->len != recv_msg.payload_size + BSMP_HEADER_SIZE) - MESSAGE_SET_ANSWER(&send_msg, CMD_ERR_MALFORMED_MESSAGE); - // Check existence of the requested command - else if(!command[recv_msg.command_code]) - MESSAGE_SET_ANSWER(&send_msg, CMD_ERR_OP_NOT_SUPPORTED); - else - command[recv_msg.command_code](server, &recv_msg, &send_msg); - - send_raw_msg->command_code = send_msg.command_code; - - send_raw_msg->size[0] = send_msg.payload_size >> 8; - send_raw_msg->size[1] = send_msg.payload_size; - - response->len = send_msg.payload_size + BSMP_HEADER_SIZE; - - return BSMP_SUCCESS; -} - diff --git a/legacy/app/bsmp/server.h b/legacy/app/bsmp/server.h deleted file mode 100644 index 7049f38..0000000 --- a/legacy/app/bsmp/server.h +++ /dev/null @@ -1,191 +0,0 @@ -#ifndef BSMP_SERVER_H -#define BSMP_SERVER_H - -#include "bsmp.h" - -// Types - -// Handle to a server instance -typedef struct bsmp_server bsmp_server_t; - -// Hook function. Called before the values of a set of variables are read and -// after values of a set of variables are written. -enum bsmp_operation -{ - BSMP_OP_READ, // Read command arrived - BSMP_OP_WRITE, // Write command arrived -}; - -typedef void (*bsmp_hook_t) (enum bsmp_operation op, struct bsmp_var **list); - -// Structures - -// Represent a packet that either was received or is to be sent -struct bsmp_raw_packet -{ - uint8_t *data; - uint16_t len; -}; - -/** - * Allocate a new server instance, returning a handle to it. This instance - * should be deallocated with bsmp_destroy after its use. The instance returned - * is already initialized. The instance is allocated with malloc(). - * - * @return A handle to a server or NULL if there wasn't enough memory to do the - * allocation. - */ -bsmp_server_t *bsmp_server_new (void); - -/** - * Allocate a new server instance, returning a handle to it. This instance - * should be deallocated with bsmp_destroy after its use. The instance returned - * is already initialized. The instance is returned from a pool of instances - * allocated on the heap. - * - * @return A handle to a server or NULL if there wasn't enough memory to do the - * allocation. - */ -bsmp_server_t *bsmp_server_new_from_pool (void); - -/** - * Deallocate a server instance - * - * @param server [input] Handle to the instance to be deallocated. - * - * @return BSMP_SUCCESS or one of the following errors: - *
    - *
  • BSMP_ERR_PARAM_INVALID: server is a NULL pointer.
    • - *
- */ -enum bsmp_err bsmp_server_destroy (bsmp_server_t *server); - -/** - * Register a variable with a server instance. The memory pointed by the var - * parameter must remain valid throughout the entire lifespan of the server - * instance. The id field of the var parameter will be written by the BSMP lib. - * - * The fields writable, size and data of the var parameter must be filled - * correctly. - * - * The user field is untouched. - * - * @param server [input] Handle to the instance. - * @param var [input] Structure describing the variable to be registered. - * - * @return BSMP_SUCCESS or one of the following errors: - *
    - *
  • BSMP_ERR_PARAM_INVALID: server or var->data is a NULL pointer.
    • - *
  • BSMP_PARAM_OUT_OF_RANGE: var->size is less than 1 or greater than 127. - *
    • - *
- */ -enum bsmp_err bsmp_register_variable (bsmp_server_t *server, - struct bsmp_var *var); - -/** - * Register a curve with a BSMP instance. The memory pointed by the curve - * parameter must remain valid throughout the entire lifespan of the server - * instance. The id field of the curve parameter will be written by the BSMP - * lib. - * - * The fields writable, nblocks and read_block must be filled correctly. - * If writable is true, the field write_block must also be filled correctly. - * Otherwise, write_block must be NULL. - * - * The user field is untouched. - * - * @param server [input] Handle to the server instance. - * @param curve [input] Pointer to the curve to be registered. - * - * @return BSMP_SUCCESS or one of the following errors: - *
    - *
  • BSMP_ERR_PARAM_INVALID: either server or curve is a NULL pointer.
    • - *
  • BSMP_ERR_PARAM_INVALID: curve->info.nblocks less than - * BSMP_CURVE_MIN_BLOCKS or greater than - * BSMP_CURVE_MAX_BLOCKS.
    • - *
  • BSMP_ERR_PARAM_INVALID: curve->read_block is NULL.
    • - *
  • BSMP_ERR_PARAM_INVALID: curve->writable is true and curve->write_block - * is NULL.
    • - *
  • BSMP_ERR_PARAM_INVALID: curve->writable is false and curve->write_block - * is not NULL.
    • - *
- */ -enum bsmp_err bsmp_register_curve (bsmp_server_t *server, - struct bsmp_curve *curve); - -/** - * Register a function with a BSMP instance. The memory pointed by the func - * parameter must remain valid throughout the entire lifespan of the server - * instance. The info.id field of the func parameter will be written by the - * BSMP lib. - * - * The fields func_p, info.input_size and info.output_size must be filled - * correctly. info.input_size must be less than or equal to BSMP_FUNC_MAX_INPUT. - * Likewise, info.output_size must be less than or equal to - * BSMP_FUNC_MAS_OUTPUT. - * - * @param server [input] Handle to the server instance. - * @param func [input] Pointer to the function to be registered. - * - * @return BSMP_SUCCESS or one of the following errors: - *
    - *
  • BSMP_ERR_PARAM_INVALID: either server or func is a NULL pointer.
    • - *
  • BSMP_ERR_PARAM_INVALID: func->func_p is NULL.
    • - *
  • BSMP_ERR_PARAM_OUT_OF_RANGE: info.input_size is greater than - * BSMP_FUNC_MAX_INPUT. - *
  • BSMP_ERR_PARAM_OUT_OF_RANGE: info.output_size is greater than - * BSMP_FUNC_MAX_OUTPUT. - *
- */ -enum bsmp_err bsmp_register_function (bsmp_server_t *server, - struct bsmp_func *func); - -/** - * Register a function that will be called in two moments: - * - * 1. When a command that reads one or more variables arrives, the hook function - * is called right BEFORE reading the variables and putting the read values in - * the response message. - * - * 2. When a command that writes to one or more variables arrives, the hook - * function is called AFTER writing the values of the variables. - * - * Other commands don't call the hook function. It's not required to register a - * hook function. It's possible to deregister a previously registered hook - * function by simply passing a NULL pointer in the hook parameter. - * - * A hook function receives two parameters: the first one indicating the type - * of operation being performed (specified in enum bsmp_operation) and the - * second one containing the list of variables being affected by that operation. - * - * @param server [input] Handle to a BSMP instance. - * @param hook [input] Hook function - * - * @return BSMP_SUCCESS or one of the following errors: - *
    - *
  • BSMP_ERR_INVALID_PARAM: bsmp is a NULL pointer. - *
- */ -enum bsmp_err bsmp_register_hook (bsmp_server_t *server, bsmp_hook_t hook); - -/** - * Process a received message and prepare an answer. - * - * @param server [input] Handle to a server instance. - * @param request [input] The message to be processed. - * @param response [output] The answer to be sent - * - * @return BSMP_SUCCESS or one of the following errors: - *
    - *
  • SSLP_ERR_PARAM_INVALID: Either server, request, or response is - * a NULL pointer.
    • - *
- */ -enum bsmp_err bsmp_process_packet (bsmp_server_t *server, - struct bsmp_raw_packet *request, - struct bsmp_raw_packet *response); - -#endif - - diff --git a/legacy/app/bsmp/server_priv.c b/legacy/app/bsmp/server_priv.c deleted file mode 100644 index 895576e..0000000 --- a/legacy/app/bsmp/server_priv.c +++ /dev/null @@ -1,737 +0,0 @@ -#include "bsmp_priv.h" -#include "server_priv.h" -#include "server.h" -#include "md5/md5.h" - -#include -#include - -/* Check entities */ - -enum bsmp_err var_check (struct bsmp_var *var) -{ - if(!var) - return BSMP_ERR_PARAM_INVALID; - - // Check variable fields - if(var->info.size > BSMP_VAR_MAX_SIZE) - return BSMP_ERR_PARAM_OUT_OF_RANGE; - - if(!var->data) - return BSMP_ERR_PARAM_INVALID; - - return BSMP_SUCCESS; -} - -enum bsmp_err curve_check(struct bsmp_curve *curve) -{ - if(!curve) - return BSMP_ERR_PARAM_INVALID; - - if(curve->info.nblocks > BSMP_CURVE_MAX_BLOCKS) - return BSMP_ERR_PARAM_INVALID; - - if(curve->info.block_size > BSMP_CURVE_BLOCK_MAX_SIZE) - return BSMP_ERR_PARAM_INVALID; - - if(!curve->read_block) - return BSMP_ERR_PARAM_INVALID; - - if(curve->info.writable && !curve->write_block) - return BSMP_ERR_PARAM_INVALID; - - return BSMP_SUCCESS; -} - -enum bsmp_err func_check(struct bsmp_func *func) -{ - if(!func) - return BSMP_ERR_PARAM_INVALID; - - if(!func->func_p) - return BSMP_ERR_PARAM_INVALID; - - if(func->info.input_size > BSMP_FUNC_MAX_INPUT) - return BSMP_ERR_PARAM_OUT_OF_RANGE; - - if(func->info.output_size > BSMP_FUNC_MAX_OUTPUT) - return BSMP_ERR_PARAM_OUT_OF_RANGE; - - return BSMP_SUCCESS; -} - -/* Helper Group functions */ - -void group_init (struct bsmp_group *grp, uint8_t id) -{ - memset(grp, 0, sizeof(*grp)); - grp->id = id; - grp->writable = true; -} - -void group_add_var (struct bsmp_group *grp, struct bsmp_var *var) -{ - grp->vars.list[grp->vars.count++] = &var->info; - grp->size += var->info.size; - grp->writable &= var->info.writable; -} - -static void group_to_mod_list (bsmp_server_t *server, struct bsmp_group *grp) -{ - unsigned int i; - for(i = 0; i < grp->vars.count; ++i) - server->modified_list[i] = server->vars.list[grp->vars.list[i]->id]; - server->modified_list[i] = NULL; -} - -/* Version */ - -SERVER_CMD_FUNCTION (query_version) -{ - // Check payload size - if(recv_msg->payload_size != 0) - { - MESSAGE_SET_ANSWER(send_msg, CMD_ERR_INVALID_PAYLOAD_SIZE); - return; - } - - // Set answer's command_code and payload_size - MESSAGE_SET_ANSWER(send_msg, CMD_VERSION); - - send_msg->payload_size = 3; - send_msg->payload[0] = VERSION; - send_msg->payload[1] = SUBVERSION; - send_msg->payload[2] = REVISION; -} - -/* Variables */ - -SERVER_CMD_FUNCTION (var_query_list) -{ - // Payload must be zero - if(recv_msg->payload_size != 0) - MESSAGE_SET_ANSWER_RET(send_msg, CMD_ERR_INVALID_PAYLOAD_SIZE); - - // Set answer's command_code and payload_size - MESSAGE_SET_ANSWER(send_msg, CMD_VAR_LIST); - - // Variables are in order of their ID's - struct bsmp_var *var; - - // Add each variable to the response - unsigned int i; - for(i = 0; i < server->vars.count; ++i) - { - var = server->vars.list[i]; - send_msg->payload[i] = var->info.size & SIZE_MASK; - send_msg->payload[i] |= var->info.writable ? WRITABLE : READ_ONLY; - } - send_msg->payload_size = server->vars.count; -} - -SERVER_CMD_FUNCTION (var_read) -{ - // Payload must contain exactly one byte - if(recv_msg->payload_size != 1) - MESSAGE_SET_ANSWER_RET(send_msg, CMD_ERR_INVALID_PAYLOAD_SIZE); - - // Check ID - uint8_t var_id = recv_msg->payload[0]; - - if(var_id >= server->vars.count) - MESSAGE_SET_ANSWER_RET(send_msg, CMD_ERR_INVALID_ID); - - // Get desired variable - struct bsmp_var *var = server->vars.list[var_id]; - - if(server->hook) - { - server->modified_list[0] = var; - server->modified_list[1] = NULL; - server->hook(BSMP_OP_READ, server->modified_list); - } - - // Set answer - MESSAGE_SET_ANSWER(send_msg, CMD_VAR_VALUE); - send_msg->payload_size = var->info.size; - memcpy(send_msg->payload, var->data, var->info.size); -} - -SERVER_CMD_FUNCTION (var_write) -{ - // Payload must contain, at least, two bytes (ID + 1 byte of value) - if(recv_msg->payload_size < 2) - MESSAGE_SET_ANSWER_RET(send_msg, CMD_ERR_INVALID_PAYLOAD_SIZE); - - // Check ID - uint8_t var_id = recv_msg->payload[0]; - - if(var_id >= server->vars.count) - MESSAGE_SET_ANSWER_RET(send_msg, CMD_ERR_INVALID_ID); - - // Get desired var - struct bsmp_var *var = server->vars.list[var_id]; - - // Payload must contain, exactly 1 byte (ID) plus the Variable's size - if(recv_msg->payload_size != 1 + var->info.size) - MESSAGE_SET_ANSWER_RET(send_msg, CMD_ERR_INVALID_PAYLOAD_SIZE); - - // Check write permission - if(!var->info.writable) - MESSAGE_SET_ANSWER_RET(send_msg, CMD_ERR_READ_ONLY); - - // Check payload value - if(var->value_ok && !var->value_ok(var, recv_msg->payload + 1)) - MESSAGE_SET_ANSWER_RET(send_msg, CMD_ERR_INVALID_VALUE); - - // Everything is OK, perform operation - memcpy(var->data, recv_msg->payload + 1, var->info.size); - - // Call hook - if(server->hook) - { - server->modified_list[0] = var; - server->modified_list[1] = NULL; - server->hook(BSMP_OP_WRITE, server->modified_list); - } - - // Set answer code - MESSAGE_SET_ANSWER(send_msg, CMD_OK); -} - -SERVER_CMD_FUNCTION (var_write_read) -{ - // Payload must contain, at least, 3 bytes (2 ID's and 1 byte of the value) - if(recv_msg->payload_size < 3) - MESSAGE_SET_ANSWER_RET(send_msg, CMD_ERR_INVALID_PAYLOAD_SIZE); - - // Check ID - uint8_t var_wr_id = recv_msg->payload[0]; - uint8_t var_rd_id = recv_msg->payload[1]; - - if(var_wr_id >= server->vars.count || var_rd_id >= server->vars.count) - MESSAGE_SET_ANSWER_RET(send_msg, CMD_ERR_INVALID_ID); - - // Get desired vars - struct bsmp_var *var_wr = server->vars.list[var_wr_id]; - struct bsmp_var *var_rd = server->vars.list[var_rd_id]; - - // Check payload size - if(recv_msg->payload_size != 2 + var_wr->info.size) - MESSAGE_SET_ANSWER_RET(send_msg, CMD_ERR_INVALID_PAYLOAD_SIZE); - - // Check write permission - if(!var_wr->info.writable) - MESSAGE_SET_ANSWER_RET(send_msg, CMD_ERR_READ_ONLY); - - // Check payload value - if(var_wr->value_ok && !var_wr->value_ok(var_wr, recv_msg->payload + 2)) - MESSAGE_SET_ANSWER_RET(send_msg, CMD_ERR_INVALID_VALUE); - - // Everything is OK, perform WRITE operation - memcpy(var_wr->data, recv_msg->payload + 2, var_wr->info.size); - - // Call hooks - if(server->hook) - { - // Write hook - server->modified_list[0] = var_wr; - server->modified_list[1] = NULL; - server->hook(BSMP_OP_WRITE, server->modified_list); - - server->modified_list[0] = var_rd; - server->hook(BSMP_OP_READ, server->modified_list); - } - - // Now perform READ operation - MESSAGE_SET_ANSWER(send_msg, CMD_VAR_VALUE); - send_msg->payload_size = var_rd->info.size; - memcpy(send_msg->payload, var_rd->data, var_rd->info.size); -} - -SERVER_CMD_FUNCTION (var_bin_op) -{ - // Check if body has at least 3 bytes (ID + binary operation + 1 mask byte) - if(recv_msg->payload_size < 3) - MESSAGE_SET_ANSWER_RET(send_msg, CMD_ERR_INVALID_PAYLOAD_SIZE); - - // Check ID - uint8_t var_id = recv_msg->payload[0]; - - if(var_id >= server->vars.count) - MESSAGE_SET_ANSWER_RET(send_msg, CMD_ERR_INVALID_ID); - - // Get desired var - struct bsmp_var *var = server->vars.list[var_id]; - - // Get operation - unsigned char operation = recv_msg->payload[1]; - - // Check operation - if(!bin_op[operation]) - MESSAGE_SET_ANSWER_RET(send_msg, CMD_ERR_OP_NOT_SUPPORTED); - - // Check payload size - if(recv_msg->payload_size != 2 + var->info.size) - MESSAGE_SET_ANSWER_RET(send_msg, CMD_ERR_INVALID_PAYLOAD_SIZE); - - // Check write permission - if(!var->info.writable) - MESSAGE_SET_ANSWER_RET(send_msg, CMD_ERR_READ_ONLY); - - // Everything is OK, perform operation - bin_op[operation](var->data, recv_msg->payload + 2, var->info.size); - - // Call hook - if(server->hook) - { - server->modified_list[0] = var; - server->modified_list[1] = NULL; - server->hook(BSMP_OP_WRITE, server->modified_list); - } - - // Set answer code - MESSAGE_SET_ANSWER(send_msg, CMD_OK); -} - -/* Groups */ - -SERVER_CMD_FUNCTION (group_query_list) -{ - // Payload size must be zero - if(recv_msg->payload_size != 0) - MESSAGE_SET_ANSWER_RET(send_msg, CMD_ERR_INVALID_PAYLOAD_SIZE); - - // Set answer's command_code and payload_size - MESSAGE_SET_ANSWER(send_msg, CMD_GROUP_LIST); - - // Add each group to the response - struct bsmp_group *grp; - - unsigned int i; - for(i = 0; i < server->groups.count; ++i) - { - grp = &server->groups.list[i]; - send_msg->payload[i] = grp->writable ? WRITABLE : READ_ONLY; - send_msg->payload[i] += grp->vars.count; - } - send_msg->payload_size = server->groups.count; -} - -SERVER_CMD_FUNCTION (group_query) -{ - // Payload size must be 1 (ID) - if(recv_msg->payload_size != 1) - MESSAGE_SET_ANSWER_RET(send_msg, CMD_ERR_INVALID_PAYLOAD_SIZE); - - // Set answer code - MESSAGE_SET_ANSWER(send_msg, CMD_GROUP); - - // Check ID - uint8_t group_id = recv_msg->payload[0]; - if(group_id >= server->groups.count) - MESSAGE_SET_ANSWER_RET(send_msg, CMD_ERR_INVALID_ID); - - // Get desired group - struct bsmp_group *grp = &server->groups.list[group_id]; - - unsigned int i; - for(i = 0; i < grp->vars.count; ++i) - send_msg->payload[i] = grp->vars.list[i]->id; - - send_msg->payload_size = grp->vars.count; -} - -SERVER_CMD_FUNCTION (group_read) -{ - // Payload size must be 1 (ID) - if(recv_msg->payload_size != 1) - MESSAGE_SET_ANSWER_RET(send_msg, CMD_ERR_INVALID_PAYLOAD_SIZE); - - // Check group ID - uint8_t group_id = recv_msg->payload[0]; - - if(group_id >= server->groups.count) - MESSAGE_SET_ANSWER_RET(send_msg, CMD_ERR_INVALID_ID); - - // Get desired group - struct bsmp_group *grp = &server->groups.list[group_id]; - - // Call hook - if(server->hook) - { - group_to_mod_list(server, grp); - server->hook(BSMP_OP_READ, server->modified_list); - } - - // Iterate over group's variables - MESSAGE_SET_ANSWER(send_msg, CMD_GROUP_VALUES); - - struct bsmp_var *var; - unsigned int i; - uint8_t *payloadp = send_msg->payload; - for(i = 0; i < grp->vars.count; ++i) - { - var = server->vars.list[grp->vars.list[i]->id]; - memcpy(payloadp, var->data, var->info.size); - payloadp += var->info.size; - } - send_msg->payload_size = grp->size; -} - -SERVER_CMD_FUNCTION (group_write) -{ - // Check if body has at least 2 bytes (ID + 1 byte of data) - if(recv_msg->payload_size < 2) - MESSAGE_SET_ANSWER_RET(send_msg, CMD_ERR_INVALID_PAYLOAD_SIZE); - - // Check ID - uint8_t group_id = recv_msg->payload[0]; - - if(group_id >= server->groups.count) - MESSAGE_SET_ANSWER_RET(send_msg, CMD_ERR_INVALID_ID); - - // Get desired group - struct bsmp_group *grp = &server->groups.list[group_id]; - - // Check payload size - if(recv_msg->payload_size != 1 + grp->size) - MESSAGE_SET_ANSWER_RET(send_msg, CMD_ERR_INVALID_PAYLOAD_SIZE); - - // Check write permission - if(!grp->writable) - MESSAGE_SET_ANSWER_RET(send_msg, CMD_ERR_READ_ONLY); - - // Everything is OK, iterate - struct bsmp_var *var; - uint8_t *payloadp = recv_msg->payload + 1; - unsigned int i; - bool check_failed = false; - - for(i = 0; i < grp->vars.count; ++i) - { - var = server->vars.list[grp->vars.list[i]->id]; - - // Check payload value - if(var->value_ok && !var->value_ok(var, payloadp)) - check_failed = true; - else - memcpy(var->data, payloadp, var->info.size); - payloadp += var->info.size; - } - - // Call hook - if(server->hook) - { - group_to_mod_list(server, grp); - server->hook(BSMP_OP_WRITE, server->modified_list); - } - - MESSAGE_SET_ANSWER(send_msg, check_failed ? CMD_ERR_INVALID_VALUE : CMD_OK); -} - -SERVER_CMD_FUNCTION (group_bin_op) -{ - // Check if body has at least two bytes (ID + binary operation) - if(recv_msg->payload_size < 2) - MESSAGE_SET_ANSWER_RET(send_msg, CMD_ERR_INVALID_PAYLOAD_SIZE); - - // Check ID - uint8_t group_id = recv_msg->payload[0]; - - if(group_id >= server->groups.count) - MESSAGE_SET_ANSWER_RET(send_msg, CMD_ERR_INVALID_ID); - - // Get desired group - struct bsmp_group *grp = &server->groups.list[group_id]; - - // Get operation - unsigned char operation = recv_msg->payload[1]; - - // Check operation - if(!bin_op[operation]) - MESSAGE_SET_ANSWER_RET(send_msg, CMD_ERR_OP_NOT_SUPPORTED); - - // Check payload size - if(recv_msg->payload_size != 2 + grp->size) - MESSAGE_SET_ANSWER_RET(send_msg, CMD_ERR_INVALID_PAYLOAD_SIZE); - - // Check write permission - if(!grp->writable) - MESSAGE_SET_ANSWER_RET(send_msg, CMD_ERR_READ_ONLY); - - // Everything is OK, iterate - struct bsmp_var *var; - uint8_t *payloadp = recv_msg->payload + 2; - - unsigned int i; - for(i = 0; i < grp->vars.count; ++i) - { - var = server->vars.list[grp->vars.list[i]->id]; - bin_op[operation](var->data, payloadp, var->info.size); - payloadp += var->info.size; - } - - // Call hook - if(server->hook) - { - group_to_mod_list(server, grp); - server->hook(BSMP_OP_WRITE, server->modified_list); - } - - MESSAGE_SET_ANSWER(send_msg, CMD_OK); -} - -SERVER_CMD_FUNCTION (group_create) -{ - // Check if there's at least one variable to put on the group - if(recv_msg->payload_size < 1 || - recv_msg->payload_size > server->vars.count) - MESSAGE_SET_ANSWER_RET(send_msg, CMD_ERR_INVALID_PAYLOAD_SIZE); - - // Check if there's available space for the new group - if(server->groups.count == BSMP_MAX_GROUPS) - MESSAGE_SET_ANSWER_RET(send_msg, CMD_ERR_INSUFFICIENT_MEMORY); - - struct bsmp_group *grp = &server->groups.list[server->groups.count]; - - // Initialize group id - group_init(grp, server->groups.count); - - // Populate group - int i; - for(i = 0; i < recv_msg->payload_size; ++i) - { - // Check var ID - uint8_t var_id = recv_msg->payload[i]; - - if(var_id >= server->vars.count) - MESSAGE_SET_ANSWER_RET(send_msg, CMD_ERR_INVALID_ID); - - if(i && (var_id <= grp->vars.list[i-1]->id)) - MESSAGE_SET_ANSWER_RET(send_msg, CMD_ERR_INVALID_ID); - - // Add var by ID - group_add_var(grp, server->vars.list[var_id]); - } - - // Group created - ++server->groups.count; - - // Prepare answer - MESSAGE_SET_ANSWER(send_msg, CMD_OK); -} - -SERVER_CMD_FUNCTION (group_remove_all) -{ - // Payload size must be zero - if(recv_msg->payload_size != 0) - MESSAGE_SET_ANSWER_RET(send_msg, CMD_ERR_INVALID_PAYLOAD_SIZE); - - server->groups.count = GROUP_STANDARD_COUNT; - MESSAGE_SET_ANSWER(send_msg, CMD_OK); -} - -/* Curves */ - -SERVER_CMD_FUNCTION (curve_query_list) -{ - // Payload size must be zero - if(recv_msg->payload_size != 0) - MESSAGE_SET_ANSWER_RET(send_msg, CMD_ERR_INVALID_PAYLOAD_SIZE); - - MESSAGE_SET_ANSWER(send_msg, CMD_CURVE_LIST); - - struct bsmp_curve_info *curve; - unsigned int i; - uint8_t *payloadp = send_msg->payload; - - for(i = 0; i < server->curves.count; ++i) - { - curve = &server->curves.list[i]->info; - - *(payloadp++) = curve->writable; - *(payloadp++) = curve->block_size >> 8; - *(payloadp++) = curve->block_size; - *(payloadp++) = curve->nblocks >> 8; - *(payloadp++) = curve->nblocks; - } - - send_msg->payload_size = server->curves.count*BSMP_CURVE_LIST_INFO; -} - -SERVER_CMD_FUNCTION (curve_query_csum) -{ - // Check payload size - if(recv_msg->payload_size != 1) - MESSAGE_SET_ANSWER_RET(send_msg, CMD_ERR_INVALID_PAYLOAD_SIZE); - - uint8_t curve_id = recv_msg->payload[0]; - - if(curve_id >= server->curves.count) - MESSAGE_SET_ANSWER_RET(send_msg, CMD_ERR_INVALID_ID); - - struct bsmp_curve *curve = server->curves.list[curve_id]; - - MESSAGE_SET_ANSWER(send_msg, CMD_CURVE_CSUM); - memcpy(send_msg->payload, curve->info.checksum, BSMP_CURVE_CSUM_SIZE); - send_msg->payload_size = BSMP_CURVE_CSUM_SIZE; -} - -SERVER_CMD_FUNCTION (curve_block_request) -{ - // Payload size must be equal to BSMP_CURVE_BLOCK_INFO - if(recv_msg->payload_size != BSMP_CURVE_BLOCK_INFO) - MESSAGE_SET_ANSWER_RET(send_msg, CMD_ERR_INVALID_PAYLOAD_SIZE); - - // Check curve ID - uint8_t curve_id = recv_msg->payload[0]; - - if(curve_id >= server->curves.count) - MESSAGE_SET_ANSWER_RET(send_msg, CMD_ERR_INVALID_ID); - - // Get curve - struct bsmp_curve *curve = server->curves.list[curve_id]; - - uint16_t block_offset = (recv_msg->payload[1] << 8) + recv_msg->payload[2]; - - if(block_offset >= curve->info.nblocks) - MESSAGE_SET_ANSWER_RET(send_msg, CMD_ERR_INVALID_VALUE); - - MESSAGE_SET_ANSWER(send_msg, CMD_CURVE_BLOCK); - send_msg->payload[0] = recv_msg->payload[0]; // Curve ID - send_msg->payload[1] = recv_msg->payload[1]; // Offset (most sig.) - send_msg->payload[2] = recv_msg->payload[2]; // Offset (less sig.) - - curve->read_block(curve, block_offset, - send_msg->payload + BSMP_CURVE_BLOCK_INFO, - &send_msg->payload_size); - - send_msg->payload_size += BSMP_CURVE_BLOCK_INFO; -} - -SERVER_CMD_FUNCTION (curve_block) -{ - // Payload must contain, at least, 4 bytes (1 for ID, 2 for offset, 1 for - // data) - if(recv_msg->payload_size < BSMP_CURVE_BLOCK_INFO + 1) - MESSAGE_SET_ANSWER_RET(send_msg, CMD_ERR_INVALID_PAYLOAD_SIZE); - - // Check curve ID - uint8_t curve_id = recv_msg->payload[0]; - - if(curve_id >= server->curves.count) - MESSAGE_SET_ANSWER_RET(send_msg, CMD_ERR_INVALID_ID); - - // Get curve - struct bsmp_curve *curve = server->curves.list[curve_id]; - - // Check block size - if(recv_msg->payload_size > curve->info.block_size + BSMP_CURVE_BLOCK_INFO) - MESSAGE_SET_ANSWER_RET(send_msg, CMD_ERR_INVALID_PAYLOAD_SIZE); - - // Check offset - uint16_t block_offset = (recv_msg->payload[1] << 8) + recv_msg->payload[2]; - if(block_offset >= curve->info.nblocks) - MESSAGE_SET_ANSWER_RET(send_msg, CMD_ERR_INVALID_VALUE); - - // Everything ok, write block - curve->write_block(curve, block_offset, - recv_msg->payload + BSMP_CURVE_BLOCK_INFO, - recv_msg->payload_size - BSMP_CURVE_BLOCK_INFO); - - memset(curve->info.checksum, 0, sizeof(curve->info.checksum)); - MESSAGE_SET_ANSWER(send_msg, CMD_OK); -} - -SERVER_CMD_FUNCTION (curve_recalc_csum) -{ - // Payload must contain Curve ID only - if(recv_msg->payload_size != 1) - MESSAGE_SET_ANSWER_RET(send_msg, CMD_ERR_INVALID_PAYLOAD_SIZE); - - // Check curve ID - uint8_t curve_id = recv_msg->payload[0]; - - if(curve_id >= server->curves.count) - MESSAGE_SET_ANSWER_RET(send_msg, CMD_ERR_INVALID_ID); - - // Get curve - struct bsmp_curve *curve = server->curves.list[curve_id]; - - // Calculate checksum (this might take a while) - uint8_t block[curve->info.block_size]; - MD5_CTX md5ctx; - - MD5Init(&md5ctx); - - unsigned int i; - for(i = 0; i < curve->info.nblocks; ++i) - { - uint16_t read_bytes = 0; - curve->read_block(curve, (uint16_t)i, block, &read_bytes); - MD5Update(&md5ctx, block, read_bytes); - } - MD5Final(curve->info.checksum, &md5ctx); - - MESSAGE_SET_ANSWER(send_msg, CMD_CURVE_CSUM); - memcpy(send_msg->payload, curve->info.checksum, BSMP_CURVE_CSUM_SIZE); - send_msg->payload_size = BSMP_CURVE_CSUM_SIZE; -} - -/* Functions */ - -SERVER_CMD_FUNCTION (func_query_list) -{ - // Check payload size - if(recv_msg->payload_size != 0) - MESSAGE_SET_ANSWER_RET(send_msg, CMD_ERR_INVALID_PAYLOAD_SIZE); - - MESSAGE_SET_ANSWER(send_msg, CMD_FUNC_LIST); - - struct bsmp_func_info *func_info; - unsigned int i; - for(i = 0; i < server->funcs.count; ++i) - { - func_info = &server->funcs.list[i]->info; - - send_msg->payload[i] = (func_info->input_size << 4) | - (func_info->output_size & 0x0F); - } - - send_msg->payload_size = server->funcs.count; -} - -SERVER_CMD_FUNCTION (func_execute) -{ - if(!recv_msg->payload_size) - MESSAGE_SET_ANSWER_RET(send_msg, CMD_ERR_INVALID_PAYLOAD_SIZE); - - uint8_t func_id = recv_msg->payload[0]; - - if(func_id >= server->funcs.count) - MESSAGE_SET_ANSWER_RET(send_msg, CMD_ERR_INVALID_ID); - - struct bsmp_func *func = server->funcs.list[func_id]; - - if(recv_msg->payload_size != 1 + func->info.input_size) - MESSAGE_SET_ANSWER_RET(send_msg, CMD_ERR_INVALID_PAYLOAD_SIZE); - - uint8_t ret; - - ret = func->func_p(&recv_msg->payload[1], &send_msg->payload[0]); - - if(ret) - { - MESSAGE_SET_ANSWER(send_msg, CMD_FUNC_ERROR); - send_msg->payload[0] = ret; - send_msg->payload_size = 1; - } - else - { - MESSAGE_SET_ANSWER(send_msg, CMD_FUNC_RETURN); - send_msg->payload_size = func->info.output_size; - } -} - - diff --git a/legacy/app/bsmp/server_priv.h b/legacy/app/bsmp/server_priv.h deleted file mode 100644 index 96da58f..0000000 --- a/legacy/app/bsmp/server_priv.h +++ /dev/null @@ -1,84 +0,0 @@ -#ifndef BSMP_SERVER_PRIV_H -#define BSMP_SERVER_PRIV_H - -#include -#include "bsmp.h" -#include "server.h" - -#define VERSION 2 -#define SUBVERSION 0 -#define REVISION 0 // unused - -#define MESSAGE_SET_ANSWER(msg, code)\ - do {\ - (msg)->command_code = (code);\ - (msg)->payload_size = 0;\ - }while(0) - -#define MESSAGE_SET_ANSWER_RET(msg, code)\ - do {\ - (msg)->command_code = (code);\ - (msg)->payload_size = 0;\ - return;\ - }while(0) - -struct message -{ - uint8_t command_code; - uint16_t payload_size; - uint8_t *payload; -}; - -struct generic_list -{ - uint32_t count; - void *list[]; -}; - -#define SERVER_CMD_FUNCTION(name) \ - void name (bsmp_server_t *server, struct message *recv_msg, \ - struct message *send_msg) - -typedef SERVER_CMD_FUNCTION((*command_function_t)); - -struct bsmp_server -{ - struct bsmp_var_ptr_list vars; - struct bsmp_group_list groups; - struct bsmp_curve_ptr_list curves; - struct bsmp_func_ptr_list funcs; - - struct bsmp_var *modified_list[BSMP_MAX_VARIABLES+1]; - bsmp_hook_t hook; -}; - -enum bsmp_err var_check (struct bsmp_var *var); -enum bsmp_err curve_check (struct bsmp_curve *curve); -enum bsmp_err func_check (struct bsmp_func *func); - -void group_init (struct bsmp_group *grp, uint8_t id); -void group_add_var (struct bsmp_group *grp, struct bsmp_var *var); - -SERVER_CMD_FUNCTION (query_version); -SERVER_CMD_FUNCTION (var_query_list); -SERVER_CMD_FUNCTION (var_read); -SERVER_CMD_FUNCTION (var_write); -SERVER_CMD_FUNCTION (var_write_read); -SERVER_CMD_FUNCTION (var_bin_op); -SERVER_CMD_FUNCTION (group_query_list); -SERVER_CMD_FUNCTION (group_query); -SERVER_CMD_FUNCTION (group_read); -SERVER_CMD_FUNCTION (group_write); -SERVER_CMD_FUNCTION (group_bin_op); -SERVER_CMD_FUNCTION (group_create); -SERVER_CMD_FUNCTION (group_remove_all); -SERVER_CMD_FUNCTION (curve_query_list); -SERVER_CMD_FUNCTION (curve_query_csum); -SERVER_CMD_FUNCTION (curve_block_request); -SERVER_CMD_FUNCTION (curve_block); -SERVER_CMD_FUNCTION (curve_recalc_csum); -SERVER_CMD_FUNCTION (func_query_list); -SERVER_CMD_FUNCTION (func_execute); - -#endif - diff --git a/legacy/app/cli.cpp b/legacy/app/cli.cpp deleted file mode 100644 index 473d037..0000000 --- a/legacy/app/cli.cpp +++ /dev/null @@ -1,171 +0,0 @@ -/* Serial command interface listens to inbound serial interupts - saves the characters as they arrive and places a pointer to - the last complete command in the last_cmd array and calls - user callback when supplied. Can support simutaneous - routing of input from multiple SIO ports. It considers - \n or \r as command terminators The client is responsible - to parse the command furhter if needed. - - Intended use is for caller to periodically check for - new commands and execute the last one found. Or caller - can setup a callback so when a complete command which - must be at least 1 character long between \n or \r - characters. - - *** - * By Joseph Ellsworth CTO of A2WH - * Take a look at A2WH.com Producing Water from Air using Solar Energy - * March-2016 License: https://developer.mbed.org/handbook/MIT-Licence - * Please contact us http://a2wh.com for help with custom design projects. - *** -*/ - -#include "cli.h" -#include "ctype.h" - -struct SCMD *sc_listeners[SCMD_MAX_LISTENERS]; // set up to support upto 10 listeners - -// Add a listener to queue for processing -// so it receives interupts from the Serial -// IO in wrk->sio -int sc_add_listener(struct SCMD *wrk) { - short ndx; - for (ndx=0; ndx < SCMD_MAX_LISTENERS; ndx++) { - if (sc_listeners[ndx] == wrk) { - return ndx; // listener already present - } - if (sc_listeners[ndx] == NULL) { - sc_listeners[ndx] = wrk; // take available slot - return ndx; - } - } - return SCMD_TOO_MANY_LISTENER; -} - -// Removes listener from queue and frees up it's -// memory. After calling this the wrk pointer -// will no longer be valid. Returns the index -// in queue where it found the listener or -// SCMD_LISTENER_NOT_FOUND if it was not found -// in queue. -int sc_delete_listener(struct SCMD *wrk) { - short ndx; - for (ndx=0; ndx < SCMD_MAX_LISTENERS; ndx++) { - if (sc_listeners[ndx] == wrk) { - sc_listeners[ndx] = NULL; - free(wrk); - return ndx; // listener already present - } - } - free(wrk); - return SCMD_LISTENER_NOT_FOUND; -} - - -// returns the index in queue where the wrk -// listener is found or SCMD_LISTENER_NOT_FOUND -// if not present in the queue. -int sc_listener_ndx(struct SCMD *wrk) { - short ndx; - for (ndx=0; ndx < SCMD_MAX_LISTENERS; ndx++) { - if (sc_listeners[ndx] == wrk) { - return ndx; // listener already present - } - } - return SCMD_LISTENER_NOT_FOUND; -} - - -// constuct a new listener for the specified -// serial IO and add it to the listen queue -// to read inbound data on that port. -// callback extra is a extra pointer to allow recievers -// to rebuild state as needed. They are expected -// to cast it to something useful -struct SCMD *scMake(RawSerial *sio, void (*callback)(char *, void *), void *callbackExtra) { - struct SCMD *sc = (struct SCMD *) malloc(sizeof(struct SCMD)); - sc->sio = sio; - memset(sc->buff,SCMD_MAX_CMD_LEN+1,0); - sc->callback = callback; - sc->callbackExtra = callbackExtra; - sc_add_listener(sc); - sc->sio->attach(&sc_rx_interrupt, RawSerial::RxIrq); - sc->in_ndx = 0; - return sc; -} - - -// process any inbound characters available -// in the uart buffer for the Serial device -// associated with wrk->sio. Also detects -// end of command and call the command -// processor callback. -void sc_rx_process(struct SCMD *wrk) { - // Loop just in case more than one character is in UART's receive FIFO buffer - // Stop if buffer full - - while ((wrk->sio->readable())) { - char cin = wrk->sio->getc(); - - switch (cin) { - - /* Carriage Return or Line Feed (CRLF) */ - case 10: - case 13: - if (wrk->in_ndx > 0) { - // commands must be at least 1 byte long - wrk->buff[wrk->in_ndx] = 0; // add terminating null - wrk->callback(wrk->buff, wrk->callbackExtra); - } - wrk->in_ndx = 0; // reset for next cycle; - wrk->buff[0] = 0; // add null terminator - break; - - /* Backspace */ - case 8: - /* Print a space over the last char and rewind the cursor */ - wrk->sio->putc(cin); - wrk->sio->putc(' '); - wrk->sio->putc(cin); - if ( wrk->in_ndx > 0 ) { - wrk->in_ndx--; - } - wrk->buff[wrk->in_ndx] = 0; - - break; - - default: - /* Check if input char is printable (valid) */ - if (!isprint(cin)) { - break; - } - /* Echo back */ - wrk->sio->putc(cin); - /* Add character to the buffer */ - wrk->buff[wrk->in_ndx] = cin; - /* Add null terminator just in case */ - wrk->buff[wrk->in_ndx + 1] = 0; - wrk->in_ndx++; - - if (wrk->in_ndx >= SCMD_MAX_CMD_LEN) { - /* Buffer is full so treat as command */ - wrk->callback(wrk->buff, wrk->callbackExtra); - wrk->buff[0] = 0; - wrk->in_ndx = 0; - } - break; - } - } -} - -// Process all characters available in all the -// uart buffers for our listeners -void sc_rx_interrupt() { - int ndx; - for (ndx=0; ndx < SCMD_MAX_LISTENERS; ndx++) { - if (sc_listeners[ndx] != NULL) { - sc_rx_process(sc_listeners[ndx]); - } - } - return; -} diff --git a/legacy/app/cli.h b/legacy/app/cli.h deleted file mode 100644 index f000d51..0000000 --- a/legacy/app/cli.h +++ /dev/null @@ -1,194 +0,0 @@ -/* Serial command interface listens to inbound serial interupts - saves the characters as they arrive and places a pointer to - the last complete command in the last_cmd array and calls - user callback when supplied. Can support simutaneous - routing of input from multiple SIO ports. It considers - \n or \r as command terminators The client is responsible - to parse the command furhter if needed. - - Intended use is for caller to periodically check for - new commands and execute the last one found. Or caller - can setup a callback so when a complete command which - must be at least 1 character long between \n or \r - characters. - - *** - * By Joseph Ellsworth CTO of A2WH - * Take a look at A2WH.com Producing Water from Air using Solar Energy - * March-2016 License: https://developer.mbed.org/handbook/MIT-Licence - * Please contact us http://a2wh.com for help with custom design projects. - *** - - Sample Use Example: https://developer.mbed.org/users/joeata2wh/code/xj-multi-serial-command-listener-example/ - - #include "mbed.h" - #include "multi-serial-command-listener.h" - - Serial pc(USBTX, USBRX); - char myCommand[SCMD_MAX_CMD_LEN+1]; - - - void commandCallback(char *cmdIn, void *extraContext) { - strcpy(myCommand, cmdIn); - // all our commands will be recieved async in commandCallback - // we don't want to do time consuming things since it could - // block the reader and allow the uart to overflow so we simply - // copy it out in the callback and then process it latter. - - // See data_log one of dependants of this library for example - // of using *extraContext - } - - int main() { - pc.baud(9600); - pc.printf("Demo multi-serial-command-listener\r\n"); - - // Instantiate our command processor for the - // USB serial line. - struct SCMD *cmdProc = scMake(&pc, commandCallback, NULL) ; - - while(1) { - if (myCommand[0] != 0) { - pc.printf("Command Recieved =%s\r\n", myCommand); - myCommand[0] = 0; // clear until we recieve the next one - } - wait(0.05); - } - } - - - ** Basic Therory of Operation ** - The operation is the system will append new characters - to the buffer until it hits the end. Whenever it sees - a \r or \n will insert a \000 (null) so the previous - characters can be used safely in strcpy. - - It will then set up a null terminator and call - the user specified callback. - - To minimize risk of invalid data it is recomended the - caller copies the last_cmd to local buffer using the - sc_last_cmd_copy(char *dest) which disables interupts - performs the copy and then re-enables the interupts. - Otherwise a new character inbound could cause the - command data to change out from under the user. - - If the buffer fills up with more than SC_MAX_CMD_LEN - characters what is already present will be treated - as if it had encountered a \r or \n. - - A cmd must contain at least 1 charcter or it will - be ignored. - - ** Multiple Listeners ** - The system will allow upto 10 serial listeners - to each be processing new character. It will - automatically multi-plex between these listeners. - as needed. Each listner can have it's own cmd - callback. - - ** Known limitations ** - # If data arrives fast enough we could have sufficient - data in uart buffer to contain multiple commands. In - that instnace it is possible that commands before - the last command could be over-written before - calling code can process them. - - # Can have SCMD_MAX_LISTENERS and no current report - if new listener overflow is provied but it can be - checked with sc_listener_ndx() which will return the - index of the listener in queue or SCMD_LISTENER_NOT_FOUND - - # it takes some time to multi-plex across the listeners - and check each one for a new character. Under very fast - connection speeds it is possible that arriving data - could overflow the uart buffer before we can copy the - data out. - - # There is no provision to detect the same Serial - connection being used by more than one command - listener. This is a problem because the first - one in the listener queue will get all the data. - - # No current detach processed for listener in - sc_delete_listener which could increase interupt - callback overhead. Need to research what happens - with multiple attach calls. - - # Consumes at least SCMD_MAX_CMD_LEN memory one for - inbound buffer. - - ** References ** - https://developer.mbed.org/cookbook/Serial-Interrupts - - NOTE: I am using a struct instead of a class here - because I may need to port to PSoC in near future - and it is unclear when they will get full C++. - - ** TODO ** - Modify the callbacks so they are queued for a timer - that sends the actual callback to the command processor - rather than blocking the uart read loop. - - Separate into .h, .c files. -*/ - -#ifndef serial_command_H -#define serial_command_H - -#include "mbed.h" - -#define SCMD_MAX_LISTENERS 1 -#define SCMD_MAX_CMD_LEN 30 -#define SCMD_TOO_MANY_LISTENER -2 -#define SCMD_LISTENER_NOT_FOUND -1 - -struct SCMD { - RawSerial *sio; - char buff[SCMD_MAX_CMD_LEN+1]; - short in_ndx; - char last_char; - void *callbackExtra; - void (*callback)(char *, void *); - -}; - -// Add a listener to queue for processing -// so it receives interupts from the Serial -// IO in wrk->sio -int sc_add_listener(struct SCMD *wrk); - -// Removes listener from queue and frees up it's -// memory. After calling this the wrk pointer -// will no longer be valid. Returns the index -// in queue where it found the listener or -// SCMD_LISTENER_NOT_FOUND if it was not found -// in queue. -int sc_delete_listener(struct SCMD *wrk); - -// returns the index in queue where the wrk -// listener is found or SCMD_LISTENER_NOT_FOUND -// if not present in the queue. -int sc_listener_ndx(struct SCMD *wrk); - - -// constuct a new listener for the specified -// serial IO and add it to the listen queue -// to read inbound data on that port. -// callback extra is a extra pointer to allow recievers -// to rebuild state as needed. They are expected -// to cast it to something useful -struct SCMD *scMake(RawSerial *sio, void (*callback)(char *, void *), void *callbackExtra); - -// process any inbound characters available -// in the uart buffer for the Serial device -// associated with wrk->sio. Also detects -// end of command and call the command -// processor callback. -void sc_rx_process(struct SCMD *wrk); - -// Process all characters available in all the -// uart buffers for our listeners -void sc_rx_interrupt(); - -#endif diff --git a/legacy/app/ethernet.cpp b/legacy/app/ethernet.cpp deleted file mode 100644 index ad38f8b..0000000 --- a/legacy/app/ethernet.cpp +++ /dev/null @@ -1,276 +0,0 @@ -#if 0 -/* Ethernet PLL */ -I2C pll_i2c(P0_27, P0_28); -CDCE906 pll(pll_i2c, 0b11010010); - -RFFEServer::RFFEServer() -{ - -} - -void RFFEServer::eth_init() -{ - _pll.cfg_eth(); - ThisThread::sleep_for(100); - - if (_addressing == DHCP) { - _net.set_dhcp(true); - } else if (_addressing == FIX_IP) { - _net.set_network(IP_Addr,Mask_Addr,Gateway_Addr); - } -} - -void RFFEServer::eth_connect() -{ - int err; - - printf("Trying to bring up ethernet connection...\r\n"); - - /* Blocking connection */ - do { - err = _net.connect(); - - if (!_cable_status.link()) { - printf(MODULE_STR" Cable disconnected!\r\n"); - } else { - switch (err) { - case NSAPI_ERROR_OK: - printf(MODULE_STR" Interface is UP!\r\n"); - break; - - case NSAPI_ERROR_NO_CONNECTION: - printf(MODULE_STR" Link up has failed. Check if the cable link functional.\r\n"); - break; - - case NSAPI_ERROR_DHCP_FAILURE: - printf(MODULE_STR" DHCP Failure. Could not obtain an IP Address.\r\n"); - printf("Please check if the address configuration server is functional or change the addressing to Fixed IP via CLI (type \"help\" for more info).\r\n"); - break; - - case NSAPI_ERROR_ALREADY: - /* The ethernet interface is still trying to connect */ - break; - - default: - printf(MODULE_STR" Unknown error: %d\r\n", err); - break; - } - } - - ThisThread::sleep_for(1000); - } while ( err != NSAPI_ERROR_OK ); - - /* Bring up TCP Server */ - _server.open(&_net); - _server.bind(_net.get_ip_address(), _port); - _server.listen(); - _server.set_blocking(1500); - - printf(MODULE_STR" Listening on port %d...\r\n", _port); -} - -const char* RFFEServer::get_ip_address( void ) -{ - return _net.get_ip_address(); -} - -const char* RFFEServer::get_gateway( void ) -{ - return _net.get_gateway(); -} - -const char* RFFEServer::get_netmask( void ) -{ - return _net.get_netmask(); -} - -void EthernetThread( void ) -{ - uint8_t state = 0; - uint32_t last_page_addr, next_sector; - bool full_page = false, sector_erased = false; - uint8_t v_major = 0, v_minor = 0, v_patch = 0; - uint8_t buf[BUFSIZE]; - - int recv_sz, sent_sz; - - RFFEServer rffe_eth(&pll, FIX_IP); - - /* Ethernet initialization */ - rffe_eth.eth_init(); - - /* Try to connect the ethernet interface (will block here until ready) */ - rffe_eth.eth_connect(); - - //led3 = 1; - - if (get_value8(Eth_Addressing) == DHCP) { - set_value(IP_Addr, rffe_eth.get_ip_address(), sizeof(IP_Addr)); - set_value(Gateway_Addr, rffe_eth.get_gateway(), sizeof(Gateway_Addr)); - set_value(Mask_Addr, rffe_eth.get_netmask(), sizeof(Mask_Addr)); - - printf("Ethernet configs from DHCP:\r\n"); - printf("\tIP: %s\r\n", IP_Addr); - printf("\tNetmask: %s\r\n", Mask_Addr); - printf("\tGateway: %s\r\n", Gateway_Addr); - } - - while (true) { - printf("Waiting for new client connection...\r\n"); - - server.accept(&client, &client_addr); - client.set_blocking(1500); - - printf("Connection from client: %s\r\n", client_addr.get_ip_address()); - - while ( cable_status.link() ) { - /* Wait to receive data from client */ - recv_sz = client.recv((char*)buf, 3); - - if (recv_sz == 3) { - /* We received a complete message header */ - uint16_t payload_len = (buf[1] << 8) | buf[2]; - /* Check if we need to receive some more bytes. This - * fixes #9 github issue, in that we end up stuck here - * waiting for more bytes that never comes */ - if (payload_len > 0) { - recv_sz += client.recv( (char*) &buf[3], payload_len ); - } - } else if (recv_sz <= 0) { - /* Special case for disconnections - just discard the socket and await a new connection */ - break; - } else { - printf("Received malformed message header of size: %d , discarding...", recv_sz ); - continue; - } - -#ifdef DEBUG_PRINTF - printf("Received message of %d bytes: ", recv_sz); - for (int i = 0; i < recv_sz; i++) { - printf("0x%X ",buf[i]); - } - printf("\r\n"); -#endif - bsmp_mail_t *mail = bsmp_mail_box.alloc(); - - mail->response_mail_box = ð_mail_box; - mail->msg.data = buf; - mail->msg.len = recv_sz; - - bsmp_mail_box.put(mail); - - osEvent evt = eth_mail_box.get(); - - if (evt.status != osEventMail) { - /* Quietly ignore errors for now */ - continue; - } - - struct bsmp_raw_packet *response_mail = (struct bsmp_raw_packet *)evt.value.p; - - sent_sz = client.send((char*)response_mail->data, response_mail->len); - -#ifdef DEBUG_PRINTF - printf("Sending message of %d bytes: ", sent_sz); - for (int i = 0; i < sent_sz; i++) { - printf("0x%X ",response_mail->data[i]); - } - printf("\r\n"); -#endif - free(response_mail->data); - eth_mail_box.free(response_mail); - - if (sent_sz <= 0) { - printf("ERROR while writing to socket!\r\n"); - continue; - } - - if (state != get_value8(Reprogramming)) { - switch (get_value8(Reprogramming)) { - case 1: - /* Read new firmware version */ - v_major = Data[0]; - v_minor = Data[1]; - v_patch = Data[2]; - - sector_erased = false; - last_page_addr = (APPLICATION_ADDR + APPLICATION_SIZE); - next_sector = last_page_addr + flash.get_sector_size(last_page_addr); - memset(fw_buffer, 0xFF, sizeof(fw_buffer)); - break; - - case 2: - { - const uint32_t magic_addr = flash.get_flash_size() - 256; - memcpy(fw_buffer, (uint32_t *)magic_addr, 256); - - /* Store version number */ - fw_buffer[248] = v_major; - fw_buffer[249] = v_minor; - fw_buffer[250] = v_patch; - - /* Write the bootloader magic word in the last 4 bytes of the page */ - const uint32_t magic_word[] = {0xAAAAAAAA}; - - printf("Writing bootloader magic word at 0x%lX\r\n", magic_addr + 252); - memcpy(&fw_buffer[252], magic_word, sizeof(magic_word)); - - /* Write back to flash */ - __disable_irq(); - flash.write((uint32_t *)fw_buffer, magic_addr, 256); - __enable_irq(); - break; - } - default: - break; - } - state = get_value8(Reprogramming); - } - - if (get_value8(Reprogramming) == 1 && buf[0] == 0x20 && buf[3] == 0x0A ) { - if (full_page == false) { - memcpy(fw_buffer, Data, FILE_DATASIZE); - full_page = true; - } else { - memcpy(&fw_buffer[FILE_DATASIZE], Data, FILE_DATASIZE); -#ifdef DEBUG_PRINTF - printf("[REPROGRAM] Writing page 0x%X\r\n", last_page_addr); -#endif - /* A full firmware page was sent, copy data to file */ - if (!sector_erased) { - __disable_irq(); - flash.erase(flash.find_sector(last_page_addr)); - __enable_irq(); - sector_erased = true; - } - __disable_irq(); - flash.write((uint32_t *)fw_buffer, last_page_addr, 256); - __enable_irq(); - last_page_addr += 256; - if (last_page_addr >= next_sector) { - next_sector = last_page_addr + flash.get_sector_size(last_page_addr); - sector_erased = false; - } - - full_page = false; - } - } - - if (get_value8(Reset) == 1) { - printf("Resetting MBED!\r\n"); - mbed_reset(); - } - } - - client.close(); - printf("Client Disconnected!\r\n"); - - if (cable_status.link() == 0) { - /* Eth link is down, clean-up server connection */ - server.close(); - net.disconnect(); - break; - } - } -} -#endif diff --git a/legacy/app/ethernet.h b/legacy/app/ethernet.h deleted file mode 100644 index 2b736e8..0000000 --- a/legacy/app/ethernet.h +++ /dev/null @@ -1,36 +0,0 @@ -#if 0 -#ifndef ETHERNET_APP -#define ETHERNET_APP - -#define MODULE_STR "[ETHERNET]" - -enum { - FIX_IP, - DHCP -}; - -class RFFEServer { -public: - RFFEServer(CDCE906 &pll, int addressing, int port); - void eth_init(); - void eth_connect(); - - - const char* get_ip_address(); - const char* get_gateway(); - const char* get_netmask(); -private: - CDCE906 _pll; - - EthernetInterface _net; - TCPSocket _client; - SocketAddress _client_addr; - TCPServer _server; - Ethernet _cable_status; - - int _port; - int _addressing; -}; - -#endif -#endif diff --git a/legacy/app/main.cpp b/legacy/app/main.cpp deleted file mode 100644 index 1f9f4ba..0000000 --- a/legacy/app/main.cpp +++ /dev/null @@ -1,860 +0,0 @@ -/** MBED headers */ -#include "mbed.h" -#include "rtos.h" -#include "EthernetInterface.h" -#include "TCPServer.h" -#include "TCPSocket.h" -#include "watchdog.h" - -/* IAP includes */ -#include "IAP.h" - -/* Drivers */ -#include "PID.h" -#include "pcbnAPI.h" -#include "Drivers.h" -#include "cli.h" -#include "util.h" -#include "attenuators.h" - -/** BSMP headers */ -extern "C" { -#include "server_priv.h" -#include "server.h" -#include -} - -#define BUFSIZE 256 -#define SERVER_PORT 6791 - -/* PID Constants */ -#define PID_RATE 1.0 -#define PID_OUTMAX 3.3 -#define PID_OUTMIN 0.0 - -#define FILE_DATASIZE 128 - -/* Firmware version macros */ -#define FW_VERSION "V2_0_1" - -// BSMP Variables arrays -double Att[1]; -double TempAC[1]; -double TempBD[1]; -double Set_PointAC[1]; -double Set_PointBD[1]; -uint8_t Temp_Control[1]; -double HeaterAC[1]; -double HeaterBD[1]; -uint8_t Reset[1]; -uint8_t Reprogramming[1]; -uint8_t Data[FILE_DATASIZE]; -char Version[8]; -double PID_AC_Kc[1]; -double PID_AC_tauI[1]; -double PID_AC_tauD[1]; -double PID_BD_Kc[1]; -double PID_BD_tauI[1]; -double PID_BD_tauD[1]; -char IP_Addr[16]; -char Mask_Addr[16]; -char Gateway_Addr[16]; -char MAC_Addr[18]; -uint8_t Eth_Addressing[1]; - -char mac_buffer[6]; -uint8_t buf[BUFSIZE]; - -#define READ_ONLY 0 -#define READ_WRITE 1 - -#define RFFE_VAR( data, rw ) { { 0, rw, sizeof(data) }, NULL, data, NULL } -/* The index in this table will coincide with the index on the server list, since it registrates the variables sequentially */ - -struct bsmp_var rffe_vars[] = { - /* [0] = */ RFFE_VAR( Att, READ_WRITE ), // Attenuators - /* [1] = */ RFFE_VAR( TempAC, READ_ONLY ), // TempAC - /* [2] = */ RFFE_VAR( TempBD, READ_ONLY ), // TempBD - /* [3] = */ RFFE_VAR( Set_PointAC, READ_WRITE ), // Set_PointAC - /* [4] = */ RFFE_VAR( Set_PointBD, READ_WRITE ), // Set_PointBD - /* [5] = */ RFFE_VAR( Temp_Control, READ_WRITE ), // Temp_Control - /* [6] = */ RFFE_VAR( HeaterAC, READ_WRITE ), // HeaterAC - /* [7] = */ RFFE_VAR( HeaterBD, READ_WRITE ), // HeaterBD - /* [8] = */ RFFE_VAR( Reset, READ_WRITE ), // Reset - /* [9] = */ RFFE_VAR( Reprogramming, READ_WRITE ), // Reprogramming - /* [10] = */ RFFE_VAR( Data, READ_WRITE ), // Data - /* [11] = */ RFFE_VAR( Version, READ_ONLY ), // Version - /* [12] = */ RFFE_VAR( PID_AC_Kc, READ_WRITE ), // PID_AC_Kc - /* [13] = */ RFFE_VAR( PID_AC_tauI, READ_WRITE ), // PID_AC_tauI - /* [14] = */ RFFE_VAR( PID_AC_tauD, READ_WRITE ), // PID_AC_tauD - /* [15] = */ RFFE_VAR( PID_BD_Kc, READ_WRITE ), // PID_BD_Kc - /* [16] = */ RFFE_VAR( PID_BD_tauI, READ_WRITE ), // PID_BD_tauI - /* [17] = */ RFFE_VAR( PID_BD_tauD, READ_WRITE ), // PID_BD_tauD - /* [18] = */ RFFE_VAR( IP_Addr, READ_WRITE ), // Ip Address - /* [19] = */ RFFE_VAR( MAC_Addr, READ_WRITE ), // MAC Address - /* [20] = */ RFFE_VAR( Gateway_Addr, READ_WRITE ), // Gateway Address - /* [21] = */ RFFE_VAR( Mask_Addr, READ_WRITE ), // Mask Address - /* [22] = */ RFFE_VAR( Eth_Addressing, READ_WRITE ), // Eth Addressing type -}; - -typedef struct { - struct bsmp_raw_packet msg; - Mail *response_mail_box; -} bsmp_mail_t; - -Mail bsmp_mail_box; -Mail eth_mail_box; - -/* Setup the watchdog timer */ -Watchdog wdt; - -/* BSMP server */ -bsmp_server_t *bsmp; - -// Threads -Thread Temp_Control_thread(osPriorityNormal, 1280, NULL, "TEMP"); -Thread CLI_Proccess_Thread(osPriorityNormal, 1024, NULL, "CLI"); -Thread BSMP_Thread(osPriorityNormal, 1024, NULL, "BSMP"); -Thread Eth_Thread(osPriorityNormal, 1536, NULL, "ETH"); - -// Hardware Initialization - MBED - -// MBED Leds -DigitalOut led1(P1_18); -DigitalOut led2(P1_20); -DigitalOut led3(P1_21); -DigitalOut led4(P1_23); - -DigitalIn sw1(P1_29); - -// MBED pins -DigitalOut CSac(P2_1); // Chip select for ADT7320UCPZ-R2. LVTTL, high = disable, init = high.Temp. measurement in RFFE_AC -DigitalOut SHDN_temp(P0_23); // Shut down the temperature current boost output amplifier. LVTTL, low = disable, init = low. -DigitalOut led_g(P1_30); // Green LED -DigitalOut led_r(P1_31); // Red LED -DigitalOut CSbd(P0_16); // Chip select for ADT7320UCPZ-R2. LVTTL, high = disable, init = high.Temp. measurement in RFFE_BD -DigitalOut CS_dac(P0_24); // Chip select for DAC. LVTTL, low = Selected, init = high.Chip select -RawSerial pc(P0_2, P0_3); // Serial USB port. (NOTE: All printf() calls are redirected to this port) -SPI spi1(P0_9,P0_8,P0_7); //SPI Interface - spi(mosi, miso, sclk) - -/* Ethernet PLL */ -I2C pll_i2c(P0_27, P0_28); -CDCE906 pll(pll_i2c, 0b11010010); - -/* FeRAM */ -I2C feram_i2c(P0_19, P0_20); -DigitalOut feram_wp(P0_21); -FeRAM feram(feram_i2c, feram_wp); - -/* FlashIAP */ -IAP flash; -uint8_t fw_buffer[256]; - -/* MBED functions replacements */ -extern "C" void mbed_mac_address(char *s) -{ - memcpy(s, mac_buffer, 6); -} - -/* MBED Reset function */ -void mbed_reset( void ) -{ - wdt.kick(0.1); - /* Lock the firmware and wait for the overflow */ - while(1); -} - -void Temp_Feedback_Control( void ) -{ - /* Temperature Sensors */ -#if (TEMP_SENSOR == 0) - LM71 AC_Temp_sensor( spi1, CSac, 1000000, LM71_MODE_CONVERSION, 0.0, 100.0 ); - LM71 BD_Temp_sensor( spi1, CSbd, 1000000, LM71_MODE_CONVERSION, 0.0, 100.0 ); -#else -#if (TEMP_SENSOR == 1) - - ADT7320 AC_Temp_sensor( spi1, CSac, 1000000, ADT7320_CFG_16_BITS, 0, 0.0, 100.0 ); - ADT7320 BD_Temp_sensor( spi1, CSbd, 1000000, ADT7320_CFG_16_BITS, 0, 0.0, 100.0 ); -#else -#error "No temperature sensor selected! Please choose on mbed_app.json file!" -#endif -#endif - - /* Heater DAC output */ - DAC7554 AC_Heater_DAC( spi1, CS_dac, DAC_AC_SEL, 3.3 ); - DAC7554 BD_Heater_DAC( spi1, CS_dac, DAC_BD_SEL, 3.3 ); - - /* Temperature PIDs */ - double SetP_AC, SetP_BD; - double ProcessValueAC, ProcessValueBD; - double voutAC, voutBD; - - PID pidAC( &ProcessValueAC, &voutAC, &SetP_AC, get_value64(PID_AC_Kc), get_value64(PID_AC_tauI), get_value64(PID_AC_tauD), DIRECT ); - PID pidBD( &ProcessValueBD, &voutBD, &SetP_BD, get_value64(PID_BD_Kc), get_value64(PID_BD_tauI), get_value64(PID_BD_tauD), DIRECT ); - - int state = 2; - int pid_state = MANUAL; - - printf("Initializing Temp Control thread\r\n"); - - /* Create PIDs with generic tuning constants (they will be updated as soon as the control loop starts) */ - pidAC.SetSampleTime( PID_RATE*1000 ); - //pidAC.SetInputLimits( 0.0 , 100.0 ); - pidAC.SetOutputLimits( PID_OUTMIN , PID_OUTMAX ); - pidAC.SetMode( pid_state ); // Start with the automatic control disabled - - pidBD.SetSampleTime( PID_RATE*1000 ); - //pidBD.SetInputLimits( 0.0 , 100.0 ); - pidBD.SetOutputLimits( PID_OUTMIN, PID_OUTMAX ); - pidAC.SetMode( pid_state ); // Start with the automatic control disabled - - SHDN_temp = 1; - - while (1) { - if (state != get_value8(Temp_Control)) { - printf ("Temperature control in %s mode!\r\n", (get_value8(Temp_Control) == AUTOMATIC) ? "AUTOMATIC":"MANUAL"); - state = get_value8(Temp_Control); - - pid_state = (state != MANUAL) ? AUTOMATIC : MANUAL; - - pidAC.SetMode( pid_state ); - pidBD.SetMode( pid_state ); - } - - // Read values from RFFE's temperature sensors - set_value(TempAC,AC_Temp_sensor.Read()); - set_value(TempBD,BD_Temp_sensor.Read()); - - // Update the Process Values - ProcessValueAC = get_value64(TempAC); - ProcessValueBD = get_value64(TempBD); - - /* Update Set Points */ - SetP_AC = get_value64(Set_PointAC); - SetP_BD = get_value64(Set_PointBD); - -#ifdef DEBUG_PRINTF - printf( "AC_Temp = %f \r\n", ProcessValueAC ); - printf( "BD_Temp = %f \r\n", ProcessValueBD ); - printf( "PID_AC Params:\r\n"); - printf( "\tKc:%f\ttauI:%f\ttauD:%f\r\n", get_value64(PID_AC_Kc), get_value64(PID_AC_tauI), get_value64(PID_AC_tauD)); - printf( "PID_BD Params:\r\n"); - printf( "\tKc:%f\ttauI:%f\ttauD:%f\r\n", get_value64(PID_BD_Kc), get_value64(PID_BD_tauI), get_value64(PID_BD_tauD)); -#endif - - // Update PID tuning values - pidAC.SetTunings( get_value64(PID_AC_Kc), get_value64(PID_AC_tauI), get_value64(PID_AC_tauD) ); - pidBD.SetTunings( get_value64(PID_BD_Kc), get_value64(PID_BD_tauI), get_value64(PID_BD_tauD) ); - - /* Compute the PID values (this functions returns false and does nothing if set in MANUAL mode) */ - if ( ( pidAC.Compute() == false ) ) { - // Use the heater values provided by the user - voutAC = get_value64(HeaterAC); - - // Check if the user set values within the DAC range - if (get_value64(HeaterAC) > PID_OUTMAX) { - voutAC = PID_OUTMAX; - } - if (get_value64(HeaterAC) < PID_OUTMIN) { - voutAC = PID_OUTMIN; - } - } - - if ( ( pidBD.Compute() == false ) ) { - // Use the heater values provided by the user - voutBD = get_value64(HeaterBD); - - // Check if the user set values within the DAC range - if (get_value64(HeaterBD) > PID_OUTMAX) { - voutBD = PID_OUTMAX; - } - if (get_value64(HeaterBD) < PID_OUTMIN) { - voutBD = PID_OUTMIN; - } - } - - // Update values in BSMP registers list - set_value(HeaterAC, voutAC); - set_value(HeaterBD, voutBD); - - AC_Heater_DAC.Write( voutAC ); - BD_Heater_DAC.Write( voutBD ); - -#ifdef DEBUG_PRINTF - printf("Heater output AC: %f \t BD: %f\r\n", voutAC, voutBD); -#endif - ThisThread::sleep_for(100); - } -} - -char cli_cmd[SCMD_MAX_CMD_LEN+1]; - -void commandCallback(char *cmdIn, void *extraContext) -{ - // all our commands will be recieved async in commandCallback - // we don't want to do time consuming things since it could - // block the reader and allow the uart to overflow so we simply - // copy it out in the callback and then process it latter. - strcpy(cli_cmd, cmdIn); - - CLI_Proccess_Thread.flags_set(0x01); -} - -void CLI_Proccess( void ) -{ - char *cmd, *save_ptr; - char *arg[2]; - uint8_t msg_buffer[30] = {0}; - - printf("[CLI] Initializing CLI thread\r\n"); - - /* Instantiate our command processor for the USB serial line. */ - scMake(&pc, commandCallback, NULL); - - for( ; ; ) { - ThisThread::flags_wait_all(0x01); - cmd = strtok_r( cli_cmd, " ", &save_ptr); - - for ( uint8_t i = 0; i < sizeof(arg)/sizeof(arg[0]); i++) { - arg[i] = strtok_r( NULL, " ", &save_ptr); - } - printf("\r\n"); - if (strncmp( cmd, "dump", 5 ) == 0) { - printf("RFFE Vars dump:\r\n"); - printf("\t[0] Att: %f\r\n", get_value64(Att)); - printf("\t[1] Temperature AC: %f\r\n", get_value64(TempAC)); - printf("\t[2] Temperature BD: %f\r\n", get_value64(TempBD)); - printf("\t[3] Set PointAC: %f\r\n", get_value64(Set_PointAC)); - printf("\t[4] Set PointBD: %f\r\n", get_value64(Set_PointBD)); - printf("\t[5] Temperature Control PID: %s\r\n", get_value8(Temp_Control) ? "AUTOMATIC":"MANUAL"); - printf("\t[6] Heater AC: %f\r\n", get_value64(HeaterAC)); - printf("\t[7] Heater BD: %f\r\n", get_value64(HeaterBD)); - printf("\t[8] Reset: %d\r\n", get_value8(Reset)); - printf("\t[9] Reprogramming: %d\r\n", get_value8(Reprogramming)); - printf("\t[10] New FW Data\r\n"); - printf("\t[11] Firmware version: %s\r\n", FW_VERSION); - printf("\t[12] PID_AC_Kc: %f\r\n", get_value64(PID_AC_Kc)); - printf("\t[13] PID_AC_tauI: %f\r\n", get_value64(PID_AC_tauI)); - printf("\t[14] PID_AC_tauD: %f\r\n", get_value64(PID_AC_tauD)); - printf("\t[15] PID_BD_Kc: %f\r\n", get_value64(PID_BD_Kc)); - printf("\t[16] PID_BD_tauI: %f\r\n", get_value64(PID_BD_tauI)); - printf("\t[17] PID_BD_tauD: %f\r\n", get_value64(PID_BD_tauD)); - printf("\t[18] IP-Address: %s\r\n", IP_Addr); - printf("\t[19] MAC-Address: %s\r\n", MAC_Addr); - printf("\t[20] Gateway-Address: %s\r\n", Gateway_Addr); - printf("\t[21] Mask-Address: %s\r\n", Mask_Addr); - printf("\t[22] Eth Addressing: %s\r\n", get_value8(Eth_Addressing) ? "DHCP (1)" : "Fixed IP (0)"); - printf("\r\n"); - } else if (strncmp( cmd, "set", 4 ) == 0) { - if ((arg[0] == NULL) || (arg[1] == NULL)) { - printf("Command \"set\" used but no arguments given! Type \"help\" to see its correct usage.\r\n"); - continue; - } - uint8_t var_index = strtol( arg[0], NULL, 10); - - if (rffe_vars[var_index].info.writable == READ_ONLY) { - printf("The requested variable is READ_ONLY!\r\n"); - continue; - } - - /* Clear request msg buffer */ - memset(msg_buffer, 0, sizeof(msg_buffer)); - - bsmp_mail_t *mail = bsmp_mail_box.alloc(); - - mail->response_mail_box = NULL; - mail->msg.data = msg_buffer; - mail->msg.data[0] = 0x20; /* CMD_VAR_WRITE */ - mail->msg.data[3] = var_index; /* Payload[0]: Var id */ - - uint16_t payload_size = 0; - - switch(rffe_vars[var_index].info.size) { - case sizeof(int): - { - int arg_int = strtol( arg[1], NULL, 10); - memcpy(&(mail->msg.data[4]), &arg_int, sizeof(arg_int)); - payload_size = sizeof(int); - break; - } - case sizeof(double): - { - double arg_dbl = strtod( arg[1], NULL); - memcpy(&(mail->msg.data[4]), &arg_dbl, sizeof(arg_dbl)); - payload_size = sizeof(double); - break; - } - case sizeof(uint8_t): - { - uint8_t arg_byte = strtoul( arg[1], NULL, 10); - memcpy(&(mail->msg.data[4]), &arg_byte, sizeof(arg_byte)); - payload_size = sizeof(uint8_t); - break; - } - default: - strncpy((char *)&(mail->msg.data[4]), arg[1], rffe_vars[var_index].info.size); - payload_size = rffe_vars[var_index].info.size; - } - - payload_size++; /* Var id counts as payload */ - mail->msg.data[1] = (payload_size >> 8) & 0xFF; /* Payload size >> 8 */ - mail->msg.data[2] = payload_size & 0xFF; /* Payload size */ - mail->msg.len = payload_size + 3; - - bsmp_mail_box.put(mail); - - } else if ((strncmp( cmd, "help", 5 ) == 0) || (strncmp( cmd, "?", 2 ) == 0) ) { - printf("RFFE Firmware help. Available commands:\r\n"); - printf("\tCMD\t[arg1]\t[arg2]\r\n"); - printf("\tdump\t\t\tList all variables available and their current status\r\n"); - printf("\tset\t[VAR]\t[VALUE]\tSet value to a variable in the list\r\n"); - printf("\thelp\t\t\tShow this help menu\r\n"); - } else { - printf("Command \"%s\" not recognized! Please use the command \"help\" to check the CLI usage\r\n", cli_cmd); - } - } -} - -void bsmp_hook_signal_threads(enum bsmp_operation op, struct bsmp_var **list) -{ - bsmp_var *var = NULL; - uint8_t i = 0; - - if (op == BSMP_OP_READ) return; - - for (i = 0; list[i] != NULL; i++) { - var = list[i]; - /* Special cases */ - switch( var->info.id ) { - case 0: - /* Attenuators */ - set_value(Att, attenuators_update(get_value64(Att))); - printf("[ATT] Attenuation updated to %f\r\r\n", get_value64(Att)); - break; - case 8: - /* Reset */ - printf("Resetting MBED...\r\n"); - mbed_reset(); - break; - case 18: - /* IP Address */ - printf("[FERAM] Updating IP address on FeRAM to %s ...\r\n", IP_Addr); - feram.set_ip_addr(IP_Addr); - break; - case 19: - /* MAC Address */ - printf("[FERAM] Updating MAC address on FeRAM to %s ...\r\n", MAC_Addr); - feram.set_mac_addr(MAC_Addr); - break; - case 20: - /* Gateway Address */ - printf("[FERAM] Updating Gateway address on FeRAM to %s ...\r\n", Gateway_Addr); - feram.set_gateway_addr(Gateway_Addr); - break; - case 21: - /* Mask Address */ - printf("[FERAM] Updating Mask address on FeRAM to %s ...\r\n", Mask_Addr); - feram.set_mask_addr(Mask_Addr); - break; - case 22: - /* Eth Addressing */ - printf("[FERAM] Updating Ethernet Addressing type on FeRAM to %s ...\r\n", get_value8(Eth_Addressing) ? "DHCP (1)" : "Fixed IP (0)"); - feram.set_eth_addressing(get_value8(Eth_Addressing)); - break; - } - } -} - -void bsmp_dispatcher( void ) -{ - struct bsmp_raw_packet mock_response; - - while(1) { - /* Wait for a new message */ - osEvent evt = bsmp_mail_box.get(); - - if (evt.status != osEventMail) { - /* Quietly ignore errors for now */ - continue; - } - - bsmp_mail_t *mail = (bsmp_mail_t*)evt.value.p; - - mock_response.data = (uint8_t *) malloc(sizeof(uint8_t)*30); - - /* Proccess BSMP request */ - bsmp_process_packet(bsmp, &mail->msg, &mock_response); - - /* Only respond if there's a valid mailbox to put the response in */ - if (mail->response_mail_box) { - struct bsmp_raw_packet *response = mail->response_mail_box->alloc(); - response->data = mock_response.data; - response->len = mock_response.len; - mail->response_mail_box->put(response); - } else { - free(mock_response.data); - } - - bsmp_mail_box.free(mail); - } -} - -void print_buffer( uint8_t *buf, size_t sz ) -{ - for (size_t i = 0; i < sz; i++) { - printf("0x%X ",buf[i]); - } - printf("\r\n"); -} - -void Eth_Handler( void ) -{ - uint8_t state = 0; - uint32_t last_page_addr, next_sector; - bool full_page = false, sector_erased = false; - uint8_t v_major = 0, v_minor = 0, v_patch = 0, fw_type = 0; - - led2 = !pll.cfg_eth(); - - ThisThread::sleep_for(100); - - // Ethernet initialization - EthernetInterface net; - TCPSocket client; - SocketAddress client_addr; - TCPServer server; - int recv_sz, sent_sz; - int err, link; - - while (true) { - printf("[ETHERNET] Trying to bring up connection...\r\n"); - led_r = 1; - - if (get_value8(Eth_Addressing)) { - net.set_dhcp(true); - } else { - net.set_network(IP_Addr,Mask_Addr,Gateway_Addr); - } - - do { - err = net.connect(); - - switch (err) { - case NSAPI_ERROR_OK: - printf("[ETHERNET] Interface is UP!\r\n"); - break; - - case NSAPI_ERROR_NO_CONNECTION: - printf("[ETHERNET] Link up has failed. Check if the cable link is functional.\r\n"); - break; - - case NSAPI_ERROR_DHCP_FAILURE: - printf("[ETHERNET] DHCP Failure. Could not obtain an IP Address.\r\n"); - printf("Please check if the address configuration server is functional or change the addressing to Fixed IP via CLI (type \"help\" for more info).\r\n"); - break; - - case NSAPI_ERROR_ALREADY: - /* The ethernet interface is still trying to connect */ - break; - - case NSAPI_ERROR_IS_CONNECTED: - printf("[ETHERNET] Interface is connected!\r\n"); - err = NSAPI_ERROR_OK; - break; - - default: - printf("[ETHERNET] Unknown error: %d\r\n", err); - break; - } - - ThisThread::sleep_for(1000); - } while ( err != NSAPI_ERROR_OK ); - - led_r = 0; - led3 = 1; - - if (get_value8(Eth_Addressing)) { - set_value(IP_Addr, net.get_ip_address(), sizeof(IP_Addr)); - set_value(Gateway_Addr, net.get_gateway(), sizeof(Gateway_Addr)); - set_value(Mask_Addr, net.get_netmask(), sizeof(Mask_Addr)); - - printf("[ETHERNET] Configs from DHCP:\r\n"); - printf("\tIP: %s\r\n", IP_Addr); - printf("\tNetmask: %s\r\n", Mask_Addr); - printf("\tGateway: %s\r\n", Gateway_Addr); - } - - server.open(&net); - server.bind(net.get_ip_address(), SERVER_PORT); - server.listen(); - server.set_blocking(true); - server.set_timeout(1000); - - printf("[ETHERNET] RFFE eth server is up and listening on port %d!\r\n", SERVER_PORT); - - link = net.get_connection_status(); - while (link == NSAPI_STATUS_GLOBAL_UP) { - printf("[ETHERNET] Waiting for new client connection...\r\n"); - led_g = 0; - - do { - err = server.accept(&client, &client_addr); - } while ( err != NSAPI_ERROR_OK ); - - client.set_blocking(false); - client.set_timeout(1000); - - printf("[ETHERNET] Connection from client: %s\r\n", client_addr.get_ip_address()); - - led_g = 1; - led4 = 1; - while ( true ) { - /* Wait to receive data from client */ - recv_sz = client.recv((char*)buf, 3); - - /* Update cable link status */ - link = net.get_connection_status(); - - if (link == NSAPI_STATUS_CONNECTING) { - printf("[ETHERNET] Cable disconnected!\r\n"); - break; - } - - if (recv_sz == 3) { - /* We received a complete message header */ - uint16_t payload_len = (buf[1] << 8) | buf[2]; - /* Check if we need to receive some more bytes. This - * fixes #9 github issue, in that we end up stuck here - * waiting for more bytes that never comes */ - if (payload_len > 0) { - recv_sz += client.recv( (char*) &buf[3], payload_len ); - } - } else if (recv_sz == NSAPI_ERROR_WOULD_BLOCK) { - /* Would block */ - continue; - } else if (recv_sz < 0) { - printf("[ETHERNET] Unknown error when trying to receive msg from client: %d\r\n", recv_sz); - break; - } else if (recv_sz == 0) { - printf("[ETHERNET] Client disconnected!\r\n"); - break; - } else { - printf("[BSMP] Received malformed message header of size: %d\r\n\t", recv_sz ); - print_buffer(buf, recv_sz); - continue; - } - -#ifdef DEBUG_PRINTF - printf("[ETHERNET] Received message of %d bytes:\r\n\t", recv_sz); - print_buffer(buf, recv_sz); -#endif - bsmp_mail_t *mail = bsmp_mail_box.alloc(); - - mail->response_mail_box = ð_mail_box; - mail->msg.data = buf; - mail->msg.len = recv_sz; - - bsmp_mail_box.put(mail); - - osEvent evt = eth_mail_box.get(); - - if (evt.status != osEventMail) { - /* Quietly ignore errors for now */ - continue; - } - - struct bsmp_raw_packet *response_mail = (struct bsmp_raw_packet *)evt.value.p; - - sent_sz = client.send((char*)response_mail->data, response_mail->len); - -#ifdef DEBUG_PRINTF - printf("[ETHERNET] Sending message of %d bytes:\r\n\t", sent_sz); - print_buffer(buf, recv_sz); -#endif - free(response_mail->data); - eth_mail_box.free(response_mail); - - if (sent_sz <= 0) { - printf("[ETHERNET] Error while writing to socket: %d\r\n", sent_sz); - break; - } - - if (state != get_value8(Reprogramming)) { - switch (get_value8(Reprogramming)) { - case 1: - sector_erased = false; - - /* Read new firmware version */ - v_major = Data[0]; - v_minor = Data[1]; - v_patch = Data[2]; - /* Read which firmware will be sent: [1] - Application; [2] - Bootloader */ - fw_type = Data[3]; - - /* Bootloader first page address on EEPROM: (0) */ - last_page_addr = (fw_type == 2) ? (0) : (APPLICATION_ADDR + APPLICATION_SIZE); - - next_sector = last_page_addr + flash.get_sector_size(last_page_addr); - memset(fw_buffer, 0xFF, sizeof(fw_buffer)); - break; - - case 2: - { - const uint32_t magic_addr = flash.get_flash_size() - 256; - memcpy(fw_buffer, (uint32_t *)magic_addr, 256); - - /* Store version number */ - fw_buffer[248] = v_major; - fw_buffer[249] = v_minor; - fw_buffer[250] = v_patch; - fw_buffer[251] = fw_type; - - /* Write the bootloader magic word in the last 4 bytes of the page */ - const uint32_t magic_word[] = {0xAAAAAAAA}; - - printf("[REPROGRAM] Writing bootloader magic word at 0x%lX\r\n", magic_addr + 252); - memcpy(&fw_buffer[252], magic_word, sizeof(magic_word)); - - /* Write back to flash */ - __disable_irq(); - flash.write((uint32_t *)fw_buffer, magic_addr, 256); - __enable_irq(); - break; - } - default: - break; - } - state = get_value8(Reprogramming); - } - - if (get_value8(Reprogramming) == 1 && buf[0] == 0x20 && buf[3] == 0x0A ) { - if (full_page == false) { - memcpy(fw_buffer, Data, FILE_DATASIZE); - full_page = true; - } else { - memcpy(&fw_buffer[FILE_DATASIZE], Data, FILE_DATASIZE); - - printf("[REPROGRAM] Writing page 0x%lX\r\n", last_page_addr); - - /* A full firmware page was sent, copy data to file */ - if (!sector_erased) { - __disable_irq(); - flash.erase(flash.find_sector(last_page_addr)); - __enable_irq(); - sector_erased = true; - } - __disable_irq(); - flash.write((uint32_t *)fw_buffer, last_page_addr, 256); - __enable_irq(); - last_page_addr += 256; - if (last_page_addr >= next_sector) { - next_sector = last_page_addr + flash.get_sector_size(last_page_addr); - sector_erased = false; - } - - full_page = false; - } - } - - if (get_value8(Reset) == 1) { - printf("Resetting MBED!\r\n"); - mbed_reset(); - } - } - /* If we're out of the connection loop, either the connection has crashed or the client has disconnected, clean-up */ - client.close(); - } - - /* Eth link is down, clean-up server connection */ - printf("[ETHERNET] Cleaning up server connection and interface\r\n"); - server.close(); - net.disconnect(); - } -} - -int main( void ) -{ - wdt.clear_overflow_flag(); - - //Init serial port for info printf - pc.baud(115200); - - printf("Starting RFFEuC firmware "FW_VERSION" !\r\n\r\n"); - - bsmp = bsmp_server_new(); - - bsmp_register_hook(bsmp, bsmp_hook_signal_threads); - - led1 = 1; - led_r = 0; - - // Variables initialization - // Attenuators - //set_value(Att, 30.0); - // TempAC - set_value(TempAC, 0.0); - // TempBD - set_value(TempBD, 0.0); - // Set_PointAC - set_value(Set_PointAC, 51.5); - // Set_PointBD - set_value(Set_PointBD, 51.5); - // Temp_Control - set_value(Temp_Control, 0); - // HeaterAC - set_value(HeaterAC, 0.0); - // HeaterBD - set_value(HeaterBD, 0.0); - // Reset - set_value(Reset, 0); - // Reprogramming - set_value(Reprogramming, 0); - // Version - set_value(Version, FW_VERSION, sizeof(FW_VERSION)); - //PID_AC Kc parameter - set_value(PID_AC_Kc, 10.5); - //PID_AC tauI parameter - set_value(PID_AC_tauI, 12); - //PID_AC tauI parameter - set_value(PID_AC_tauD, 2); - //PID_BD Kc parameter - set_value(PID_BD_Kc, 10.5); - //PID_BD tauI parameter - set_value(PID_BD_tauI, 12); - //PID_BD tauI parameter - set_value(PID_BD_tauD, 2); - - feram.get_attenuation(Att); - feram.get_ip_addr(IP_Addr); - feram.get_gateway_addr(Gateway_Addr); - feram.get_mask_addr(Mask_Addr); - feram.get_mac_addr(MAC_Addr, mac_buffer); - feram.get_eth_addressing(Eth_Addressing); - - printf("Ethernet configuration from FeRAM:\r\n"); - printf("\tIP : %s\r\n", IP_Addr); - printf("\tMask : %s\r\n", Mask_Addr); - printf("\tGateway : %s\r\n", Gateway_Addr); - printf("\tMAC : %s\r\n", MAC_Addr); - printf("\r\n"); - - for ( uint8_t i = 0; i < sizeof(rffe_vars)/sizeof(rffe_vars[0]); i++) { - rffe_vars[i].info.id = i; - bsmp_register_variable( bsmp, &rffe_vars[i] ); - } - - set_value(Att, attenuators_update(get_value64(Att))); - - // *************************************Threads*************************************** - Temp_Control_thread.start(Temp_Feedback_Control); - CLI_Proccess_Thread.start(CLI_Proccess); - BSMP_Thread.start(bsmp_dispatcher); - Eth_Thread.start(Eth_Handler); - - - /* Should never get here, but wait for all threads to die */ - Temp_Control_thread.join(); - CLI_Proccess_Thread.join(); - BSMP_Thread.join(); - Eth_Thread.join(); -} diff --git a/legacy/app/mbed_app.json b/legacy/app/mbed_app.json deleted file mode 100644 index cb9c003..0000000 --- a/legacy/app/mbed_app.json +++ /dev/null @@ -1,32 +0,0 @@ -{ - "config": { - "Temperature_Sensor": { - "help": "Select temperature sensor being used in the control board (0: LM71; 1: ADT7320)", - "macro_name": "TEMP_SENSOR", - "value": 0 - }, - - "main-stack-size": { - "value": 1024 - } - }, - - "target_overrides": { - "*": { - "target.restrict_size": "0x38000", - "target.bootloader_img": "../BUILD/bootloader/bootloader.bin", - "target.features_add": ["LWIP", "COMMON_PAL"], - "mbed-trace.enable": true, - "platform.stdio-convert-newlines": true, - "platform.stdio-baud-rate": 115200, - "platform.default-serial-baud-rate": 115200, - "platform.error-filename-capture-enabled": true, - "platform.memory-tracing-enabled": true, - "target.network-default-interface-type": "ETHERNET", - "lwip.use-mbed-trace": false, - "lwip.debug-enabled": false, - "filesystem.present": false, - "events.present": true - } - } -} diff --git a/legacy/app/pcbnAPI.cpp b/legacy/app/pcbnAPI.cpp deleted file mode 100644 index 4ed2dd1..0000000 --- a/legacy/app/pcbnAPI.cpp +++ /dev/null @@ -1,260 +0,0 @@ -#include "rtos.h" -#include "pcbnAPI.h" - -//int build_variable(int ID, int type, int size, int value); - -// Mutex to access shared resources (write/read from BSMP variables) -Mutex bsmp_var_mutex; - -unsigned char calculate_size(unsigned char size){ - if (size || 128) { - return 128*(size+1)+2; - } - return size; -} - -void status_command_ask(command_header *status){ - status->command = STATUS_CODE_ASK; - status->size = 0x00; - return; -} - -void status_command_answer(command_header *status){ - status->command = STATUS_CODE_ANSWER; - status->size = 0x00; - return; -} - -void var_list_command_ask(command_header *varlist){ - varlist->command = VAR_LIST_CODE_ASK; - varlist->size = 0x00; - return; -} - -void var_list_command_answer(command_header *varlist,int size){ - varlist->command = VAR_LIST_CODE_ANSWER; - varlist->size = size; - return; -} - -void var_read_command_ask(command_header *varread){ - varread->command = VAR_READ_CODE_ASK; - varread->size = 0x01; - return; -} - -void var_read_command_answer(command_header *varread, int size){ - varread->command = VAR_READ_CODE_ANSWER; - varread->size = size; - return; -} - -void var_write_command_ask(command_header *varwrite,int size){ - varwrite->command = VAR_WRITE_CODE_ASK; - varwrite->size = 1 + size; - return; -} - -void ping_command(command_header *ping, int size){ - ping->command = PING_CODE; - ping->size = 8 + size; - return; -} - -void error_commands(command_header *error,int code){ - error->command = code; - error->size = 0x0; - return; -} - -void ok_command(command_header *error){ - error_commands(error,OK_CODE); - return; -} -void bad_message_command(command_header *error){ - error_commands(error,BAD_MESSAGE_CODE); - return; -} - -void op_not_supported_command(command_header *error){ - error_commands(error,OP_NOT_SUPPORTED_CODE); - return; -} - -void invalid_id_command(command_header *error){ - error_commands(error,INVALID_ID_CODE); - return; -} - -void invalid_value_command(command_header *error){ - error_commands(error,INVALID_VALUE_CODE); - return; -} - -void invalid_payload_command(command_header *error){ - error_commands(error,INVALID_PAYLOAD_CODE); - return; -} - -void read_only_command(command_header *error){ - error_commands(error,READ_ONLY_COMMAND); - return; -} - -void no_memory_command(command_header *error){ - error_commands(error,NO_MEMORY_CODE); - return; -} - -void internal_error_command(command_header *error){ - error_commands(error,INTERNAL_ERROR_CODE); - return; -} - -void message(command_header *recv, command_header *send, var_list * Vars){ - Charge aux; - switch (recv->command) - { - case STATUS_CODE_ASK: - if (recv->size != 0) { - bad_message_command(send); - break; - } - status_command_answer(send); - break; - - case VAR_LIST_CODE_ASK: - if (recv->size != 0) { - bad_message_command(send); - break; - } - var_list_command_answer(send,Vars->count); - bsmp_var_mutex.lock(); - for (uint16_t n = 0; n < Vars->count; n++) { - send->charge[n] = Vars->var[n]->size + 0x80*(Vars->var[n]->type); - } - bsmp_var_mutex.unlock(); - break; - - case VAR_READ_CODE_ASK: - if (recv->size != 1) { - invalid_payload_command(send); - break; - } - - if (recv->charge[0] >= Vars->count) { - invalid_id_command(send); - break; - } - - bsmp_var_mutex.lock(); - var_read_command_answer(send,Vars->var[recv->charge[0]]->size); - - memcpy(aux.charge1,&(Vars->var[recv->charge[0]]->value),Vars->var[recv->charge[0]]->size); -#if 0 - printf("\nVariable ID: %d",recv->charge[0]); - if (Vars->var[recv->charge[0]]->size == 1) - printf("\nValue: %2X\n",aux.charge1[0]); - if (Vars->var[recv->charge[0]]->size == 2) - printf("\nValue: %d\n",aux.charge2[0]); - if (Vars->var[recv->charge[0]]->size == 4) - printf("\nValue: %f\n",aux.charge3[0]); -#endif - memcpy(send->charge,&(Vars->var[recv->charge[0]]->value),Vars->var[recv->charge[0]]->size); - bsmp_var_mutex.unlock(); - break; - - case VAR_WRITE_CODE_ASK: - if (recv->charge[0] >= Vars->count) { - invalid_id_command(send); - break; - } - - if (recv->size != (Vars->var[recv->charge[0]]->size + 1)) { - invalid_payload_command(send); - break; - } - - if (Vars->var[recv->charge[0]]->type == 0) { - read_only_command(send); - break; - } - - bsmp_var_mutex.lock(); - memcpy(&(Vars->var[recv->charge[0]]->value),&recv->charge[1],Vars->var[recv->charge[0]]->size); - ok_command(send); - bsmp_var_mutex.unlock(); - break; - - default: - op_not_supported_command(send); - } - /* - free(aux.charge1); - free(aux.charge2); - free(aux.charge3); - */ - return; -} - -void set_value(double *var, double value){ - Charge aux; - - bsmp_var_mutex.lock(); - aux.charge3[0] = value; - memcpy(var,&aux, sizeof(double)); - bsmp_var_mutex.unlock(); -} - - -void set_value(char *var, char const* value, size_t sz){ - bsmp_var_mutex.lock(); - strncpy(var,value, sz); - bsmp_var_mutex.unlock(); -} - -void set_value(int *var, int value){ - Charge aux; - - bsmp_var_mutex.lock(); - aux.charge2[0] = value; - memcpy(var,&aux, sizeof(int)); - bsmp_var_mutex.unlock(); -} - -void set_value(uint8_t *var, uint8_t value){ - Charge aux; - - bsmp_var_mutex.lock(); - aux.charge1[0] = value; - memcpy(var,&aux, sizeof(uint8_t)); - bsmp_var_mutex.unlock(); -} - -unsigned char get_value8(void *var){ - Charge aux; - bsmp_var_mutex.lock(); - memcpy(&aux,var, sizeof(unsigned char)); - bsmp_var_mutex.unlock(); - return aux.charge1[0]; -} - -int get_value32(void *var){ - Charge aux; - - bsmp_var_mutex.lock(); - memcpy(&aux,var, sizeof(int)); - bsmp_var_mutex.unlock(); - - return aux.charge2[0]; -} - -double get_value64(void *var){ - Charge aux; - - bsmp_var_mutex.lock(); - memcpy(&aux,var, sizeof(double)); - bsmp_var_mutex.unlock(); - - return aux.charge3[0]; -} diff --git a/legacy/app/pcbnAPI.h b/legacy/app/pcbnAPI.h deleted file mode 100644 index 38fb351..0000000 --- a/legacy/app/pcbnAPI.h +++ /dev/null @@ -1,84 +0,0 @@ -#ifndef PCBNAPI_H_ -#define PCBNAPI_H_ - -#include -#include -#include -#include "mbed.h" - - -#define MAX_PAYLOAD_COMM 256 -#define MAX_VALUE_VAR 256 -#define STATUS_CODE_ASK 0x00 -#define STATUS_CODE_ANSWER 0x01 -#define VAR_LIST_CODE_ASK 0x02 -#define VAR_LIST_CODE_ANSWER 0x03 -#define VAR_READ_CODE_ASK 0x10 -#define VAR_READ_CODE_ANSWER 0x11 -#define VAR_WRITE_CODE_ASK 0x20 -#define PING_CODE 0xD6 -#define OK_CODE 0xE0 -#define BAD_MESSAGE_CODE 0xE1 -#define OP_NOT_SUPPORTED_CODE 0xE2 -#define INVALID_ID_CODE 0xE3 -#define INVALID_VALUE_CODE 0xE4 -#define INVALID_PAYLOAD_CODE 0xE5 -#define READ_ONLY_COMMAND 0xE6 -#define NO_MEMORY_CODE 0xE7 -#define INTERNAL_ERROR_CODE 0xE8 - -typedef struct vheader{ - unsigned char id; - unsigned char type; // write = 1; read = 0 - unsigned char size; - unsigned char value[MAX_VALUE_VAR]; -}variable_header; - -typedef struct cheader{ - unsigned char command; - unsigned char size; - unsigned char charge[MAX_PAYLOAD_COMM]; -}command_header; - -typedef struct vlist{ - variable_header ** var; - unsigned int count; -}var_list; - -typedef union ChargeType { - uint8_t charge1[MAX_VALUE_VAR]; - int charge2[MAX_VALUE_VAR/2]; - double charge3[MAX_VALUE_VAR/4]; -} Charge; - -unsigned char calculate_size(unsigned char size); -void status_command_ask(command_header *status); -void status_command_answer(command_header *status); -void var_list_command_ask(command_header *varlist); -void var_list_command_answer(command_header *varlist,int size); -void var_read_command_ask(command_header *varread); -void var_read_command_answer(command_header *varread, int size); -void var_write_command_ask(command_header *varwrite,int size); -void ping_command(command_header *ping, int size); -void error_commands(command_header *error,int code); -void ok_command(command_header *error); -void bad_message_command(command_header *error); -void op_not_supported_command(command_header *error); -void invalid_id_command(command_header *error); -void invalid_value_command(command_header *error); -void invalid_payload_command(command_header *error); -void read_only_command(command_header *error); -void no_memory_command(command_header *error); -void internal_error_command(command_header *error); - -void message(command_header *recv, command_header *send, var_list * Vars); - -void set_value(int *var, int value); -void set_value(double *var, double value); -void set_value(char *var, char const* value, size_t sz); -void set_value(uint8_t *var, uint8_t value); -unsigned char get_value8(void *var); -int get_value32(void *var); -double get_value64(void *var); - -#endif diff --git a/legacy/app/util.cpp b/legacy/app/util.cpp deleted file mode 100644 index f21e6e1..0000000 --- a/legacy/app/util.cpp +++ /dev/null @@ -1,117 +0,0 @@ -#include "util.h" - -#include -#include -#include - -void int2bin6(int value, bool * bin) -{ - int resul; - - memset( bin, 0, 6 ); - - for (int i = 5; i >= 0; i--) { - bin[i] = 1; - resul = bin[5]*32+bin[4]*16+bin[3]*8+bin[2]*4+bin[1]*2+bin[0]*1; - - if (resul == value) { - return; - } - if (resul > value) { - bin[i] = 0; - } - } -} - -uint32_t str2uint( char *s ) -{ - uint32_t result = 0; - - if (s == 0) { - return 0; - } - - while ( (*s >= '0') && (*s <='9') ) { - result *= 10; - result += *s - '0'; - s++; - } - - return result; -} - -void int2str( char *s, int num ) -{ - short k = 0; - char aux[11]; - - if (num == 0) { - aux[k] = 0; - k++; - } - - while (num) { - aux[k] = num%10; - num = num/10; - k++; - } - - while (k>0) { - *s = (aux[k-1] + '0'); - s++; - k--; - } - - *s = 0; -} - -bool version_str2int( char *s, uint8_t *maj, uint8_t *min, uint8_t *pat ) -{ - if( s[0] == 'V' && isdigit(s[1]) && isdigit(s[3]) && isdigit(s[5]) ) { - *maj = s[1]-'0'; - *min = s[3]-'0'; - *pat = s[5]-'0'; - return true; - } - /* Bad formatted string */ - return false; -} - -int file_rename( const char *oldfname, const char *newfname, const char *prefix = NULL ) -{ - int retval = 0; - int ch; - - char oldf[20], newf[20]; - - if (prefix) { - strcpy(oldf, prefix); - strcpy(newf, prefix); - } - - strcat(oldf, oldfname); - strcat(newf, newfname); - - FILE *fpold = fopen(oldf, "r"); // src file - FILE *fpnew = fopen(newf, "w"); // dest file - - while (1) { // Copy src to dest - ch = fgetc(fpold); // until src EOF read. - if (ch == EOF) break; - fputc(ch, fpnew); - } - - fclose(fpnew); - fclose(fpold); - - fpnew = fopen(newf, "r"); // Reopen dest to insure - if(fpnew == NULL) { // that it was created. - retval = (-1); // Return Error. - } - else { - fclose(fpnew); - remove(oldf); // Remove original file. - retval = (0); // Return Success. - } - return (retval); -} diff --git a/legacy/app/util.h b/legacy/app/util.h deleted file mode 100644 index ab932da..0000000 --- a/legacy/app/util.h +++ /dev/null @@ -1,12 +0,0 @@ -#ifndef UTIL_H_ -#define UTIL_H_ - -#include - -void int2bin6(int value, bool * bin); -uint32_t str2uint( char *s ); -void int2str( char *s, int num ); -bool version_str2int( char *s, uint8_t *maj, uint8_t *min, uint8_t *pat ); - -int file_rename( const char *oldfname, const char *newfname, const char *prefix ); -#endif diff --git a/legacy/app/watchdog.h b/legacy/app/watchdog.h deleted file mode 100644 index e3abcfa..0000000 --- a/legacy/app/watchdog.h +++ /dev/null @@ -1,32 +0,0 @@ -#ifndef WATCHDOG_H -#define WATCHDOG_H - -#include "mbed.h" - -// Based on Simon's Watchdog code from -// http://mbed.org/forum/mbed/topic/508/ - -class Watchdog { -public: -// Load timeout value in watchdog timer and enable - void kick(float s) { - LPC_WDT->WDCLKSEL = 0x1; // Set CLK src to PCLK - uint32_t clk = SystemCoreClock / 16; // WD has a fixed /4 prescaler, PCLK default is /4 - LPC_WDT->WDTC = s * (float)clk; - LPC_WDT->WDMOD = 0x3; // Enabled and Reset - kick(); - } -// "kick" or "feed" the dog - reset the watchdog timer -// by writing this required bit pattern - void kick() { - LPC_WDT->WDFEED = 0xAA; - LPC_WDT->WDFEED = 0x55; - } - int check_overflow_flag() { - return (LPC_WDT->WDMOD >> 2) & 1; - } - void clear_overflow_flag() { - LPC_WDT->WDMOD &= ~(1 << 2); - } -}; -#endif diff --git a/legacy/bootloader/.mbed b/legacy/bootloader/.mbed deleted file mode 100644 index e87b56d..0000000 --- a/legacy/bootloader/.mbed +++ /dev/null @@ -1 +0,0 @@ -ROOT=. diff --git a/legacy/bootloader/boot.h b/legacy/bootloader/boot.h deleted file mode 100644 index 7946d06..0000000 --- a/legacy/bootloader/boot.h +++ /dev/null @@ -1,20 +0,0 @@ -#ifndef BOOTLOADER_H_ -#define BOOTLOADER_H_ - -#define BOOT_SECTOR_START 0 -#define BOOT_SECTOR_END 7 -#define BOOT_ADDRESS_OFFSET 0x0000 - -#define RUNTIME_SECTOR_START 8 -#define RUNTIME_SECTOR_END 21 -#define RUNTIME_ADDRESS_OFFSET 0x8000 - -#define UPDATE_SECTOR_START 22 -#define UPDATE_SECTOR_END 29 -#define UPDATE_ADDRESS_OFFSET 0x40000 - -#define BOOTLOADER_MAGIC_WORD 0xAAAAAAAA - -void update_firmware( void ); - -#endif diff --git a/legacy/bootloader/bootloader.cpp b/legacy/bootloader/bootloader.cpp deleted file mode 100644 index a8060a7..0000000 --- a/legacy/bootloader/bootloader.cpp +++ /dev/null @@ -1,89 +0,0 @@ -#include "mbed.h" - -#define BOOTLOADER_MAGIC_WORD 0xAAAAAAAA -#define UPDATE_ADDRESS_OFFSET 0x48000 - -RawSerial pc(P0_2, P0_3); // Serial USB port. (NOTE: All printf() calls are redirected to this port) -FlashIAP flash; -const uint32_t page_size = flash.get_page_size(); -const uint32_t flash_size = flash.get_flash_size(); - -typedef struct { - uint8_t version[3]; - uint8_t fw_type; - uint32_t upgr_fw_id; -} fw_info; - -void update( uint32_t address ) -{ - char *page_buffer = new char[page_size]; - uint32_t addr = address; - uint32_t next_sector = addr + flash.get_sector_size(addr); - bool sector_erased = false; - uint32_t src = UPDATE_ADDRESS_OFFSET; - - while (src < flash_size) { - // Read data for this page - memset(page_buffer, 0, sizeof(page_buffer)); - memcpy(page_buffer, (uint32_t *) src, page_size); - - // Erase this page if it hasn't been erased - if (!sector_erased) { - flash.erase(addr, flash.get_sector_size(addr)); - sector_erased = true; - } - - // Program page - flash.program(page_buffer, addr, page_size); - - addr += page_size; - src += page_size; - if (addr >= next_sector) { - next_sector = addr + flash.get_sector_size(addr); - sector_erased = false; - } - } - - /* Erase the update sector of the Flash */ - src = UPDATE_ADDRESS_OFFSET; - while (src < flash_size) { - flash.erase(src, flash.get_sector_size(src)); - src += flash.get_sector_size(src); - } - - delete[] page_buffer; -} - -int main( void ) -{ - fw_info header; - - flash.init(); - - pc.baud(115200); - - flash.read(&header, (flash_size - sizeof(fw_info)), sizeof(fw_info)); - - if(header.upgr_fw_id == BOOTLOADER_MAGIC_WORD) { - if (header.fw_type == 1) { - printf("[BOOTLOADER] Updating firmware to new version %d.%d.%d\r\n", header.version[0], header.version[1], header.version[2]); - update(POST_APPLICATION_ADDR); - } else if (header.fw_type == 2) { - printf("[BOOTLOADER] New bootloader firmware was sent! Erasing the temporary data\r\n"); - /* Erase the update sector of the Flash */ - uint32_t src = UPDATE_ADDRESS_OFFSET; - while (src < flash_size) { - flash.erase(src, flash.get_sector_size(src)); - src += flash.get_sector_size(src); - } - } else { - printf("[BOOTLOADER] Unknown firmware type, ignoring\r\n"); - } - } - - flash.deinit(); - - mbed_start_application(POST_APPLICATION_ADDR); - - while (1); -} diff --git a/legacy/bootloader/mbed_app.json b/legacy/bootloader/mbed_app.json deleted file mode 100644 index c208feb..0000000 --- a/legacy/bootloader/mbed_app.json +++ /dev/null @@ -1,7 +0,0 @@ -{ - "target_overrides": { - "*": { - "target.restrict_size": "0x10000" - } - } -} diff --git a/legacy/bootloader/mbed_settings.py b/legacy/bootloader/mbed_settings.py deleted file mode 100644 index 494f60d..0000000 --- a/legacy/bootloader/mbed_settings.py +++ /dev/null @@ -1,45 +0,0 @@ -""" -mbed SDK -Copyright (c) 2016 ARM Limited - -Licensed under the Apache License, Version 2.0 (the "License"); -you may not use this file except in compliance with the License. -You may obtain a copy of the License at - -http://www.apache.org/licenses/LICENSE-2.0 - -Unless required by applicable law or agreed to in writing, software -distributed under the License is distributed on an "AS IS" BASIS, -WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -See the License for the specific language governing permissions and -limitations under the License. -""" - -from os.path import join, abspath, dirname - -#ROOT = abspath(join(dirname(__file__), ".")) - -############################################################################## -# Build System Settings -############################################################################## -#BUILD_DIR = abspath(join(ROOT, "build")) - -# ARM -#ARM_PATH = "C:/Program Files/ARM" - -# GCC ARM -#GCC_ARM_PATH = "" - -# IAR -#IAR_PATH = "C:/Program Files (x86)/IAR Systems/Embedded Workbench 7.0/arm" - -# Goanna static analyser. Please overload it in private_settings.py -#GOANNA_PATH = "c:/Program Files (x86)/RedLizards/Goanna Central 3.2.3/bin" - -#BUILD_OPTIONS = [] - -# mbed.org username -#MBED_ORG_USER = "" - -# Print compiler warnings and errors as link format -#PRINT_COMPILER_OUTPUT_AS_LINK = False diff --git a/legacy/compile.sh b/legacy/compile.sh deleted file mode 100755 index f2ffcff..0000000 --- a/legacy/compile.sh +++ /dev/null @@ -1,5 +0,0 @@ -#!/bin/bash -set -e - -mbed compile -j 4 -t GCC_ARM -m LPC1768 --source bootloader/ --source mbed-os/ --build BUILD/bootloader -mbed compile -j 4 -t GCC_ARM -m LPC1768 --source app/ --source mbed-os/ -N rffe-uc-firmware --build BUILD/rffe-uc-firmware diff --git a/legacy/mbed-os b/legacy/mbed-os deleted file mode 160000 index 5a8a598..0000000 --- a/legacy/mbed-os +++ /dev/null @@ -1 +0,0 @@ -Subproject commit 5a8a598773fa9d2ab40a42b66b19bcfd1583fdeb diff --git a/legacy/mbed_app.json b/legacy/mbed_app.json deleted file mode 100644 index ce6f9d9..0000000 --- a/legacy/mbed_app.json +++ /dev/null @@ -1,20 +0,0 @@ -{ - "target_overrides": { - "*": { - "target.restrict_size": "0x38000", - "target.bootloader_img": "../BUILD/bootloader/bootloader.bin", - "target.features_add": ["LWIP", "COMMON_PAL"], - "mbed-trace.enable": true, - "platform.stdio-convert-newlines": true, - "platform.stdio-baud-rate": 115200, - "platform.default-serial-baud-rate": 115200, - "platform.error-filename-capture-enabled": true, - "platform.memory-tracing-enabled": true, - "target.network-default-interface-type": "ETHERNET", - "lwip.use-mbed-trace": false, - "lwip.debug-enabled": false, - "filesystem.present": false, - "events.present": true - } - } -} diff --git a/legacy/mbed_settings.py b/legacy/mbed_settings.py deleted file mode 100644 index 494f60d..0000000 --- a/legacy/mbed_settings.py +++ /dev/null @@ -1,45 +0,0 @@ -""" -mbed SDK -Copyright (c) 2016 ARM Limited - -Licensed under the Apache License, Version 2.0 (the "License"); -you may not use this file except in compliance with the License. -You may obtain a copy of the License at - -http://www.apache.org/licenses/LICENSE-2.0 - -Unless required by applicable law or agreed to in writing, software -distributed under the License is distributed on an "AS IS" BASIS, -WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -See the License for the specific language governing permissions and -limitations under the License. -""" - -from os.path import join, abspath, dirname - -#ROOT = abspath(join(dirname(__file__), ".")) - -############################################################################## -# Build System Settings -############################################################################## -#BUILD_DIR = abspath(join(ROOT, "build")) - -# ARM -#ARM_PATH = "C:/Program Files/ARM" - -# GCC ARM -#GCC_ARM_PATH = "" - -# IAR -#IAR_PATH = "C:/Program Files (x86)/IAR Systems/Embedded Workbench 7.0/arm" - -# Goanna static analyser. Please overload it in private_settings.py -#GOANNA_PATH = "c:/Program Files (x86)/RedLizards/Goanna Central 3.2.3/bin" - -#BUILD_OPTIONS = [] - -# mbed.org username -#MBED_ORG_USER = "" - -# Print compiler warnings and errors as link format -#PRINT_COMPILER_OUTPUT_AS_LINK = False From 69e1a901afa0eaae66883f56ae7371435a32cbd8 Mon Sep 17 00:00:00 2001 From: Augusto Fraga Giachero Date: Mon, 17 Feb 2020 10:42:28 -0300 Subject: [PATCH 6/8] The flash rule should depend upon the final .bin file [bootloader] Although OpenOCD supports ELF files, it will erase all the flash area, (the application firmware will be erased). Flashing a raw binary file only erases the necessary flash sectors. --- bootloader/Makefile | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/bootloader/Makefile b/bootloader/Makefile index da4223b..acc1cfb 100644 --- a/bootloader/Makefile +++ b/bootloader/Makefile @@ -14,7 +14,7 @@ CFLAGS = -fdata-sections -ffunction-sections -g3 -Wall -mcpu=cortex-m3 -mlit ASFLAGS = $(CFLAGS) LDFLAGS = -T $(LDSCRIPT) -Wl,--gc-sections --specs=nano.specs --specs=nosys.specs -.PHONY: all clean flash burn hex bin +.PHONY: all clean flash all: $(PRJ_NAME).bin @@ -33,11 +33,11 @@ $(PRJ_NAME).elf: $(OBJ) clean: rm -f $(OBJ) $(PRJ_NAME).elf $(PRJ_NAME)-pad.elf $(PRJ_NAME).hex $(PRJ_NAME).bin $(SRCDIR)/*.d -flash: bin +flash: $(PRJ_NAME).bin $(PROGRAMMER) $(PGFLAGS) $(PRJ_NAME)-pad.elf: $(PRJ_NAME).elf $(OBJCOPY) --gap-fill 0xFF --pad-to 0x10000 $< $@ $(PRJ_NAME).bin: $(PRJ_NAME)-pad.elf - $(OBJCOPY) -O binary $< $(PRJ_NAME).bin + $(OBJCOPY) -O binary $< $@ From c70cde9574714068b42686d378f5ec6fc2aacd4f Mon Sep 17 00:00:00 2001 From: Augusto Fraga Giachero Date: Tue, 3 Mar 2020 12:39:32 -0300 Subject: [PATCH 7/8] Bootloader documentation [bootloader] --- README.md | 2 +- bootloader/README.md | 21 +++++++++++++++++++++ 2 files changed, 22 insertions(+), 1 deletion(-) create mode 100644 bootloader/README.md diff --git a/README.md b/README.md index cb38340..868b5c2 100644 --- a/README.md +++ b/README.md @@ -48,7 +48,7 @@ Make sure to include the ```your_prefix_path/usr/bin``` directory in your ```PAT ## Flashing -The nuttx.bin image does not contains the bootloader and is expected to be loaded at 0x00010000, so if you are flashing blank uCs, flash the bootloader from legacy/bootloader first. +The nuttx.bin image does not contains the bootloader and is expected to be loaded at 0x00010000, so if you are flashing blank uCs, flash the bootloader from bootloader/ first. ### Via CMSIS-DAP diff --git a/bootloader/README.md b/bootloader/README.md new file mode 100644 index 0000000..726d422 --- /dev/null +++ b/bootloader/README.md @@ -0,0 +1,21 @@ +# RFFE Bootloader + +The flash memory is divided in three regions: +* Bootloader 0x00000000 - 0x0000FFFF (64KiB); +* Application 0x00010000 - 0x00047FFF (224KiB); +* Firmware update 0x00048000 - 0x00080000 (224KiB). + +``` +New firmware record at flash address 0x0007FFF0: + + +-----------------+-----------------+-----------------+---------------+------------+ + | Major version | Minor version | Build version | Firmware type | Magic word | + | number (1 byte) | number (1 byte) | number (1 byte) | (1 byte) | (4 bytes) | + +-----------------+-----------------+-----------------+---------------+------------+ + +``` + +The bootloader checks the last 32bit word in flash is equal to 0xAAAAAAAA (firmware update magic word), if it is, the new firmware will be copied from 0x00048000 to 0x00010000 or 0x00000000 depending on the firmware type (application or bootloader). After finishing the copying, the bootloader will erase the last flash sector to prevent unnecessary rewrites to flash after reset. + +The Firmware type byte indicates what to update, (0x01: application, 0x02: bootloader). All flash writing logic is executed from SRAM to allow self updating. + From 19754191c45d2429c2e4e69d9f0da1bae56a4994 Mon Sep 17 00:00:00 2001 From: Augusto Fraga Giachero Date: Tue, 3 Mar 2020 12:46:23 -0300 Subject: [PATCH 8/8] Fix I2C crashes [nuttx] A bug in the lpc17 I2C driver would cause random crashes compromising the overall system stability. I've patched nuttx to fix this issue. --- nuttx | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/nuttx b/nuttx index adb657b..4f632e2 160000 --- a/nuttx +++ b/nuttx @@ -1 +1 @@ -Subproject commit adb657b95e6a274e160fddef364d811de2e3cfda +Subproject commit 4f632e2eba06991b1e286503170d483f037b3d1b