diff --git a/core/common/include/hw/wb_fmc_adc_common_regs.h b/core/common/include/hw/wb_fmc_adc_common_regs.h
index 22748bc3..500099c7 100644
--- a/core/common/include/hw/wb_fmc_adc_common_regs.h
+++ b/core/common/include/hw/wb_fmc_adc_common_regs.h
@@ -3,7 +3,7 @@
 
   * File           : wb_fmc_adc_common_regs.h
   * Author         : auto-generated by wbgen2 from wb_fmc_adc_common_regs.wb
-  * Created        : Mon Apr 18 09:02:33 2016
+  * Created        : Fri Jul 21 13:54:07 2017
   * Standard       : ANSI C
 
     THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE wb_fmc_adc_common_regs.wb
@@ -79,11 +79,14 @@
 /* definitions for field: Led 3 in reg: Monitor and FMC status control register */
 #define WB_FMC_ADC_COMMON_CSR_MONITOR_LED3    WBGEN2_GEN_MASK(3, 1)
 
+/* definitions for field: MMCM reset in reg: Monitor and FMC status control register */
+#define WB_FMC_ADC_COMMON_CSR_MONITOR_MMCM_RST WBGEN2_GEN_MASK(4, 1)
+
 /* definitions for field: Reserved in reg: Monitor and FMC status control register */
-#define WB_FMC_ADC_COMMON_CSR_MONITOR_RESERVED_MASK WBGEN2_GEN_MASK(4, 28)
-#define WB_FMC_ADC_COMMON_CSR_MONITOR_RESERVED_SHIFT 4
-#define WB_FMC_ADC_COMMON_CSR_MONITOR_RESERVED_W(value) WBGEN2_GEN_WRITE(value, 4, 28)
-#define WB_FMC_ADC_COMMON_CSR_MONITOR_RESERVED_R(reg) WBGEN2_GEN_READ(reg, 4, 28)
+#define WB_FMC_ADC_COMMON_CSR_MONITOR_RESERVED_MASK WBGEN2_GEN_MASK(5, 27)
+#define WB_FMC_ADC_COMMON_CSR_MONITOR_RESERVED_SHIFT 5
+#define WB_FMC_ADC_COMMON_CSR_MONITOR_RESERVED_W(value) WBGEN2_GEN_WRITE(value, 5, 27)
+#define WB_FMC_ADC_COMMON_CSR_MONITOR_RESERVED_R(reg) WBGEN2_GEN_READ(reg, 5, 27)
 /* [0x0]: REG Status register */
 #define WB_FMC_ADC_COMMON_CSR_REG_FMC_STATUS 0x00000000
 /* [0x4]: REG Trigger control */
diff --git a/core/common/include/hw/wb_pos_calc_regs.h b/core/common/include/hw/wb_pos_calc_regs.h
index 98b1ea92..044e6b16 100644
--- a/core/common/include/hw/wb_pos_calc_regs.h
+++ b/core/common/include/hw/wb_pos_calc_regs.h
@@ -3,7 +3,7 @@
 
   * File           : pos_calc_regs.h
   * Author         : auto-generated by wbgen2 from wb_pos_calc_regs.wb
-  * Created        : Mon Jan 23 10:11:17 2017
+  * Created        : Fri Jul 14 16:40:58 2017
   * Standard       : ANSI C
 
     THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE wb_pos_calc_regs.wb
@@ -11,6 +11,9 @@
 
 */
 
+/* Modified to include 32-bit register modifier. This needed a 64-bit 
+ * shitft macro to avoid "left shift count >= width of type" errors*/
+
 #ifndef __WBGEN2_REGDEFS_WB_POS_CALC_REGS_WB
 #define __WBGEN2_REGDEFS_WB_POS_CALC_REGS_WB
 
@@ -22,321 +25,321 @@
 #error "Unsupported compiler?"
 #endif
 
-#ifndef __WBGEN2_MACROS_DEFINED__
-#define __WBGEN2_MACROS_DEFINED__
-#define WBGEN2_GEN_MASK(offset, size) (((1<<(size))-1) << (offset))
-#define WBGEN2_GEN_WRITE(value, offset, size) (((value) & ((1<<(size))-1)) << (offset))
-#define WBGEN2_GEN_READ(reg, offset, size) (((reg) >> (offset)) & ((1<<(size))-1))
-#define WBGEN2_SIGN_EXTEND(value, bits) (((value) & (1<<bits) ? ~((1<<(bits))-1): 0 ) | (value))
+#ifndef __WBGEN2_DSP_MACROS_DEFINED__
+#define __WBGEN2_DSP_MACROS_DEFINED__
+#define WBGEN2_DSP_GEN_MASK(offset, size) ((((uint64_t)1<<(size))-1) << (offset))
+#define WBGEN2_DSP_GEN_WRITE(value, offset, size) (((value) & (((uint64_t)1<<(size))-1)) << (offset))
+#define WBGEN2_DSP_GEN_READ(reg, offset, size) (((reg) >> (offset)) & (((uint64_t)1<<(size))-1))
+#define WBGEN2_DSP_SIGN_EXTEND(value, bits) (((value) & ((uint64_t)1<<bits) ? ~(((uint64_t)1<<(bits))-1): 0 ) | (value))
 #endif
 
 
 /* definitions for register: Config divisor threshold TBT register */
 
 /* definitions for field: Config divisor threshold TBT in reg: Config divisor threshold TBT register */
-#define POS_CALC_DS_TBT_THRES_VAL_MASK        WBGEN2_GEN_MASK(0, 26)
+#define POS_CALC_DS_TBT_THRES_VAL_MASK        WBGEN2_DSP_GEN_MASK(0, 26)
 #define POS_CALC_DS_TBT_THRES_VAL_SHIFT       0
-#define POS_CALC_DS_TBT_THRES_VAL_W(value)    WBGEN2_GEN_WRITE(value, 0, 26)
-#define POS_CALC_DS_TBT_THRES_VAL_R(reg)      WBGEN2_GEN_READ(reg, 0, 26)
+#define POS_CALC_DS_TBT_THRES_VAL_W(value)    WBGEN2_DSP_GEN_WRITE(value, 0, 26)
+#define POS_CALC_DS_TBT_THRES_VAL_R(reg)      WBGEN2_DSP_GEN_READ(reg, 0, 26)
 
 /* definitions for field: Reserved in reg: Config divisor threshold TBT register */
-#define POS_CALC_DS_TBT_THRES_RESERVED_MASK   WBGEN2_GEN_MASK(26, 6)
+#define POS_CALC_DS_TBT_THRES_RESERVED_MASK   WBGEN2_DSP_GEN_MASK(26, 6)
 #define POS_CALC_DS_TBT_THRES_RESERVED_SHIFT  26
-#define POS_CALC_DS_TBT_THRES_RESERVED_W(value) WBGEN2_GEN_WRITE(value, 26, 6)
-#define POS_CALC_DS_TBT_THRES_RESERVED_R(reg) WBGEN2_GEN_READ(reg, 26, 6)
+#define POS_CALC_DS_TBT_THRES_RESERVED_W(value) WBGEN2_DSP_GEN_WRITE(value, 26, 6)
+#define POS_CALC_DS_TBT_THRES_RESERVED_R(reg) WBGEN2_DSP_GEN_READ(reg, 26, 6)
 
 /* definitions for register: Config divisor threshold FOFB register */
 
 /* definitions for field: Config divisor threshold FOFB in reg: Config divisor threshold FOFB register */
-#define POS_CALC_DS_FOFB_THRES_VAL_MASK       WBGEN2_GEN_MASK(0, 26)
+#define POS_CALC_DS_FOFB_THRES_VAL_MASK       WBGEN2_DSP_GEN_MASK(0, 26)
 #define POS_CALC_DS_FOFB_THRES_VAL_SHIFT      0
-#define POS_CALC_DS_FOFB_THRES_VAL_W(value)   WBGEN2_GEN_WRITE(value, 0, 26)
-#define POS_CALC_DS_FOFB_THRES_VAL_R(reg)     WBGEN2_GEN_READ(reg, 0, 26)
+#define POS_CALC_DS_FOFB_THRES_VAL_W(value)   WBGEN2_DSP_GEN_WRITE(value, 0, 26)
+#define POS_CALC_DS_FOFB_THRES_VAL_R(reg)     WBGEN2_DSP_GEN_READ(reg, 0, 26)
 
 /* definitions for field: Reserved in reg: Config divisor threshold FOFB register */
-#define POS_CALC_DS_FOFB_THRES_RESERVED_MASK  WBGEN2_GEN_MASK(26, 6)
+#define POS_CALC_DS_FOFB_THRES_RESERVED_MASK  WBGEN2_DSP_GEN_MASK(26, 6)
 #define POS_CALC_DS_FOFB_THRES_RESERVED_SHIFT 26
-#define POS_CALC_DS_FOFB_THRES_RESERVED_W(value) WBGEN2_GEN_WRITE(value, 26, 6)
-#define POS_CALC_DS_FOFB_THRES_RESERVED_R(reg) WBGEN2_GEN_READ(reg, 26, 6)
+#define POS_CALC_DS_FOFB_THRES_RESERVED_W(value) WBGEN2_DSP_GEN_WRITE(value, 26, 6)
+#define POS_CALC_DS_FOFB_THRES_RESERVED_R(reg) WBGEN2_DSP_GEN_READ(reg, 26, 6)
 
 /* definitions for register: Config divisor threshold Monit. register */
 
 /* definitions for field: Config Divisor Threshold Monit. in reg: Config divisor threshold Monit. register */
-#define POS_CALC_DS_MONIT_THRES_VAL_MASK      WBGEN2_GEN_MASK(0, 26)
+#define POS_CALC_DS_MONIT_THRES_VAL_MASK      WBGEN2_DSP_GEN_MASK(0, 26)
 #define POS_CALC_DS_MONIT_THRES_VAL_SHIFT     0
-#define POS_CALC_DS_MONIT_THRES_VAL_W(value)  WBGEN2_GEN_WRITE(value, 0, 26)
-#define POS_CALC_DS_MONIT_THRES_VAL_R(reg)    WBGEN2_GEN_READ(reg, 0, 26)
+#define POS_CALC_DS_MONIT_THRES_VAL_W(value)  WBGEN2_DSP_GEN_WRITE(value, 0, 26)
+#define POS_CALC_DS_MONIT_THRES_VAL_R(reg)    WBGEN2_DSP_GEN_READ(reg, 0, 26)
 
 /* definitions for field: Reserved in reg: Config divisor threshold Monit. register */
-#define POS_CALC_DS_MONIT_THRES_RESERVED_MASK WBGEN2_GEN_MASK(26, 6)
+#define POS_CALC_DS_MONIT_THRES_RESERVED_MASK WBGEN2_DSP_GEN_MASK(26, 6)
 #define POS_CALC_DS_MONIT_THRES_RESERVED_SHIFT 26
-#define POS_CALC_DS_MONIT_THRES_RESERVED_W(value) WBGEN2_GEN_WRITE(value, 26, 6)
-#define POS_CALC_DS_MONIT_THRES_RESERVED_R(reg) WBGEN2_GEN_READ(reg, 26, 6)
+#define POS_CALC_DS_MONIT_THRES_RESERVED_W(value) WBGEN2_DSP_GEN_WRITE(value, 26, 6)
+#define POS_CALC_DS_MONIT_THRES_RESERVED_R(reg) WBGEN2_DSP_GEN_READ(reg, 26, 6)
 
 /* definitions for register: BPM sensitivity (X axis) parameter register */
 
 /* definitions for field: BPM sensitivity (X axis) parameter register in reg: BPM sensitivity (X axis) parameter register */
-#define POS_CALC_KX_VAL_MASK                  WBGEN2_GEN_MASK(0, 25)
+#define POS_CALC_KX_VAL_MASK                  WBGEN2_DSP_GEN_MASK(0, 25)
 #define POS_CALC_KX_VAL_SHIFT                 0
-#define POS_CALC_KX_VAL_W(value)              WBGEN2_GEN_WRITE(value, 0, 25)
-#define POS_CALC_KX_VAL_R(reg)                WBGEN2_GEN_READ(reg, 0, 25)
+#define POS_CALC_KX_VAL_W(value)              WBGEN2_DSP_GEN_WRITE(value, 0, 25)
+#define POS_CALC_KX_VAL_R(reg)                WBGEN2_DSP_GEN_READ(reg, 0, 25)
 
 /* definitions for field: Reserved in reg: BPM sensitivity (X axis) parameter register */
-#define POS_CALC_KX_RESERVED_MASK             WBGEN2_GEN_MASK(25, 7)
+#define POS_CALC_KX_RESERVED_MASK             WBGEN2_DSP_GEN_MASK(25, 7)
 #define POS_CALC_KX_RESERVED_SHIFT            25
-#define POS_CALC_KX_RESERVED_W(value)         WBGEN2_GEN_WRITE(value, 25, 7)
-#define POS_CALC_KX_RESERVED_R(reg)           WBGEN2_GEN_READ(reg, 25, 7)
+#define POS_CALC_KX_RESERVED_W(value)         WBGEN2_DSP_GEN_WRITE(value, 25, 7)
+#define POS_CALC_KX_RESERVED_R(reg)           WBGEN2_DSP_GEN_READ(reg, 25, 7)
 
 /* definitions for register: BPM sensitivity (Y axis) parameter register */
 
 /* definitions for field: BPM sensitivity (Y axis) parameter register in reg: BPM sensitivity (Y axis) parameter register */
-#define POS_CALC_KY_VAL_MASK                  WBGEN2_GEN_MASK(0, 25)
+#define POS_CALC_KY_VAL_MASK                  WBGEN2_DSP_GEN_MASK(0, 25)
 #define POS_CALC_KY_VAL_SHIFT                 0
-#define POS_CALC_KY_VAL_W(value)              WBGEN2_GEN_WRITE(value, 0, 25)
-#define POS_CALC_KY_VAL_R(reg)                WBGEN2_GEN_READ(reg, 0, 25)
+#define POS_CALC_KY_VAL_W(value)              WBGEN2_DSP_GEN_WRITE(value, 0, 25)
+#define POS_CALC_KY_VAL_R(reg)                WBGEN2_DSP_GEN_READ(reg, 0, 25)
 
 /* definitions for field: Reserved in reg: BPM sensitivity (Y axis) parameter register */
-#define POS_CALC_KY_RESERVED_MASK             WBGEN2_GEN_MASK(25, 7)
+#define POS_CALC_KY_RESERVED_MASK             WBGEN2_DSP_GEN_MASK(25, 7)
 #define POS_CALC_KY_RESERVED_SHIFT            25
-#define POS_CALC_KY_RESERVED_W(value)         WBGEN2_GEN_WRITE(value, 25, 7)
-#define POS_CALC_KY_RESERVED_R(reg)           WBGEN2_GEN_READ(reg, 25, 7)
+#define POS_CALC_KY_RESERVED_W(value)         WBGEN2_DSP_GEN_WRITE(value, 25, 7)
+#define POS_CALC_KY_RESERVED_R(reg)           WBGEN2_DSP_GEN_READ(reg, 25, 7)
 
 /* definitions for register: BPM sensitivity (Sum) parameter register */
 
 /* definitions for field: BPM sensitivity (Sum) parameter register in reg: BPM sensitivity (Sum) parameter register */
-#define POS_CALC_KSUM_VAL_MASK                WBGEN2_GEN_MASK(0, 25)
+#define POS_CALC_KSUM_VAL_MASK                WBGEN2_DSP_GEN_MASK(0, 25)
 #define POS_CALC_KSUM_VAL_SHIFT               0
-#define POS_CALC_KSUM_VAL_W(value)            WBGEN2_GEN_WRITE(value, 0, 25)
-#define POS_CALC_KSUM_VAL_R(reg)              WBGEN2_GEN_READ(reg, 0, 25)
+#define POS_CALC_KSUM_VAL_W(value)            WBGEN2_DSP_GEN_WRITE(value, 0, 25)
+#define POS_CALC_KSUM_VAL_R(reg)              WBGEN2_DSP_GEN_READ(reg, 0, 25)
 
 /* definitions for field: Reserved in reg: BPM sensitivity (Sum) parameter register */
-#define POS_CALC_KSUM_RESERVED_MASK           WBGEN2_GEN_MASK(25, 7)
+#define POS_CALC_KSUM_RESERVED_MASK           WBGEN2_DSP_GEN_MASK(25, 7)
 #define POS_CALC_KSUM_RESERVED_SHIFT          25
-#define POS_CALC_KSUM_RESERVED_W(value)       WBGEN2_GEN_WRITE(value, 25, 7)
-#define POS_CALC_KSUM_RESERVED_R(reg)         WBGEN2_GEN_READ(reg, 25, 7)
+#define POS_CALC_KSUM_RESERVED_W(value)       WBGEN2_DSP_GEN_WRITE(value, 25, 7)
+#define POS_CALC_KSUM_RESERVED_R(reg)         WBGEN2_DSP_GEN_READ(reg, 25, 7)
 
 /* definitions for register: DSP TBT incorrect TDM counter */
 
 /* definitions for field: TBT incorrect counter for channels 0/1 (multiplexed) in reg: DSP TBT incorrect TDM counter */
-#define POS_CALC_DSP_CTNR_TBT_CH01_MASK       WBGEN2_GEN_MASK(0, 16)
+#define POS_CALC_DSP_CTNR_TBT_CH01_MASK       WBGEN2_DSP_GEN_MASK(0, 16)
 #define POS_CALC_DSP_CTNR_TBT_CH01_SHIFT      0
-#define POS_CALC_DSP_CTNR_TBT_CH01_W(value)   WBGEN2_GEN_WRITE(value, 0, 16)
-#define POS_CALC_DSP_CTNR_TBT_CH01_R(reg)     WBGEN2_GEN_READ(reg, 0, 16)
+#define POS_CALC_DSP_CTNR_TBT_CH01_W(value)   WBGEN2_DSP_GEN_WRITE(value, 0, 16)
+#define POS_CALC_DSP_CTNR_TBT_CH01_R(reg)     WBGEN2_DSP_GEN_READ(reg, 0, 16)
 
 /* definitions for field: TBT incorrect counter for channels 2/3 (multiplexed) in reg: DSP TBT incorrect TDM counter */
-#define POS_CALC_DSP_CTNR_TBT_CH23_MASK       WBGEN2_GEN_MASK(16, 16)
+#define POS_CALC_DSP_CTNR_TBT_CH23_MASK       WBGEN2_DSP_GEN_MASK(16, 16)
 #define POS_CALC_DSP_CTNR_TBT_CH23_SHIFT      16
-#define POS_CALC_DSP_CTNR_TBT_CH23_W(value)   WBGEN2_GEN_WRITE(value, 16, 16)
-#define POS_CALC_DSP_CTNR_TBT_CH23_R(reg)     WBGEN2_GEN_READ(reg, 16, 16)
+#define POS_CALC_DSP_CTNR_TBT_CH23_W(value)   WBGEN2_DSP_GEN_WRITE(value, 16, 16)
+#define POS_CALC_DSP_CTNR_TBT_CH23_R(reg)     WBGEN2_DSP_GEN_READ(reg, 16, 16)
 
 /* definitions for register: DSP FOFB incorrect TDM counter */
 
 /* definitions for field: FOFB incorrect counter for channels 0/1 (multiplexed) in reg: DSP FOFB incorrect TDM counter */
-#define POS_CALC_DSP_CTNR_FOFB_CH01_MASK      WBGEN2_GEN_MASK(0, 16)
+#define POS_CALC_DSP_CTNR_FOFB_CH01_MASK      WBGEN2_DSP_GEN_MASK(0, 16)
 #define POS_CALC_DSP_CTNR_FOFB_CH01_SHIFT     0
-#define POS_CALC_DSP_CTNR_FOFB_CH01_W(value)  WBGEN2_GEN_WRITE(value, 0, 16)
-#define POS_CALC_DSP_CTNR_FOFB_CH01_R(reg)    WBGEN2_GEN_READ(reg, 0, 16)
+#define POS_CALC_DSP_CTNR_FOFB_CH01_W(value)  WBGEN2_DSP_GEN_WRITE(value, 0, 16)
+#define POS_CALC_DSP_CTNR_FOFB_CH01_R(reg)    WBGEN2_DSP_GEN_READ(reg, 0, 16)
 
 /* definitions for field: FOFB incorrect counter for channels 2/3 (multiplexed) in reg: DSP FOFB incorrect TDM counter */
-#define POS_CALC_DSP_CTNR_FOFB_CH23_MASK      WBGEN2_GEN_MASK(16, 16)
+#define POS_CALC_DSP_CTNR_FOFB_CH23_MASK      WBGEN2_DSP_GEN_MASK(16, 16)
 #define POS_CALC_DSP_CTNR_FOFB_CH23_SHIFT     16
-#define POS_CALC_DSP_CTNR_FOFB_CH23_W(value)  WBGEN2_GEN_WRITE(value, 16, 16)
-#define POS_CALC_DSP_CTNR_FOFB_CH23_R(reg)    WBGEN2_GEN_READ(reg, 16, 16)
+#define POS_CALC_DSP_CTNR_FOFB_CH23_W(value)  WBGEN2_DSP_GEN_WRITE(value, 16, 16)
+#define POS_CALC_DSP_CTNR_FOFB_CH23_R(reg)    WBGEN2_DSP_GEN_READ(reg, 16, 16)
 
 /* definitions for register: DSP Monit. incorrect TDM counter part 1 */
 
 /* definitions for field: Monit. CIC incorrect counter for channels 0/1/2/3 (multiplexed) in reg: DSP Monit. incorrect TDM counter part 1 */
-#define POS_CALC_DSP_CTNR1_MONIT_CIC_MASK     WBGEN2_GEN_MASK(0, 16)
+#define POS_CALC_DSP_CTNR1_MONIT_CIC_MASK     WBGEN2_DSP_GEN_MASK(0, 16)
 #define POS_CALC_DSP_CTNR1_MONIT_CIC_SHIFT    0
-#define POS_CALC_DSP_CTNR1_MONIT_CIC_W(value) WBGEN2_GEN_WRITE(value, 0, 16)
-#define POS_CALC_DSP_CTNR1_MONIT_CIC_R(reg)   WBGEN2_GEN_READ(reg, 0, 16)
+#define POS_CALC_DSP_CTNR1_MONIT_CIC_W(value) WBGEN2_DSP_GEN_WRITE(value, 0, 16)
+#define POS_CALC_DSP_CTNR1_MONIT_CIC_R(reg)   WBGEN2_DSP_GEN_READ(reg, 0, 16)
 
 /* definitions for field: Monit. CFIR incorrect counter for channels 0/1/2/3 (multiplexed) in reg: DSP Monit. incorrect TDM counter part 1 */
-#define POS_CALC_DSP_CTNR1_MONIT_CFIR_MASK    WBGEN2_GEN_MASK(16, 16)
+#define POS_CALC_DSP_CTNR1_MONIT_CFIR_MASK    WBGEN2_DSP_GEN_MASK(16, 16)
 #define POS_CALC_DSP_CTNR1_MONIT_CFIR_SHIFT   16
-#define POS_CALC_DSP_CTNR1_MONIT_CFIR_W(value) WBGEN2_GEN_WRITE(value, 16, 16)
-#define POS_CALC_DSP_CTNR1_MONIT_CFIR_R(reg)  WBGEN2_GEN_READ(reg, 16, 16)
+#define POS_CALC_DSP_CTNR1_MONIT_CFIR_W(value) WBGEN2_DSP_GEN_WRITE(value, 16, 16)
+#define POS_CALC_DSP_CTNR1_MONIT_CFIR_R(reg)  WBGEN2_DSP_GEN_READ(reg, 16, 16)
 
 /* definitions for register: DSP Monit. incorrect TDM counter part 2 */
 
 /* definitions for field: Monit. PFIR incorrect counter for channels 0/1/2/3 (multiplexed) in reg: DSP Monit. incorrect TDM counter part 2 */
-#define POS_CALC_DSP_CTNR2_MONIT_PFIR_MASK    WBGEN2_GEN_MASK(0, 16)
+#define POS_CALC_DSP_CTNR2_MONIT_PFIR_MASK    WBGEN2_DSP_GEN_MASK(0, 16)
 #define POS_CALC_DSP_CTNR2_MONIT_PFIR_SHIFT   0
-#define POS_CALC_DSP_CTNR2_MONIT_PFIR_W(value) WBGEN2_GEN_WRITE(value, 0, 16)
-#define POS_CALC_DSP_CTNR2_MONIT_PFIR_R(reg)  WBGEN2_GEN_READ(reg, 0, 16)
+#define POS_CALC_DSP_CTNR2_MONIT_PFIR_W(value) WBGEN2_DSP_GEN_WRITE(value, 0, 16)
+#define POS_CALC_DSP_CTNR2_MONIT_PFIR_R(reg)  WBGEN2_DSP_GEN_READ(reg, 0, 16)
 
 /* definitions for field: Monit. 0.1 Hz incorrect counter for channels 0/1/2/3 (multiplexed) in reg: DSP Monit. incorrect TDM counter part 2 */
-#define POS_CALC_DSP_CTNR2_MONIT_FIR_01_MASK  WBGEN2_GEN_MASK(16, 16)
+#define POS_CALC_DSP_CTNR2_MONIT_FIR_01_MASK  WBGEN2_DSP_GEN_MASK(16, 16)
 #define POS_CALC_DSP_CTNR2_MONIT_FIR_01_SHIFT 16
-#define POS_CALC_DSP_CTNR2_MONIT_FIR_01_W(value) WBGEN2_GEN_WRITE(value, 16, 16)
-#define POS_CALC_DSP_CTNR2_MONIT_FIR_01_R(reg) WBGEN2_GEN_READ(reg, 16, 16)
+#define POS_CALC_DSP_CTNR2_MONIT_FIR_01_W(value) WBGEN2_DSP_GEN_WRITE(value, 16, 16)
+#define POS_CALC_DSP_CTNR2_MONIT_FIR_01_R(reg) WBGEN2_DSP_GEN_READ(reg, 16, 16)
 
 /* definitions for register: DSP error clearing */
 
 /* definitions for field: Clear TBT error counters in reg: DSP error clearing */
-#define POS_CALC_DSP_ERR_CLR_TBT              WBGEN2_GEN_MASK(0, 1)
+#define POS_CALC_DSP_ERR_CLR_TBT              WBGEN2_DSP_GEN_MASK(0, 1)
 
 /* definitions for field: Clear FOFB error counters in reg: DSP error clearing */
-#define POS_CALC_DSP_ERR_CLR_FOFB             WBGEN2_GEN_MASK(1, 1)
+#define POS_CALC_DSP_ERR_CLR_FOFB             WBGEN2_DSP_GEN_MASK(1, 1)
 
 /* definitions for field: Clear Monit. CIC and CFIR error counters in reg: DSP error clearing */
-#define POS_CALC_DSP_ERR_CLR_MONIT_PART1      WBGEN2_GEN_MASK(2, 1)
+#define POS_CALC_DSP_ERR_CLR_MONIT_PART1      WBGEN2_DSP_GEN_MASK(2, 1)
 
 /* definitions for field: Clear Monit. PFIR and Monit. 0.1 error counters in reg: DSP error clearing */
-#define POS_CALC_DSP_ERR_CLR_MONIT_PART2      WBGEN2_GEN_MASK(3, 1)
+#define POS_CALC_DSP_ERR_CLR_MONIT_PART2      WBGEN2_DSP_GEN_MASK(3, 1)
 
 /* definitions for register: DDS general config registers for all channels */
 
 /* definitions for field: Valid signal for channel 0 DDS in reg: DDS general config registers for all channels */
-#define POS_CALC_DDS_CFG_VALID_CH0            WBGEN2_GEN_MASK(0, 1)
+#define POS_CALC_DDS_CFG_VALID_CH0            WBGEN2_DSP_GEN_MASK(0, 1)
 
 /* definitions for field: Test data counter for all channels in reg: DDS general config registers for all channels */
-#define POS_CALC_DDS_CFG_TEST_DATA            WBGEN2_GEN_MASK(1, 1)
+#define POS_CALC_DDS_CFG_TEST_DATA            WBGEN2_DSP_GEN_MASK(1, 1)
 
 /* definitions for field: Reserved in reg: DDS general config registers for all channels */
-#define POS_CALC_DDS_CFG_RESERVED_CH0_MASK    WBGEN2_GEN_MASK(2, 6)
+#define POS_CALC_DDS_CFG_RESERVED_CH0_MASK    WBGEN2_DSP_GEN_MASK(2, 6)
 #define POS_CALC_DDS_CFG_RESERVED_CH0_SHIFT   2
-#define POS_CALC_DDS_CFG_RESERVED_CH0_W(value) WBGEN2_GEN_WRITE(value, 2, 6)
-#define POS_CALC_DDS_CFG_RESERVED_CH0_R(reg)  WBGEN2_GEN_READ(reg, 2, 6)
+#define POS_CALC_DDS_CFG_RESERVED_CH0_W(value) WBGEN2_DSP_GEN_WRITE(value, 2, 6)
+#define POS_CALC_DDS_CFG_RESERVED_CH0_R(reg)  WBGEN2_DSP_GEN_READ(reg, 2, 6)
 
 /* definitions for field: Valid signal for channel 1 DDS in reg: DDS general config registers for all channels */
-#define POS_CALC_DDS_CFG_VALID_CH1            WBGEN2_GEN_MASK(8, 1)
+#define POS_CALC_DDS_CFG_VALID_CH1            WBGEN2_DSP_GEN_MASK(8, 1)
 
 /* definitions for field: Reserved in reg: DDS general config registers for all channels */
-#define POS_CALC_DDS_CFG_RESERVED_CH1_MASK    WBGEN2_GEN_MASK(9, 7)
+#define POS_CALC_DDS_CFG_RESERVED_CH1_MASK    WBGEN2_DSP_GEN_MASK(9, 7)
 #define POS_CALC_DDS_CFG_RESERVED_CH1_SHIFT   9
-#define POS_CALC_DDS_CFG_RESERVED_CH1_W(value) WBGEN2_GEN_WRITE(value, 9, 7)
-#define POS_CALC_DDS_CFG_RESERVED_CH1_R(reg)  WBGEN2_GEN_READ(reg, 9, 7)
+#define POS_CALC_DDS_CFG_RESERVED_CH1_W(value) WBGEN2_DSP_GEN_WRITE(value, 9, 7)
+#define POS_CALC_DDS_CFG_RESERVED_CH1_R(reg)  WBGEN2_DSP_GEN_READ(reg, 9, 7)
 
 /* definitions for field: Valid signal for channel 2 DDS in reg: DDS general config registers for all channels */
-#define POS_CALC_DDS_CFG_VALID_CH2            WBGEN2_GEN_MASK(16, 1)
+#define POS_CALC_DDS_CFG_VALID_CH2            WBGEN2_DSP_GEN_MASK(16, 1)
 
 /* definitions for field: Reserved in reg: DDS general config registers for all channels */
-#define POS_CALC_DDS_CFG_RESERVED_CH2_MASK    WBGEN2_GEN_MASK(17, 7)
+#define POS_CALC_DDS_CFG_RESERVED_CH2_MASK    WBGEN2_DSP_GEN_MASK(17, 7)
 #define POS_CALC_DDS_CFG_RESERVED_CH2_SHIFT   17
-#define POS_CALC_DDS_CFG_RESERVED_CH2_W(value) WBGEN2_GEN_WRITE(value, 17, 7)
-#define POS_CALC_DDS_CFG_RESERVED_CH2_R(reg)  WBGEN2_GEN_READ(reg, 17, 7)
+#define POS_CALC_DDS_CFG_RESERVED_CH2_W(value) WBGEN2_DSP_GEN_WRITE(value, 17, 7)
+#define POS_CALC_DDS_CFG_RESERVED_CH2_R(reg)  WBGEN2_DSP_GEN_READ(reg, 17, 7)
 
 /* definitions for field: Valid signal for channel 3 DDS in reg: DDS general config registers for all channels */
-#define POS_CALC_DDS_CFG_VALID_CH3            WBGEN2_GEN_MASK(24, 1)
+#define POS_CALC_DDS_CFG_VALID_CH3            WBGEN2_DSP_GEN_MASK(24, 1)
 
 /* definitions for field: Reserved in reg: DDS general config registers for all channels */
-#define POS_CALC_DDS_CFG_RESERVED_CH3_MASK    WBGEN2_GEN_MASK(25, 7)
+#define POS_CALC_DDS_CFG_RESERVED_CH3_MASK    WBGEN2_DSP_GEN_MASK(25, 7)
 #define POS_CALC_DDS_CFG_RESERVED_CH3_SHIFT   25
-#define POS_CALC_DDS_CFG_RESERVED_CH3_W(value) WBGEN2_GEN_WRITE(value, 25, 7)
-#define POS_CALC_DDS_CFG_RESERVED_CH3_R(reg)  WBGEN2_GEN_READ(reg, 25, 7)
+#define POS_CALC_DDS_CFG_RESERVED_CH3_W(value) WBGEN2_DSP_GEN_WRITE(value, 25, 7)
+#define POS_CALC_DDS_CFG_RESERVED_CH3_R(reg)  WBGEN2_DSP_GEN_READ(reg, 25, 7)
 
 /* definitions for register: DDS phase increment parameter register for channel 0 */
 
 /* definitions for field: DDS phase increment parameter register for channel 0 in reg: DDS phase increment parameter register for channel 0 */
-#define POS_CALC_DDS_PINC_CH0_VAL_MASK        WBGEN2_GEN_MASK(0, 30)
+#define POS_CALC_DDS_PINC_CH0_VAL_MASK        WBGEN2_DSP_GEN_MASK(0, 30)
 #define POS_CALC_DDS_PINC_CH0_VAL_SHIFT       0
-#define POS_CALC_DDS_PINC_CH0_VAL_W(value)    WBGEN2_GEN_WRITE(value, 0, 30)
-#define POS_CALC_DDS_PINC_CH0_VAL_R(reg)      WBGEN2_GEN_READ(reg, 0, 30)
+#define POS_CALC_DDS_PINC_CH0_VAL_W(value)    WBGEN2_DSP_GEN_WRITE(value, 0, 30)
+#define POS_CALC_DDS_PINC_CH0_VAL_R(reg)      WBGEN2_DSP_GEN_READ(reg, 0, 30)
 
 /* definitions for field: Reserved in reg: DDS phase increment parameter register for channel 0 */
-#define POS_CALC_DDS_PINC_CH0_RESERVED_MASK   WBGEN2_GEN_MASK(30, 2)
+#define POS_CALC_DDS_PINC_CH0_RESERVED_MASK   WBGEN2_DSP_GEN_MASK(30, 2)
 #define POS_CALC_DDS_PINC_CH0_RESERVED_SHIFT  30
-#define POS_CALC_DDS_PINC_CH0_RESERVED_W(value) WBGEN2_GEN_WRITE(value, 30, 2)
-#define POS_CALC_DDS_PINC_CH0_RESERVED_R(reg) WBGEN2_GEN_READ(reg, 30, 2)
+#define POS_CALC_DDS_PINC_CH0_RESERVED_W(value) WBGEN2_DSP_GEN_WRITE(value, 30, 2)
+#define POS_CALC_DDS_PINC_CH0_RESERVED_R(reg) WBGEN2_DSP_GEN_READ(reg, 30, 2)
 
 /* definitions for register: DDS phase increment parameter register for channel 1 */
 
 /* definitions for field: DDS phase increment parameter register for channel 1 in reg: DDS phase increment parameter register for channel 1 */
-#define POS_CALC_DDS_PINC_CH1_VAL_MASK        WBGEN2_GEN_MASK(0, 30)
+#define POS_CALC_DDS_PINC_CH1_VAL_MASK        WBGEN2_DSP_GEN_MASK(0, 30)
 #define POS_CALC_DDS_PINC_CH1_VAL_SHIFT       0
-#define POS_CALC_DDS_PINC_CH1_VAL_W(value)    WBGEN2_GEN_WRITE(value, 0, 30)
-#define POS_CALC_DDS_PINC_CH1_VAL_R(reg)      WBGEN2_GEN_READ(reg, 0, 30)
+#define POS_CALC_DDS_PINC_CH1_VAL_W(value)    WBGEN2_DSP_GEN_WRITE(value, 0, 30)
+#define POS_CALC_DDS_PINC_CH1_VAL_R(reg)      WBGEN2_DSP_GEN_READ(reg, 0, 30)
 
 /* definitions for field: Reserved in reg: DDS phase increment parameter register for channel 1 */
-#define POS_CALC_DDS_PINC_CH1_RESERVED_MASK   WBGEN2_GEN_MASK(30, 2)
+#define POS_CALC_DDS_PINC_CH1_RESERVED_MASK   WBGEN2_DSP_GEN_MASK(30, 2)
 #define POS_CALC_DDS_PINC_CH1_RESERVED_SHIFT  30
-#define POS_CALC_DDS_PINC_CH1_RESERVED_W(value) WBGEN2_GEN_WRITE(value, 30, 2)
-#define POS_CALC_DDS_PINC_CH1_RESERVED_R(reg) WBGEN2_GEN_READ(reg, 30, 2)
+#define POS_CALC_DDS_PINC_CH1_RESERVED_W(value) WBGEN2_DSP_GEN_WRITE(value, 30, 2)
+#define POS_CALC_DDS_PINC_CH1_RESERVED_R(reg) WBGEN2_DSP_GEN_READ(reg, 30, 2)
 
 /* definitions for register: DDS phase increment parameter register for channel 2 */
 
 /* definitions for field: DDS phase increment parameter register for channel 2 in reg: DDS phase increment parameter register for channel 2 */
-#define POS_CALC_DDS_PINC_CH2_VAL_MASK        WBGEN2_GEN_MASK(0, 30)
+#define POS_CALC_DDS_PINC_CH2_VAL_MASK        WBGEN2_DSP_GEN_MASK(0, 30)
 #define POS_CALC_DDS_PINC_CH2_VAL_SHIFT       0
-#define POS_CALC_DDS_PINC_CH2_VAL_W(value)    WBGEN2_GEN_WRITE(value, 0, 30)
-#define POS_CALC_DDS_PINC_CH2_VAL_R(reg)      WBGEN2_GEN_READ(reg, 0, 30)
+#define POS_CALC_DDS_PINC_CH2_VAL_W(value)    WBGEN2_DSP_GEN_WRITE(value, 0, 30)
+#define POS_CALC_DDS_PINC_CH2_VAL_R(reg)      WBGEN2_DSP_GEN_READ(reg, 0, 30)
 
 /* definitions for field: Reserved in reg: DDS phase increment parameter register for channel 2 */
-#define POS_CALC_DDS_PINC_CH2_RESERVED_MASK   WBGEN2_GEN_MASK(30, 2)
+#define POS_CALC_DDS_PINC_CH2_RESERVED_MASK   WBGEN2_DSP_GEN_MASK(30, 2)
 #define POS_CALC_DDS_PINC_CH2_RESERVED_SHIFT  30
-#define POS_CALC_DDS_PINC_CH2_RESERVED_W(value) WBGEN2_GEN_WRITE(value, 30, 2)
-#define POS_CALC_DDS_PINC_CH2_RESERVED_R(reg) WBGEN2_GEN_READ(reg, 30, 2)
+#define POS_CALC_DDS_PINC_CH2_RESERVED_W(value) WBGEN2_DSP_GEN_WRITE(value, 30, 2)
+#define POS_CALC_DDS_PINC_CH2_RESERVED_R(reg) WBGEN2_DSP_GEN_READ(reg, 30, 2)
 
 /* definitions for register: DDS phase increment parameter register for channel 3 */
 
 /* definitions for field: DDS phase increment parameter register for channel 3 in reg: DDS phase increment parameter register for channel 3 */
-#define POS_CALC_DDS_PINC_CH3_VAL_MASK        WBGEN2_GEN_MASK(0, 30)
+#define POS_CALC_DDS_PINC_CH3_VAL_MASK        WBGEN2_DSP_GEN_MASK(0, 30)
 #define POS_CALC_DDS_PINC_CH3_VAL_SHIFT       0
-#define POS_CALC_DDS_PINC_CH3_VAL_W(value)    WBGEN2_GEN_WRITE(value, 0, 30)
-#define POS_CALC_DDS_PINC_CH3_VAL_R(reg)      WBGEN2_GEN_READ(reg, 0, 30)
+#define POS_CALC_DDS_PINC_CH3_VAL_W(value)    WBGEN2_DSP_GEN_WRITE(value, 0, 30)
+#define POS_CALC_DDS_PINC_CH3_VAL_R(reg)      WBGEN2_DSP_GEN_READ(reg, 0, 30)
 
 /* definitions for field: Reserved in reg: DDS phase increment parameter register for channel 3 */
-#define POS_CALC_DDS_PINC_CH3_RESERVED_MASK   WBGEN2_GEN_MASK(30, 2)
+#define POS_CALC_DDS_PINC_CH3_RESERVED_MASK   WBGEN2_DSP_GEN_MASK(30, 2)
 #define POS_CALC_DDS_PINC_CH3_RESERVED_SHIFT  30
-#define POS_CALC_DDS_PINC_CH3_RESERVED_W(value) WBGEN2_GEN_WRITE(value, 30, 2)
-#define POS_CALC_DDS_PINC_CH3_RESERVED_R(reg) WBGEN2_GEN_READ(reg, 30, 2)
+#define POS_CALC_DDS_PINC_CH3_RESERVED_W(value) WBGEN2_DSP_GEN_WRITE(value, 30, 2)
+#define POS_CALC_DDS_PINC_CH3_RESERVED_R(reg) WBGEN2_DSP_GEN_READ(reg, 30, 2)
 
 /* definitions for register: DDS phase offset parameter register for channel 0 */
 
 /* definitions for field: DDS phase offset parameter register for channel 0 in reg: DDS phase offset parameter register for channel 0 */
-#define POS_CALC_DDS_POFF_CH0_VAL_MASK        WBGEN2_GEN_MASK(0, 30)
+#define POS_CALC_DDS_POFF_CH0_VAL_MASK        WBGEN2_DSP_GEN_MASK(0, 30)
 #define POS_CALC_DDS_POFF_CH0_VAL_SHIFT       0
-#define POS_CALC_DDS_POFF_CH0_VAL_W(value)    WBGEN2_GEN_WRITE(value, 0, 30)
-#define POS_CALC_DDS_POFF_CH0_VAL_R(reg)      WBGEN2_GEN_READ(reg, 0, 30)
+#define POS_CALC_DDS_POFF_CH0_VAL_W(value)    WBGEN2_DSP_GEN_WRITE(value, 0, 30)
+#define POS_CALC_DDS_POFF_CH0_VAL_R(reg)      WBGEN2_DSP_GEN_READ(reg, 0, 30)
 
 /* definitions for field: Reserved in reg: DDS phase offset parameter register for channel 0 */
-#define POS_CALC_DDS_POFF_CH0_RESERVED_MASK   WBGEN2_GEN_MASK(30, 2)
+#define POS_CALC_DDS_POFF_CH0_RESERVED_MASK   WBGEN2_DSP_GEN_MASK(30, 2)
 #define POS_CALC_DDS_POFF_CH0_RESERVED_SHIFT  30
-#define POS_CALC_DDS_POFF_CH0_RESERVED_W(value) WBGEN2_GEN_WRITE(value, 30, 2)
-#define POS_CALC_DDS_POFF_CH0_RESERVED_R(reg) WBGEN2_GEN_READ(reg, 30, 2)
+#define POS_CALC_DDS_POFF_CH0_RESERVED_W(value) WBGEN2_DSP_GEN_WRITE(value, 30, 2)
+#define POS_CALC_DDS_POFF_CH0_RESERVED_R(reg) WBGEN2_DSP_GEN_READ(reg, 30, 2)
 
 /* definitions for register: DDS phase offset parameter register for channel 1 */
 
 /* definitions for field: DDS phase offset parameter register for channel 1 in reg: DDS phase offset parameter register for channel 1 */
-#define POS_CALC_DDS_POFF_CH1_VAL_MASK        WBGEN2_GEN_MASK(0, 30)
+#define POS_CALC_DDS_POFF_CH1_VAL_MASK        WBGEN2_DSP_GEN_MASK(0, 30)
 #define POS_CALC_DDS_POFF_CH1_VAL_SHIFT       0
-#define POS_CALC_DDS_POFF_CH1_VAL_W(value)    WBGEN2_GEN_WRITE(value, 0, 30)
-#define POS_CALC_DDS_POFF_CH1_VAL_R(reg)      WBGEN2_GEN_READ(reg, 0, 30)
+#define POS_CALC_DDS_POFF_CH1_VAL_W(value)    WBGEN2_DSP_GEN_WRITE(value, 0, 30)
+#define POS_CALC_DDS_POFF_CH1_VAL_R(reg)      WBGEN2_DSP_GEN_READ(reg, 0, 30)
 
 /* definitions for field: Reserved in reg: DDS phase offset parameter register for channel 1 */
-#define POS_CALC_DDS_POFF_CH1_RESERVED_MASK   WBGEN2_GEN_MASK(30, 2)
+#define POS_CALC_DDS_POFF_CH1_RESERVED_MASK   WBGEN2_DSP_GEN_MASK(30, 2)
 #define POS_CALC_DDS_POFF_CH1_RESERVED_SHIFT  30
-#define POS_CALC_DDS_POFF_CH1_RESERVED_W(value) WBGEN2_GEN_WRITE(value, 30, 2)
-#define POS_CALC_DDS_POFF_CH1_RESERVED_R(reg) WBGEN2_GEN_READ(reg, 30, 2)
+#define POS_CALC_DDS_POFF_CH1_RESERVED_W(value) WBGEN2_DSP_GEN_WRITE(value, 30, 2)
+#define POS_CALC_DDS_POFF_CH1_RESERVED_R(reg) WBGEN2_DSP_GEN_READ(reg, 30, 2)
 
 /* definitions for register: DDS phase offset parameter register for channel 2 */
 
 /* definitions for field: DDS phase offset parameter register for channel 2 in reg: DDS phase offset parameter register for channel 2 */
-#define POS_CALC_DDS_POFF_CH2_VAL_MASK        WBGEN2_GEN_MASK(0, 30)
+#define POS_CALC_DDS_POFF_CH2_VAL_MASK        WBGEN2_DSP_GEN_MASK(0, 30)
 #define POS_CALC_DDS_POFF_CH2_VAL_SHIFT       0
-#define POS_CALC_DDS_POFF_CH2_VAL_W(value)    WBGEN2_GEN_WRITE(value, 0, 30)
-#define POS_CALC_DDS_POFF_CH2_VAL_R(reg)      WBGEN2_GEN_READ(reg, 0, 30)
+#define POS_CALC_DDS_POFF_CH2_VAL_W(value)    WBGEN2_DSP_GEN_WRITE(value, 0, 30)
+#define POS_CALC_DDS_POFF_CH2_VAL_R(reg)      WBGEN2_DSP_GEN_READ(reg, 0, 30)
 
 /* definitions for field: Reserved in reg: DDS phase offset parameter register for channel 2 */
-#define POS_CALC_DDS_POFF_CH2_RESERVED_MASK   WBGEN2_GEN_MASK(30, 2)
+#define POS_CALC_DDS_POFF_CH2_RESERVED_MASK   WBGEN2_DSP_GEN_MASK(30, 2)
 #define POS_CALC_DDS_POFF_CH2_RESERVED_SHIFT  30
-#define POS_CALC_DDS_POFF_CH2_RESERVED_W(value) WBGEN2_GEN_WRITE(value, 30, 2)
-#define POS_CALC_DDS_POFF_CH2_RESERVED_R(reg) WBGEN2_GEN_READ(reg, 30, 2)
+#define POS_CALC_DDS_POFF_CH2_RESERVED_W(value) WBGEN2_DSP_GEN_WRITE(value, 30, 2)
+#define POS_CALC_DDS_POFF_CH2_RESERVED_R(reg) WBGEN2_DSP_GEN_READ(reg, 30, 2)
 
 /* definitions for register: DDS phase offset parameter register for channel 3 */
 
 /* definitions for field: DDS phase offset parameter register for channel 3 in reg: DDS phase offset parameter register for channel 3 */
-#define POS_CALC_DDS_POFF_CH3_VAL_MASK        WBGEN2_GEN_MASK(0, 30)
+#define POS_CALC_DDS_POFF_CH3_VAL_MASK        WBGEN2_DSP_GEN_MASK(0, 30)
 #define POS_CALC_DDS_POFF_CH3_VAL_SHIFT       0
-#define POS_CALC_DDS_POFF_CH3_VAL_W(value)    WBGEN2_GEN_WRITE(value, 0, 30)
-#define POS_CALC_DDS_POFF_CH3_VAL_R(reg)      WBGEN2_GEN_READ(reg, 0, 30)
+#define POS_CALC_DDS_POFF_CH3_VAL_W(value)    WBGEN2_DSP_GEN_WRITE(value, 0, 30)
+#define POS_CALC_DDS_POFF_CH3_VAL_R(reg)      WBGEN2_DSP_GEN_READ(reg, 0, 30)
 
 /* definitions for field: Reserved in reg: DDS phase offset parameter register for channel 3 */
-#define POS_CALC_DDS_POFF_CH3_RESERVED_MASK   WBGEN2_GEN_MASK(30, 2)
+#define POS_CALC_DDS_POFF_CH3_RESERVED_MASK   WBGEN2_DSP_GEN_MASK(30, 2)
 #define POS_CALC_DDS_POFF_CH3_RESERVED_SHIFT  30
-#define POS_CALC_DDS_POFF_CH3_RESERVED_W(value) WBGEN2_GEN_WRITE(value, 30, 2)
-#define POS_CALC_DDS_POFF_CH3_RESERVED_R(reg) WBGEN2_GEN_READ(reg, 30, 2)
+#define POS_CALC_DDS_POFF_CH3_RESERVED_W(value) WBGEN2_DSP_GEN_WRITE(value, 30, 2)
+#define POS_CALC_DDS_POFF_CH3_RESERVED_R(reg) WBGEN2_DSP_GEN_READ(reg, 30, 2)
 
 /* definitions for register: Monit. Amplitude Value for channel 0 */
 
@@ -355,6 +358,98 @@
 /* definitions for register: Monit. Sum Position Value */
 
 /* definitions for register: Monit. Amp/Pos update trigger */
+
+/* definitions for register: FIFO 'AMP FIFO' data output register 0 */
+
+/* definitions for field: Channel 0 Amplitude in reg: FIFO 'AMP FIFO' data output register 0 */
+#define POS_CALC_AMPFIFO_R0_MONIT_AMP_CH0_MASK WBGEN2_DSP_GEN_MASK(0, 32)
+#define POS_CALC_AMPFIFO_R0_MONIT_AMP_CH0_SHIFT 0
+#define POS_CALC_AMPFIFO_R0_MONIT_AMP_CH0_W(value) WBGEN2_DSP_GEN_WRITE(value, 0, 32)
+#define POS_CALC_AMPFIFO_R0_MONIT_AMP_CH0_R(reg) WBGEN2_DSP_GEN_READ(reg, 0, 32)
+
+/* definitions for register: FIFO 'AMP FIFO' data output register 1 */
+
+/* definitions for field: Channel 1 Amplitude in reg: FIFO 'AMP FIFO' data output register 1 */
+#define POS_CALC_AMPFIFO_R1_MONIT_AMP_CH1_MASK WBGEN2_DSP_GEN_MASK(0, 32)
+#define POS_CALC_AMPFIFO_R1_MONIT_AMP_CH1_SHIFT 0
+#define POS_CALC_AMPFIFO_R1_MONIT_AMP_CH1_W(value) WBGEN2_DSP_GEN_WRITE(value, 0, 32)
+#define POS_CALC_AMPFIFO_R1_MONIT_AMP_CH1_R(reg) WBGEN2_DSP_GEN_READ(reg, 0, 32)
+
+/* definitions for register: FIFO 'AMP FIFO' data output register 2 */
+
+/* definitions for field: Channel 2 Amplitude in reg: FIFO 'AMP FIFO' data output register 2 */
+#define POS_CALC_AMPFIFO_R2_MONIT_AMP_CH2_MASK WBGEN2_DSP_GEN_MASK(0, 32)
+#define POS_CALC_AMPFIFO_R2_MONIT_AMP_CH2_SHIFT 0
+#define POS_CALC_AMPFIFO_R2_MONIT_AMP_CH2_W(value) WBGEN2_DSP_GEN_WRITE(value, 0, 32)
+#define POS_CALC_AMPFIFO_R2_MONIT_AMP_CH2_R(reg) WBGEN2_DSP_GEN_READ(reg, 0, 32)
+
+/* definitions for register: FIFO 'AMP FIFO' data output register 3 */
+
+/* definitions for field: Channel 3 Amplitude in reg: FIFO 'AMP FIFO' data output register 3 */
+#define POS_CALC_AMPFIFO_R3_MONIT_AMP_CH3_MASK WBGEN2_DSP_GEN_MASK(0, 32)
+#define POS_CALC_AMPFIFO_R3_MONIT_AMP_CH3_SHIFT 0
+#define POS_CALC_AMPFIFO_R3_MONIT_AMP_CH3_W(value) WBGEN2_DSP_GEN_WRITE(value, 0, 32)
+#define POS_CALC_AMPFIFO_R3_MONIT_AMP_CH3_R(reg) WBGEN2_DSP_GEN_READ(reg, 0, 32)
+
+/* definitions for register: FIFO 'AMP FIFO' control/status register */
+
+/* definitions for field: FIFO full flag in reg: FIFO 'AMP FIFO' control/status register */
+#define POS_CALC_AMPFIFO_CSR_FULL             WBGEN2_DSP_GEN_MASK(16, 1)
+
+/* definitions for field: FIFO empty flag in reg: FIFO 'AMP FIFO' control/status register */
+#define POS_CALC_AMPFIFO_CSR_EMPTY            WBGEN2_DSP_GEN_MASK(17, 1)
+
+/* definitions for field: FIFO counter in reg: FIFO 'AMP FIFO' control/status register */
+#define POS_CALC_AMPFIFO_CSR_USEDW_MASK       WBGEN2_DSP_GEN_MASK(0, 4)
+#define POS_CALC_AMPFIFO_CSR_USEDW_SHIFT      0
+#define POS_CALC_AMPFIFO_CSR_USEDW_W(value)   WBGEN2_DSP_GEN_WRITE(value, 0, 4)
+#define POS_CALC_AMPFIFO_CSR_USEDW_R(reg)     WBGEN2_DSP_GEN_READ(reg, 0, 4)
+
+/* definitions for register: FIFO 'POS FIFO' data output register 0 */
+
+/* definitions for field: Channel X Position in reg: FIFO 'POS FIFO' data output register 0 */
+#define POS_CALC_POSFIFO_R0_MONIT_POS_X_MASK  WBGEN2_DSP_GEN_MASK(0, 32)
+#define POS_CALC_POSFIFO_R0_MONIT_POS_X_SHIFT 0
+#define POS_CALC_POSFIFO_R0_MONIT_POS_X_W(value) WBGEN2_DSP_GEN_WRITE(value, 0, 32)
+#define POS_CALC_POSFIFO_R0_MONIT_POS_X_R(reg) WBGEN2_DSP_GEN_READ(reg, 0, 32)
+
+/* definitions for register: FIFO 'POS FIFO' data output register 1 */
+
+/* definitions for field: Channel Y Position in reg: FIFO 'POS FIFO' data output register 1 */
+#define POS_CALC_POSFIFO_R1_MONIT_POS_Y_MASK  WBGEN2_DSP_GEN_MASK(0, 32)
+#define POS_CALC_POSFIFO_R1_MONIT_POS_Y_SHIFT 0
+#define POS_CALC_POSFIFO_R1_MONIT_POS_Y_W(value) WBGEN2_DSP_GEN_WRITE(value, 0, 32)
+#define POS_CALC_POSFIFO_R1_MONIT_POS_Y_R(reg) WBGEN2_DSP_GEN_READ(reg, 0, 32)
+
+/* definitions for register: FIFO 'POS FIFO' data output register 2 */
+
+/* definitions for field: Channel Q Position in reg: FIFO 'POS FIFO' data output register 2 */
+#define POS_CALC_POSFIFO_R2_MONIT_POS_Q_MASK  WBGEN2_DSP_GEN_MASK(0, 32)
+#define POS_CALC_POSFIFO_R2_MONIT_POS_Q_SHIFT 0
+#define POS_CALC_POSFIFO_R2_MONIT_POS_Q_W(value) WBGEN2_DSP_GEN_WRITE(value, 0, 32)
+#define POS_CALC_POSFIFO_R2_MONIT_POS_Q_R(reg) WBGEN2_DSP_GEN_READ(reg, 0, 32)
+
+/* definitions for register: FIFO 'POS FIFO' data output register 3 */
+
+/* definitions for field: Channel Sum Position in reg: FIFO 'POS FIFO' data output register 3 */
+#define POS_CALC_POSFIFO_R3_MONIT_POS_SUM_MASK WBGEN2_DSP_GEN_MASK(0, 32)
+#define POS_CALC_POSFIFO_R3_MONIT_POS_SUM_SHIFT 0
+#define POS_CALC_POSFIFO_R3_MONIT_POS_SUM_W(value) WBGEN2_DSP_GEN_WRITE(value, 0, 32)
+#define POS_CALC_POSFIFO_R3_MONIT_POS_SUM_R(reg) WBGEN2_DSP_GEN_READ(reg, 0, 32)
+
+/* definitions for register: FIFO 'POS FIFO' control/status register */
+
+/* definitions for field: FIFO full flag in reg: FIFO 'POS FIFO' control/status register */
+#define POS_CALC_POSFIFO_CSR_FULL             WBGEN2_DSP_GEN_MASK(16, 1)
+
+/* definitions for field: FIFO empty flag in reg: FIFO 'POS FIFO' control/status register */
+#define POS_CALC_POSFIFO_CSR_EMPTY            WBGEN2_DSP_GEN_MASK(17, 1)
+
+/* definitions for field: FIFO counter in reg: FIFO 'POS FIFO' control/status register */
+#define POS_CALC_POSFIFO_CSR_USEDW_MASK       WBGEN2_DSP_GEN_MASK(0, 4)
+#define POS_CALC_POSFIFO_CSR_USEDW_SHIFT      0
+#define POS_CALC_POSFIFO_CSR_USEDW_W(value)   WBGEN2_DSP_GEN_WRITE(value, 0, 4)
+#define POS_CALC_POSFIFO_CSR_USEDW_R(reg)     WBGEN2_DSP_GEN_READ(reg, 0, 4)
 /* [0x0]: REG Config divisor threshold TBT register */
 #define POS_CALC_REG_DS_TBT_THRES 0x00000000
 /* [0x4]: REG Config divisor threshold FOFB register */
@@ -413,4 +508,24 @@
 #define POS_CALC_REG_DSP_MONIT_POS_SUM 0x0000006c
 /* [0x70]: REG Monit. Amp/Pos update trigger */
 #define POS_CALC_REG_DSP_MONIT_UPDT 0x00000070
+/* [0x74]: REG FIFO 'AMP FIFO' data output register 0 */
+#define POS_CALC_REG_AMPFIFO_R0 0x00000074
+/* [0x78]: REG FIFO 'AMP FIFO' data output register 1 */
+#define POS_CALC_REG_AMPFIFO_R1 0x00000078
+/* [0x7c]: REG FIFO 'AMP FIFO' data output register 2 */
+#define POS_CALC_REG_AMPFIFO_R2 0x0000007c
+/* [0x80]: REG FIFO 'AMP FIFO' data output register 3 */
+#define POS_CALC_REG_AMPFIFO_R3 0x00000080
+/* [0x84]: REG FIFO 'AMP FIFO' control/status register */
+#define POS_CALC_REG_AMPFIFO_CSR 0x00000084
+/* [0x88]: REG FIFO 'POS FIFO' data output register 0 */
+#define POS_CALC_REG_POSFIFO_R0 0x00000088
+/* [0x8c]: REG FIFO 'POS FIFO' data output register 1 */
+#define POS_CALC_REG_POSFIFO_R1 0x0000008c
+/* [0x90]: REG FIFO 'POS FIFO' data output register 2 */
+#define POS_CALC_REG_POSFIFO_R2 0x00000090
+/* [0x94]: REG FIFO 'POS FIFO' data output register 3 */
+#define POS_CALC_REG_POSFIFO_R3 0x00000094
+/* [0x98]: REG FIFO 'POS FIFO' control/status register */
+#define POS_CALC_REG_POSFIFO_CSR 0x00000098
 #endif
diff --git a/core/sm_io/include/sm_io_dsp_codes.h b/core/sm_io/include/sm_io_dsp_codes.h
index 0601dd90..43f3dcf8 100644
--- a/core/sm_io/include/sm_io_dsp_codes.h
+++ b/core/sm_io/include/sm_io_dsp_codes.h
@@ -13,10 +13,12 @@ struct _smio_dsp_data_t {
     uint32_t amp_ch1;                    /* Amplitude CH1 */
     uint32_t amp_ch2;                    /* Amplitude CH2 */
     uint32_t amp_ch3;                    /* Amplitude CH3 */
+    uint32_t new_amp_data;               /* Do we have new AMP data? */
     int32_t pos_x;                       /* Position X */
     int32_t pos_y;                       /* Position Y */
     int32_t pos_q;                       /* Position Q */
     uint32_t pos_sum;                    /* Position Sum */
+    uint32_t new_pos_data;               /* Do we have new POS data? */
 };
 
 /* Messaging OPCODES */
diff --git a/core/sm_io/include/sm_io_fmc_adc_common_codes.h b/core/sm_io/include/sm_io_fmc_adc_common_codes.h
index 9c8b3141..7d74b82a 100644
--- a/core/sm_io/include/sm_io_fmc_adc_common_codes.h
+++ b/core/sm_io/include/sm_io_fmc_adc_common_codes.h
@@ -14,15 +14,17 @@
 
 #define FMC_ADC_COMMON_OPCODE_LEDS                          0
 #define FMC_ADC_COMMON_NAME_LEDS                            "fmc_adc_common_leds"
-#define FMC_ADC_COMMON_OPCODE_TEST_DATA_EN                  1
+#define FMC_ADC_COMMON_OPCODE_MMCM_RST                      1
+#define FMC_ADC_COMMON_NAME_MMCM_RST                        "fmc_adc_common_mmcm_rst"
+#define FMC_ADC_COMMON_OPCODE_TEST_DATA_EN                  2
 #define FMC_ADC_COMMON_NAME_TEST_DATA_EN                    "fmc_adc_common_adc_test_data_en"
-#define FMC_ADC_COMMON_OPCODE_TRIG_DIR                      2
+#define FMC_ADC_COMMON_OPCODE_TRIG_DIR                      3
 #define FMC_ADC_COMMON_NAME_TRIG_DIR                        "fmc_adc_common_trig_dir"
-#define FMC_ADC_COMMON_OPCODE_TRIG_TERM                     3
+#define FMC_ADC_COMMON_OPCODE_TRIG_TERM                     4
 #define FMC_ADC_COMMON_NAME_TRIG_TERM                       "fmc_adc_common_trig_term"
-#define FMC_ADC_COMMON_OPCODE_TRIG_VAL                      4
+#define FMC_ADC_COMMON_OPCODE_TRIG_VAL                      5
 #define FMC_ADC_COMMON_NAME_TRIG_VAL                        "fmc_adc_common_trig_val"
-#define FMC_ADC_COMMON_OPCODE_END                           5
+#define FMC_ADC_COMMON_OPCODE_END                           6
 
 /* Messaging Reply OPCODES */
 #define FMC_ADC_COMMON_REPLY_TYPE                           uint32_t
diff --git a/core/sm_io/src/sm_io/c/chips/sm_ch_ad9510.c b/core/sm_io/src/sm_io/c/chips/sm_ch_ad9510.c
index 6f7d327c..4cb0d344 100644
--- a/core/sm_io/src/sm_io/c/chips/sm_ch_ad9510.c
+++ b/core/sm_io/src/sm_io/c/chips/sm_ch_ad9510.c
@@ -191,7 +191,7 @@ smch_err_e smch_ad9510_cfg_defaults (smch_ad9510_t *self)
     _smch_ad9510_write_8 (self, AD9510_REG_PLL_R_LSB_COUNTER, &data);
 
     /* Power-up LVPECL outputs */
-    DBE_DEBUG (DBG_SM_CH | DBG_LVL_INFO,
+    DBE_DEBUG (DBG_SM_CH | DBG_LVL_TRACE,
             "[sm_ch:ad9510] Powering up LVPECL outputs 0-3\n");
     data = AD9510_LVPECL_OUT_LVL_W(0x02) /* 810 mV output */ |
         AD9510_LVPECL_OUT_PDOWN_W(0x0) /* Do not power down */;
@@ -201,14 +201,14 @@ smch_err_e smch_ad9510_cfg_defaults (smch_ad9510_t *self)
     _smch_ad9510_write_8 (self, AD9510_REG_LVPECL_OUT3, &data);
 
     /* Power-up LVCMOS/LVDS output 4 (DEBUG) */
-    DBE_DEBUG (DBG_SM_CH | DBG_LVL_INFO,
+    DBE_DEBUG (DBG_SM_CH | DBG_LVL_TRACE,
             "[sm_ch:ad9510] Powering up LVDS/CMOS output 4\n");
     data = AD9510_LVDS_CMOS_CURR_W(0x1) /* 3.5 mA, 100 Ohm */ & (
         ~AD9510_LVDS_CMOS_PDOWN /* Do not power down */);
     _smch_ad9510_write_8 (self, AD9510_REG_LVDS_CMOS_OUT4, &data);
 
     /* Power-down LVCMOS/LVDS outputs 5-7*/
-    DBE_DEBUG (DBG_SM_CH | DBG_LVL_INFO,
+    DBE_DEBUG (DBG_SM_CH | DBG_LVL_TRACE,
             "[sm_ch:ad9510] Powering down LVDS/CMOS outputs 5-7\n");
     data = AD9510_LVDS_CMOS_CURR_W(0x1) /* 3.5 mA, 100 Ohm */ | (
         AD9510_LVDS_CMOS_PDOWN /* Power down */);
@@ -601,14 +601,14 @@ smch_err_e smch_ad9510_set_outputs (smch_ad9510_t *self, uint32_t *out_en)
 
         /* Output disabled */
         if ((__out_en & AD9510_OUTPUT_EN_LSB_MASK) == 0) {
-            DBE_DEBUG (DBG_SM_CH | DBG_LVL_INFO,
+            DBE_DEBUG (DBG_SM_CH | DBG_LVL_TRACE,
                     "[sm_ch:ad9510] Output #%u is going to be disabled\n", i);
             data = (data & ~AD9510_LVPECL_OUT_PDOWN_MASK) |
                 AD9510_LVPECL_OUT_PDOWN_W(0x02); /* Safe power down */
         }
         /* Output enabled */
         else {
-            DBE_DEBUG (DBG_SM_CH | DBG_LVL_INFO,
+            DBE_DEBUG (DBG_SM_CH | DBG_LVL_TRACE,
                     "[sm_ch:ad9510] Output #%u is going to be enabled\n", i);
             data = (data & ~AD9510_LVPECL_OUT_PDOWN_MASK) |
                 AD9510_LVPECL_OUT_PDOWN_W(0x00); /* Power up */
@@ -624,13 +624,13 @@ smch_err_e smch_ad9510_set_outputs (smch_ad9510_t *self, uint32_t *out_en)
 
         /* Output disabled */
         if ((__out_en & AD9510_OUTPUT_EN_LSB_MASK) == 0) {
-            DBE_DEBUG (DBG_SM_CH | DBG_LVL_INFO,
+            DBE_DEBUG (DBG_SM_CH | DBG_LVL_TRACE,
                     "[sm_ch:ad9510] Output #%u is going to be enabled\n", i);
             data |= AD9510_LVDS_CMOS_PDOWN;
         }
         /* Output enabled */
         else {
-            DBE_DEBUG (DBG_SM_CH | DBG_LVL_INFO,
+            DBE_DEBUG (DBG_SM_CH | DBG_LVL_TRACE,
                     "[sm_ch:ad9510] Output #%u is going to be enabled\n", i);
             data &= ~AD9510_LVDS_CMOS_PDOWN;
         }
diff --git a/core/sm_io/src/sm_io/c/chips/sm_ch_si57x.c b/core/sm_io/src/sm_io/c/chips/sm_ch_si57x.c
index 6cac68c2..7cf49f66 100644
--- a/core/sm_io/src/sm_io/c/chips/sm_ch_si57x.c
+++ b/core/sm_io/src/sm_io/c/chips/sm_ch_si57x.c
@@ -343,7 +343,7 @@ static smch_err_e _smch_si57x_get_divs (smch_si57x_t *self, uint64_t *rfreq,
     tmp = (tmp << 8) + SI57X_RFREQ4_RFREQ_7_0_R(divs[5]);
     *rfreq = tmp;
 
-    DBE_DEBUG (DBG_SM_CH | DBG_LVL_INFO, "[sm_ch:si57x_get_divs]\n"
+    DBE_DEBUG (DBG_SM_CH | DBG_LVL_TRACE, "[sm_ch:si57x_get_divs]\n"
             "\tRFREQ = %"PRIu64", HS_DIV = %u, N1 = %u\n", *rfreq, *hs_div, *n1);
 
 err_exit:
@@ -416,7 +416,7 @@ static smch_err_e _smch_si57x_set_freq_raw (smch_si57x_t *self, uint8_t *data,
     err = _smch_si57x_wait_new_freq (self);
     ASSERT_TEST(err == SMCH_SUCCESS, "New frequency setting timeout", err_exit);
 
-    DBE_DEBUG (DBG_SM_CH | DBG_LVL_INFO, "[sm_ch:si57x_set_freq_raw] Setup new "
+    DBE_DEBUG (DBG_SM_CH | DBG_LVL_TRACE, "[sm_ch:si57x_set_freq_raw] Setup new "
             "frequency completed\n");
 
 err_exit:
diff --git a/core/sm_io/src/sm_io/c/modules/dsp/sm_io_dsp_exp.c b/core/sm_io/src/sm_io/c/modules/dsp/sm_io_dsp_exp.c
index d4aed561..31af8501 100644
--- a/core/sm_io/src/sm_io/c/modules/dsp/sm_io_dsp_exp.c
+++ b/core/sm_io/src/sm_io/c/modules/dsp/sm_io_dsp_exp.c
@@ -186,7 +186,8 @@ static int _dsp_monit_amp_pos (void *owner, void *args, void *ret)
     assert (owner);
     assert (args);
     int err = -DSP_OK;
-    RW_REPLY_TYPE rw_err = RW_OK;
+    uint32_t ampfifo_empty;
+    uint32_t posfifo_empty;
 
     DBE_DEBUG (DBG_SM_IO | DBG_LVL_TRACE, "[sm_io:dsp] "
             "Calling _dsp_monit_amp_pos\n");
@@ -199,27 +200,73 @@ static int _dsp_monit_amp_pos (void *owner, void *args, void *ret)
      * Message is:
      * frame 0: operation code
      */
+    
     smio_dsp_data_t *data = (smio_dsp_data_t *) ret;
+    data->new_amp_data = false;
+    data->new_pos_data = false;
 
-    rw_err |= GET_PARAM(self, dsp, 0x0, POS_CALC,
-            DSP_MONIT_AMP_CH0, /* field = NULL */, MULT_BIT_PARAM, 
+    /* Check if FIFO is empty before reading from it */
+    GET_PARAM(self, dsp, 0x0, POS_CALC,
+        AMPFIFO_CSR, EMPTY, SINGLE_BIT_PARAM, 
+        ampfifo_empty, NO_FMT_FUNC);
+    GET_PARAM(self, dsp, 0x0, POS_CALC,
+        POSFIFO_CSR, EMPTY, SINGLE_BIT_PARAM, 
+        posfifo_empty, NO_FMT_FUNC);
+
+    DBE_DEBUG (DBG_SM_IO | DBG_LVL_TRACE, "[sm_io:dsp] "
+            "ampfifo empty: %u\n", ampfifo_empty);
+    DBE_DEBUG (DBG_SM_IO | DBG_LVL_TRACE, "[sm_io:dsp] "
+            "posfifo empty: %u\n", posfifo_empty);
+
+    if (!ampfifo_empty) {
+        GET_PARAM(self, dsp, 0x0, POS_CALC,
+            AMPFIFO_R0, MONIT_AMP_CH0, MULT_BIT_PARAM, 
             data->amp_ch0, NO_FMT_FUNC);
-    rw_err |= GET_PARAM(self, dsp, 0x0, POS_CALC,
-            DSP_MONIT_AMP_CH1, /* field = NULL */, MULT_BIT_PARAM, 
+        GET_PARAM(self, dsp, 0x0, POS_CALC,
+            AMPFIFO_R1, MONIT_AMP_CH1, MULT_BIT_PARAM, 
             data->amp_ch1, NO_FMT_FUNC);
-    rw_err |= GET_PARAM(self, dsp, 0x0, POS_CALC,
-            DSP_MONIT_AMP_CH2, /* field = NULL */, MULT_BIT_PARAM, 
+        GET_PARAM(self, dsp, 0x0, POS_CALC,
+            AMPFIFO_R2, MONIT_AMP_CH2, MULT_BIT_PARAM, 
             data->amp_ch2, NO_FMT_FUNC);
-    rw_err |= GET_PARAM(self, dsp, 0x0, POS_CALC,
-            DSP_MONIT_AMP_CH3, /* field = NULL */, MULT_BIT_PARAM, 
+        GET_PARAM(self, dsp, 0x0, POS_CALC,
+            AMPFIFO_R3, MONIT_AMP_CH3, MULT_BIT_PARAM, 
             data->amp_ch3, NO_FMT_FUNC);
-    ASSERT_TEST(rw_err == RW_OK, "Could not get MONIT. amp/pos parameters", 
-        err_exit, -DSP_ERR);
-
-    return sizeof (*data);
+    }
+
+    if (!posfifo_empty) {
+        GET_PARAM(self, dsp, 0x0, POS_CALC,
+            POSFIFO_R0, MONIT_POS_X, MULT_BIT_PARAM, 
+            data->pos_x, NO_FMT_FUNC);
+        GET_PARAM(self, dsp, 0x0, POS_CALC,
+            POSFIFO_R1, MONIT_POS_Y, MULT_BIT_PARAM, 
+            data->pos_y, NO_FMT_FUNC);
+        GET_PARAM(self, dsp, 0x0, POS_CALC,
+            POSFIFO_R2, MONIT_POS_Q, MULT_BIT_PARAM, 
+            data->pos_q, NO_FMT_FUNC);
+        GET_PARAM(self, dsp, 0x0, POS_CALC,
+            POSFIFO_R3, MONIT_POS_SUM, MULT_BIT_PARAM, 
+            data->pos_sum, NO_FMT_FUNC);
+    }
+
+    if (!ampfifo_empty) {
+        DBE_DEBUG (DBG_SM_IO | DBG_LVL_TRACE, "[sm_io:dsp_exp] Data AMP: %u %u %u %u\n",
+            data->amp_ch0, data->amp_ch1, data->amp_ch2, data->amp_ch3);
+        data->new_amp_data = true;
+        err = sizeof (*data);
+    }
+
+    if (!posfifo_empty) {
+        DBE_DEBUG (DBG_SM_IO | DBG_LVL_TRACE, "[sm_io:dsp_exp] Data POS: %d %d %d %d\n",
+            data->pos_x, data->pos_y, data->pos_q, data->pos_sum);
+        data->new_pos_data = true;
+        err = sizeof (*data);
+    }
+
+    /* return the whole dsp_data structure even if we don't have new data.
+     *   This avoids specific treatment for client handling */
+    err = sizeof (*data);
 
 err_get_dsp_handler:
-err_exit:
     return err;
 }
 
diff --git a/core/sm_io/src/sm_io/c/modules/fmc_adc_common/sm_io_fmc_adc_common_exp.c b/core/sm_io/src/sm_io/c/modules/fmc_adc_common/sm_io_fmc_adc_common_exp.c
index 6363a5e0..b2a10799 100644
--- a/core/sm_io/src/sm_io/c/modules/fmc_adc_common/sm_io_fmc_adc_common_exp.c
+++ b/core/sm_io/src/sm_io/c/modules/fmc_adc_common/sm_io_fmc_adc_common_exp.c
@@ -54,6 +54,16 @@ RW_PARAM_FUNC(fmc_adc_common, leds) {
             NO_FMT_FUNC, SET_FIELD);
 }
 
+
+#define HALCS_FMC_ADC_COMMON_MMCM_RST_MIN                 0       /* No effect */
+#define HALCS_FMC_ADC_COMMON_MMCM_RST_MAX                 1       /* Reset MMCM. Must clear the bit after a while */
+RW_PARAM_FUNC(fmc_adc_common, mmcm_rst) {
+    SET_GET_PARAM(fmc_adc_common, 0x0, WB_FMC_ADC_COMMON_CSR,
+            MONITOR, MMCM_RST, SINGLE_BIT_PARAM,
+            HALCS_FMC_ADC_COMMON_MMCM_RST_MIN, HALCS_FMC_ADC_COMMON_MMCM_RST_MAX, 
+            NO_CHK_FUNC, NO_FMT_FUNC, SET_FIELD);
+}
+
 /***************************** FPGA Control ***************************/
 
 #define HALCS_FMC_ADC_COMMON_TEST_DATA_EN_MIN             0 /* TEST data enable off */
@@ -99,6 +109,7 @@ RW_PARAM_FUNC(fmc_adc_common, trig_val) {
 /* Exported function pointers */
 const disp_table_func_fp fmc_adc_common_exp_fp [] = {
     RW_PARAM_FUNC_NAME(fmc_adc_common, leds),
+    RW_PARAM_FUNC_NAME(fmc_adc_common, mmcm_rst),
     RW_PARAM_FUNC_NAME(fmc_adc_common, test_data_en),
     RW_PARAM_FUNC_NAME(fmc_adc_common, trig_dir),
     RW_PARAM_FUNC_NAME(fmc_adc_common, trig_term),
diff --git a/core/sm_io_table/include/sm_io_fmc_adc_common_exports.h b/core/sm_io_table/include/sm_io_fmc_adc_common_exports.h
index 0b302f4f..3fc1c3f7 100644
--- a/core/sm_io_table/include/sm_io_fmc_adc_common_exports.h
+++ b/core/sm_io_table/include/sm_io_fmc_adc_common_exports.h
@@ -11,6 +11,7 @@
 #include "disptable.h"
 
 extern disp_op_t fmc_adc_common_leds_exp;
+extern disp_op_t fmc_adc_common_mmcm_rst_exp;
 extern disp_op_t fmc_adc_common_test_data_en_exp;
 extern disp_op_t fmc_adc_common_trig_dir_exp;
 extern disp_op_t fmc_adc_common_trig_term_exp;
diff --git a/core/sm_io_table/src/sm_io_table/c/modules/fmc_adc_common/sm_io_fmc_adc_common_exports.c b/core/sm_io_table/src/sm_io_table/c/modules/fmc_adc_common/sm_io_fmc_adc_common_exports.c
index 048a140c..d87cdc7e 100644
--- a/core/sm_io_table/src/sm_io_table/c/modules/fmc_adc_common/sm_io_fmc_adc_common_exports.c
+++ b/core/sm_io_table/src/sm_io_table/c/modules/fmc_adc_common/sm_io_fmc_adc_common_exports.c
@@ -22,6 +22,18 @@ disp_op_t fmc_adc_common_leds_exp = {
     }
 };
 
+disp_op_t fmc_adc_common_mmcm_rst_exp = {
+    .name = FMC_ADC_COMMON_NAME_MMCM_RST,
+    .opcode = FMC_ADC_COMMON_OPCODE_MMCM_RST,
+    .retval = DISP_ARG_ENCODE(DISP_ATYPE_UINT32, uint32_t),
+    .retval_owner = DISP_OWNER_OTHER,
+    .args = {
+        DISP_ARG_ENCODE(DISP_ATYPE_UINT32, uint32_t),
+        DISP_ARG_ENCODE(DISP_ATYPE_UINT32, uint32_t),
+        DISP_ARG_END
+    }
+};
+
 disp_op_t fmc_adc_common_test_data_en_exp = {
     .name = FMC_ADC_COMMON_NAME_TEST_DATA_EN,
     .opcode = FMC_ADC_COMMON_OPCODE_TEST_DATA_EN,
@@ -73,6 +85,7 @@ disp_op_t fmc_adc_common_trig_val_exp = {
 /* Exported function description */
 const disp_op_t *fmc_adc_common_exp_ops [] = {
     &fmc_adc_common_leds_exp,
+    &fmc_adc_common_mmcm_rst_exp,
     &fmc_adc_common_test_data_en_exp,
     &fmc_adc_common_trig_dir_exp,
     &fmc_adc_common_trig_term_exp,
diff --git a/examples/src/acq/c/acq.c b/examples/src/acq/c/acq.c
index 99a2e04c..68c9635e 100644
--- a/examples/src/acq/c/acq.c
+++ b/examples/src/acq/c/acq.c
@@ -25,6 +25,7 @@
 #define MAX_NUM_CHANS               (1 << 8)
 
 #define DFLT_FILE_FMT               0
+#define DFLT_NEWACQ_NUM             1
 
 typedef enum {
     TEXT = 0,
@@ -81,15 +82,16 @@ static struct option long_options[] =
     {"help",                no_argument,         NULL, 'h'},
     {"brokerendp",          required_argument,   NULL, 'b'},
     {"verbose",             no_argument,         NULL, 'v'},
-    {"halcsnumber",           required_argument,   NULL, 's'},
+    {"halcsnumber",         required_argument,   NULL, 's'},
     {"boardslot",           required_argument,   NULL, 'o'},
     {"channumber",          required_argument,   NULL, 'c'},
     {"numsamples",          required_argument,   NULL, 'n'},
     {"filefmt",             required_argument,   NULL, 'f'},
+    {"newacq",              required_argument,   NULL, 'a'},
     {NULL, 0, NULL, 0}
 };
 
-static const char* shortopt = "hb:vo:s:c:n:f:";
+static const char* shortopt = "hb:vo:s:c:n:f:a:";
 
 void print_help (char *program_name)
 {
@@ -111,7 +113,8 @@ void print_help (char *program_name)
             "                                     13 -> FOFB Pos; 14 -> Monit Amp; 15 -> Monit Pha; 16 -> Monit Pos]\n"
             "  -n  --numsamples <Number of samples> Number of samples\n"
             "  -f  --filefmt <Output format = [0 = text | 1=binary]>\n"
-            "                                       Output format\n",
+            "                                       Output format\n"
+            "  -a  --newcq <Trigger new acquisition = [0 = no | 1 = yes]\n",
             program_name);
 }
 
@@ -123,6 +126,7 @@ int main (int argc, char *argv [])
     char *board_number_str = NULL;
     char *halcs_number_str = NULL;
     char *chan_str = NULL;
+    char *new_acq_str = NULL;
     char *file_fmt_str = NULL;
     int opt;
 
@@ -159,6 +163,10 @@ int main (int argc, char *argv [])
                 num_samples_str = strdup (optarg);
                 break;
 
+            case 'a':
+                new_acq_str = strdup (optarg);
+                break;
+
             case 'f':
                 file_fmt_str = strdup (optarg);
                 break;
@@ -259,6 +267,20 @@ int main (int argc, char *argv [])
         }
     }
 
+    /* Set new_acq */
+    uint32_t new_acq;
+    if (new_acq_str == NULL) {
+        new_acq = DFLT_NEWACQ_NUM;
+    }
+    else {
+        new_acq = strtoul (new_acq_str, NULL, 10);
+
+        if (new_acq != 0 && new_acq != 1) {
+            fprintf (stderr, "[client:acq]: Newacq parameter is invalid\n");
+            exit (1);
+        }
+    }
+
     char service[50];
     snprintf (service, sizeof (service), "HALCS%u:DEVIO:ACQ%u", board_number, halcs_number);
 
@@ -295,7 +317,7 @@ int main (int argc, char *argv [])
 
     uint32_t data_size = num_samples*req_ch_sample_size;
     uint32_t *data = (uint32_t *) zmalloc (data_size*sizeof (uint8_t));
-    bool new_acq = true;
+    bool new_acq_arg = new_acq;
     acq_trans_t acq_trans = {.req =   {
                                         .num_samples_pre = num_samples,
                                         .num_samples_post = 0,
@@ -307,7 +329,7 @@ int main (int argc, char *argv [])
                                         .data_size = data_size,
                                       }
                             };
-    err = acq_full_compat (acq_client, service, &acq_trans, 50000, new_acq);
+    err = acq_full_compat (acq_client, service, &acq_trans, 50000, new_acq_arg);
     if (err != HALCS_CLIENT_SUCCESS){
         fprintf (stderr, "[client:acq]: acq_full_compat failed\n");
         goto err_acq_full_compat;
diff --git a/examples/src/monit_amp/c/monit_amp.c b/examples/src/monit_amp/c/monit_amp.c
index 5e78d04e..42ec43b4 100644
--- a/examples/src/monit_amp/c/monit_amp.c
+++ b/examples/src/monit_amp/c/monit_amp.c
@@ -108,16 +108,8 @@ int main (int argc, char *argv [])
         goto err_halcs_client_new;
     }
 
-    uint32_t monit_updt = 1;
-    halcs_client_err_e err = halcs_set_monit_updt (halcs_client, service,
-            monit_updt);
-    if (err != HALCS_CLIENT_SUCCESS){
-        fprintf (stderr, "[client:acq]: halcs_set_monit_updt failed\n");
-        goto err_set_monit_updt;
-    }
-    
     smio_dsp_data_t dsp_data;
-    err = halcs_get_monit_amp_pos (halcs_client, service, &dsp_data);
+    halcs_client_err_e err = halcs_get_monit_amp_pos (halcs_client, service, &dsp_data);
     if (err != HALCS_CLIENT_SUCCESS){
         fprintf (stderr, "[client:monit_amp]: halcs_get_monit_amp_pos failed\n");
         goto err_get_monit_amp;
@@ -134,7 +126,6 @@ int main (int argc, char *argv [])
               dsp_data.amp_ch3);
 
 err_get_monit_amp:
-err_set_monit_updt:
 err_halcs_client_new:
     halcs_client_destroy (&halcs_client);
     str_p = &board_number_str;
diff --git a/examples/src/si571_ctl/c/si571_ctl.c b/examples/src/si571_ctl/c/si571_ctl.c
index cf478ecc..35843004 100644
--- a/examples/src/si571_ctl/c/si571_ctl.c
+++ b/examples/src/si571_ctl/c/si571_ctl.c
@@ -127,7 +127,9 @@ int main (int argc, char *argv [])
     }
 
     char service[50];
+    char service_common[50];
     snprintf (service, sizeof (service), "HALCS%u:DEVIO:FMC_ACTIVE_CLK%u", board_number, halcs_number);
+    snprintf (service_common, sizeof (service_common), "HALCS%u:DEVIO:FMC_ADC_COMMON%u", board_number, halcs_number);
 
     halcs_client_t *halcs_client = halcs_client_new (broker_endp, verbose, NULL);
     if (halcs_client == NULL) {
@@ -156,8 +158,18 @@ int main (int argc, char *argv [])
 
     printf ("Freq: %f\n", freq);
 
-err_halcs_client_new:
+    /* Always reset MMCM when changing frequency */
+    err = halcs_set_adc_mmcm_rst (halcs_client, service_common, 1);
+    usleep (1000);
+    err |= halcs_set_adc_mmcm_rst (halcs_client, service_common, 0);
+    if (err != HALCS_CLIENT_SUCCESS){
+        fprintf (stderr, "[client:si571_ctl]: MMCM reset failed\n");
+        goto err_halcs_mmcm_rst;
+    }
+
+err_halcs_mmcm_rst:
 err_halcs_set_freq:
+err_halcs_client_new:
     halcs_client_destroy (&halcs_client);
 
     str_p = &si571_freq_str;
diff --git a/libs/halcsclient/include/halcs_client_core.h b/libs/halcsclient/include/halcs_client_core.h
index 5d5ab94c..5c6604fa 100644
--- a/libs/halcsclient/include/halcs_client_core.h
+++ b/libs/halcsclient/include/halcs_client_core.h
@@ -96,6 +96,14 @@ halcs_client_err_e halcs_get_fmc_leds (halcs_client_t *self, char *service,
 /* Macros for compatibility */
 #define halcs_blink_leds halcs_set_fmc_leds
 
+/* MMCM Reset. Sets or clears the reset to FMC ADC MMCM.
+ * Returns HALCS_CLIENT_SUCCESS if ok and HALCS_CLIIENT_ERR_SERVER if
+ * if server could not complete the request */
+halcs_client_err_e halcs_set_adc_mmcm_rst (halcs_client_t *self, char *service,
+        uint32_t adc_mmcm_rst);
+halcs_client_err_e halcs_get_adc_mmcm_rst (halcs_client_t *self, char *service,
+        uint32_t *adc_mmcm_rst);
+
 /* Simple AD9510 Config test.
  * Returns HALCS_CLIENT_SUCCESS if ok and HALCS_CLIIENT_ERR_SERVER if
  * if server could not complete the request */
diff --git a/libs/halcsclient/src/halcsclient/c/halcs_client_core.c b/libs/halcsclient/src/halcsclient/c/halcs_client_core.c
index 414f7a13..96cd171a 100644
--- a/libs/halcsclient/src/halcsclient/c/halcs_client_core.c
+++ b/libs/halcsclient/src/halcsclient/c/halcs_client_core.c
@@ -339,6 +339,16 @@ PARAM_FUNC_CLIENT_READ(fmc_leds)
             fmc_leds);
 }
 
+PARAM_FUNC_CLIENT_WRITE(adc_mmcm_rst)
+{
+    return param_client_write (self, service, FMC_ADC_COMMON_OPCODE_MMCM_RST, adc_mmcm_rst);
+}
+
+PARAM_FUNC_CLIENT_READ(adc_mmcm_rst)
+{
+     return param_client_read (self, service, FMC_ADC_COMMON_OPCODE_MMCM_RST, adc_mmcm_rst);
+}
+
 PARAM_FUNC_CLIENT_WRITE(adc_test_data_en)
 {
     return param_client_write (self, service, FMC_ADC_COMMON_OPCODE_TEST_DATA_EN, adc_test_data_en);