From 824a3e5dec3aabc91428f009c1f439a75f577469 Mon Sep 17 00:00:00 2001 From: Jay Foad Date: Thu, 25 Jan 2024 15:17:06 +0000 Subject: [PATCH] [AMDGPU] Do not bother adding reserved registers to liveins (#79436) Tweak the implementation of llvm.amdgcn.wave.id to not add TTMP8 to the function liveins. --- llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp | 4 +--- llvm/lib/Target/AMDGPU/SIISelLowering.cpp | 3 +-- 2 files changed, 2 insertions(+), 5 deletions(-) diff --git a/llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp b/llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp index e98ede88a7e2db..17ffb7ec988f0a 100644 --- a/llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp +++ b/llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp @@ -6890,9 +6890,7 @@ bool AMDGPULegalizerInfo::legalizeWaveID(MachineInstr &MI, return false; LLT S32 = LLT::scalar(32); Register DstReg = MI.getOperand(0).getReg(); - Register TTMP8 = - getFunctionLiveInPhysReg(B.getMF(), B.getTII(), AMDGPU::TTMP8, - AMDGPU::SReg_32RegClass, B.getDebugLoc(), S32); + auto TTMP8 = B.buildCopy(S32, Register(AMDGPU::TTMP8)); auto LSB = B.buildConstant(S32, 25); auto Width = B.buildConstant(S32, 5); B.buildUbfx(DstReg, TTMP8, LSB, Width); diff --git a/llvm/lib/Target/AMDGPU/SIISelLowering.cpp b/llvm/lib/Target/AMDGPU/SIISelLowering.cpp index c5ad9da88ec2b3..d6bf0d8cb2efa8 100644 --- a/llvm/lib/Target/AMDGPU/SIISelLowering.cpp +++ b/llvm/lib/Target/AMDGPU/SIISelLowering.cpp @@ -7926,8 +7926,7 @@ SDValue SITargetLowering::lowerWaveID(SelectionDAG &DAG, SDValue Op) const { return {}; SDLoc SL(Op); MVT VT = MVT::i32; - SDValue TTMP8 = CreateLiveInRegister(DAG, &AMDGPU::SReg_32RegClass, - AMDGPU::TTMP8, VT, SL); + SDValue TTMP8 = DAG.getCopyFromReg(DAG.getEntryNode(), SL, AMDGPU::TTMP8, VT); return DAG.getNode(AMDGPUISD::BFE_U32, SL, VT, TTMP8, DAG.getConstant(25, SL, VT), DAG.getConstant(5, SL, VT)); }