Skip to content
New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

Is there any generic cpu model support for RVV?Or how to add a cpu model for RISCV? #88851

Open
dinyy opened this issue Apr 16, 2024 · 9 comments
Labels
backend:RISC-V question A question, not bug report. Check out https://llvm.org/docs/GettingInvolved.html instead!

Comments

@dinyy
Copy link

dinyy commented Apr 16, 2024

While I‘m tryring OpenCL(PoCL) on RISC-V,it call llvm to generate it's kernel. I want to use -march=rv64gcv, but it occurs that I need -mcpu when I use opt. I need a cpu model which support RVV.
Now I change the code in llvm-project/llvm/lib/Target/RISCV/RISCVProcessors.td that :
image
but I don't find other place to change,I saw that page,but code has been changed so much.

@dinyy
Copy link
Author

dinyy commented Apr 16, 2024

I saw a PR here.But it occured some conflicts.

@EugeneZelenko EugeneZelenko added question A question, not bug report. Check out https://llvm.org/docs/GettingInvolved.html instead! backend:RISC-V and removed new issue labels Apr 16, 2024
@llvmbot
Copy link
Collaborator

llvmbot commented Apr 16, 2024

@llvm/issue-subscribers-backend-risc-v

Author: None (dinyy)

While I‘m tryring OpenCL(PoCL) on RISC-V,it call llvm to generate it's kernel. I want to use `-march=rv64gcv`, but it occurs that I need `-mcpu` when I use opt. I need a cpu model which support RVV. Now I change the code in `llvm-project/llvm/lib/Target/RISCV/RISCVProcessors.td` that : ![image](https://github.com/llvm/llvm-project/assets/107465691/ee44f36c-11d4-41e2-9c0c-4a53ab46801c) but I don't find other place to change,I saw that [page](https://discourse.llvm.org/t/custom-risc-v-processor-can-be-selected-via-mcpu-in-llc-but-not-in-clang/5849),but code has been changed so much.

@topperc
Copy link
Collaborator

topperc commented Apr 16, 2024

When https://discourse.llvm.org/t/custom-risc-v-processor-can-be-selected-via-mcpu-in-llc-but-not-in-clang/5849 was written, there were two files that contained the list of CPUs. One for the backend and one for the frontend.

Since early 2023, RISCVProcessors.td is used by both the frontend and the backend.

@michaelmaitland
Copy link
Contributor

michaelmaitland commented Apr 16, 2024

I saw a PR #84877 it occured some conflicts.

Have you seen #76357?

I think -march=rva23s64 and -march=rva23u64 profile has V extension. I did search for +v on this commit. You can see more about what extensions are part of which profiles here.

@topperc
Copy link
Collaborator

topperc commented Apr 16, 2024

I think -march=rva23s64 and -march=rva23u64 profile has V extension. I did search for +v on this commit. You can see more about what extensions are part of which profiles here.

-march is a clang option. The description mentions the opt tool which does not support -march

@dinyy
Copy link
Author

dinyy commented Apr 16, 2024

I think -march=rva23s64 and -march=rva23u64 profile has V extension. I did search for +v on this commit. You can see more about what extensions are part of which profiles here.

-march is a clang option. The description mentions the opt tool which does not support -march

So I must add a cpu model, do you mean I could add a cpu model just by changing llvm-project/llvm/lib/Target/RISCV/RISCVProcessors.td?
But I added as above picture, and failed.

@michaelmaitland
Copy link
Contributor

michaelmaitland commented Apr 16, 2024

63f742c might help you see what is needed to add a new mcpu. It looks like you were on the right path in your original screen shot.

@dinyy
Copy link
Author

dinyy commented Apr 16, 2024

63f742c might help you see what is needed to add a new mcpu. It looks like you were on the right path in your original screen shot.

Thank you very much, I will try again.

@wangpc-pp
Copy link
Contributor

I saw a PR here.But it occured some conflicts.

I can fix these conflicts and thanks for raising this problem! I think this can be a good use case to push #84877 forward. cc @asb @preames

Sign up for free to join this conversation on GitHub. Already have an account? Sign in to comment
Labels
backend:RISC-V question A question, not bug report. Check out https://llvm.org/docs/GettingInvolved.html instead!
Projects
None yet
Development

No branches or pull requests

6 participants