diff --git a/bolt/lib/Core/BinaryFunction.cpp b/bolt/lib/Core/BinaryFunction.cpp index ef3fba37817daa..c12217d549479b 100644 --- a/bolt/lib/Core/BinaryFunction.cpp +++ b/bolt/lib/Core/BinaryFunction.cpp @@ -2577,6 +2577,7 @@ struct CFISnapshot { case MCCFIInstruction::OpAdjustCfaOffset: case MCCFIInstruction::OpWindowSave: case MCCFIInstruction::OpNegateRAState: + case MCCFIInstruction::OpNegateRAStateWithPC: case MCCFIInstruction::OpLLVMDefAspaceCfa: case MCCFIInstruction::OpLabel: llvm_unreachable("unsupported CFI opcode"); @@ -2715,6 +2716,7 @@ struct CFISnapshotDiff : public CFISnapshot { case MCCFIInstruction::OpAdjustCfaOffset: case MCCFIInstruction::OpWindowSave: case MCCFIInstruction::OpNegateRAState: + case MCCFIInstruction::OpNegateRAStateWithPC: case MCCFIInstruction::OpLLVMDefAspaceCfa: case MCCFIInstruction::OpLabel: llvm_unreachable("unsupported CFI opcode"); @@ -2864,6 +2866,7 @@ BinaryFunction::unwindCFIState(int32_t FromState, int32_t ToState, case MCCFIInstruction::OpAdjustCfaOffset: case MCCFIInstruction::OpWindowSave: case MCCFIInstruction::OpNegateRAState: + case MCCFIInstruction::OpNegateRAStateWithPC: case MCCFIInstruction::OpLLVMDefAspaceCfa: case MCCFIInstruction::OpLabel: llvm_unreachable("unsupported CFI opcode"); diff --git a/clang-tools-extra/clang-tidy/modernize/UseDesignatedInitializersCheck.cpp b/clang-tools-extra/clang-tidy/modernize/UseDesignatedInitializersCheck.cpp index 2a0cc403b726e8..3132067f3d5ece 100644 --- a/clang-tools-extra/clang-tidy/modernize/UseDesignatedInitializersCheck.cpp +++ b/clang-tools-extra/clang-tidy/modernize/UseDesignatedInitializersCheck.cpp @@ -80,9 +80,13 @@ unsigned getNumberOfDesignated(const InitListExpr *SyntacticInitList) { }); } -AST_MATCHER(CXXRecordDecl, isAggregate) { return Node.isAggregate(); } +AST_MATCHER(CXXRecordDecl, isAggregate) { + return Node.hasDefinition() && Node.isAggregate(); +} -AST_MATCHER(CXXRecordDecl, isPOD) { return Node.isPOD(); } +AST_MATCHER(CXXRecordDecl, isPOD) { + return Node.hasDefinition() && Node.isPOD(); +} AST_MATCHER(InitListExpr, isFullyDesignated) { if (const InitListExpr *SyntacticForm = diff --git a/clang-tools-extra/docs/ReleaseNotes.rst b/clang-tools-extra/docs/ReleaseNotes.rst index 54118e5f92f417..ccebf74e8a67e7 100644 --- a/clang-tools-extra/docs/ReleaseNotes.rst +++ b/clang-tools-extra/docs/ReleaseNotes.rst @@ -216,6 +216,10 @@ Changes in existing checks a false positive when only an implicit conversion happened inside an initializer list. +- Improved :doc:`modernize-use-designated-initializers + ` check to fix a + crash when a class is declared but not defined. + - Improved :doc:`modernize-use-nullptr ` check to also recognize ``NULL``/``__null`` (but not ``0``) when used with a templated type. diff --git a/clang-tools-extra/test/clang-tidy/checkers/modernize/use-designated-initializers.cpp b/clang-tools-extra/test/clang-tidy/checkers/modernize/use-designated-initializers.cpp index 9b769ad0be23ca..048665b2e54ac5 100644 --- a/clang-tools-extra/test/clang-tidy/checkers/modernize/use-designated-initializers.cpp +++ b/clang-tools-extra/test/clang-tidy/checkers/modernize/use-designated-initializers.cpp @@ -201,3 +201,11 @@ DECLARE_S93; // CHECK-MESSAGES-MACROS: :[[@LINE-1]]:1: warning: use designated initializer list to initialize 'S9' [modernize-use-designated-initializers] // CHECK-MESSAGES-MACROS: :[[@LINE-4]]:28: note: expanded from macro 'DECLARE_S93' // CHECK-MESSAGES-MACROS: :[[@LINE-71]]:1: note: aggregate type is defined here + +// Issue #113652. +struct S14; + +struct S15{ + S15(S14& d):d{d}{} + S14& d; +}; diff --git a/clang/Maintainers.rst b/clang/Maintainers.rst index ee5334b02f7000..35c218d8e0e8fa 100644 --- a/clang/Maintainers.rst +++ b/clang/Maintainers.rst @@ -33,6 +33,12 @@ AST matchers | aaron\@aaronballman.com (email), aaron.ballman (Phabricator), AaronBallman (GitHub), AaronBallman (Discourse), aaronballman (Discord), AaronBallman (IRC) +AST Visitors +~~~~~~~~~~~~ +| Sirraide +| aeternalmail\@gmail.com (email), Sirraide (GitHub), Ætérnal (Discord), Sirraide (Discourse) + + Clang LLVM IR generation ~~~~~~~~~~~~~~~~~~~~~~~~ | John McCall @@ -57,6 +63,12 @@ Analysis & CFG | sgatev\@google.com (email), sgatev (Phabricator), sgatev (GitHub) +Sema +~~~~ +| Sirraide +| aeternalmail\@gmail.com (email), Sirraide (GitHub), Ætérnal (Discord), Sirraide (Discourse) + + Experimental new constant interpreter ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ | Timm Bäder @@ -71,6 +83,9 @@ Modules & serialization | Michael Spencer | bigcheesegs\@gmail.com (email), Bigcheese (Phabricator), Bigcheese (GitHub) +| Vassil Vassilev +| Vassil.Vassilev\@cern.ch (email), v.g.vassilev (Phabricator), vgvassilev (GitHub) + Templates ~~~~~~~~~ @@ -78,6 +93,12 @@ Templates | ekeane\@nvidia.com (email), ErichKeane (Phabricator), erichkeane (GitHub) +Lambdas +~~~~~~~ +| Corentin Jabot +| corentin.jabot\@gmail.com (email), cor3ntin (Phabricator), cor3ntin (GitHub) + + Debug information ~~~~~~~~~~~~~~~~~ | Adrian Prantl @@ -172,6 +193,12 @@ Attributes | ekeane\@nvidia.com (email), ErichKeane (Phabricator), erichkeane (GitHub) +Plugins +~~~~~~~ +| Vassil Vassilev +| Vassil.Vassilev\@cern.ch (email), v.g.vassilev (Phabricator), vgvassilev (GitHub) + + Inline assembly ~~~~~~~~~~~~~~~ | Eric Christopher @@ -225,6 +252,18 @@ C++ conformance | Hubert Tong | hubert.reinterpretcast\@gmail.com (email), hubert.reinterpretcast (Phabricator), hubert-reinterpretcast (GitHub) +| Shafik Yaghmour +| shafik.yaghmour\@intel.com (email), shafik (GitHub), shafik.yaghmour (Discord), shafik (Discourse) + +| Vlad Serebrennikov +| serebrennikov.vladislav\@gmail.com (email), Endilll (GitHub), Endill (Discord), Endill (Discourse) + + +C++ Defect Reports +~~~~~~~~~~~~~~~~~~ +| Vlad Serebrennikov +| serebrennikov.vladislav\@gmail.com (email), Endilll (GitHub), Endill (Discord), Endill (Discourse) + Objective-C/C++ conformance ~~~~~~~~~~~~~~~~~~~~~~~~~~~ @@ -244,6 +283,12 @@ OpenCL conformance | anastasia\@compiler-experts.com (email), Anastasia (Phabricator), AnastasiaStulova (GitHub) +OpenACC +~~~~~~~ +| Erich Keane +| ekeane\@nvidia.com (email), ErichKeane (Phabricator), erichkeane (GitHub) + + SYCL conformance ~~~~~~~~~~~~~~~~ | Alexey Bader diff --git a/clang/docs/ClangFormattedStatus.rst b/clang/docs/ClangFormattedStatus.rst deleted file mode 100644 index 2475a5d4b2775b..00000000000000 --- a/clang/docs/ClangFormattedStatus.rst +++ /dev/null @@ -1,8536 +0,0 @@ -.. raw:: html - - - -.. role:: none -.. role:: part -.. role:: good -.. role:: total - -====================== -Clang Formatted Status -====================== - -:doc:`ClangFormattedStatus` describes the state of LLVM source -tree in terms of conformance to :doc:`ClangFormat` as of: March 06, 2022 17:32:26 (`830ba4cebe79 `_). - - -.. list-table:: LLVM Clang-Format Status - :widths: 50 25 25 25 25 - :header-rows: 1 - - * - Directory - - Total Files - - Formatted Files - - Unformatted Files - - % Complete - * - bolt/include/bolt/Core - - `15` - - `10` - - `5` - - :part:`66%` - * - bolt/include/bolt/Passes - - `47` - - `47` - - `0` - - :good:`100%` - * - bolt/include/bolt/Profile - - `8` - - `8` - - `0` - - :good:`100%` - * - bolt/include/bolt/Rewrite - - `5` - - `4` - - `1` - - :part:`80%` - * - bolt/include/bolt/RuntimeLibs - - `3` - - `3` - - `0` - - :good:`100%` - * - bolt/include/bolt/Utils - - `4` - - `4` - - `0` - - :good:`100%` - * - bolt/lib/Core - - `14` - - `5` - - `9` - - :part:`35%` - * - bolt/lib/Passes - - `45` - - `21` - - `24` - - :part:`46%` - * - bolt/lib/Profile - - `7` - - `3` - - `4` - - :part:`42%` - * - bolt/lib/Rewrite - - `6` - - `0` - - `6` - - :none:`0%` - * - bolt/lib/RuntimeLibs - - `3` - - `3` - - `0` - - :good:`100%` - * - bolt/lib/Target/AArch64 - - `1` - - `0` - - `1` - - :none:`0%` - * - bolt/lib/Target/X86 - - `1` - - `0` - - `1` - - :none:`0%` - * - bolt/lib/Utils - - `2` - - `1` - - `1` - - :part:`50%` - * - bolt/runtime - - `3` - - `0` - - `3` - - :none:`0%` - * - bolt/tools/driver - - `1` - - `0` - - `1` - - :none:`0%` - * - bolt/tools/heatmap - - `1` - - `1` - - `0` - - :good:`100%` - * - bolt/tools/llvm-bolt-fuzzer - - `1` - - `1` - - `0` - - :good:`100%` - * - bolt/tools/merge-fdata - - `1` - - `0` - - `1` - - :none:`0%` - * - bolt/unittests/Core - - `1` - - `1` - - `0` - - :good:`100%` - * - clang/bindings/python/tests/cindex/INPUTS - - `5` - - `3` - - `2` - - :part:`60%` - * - clang/docs/analyzer/checkers - - `2` - - `0` - - `2` - - :none:`0%` - * - clang/examples/AnnotateFunctions - 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clang/include/clang/ASTMatchers - - `5` - - `1` - - `4` - - :part:`20%` - * - clang/include/clang/ASTMatchers/Dynamic - - `4` - - `1` - - `3` - - :part:`25%` - * - clang/include/clang/Basic - - `82` - - `32` - - `50` - - :part:`39%` - * - clang/include/clang/CodeGen - - `9` - - `0` - - `9` - - :none:`0%` - * - clang/include/clang/CrossTU - - `2` - - `1` - - `1` - - :part:`50%` - * - clang/include/clang/DirectoryWatcher - - `1` - - `1` - - `0` - - :good:`100%` - * - clang/include/clang/Driver - - `17` - - `4` - - `13` - - :part:`23%` - * - clang/include/clang/Edit - - `5` - - `1` - - `4` - - :part:`20%` - * - clang/include/clang/Format - - `1` - - `1` - - `0` - - :good:`100%` - * - clang/include/clang/Frontend - - `28` - - `7` - - `21` - - :part:`25%` - * - clang/include/clang/FrontendTool - - `1` - - `0` - - `1` - - :none:`0%` - * - clang/include/clang/Index - - `7` - - `2` - - `5` - - :part:`28%` - * - clang/include/clang/IndexSerialization - - `1` - - `1` - - `0` - - :good:`100%` - * - clang/include/clang/Interpreter - - `2` - - `2` - - `0` - - :good:`100%` - * - clang/include/clang/Lex - - `29` - - `6` - - `23` - - :part:`20%` - * - clang/include/clang/Parse - - `5` - - `2` - - `3` - - :part:`40%` - * - clang/include/clang/Rewrite/Core - - `6` - - `0` - - `6` - - :none:`0%` - * - clang/include/clang/Rewrite/Frontend - - `4` - - `0` - - `4` - - :none:`0%` - * - clang/include/clang/Sema - - `32` - - `3` - - `29` - - :part:`9%` - * - clang/include/clang/Serialization - - `14` - - `3` - - `11` - - :part:`21%` - * - clang/include/clang/StaticAnalyzer/Checkers - - `4` - - `1` - - `3` - - :part:`25%` - * - clang/include/clang/StaticAnalyzer/Core - - `5` - - `1` - - `4` - - :part:`20%` - * - clang/include/clang/StaticAnalyzer/Core/BugReporter - - `4` - - `1` - - `3` - - :part:`25%` - * - clang/include/clang/StaticAnalyzer/Core/PathSensitive - - `37` - - `10` - - `27` - - :part:`27%` - * - clang/include/clang/StaticAnalyzer/Frontend - - `5` - - `2` - - `3` - - :part:`40%` - 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* - clang/tools/clang-extdef-mapping - - `1` - - `0` - - `1` - - :none:`0%` - * - clang/tools/clang-format - - `1` - - `1` - - `0` - - :good:`100%` - * - clang/tools/clang-format/fuzzer - - `1` - - `0` - - `1` - - :none:`0%` - * - clang/tools/clang-fuzzer - - `6` - - `4` - - `2` - - :part:`66%` - * - clang/tools/clang-fuzzer/fuzzer-initialize - - `2` - - `0` - - `2` - - :none:`0%` - * - clang/tools/clang-fuzzer/handle-cxx - - `2` - - `0` - - `2` - - :none:`0%` - * - clang/tools/clang-fuzzer/handle-llvm - - `3` - - `1` - - `2` - - :part:`33%` - * - clang/tools/clang-fuzzer/proto-to-cxx - - `5` - - `0` - - `5` - - :none:`0%` - * - clang/tools/clang-fuzzer/proto-to-llvm - - `3` - - `0` - - `3` - - :none:`0%` - * - clang/tools/clang-import-test - - `1` - - `0` - - `1` - - :none:`0%` - * - clang/tools/clang-linker-wrapper - - `3` - - `2` - - `1` - - :part:`66%` - * - clang/tools/clang-nvlink-wrapper - - `1` - - `1` - - `0` - - :good:`100%` - * - clang/tools/clang-offload-bundler - - `1` - - `0` - - `1` - - :none:`0%` - * - clang/tools/clang-offload-wrapper - - `1` - - `1` - - `0` - - :good:`100%` - * - clang/tools/clang-refactor - - `4` - - `4` - - `0` - - :good:`100%` - * - clang/tools/clang-repl - - `1` - - `1` - - `0` - - :good:`100%` - * - clang/tools/clang-scan-deps - - `1` - - `1` - - `0` - - :good:`100%` - * - clang/tools/clang-shlib - - `1` - - `1` - - `0` - - :good:`100%` - * - clang/tools/diagtool - - `9` - - `0` - - `9` - - :none:`0%` - * - clang/tools/driver - - `4` - - `1` - - `3` - - :part:`25%` - * - clang/tools/libclang - - `35` - - `5` - - `30` - - :part:`14%` - * - clang/tools/scan-build-py/tests/functional/src/include - - `1` - - `1` - - `0` - - :good:`100%` - * - clang/unittests/Analysis - - `6` - - `2` - - `4` - - :part:`33%` - * - clang/unittests/Analysis/FlowSensitive - - `14` - - `13` - - `1` - - :part:`92%` - * - clang/unittests/AST - - `30` - - `8` - - `22` - - :part:`26%` - * - clang/unittests/ASTMatchers - - `6` - - `3` - - `3` - - :part:`50%` - * - clang/unittests/ASTMatchers/Dynamic - - `3` - - `0` - - `3` - - :none:`0%` - * - clang/unittests/Basic - - `8` - - `4` - - `4` - - :part:`50%` - * - clang/unittests/CodeGen - - `6` - - `1` - - `5` - - :part:`16%` - * - clang/unittests/CrossTU - - `1` - - `1` - - `0` - - :good:`100%` - * - clang/unittests/DirectoryWatcher - - `1` - - `0` - - `1` - - :none:`0%` - * - clang/unittests/Driver - - `5` - - `1` - - `4` - - :part:`20%` - * - clang/unittests/Format - - `24` - - `24` - - `0` - - :good:`100%` - * - clang/unittests/Frontend - - `11` - - `7` - - `4` - - :part:`63%` - * - clang/unittests/Index - - `1` - - `1` - - `0` - - :good:`100%` - * - clang/unittests/Interpreter - - `2` - - `2` - - `0` - - :good:`100%` - * - clang/unittests/Interpreter/ExceptionTests - - `1` - - `0` - - `1` - - :none:`0%` - * - clang/unittests/Introspection - - `1` - - `0` - - `1` - - :none:`0%` - * - clang/unittests/Lex - - `8` - - `4` - - `4` - - :part:`50%` - * - clang/unittests/libclang - - `2` - - `0` - - `2` - - :none:`0%` - * - clang/unittests/libclang/CrashTests - - `1` - - `1` - - `0` - - :good:`100%` - * - clang/unittests/Rename - - `6` - - `0` - - `6` - - :none:`0%` - * - clang/unittests/Rewrite - - `2` - - `1` - - `1` - - :part:`50%` - * - clang/unittests/Sema - - `3` - - `2` - - `1` - - :part:`66%` - * - clang/unittests/Serialization - - `2` - - `2` - - `0` - - :good:`100%` - * - clang/unittests/StaticAnalyzer - - `16` - - `7` - - `9` - - :part:`43%` - * - clang/unittests/Tooling - - `30` - - `10` - - `20` - - :part:`33%` - * - clang/unittests/Tooling/RecursiveASTVisitorTests - - `30` - - `12` - - `18` - - :part:`40%` - * - clang/unittests/Tooling/Syntax - - `7` - - `3` - - `4` - - :part:`42%` - * - clang/unittests/Tooling/Syntax/Pseudo - - `4` - - `4` - - `0` - - :good:`100%` - * - clang/utils/perf-training/cxx - - `1` - - `0` - - `1` - - :none:`0%` - * - clang/utils/TableGen - - `22` - - `3` - - `19` - - :part:`13%` - * - clang-tools-extra/clang-apply-replacements/include/clang-apply-replacements/Tooling - - `1` - - `1` - - `0` - - :good:`100%` - * - clang-tools-extra/clang-apply-replacements/lib/Tooling - - `1` - - `1` - - `0` - - :good:`100%` - * - clang-tools-extra/clang-apply-replacements/tool - - `1` - - `1` - - `0` - - :good:`100%` - * - clang-tools-extra/clang-change-namespace - - `2` - - `0` - - `2` - - :none:`0%` - * - clang-tools-extra/clang-change-namespace/tool - - `1` - - `0` - - `1` - - :none:`0%` - * - clang-tools-extra/clang-doc - - `17` - - `16` - - `1` - - :part:`94%` - * - clang-tools-extra/clang-doc/tool - - `1` - - `1` - - `0` - - :good:`100%` - * - clang-tools-extra/clang-include-fixer - - `13` - - `8` - - `5` - - :part:`61%` - * - clang-tools-extra/clang-include-fixer/find-all-symbols - - `17` - - `13` - - `4` - - :part:`76%` - * - clang-tools-extra/clang-include-fixer/find-all-symbols/tool - - `1` - - `0` - - `1` - - :none:`0%` - * - clang-tools-extra/clang-include-fixer/plugin - - `1` - - `1` - - `0` - - :good:`100%` - * - clang-tools-extra/clang-include-fixer/tool - - `1` - - `0` - - `1` - - :none:`0%` - * - clang-tools-extra/clang-move - - `4` - - `1` - - `3` - - :part:`25%` - * - clang-tools-extra/clang-move/tool - - `1` - - `1` - - `0` - - :good:`100%` - * - clang-tools-extra/clang-query - - `5` - - `4` - - `1` - - :part:`80%` - * - clang-tools-extra/clang-query/tool - - `1` - - `0` - - `1` - - :none:`0%` - * - clang-tools-extra/clang-reorder-fields - - `2` - - `1` - - `1` - - :part:`50%` - * - clang-tools-extra/clang-reorder-fields/tool - - `1` - - `0` - - `1` - - :none:`0%` - * - clang-tools-extra/clang-tidy - - `20` - - `14` - - `6` - - :part:`70%` - * - clang-tools-extra/clang-tidy/abseil - - `42` - - `31` - - `11` - - :part:`73%` - * - clang-tools-extra/clang-tidy/altera - - `11` - - `9` - - `2` - - :part:`81%` - * - clang-tools-extra/clang-tidy/android - - `33` - - `23` - - `10` - - :part:`69%` - * - clang-tools-extra/clang-tidy/boost - - `3` - - `3` - - `0` - - :good:`100%` - * - clang-tools-extra/clang-tidy/bugprone - - `125` - - `106` - - `19` - - :part:`84%` - * - clang-tools-extra/clang-tidy/cert - - `29` - - `28` - - `1` - - :part:`96%` - * - clang-tools-extra/clang-tidy/concurrency - - `5` - - `4` - - `1` - - :part:`80%` - * - clang-tools-extra/clang-tidy/cppcoreguidelines - - `45` - - `42` - - `3` - - :part:`93%` - * - clang-tools-extra/clang-tidy/darwin - - `5` - - `2` - - `3` - - :part:`40%` - * - clang-tools-extra/clang-tidy/fuchsia - - `15` - - `10` - - `5` - - :part:`66%` - * - clang-tools-extra/clang-tidy/google - - `33` - - `22` - - `11` - - :part:`66%` - * - clang-tools-extra/clang-tidy/hicpp - - `9` - - `7` - - `2` - - :part:`77%` - * - clang-tools-extra/clang-tidy/linuxkernel - - `3` - - `2` - - `1` - - :part:`66%` - * - clang-tools-extra/clang-tidy/llvm - - `11` - - `10` - - `1` - - :part:`90%` - * - clang-tools-extra/clang-tidy/llvmlibc - - `7` - - `7` - - `0` - - :good:`100%` - * - clang-tools-extra/clang-tidy/misc - - `33` - - `30` - - `3` - - :part:`90%` - * - clang-tools-extra/clang-tidy/modernize - - `67` - - `48` - - `19` - - :part:`71%` - * - clang-tools-extra/clang-tidy/mpi - - `5` - - `5` - - `0` - - :good:`100%` - * - clang-tools-extra/clang-tidy/objc - - `17` - - `12` - - `5` - - :part:`70%` - * - clang-tools-extra/clang-tidy/openmp - - `5` - - `5` - - `0` - - :good:`100%` - * - clang-tools-extra/clang-tidy/performance - - `31` - - `24` - - `7` - - :part:`77%` - * - clang-tools-extra/clang-tidy/plugin - - `1` - - `1` - - `0` - - :good:`100%` - * - clang-tools-extra/clang-tidy/portability - - `5` - - `3` - - `2` - - :part:`60%` - * - clang-tools-extra/clang-tidy/readability - - `88` - - `76` - - `12` - - :part:`86%` - * - clang-tools-extra/clang-tidy/tool - - `3` - - `2` - - `1` - - :part:`66%` - * - clang-tools-extra/clang-tidy/utils - - `35` - - `31` - - `4` - - :part:`88%` - * - clang-tools-extra/clang-tidy/zircon - - `3` - - `3` - - `0` - - :good:`100%` - * - clang-tools-extra/clangd - - `97` - - `81` - - `16` - - :part:`83%` - * - clang-tools-extra/clangd/benchmarks - - `1` - - `1` - - `0` - - :good:`100%` - * - clang-tools-extra/clangd/benchmarks/CompletionModel - - `1` - - `0` - - `1` - - :none:`0%` - * - clang-tools-extra/clangd/fuzzer - - `2` - - `2` - - `0` - - :good:`100%` - * - clang-tools-extra/clangd/index - - `39` - - `36` - - `3` - - :part:`92%` - * - clang-tools-extra/clangd/index/dex - - `9` - - `7` - - `2` - - :part:`77%` - * - clang-tools-extra/clangd/index/dex/dexp - - `1` - - `1` - - `0` - - :good:`100%` - * - clang-tools-extra/clangd/index/remote - - `2` - - `2` - - `0` - - :good:`100%` - * - clang-tools-extra/clangd/index/remote/marshalling - - `2` - - `2` - - `0` - - :good:`100%` - * - clang-tools-extra/clangd/index/remote/monitor - - `1` - - `1` - - `0` - - :good:`100%` - * - clang-tools-extra/clangd/index/remote/server - - `1` - - `1` - - `0` - - :good:`100%` - * - clang-tools-extra/clangd/index/remote/unimplemented - - `1` - - `1` - - `0` - - :good:`100%` - * - clang-tools-extra/clangd/indexer - - `1` - - `1` - - `0` - - :good:`100%` - * - clang-tools-extra/clangd/refactor - - `6` - - `5` - - `1` - - :part:`83%` - * - clang-tools-extra/clangd/refactor/tweaks - - `14` - - `10` - - `4` - - :part:`71%` - * - clang-tools-extra/clangd/support - - `25` - - `24` - - `1` - - :part:`96%` - * - clang-tools-extra/clangd/tool - - `2` - - `2` - - `0` - - :good:`100%` - * - clang-tools-extra/clangd/unittests - - `79` - - `66` - - `13` - - :part:`83%` - * - clang-tools-extra/clangd/unittests/decision_forest_model - - `1` - - `1` - - `0` - - :good:`100%` - * - clang-tools-extra/clangd/unittests/remote - - `1` - - `1` - - `0` - - :good:`100%` - * - clang-tools-extra/clangd/unittests/support - - `11` - - `11` - - `0` - - :good:`100%` - * - clang-tools-extra/clangd/unittests/tweaks - - `20` - - `19` - - `1` - - :part:`95%` - * - clang-tools-extra/clangd/unittests/xpc - - `1` - - `1` - - `0` - - :good:`100%` - * - clang-tools-extra/clangd/xpc - - `3` - - `3` - - `0` - - :good:`100%` - * - clang-tools-extra/clangd/xpc/framework - - `1` - - `1` - - `0` - - :good:`100%` - * - clang-tools-extra/clangd/xpc/test-client - - `1` - - `1` - - `0` - - :good:`100%` - * - clang-tools-extra/modularize - - `9` - - `1` - - `8` - - :part:`11%` - * - clang-tools-extra/pp-trace - - `3` - - `1` - - `2` - - :part:`33%` - * - clang-tools-extra/tool-template - - `1` - - `1` - - `0` - - :good:`100%` - * - clang-tools-extra/unittests/clang-apply-replacements - - `1` - - `1` - - `0` - - :good:`100%` - * - clang-tools-extra/unittests/clang-change-namespace - - `1` - - `0` - - `1` - - :none:`0%` - * - clang-tools-extra/unittests/clang-doc - - `9` - - `9` - - `0` - - :good:`100%` - * - clang-tools-extra/unittests/clang-include-fixer - - `2` - - `0` - - `2` - - :none:`0%` - * - clang-tools-extra/unittests/clang-include-fixer/find-all-symbols - - `1` - - `0` - - `1` - - :none:`0%` - * - clang-tools-extra/unittests/clang-move - - `1` - - `0` - - `1` - - :none:`0%` - * - clang-tools-extra/unittests/clang-query - - `2` - - `0` - - `2` - - :none:`0%` - * - clang-tools-extra/unittests/clang-tidy - - `16` - - `9` - - `7` - - :part:`56%` - * - clang-tools-extra/unittests/include/common - - `1` - - `0` - - `1` - - :none:`0%` - * - compiler-rt/include/fuzzer - - `1` - - `0` - - `1` - - :none:`0%` - * - compiler-rt/include/sanitizer - - `15` - - `3` - - `12` - - :part:`20%` - * - compiler-rt/include/xray - - `3` - - `2` - - `1` - - :part:`66%` - * - compiler-rt/lib/asan - - `57` - - `5` - - `52` - - :part:`8%` - * - compiler-rt/lib/asan/tests - - `17` - - `1` - - `16` - - :part:`5%` - * - compiler-rt/lib/BlocksRuntime - - `2` - - `0` - - `2` - - :none:`0%` - * - compiler-rt/lib/builtins - - `11` - - `9` - - `2` - - :part:`81%` - * - compiler-rt/lib/builtins/arm - - `1` - - `0` - - `1` - - :none:`0%` - * - compiler-rt/lib/builtins/ppc - - `1` - - `1` - - `0` - - :good:`100%` - * - compiler-rt/lib/cfi - - `1` - - `0` - - `1` - - :none:`0%` - * - compiler-rt/lib/dfsan - - `14` - - `9` - - `5` - - :part:`64%` - * - compiler-rt/lib/fuzzer - - `47` - - `9` - - `38` - - :part:`19%` - * - compiler-rt/lib/fuzzer/afl - - `1` - - `0` - - `1` - - :none:`0%` - * - compiler-rt/lib/fuzzer/dataflow - - `3` - - `0` - - `3` - - :none:`0%` - * - compiler-rt/lib/fuzzer/tests - - `2` - - `1` - - `1` - - :part:`50%` - * - compiler-rt/lib/gwp_asan - - `12` - - `12` - - `0` - - :good:`100%` - * - compiler-rt/lib/gwp_asan/optional - - `10` - - `10` - - `0` - - :good:`100%` - * - compiler-rt/lib/gwp_asan/platform_specific - - `13` - - `13` - - `0` - - :good:`100%` - * - compiler-rt/lib/gwp_asan/tests - - `15` - - `14` - - `1` - - :part:`93%` - * - compiler-rt/lib/gwp_asan/tests/platform_specific - - `1` - - `1` - - `0` - - :good:`100%` - * - compiler-rt/lib/hwasan - - `30` - - `9` - - `21` - - :part:`30%` - * - compiler-rt/lib/interception - - `8` - - `1` - - `7` - - :part:`12%` - * - compiler-rt/lib/interception/tests - - `3` - - `1` - - `2` - - :part:`33%` - * - compiler-rt/lib/lsan - - `20` - - `4` - - `16` - - :part:`20%` - * - compiler-rt/lib/memprof - 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- :part:`88%` - * - llvm/lib/MCA/HardwareUnits - - `6` - - `4` - - `2` - - :part:`66%` - * - llvm/lib/MCA/Stages - - `8` - - `7` - - `1` - - :part:`87%` - * - llvm/lib/ObjCopy - - `4` - - `3` - - `1` - - :part:`75%` - * - llvm/lib/ObjCopy/COFF - - `7` - - `7` - - `0` - - :good:`100%` - * - llvm/lib/ObjCopy/ELF - - `3` - - `3` - - `0` - - :good:`100%` - * - llvm/lib/ObjCopy/MachO - - `9` - - `9` - - `0` - - :good:`100%` - * - llvm/lib/ObjCopy/wasm - - `7` - - `7` - - `0` - - :good:`100%` - * - llvm/lib/ObjCopy/XCOFF - - `6` - - `3` - - `3` - - :part:`50%` - * - llvm/lib/Object - - `31` - - `16` - - `15` - - :part:`51%` - * - llvm/lib/ObjectYAML - - `23` - - `9` - - `14` - - :part:`39%` - * - llvm/lib/Option - - `4` - - `0` - - `4` - - :none:`0%` - * - llvm/lib/Passes - - `6` - - `3` - - `3` - - :part:`50%` - * - llvm/lib/ProfileData - - `11` - - `4` - - `7` - - :part:`36%` - * - llvm/lib/ProfileData/Coverage - - `3` - - `0` - - `3` - - :none:`0%` - * - llvm/lib/Remarks - - `13` - - `10` - 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* - llvm/lib/Target/CSKY/Disassembler - - `1` - - `1` - - `0` - - :good:`100%` - * - llvm/lib/Target/CSKY/MCTargetDesc - - `15` - - `14` - - `1` - - :part:`93%` - * - llvm/lib/Target/CSKY/TargetInfo - - `2` - - `2` - - `0` - - :good:`100%` - * - llvm/lib/Target/Hexagon - - `80` - - `6` - - `74` - - :part:`7%` - * - llvm/lib/Target/Hexagon/AsmParser - - `1` - - `0` - - `1` - - :none:`0%` - * - llvm/lib/Target/Hexagon/Disassembler - - `1` - - `0` - - `1` - - :none:`0%` - * - llvm/lib/Target/Hexagon/MCTargetDesc - - `26` - - `6` - - `20` - - :part:`23%` - * - llvm/lib/Target/Hexagon/TargetInfo - - `2` - - `1` - - `1` - - :part:`50%` - * - llvm/lib/Target/Lanai - - `28` - - `20` - - `8` - - :part:`71%` - * - llvm/lib/Target/Lanai/AsmParser - - `1` - - `0` - - `1` - - :none:`0%` - * - llvm/lib/Target/Lanai/Disassembler - - `2` - - `2` - - `0` - - :good:`100%` - * - llvm/lib/Target/Lanai/MCTargetDesc - - `13` - - `12` - - `1` - - :part:`92%` - * - llvm/lib/Target/Lanai/TargetInfo - - `2` - - `2` - - `0` - - :good:`100%` - * - llvm/lib/Target/LoongArch - - `19` - - `19` - - `0` - - :good:`100%` - * - llvm/lib/Target/LoongArch/MCTargetDesc - - `12` - - `12` - - `0` - - :good:`100%` - * - llvm/lib/Target/LoongArch/TargetInfo - - `2` - - `2` - - `0` - - :good:`100%` - * - llvm/lib/Target/M68k - - `26` - - `25` - - `1` - - :part:`96%` - * - llvm/lib/Target/M68k/AsmParser - - `1` - - `1` - - `0` - - :good:`100%` - * - llvm/lib/Target/M68k/Disassembler - - `1` - - `1` - - `0` - - :good:`100%` - * - llvm/lib/Target/M68k/GISel - - `7` - - `6` - - `1` - - :part:`85%` - * - llvm/lib/Target/M68k/MCTargetDesc - - `12` - - `11` - - `1` - - :part:`91%` - * - llvm/lib/Target/M68k/TargetInfo - - `2` - - `2` - - `0` - - :good:`100%` - * - llvm/lib/Target/Mips - - `70` - - `12` - - `58` - - :part:`17%` - * - llvm/lib/Target/Mips/AsmParser - - `1` - - `0` - - `1` - - :none:`0%` - * - llvm/lib/Target/Mips/Disassembler - - `1` - - `0` - - `1` - - :none:`0%` - * - llvm/lib/Target/Mips/MCTargetDesc - - `25` - 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* - mlir/lib/Target/LLVMIR/Dialect/ArmSVE - - `1` - - `1` - - `0` - - :good:`100%` - * - mlir/lib/Target/LLVMIR/Dialect/LLVMIR - - `1` - - `1` - - `0` - - :good:`100%` - * - mlir/lib/Target/LLVMIR/Dialect/NVVM - - `1` - - `1` - - `0` - - :good:`100%` - * - mlir/lib/Target/LLVMIR/Dialect/OpenACC - - `1` - - `0` - - `1` - - :none:`0%` - * - mlir/lib/Target/LLVMIR/Dialect/OpenMP - - `1` - - `1` - - `0` - - :good:`100%` - * - mlir/lib/Target/LLVMIR/Dialect/ROCDL - - `1` - - `1` - - `0` - - :good:`100%` - * - mlir/lib/Target/LLVMIR/Dialect/X86Vector - - `1` - - `1` - - `0` - - :good:`100%` - * - mlir/lib/Target/SPIRV - - `2` - - `2` - - `0` - - :good:`100%` - * - mlir/lib/Target/SPIRV/Deserialization - - `4` - - `3` - - `1` - - :part:`75%` - * - mlir/lib/Target/SPIRV/Serialization - - `4` - - `3` - - `1` - - :part:`75%` - * - mlir/lib/Tools/mlir-lsp-server - - `5` - - `4` - - `1` - - :part:`80%` - * - mlir/lib/Tools/mlir-lsp-server/lsp - - `6` - - `4` - - `2` - - :part:`66%` - * - mlir/lib/Tools/mlir-reduce - - `1` - - `1` - - `0` - - :good:`100%` - * - mlir/lib/Tools/PDLL/AST - - `6` - - `5` - - `1` - - :part:`83%` - * - mlir/lib/Tools/PDLL/CodeGen - - `2` - - `1` - - `1` - - :part:`50%` - * - mlir/lib/Tools/PDLL/ODS - - `3` - - `3` - - `0` - - :good:`100%` - * - mlir/lib/Tools/PDLL/Parser - - `3` - - `1` - - `2` - - :part:`33%` - * - mlir/lib/Transforms - - `13` - - `11` - - `2` - - :part:`84%` - * - mlir/lib/Transforms/Utils - - `6` - - `6` - - `0` - - :good:`100%` - * - mlir/lib/Translation - - `1` - - `1` - - `0` - - :good:`100%` - * - mlir/tools/mlir-cpu-runner - - `1` - - `1` - - `0` - - :good:`100%` - * - mlir/tools/mlir-linalg-ods-gen - - `1` - - `1` - - `0` - - :good:`100%` - * - mlir/tools/mlir-lsp-server - - `1` - - `1` - - `0` - - :good:`100%` - * - mlir/tools/mlir-opt - - `1` - - `1` - - `0` - - :good:`100%` - * - mlir/tools/mlir-pdll - - `1` - - `1` - - `0` - - :good:`100%` - * - mlir/tools/mlir-reduce - - `1` - - `1` - - `0` - - :good:`100%` - * - mlir/tools/mlir-shlib - - `1` - - `1` - - `0` - - :good:`100%` - * - mlir/tools/mlir-spirv-cpu-runner - - `1` - - `1` - - `0` - - :good:`100%` - * - mlir/tools/mlir-tblgen - - `29` - - `28` - - `1` - - :part:`96%` - * - mlir/tools/mlir-translate - - `1` - - `1` - - `0` - - :good:`100%` - * - mlir/tools/mlir-vulkan-runner - - `4` - - `4` - - `0` - - :good:`100%` - * - mlir/unittests/Analysis/Presburger - - `8` - - `8` - - `0` - - :good:`100%` - * - mlir/unittests/Conversion/PDLToPDLInterp - - `1` - - `1` - - `0` - - :good:`100%` - * - mlir/unittests/Dialect - - `1` - - `1` - - `0` - - :good:`100%` - * - mlir/unittests/Dialect/Affine/Analysis - - `3` - - `3` - - `0` - - :good:`100%` - * - mlir/unittests/Dialect/Quant - - `1` - - `1` - - `0` - - :good:`100%` - * - mlir/unittests/Dialect/SparseTensor - - `1` - - `1` - - `0` - - :good:`100%` - * - mlir/unittests/Dialect/SPIRV - - `2` - - `2` - - `0` - - :good:`100%` - * - mlir/unittests/Dialect/Utils - - `1` - - `1` - - `0` - - :good:`100%` - * - mlir/unittests/ExecutionEngine - - `1` - - `1` - - `0` - - :good:`100%` - * - mlir/unittests/Interfaces - - `3` - - `3` - - `0` - - :good:`100%` - * - mlir/unittests/IR - - `7` - - `7` - - `0` - - :good:`100%` - * - mlir/unittests/Pass - - `3` - - `3` - - `0` - - :good:`100%` - * - mlir/unittests/Rewrite - - `1` - - `1` - - `0` - - :good:`100%` - * - mlir/unittests/Support - - `5` - - `4` - - `1` - - :part:`80%` - * - mlir/unittests/TableGen - - `5` - - `3` - - `2` - - :part:`60%` - * - mlir/unittests/Transforms - - `2` - - `2` - - `0` - - :good:`100%` - * - openmp/libompd/src - - `9` - - `9` - - `0` - - :good:`100%` - * - openmp/libomptarget/DeviceRTL/include - - `8` - - `8` - - `0` - - :good:`100%` - * - openmp/libomptarget/DeviceRTL/src - - `12` - - `9` - - `3` - - :part:`75%` - * - openmp/libomptarget/include - - `9` - - `8` - - `1` - - :part:`88%` - * - openmp/libomptarget/plugins/amdgpu/dynamic_hsa - - `3` - - `2` - - `1` - - :part:`66%` - * - openmp/libomptarget/plugins/amdgpu/impl - - `13` - - `10` - - `3` - - :part:`76%` - * - openmp/libomptarget/plugins/amdgpu/src - - `2` - - `1` - - `1` - - :part:`50%` - * - openmp/libomptarget/plugins/common/elf_common - - `2` - - `2` - - `0` - - :good:`100%` - * - openmp/libomptarget/plugins/common/MemoryManager - - `1` - - `1` - - `0` - - :good:`100%` - * - openmp/libomptarget/plugins/cuda/dynamic_cuda - - `2` - - `2` - - `0` - - :good:`100%` - * - openmp/libomptarget/plugins/cuda/src - - `1` - - `0` - - `1` - - :none:`0%` - * - openmp/libomptarget/plugins/generic-elf-64bit/src - - `1` - - `1` - - `0` - - :good:`100%` - * - openmp/libomptarget/plugins/remote/include - - `1` - - `1` - - `0` - - :good:`100%` - * - openmp/libomptarget/plugins/remote/lib - - `1` - - `0` - - `1` - - :none:`0%` - * - openmp/libomptarget/plugins/remote/server - - `3` - - `3` - - `0` - - :good:`100%` - * - openmp/libomptarget/plugins/remote/src - - `3` - - `2` - - `1` - - :part:`66%` - * - openmp/libomptarget/plugins/ve/src - - `1` - - `1` - - `0` - - :good:`100%` - * - openmp/libomptarget/src - - `7` - - `6` - - `1` - - :part:`85%` - * - openmp/libomptarget/tools/deviceinfo - - `1` - - `1` - - `0` - - :good:`100%` - * - openmp/runtime/doc/doxygen - - `1` - - `1` - - `0` - - :good:`100%` - * - openmp/runtime/src - - `75` - - `65` - - `10` - - :part:`86%` - * - openmp/runtime/src/thirdparty/ittnotify - - `6` - - `5` - - `1` - - :part:`83%` - * - openmp/runtime/src/thirdparty/ittnotify/legacy - - `1` - - `1` - - `0` - - :good:`100%` - * - openmp/tools/archer - - `1` - - `1` - - `0` - - :good:`100%` - * - openmp/tools/archer/tests/ompt - - `1` - - `1` - - `0` - - :good:`100%` - * - openmp/tools/multiplex - - `1` - - `1` - - `0` - - :good:`100%` - * - openmp/tools/multiplex/tests - - `1` - - `1` - - `0` - - :good:`100%` - * - openmp/tools/multiplex/tests/custom_data_storage - - `2` - - `1` - - `1` - - :part:`50%` - * - openmp/tools/multiplex/tests/print - - `2` - - `2` - - `0` - - :good:`100%` - * - polly/include/polly - - `25` - - `25` - - `0` - - :good:`100%` - * - polly/include/polly/CodeGen - - `14` - - `14` - - `0` - - :good:`100%` - * - polly/include/polly/Support - - `12` - - `12` - - `0` - - :good:`100%` - * - polly/lib/Analysis - - `9` - - `9` - - `0` - - :good:`100%` - * - polly/lib/CodeGen - - `15` - - `15` - - `0` - - :good:`100%` - * - polly/lib/Exchange - - `1` - - `1` - - `0` - - :good:`100%` - * - polly/lib/External/isl - - `68` - - `1` - - `67` - - :part:`1%` - * - polly/lib/External/isl/imath - - `6` - - `1` - - `5` - - :part:`16%` - * - polly/lib/External/isl/imath_wrap - - `4` - - `0` - - `4` - - :none:`0%` - * - polly/lib/External/isl/include/isl - - `59` - - `9` - - `50` - - :part:`15%` - * - polly/lib/External/isl/interface - - `8` - - `1` - - `7` - - :part:`12%` - * - polly/lib/External/pet/include - - `1` - - `0` - - `1` - - :none:`0%` - * - polly/lib/External/ppcg - - `17` - - `0` - - `17` - - :none:`0%` - * - polly/lib/Plugin - - `1` - - `1` - - `0` - - :good:`100%` - * - polly/lib/Support - - `11` - - `11` - - `0` - - :good:`100%` - * - polly/lib/Transform - - `15` - - `15` - - `0` - - :good:`100%` - * - polly/tools/GPURuntime - - `1` - - `1` - - `0` - - :good:`100%` - * - polly/unittests/DeLICM - - `1` - - `1` - - `0` - - :good:`100%` - * - polly/unittests/Flatten - - `1` - - `1` - - `0` - - :good:`100%` - * - polly/unittests/Isl - - `1` - - `1` - - `0` - - :good:`100%` - * - polly/unittests/ScheduleOptimizer - - `1` - - `1` - - `0` - - :good:`100%` - * - polly/unittests/ScopPassManager - - `1` - - `1` - - `0` - - :good:`100%` - * - polly/unittests/Support - - `1` - - `1` - - `0` - - :good:`100%` - * - pstl/include/pstl/internal - - `23` - - `16` - - `7` - - :part:`69%` - * - pstl/include/pstl/internal/omp - - `11` - - `8` - - `3` - - :part:`72%` - * - third-party/benchmark/cmake - - `5` - - `1` - - `4` - - :part:`20%` - * - third-party/benchmark/include/benchmark - - `1` - - `0` - - `1` - - :none:`0%` - * - third-party/benchmark/src - - `21` - - `21` - - `0` - - :good:`100%` - * - utils/bazel/llvm-project-overlay/clang/include/clang/Config - - `1` - - `1` - - `0` - - :good:`100%` - * - utils/bazel/llvm-project-overlay/llvm/include/llvm/Config - - `2` - - `1` - - `1` - - :part:`50%` - * - Total - - :total:`16432` - - :total:`8857` - - :total:`7575` - - :total:`53%` diff --git a/clang/docs/ReleaseNotes.rst b/clang/docs/ReleaseNotes.rst index a72a0e19c37b19..b001a693852457 100644 --- a/clang/docs/ReleaseNotes.rst +++ b/clang/docs/ReleaseNotes.rst @@ -140,7 +140,7 @@ C++ Specific Potentially Breaking Changes unsigned operator""_udl_name(unsigned long long); - Clang will now produce an error diagnostic when [[clang::lifetimebound]] is - applied on a parameter of a function that returns void. This was previously + applied on a parameter of a function that returns void. This was previously ignored and had no effect. (#GH107556) .. code-block:: c++ @@ -469,7 +469,8 @@ Bug Fixes in This Version - Fixed a crash using ``__array_rank`` on 64-bit targets. (#GH113044). - The warning emitted for an unsupported register variable type now points to the unsupported type instead of the ``register`` keyword (#GH109776). -- Fixed a crash when emit ctor for global variant with flexible array init (#GH113187). +- Fixed a crash when emit ctor for global variant with flexible array init (#GH113187). +- Fixed a crash when GNU statement expression contains invalid statement (#GH113468). Bug Fixes to Compiler Builtins ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ @@ -573,6 +574,8 @@ Bug Fixes to C++ Support (#GH95854). - Fixed an assertion failure when evaluating an invalid expression in an array initializer. (#GH112140) - Fixed an assertion failure in range calculations for conditional throw expressions. (#GH111854) +- Clang now correctly ignores previous partial specializations of member templates explicitly specialized for + an implicitly instantiated class template specialization. (#GH51051) - Fixed an assertion failure caused by an invalid template instantiation pattern for adding instantiated parameters to the scope in friend functions with defaulted parameters. (#GH113324). diff --git a/clang/docs/tools/clang-formatted-files.txt b/clang/docs/tools/clang-formatted-files.txt deleted file mode 100644 index 67ff085144f4de..00000000000000 --- a/clang/docs/tools/clang-formatted-files.txt +++ /dev/null @@ -1,8827 +0,0 @@ -bolt/include/bolt/Core/BinaryData.h -bolt/include/bolt/Core/BinaryEmitter.h -bolt/include/bolt/Core/BinaryLoop.h -bolt/include/bolt/Core/BinarySection.h -bolt/include/bolt/Core/DebugData.h -bolt/include/bolt/Core/Exceptions.h -bolt/include/bolt/Core/JumpTable.h -bolt/include/bolt/Core/MCPlus.h -bolt/include/bolt/Core/MCPlusBuilder.h -bolt/include/bolt/Core/ParallelUtilities.h -bolt/include/bolt/Passes/ADRRelaxationPass.h -bolt/include/bolt/Passes/Aligner.h -bolt/include/bolt/Passes/AllocCombiner.h -bolt/include/bolt/Passes/AsmDump.h -bolt/include/bolt/Passes/BinaryFunctionCallGraph.h -bolt/include/bolt/Passes/BinaryPasses.h -bolt/include/bolt/Passes/CacheMetrics.h -bolt/include/bolt/Passes/CallGraph.h -bolt/include/bolt/Passes/CallGraphWalker.h -bolt/include/bolt/Passes/DataflowAnalysis.h -bolt/include/bolt/Passes/DataflowInfoManager.h -bolt/include/bolt/Passes/DominatorAnalysis.h -bolt/include/bolt/Passes/FrameAnalysis.h -bolt/include/bolt/Passes/FrameOptimizer.h -bolt/include/bolt/Passes/HFSort.h -bolt/include/bolt/Passes/IdenticalCodeFolding.h -bolt/include/bolt/Passes/IndirectCallPromotion.h -bolt/include/bolt/Passes/Inliner.h -bolt/include/bolt/Passes/Instrumentation.h -bolt/include/bolt/Passes/InstrumentationSummary.h -bolt/include/bolt/Passes/JTFootprintReduction.h -bolt/include/bolt/Passes/LivenessAnalysis.h -bolt/include/bolt/Passes/LongJmp.h -bolt/include/bolt/Passes/LoopInversionPass.h -bolt/include/bolt/Passes/MCF.h -bolt/include/bolt/Passes/PatchEntries.h -bolt/include/bolt/Passes/PLTCall.h -bolt/include/bolt/Passes/ReachingDefOrUse.h -bolt/include/bolt/Passes/ReachingInsns.h -bolt/include/bolt/Passes/RegAnalysis.h -bolt/include/bolt/Passes/RegReAssign.h -bolt/include/bolt/Passes/ReorderAlgorithm.h -bolt/include/bolt/Passes/ReorderData.h -bolt/include/bolt/Passes/ReorderFunctions.h -bolt/include/bolt/Passes/ReorderUtils.h -bolt/include/bolt/Passes/RetpolineInsertion.h -bolt/include/bolt/Passes/ShrinkWrapping.h -bolt/include/bolt/Passes/SplitFunctions.h -bolt/include/bolt/Passes/StackAllocationAnalysis.h -bolt/include/bolt/Passes/StackAvailableExpressions.h -bolt/include/bolt/Passes/StackPointerTracking.h -bolt/include/bolt/Passes/StackReachingUses.h -bolt/include/bolt/Passes/StokeInfo.h -bolt/include/bolt/Passes/TailDuplication.h -bolt/include/bolt/Passes/ThreeWayBranch.h -bolt/include/bolt/Passes/ValidateInternalCalls.h -bolt/include/bolt/Passes/VeneerElimination.h -bolt/include/bolt/Profile/BoltAddressTranslation.h -bolt/include/bolt/Profile/DataAggregator.h -bolt/include/bolt/Profile/DataReader.h -bolt/include/bolt/Profile/Heatmap.h -bolt/include/bolt/Profile/ProfileReaderBase.h -bolt/include/bolt/Profile/ProfileYAMLMapping.h -bolt/include/bolt/Profile/YAMLProfileReader.h -bolt/include/bolt/Profile/YAMLProfileWriter.h -bolt/include/bolt/Rewrite/BinaryPassManager.h -bolt/include/bolt/Rewrite/DWARFRewriter.h -bolt/include/bolt/Rewrite/ExecutableFileMemoryManager.h -bolt/include/bolt/Rewrite/MachORewriteInstance.h -bolt/include/bolt/RuntimeLibs/HugifyRuntimeLibrary.h -bolt/include/bolt/RuntimeLibs/InstrumentationRuntimeLibrary.h -bolt/include/bolt/RuntimeLibs/RuntimeLibrary.h -bolt/include/bolt/Utils/CommandLineOpts.h -bolt/include/bolt/Utils/NameResolver.h -bolt/include/bolt/Utils/NameShortener.h -bolt/include/bolt/Utils/Utils.h -bolt/lib/Core/BinaryBasicBlock.cpp -bolt/lib/Core/BinarySection.cpp -bolt/lib/Core/DebugData.cpp -bolt/lib/Core/JumpTable.cpp -bolt/lib/Core/MCPlusBuilder.cpp -bolt/lib/Passes/ADRRelaxationPass.cpp -bolt/lib/Passes/AllocCombiner.cpp -bolt/lib/Passes/AsmDump.cpp -bolt/lib/Passes/BinaryFunctionCallGraph.cpp -bolt/lib/Passes/CacheMetrics.cpp -bolt/lib/Passes/CallGraphWalker.cpp -bolt/lib/Passes/DataflowAnalysis.cpp -bolt/lib/Passes/DataflowInfoManager.cpp -bolt/lib/Passes/HFSort.cpp -bolt/lib/Passes/IndirectCallPromotion.cpp -bolt/lib/Passes/Instrumentation.cpp -bolt/lib/Passes/JTFootprintReduction.cpp -bolt/lib/Passes/LivenessAnalysis.cpp -bolt/lib/Passes/LoopInversionPass.cpp -bolt/lib/Passes/PettisAndHansen.cpp -bolt/lib/Passes/StackAllocationAnalysis.cpp -bolt/lib/Passes/StackPointerTracking.cpp -bolt/lib/Passes/StackReachingUses.cpp -bolt/lib/Passes/TailDuplication.cpp -bolt/lib/Passes/ThreeWayBranch.cpp -bolt/lib/Passes/ValidateInternalCalls.cpp -bolt/lib/Profile/BoltAddressTranslation.cpp -bolt/lib/Profile/Heatmap.cpp -bolt/lib/Profile/ProfileReaderBase.cpp -bolt/lib/RuntimeLibs/HugifyRuntimeLibrary.cpp -bolt/lib/RuntimeLibs/InstrumentationRuntimeLibrary.cpp -bolt/lib/RuntimeLibs/RuntimeLibrary.cpp -bolt/lib/Utils/Utils.cpp -bolt/tools/heatmap/heatmap.cpp -bolt/tools/llvm-bolt-fuzzer/llvm-bolt-fuzzer.cpp -bolt/unittests/Core/MCPlusBuilder.cpp -clang/bindings/python/tests/cindex/INPUTS/header1.h -clang/bindings/python/tests/cindex/INPUTS/header2.h -clang/bindings/python/tests/cindex/INPUTS/header3.h -clang/examples/Attribute/Attribute.cpp -clang/examples/CallSuperAttribute/CallSuperAttrInfo.cpp -clang/examples/PluginsOrder/PluginsOrder.cpp -clang/include/clang/Analysis/BodyFarm.h -clang/include/clang/Analysis/IssueHash.h -clang/include/clang/Analysis/MacroExpansionContext.h -clang/include/clang/Analysis/Analyses/CalledOnceCheck.h -clang/include/clang/Analysis/Analyses/CFGReachabilityAnalysis.h -clang/include/clang/Analysis/Analyses/ExprMutationAnalyzer.h -clang/include/clang/Analysis/FlowSensitive/AdornedCFG.h -clang/include/clang/Analysis/FlowSensitive/ASTOps.h -clang/include/clang/Analysis/FlowSensitive/CNFFormula.h -clang/include/clang/Analysis/FlowSensitive/DataflowAnalysis.h -clang/include/clang/Analysis/FlowSensitive/DataflowAnalysisContext.h -clang/include/clang/Analysis/FlowSensitive/DataflowEnvironment.h -clang/include/clang/Analysis/FlowSensitive/DataflowLattice.h -clang/include/clang/Analysis/FlowSensitive/DataflowWorklist.h -clang/include/clang/Analysis/FlowSensitive/DebugSupport.h -clang/include/clang/Analysis/FlowSensitive/MapLattice.h -clang/include/clang/Analysis/FlowSensitive/MatchSwitch.h -clang/include/clang/Analysis/FlowSensitive/NoopAnalysis.h -clang/include/clang/Analysis/FlowSensitive/NoopLattice.h -clang/include/clang/Analysis/FlowSensitive/Solver.h -clang/include/clang/Analysis/FlowSensitive/StorageLocation.h -clang/include/clang/Analysis/FlowSensitive/Transfer.h -clang/include/clang/Analysis/FlowSensitive/TypeErasedDataflowAnalysis.h -clang/include/clang/Analysis/FlowSensitive/Value.h -clang/include/clang/Analysis/FlowSensitive/WatchedLiteralsSolver.h -clang/include/clang/APINotes/APINotesYAMLCompiler.h -clang/include/clang/APINotes/Types.h -clang/include/clang/AST/AST.h -clang/include/clang/AST/ASTContextAllocate.h -clang/include/clang/AST/ASTDumper.h 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-polly/lib/Support/Mainpage.h -polly/lib/Support/RegisterPasses.cpp -polly/lib/Support/SCEVAffinator.cpp -polly/lib/Support/SCEVValidator.cpp -polly/lib/Support/ScopHelper.cpp -polly/lib/Support/ScopLocation.cpp -polly/lib/Support/VirtualInstruction.cpp -polly/lib/Transform/Canonicalization.cpp -polly/lib/Transform/CodePreparation.cpp -polly/lib/Transform/DeadCodeElimination.cpp -polly/lib/Transform/DeLICM.cpp -polly/lib/Transform/FlattenAlgo.cpp -polly/lib/Transform/FlattenSchedule.cpp -polly/lib/Transform/ForwardOpTree.cpp -polly/lib/Transform/ManualOptimizer.cpp -polly/lib/Transform/MatmulOptimizer.cpp -polly/lib/Transform/MaximalStaticExpansion.cpp -polly/lib/Transform/ScheduleOptimizer.cpp -polly/lib/Transform/ScheduleTreeTransform.cpp -polly/lib/Transform/ScopInliner.cpp -polly/lib/Transform/Simplify.cpp -polly/lib/Transform/ZoneAlgo.cpp -polly/tools/GPURuntime/GPUJIT.h -polly/unittests/DeLICM/DeLICMTest.cpp -polly/unittests/Flatten/FlattenTest.cpp -polly/unittests/Isl/IslTest.cpp -polly/unittests/ScheduleOptimizer/ScheduleTreeTransformTest.cpp -polly/unittests/ScopPassManager/PassManagerTest.cpp -polly/unittests/Support/ISLTools.cpp -pstl/include/pstl/internal/algorithm_fwd.h -pstl/include/pstl/internal/execution_defs.h -pstl/include/pstl/internal/execution_impl.h -pstl/include/pstl/internal/glue_algorithm_defs.h -pstl/include/pstl/internal/glue_algorithm_impl.h -pstl/include/pstl/internal/glue_execution_defs.h -pstl/include/pstl/internal/glue_memory_defs.h -pstl/include/pstl/internal/glue_memory_impl.h -pstl/include/pstl/internal/glue_numeric_defs.h -pstl/include/pstl/internal/glue_numeric_impl.h -pstl/include/pstl/internal/numeric_fwd.h -pstl/include/pstl/internal/parallel_backend.h -pstl/include/pstl/internal/parallel_backend_omp.h -pstl/include/pstl/internal/parallel_backend_serial.h -pstl/include/pstl/internal/parallel_backend_utils.h -pstl/include/pstl/internal/parallel_impl.h -pstl/include/pstl/internal/omp/parallel_for.h -pstl/include/pstl/internal/omp/parallel_for_each.h -pstl/include/pstl/internal/omp/parallel_invoke.h -pstl/include/pstl/internal/omp/parallel_reduce.h -pstl/include/pstl/internal/omp/parallel_scan.h -pstl/include/pstl/internal/omp/parallel_stable_partial_sort.h -pstl/include/pstl/internal/omp/parallel_transform_scan.h -pstl/include/pstl/internal/omp/util.h -third-party/benchmark/cmake/thread_safety_attributes.cpp -third-party/benchmark/src/arraysize.h -third-party/benchmark/src/benchmark_api_internal.h -third-party/benchmark/src/benchmark_register.h -third-party/benchmark/src/benchmark_runner.h -third-party/benchmark/src/check.h -third-party/benchmark/src/colorprint.h -third-party/benchmark/src/commandlineflags.h -third-party/benchmark/src/complexity.h -third-party/benchmark/src/counter.h -third-party/benchmark/src/cycleclock.h -third-party/benchmark/src/internal_macros.h -third-party/benchmark/src/log.h -third-party/benchmark/src/mutex.h -third-party/benchmark/src/perf_counters.h -third-party/benchmark/src/re.h -third-party/benchmark/src/sleep.h -third-party/benchmark/src/statistics.h -third-party/benchmark/src/string_util.h -third-party/benchmark/src/thread_manager.h -third-party/benchmark/src/thread_timer.h -third-party/benchmark/src/timers.h -utils/bazel/llvm-project-overlay/clang/include/clang/Config/config.h -utils/bazel/llvm-project-overlay/llvm/include/llvm/Config/config.h diff --git a/clang/include/clang/AST/ASTContext.h b/clang/include/clang/AST/ASTContext.h index a4d36f2eacd5d1..07b4e36f3ef05e 100644 --- a/clang/include/clang/AST/ASTContext.h +++ b/clang/include/clang/AST/ASTContext.h @@ -239,7 +239,7 @@ class ASTContext : public RefCountedBase { mutable llvm::ContextualFoldingSet DependentTemplateSpecializationTypes; - llvm::FoldingSet PackExpansionTypes; + mutable llvm::FoldingSet PackExpansionTypes; mutable llvm::FoldingSet ObjCObjectTypes; mutable llvm::FoldingSet ObjCObjectPointerTypes; mutable llvm::FoldingSet @@ -1778,13 +1778,7 @@ class ASTContext : public RefCountedBase { ElaboratedTypeKeyword Keyword, NestedNameSpecifier *NNS, const IdentifierInfo *Name, ArrayRef Args) const; - TemplateArgument getInjectedTemplateArg(NamedDecl *ParamDecl); - - /// Get a template argument list with one argument per template parameter - /// in a template parameter list, such as for the injected class name of - /// a class template. - void getInjectedTemplateArgs(const TemplateParameterList *Params, - SmallVectorImpl &Args); + TemplateArgument getInjectedTemplateArg(NamedDecl *ParamDecl) const; /// Form a pack expansion type with the given pattern. /// \param NumExpansions The number of expansions for the pack, if known. @@ -1795,7 +1789,7 @@ class ASTContext : public RefCountedBase { /// if this is the canonical type of another pack expansion type. QualType getPackExpansionType(QualType Pattern, std::optional NumExpansions, - bool ExpectPackInType = true); + bool ExpectPackInType = true) const; QualType getObjCInterfaceType(const ObjCInterfaceDecl *Decl, ObjCInterfaceDecl *PrevDecl = nullptr) const; diff --git a/clang/include/clang/AST/DeclTemplate.h b/clang/include/clang/AST/DeclTemplate.h index 0f0c0bf6e4ef4f..a572e3380f1655 100644 --- a/clang/include/clang/AST/DeclTemplate.h +++ b/clang/include/clang/AST/DeclTemplate.h @@ -71,6 +71,9 @@ NamedDecl *getAsNamedDecl(TemplateParameter P); class TemplateParameterList final : private llvm::TrailingObjects { + /// The template argument list of the template parameter list. + TemplateArgument *InjectedArgs = nullptr; + /// The location of the 'template' keyword. SourceLocation TemplateLoc; @@ -196,6 +199,9 @@ class TemplateParameterList final bool hasAssociatedConstraints() const; + /// Get the template argument list of the template parameter list. + ArrayRef getInjectedTemplateArgs(const ASTContext &Context); + SourceLocation getTemplateLoc() const { return TemplateLoc; } SourceLocation getLAngleLoc() const { return LAngleLoc; } SourceLocation getRAngleLoc() const { return RAngleLoc; } @@ -793,15 +799,6 @@ class RedeclarableTemplateDecl : public TemplateDecl, /// The first value in the array is the number of specializations/partial /// specializations that follow. GlobalDeclID *LazySpecializations = nullptr; - - /// The set of "injected" template arguments used within this - /// template. - /// - /// This pointer refers to the template arguments (there are as - /// many template arguments as template parameters) for the - /// template, and is allocated lazily, since most templates do not - /// require the use of this information. - TemplateArgument *InjectedArgs = nullptr; }; /// Pointer to the common data shared by all declarations of this @@ -927,7 +924,10 @@ class RedeclarableTemplateDecl : public TemplateDecl, /// Although the C++ standard has no notion of the "injected" template /// arguments for a template, the notion is convenient when /// we need to perform substitutions inside the definition of a template. - ArrayRef getInjectedTemplateArgs(); + ArrayRef + getInjectedTemplateArgs(const ASTContext &Context) const { + return getTemplateParameters()->getInjectedTemplateArgs(Context); + } using redecl_range = redeclarable_base::redecl_range; using redecl_iterator = redeclarable_base::redecl_iterator; @@ -2087,10 +2087,6 @@ class ClassTemplatePartialSpecializationDecl /// The list of template parameters TemplateParameterList *TemplateParams = nullptr; - /// The set of "injected" template arguments used within this - /// partial specialization. - TemplateArgument *InjectedArgs = nullptr; - /// The class template partial specialization from which this /// class template partial specialization was instantiated. /// @@ -2136,9 +2132,11 @@ class ClassTemplatePartialSpecializationDecl return TemplateParams; } - /// Retrieve the template arguments list of the template parameter list - /// of this template. - ArrayRef getInjectedTemplateArgs(); + /// Get the template argument list of the template parameter list. + ArrayRef + getInjectedTemplateArgs(const ASTContext &Context) const { + return getTemplateParameters()->getInjectedTemplateArgs(Context); + } /// \brief All associated constraints of this partial specialization, /// including the requires clause and any constraints derived from @@ -2864,10 +2862,6 @@ class VarTemplatePartialSpecializationDecl /// The list of template parameters TemplateParameterList *TemplateParams = nullptr; - /// The set of "injected" template arguments used within this - /// partial specialization. - TemplateArgument *InjectedArgs = nullptr; - /// The variable template partial specialization from which this /// variable template partial specialization was instantiated. /// @@ -2914,9 +2908,11 @@ class VarTemplatePartialSpecializationDecl return TemplateParams; } - /// Retrieve the template arguments list of the template parameter list - /// of this template. - ArrayRef getInjectedTemplateArgs(); + /// Get the template argument list of the template parameter list. + ArrayRef + getInjectedTemplateArgs(const ASTContext &Context) const { + return getTemplateParameters()->getInjectedTemplateArgs(Context); + } /// \brief All associated constraints of this partial specialization, /// including the requires clause and any constraints derived from diff --git a/clang/include/clang/Basic/AttrDocs.td b/clang/include/clang/Basic/AttrDocs.td index 7a130c434e73ce..fbbfc4acdf391e 100644 --- a/clang/include/clang/Basic/AttrDocs.td +++ b/clang/include/clang/Basic/AttrDocs.td @@ -3702,20 +3702,32 @@ user-declared functions. For example: .. code-block:: c++ + #include + #include + + using namespace std::literals; + // Returns m[key] if key is present, or default_value if not. template const U &get_or_default(const std::map &m [[clang::lifetimebound]], const T &key, /* note, not lifetimebound */ - const U &default_value [[clang::lifetimebound]]); + const U &default_value [[clang::lifetimebound]]) { + if (auto iter = m.find(key); iter != m.end()) return iter->second; + else return default_value; + } - std::map m; - // warning: temporary "bar"s that might be bound to local reference 'val' - // will be destroyed at the end of the full-expression - const std::string &val = get_or_default(m, "foo"s, "bar"s); + int main() { + std::map m; + // warning: temporary bound to local reference 'val1' will be destroyed + // at the end of the full-expression + const std::string &val1 = get_or_default(m, "foo"s, "bar"s); - // No warning in this case. - std::string def_val = "bar"s; - const std::string &val = get_or_default(m, "foo"s, def_val); + // No warning in this case. + std::string def_val = "bar"s; + const std::string &val2 = get_or_default(m, "foo"s, def_val); + + return 0; + } The attribute can be applied to the implicit ``this`` parameter of a member function by writing the attribute after the function type: diff --git a/clang/include/clang/Basic/BuiltinsBase.td b/clang/include/clang/Basic/BuiltinsBase.td index 58dee22fc0a450..cff182f3f282cb 100644 --- a/clang/include/clang/Basic/BuiltinsBase.td +++ b/clang/include/clang/Basic/BuiltinsBase.td @@ -60,6 +60,10 @@ def ConstIgnoringExceptions : Attribute<"g">; // This function requires a specific header or an explicit declaration. def RequireDeclaration : Attribute<"h">; +// FIXME: Why is this not simply the min_vector_width attribute? +// Vector has to be at least N bits wide. +class RequiredVectorWidth : IndexedAttribute<"V", N>; + class PrintfFormat : IndexedAttribute<"p", I>; class VPrintfFormat : IndexedAttribute<"P", I>; class ScanfFormat : IndexedAttribute<"s", I>; diff --git a/clang/include/clang/Basic/BuiltinsX86.def b/clang/include/clang/Basic/BuiltinsX86.def index 4486eb73a11fa6..c93ea27f164e34 100644 --- a/clang/include/clang/Basic/BuiltinsX86.def +++ b/clang/include/clang/Basic/BuiltinsX86.def @@ -26,17 +26,6 @@ # define TARGET_HEADER_BUILTIN(ID, TYPE, ATTRS, HEADER, LANG, FEATURE) BUILTIN(ID, TYPE, ATTRS) #endif -// Undefined Values -// -TARGET_BUILTIN(__builtin_ia32_undef128, "V2d", "ncV:128:", "") -TARGET_BUILTIN(__builtin_ia32_undef256, "V4d", "ncV:256:", "") -TARGET_BUILTIN(__builtin_ia32_undef512, "V8d", "ncV:512:", "") - -// FLAGS -// -TARGET_BUILTIN(__builtin_ia32_readeflags_u32, "Ui", "n", "") -TARGET_BUILTIN(__builtin_ia32_writeeflags_u32, "vUi", "n", "") - // MMX // // All MMX instructions will be generated via builtins. Any MMX vector @@ -46,113 +35,8 @@ TARGET_BUILTIN(__builtin_ia32_writeeflags_u32, "vUi", "n", "") // argument and our prior approach of using a #define to the current built-in // doesn't work in the presence of re-declaration of _mm_prefetch for windows. TARGET_BUILTIN(_mm_prefetch, "vcC*i", "nc", "mmx") -TARGET_BUILTIN(__builtin_ia32_emms, "v", "n", "mmx") -TARGET_BUILTIN(__builtin_ia32_vec_ext_v4hi, "sV4sIi", "ncV:64:", "sse") -TARGET_BUILTIN(__builtin_ia32_vec_set_v4hi, "V4sV4ssIi", "ncV:64:", "sse") // SSE intrinsics. -TARGET_BUILTIN(__builtin_ia32_comieq, "iV4fV4f", "ncV:128:", "sse") -TARGET_BUILTIN(__builtin_ia32_comilt, "iV4fV4f", "ncV:128:", "sse") -TARGET_BUILTIN(__builtin_ia32_comile, "iV4fV4f", "ncV:128:", "sse") -TARGET_BUILTIN(__builtin_ia32_comigt, "iV4fV4f", "ncV:128:", "sse") -TARGET_BUILTIN(__builtin_ia32_comige, "iV4fV4f", "ncV:128:", "sse") -TARGET_BUILTIN(__builtin_ia32_comineq, "iV4fV4f", "ncV:128:", "sse") -TARGET_BUILTIN(__builtin_ia32_ucomieq, "iV4fV4f", "ncV:128:", "sse") -TARGET_BUILTIN(__builtin_ia32_ucomilt, "iV4fV4f", "ncV:128:", "sse") -TARGET_BUILTIN(__builtin_ia32_ucomile, "iV4fV4f", "ncV:128:", "sse") -TARGET_BUILTIN(__builtin_ia32_ucomigt, "iV4fV4f", "ncV:128:", "sse") -TARGET_BUILTIN(__builtin_ia32_ucomige, "iV4fV4f", "ncV:128:", "sse") -TARGET_BUILTIN(__builtin_ia32_ucomineq, "iV4fV4f", "ncV:128:", "sse") - -TARGET_BUILTIN(__builtin_ia32_comisdeq, "iV2dV2d", "ncV:128:", "sse2") -TARGET_BUILTIN(__builtin_ia32_comisdlt, "iV2dV2d", "ncV:128:", "sse2") -TARGET_BUILTIN(__builtin_ia32_comisdle, "iV2dV2d", "ncV:128:", "sse2") -TARGET_BUILTIN(__builtin_ia32_comisdgt, "iV2dV2d", "ncV:128:", "sse2") -TARGET_BUILTIN(__builtin_ia32_comisdge, "iV2dV2d", "ncV:128:", "sse2") -TARGET_BUILTIN(__builtin_ia32_comisdneq, "iV2dV2d", "ncV:128:", "sse2") -TARGET_BUILTIN(__builtin_ia32_ucomisdeq, "iV2dV2d", "ncV:128:", "sse2") -TARGET_BUILTIN(__builtin_ia32_ucomisdlt, "iV2dV2d", "ncV:128:", "sse2") -TARGET_BUILTIN(__builtin_ia32_ucomisdle, "iV2dV2d", "ncV:128:", "sse2") -TARGET_BUILTIN(__builtin_ia32_ucomisdgt, "iV2dV2d", "ncV:128:", "sse2") -TARGET_BUILTIN(__builtin_ia32_ucomisdge, "iV2dV2d", "ncV:128:", "sse2") -TARGET_BUILTIN(__builtin_ia32_ucomisdneq, "iV2dV2d", "ncV:128:", "sse2") - -TARGET_BUILTIN(__builtin_ia32_cmpeqps, "V4fV4fV4f", "ncV:128:", "sse") -TARGET_BUILTIN(__builtin_ia32_cmpltps, "V4fV4fV4f", "ncV:128:", "sse") -TARGET_BUILTIN(__builtin_ia32_cmpleps, "V4fV4fV4f", "ncV:128:", "sse") -TARGET_BUILTIN(__builtin_ia32_cmpunordps, "V4fV4fV4f", "ncV:128:", "sse") -TARGET_BUILTIN(__builtin_ia32_cmpneqps, "V4fV4fV4f", "ncV:128:", "sse") -TARGET_BUILTIN(__builtin_ia32_cmpnltps, "V4fV4fV4f", "ncV:128:", "sse") -TARGET_BUILTIN(__builtin_ia32_cmpnleps, "V4fV4fV4f", "ncV:128:", "sse") -TARGET_BUILTIN(__builtin_ia32_cmpordps, "V4fV4fV4f", "ncV:128:", "sse") -TARGET_BUILTIN(__builtin_ia32_cmpeqss, "V4fV4fV4f", "ncV:128:", "sse") -TARGET_BUILTIN(__builtin_ia32_cmpltss, "V4fV4fV4f", "ncV:128:", "sse") -TARGET_BUILTIN(__builtin_ia32_cmpless, "V4fV4fV4f", "ncV:128:", "sse") -TARGET_BUILTIN(__builtin_ia32_cmpunordss, "V4fV4fV4f", "ncV:128:", "sse") -TARGET_BUILTIN(__builtin_ia32_cmpneqss, "V4fV4fV4f", "ncV:128:", "sse") -TARGET_BUILTIN(__builtin_ia32_cmpnltss, "V4fV4fV4f", "ncV:128:", "sse") -TARGET_BUILTIN(__builtin_ia32_cmpnless, "V4fV4fV4f", "ncV:128:", "sse") -TARGET_BUILTIN(__builtin_ia32_cmpordss, "V4fV4fV4f", "ncV:128:", "sse") -TARGET_BUILTIN(__builtin_ia32_minps, "V4fV4fV4f", "ncV:128:", "sse") -TARGET_BUILTIN(__builtin_ia32_maxps, "V4fV4fV4f", "ncV:128:", "sse") -TARGET_BUILTIN(__builtin_ia32_minss, "V4fV4fV4f", "ncV:128:", "sse") -TARGET_BUILTIN(__builtin_ia32_maxss, "V4fV4fV4f", "ncV:128:", "sse") -TARGET_BUILTIN(__builtin_ia32_cmpps, "V4fV4fV4fIc", "ncV:128:", "sse") -TARGET_BUILTIN(__builtin_ia32_cmpss, "V4fV4fV4fIc", "ncV:128:", "sse") - -TARGET_BUILTIN(__builtin_ia32_cmpeqpd, "V2dV2dV2d", "ncV:128:", "sse2") -TARGET_BUILTIN(__builtin_ia32_cmpltpd, "V2dV2dV2d", "ncV:128:", "sse2") -TARGET_BUILTIN(__builtin_ia32_cmplepd, "V2dV2dV2d", "ncV:128:", "sse2") -TARGET_BUILTIN(__builtin_ia32_cmpunordpd, "V2dV2dV2d", "ncV:128:", "sse2") -TARGET_BUILTIN(__builtin_ia32_cmpneqpd, "V2dV2dV2d", "ncV:128:", "sse2") -TARGET_BUILTIN(__builtin_ia32_cmpnltpd, "V2dV2dV2d", "ncV:128:", "sse2") -TARGET_BUILTIN(__builtin_ia32_cmpnlepd, "V2dV2dV2d", "ncV:128:", "sse2") -TARGET_BUILTIN(__builtin_ia32_cmpordpd, "V2dV2dV2d", "ncV:128:", "sse2") -TARGET_BUILTIN(__builtin_ia32_cmpeqsd, "V2dV2dV2d", "ncV:128:", "sse2") -TARGET_BUILTIN(__builtin_ia32_cmpltsd, "V2dV2dV2d", "ncV:128:", "sse2") -TARGET_BUILTIN(__builtin_ia32_cmplesd, "V2dV2dV2d", "ncV:128:", "sse2") -TARGET_BUILTIN(__builtin_ia32_cmpunordsd, "V2dV2dV2d", "ncV:128:", "sse2") -TARGET_BUILTIN(__builtin_ia32_cmpneqsd, "V2dV2dV2d", "ncV:128:", "sse2") -TARGET_BUILTIN(__builtin_ia32_cmpnltsd, "V2dV2dV2d", "ncV:128:", "sse2") -TARGET_BUILTIN(__builtin_ia32_cmpnlesd, "V2dV2dV2d", "ncV:128:", "sse2") -TARGET_BUILTIN(__builtin_ia32_cmpordsd, "V2dV2dV2d", "ncV:128:", "sse2") -TARGET_BUILTIN(__builtin_ia32_cmpsd, "V2dV2dV2dIc", "ncV:128:", "sse2") -TARGET_BUILTIN(__builtin_ia32_cmppd, "V2dV2dV2dIc", "ncV:128:", "sse2") -TARGET_BUILTIN(__builtin_ia32_minpd, "V2dV2dV2d", "ncV:128:", "sse2") -TARGET_BUILTIN(__builtin_ia32_maxpd, "V2dV2dV2d", "ncV:128:", "sse2") -TARGET_BUILTIN(__builtin_ia32_minsd, "V2dV2dV2d", "ncV:128:", "sse2") -TARGET_BUILTIN(__builtin_ia32_maxsd, "V2dV2dV2d", "ncV:128:", "sse2") -TARGET_BUILTIN(__builtin_ia32_pmulhw128, "V8sV8sV8s", "ncV:128:", "sse2") -TARGET_BUILTIN(__builtin_ia32_pavgb128, "V16cV16cV16c", "ncV:128:", "sse2") -TARGET_BUILTIN(__builtin_ia32_pavgw128, "V8sV8sV8s", "ncV:128:", "sse2") -TARGET_BUILTIN(__builtin_ia32_packsswb128, "V16cV8sV8s", "ncV:128:", "sse2") -TARGET_BUILTIN(__builtin_ia32_packssdw128, "V8sV4iV4i", "ncV:128:", "sse2") -TARGET_BUILTIN(__builtin_ia32_packuswb128, "V16cV8sV8s", "ncV:128:", "sse2") -TARGET_BUILTIN(__builtin_ia32_pmulhuw128, "V8sV8sV8s", "ncV:128:", "sse2") -TARGET_BUILTIN(__builtin_ia32_vec_ext_v2di, "OiV2OiIi", "ncV:128:", "sse2") -TARGET_BUILTIN(__builtin_ia32_vec_ext_v4si, "iV4iIi", "ncV:128:", "sse2") -TARGET_BUILTIN(__builtin_ia32_vec_ext_v4sf, "fV4fIi", "ncV:128:", "sse2") -TARGET_BUILTIN(__builtin_ia32_vec_ext_v8hi, "sV8sIi", "ncV:128:", "sse2") -TARGET_BUILTIN(__builtin_ia32_vec_set_v8hi, "V8sV8ssIi", "ncV:128:", "sse2") - -TARGET_BUILTIN(__builtin_ia32_addsubps, "V4fV4fV4f", "ncV:128:", "sse3") -TARGET_BUILTIN(__builtin_ia32_addsubpd, "V2dV2dV2d", "ncV:128:", "sse3") -TARGET_BUILTIN(__builtin_ia32_haddps, "V4fV4fV4f", "ncV:128:", "sse3") -TARGET_BUILTIN(__builtin_ia32_haddpd, "V2dV2dV2d", "ncV:128:", "sse3") -TARGET_BUILTIN(__builtin_ia32_hsubps, "V4fV4fV4f", "ncV:128:", "sse3") -TARGET_BUILTIN(__builtin_ia32_hsubpd, "V2dV2dV2d", "ncV:128:", "sse3") -TARGET_BUILTIN(__builtin_ia32_phaddw128, "V8sV8sV8s", "ncV:128:", "ssse3") -TARGET_BUILTIN(__builtin_ia32_phaddd128, "V4iV4iV4i", "ncV:128:", "ssse3") -TARGET_BUILTIN(__builtin_ia32_phaddsw128, "V8sV8sV8s", "ncV:128:", "ssse3") -TARGET_BUILTIN(__builtin_ia32_phsubw128, "V8sV8sV8s", "ncV:128:", "ssse3") -TARGET_BUILTIN(__builtin_ia32_phsubd128, "V4iV4iV4i", "ncV:128:", "ssse3") -TARGET_BUILTIN(__builtin_ia32_phsubsw128, "V8sV8sV8s", "ncV:128:", "ssse3") -TARGET_BUILTIN(__builtin_ia32_pmaddubsw128, "V8sV16cV16c", "ncV:128:", "ssse3") -TARGET_BUILTIN(__builtin_ia32_pmulhrsw128, "V8sV8sV8s", "ncV:128:", "ssse3") -TARGET_BUILTIN(__builtin_ia32_pshufb128, "V16cV16cV16c", "ncV:128:", "ssse3") -TARGET_BUILTIN(__builtin_ia32_psignb128, "V16cV16cV16c", "ncV:128:", "ssse3") -TARGET_BUILTIN(__builtin_ia32_psignw128, "V8sV8sV8s", "ncV:128:", "ssse3") -TARGET_BUILTIN(__builtin_ia32_psignd128, "V4iV4iV4i", "ncV:128:", "ssse3") TARGET_BUILTIN(__builtin_ia32_ldmxcsr, "vUi", "n", "sse") TARGET_HEADER_BUILTIN(_mm_setcsr, "vUi", "nh",XMMINTRIN_H, ALL_LANGUAGES, "sse") @@ -316,16 +200,6 @@ TARGET_BUILTIN(__builtin_ia32_pclmulqdq256, "V4OiV4OiV4OiIc", "ncV:256:", "vpclm TARGET_BUILTIN(__builtin_ia32_pclmulqdq512, "V8OiV8OiV8OiIc", "ncV:512:", "avx512f,evex512,vpclmulqdq") // AVX -TARGET_BUILTIN(__builtin_ia32_addsubpd256, "V4dV4dV4d", "ncV:256:", "avx") -TARGET_BUILTIN(__builtin_ia32_addsubps256, "V8fV8fV8f", "ncV:256:", "avx") -TARGET_BUILTIN(__builtin_ia32_haddpd256, "V4dV4dV4d", "ncV:256:", "avx") -TARGET_BUILTIN(__builtin_ia32_hsubps256, "V8fV8fV8f", "ncV:256:", "avx") -TARGET_BUILTIN(__builtin_ia32_hsubpd256, "V4dV4dV4d", "ncV:256:", "avx") -TARGET_BUILTIN(__builtin_ia32_haddps256, "V8fV8fV8f", "ncV:256:", "avx") -TARGET_BUILTIN(__builtin_ia32_maxpd256, "V4dV4dV4d", "ncV:256:", "avx") -TARGET_BUILTIN(__builtin_ia32_maxps256, "V8fV8fV8f", "ncV:256:", "avx") -TARGET_BUILTIN(__builtin_ia32_minpd256, "V4dV4dV4d", "ncV:256:", "avx") -TARGET_BUILTIN(__builtin_ia32_minps256, "V8fV8fV8f", "ncV:256:", "avx") TARGET_BUILTIN(__builtin_ia32_vpermilvarpd, "V2dV2dV2Oi", "ncV:256:", "avx") TARGET_BUILTIN(__builtin_ia32_vpermilvarps, "V4fV4fV4i", "ncV:256:", "avx") TARGET_BUILTIN(__builtin_ia32_vpermilvarpd256, "V4dV4dV4Oi", "ncV:256:", "avx") diff --git a/clang/include/clang/Basic/BuiltinsX86.td b/clang/include/clang/Basic/BuiltinsX86.td new file mode 100644 index 00000000000000..cf8d2771310e3c --- /dev/null +++ b/clang/include/clang/Basic/BuiltinsX86.td @@ -0,0 +1,137 @@ +//===--- BuiltinsX86.td - X86 Builtin function database ---------*- C++ -*-===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// +// +// This file defines the X86-specific builtin function database. +// +//===----------------------------------------------------------------------===// + +include "clang/Basic/BuiltinsBase.td" + +class X86Builtin : TargetBuiltin { + let Spellings = ["__builtin_ia32_" # NAME]; + let Prototype = prototype; +} + +// Undefined Values +def undef128 : X86Builtin<"_Vector<2, double>()"> { + let Attributes = [Const, NoThrow, RequiredVectorWidth<128>]; +} + +def undef256 : X86Builtin<"_Vector<4, double>()"> { + let Attributes = [Const, NoThrow, RequiredVectorWidth<256>]; +} + +def undef512 : X86Builtin<"_Vector<8, double>()"> { + let Attributes = [Const, NoThrow, RequiredVectorWidth<512>]; +} + +// FLAGS +def readeflags_u32 : X86Builtin<"unsigned int()"> { + let Attributes = [NoThrow]; +} + +def writeeflags_u32 : X86Builtin<"void(unsigned int)"> { + let Attributes = [NoThrow]; +} + +// MMX +// +// All MMX instructions will be generated via builtins. Any MMX vector +// types (<1 x i64>, <2 x i32>, etc.) that aren't used by these builtins will be +// expanded by the back-end. + +def emms : X86Builtin<"void()"> { + let Attributes = [NoThrow]; + let Features = "mmx"; +} + +let Attributes = [NoThrow, Const, RequiredVectorWidth<64>], Features = "sse" in { + def vec_ext_v4hi : X86Builtin<"short(_Vector<4, short>, _Constant int)">; + def vec_set_v4hi : X86Builtin<"_Vector<4, short>(_Vector<4, short>, short, _Constant int)">; +} + +// SSE intrinsics +let Attributes = [Const, NoThrow, RequiredVectorWidth<128>] in { + foreach Cmp = ["eq", "lt", "le", "gt", "ge", "neq"] in { + let Features = "sse" in { + def comi#Cmp : X86Builtin<"int(_Vector<4, float>, _Vector<4, float>)">; + def ucomi#Cmp : X86Builtin<"int(_Vector<4, float>, _Vector<4, float>)">; + } + let Features = "sse2" in { + def comisd#Cmp : X86Builtin<"int(_Vector<2, double>, _Vector<2, double>)">; + def ucomisd#Cmp : X86Builtin<"int(_Vector<2, double>, _Vector<2, double>)">; + } + } + + foreach Cmp = ["cmpeq", "cmplt", "cmple", "cmpunord", "cmpneq", "cmpnlt", + "cmpnle", "cmpord", "min", "max"] in { + let Features = "sse" in { + def Cmp#ps : X86Builtin<"_Vector<4, float>(_Vector<4, float>, _Vector<4, float>)">; + def Cmp#ss : X86Builtin<"_Vector<4, float>(_Vector<4, float>, _Vector<4, float>)">; + } + let Features = "sse2" in { + def Cmp#pd : X86Builtin<"_Vector<2, double>(_Vector<2, double>, _Vector<2, double>)">; + def Cmp#sd : X86Builtin<"_Vector<2, double>(_Vector<2, double>, _Vector<2, double>)">; + } + } + + let Features = "sse" in { + def cmpps : X86Builtin<"_Vector<4, float>(_Vector<4, float>, _Vector<4, float>, _Constant char)">; + def cmpss : X86Builtin<"_Vector<4, float>(_Vector<4, float>, _Vector<4, float>, _Constant char)">; + } + + let Features = "sse2" in { + def cmppd : X86Builtin<"_Vector<2, double>(_Vector<2, double>, _Vector<2, double>, _Constant char)">; + def cmpsd : X86Builtin<"_Vector<2, double>(_Vector<2, double>, _Vector<2, double>, _Constant char)">; + } + + let Features = "sse2" in { + def pmulhw128 : X86Builtin<"_Vector<8, short>(_Vector<8, short>, _Vector<8, short>)">; + def pavgb128 : X86Builtin<"_Vector<16, char>(_Vector<16, char>, _Vector<16, char>)">; + def pavgw128 : X86Builtin<"_Vector<8, short>(_Vector<8, short>, _Vector<8, short>)">; + def packsswb128 : X86Builtin<"_Vector<16, char>(_Vector<8, short>, _Vector<8, short>)">; + def packssdw128 : X86Builtin<"_Vector<8, short>(_Vector<4, int>, _Vector<4, int>)">; + def packuswb128 : X86Builtin<"_Vector<16, char>(_Vector<8, short>, _Vector<8, short>)">; + def pmulhuw128 : X86Builtin<"_Vector<8, short>(_Vector<8, short>, _Vector<8, short>)">; + def vec_ext_v2di : X86Builtin<"long long int(_Vector<2, long long int>, _Constant int)">; + def vec_ext_v4si : X86Builtin<"int(_Vector<4, int>, _Constant int)">; + def vec_ext_v4sf : X86Builtin<"float(_Vector<4, float>, _Constant int)">; + def vec_ext_v8hi : X86Builtin<"short(_Vector<8, short>, _Constant int)">; + def vec_set_v8hi : X86Builtin<"_Vector<8, short>(_Vector<8, short>, short, _Constant int)">; + } + + let Features = "sse3" in { + foreach Op = ["addsub", "hadd", "hsub"] in { + def Op#ps : X86Builtin<"_Vector<4, float>(_Vector<4, float>, _Vector<4, float>)">; + def Op#pd : X86Builtin<"_Vector<2, double>(_Vector<2, double>, _Vector<2, double>)">; + } + } + + let Features = "ssse3" in { + foreach Op = ["phadd", "phsub"] in { + def Op#w128 : X86Builtin<"_Vector<8, short>(_Vector<8, short>, _Vector<8, short>)">; + def Op#sw128 : X86Builtin<"_Vector<8, short>(_Vector<8, short>, _Vector<8, short>)">; + def Op#d128 : X86Builtin<"_Vector<4, int>(_Vector<4, int>, _Vector<4, int>)">; + } + + def pmaddubsw128 : X86Builtin<"_Vector<8, short>(_Vector<16, char>, _Vector<16, char>)">; + def pmulhrsw128 : X86Builtin<"_Vector<8, short>(_Vector<8, short>, _Vector<8, short>)">; + def pshufb128 : X86Builtin<"_Vector<16, char>(_Vector<16, char>, _Vector<16, char>)">; + def psignb128 : X86Builtin<"_Vector<16, char>(_Vector<16, char>, _Vector<16, char>)">; + def psignw128 : X86Builtin<"_Vector<8, short>(_Vector<8, short>, _Vector<8, short>)">; + def psignd128 : X86Builtin<"_Vector<4, int>(_Vector<4, int>, _Vector<4, int>)">; + } +} + +// AVX +let Attributes = [Const, NoThrow, RequiredVectorWidth<256>], Features = "avx" in { + foreach Op = ["addsub", "hadd", "hsub", "max", "min"] in { + def Op#pd256 : X86Builtin<"_Vector<4, double>(_Vector<4, double>, _Vector<4, double>)">; + def Op#ps256 : X86Builtin<"_Vector<8, float>(_Vector<8, float>, _Vector<8, float>)">; + } +} diff --git a/clang/include/clang/Basic/CMakeLists.txt b/clang/include/clang/Basic/CMakeLists.txt index f069f4fc118f27..76ac3367e23a66 100644 --- a/clang/include/clang/Basic/CMakeLists.txt +++ b/clang/include/clang/Basic/CMakeLists.txt @@ -60,6 +60,10 @@ clang_tablegen(BuiltinsRISCV.inc -gen-clang-builtins SOURCE BuiltinsRISCV.td TARGET ClangBuiltinsRISCV) +clang_tablegen(BuiltinsX86.inc -gen-clang-builtins + SOURCE BuiltinsX86.td + TARGET ClangBuiltinsX86) + # ARM NEON and MVE clang_tablegen(arm_neon.inc -gen-arm-neon-sema SOURCE arm_neon.td diff --git a/clang/include/clang/Basic/TargetBuiltins.h b/clang/include/clang/Basic/TargetBuiltins.h index d0f41b17c154f3..89ebf5758a5b55 100644 --- a/clang/include/clang/Basic/TargetBuiltins.h +++ b/clang/include/clang/Basic/TargetBuiltins.h @@ -125,6 +125,8 @@ namespace clang { LastTIBuiltin = clang::Builtin::FirstTSBuiltin - 1, #define BUILTIN(ID, TYPE, ATTRS) BI##ID, #include "clang/Basic/BuiltinsX86.def" +#define BUILTIN(ID, TYPE, ATTRS) BI##ID, +#include "clang/Basic/BuiltinsX86.inc" FirstX86_64Builtin, LastX86CommonBuiltin = FirstX86_64Builtin - 1, #define BUILTIN(ID, TYPE, ATTRS) BI##ID, diff --git a/clang/include/clang/Driver/Options.td b/clang/include/clang/Driver/Options.td index 1ddf488b8bf4c7..9d595984b63c4b 100644 --- a/clang/include/clang/Driver/Options.td +++ b/clang/include/clang/Driver/Options.td @@ -4678,7 +4678,8 @@ def malign_loops_EQ : Joined<["-"], "malign-loops=">, Group; def malign_branch_boundary_EQ : Joined<["-"], "malign-branch-boundary=">, Group, @@ -7363,6 +7364,7 @@ def mabi_EQ_ieeelongdouble : Flag<["-"], "mabi=ieeelongdouble">, HelpText<"Use IEEE 754 quadruple-precision for long double">, MarshallingInfoFlag>; def mabi_EQ_vec_extabi : Flag<["-"], "mabi=vec-extabi">, + Visibility<[ClangOption, CC1Option, FlangOption, FC1Option]>, HelpText<"Enable the extended Altivec ABI on AIX. Use volatile and nonvolatile vector registers">, MarshallingInfoFlag>; def mfloat_abi : Separate<["-"], "mfloat-abi">, diff --git a/clang/include/clang/Index/USRGeneration.h b/clang/include/clang/Index/USRGeneration.h index f89fc5cf49302c..61d267f3545a70 100644 --- a/clang/include/clang/Index/USRGeneration.h +++ b/clang/include/clang/Index/USRGeneration.h @@ -15,6 +15,7 @@ namespace clang { class ASTContext; class Decl; +class LangOptions; class MacroDefinitionRecord; class Module; class SourceLocation; @@ -30,6 +31,8 @@ static inline StringRef getUSRSpacePrefix() { /// Generate a USR for a Decl, including the USR prefix. /// \returns true if the results should be ignored, false otherwise. bool generateUSRForDecl(const Decl *D, SmallVectorImpl &Buf); +bool generateUSRForDecl(const Decl *D, SmallVectorImpl &Buf, + const LangOptions &LangOpts); /// Generate a USR fragment for an Objective-C class. void generateUSRForObjCClass(StringRef Cls, raw_ostream &OS, @@ -75,7 +78,10 @@ bool generateUSRForMacro(StringRef MacroName, SourceLocation Loc, /// Generates a USR for a type. /// /// \return true on error, false on success. -bool generateUSRForType(QualType T, ASTContext &Ctx, SmallVectorImpl &Buf); +bool generateUSRForType(QualType T, ASTContext &Ctx, + SmallVectorImpl &Buf); +bool generateUSRForType(QualType T, ASTContext &Ctx, SmallVectorImpl &Buf, + const LangOptions &LangOpts); /// Generate a USR for a module, including the USR prefix. /// \returns true on error, false on success. diff --git a/clang/lib/AST/ASTContext.cpp b/clang/lib/AST/ASTContext.cpp index 69892bda42b256..1c3f771f417ccf 100644 --- a/clang/lib/AST/ASTContext.cpp +++ b/clang/lib/AST/ASTContext.cpp @@ -5634,7 +5634,7 @@ ASTContext::getDependentTemplateSpecializationType( return QualType(T, 0); } -TemplateArgument ASTContext::getInjectedTemplateArg(NamedDecl *Param) { +TemplateArgument ASTContext::getInjectedTemplateArg(NamedDecl *Param) const { TemplateArgument Arg; if (const auto *TTP = dyn_cast(Param)) { QualType ArgType = getTypeDeclType(TTP); @@ -5678,23 +5678,15 @@ TemplateArgument ASTContext::getInjectedTemplateArg(NamedDecl *Param) { } if (Param->isTemplateParameterPack()) - Arg = TemplateArgument::CreatePackCopy(*this, Arg); + Arg = + TemplateArgument::CreatePackCopy(const_cast(*this), Arg); return Arg; } -void -ASTContext::getInjectedTemplateArgs(const TemplateParameterList *Params, - SmallVectorImpl &Args) { - Args.reserve(Args.size() + Params->size()); - - for (NamedDecl *Param : *Params) - Args.push_back(getInjectedTemplateArg(Param)); -} - QualType ASTContext::getPackExpansionType(QualType Pattern, std::optional NumExpansions, - bool ExpectPackInType) { + bool ExpectPackInType) const { assert((!ExpectPackInType || Pattern->containsUnexpandedParameterPack()) && "Pack expansions must expand one or more parameter packs"); diff --git a/clang/lib/AST/ByteCode/Interp.cpp b/clang/lib/AST/ByteCode/Interp.cpp index 6e45cfb7e8a20c..513d4512b45cff 100644 --- a/clang/lib/AST/ByteCode/Interp.cpp +++ b/clang/lib/AST/ByteCode/Interp.cpp @@ -1451,6 +1451,11 @@ bool CheckNewTypeMismatch(InterpState &S, CodePtr OpPC, const Expr *E, << StorageType << AllocType; return false; } + + // Can't activate fields in a union, unless the direct base is the union. + if (Ptr.inUnion() && !Ptr.isActive() && !Ptr.getBase().getRecord()->isUnion()) + return CheckActive(S, OpPC, Ptr, AK_Construct); + return true; } diff --git a/clang/lib/AST/ByteCode/Pointer.h b/clang/lib/AST/ByteCode/Pointer.h index 72e255dba13f6b..457fe93b278175 100644 --- a/clang/lib/AST/ByteCode/Pointer.h +++ b/clang/lib/AST/ByteCode/Pointer.h @@ -653,15 +653,6 @@ class Pointer { return *reinterpret_cast(asBlockPointer().Pointee->rawData() + Offset); } - /// Dereferences a primitive element. - template T &elem(unsigned I) const { - assert(I < getNumElems()); - assert(isBlockPointer()); - assert(asBlockPointer().Pointee); - return reinterpret_cast(asBlockPointer().Pointee->data() + - sizeof(InitMapPtr))[I]; - } - /// Whether this block can be read from at all. This is only true for /// block pointers that point to a valid location inside that block. bool isDereferencable() const { diff --git a/clang/lib/AST/DeclTemplate.cpp b/clang/lib/AST/DeclTemplate.cpp index 4a506b7be45642..755ec72f00bf77 100644 --- a/clang/lib/AST/DeclTemplate.cpp +++ b/clang/lib/AST/DeclTemplate.cpp @@ -51,7 +51,7 @@ DefaultTemplateArgumentContainsUnexpandedPack(const TemplateParam &P) { P.getDefaultArgument().getArgument().containsUnexpandedParameterPack(); } -TemplateParameterList::TemplateParameterList(const ASTContext& C, +TemplateParameterList::TemplateParameterList(const ASTContext &C, SourceLocation TemplateLoc, SourceLocation LAngleLoc, ArrayRef Params, @@ -244,6 +244,17 @@ bool TemplateParameterList::hasAssociatedConstraints() const { return HasRequiresClause || HasConstrainedParameters; } +ArrayRef +TemplateParameterList::getInjectedTemplateArgs(const ASTContext &Context) { + if (!InjectedArgs) { + InjectedArgs = new (Context) TemplateArgument[size()]; + llvm::transform(*this, InjectedArgs, [&](NamedDecl *ND) { + return Context.getInjectedTemplateArg(ND); + }); + } + return {InjectedArgs, NumParams}; +} + bool TemplateParameterList::shouldIncludeTypeForArgument( const PrintingPolicy &Policy, const TemplateParameterList *TPL, unsigned Idx) { @@ -396,22 +407,6 @@ void RedeclarableTemplateDecl::addSpecializationImpl( SETraits::getDecl(Entry)); } -ArrayRef RedeclarableTemplateDecl::getInjectedTemplateArgs() { - TemplateParameterList *Params = getTemplateParameters(); - auto *CommonPtr = getCommonPtr(); - if (!CommonPtr->InjectedArgs) { - auto &Context = getASTContext(); - SmallVector TemplateArgs; - Context.getInjectedTemplateArgs(Params, TemplateArgs); - CommonPtr->InjectedArgs = - new (Context) TemplateArgument[TemplateArgs.size()]; - std::copy(TemplateArgs.begin(), TemplateArgs.end(), - CommonPtr->InjectedArgs); - } - - return llvm::ArrayRef(CommonPtr->InjectedArgs, Params->size()); -} - //===----------------------------------------------------------------------===// // FunctionTemplateDecl Implementation //===----------------------------------------------------------------------===// @@ -631,13 +626,10 @@ ClassTemplateDecl::getInjectedClassNameSpecialization() { // expansion (14.5.3) whose pattern is the name of the template parameter // pack. ASTContext &Context = getASTContext(); - TemplateParameterList *Params = getTemplateParameters(); - SmallVector TemplateArgs; - Context.getInjectedTemplateArgs(Params, TemplateArgs); TemplateName Name = Context.getQualifiedTemplateName( /*NNS=*/nullptr, /*TemplateKeyword=*/false, TemplateName(this)); - CommonPtr->InjectedClassNameType = - Context.getTemplateSpecializationType(Name, TemplateArgs); + CommonPtr->InjectedClassNameType = Context.getTemplateSpecializationType( + Name, getTemplateParameters()->getInjectedTemplateArgs(Context)); return CommonPtr->InjectedClassNameType; } @@ -1184,20 +1176,6 @@ SourceRange ClassTemplatePartialSpecializationDecl::getSourceRange() const { return Range; } -ArrayRef -ClassTemplatePartialSpecializationDecl::getInjectedTemplateArgs() { - TemplateParameterList *Params = getTemplateParameters(); - auto *First = cast(getFirstDecl()); - if (!First->InjectedArgs) { - auto &Context = getASTContext(); - SmallVector TemplateArgs; - Context.getInjectedTemplateArgs(Params, TemplateArgs); - First->InjectedArgs = new (Context) TemplateArgument[TemplateArgs.size()]; - std::copy(TemplateArgs.begin(), TemplateArgs.end(), First->InjectedArgs); - } - return llvm::ArrayRef(First->InjectedArgs, Params->size()); -} - //===----------------------------------------------------------------------===// // FriendTemplateDecl Implementation //===----------------------------------------------------------------------===// @@ -1548,20 +1526,6 @@ SourceRange VarTemplatePartialSpecializationDecl::getSourceRange() const { return Range; } -ArrayRef -VarTemplatePartialSpecializationDecl::getInjectedTemplateArgs() { - TemplateParameterList *Params = getTemplateParameters(); - auto *First = cast(getFirstDecl()); - if (!First->InjectedArgs) { - auto &Context = getASTContext(); - SmallVector TemplateArgs; - Context.getInjectedTemplateArgs(Params, TemplateArgs); - First->InjectedArgs = new (Context) TemplateArgument[TemplateArgs.size()]; - std::copy(TemplateArgs.begin(), TemplateArgs.end(), First->InjectedArgs); - } - return llvm::ArrayRef(First->InjectedArgs, Params->size()); -} - static TemplateParameterList * createMakeIntegerSeqParameterList(const ASTContext &C, DeclContext *DC) { // typename T diff --git a/clang/lib/Basic/Targets/AArch64.cpp b/clang/lib/Basic/Targets/AArch64.cpp index a0f94d5d315480..3d8de0294d4ba3 100644 --- a/clang/lib/Basic/Targets/AArch64.cpp +++ b/clang/lib/Basic/Targets/AArch64.cpp @@ -765,8 +765,6 @@ bool AArch64TargetInfo::hasFeature(StringRef Feature) const { .Case("i8mm", HasMatMul) .Case("bf16", HasBFloat16) .Case("sve", FPU & SveMode) - .Case("sve-bf16", FPU & SveMode && HasBFloat16) - .Case("sve-i8mm", FPU & SveMode && HasMatMul) .Case("sve-b16b16", HasSVEB16B16) .Case("f32mm", FPU & SveMode && HasMatmulFP32) .Case("f64mm", FPU & SveMode && HasMatmulFP64) diff --git a/clang/lib/Basic/Targets/X86.cpp b/clang/lib/Basic/Targets/X86.cpp index 700c2f9a5dbd18..82d29ea9fea5c4 100644 --- a/clang/lib/Basic/Targets/X86.cpp +++ b/clang/lib/Basic/Targets/X86.cpp @@ -32,6 +32,14 @@ static constexpr Builtin::Info BuiltinInfoX86[] = { {#ID, TYPE, ATTRS, FEATURE, HeaderDesc::HEADER, LANGS}, #include "clang/Basic/BuiltinsX86.def" +#define BUILTIN(ID, TYPE, ATTRS) \ + {#ID, TYPE, ATTRS, nullptr, HeaderDesc::NO_HEADER, ALL_LANGUAGES}, +#define TARGET_BUILTIN(ID, TYPE, ATTRS, FEATURE) \ + {#ID, TYPE, ATTRS, FEATURE, HeaderDesc::NO_HEADER, ALL_LANGUAGES}, +#define TARGET_HEADER_BUILTIN(ID, TYPE, ATTRS, HEADER, LANGS, FEATURE) \ + {#ID, TYPE, ATTRS, FEATURE, HeaderDesc::HEADER, LANGS}, +#include "clang/Basic/BuiltinsX86.inc" + #define BUILTIN(ID, TYPE, ATTRS) \ {#ID, TYPE, ATTRS, nullptr, HeaderDesc::NO_HEADER, ALL_LANGUAGES}, #define TARGET_BUILTIN(ID, TYPE, ATTRS, FEATURE) \ diff --git a/clang/lib/CodeGen/CodeGenModule.cpp b/clang/lib/CodeGen/CodeGenModule.cpp index 2bcca5e85bdfeb..ba376f9ecfacde 100644 --- a/clang/lib/CodeGen/CodeGenModule.cpp +++ b/clang/lib/CodeGen/CodeGenModule.cpp @@ -7146,8 +7146,8 @@ void CodeGenModule::EmitTopLevelDecl(Decl *D) { // For C++ standard modules we are done - we will call the module // initializer for imported modules, and that will likewise call those for // any imports it has. - if (CXX20ModuleInits && Import->getImportedOwningModule() && - !Import->getImportedOwningModule()->isModuleMapModule()) + if (CXX20ModuleInits && Import->getImportedModule() && + Import->getImportedModule()->isNamedModule()) break; // For clang C++ module map modules the initializers for sub-modules are diff --git a/clang/lib/Driver/ToolChains/Flang.cpp b/clang/lib/Driver/ToolChains/Flang.cpp index a9d2b7a4dc48f9..f9d2fdffe3b2fc 100644 --- a/clang/lib/Driver/ToolChains/Flang.cpp +++ b/clang/lib/Driver/ToolChains/Flang.cpp @@ -203,6 +203,32 @@ void Flang::AddAArch64TargetArgs(const ArgList &Args, } } +void Flang::AddPPCTargetArgs(const ArgList &Args, + ArgStringList &CmdArgs) const { + const Driver &D = getToolChain().getDriver(); + bool VecExtabi = false; + + if (const Arg *A = Args.getLastArg(options::OPT_mabi_EQ)) { + StringRef V = A->getValue(); + if (V == "vec-extabi") + VecExtabi = true; + else if (V == "vec-default") + VecExtabi = false; + else + D.Diag(diag::err_drv_unsupported_option_argument) + << A->getSpelling() << V; + } + + const llvm::Triple &T = getToolChain().getTriple(); + if (VecExtabi) { + if (!T.isOSAIX()) { + D.Diag(diag::err_drv_unsupported_opt_for_target) + << "-mabi=vec-extabi" << T.str(); + } + CmdArgs.push_back("-mabi=vec-extabi"); + } +} + void Flang::AddRISCVTargetArgs(const ArgList &Args, ArgStringList &CmdArgs) const { const llvm::Triple &Triple = getToolChain().getTriple(); @@ -383,6 +409,11 @@ void Flang::addTargetOptions(const ArgList &Args, getTargetFeatures(D, Triple, Args, CmdArgs, /*ForAs*/ false); AddX86_64TargetArgs(Args, CmdArgs); break; + case llvm::Triple::ppc: + case llvm::Triple::ppc64: + case llvm::Triple::ppc64le: + AddPPCTargetArgs(Args, CmdArgs); + break; } if (Arg *A = Args.getLastArg(options::OPT_fveclib)) { diff --git a/clang/lib/Driver/ToolChains/Flang.h b/clang/lib/Driver/ToolChains/Flang.h index 9f5e26b8608324..4d7d0b8cd9ea55 100644 --- a/clang/lib/Driver/ToolChains/Flang.h +++ b/clang/lib/Driver/ToolChains/Flang.h @@ -84,6 +84,13 @@ class LLVM_LIBRARY_VISIBILITY Flang : public Tool { void AddX86_64TargetArgs(const llvm::opt::ArgList &Args, llvm::opt::ArgStringList &CmdArgs) const; + /// Add specific options for PPC target. + /// + /// \param [in] Args The list of input driver arguments + /// \param [out] CmdArgs The list of output command arguments + void AddPPCTargetArgs(const llvm::opt::ArgList &Args, + llvm::opt::ArgStringList &CmdArgs) const; + /// Extract offload options from the driver arguments and add them to /// the command arguments. /// \param [in] C The current compilation for the driver invocation diff --git a/clang/lib/Driver/ToolChains/PS4CPU.cpp b/clang/lib/Driver/ToolChains/PS4CPU.cpp index 719bba41436a57..9daafbe703f68e 100644 --- a/clang/lib/Driver/ToolChains/PS4CPU.cpp +++ b/clang/lib/Driver/ToolChains/PS4CPU.cpp @@ -430,8 +430,7 @@ toolchains::PS4PS5Base::PS4PS5Base(const Driver &D, const llvm::Triple &Triple, } void toolchains::PS4PS5Base::AddClangSystemIncludeArgs( - const ArgList &DriverArgs, - ArgStringList &CC1Args) const { + const ArgList &DriverArgs, ArgStringList &CC1Args) const { const Driver &D = getDriver(); if (DriverArgs.hasArg(options::OPT_nostdinc)) diff --git a/clang/lib/Headers/emmintrin.h b/clang/lib/Headers/emmintrin.h index d6494762169b25..4f00b7f1a8d9d4 100644 --- a/clang/lib/Headers/emmintrin.h +++ b/clang/lib/Headers/emmintrin.h @@ -2110,8 +2110,8 @@ static __inline__ __m128i __DEFAULT_FN_ATTRS _mm_add_epi16(__m128i __a, /// A 128-bit vector of [4 x i32]. /// \returns A 128-bit vector of [4 x i32] containing the sums of both /// parameters. -static __inline__ __m128i __DEFAULT_FN_ATTRS _mm_add_epi32(__m128i __a, - __m128i __b) { +static __inline__ __m128i __DEFAULT_FN_ATTRS_CONSTEXPR +_mm_add_epi32(__m128i __a, __m128i __b) { return (__m128i)((__v4su)__a + (__v4su)__b); } @@ -2147,8 +2147,8 @@ static __inline__ __m64 __DEFAULT_FN_ATTRS _mm_add_si64(__m64 __a, __m64 __b) { /// A 128-bit vector of [2 x i64]. /// \returns A 128-bit vector of [2 x i64] containing the sums of both /// parameters. -static __inline__ __m128i __DEFAULT_FN_ATTRS _mm_add_epi64(__m128i __a, - __m128i __b) { +static __inline__ __m128i __DEFAULT_FN_ATTRS_CONSTEXPR +_mm_add_epi64(__m128i __a, __m128i __b) { return (__m128i)((__v2du)__a + (__v2du)__b); } @@ -2539,8 +2539,8 @@ static __inline__ __m128i __DEFAULT_FN_ATTRS _mm_sub_epi16(__m128i __a, /// A 128-bit integer vector containing the subtrahends. /// \returns A 128-bit integer vector containing the differences of the values /// in the operands. -static __inline__ __m128i __DEFAULT_FN_ATTRS _mm_sub_epi32(__m128i __a, - __m128i __b) { +static __inline__ __m128i __DEFAULT_FN_ATTRS_CONSTEXPR +_mm_sub_epi32(__m128i __a, __m128i __b) { return (__m128i)((__v4su)__a - (__v4su)__b); } @@ -2573,8 +2573,8 @@ static __inline__ __m64 __DEFAULT_FN_ATTRS _mm_sub_si64(__m64 __a, __m64 __b) { /// A 128-bit integer vector containing the subtrahends. /// \returns A 128-bit integer vector containing the differences of the values /// in the operands. -static __inline__ __m128i __DEFAULT_FN_ATTRS _mm_sub_epi64(__m128i __a, - __m128i __b) { +static __inline__ __m128i __DEFAULT_FN_ATTRS_CONSTEXPR +_mm_sub_epi64(__m128i __a, __m128i __b) { return (__m128i)((__v2du)__a - (__v2du)__b); } @@ -3512,8 +3512,8 @@ static __inline__ __m128i __DEFAULT_FN_ATTRS _mm_undefined_si128(void) { /// destination vector of [2 x i64]. /// \returns An initialized 128-bit vector of [2 x i64] containing the values /// provided in the operands. -static __inline__ __m128i __DEFAULT_FN_ATTRS _mm_set_epi64x(long long __q1, - long long __q0) { +static __inline__ __m128i __DEFAULT_FN_ATTRS_CONSTEXPR +_mm_set_epi64x(long long __q1, long long __q0) { return __extension__(__m128i)(__v2di){__q0, __q1}; } @@ -3533,9 +3533,9 @@ static __inline__ __m128i __DEFAULT_FN_ATTRS _mm_set_epi64x(long long __q1, /// destination vector of [2 x i64]. /// \returns An initialized 128-bit vector of [2 x i64] containing the values /// provided in the operands. -static __inline__ __m128i __DEFAULT_FN_ATTRS _mm_set_epi64(__m64 __q1, - __m64 __q0) { - return _mm_set_epi64x((long long)__q1, (long long)__q0); +static __inline__ __m128i __DEFAULT_FN_ATTRS_CONSTEXPR +_mm_set_epi64(__m64 __q1, __m64 __q0) { + return _mm_set_epi64x((long long)__q1[0], (long long)__q0[0]); } /// Initializes the 32-bit values in a 128-bit vector of [4 x i32] with @@ -3560,8 +3560,10 @@ static __inline__ __m128i __DEFAULT_FN_ATTRS _mm_set_epi64(__m64 __q1, /// vector. /// \returns An initialized 128-bit vector of [4 x i32] containing the values /// provided in the operands. -static __inline__ __m128i __DEFAULT_FN_ATTRS _mm_set_epi32(int __i3, int __i2, - int __i1, int __i0) { +static __inline__ __m128i __DEFAULT_FN_ATTRS_CONSTEXPR _mm_set_epi32(int __i3, + int __i2, + int __i1, + int __i0) { return __extension__(__m128i)(__v4si){__i0, __i1, __i2, __i3}; } @@ -3599,7 +3601,7 @@ static __inline__ __m128i __DEFAULT_FN_ATTRS _mm_set_epi32(int __i3, int __i2, /// vector. /// \returns An initialized 128-bit vector of [8 x i16] containing the values /// provided in the operands. -static __inline__ __m128i __DEFAULT_FN_ATTRS +static __inline__ __m128i __DEFAULT_FN_ATTRS_CONSTEXPR _mm_set_epi16(short __w7, short __w6, short __w5, short __w4, short __w3, short __w2, short __w1, short __w0) { return __extension__(__m128i)(__v8hi){__w0, __w1, __w2, __w3, @@ -3648,7 +3650,7 @@ _mm_set_epi16(short __w7, short __w6, short __w5, short __w4, short __w3, /// Initializes bits [7:0] of the destination vector. /// \returns An initialized 128-bit vector of [16 x i8] containing the values /// provided in the operands. -static __inline__ __m128i __DEFAULT_FN_ATTRS +static __inline__ __m128i __DEFAULT_FN_ATTRS_CONSTEXPR _mm_set_epi8(char __b15, char __b14, char __b13, char __b12, char __b11, char __b10, char __b9, char __b8, char __b7, char __b6, char __b5, char __b4, char __b3, char __b2, char __b1, char __b0) { @@ -3670,7 +3672,8 @@ _mm_set_epi8(char __b15, char __b14, char __b13, char __b12, char __b11, /// vector. /// \returns An initialized 128-bit integer vector of [2 x i64] with both /// elements containing the value provided in the operand. -static __inline__ __m128i __DEFAULT_FN_ATTRS _mm_set1_epi64x(long long __q) { +static __inline__ __m128i __DEFAULT_FN_ATTRS_CONSTEXPR +_mm_set1_epi64x(long long __q) { return _mm_set_epi64x(__q, __q); } @@ -3687,7 +3690,8 @@ static __inline__ __m128i __DEFAULT_FN_ATTRS _mm_set1_epi64x(long long __q) { /// vector. /// \returns An initialized 128-bit vector of [2 x i64] with all elements /// containing the value provided in the operand. -static __inline__ __m128i __DEFAULT_FN_ATTRS _mm_set1_epi64(__m64 __q) { +static __inline__ __m128i __DEFAULT_FN_ATTRS_CONSTEXPR +_mm_set1_epi64(__m64 __q) { return _mm_set_epi64(__q, __q); } @@ -3704,7 +3708,7 @@ static __inline__ __m128i __DEFAULT_FN_ATTRS _mm_set1_epi64(__m64 __q) { /// vector. /// \returns An initialized 128-bit vector of [4 x i32] with all elements /// containing the value provided in the operand. -static __inline__ __m128i __DEFAULT_FN_ATTRS _mm_set1_epi32(int __i) { +static __inline__ __m128i __DEFAULT_FN_ATTRS_CONSTEXPR _mm_set1_epi32(int __i) { return _mm_set_epi32(__i, __i, __i, __i); } @@ -3721,7 +3725,8 @@ static __inline__ __m128i __DEFAULT_FN_ATTRS _mm_set1_epi32(int __i) { /// vector. /// \returns An initialized 128-bit vector of [8 x i16] with all elements /// containing the value provided in the operand. -static __inline__ __m128i __DEFAULT_FN_ATTRS _mm_set1_epi16(short __w) { +static __inline__ __m128i __DEFAULT_FN_ATTRS_CONSTEXPR +_mm_set1_epi16(short __w) { return _mm_set_epi16(__w, __w, __w, __w, __w, __w, __w, __w); } @@ -3738,7 +3743,7 @@ static __inline__ __m128i __DEFAULT_FN_ATTRS _mm_set1_epi16(short __w) { /// vector. /// \returns An initialized 128-bit vector of [16 x i8] with all elements /// containing the value provided in the operand. -static __inline__ __m128i __DEFAULT_FN_ATTRS _mm_set1_epi8(char __b) { +static __inline__ __m128i __DEFAULT_FN_ATTRS_CONSTEXPR _mm_set1_epi8(char __b) { return _mm_set_epi8(__b, __b, __b, __b, __b, __b, __b, __b, __b, __b, __b, __b, __b, __b, __b, __b); } @@ -3757,8 +3762,8 @@ static __inline__ __m128i __DEFAULT_FN_ATTRS _mm_set1_epi8(char __b) { /// A 64-bit integral value used to initialize the upper 64 bits of the /// result. /// \returns An initialized 128-bit integer vector. -static __inline__ __m128i __DEFAULT_FN_ATTRS _mm_setr_epi64(__m64 __q0, - __m64 __q1) { +static __inline__ __m128i __DEFAULT_FN_ATTRS_CONSTEXPR +_mm_setr_epi64(__m64 __q0, __m64 __q1) { return _mm_set_epi64(__q1, __q0); } @@ -3779,9 +3784,8 @@ static __inline__ __m128i __DEFAULT_FN_ATTRS _mm_setr_epi64(__m64 __q0, /// \param __i3 /// A 32-bit integral value used to initialize bits [127:96] of the result. /// \returns An initialized 128-bit integer vector. -static __inline__ __m128i __DEFAULT_FN_ATTRS _mm_setr_epi32(int __i0, int __i1, - int __i2, - int __i3) { +static __inline__ __m128i __DEFAULT_FN_ATTRS_CONSTEXPR +_mm_setr_epi32(int __i0, int __i1, int __i2, int __i3) { return _mm_set_epi32(__i3, __i2, __i1, __i0); } @@ -3810,7 +3814,7 @@ static __inline__ __m128i __DEFAULT_FN_ATTRS _mm_setr_epi32(int __i0, int __i1, /// \param __w7 /// A 16-bit integral value used to initialize bits [127:112] of the result. /// \returns An initialized 128-bit integer vector. -static __inline__ __m128i __DEFAULT_FN_ATTRS +static __inline__ __m128i __DEFAULT_FN_ATTRS_CONSTEXPR _mm_setr_epi16(short __w0, short __w1, short __w2, short __w3, short __w4, short __w5, short __w6, short __w7) { return _mm_set_epi16(__w7, __w6, __w5, __w4, __w3, __w2, __w1, __w0); @@ -3857,7 +3861,7 @@ _mm_setr_epi16(short __w0, short __w1, short __w2, short __w3, short __w4, /// \param __b15 /// An 8-bit integral value used to initialize bits [127:120] of the result. /// \returns An initialized 128-bit integer vector. -static __inline__ __m128i __DEFAULT_FN_ATTRS +static __inline__ __m128i __DEFAULT_FN_ATTRS_CONSTEXPR _mm_setr_epi8(char __b0, char __b1, char __b2, char __b3, char __b4, char __b5, char __b6, char __b7, char __b8, char __b9, char __b10, char __b11, char __b12, char __b13, char __b14, char __b15) { diff --git a/clang/lib/Headers/hlsl/hlsl_intrinsics.h b/clang/lib/Headers/hlsl/hlsl_intrinsics.h index 8ade4b27f360fb..d9f3a17ea23d8e 100644 --- a/clang/lib/Headers/hlsl/hlsl_intrinsics.h +++ b/clang/lib/Headers/hlsl/hlsl_intrinsics.h @@ -723,66 +723,88 @@ float4 cosh(float4); #ifdef __HLSL_ENABLE_16_BIT _HLSL_AVAILABILITY(shadermodel, 6.2) -_HLSL_BUILTIN_ALIAS(__builtin_elementwise_popcount) -int16_t countbits(int16_t); +const inline uint countbits(int16_t x) { + return __builtin_elementwise_popcount(x); +} _HLSL_AVAILABILITY(shadermodel, 6.2) -_HLSL_BUILTIN_ALIAS(__builtin_elementwise_popcount) -int16_t2 countbits(int16_t2); +const inline uint2 countbits(int16_t2 x) { + return __builtin_elementwise_popcount(x); +} _HLSL_AVAILABILITY(shadermodel, 6.2) -_HLSL_BUILTIN_ALIAS(__builtin_elementwise_popcount) -int16_t3 countbits(int16_t3); +const inline uint3 countbits(int16_t3 x) { + return __builtin_elementwise_popcount(x); +} _HLSL_AVAILABILITY(shadermodel, 6.2) -_HLSL_BUILTIN_ALIAS(__builtin_elementwise_popcount) -int16_t4 countbits(int16_t4); +const inline uint4 countbits(int16_t4 x) { + return __builtin_elementwise_popcount(x); +} _HLSL_AVAILABILITY(shadermodel, 6.2) -_HLSL_BUILTIN_ALIAS(__builtin_elementwise_popcount) -uint16_t countbits(uint16_t); +const inline uint countbits(uint16_t x) { + return __builtin_elementwise_popcount(x); +} _HLSL_AVAILABILITY(shadermodel, 6.2) -_HLSL_BUILTIN_ALIAS(__builtin_elementwise_popcount) -uint16_t2 countbits(uint16_t2); +const inline uint2 countbits(uint16_t2 x) { + return __builtin_elementwise_popcount(x); +} _HLSL_AVAILABILITY(shadermodel, 6.2) -_HLSL_BUILTIN_ALIAS(__builtin_elementwise_popcount) -uint16_t3 countbits(uint16_t3); +const inline uint3 countbits(uint16_t3 x) { + return __builtin_elementwise_popcount(x); +} _HLSL_AVAILABILITY(shadermodel, 6.2) -_HLSL_BUILTIN_ALIAS(__builtin_elementwise_popcount) -uint16_t4 countbits(uint16_t4); +const inline uint4 countbits(uint16_t4 x) { + return __builtin_elementwise_popcount(x); +} #endif -_HLSL_BUILTIN_ALIAS(__builtin_elementwise_popcount) -int countbits(int); -_HLSL_BUILTIN_ALIAS(__builtin_elementwise_popcount) -int2 countbits(int2); -_HLSL_BUILTIN_ALIAS(__builtin_elementwise_popcount) -int3 countbits(int3); -_HLSL_BUILTIN_ALIAS(__builtin_elementwise_popcount) -int4 countbits(int4); - -_HLSL_BUILTIN_ALIAS(__builtin_elementwise_popcount) -uint countbits(uint); -_HLSL_BUILTIN_ALIAS(__builtin_elementwise_popcount) -uint2 countbits(uint2); -_HLSL_BUILTIN_ALIAS(__builtin_elementwise_popcount) -uint3 countbits(uint3); -_HLSL_BUILTIN_ALIAS(__builtin_elementwise_popcount) -uint4 countbits(uint4); - -_HLSL_BUILTIN_ALIAS(__builtin_elementwise_popcount) -int64_t countbits(int64_t); -_HLSL_BUILTIN_ALIAS(__builtin_elementwise_popcount) -int64_t2 countbits(int64_t2); -_HLSL_BUILTIN_ALIAS(__builtin_elementwise_popcount) -int64_t3 countbits(int64_t3); -_HLSL_BUILTIN_ALIAS(__builtin_elementwise_popcount) -int64_t4 countbits(int64_t4); - -_HLSL_BUILTIN_ALIAS(__builtin_elementwise_popcount) -uint64_t countbits(uint64_t); -_HLSL_BUILTIN_ALIAS(__builtin_elementwise_popcount) -uint64_t2 countbits(uint64_t2); -_HLSL_BUILTIN_ALIAS(__builtin_elementwise_popcount) -uint64_t3 countbits(uint64_t3); -_HLSL_BUILTIN_ALIAS(__builtin_elementwise_popcount) -uint64_t4 countbits(uint64_t4); +const inline uint countbits(int x) { return __builtin_elementwise_popcount(x); } +const inline uint2 countbits(int2 x) { + return __builtin_elementwise_popcount(x); +} +const inline uint3 countbits(int3 x) { + return __builtin_elementwise_popcount(x); +} +const inline uint4 countbits(int4 x) { + return __builtin_elementwise_popcount(x); +} + +const inline uint countbits(uint x) { + return __builtin_elementwise_popcount(x); +} +const inline uint2 countbits(uint2 x) { + return __builtin_elementwise_popcount(x); +} +const inline uint3 countbits(uint3 x) { + return __builtin_elementwise_popcount(x); +} +const inline uint4 countbits(uint4 x) { + return __builtin_elementwise_popcount(x); +} + +const inline uint countbits(int64_t x) { + return __builtin_elementwise_popcount(x); +} +const inline uint2 countbits(int64_t2 x) { + return __builtin_elementwise_popcount(x); +} +const inline uint3 countbits(int64_t3 x) { + return __builtin_elementwise_popcount(x); +} +const inline uint4 countbits(int64_t4 x) { + return __builtin_elementwise_popcount(x); +} + +const inline uint countbits(uint64_t x) { + return __builtin_elementwise_popcount(x); +} +const inline uint2 countbits(uint64_t2 x) { + return __builtin_elementwise_popcount(x); +} +const inline uint3 countbits(uint64_t3 x) { + return __builtin_elementwise_popcount(x); +} +const inline uint4 countbits(uint64_t4 x) { + return __builtin_elementwise_popcount(x); +} //===----------------------------------------------------------------------===// // degrees builtins diff --git a/clang/lib/Index/USRGeneration.cpp b/clang/lib/Index/USRGeneration.cpp index 35d0aefaf69a68..493123459a5a4d 100644 --- a/clang/lib/Index/USRGeneration.cpp +++ b/clang/lib/Index/USRGeneration.cpp @@ -62,20 +62,17 @@ namespace { class USRGenerator : public ConstDeclVisitor { SmallVectorImpl &Buf; llvm::raw_svector_ostream Out; - bool IgnoreResults; ASTContext *Context; - bool generatedLoc; + const LangOptions &LangOpts; + bool IgnoreResults = false; + bool generatedLoc = false; llvm::DenseMap TypeSubstitutions; public: - explicit USRGenerator(ASTContext *Ctx, SmallVectorImpl &Buf) - : Buf(Buf), - Out(Buf), - IgnoreResults(false), - Context(Ctx), - generatedLoc(false) - { + USRGenerator(ASTContext *Ctx, SmallVectorImpl &Buf, + const LangOptions &LangOpts) + : Buf(Buf), Out(Buf), Context(Ctx), LangOpts(LangOpts) { // Add the USR space prefix. Out << getUSRSpacePrefix(); } @@ -246,14 +243,13 @@ void USRGenerator::VisitFunctionDecl(const FunctionDecl *D) { } else Out << "@F@"; - PrintingPolicy Policy(Context->getLangOpts()); + PrintingPolicy Policy(LangOpts); // Forward references can have different template argument names. Suppress the // template argument names in constructors to make their USR more stable. Policy.SuppressTemplateArgsInCXXConstructors = true; D->getDeclName().print(Out, Policy); - ASTContext &Ctx = *Context; - if ((!Ctx.getLangOpts().CPlusPlus || D->isExternC()) && + if ((!LangOpts.CPlusPlus || D->isExternC()) && !D->hasAttr()) return; @@ -657,9 +653,10 @@ bool USRGenerator::GenLoc(const Decl *D, bool IncludeOffset) { return IgnoreResults; } -static void printQualifier(llvm::raw_ostream &Out, ASTContext &Ctx, NestedNameSpecifier *NNS) { +static void printQualifier(llvm::raw_ostream &Out, const LangOptions &LangOpts, + NestedNameSpecifier *NNS) { // FIXME: Encode the qualifier, don't just print it. - PrintingPolicy PO(Ctx.getLangOpts()); + PrintingPolicy PO(LangOpts); PO.SuppressTagKeyword = true; PO.SuppressUnwrittenScope = true; PO.ConstantArraySizeAsWritten = false; @@ -948,7 +945,7 @@ void USRGenerator::VisitType(QualType T) { } if (const DependentNameType *DNT = T->getAs()) { Out << '^'; - printQualifier(Out, Ctx, DNT->getQualifier()); + printQualifier(Out, LangOpts, DNT->getQualifier()); Out << ':' << DNT->getIdentifier()->getName(); return; } @@ -1090,7 +1087,7 @@ void USRGenerator::VisitUnresolvedUsingValueDecl(const UnresolvedUsingValueDecl return; VisitDeclContext(D->getDeclContext()); Out << "@UUV@"; - printQualifier(Out, D->getASTContext(), D->getQualifier()); + printQualifier(Out, LangOpts, D->getQualifier()); EmitDeclName(D); } @@ -1099,7 +1096,7 @@ void USRGenerator::VisitUnresolvedUsingTypenameDecl(const UnresolvedUsingTypenam return; VisitDeclContext(D->getDeclContext()); Out << "@UUT@"; - printQualifier(Out, D->getASTContext(), D->getQualifier()); + printQualifier(Out, LangOpts, D->getQualifier()); Out << D->getName(); // Simple name. } @@ -1190,6 +1187,13 @@ bool clang::index::generateUSRForDecl(const Decl *D, SmallVectorImpl &Buf) { if (!D) return true; + return generateUSRForDecl(D, Buf, D->getASTContext().getLangOpts()); +} + +bool clang::index::generateUSRForDecl(const Decl *D, SmallVectorImpl &Buf, + const LangOptions &LangOpts) { + if (!D) + return true; // We don't ignore decls with invalid source locations. Implicit decls, like // C++'s operator new function, can have invalid locations but it is fine to // create USRs that can identify them. @@ -1203,7 +1207,7 @@ bool clang::index::generateUSRForDecl(const Decl *D, return false; } } - USRGenerator UG(&D->getASTContext(), Buf); + USRGenerator UG(&D->getASTContext(), Buf, LangOpts); UG.Visit(D); return UG.ignoreResults(); } @@ -1240,11 +1244,17 @@ bool clang::index::generateUSRForMacro(StringRef MacroName, SourceLocation Loc, bool clang::index::generateUSRForType(QualType T, ASTContext &Ctx, SmallVectorImpl &Buf) { + return generateUSRForType(T, Ctx, Buf, Ctx.getLangOpts()); +} + +bool clang::index::generateUSRForType(QualType T, ASTContext &Ctx, + SmallVectorImpl &Buf, + const LangOptions &LangOpts) { if (T.isNull()) return true; T = T.getCanonicalType(); - USRGenerator UG(&Ctx, Buf); + USRGenerator UG(&Ctx, Buf, LangOpts); UG.VisitType(T); return UG.ignoreResults(); } diff --git a/clang/lib/Parse/ParseStmt.cpp b/clang/lib/Parse/ParseStmt.cpp index 7d727efb228731..6470e55e521add 100644 --- a/clang/lib/Parse/ParseStmt.cpp +++ b/clang/lib/Parse/ParseStmt.cpp @@ -1243,6 +1243,7 @@ StmtResult Parser::ParseCompoundStatementBody(bool isStmtExpr) { ParsedStmtContext::Compound | (isStmtExpr ? ParsedStmtContext::InStmtExpr : ParsedStmtContext()); + bool LastIsError = false; while (!tryParseMisplacedModuleImport() && Tok.isNot(tok::r_brace) && Tok.isNot(tok::eof)) { if (Tok.is(tok::annot_pragma_unused)) { @@ -1299,7 +1300,15 @@ StmtResult Parser::ParseCompoundStatementBody(bool isStmtExpr) { if (R.isUsable()) Stmts.push_back(R.get()); + LastIsError = R.isInvalid(); } + // StmtExpr needs to do copy initialization for last statement. + // If last statement is invalid, the last statement in `Stmts` will be + // incorrect. Then the whole compound statement should also be marked as + // invalid to prevent subsequent errors. + if (isStmtExpr && LastIsError && !Stmts.empty()) + return StmtError(); + // Warn the user that using option `-ffp-eval-method=source` on a // 32-bit target and feature `sse` disabled, or using // `pragma clang fp eval_method=source` and feature `sse` disabled, is not diff --git a/clang/lib/Sema/CheckExprLifetime.cpp b/clang/lib/Sema/CheckExprLifetime.cpp index aa0a2e223e708f..357082fe329350 100644 --- a/clang/lib/Sema/CheckExprLifetime.cpp +++ b/clang/lib/Sema/CheckExprLifetime.cpp @@ -472,7 +472,7 @@ shouldTrackFirstArgumentForConstructor(const CXXConstructExpr *Ctor) { } // Return true if this is an "normal" assignment operator. -// We assuments that a normal assingment operator always returns *this, that is, +// We assume that a normal assignment operator always returns *this, that is, // an lvalue reference that is the same type as the implicit object parameter // (or the LHS for a non-member operator$=). static bool isNormalAssignmentOperator(const FunctionDecl *FD) { diff --git a/clang/lib/Sema/SemaChecking.cpp b/clang/lib/Sema/SemaChecking.cpp index 3308b898a5b68f..dae271c1ff5001 100644 --- a/clang/lib/Sema/SemaChecking.cpp +++ b/clang/lib/Sema/SemaChecking.cpp @@ -8900,7 +8900,12 @@ void Sema::CheckMemaccessArguments(const CallExpr *Call, << Call->getCallee()->getSourceRange()); else if (const auto *RT = PointeeTy->getAs()) { - bool IsTriviallyCopyableCXXRecord = + // FIXME: Do not consider incomplete types even though they may be + // completed later. GCC does not diagnose such code, but we may want to + // consider diagnosing it in the future, perhaps under a different, but + // related, diagnostic group. + bool MayBeTriviallyCopyableCXXRecord = + RT->isIncompleteType() || RT->desugar().isTriviallyCopyableType(Context); if ((BId == Builtin::BImemset || BId == Builtin::BIbzero) && @@ -8910,7 +8915,7 @@ void Sema::CheckMemaccessArguments(const CallExpr *Call, << ArgIdx << FnName << PointeeTy << 0); SearchNonTrivialToInitializeField::diag(PointeeTy, Dest, *this); } else if ((BId == Builtin::BImemset || BId == Builtin::BIbzero) && - !IsTriviallyCopyableCXXRecord && ArgIdx == 0) { + !MayBeTriviallyCopyableCXXRecord && ArgIdx == 0) { // FIXME: Limiting this warning to dest argument until we decide // whether it's valid for source argument too. DiagRuntimeBehavior(Dest->getExprLoc(), Dest, @@ -8923,7 +8928,7 @@ void Sema::CheckMemaccessArguments(const CallExpr *Call, << ArgIdx << FnName << PointeeTy << 1); SearchNonTrivialToCopyField::diag(PointeeTy, Dest, *this); } else if ((BId == Builtin::BImemcpy || BId == Builtin::BImemmove) && - !IsTriviallyCopyableCXXRecord && ArgIdx == 0) { + !MayBeTriviallyCopyableCXXRecord && ArgIdx == 0) { // FIXME: Limiting this warning to dest argument until we decide // whether it's valid for source argument too. DiagRuntimeBehavior(Dest->getExprLoc(), Dest, diff --git a/clang/lib/Sema/SemaTemplate.cpp b/clang/lib/Sema/SemaTemplate.cpp index fcf05798d9c709..4503e60cff8c2f 100644 --- a/clang/lib/Sema/SemaTemplate.cpp +++ b/clang/lib/Sema/SemaTemplate.cpp @@ -4381,8 +4381,20 @@ Sema::CheckVarTemplateId(VarTemplateDecl *Template, SourceLocation TemplateLoc, SmallVector PartialSpecs; Template->getPartialSpecializations(PartialSpecs); - for (unsigned I = 0, N = PartialSpecs.size(); I != N; ++I) { - VarTemplatePartialSpecializationDecl *Partial = PartialSpecs[I]; + for (VarTemplatePartialSpecializationDecl *Partial : PartialSpecs) { + // C++ [temp.spec.partial.member]p2: + // If the primary member template is explicitly specialized for a given + // (implicit) specialization of the enclosing class template, the partial + // specializations of the member template are ignored for this + // specialization of the enclosing class template. If a partial + // specialization of the member template is explicitly specialized for a + // given (implicit) specialization of the enclosing class template, the + // primary member template and its other partial specializations are still + // considered for this specialization of the enclosing class template. + if (Template->getMostRecentDecl()->isMemberSpecialization() && + !Partial->getMostRecentDecl()->isMemberSpecialization()) + continue; + TemplateDeductionInfo Info(FailedCandidates.getLocation()); if (TemplateDeductionResult Result = diff --git a/clang/lib/Sema/SemaTemplateDeduction.cpp b/clang/lib/Sema/SemaTemplateDeduction.cpp index db1d7fa237131a..b45f30fed49a64 100644 --- a/clang/lib/Sema/SemaTemplateDeduction.cpp +++ b/clang/lib/Sema/SemaTemplateDeduction.cpp @@ -6163,7 +6163,7 @@ struct TemplateArgumentListAreEqual { std::enable_if_t, bool> = true> bool operator()(T1 *Spec, T2 *Primary) { ArrayRef Args1 = Spec->getTemplateArgs().asArray(), - Args2 = Primary->getInjectedTemplateArgs(); + Args2 = Primary->getInjectedTemplateArgs(Ctx); for (unsigned I = 0, E = Args1.size(); I < E; ++I) { // We use profile, instead of structural comparison of the arguments, @@ -6342,7 +6342,7 @@ bool Sema::isMoreSpecializedThanPrimary( VarTemplateDecl *Primary = Spec->getSpecializedTemplate(); TemplateName Name(Primary); QualType PrimaryT = Context.getTemplateSpecializationType( - Name, Primary->getInjectedTemplateArgs()); + Name, Primary->getInjectedTemplateArgs(Context)); QualType PartialT = Context.getTemplateSpecializationType( Name, Spec->getTemplateArgs().asArray()); @@ -6372,18 +6372,14 @@ bool Sema::isTemplateTemplateParameterAtLeastAsSpecializedAs( // - Each function template has a single function parameter whose type is // a specialization of X with template arguments corresponding to the // template parameters from the respective function template - SmallVector AArgs; - Context.getInjectedTemplateArgs(A, AArgs); + SmallVector AArgs(A->getInjectedTemplateArgs(Context)); // Check P's arguments against A's parameter list. This will fill in default // template arguments as needed. AArgs are already correct by construction. // We can't just use CheckTemplateIdType because that will expand alias // templates. - SmallVector PArgs; + SmallVector PArgs(P->getInjectedTemplateArgs(Context)); { - SFINAETrap Trap(*this); - - Context.getInjectedTemplateArgs(P, PArgs); TemplateArgumentListInfo PArgList(P->getLAngleLoc(), P->getRAngleLoc()); for (unsigned I = 0, N = P->size(); I != N; ++I) { @@ -6399,6 +6395,7 @@ bool Sema::isTemplateTemplateParameterAtLeastAsSpecializedAs( } PArgs.clear(); + SFINAETrap Trap(*this); // C++1z [temp.arg.template]p3: // If the rewrite produces an invalid type, then P is not at least as // specialized as A. diff --git a/clang/lib/Sema/SemaTemplateInstantiate.cpp b/clang/lib/Sema/SemaTemplateInstantiate.cpp index cddfcc48312042..7a9252828ff862 100644 --- a/clang/lib/Sema/SemaTemplateInstantiate.cpp +++ b/clang/lib/Sema/SemaTemplateInstantiate.cpp @@ -200,7 +200,7 @@ struct TemplateInstantiationArgumentCollecter if (Innermost) AddInnermostTemplateArguments(FTD); else if (ForConstraintInstantiation) - AddOuterTemplateArguments(FTD, FTD->getInjectedTemplateArgs(), + AddOuterTemplateArguments(FTD, FTD->getInjectedTemplateArgs(S.Context), /*Final=*/false); if (FTD->isMemberSpecialization()) @@ -219,7 +219,7 @@ struct TemplateInstantiationArgumentCollecter if (Innermost) AddInnermostTemplateArguments(VTD); else if (ForConstraintInstantiation) - AddOuterTemplateArguments(VTD, VTD->getInjectedTemplateArgs(), + AddOuterTemplateArguments(VTD, VTD->getInjectedTemplateArgs(S.Context), /*Final=*/false); if (VTD->isMemberSpecialization()) @@ -237,7 +237,8 @@ struct TemplateInstantiationArgumentCollecter if (Innermost) AddInnermostTemplateArguments(VTPSD); else if (ForConstraintInstantiation) - AddOuterTemplateArguments(VTPSD, VTPSD->getInjectedTemplateArgs(), + AddOuterTemplateArguments(VTPSD, + VTPSD->getInjectedTemplateArgs(S.Context), /*Final=*/false); if (VTPSD->isMemberSpecialization()) @@ -254,7 +255,7 @@ struct TemplateInstantiationArgumentCollecter if (Innermost) AddInnermostTemplateArguments(CTD); else if (ForConstraintInstantiation) - AddOuterTemplateArguments(CTD, CTD->getInjectedTemplateArgs(), + AddOuterTemplateArguments(CTD, CTD->getInjectedTemplateArgs(S.Context), /*Final=*/false); if (CTD->isMemberSpecialization()) @@ -274,7 +275,8 @@ struct TemplateInstantiationArgumentCollecter if (Innermost) AddInnermostTemplateArguments(CTPSD); else if (ForConstraintInstantiation) - AddOuterTemplateArguments(CTPSD, CTPSD->getInjectedTemplateArgs(), + AddOuterTemplateArguments(CTPSD, + CTPSD->getInjectedTemplateArgs(S.Context), /*Final=*/false); if (CTPSD->isMemberSpecialization()) @@ -290,7 +292,7 @@ struct TemplateInstantiationArgumentCollecter if (Innermost) AddInnermostTemplateArguments(TATD); else if (ForConstraintInstantiation) - AddOuterTemplateArguments(TATD, TATD->getInjectedTemplateArgs(), + AddOuterTemplateArguments(TATD, TATD->getInjectedTemplateArgs(S.Context), /*Final=*/false); return UseNextDecl(TATD); @@ -3976,11 +3978,24 @@ bool Sema::usesPartialOrExplicitSpecialization( return true; SmallVector PartialSpecs; - ClassTemplateSpec->getSpecializedTemplate() - ->getPartialSpecializations(PartialSpecs); - for (unsigned I = 0, N = PartialSpecs.size(); I != N; ++I) { + ClassTemplateDecl *CTD = ClassTemplateSpec->getSpecializedTemplate(); + CTD->getPartialSpecializations(PartialSpecs); + for (ClassTemplatePartialSpecializationDecl *CTPSD : PartialSpecs) { + // C++ [temp.spec.partial.member]p2: + // If the primary member template is explicitly specialized for a given + // (implicit) specialization of the enclosing class template, the partial + // specializations of the member template are ignored for this + // specialization of the enclosing class template. If a partial + // specialization of the member template is explicitly specialized for a + // given (implicit) specialization of the enclosing class template, the + // primary member template and its other partial specializations are still + // considered for this specialization of the enclosing class template. + if (CTD->getMostRecentDecl()->isMemberSpecialization() && + !CTPSD->getMostRecentDecl()->isMemberSpecialization()) + continue; + TemplateDeductionInfo Info(Loc); - if (DeduceTemplateArguments(PartialSpecs[I], + if (DeduceTemplateArguments(CTPSD, ClassTemplateSpec->getTemplateArgs().asArray(), Info) == TemplateDeductionResult::Success) return true; @@ -4023,8 +4038,21 @@ getPatternForClassTemplateSpecialization( SmallVector PartialSpecs; Template->getPartialSpecializations(PartialSpecs); TemplateSpecCandidateSet FailedCandidates(PointOfInstantiation); - for (unsigned I = 0, N = PartialSpecs.size(); I != N; ++I) { - ClassTemplatePartialSpecializationDecl *Partial = PartialSpecs[I]; + for (ClassTemplatePartialSpecializationDecl *Partial : PartialSpecs) { + // C++ [temp.spec.partial.member]p2: + // If the primary member template is explicitly specialized for a given + // (implicit) specialization of the enclosing class template, the + // partial specializations of the member template are ignored for this + // specialization of the enclosing class template. If a partial + // specialization of the member template is explicitly specialized for a + // given (implicit) specialization of the enclosing class template, the + // primary member template and its other partial specializations are + // still considered for this specialization of the enclosing class + // template. + if (Template->getMostRecentDecl()->isMemberSpecialization() && + !Partial->getMostRecentDecl()->isMemberSpecialization()) + continue; + TemplateDeductionInfo Info(FailedCandidates.getLocation()); if (TemplateDeductionResult Result = S.DeduceTemplateArguments( Partial, ClassTemplateSpec->getTemplateArgs().asArray(), Info); diff --git a/clang/lib/StaticAnalyzer/Checkers/WebKit/UncountedLocalVarsChecker.cpp b/clang/lib/StaticAnalyzer/Checkers/WebKit/UncountedLocalVarsChecker.cpp index 5cdf047738abcb..76a4599cc8d788 100644 --- a/clang/lib/StaticAnalyzer/Checkers/WebKit/UncountedLocalVarsChecker.cpp +++ b/clang/lib/StaticAnalyzer/Checkers/WebKit/UncountedLocalVarsChecker.cpp @@ -48,6 +48,65 @@ bool isRefcountedStringsHack(const VarDecl *V) { return false; } +struct GuardianVisitor : public RecursiveASTVisitor { + using Base = RecursiveASTVisitor; + + const VarDecl *Guardian{nullptr}; + +public: + explicit GuardianVisitor(const VarDecl *Guardian) : Guardian(Guardian) { + assert(Guardian); + } + + bool VisitBinaryOperator(const BinaryOperator *BO) { + if (BO->isAssignmentOp()) { + if (auto *VarRef = dyn_cast(BO->getLHS())) { + if (VarRef->getDecl() == Guardian) + return false; + } + } + return true; + } + + bool VisitCXXConstructExpr(const CXXConstructExpr *CE) { + if (auto *Ctor = CE->getConstructor()) { + if (Ctor->isMoveConstructor() && CE->getNumArgs() == 1) { + auto *Arg = CE->getArg(0)->IgnoreParenCasts(); + if (auto *VarRef = dyn_cast(Arg)) { + if (VarRef->getDecl() == Guardian) + return false; + } + } + } + return true; + } + + bool VisitCXXMemberCallExpr(const CXXMemberCallExpr *MCE) { + auto MethodName = safeGetName(MCE->getMethodDecl()); + if (MethodName == "swap" || MethodName == "leakRef" || + MethodName == "releaseNonNull") { + auto *ThisArg = MCE->getImplicitObjectArgument()->IgnoreParenCasts(); + if (auto *VarRef = dyn_cast(ThisArg)) { + if (VarRef->getDecl() == Guardian) + return false; + } + } + return true; + } + + bool VisitCXXOperatorCallExpr(const CXXOperatorCallExpr *OCE) { + if (OCE->isAssignmentOp()) { + assert(OCE->getNumArgs() == 2); + auto *ThisArg = OCE->getArg(0)->IgnoreParenCasts(); + if (auto *VarRef = dyn_cast(ThisArg)) { + if (VarRef->getDecl() == Guardian) + return false; + } + } + return true; + } +}; + bool isGuardedScopeEmbeddedInGuardianScope(const VarDecl *Guarded, const VarDecl *MaybeGuardian) { assert(Guarded); @@ -81,7 +140,7 @@ bool isGuardedScopeEmbeddedInGuardianScope(const VarDecl *Guarded, // We need to skip the first CompoundStmt to avoid situation when guardian is // defined in the same scope as guarded variable. - bool HaveSkippedFirstCompoundStmt = false; + const CompoundStmt *FirstCompondStmt = nullptr; for (DynTypedNodeList guardedVarAncestors = ctx.getParents(*Guarded); !guardedVarAncestors.empty(); guardedVarAncestors = ctx.getParents( @@ -90,12 +149,15 @@ bool isGuardedScopeEmbeddedInGuardianScope(const VarDecl *Guarded, ) { for (auto &guardedVarAncestor : guardedVarAncestors) { if (auto *CStmtAncestor = guardedVarAncestor.get()) { - if (!HaveSkippedFirstCompoundStmt) { - HaveSkippedFirstCompoundStmt = true; + if (!FirstCompondStmt) { + FirstCompondStmt = CStmtAncestor; continue; } - if (CStmtAncestor == guardiansClosestCompStmtAncestor) - return true; + if (CStmtAncestor == guardiansClosestCompStmtAncestor) { + GuardianVisitor guardianVisitor(MaybeGuardian); + auto *GuardedScope = const_cast(FirstCompondStmt); + return guardianVisitor.TraverseCompoundStmt(GuardedScope); + } } } } diff --git a/clang/lib/Tooling/Inclusions/Stdlib/StdSpecialSymbolMap.inc b/clang/lib/Tooling/Inclusions/Stdlib/StdSpecialSymbolMap.inc index 0d351d688a3296..4d466013eeac3f 100644 --- a/clang/lib/Tooling/Inclusions/Stdlib/StdSpecialSymbolMap.inc +++ b/clang/lib/Tooling/Inclusions/Stdlib/StdSpecialSymbolMap.inc @@ -367,6 +367,11 @@ SYMBOL(any_cast, std::, ) SYMBOL(div, std::, ) SYMBOL(abort, std::, ) +SYMBOL(binary_search, std::ranges::, ) +SYMBOL(equal_range, std::ranges::, ) +SYMBOL(lower_bound, std::ranges::, ) +SYMBOL(upper_bound, std::ranges::, ) + // These are C symbols that are not under std namespace. SYMBOL(localtime_r, None, ) SYMBOL(localtime_r, None, ) diff --git a/clang/test/AST/ByteCode/placement-new.cpp b/clang/test/AST/ByteCode/placement-new.cpp index 5673b5cba3f700..56f54ff168f3e8 100644 --- a/clang/test/AST/ByteCode/placement-new.cpp +++ b/clang/test/AST/ByteCode/placement-new.cpp @@ -14,7 +14,9 @@ namespace std { template constexpr void construct_at(void *p, Args &&...args) { new (p) T((Args&&)args...); // both-note {{in call to}} \ - // both-note {{placement new would change type of storage from 'int' to 'float'}} + // both-note {{placement new would change type of storage from 'int' to 'float'}} \ + // both-note {{construction of subobject of member 'x' of union with active member 'a' is not allowed in a constant expression}} + } } @@ -284,6 +286,18 @@ namespace ConstructAt { static_assert(bad_construct_at_type()); // both-error {{not an integral constant expression}} \ // both-note {{in call}} + constexpr bool bad_construct_at_subobject() { + struct X { int a, b; }; + union A { + int a; + X x; + }; + A a = {1}; + std::construct_at(&a.x.a, 1); // both-note {{in call}} + return true; + } + static_assert(bad_construct_at_subobject()); // both-error{{not an integral constant expression}} \ + // both-note {{in call}} } namespace UsedToCrash { diff --git a/clang/test/Analysis/Checkers/WebKit/mock-types.h b/clang/test/Analysis/Checkers/WebKit/mock-types.h index 8d8a90f0afae0e..82c79c97a83de6 100644 --- a/clang/test/Analysis/Checkers/WebKit/mock-types.h +++ b/clang/test/Analysis/Checkers/WebKit/mock-types.h @@ -49,7 +49,23 @@ template , typename RefDerefTra Ref() : t{} {}; Ref(T &t) : t(&RefDerefTraits::ref(t)) { } Ref(const Ref& o) : t(RefDerefTraits::refIfNotNull(PtrTraits::unwrap(o.t))) { } + Ref(Ref&& o) : t(o.leakRef()) { } ~Ref() { RefDerefTraits::derefIfNotNull(PtrTraits::exchange(t, nullptr)); } + Ref& operator=(T &t) { + Ref o(t); + swap(o); + return *this; + } + Ref& operator=(Ref &&o) { + Ref m(o); + swap(m); + return *this; + } + void swap(Ref& o) { + typename PtrTraits::StorageType tmp = t; + t = o.t; + o.t = tmp; + } T &get() { return *PtrTraits::unwrap(t); } T *ptr() { return PtrTraits::unwrap(t); } T *operator->() { return PtrTraits::unwrap(t); } @@ -74,11 +90,27 @@ template struct RefPtr { if (t) t->deref(); } + Ref releaseNonNull() { + Ref tmp(*t); + if (t) + t->deref(); + t = nullptr; + return tmp; + } + void swap(RefPtr& o) { + T* tmp = t; + t = o.t; + o.t = tmp; + } T *get() { return t; } T *operator->() { return t; } const T *operator->() const { return t; } T &operator*() { return *t; } - RefPtr &operator=(T *) { return *this; } + RefPtr &operator=(T *t) { + RefPtr o(t); + swap(o); + return *this; + } operator bool() const { return t; } }; diff --git a/clang/test/Analysis/Checkers/WebKit/uncounted-local-vars.cpp b/clang/test/Analysis/Checkers/WebKit/uncounted-local-vars.cpp index 1c0df42cdda663..d7fb689557a6fc 100644 --- a/clang/test/Analysis/Checkers/WebKit/uncounted-local-vars.cpp +++ b/clang/test/Analysis/Checkers/WebKit/uncounted-local-vars.cpp @@ -83,6 +83,83 @@ void foo7(RefCountable* obj) { bar.obj->method(); } +void foo8(RefCountable* obj) { + RefPtr foo; + { + RefCountable *bar = foo.get(); + // expected-warning@-1{{Local variable 'bar' is uncounted and unsafe [alpha.webkit.UncountedLocalVarsChecker]}} + foo = nullptr; + bar->method(); + } + RefPtr baz; + { + RefCountable *bar = baz.get(); + // expected-warning@-1{{Local variable 'bar' is uncounted and unsafe [alpha.webkit.UncountedLocalVarsChecker]}} + baz = obj; + bar->method(); + } + foo = nullptr; + { + RefCountable *bar = foo.get(); + // No warning. It's okay to mutate RefPtr in an outer scope. + bar->method(); + } + foo = obj; + { + RefCountable *bar = foo.get(); + // expected-warning@-1{{Local variable 'bar' is uncounted and unsafe [alpha.webkit.UncountedLocalVarsChecker]}} + foo.releaseNonNull(); + bar->method(); + } + { + RefCountable *bar = foo.get(); + // expected-warning@-1{{Local variable 'bar' is uncounted and unsafe [alpha.webkit.UncountedLocalVarsChecker]}} + foo = obj ? obj : nullptr; + bar->method(); + } + { + RefCountable *bar = foo->trivial() ? foo.get() : nullptr; + // expected-warning@-1{{Local variable 'bar' is uncounted and unsafe [alpha.webkit.UncountedLocalVarsChecker]}} + foo = nullptr; + bar->method(); + } +} + +void foo9(RefCountable& o) { + Ref guardian(o); + { + RefCountable &bar = guardian.get(); + // expected-warning@-1{{Local variable 'bar' is uncounted and unsafe [alpha.webkit.UncountedLocalVarsChecker]}} + guardian = o; // We don't detect that we're setting it to the same value. + bar.method(); + } + { + RefCountable *bar = guardian.ptr(); + // expected-warning@-1{{Local variable 'bar' is uncounted and unsafe [alpha.webkit.UncountedLocalVarsChecker]}} + Ref other(*bar); // We don't detect other has the same value as guardian. + guardian.swap(other); + bar->method(); + } + { + RefCountable *bar = guardian.ptr(); + // expected-warning@-1{{Local variable 'bar' is uncounted and unsafe [alpha.webkit.UncountedLocalVarsChecker]}} + Ref other(static_cast&&>(guardian)); + bar->method(); + } + { + RefCountable *bar = guardian.ptr(); + // expected-warning@-1{{Local variable 'bar' is uncounted and unsafe [alpha.webkit.UncountedLocalVarsChecker]}} + guardian.leakRef(); + bar->method(); + } + { + RefCountable *bar = guardian.ptr(); + // expected-warning@-1{{Local variable 'bar' is uncounted and unsafe [alpha.webkit.UncountedLocalVarsChecker]}} + guardian = o.trivial() ? o : *bar; + bar->method(); + } +} + } // namespace guardian_scopes namespace auto_keyword { diff --git a/clang/test/CXX/temp/temp.decls/temp.spec.partial/temp.spec.partial.member/p2.cpp b/clang/test/CXX/temp/temp.decls/temp.spec.partial/temp.spec.partial.member/p2.cpp new file mode 100644 index 00000000000000..7969b7efe597f9 --- /dev/null +++ b/clang/test/CXX/temp/temp.decls/temp.spec.partial/temp.spec.partial.member/p2.cpp @@ -0,0 +1,85 @@ +// RUN: %clang_cc1 -std=c++20 -fsyntax-only -verify %s +// expected-no-diagnostics + +template +struct A { + template + struct B { + static constexpr int y = 0; + }; + + template + struct B { + static constexpr int y = 1; + }; + + template + static constexpr int x = 0; + + template + static constexpr int x = 1; +}; + +template +template +struct A::B { + static constexpr int y = 2; +}; + +template +template +constexpr int A::x = 2; + +static_assert(A::B::y == 0); +static_assert(A::B::y == 1); +static_assert(A::B::y == 2); +static_assert(A::x == 0); +static_assert(A::x == 1); +static_assert(A::x == 2); + +template<> +template +struct A::B { + static constexpr int y = 3; +}; + +template<> +template +struct A::B { + static constexpr int y = 4; +}; + +template<> +template +struct A::B { + static constexpr int y = 5; +}; + +template<> +template +constexpr int A::x = 3; + +template<> +template +constexpr int A::x = 4; + +template<> +template +constexpr int A::x = 5; + +static_assert(A::B::y == 3); +static_assert(A::B::y == 3); +static_assert(A::B::y == 3); +static_assert(A::B::y == 4); +static_assert(A::x == 3); +static_assert(A::x == 3); +static_assert(A::x == 3); +static_assert(A::x == 4); +static_assert(A::B::y == 0); +static_assert(A::B::y == 1); +static_assert(A::B::y == 2); +static_assert(A::B::y == 5); +static_assert(A::x == 0); +static_assert(A::x == 1); +static_assert(A::x == 2); +static_assert(A::x == 5); diff --git a/clang/test/CodeGen/X86/avx-builtins.c b/clang/test/CodeGen/X86/avx-builtins.c index 9d6c1897f540d3..4e56204c8ad40f 100644 --- a/clang/test/CodeGen/X86/avx-builtins.c +++ b/clang/test/CodeGen/X86/avx-builtins.c @@ -11,6 +11,7 @@ #include +#include "builtin_test_helpers.h" // NOTE: This should match the tests in llvm/test/CodeGen/X86/avx-intrinsics-fast-isel.ll @@ -1740,18 +1741,21 @@ __m256d test_mm256_setzero_pd(void) { // CHECK: store <4 x double> zeroinitializer return _mm256_setzero_pd(); } +TEST_CONSTEXPR(match_m256d(_mm256_setzero_pd(), +0.0, +0.0, +0.0, +0.0)); __m256 test_mm256_setzero_ps(void) { // CHECK-LABEL: test_mm256_setzero_ps // CHECK: store <8 x float> zeroinitializer return _mm256_setzero_ps(); } +TEST_CONSTEXPR(match_m256(_mm256_setzero_ps(), +0.0f, +0.0f, +0.0f, +0.0f, +0.0f, +0.0f, +0.0f, +0.0f)); __m256i test_mm256_setzero_si256(void) { // CHECK-LABEL: test_mm256_setzero_si256 // CHECK: store <4 x i64> zeroinitializer return _mm256_setzero_si256(); } +TEST_CONSTEXPR(match_m256i(_mm256_setzero_si256(), 0, 0, 0, 0)); __m256d test_mm256_shuffle_pd(__m256d A, __m256d B) { // CHECK-LABEL: test_mm256_shuffle_pd @@ -2097,19 +2101,3 @@ float test_mm256_cvtss_f32(__m256 __a) // CHECK: extractelement <8 x float> %{{.*}}, i32 0 return _mm256_cvtss_f32(__a); } - -// Test constexpr handling. -#if defined(__cplusplus) && (__cplusplus >= 201103L) - -void test_constexpr() { - constexpr __m256d v_mm256_setzero_pd = _mm256_setzero_pd(); - static_assert(v_mm256_setzero_pd[0] == +0.0 && v_mm256_setzero_pd[1] == +0.0 && v_mm256_setzero_pd[2] == +0.0 && v_mm256_setzero_pd[3] == +0.0); - - constexpr __m256 v_mm256_setzero_ps = _mm256_setzero_ps(); - static_assert(v_mm256_setzero_ps[0] == +0.0f && v_mm256_setzero_ps[1] == +0.0f && v_mm256_setzero_ps[2] == +0.0f && v_mm256_setzero_ps[3] == +0.0f && v_mm256_setzero_ps[4] == +0.0f && v_mm256_setzero_ps[5] == +0.0f && v_mm256_setzero_ps[6] == +0.0f && v_mm256_setzero_ps[7] == +0.0f); - - constexpr __m256i v_mm256_setzero_si256 = _mm256_setzero_si256(); - static_assert(v_mm256_setzero_si256[0] == 0x0000000000000000ULL && v_mm256_setzero_si256[1] == 0x0000000000000000ULL && v_mm256_setzero_si256[2] == 0x0000000000000000ULL && v_mm256_setzero_si256[3] == 0x0000000000000000ULL); -} - -#endif diff --git a/clang/test/CodeGen/X86/avx512f-builtins.c b/clang/test/CodeGen/X86/avx512f-builtins.c index 0b4f778a0637ab..372790a8cd668b 100644 --- a/clang/test/CodeGen/X86/avx512f-builtins.c +++ b/clang/test/CodeGen/X86/avx512f-builtins.c @@ -4,6 +4,7 @@ // RUN: %clang_cc1 -x c++ -flax-vector-conversions=none -fms-extensions -fms-compatibility -ffreestanding %s -triple=x86_64-windows-msvc -target-feature +avx512f -emit-llvm -o - -Wall -Werror -Wsign-conversion | FileCheck %s #include +#include "builtin_test_helpers.h" __m512d test_mm512_sqrt_pd(__m512d a) { @@ -10615,13 +10616,13 @@ __m128 test_mm_maskz_cvtsd_ss(__mmask8 __U, __m128 __A, __m128d __B) { return _mm_maskz_cvtsd_ss(__U, __A, __B); } - __m512i test_mm512_setzero_epi32(void) { // CHECK-LABEL: test_mm512_setzero_epi32 // CHECK: zeroinitializer return _mm512_setzero_epi32(); } +TEST_CONSTEXPR(match_m512i(_mm512_setzero_epi32(), 0, 0, 0, 0, 0, 0, 0, 0)); __m512 test_mm512_setzero(void) { @@ -10629,6 +10630,7 @@ __m512 test_mm512_setzero(void) // CHECK: zeroinitializer return _mm512_setzero(); } +TEST_CONSTEXPR(match_m512(_mm512_setzero(), +0.0f, +0.0f, +0.0f, +0.0f, +0.0f, +0.0f, +0.0f, +0.0f, +0.0f, +0.0f, +0.0f, +0.0f, +0.0f, +0.0f, +0.0f, +0.0f)); __m512i test_mm512_setzero_si512(void) { @@ -10636,6 +10638,7 @@ __m512i test_mm512_setzero_si512(void) // CHECK: zeroinitializer return _mm512_setzero_si512(); } +TEST_CONSTEXPR(match_m512i(_mm512_setzero_si512(), 0, 0, 0, 0, 0, 0, 0, 0)); __m512 test_mm512_setzero_ps(void) { @@ -10643,6 +10646,7 @@ __m512 test_mm512_setzero_ps(void) // CHECK: zeroinitializer return _mm512_setzero_ps(); } +TEST_CONSTEXPR(match_m512(_mm512_setzero_ps(), +0.0f, +0.0f, +0.0f, +0.0f, +0.0f, +0.0f, +0.0f, +0.0f, +0.0f, +0.0f, +0.0f, +0.0f, +0.0f, +0.0f, +0.0f, +0.0f)); __m512d test_mm512_setzero_pd(void) { @@ -10650,6 +10654,7 @@ __m512d test_mm512_setzero_pd(void) // CHECK: zeroinitializer return _mm512_setzero_pd(); } +TEST_CONSTEXPR(match_m512d(_mm512_setzero_pd(), 0.0, 0.0, 0.0, 0.0, 0.0, 0.0, 0.0, 0.0)); __mmask16 test_mm512_int2mask(int __a) { @@ -10880,25 +10885,3 @@ void test_mm512_mask_i32loscatter_epi64(void *__addr, __mmask8 __mask, __m512i _ // CHECK: @llvm.x86.avx512.mask.scatter.dpq.512 _mm512_mask_i32loscatter_epi64(__addr, __mask, __index, __v1, 2); } - -// Test constexpr handling. -#if defined(__cplusplus) && (__cplusplus >= 201103L) - -void test_constexpr() { - constexpr __m512 v_mm512_setzero = _mm512_setzero(); - static_assert(v_mm512_setzero[0] == +0.0f && v_mm512_setzero[1] == +0.0f && v_mm512_setzero[2] == +0.0f && v_mm512_setzero[3] == +0.0f && v_mm512_setzero[4] == +0.0f && v_mm512_setzero[5] == +0.0f && v_mm512_setzero[6] == +0.0f && v_mm512_setzero[7] == +0.0f && v_mm512_setzero[8] == +0.0f && v_mm512_setzero[9] == +0.0f && v_mm512_setzero[10] == +0.0f && v_mm512_setzero[11] == +0.0f && v_mm512_setzero[12] == +0.0f && v_mm512_setzero[13] == +0.0f && v_mm512_setzero[14] == +0.0f && v_mm512_setzero[15] == +0.0f); - - constexpr __m512 v_mm512_setzero_ps = _mm512_setzero_ps(); - static_assert(v_mm512_setzero_ps[0] == +0.0f && v_mm512_setzero_ps[1] == +0.0f && v_mm512_setzero_ps[2] == +0.0f && v_mm512_setzero_ps[3] == +0.0f && v_mm512_setzero_ps[4] == +0.0f && v_mm512_setzero_ps[5] == +0.0f && v_mm512_setzero_ps[6] == +0.0f && v_mm512_setzero_ps[7] == +0.0f && v_mm512_setzero_ps[8] == +0.0f && v_mm512_setzero_ps[9] == +0.0f && v_mm512_setzero_ps[10] == +0.0f && v_mm512_setzero_ps[11] == +0.0f && v_mm512_setzero_ps[12] == +0.0f && v_mm512_setzero_ps[13] == +0.0f && v_mm512_setzero_ps[14] == +0.0f && v_mm512_setzero_ps[15] == +0.0f); - - constexpr __m512d v_mm512_setzero_pd = _mm512_setzero_pd(); - static_assert(v_mm512_setzero_pd[0] == +0.0 && v_mm512_setzero_pd[1] == +0.0 && v_mm512_setzero_pd[2] == +0.0 && v_mm512_setzero_pd[3] == +0.0 && v_mm512_setzero_pd[4] == +0.0 && v_mm512_setzero_pd[5] == +0.0 && v_mm512_setzero_pd[6] == +0.0 && v_mm512_setzero_pd[7] == +0.0); - - constexpr __m512i v_mm512_setzero_si512 = _mm512_setzero_si512(); - static_assert(v_mm512_setzero_si512[0] == 0x0000000000000000ULL && v_mm512_setzero_si512[1] == 0x0000000000000000ULL && v_mm512_setzero_si512[2] == 0x0000000000000000ULL && v_mm512_setzero_si512[3] == 0x0000000000000000ULL && v_mm512_setzero_si512[4] == 0x0000000000000000ULL && v_mm512_setzero_si512[5] == 0x0000000000000000ULL && v_mm512_setzero_si512[6] == 0x0000000000000000ULL && v_mm512_setzero_si512[7] == 0x0000000000000000ULL); - - constexpr __m512i v_mm512_setzero_epi32 = _mm512_setzero_epi32(); - static_assert(v_mm512_setzero_epi32[0] == 0x0000000000000000ULL && v_mm512_setzero_epi32[1] == 0x0000000000000000ULL && v_mm512_setzero_epi32[2] == 0x0000000000000000ULL && v_mm512_setzero_epi32[3] == 0x0000000000000000ULL && v_mm512_setzero_epi32[4] == 0x0000000000000000ULL && v_mm512_setzero_epi32[5] == 0x0000000000000000ULL && v_mm512_setzero_epi32[6] == 0x0000000000000000ULL && v_mm512_setzero_epi32[7] == 0x0000000000000000ULL); -} - -#endif diff --git a/clang/test/CodeGen/X86/builtin_test_helpers.h b/clang/test/CodeGen/X86/builtin_test_helpers.h index 043b6ecbc69f18..01800db33afbb9 100644 --- a/clang/test/CodeGen/X86/builtin_test_helpers.h +++ b/clang/test/CodeGen/X86/builtin_test_helpers.h @@ -4,16 +4,59 @@ #if defined(__cplusplus) && (__cplusplus >= 201103L) -constexpr bool match_m128(__m128 v, float x, float y, float z, float w) { - return v[0] == x && v[1] == y && v[2] == z && v[3] == w; +constexpr bool match_m128(__m128 v, float a, float b, float c, float d) { + return v[0] == a && v[1] == b && v[2] == c && v[3] == d; } -constexpr bool match_m128d(__m128d v, double x, double y) { - return v[0] == x && v[1] == y; +constexpr bool match_m128d(__m128d v, double a, double b) { + return v[0] == a && v[1] == b; } -constexpr bool match_m128i(__m128i v, unsigned long long x, unsigned long long y) { - return v[0] == x && v[1] == y; +constexpr bool match_m128i(__m128i v, unsigned long long a, unsigned long long b) { + return v[0] == a && v[1] == b; +} + +constexpr bool match_v2di(__m128i v, long long a, long long b) { + return v[0] == a && v[1] == b; +} + +constexpr bool match_v4si(__m128i _v, int a, int b, int c, int d) { + __v4si v = (__v4si)_v; + return v[0] == a && v[1] == b && v[2] == c && v[3] == d; +} + +constexpr bool match_v8hi(__m128i _v, short a, short b, short c, short d, short e, short f, short g, short h) { + __v8hi v = (__v8hi)_v; + return v[0] == a && v[1] == b && v[2] == c && v[3] == d && v[4] == e && v[5] == f && v[6] == g && v[7] == h; +} + +constexpr bool match_v16qi(__m128i _v, char a, char b, char c, char d, char e, char f, char g, char h, char i, char j, char k, char l, char m, char n, char o, char p) { + __v16qi v = (__v16qi)_v; + return v[0] == a && v[1] == b && v[2] == c && v[3] == d && v[4] == e && v[5] == f && v[6] == g && v[7] == h && v[8] == i && v[9] == j && v[10] == k && v[11] == l && v[12] == m && v[13] == n && v[14] == o && v[15] == p; +} + +constexpr bool match_m256(__m256 v, float a, float b, float c, float d, float e, float f, float g, float h) { + return v[0] == a && v[1] == b && v[2] == c && v[3] == d && v[4] == e && v[5] == f && v[6] == g && v[7] == h; +} + +constexpr bool match_m256d(__m256d v, double a, double b, double c, double d) { + return v[0] == a && v[1] == b && v[2] == c && v[3] == d; +} + +constexpr bool match_m256i(__m256i v, unsigned long long a, unsigned long long b, unsigned long long c, unsigned long long d) { + return v[0] == a && v[1] == b && v[2] == c && v[3] == d; +} + +constexpr bool match_m512(__m512 v, float a, float b, float c, float d, float e, float f, float g, float h, float i, float j, float k, float l, float m, float n, float o, float p) { + return v[0] == a && v[1] == b && v[2] == c && v[3] == d && v[4] == e && v[5] == f && v[6] == g && v[7] == h && v[8] == i && v[9] == j && v[10] == k && v[11] == l && v[12] == m && v[13] == n && v[14] == o && v[15] == p; +} + +constexpr bool match_m512d(__m512d v, double a, double b, double c, double d, double e, double f, double g, double h) { + return v[0] == a && v[1] == b && v[2] == c && v[3] == d && v[4] == e && v[5] == f && v[6] == g && v[7] == h; +} + +constexpr bool match_m512i(__m512i v, unsigned long long a, unsigned long long b, unsigned long long c, unsigned long long d, unsigned long long e, unsigned long long f, unsigned long long g, unsigned long long h) { + return v[0] == a && v[1] == b && v[2] == c && v[3] == d && v[4] == e && v[5] == f && v[6] == g && v[7] == h; } #define TEST_CONSTEXPR(...) static_assert(__VA_ARGS__) @@ -22,4 +65,4 @@ constexpr bool match_m128i(__m128i v, unsigned long long x, unsigned long long y #define TEST_CONSTEXPR(...) -#endif \ No newline at end of file +#endif diff --git a/clang/test/CodeGen/X86/sse2-builtins.c b/clang/test/CodeGen/X86/sse2-builtins.c index 4287d3d4b5ec4e..c4493a49120543 100644 --- a/clang/test/CodeGen/X86/sse2-builtins.c +++ b/clang/test/CodeGen/X86/sse2-builtins.c @@ -32,12 +32,14 @@ __m128i test_mm_add_epi32(__m128i A, __m128i B) { // CHECK: add <4 x i32> return _mm_add_epi32(A, B); } +TEST_CONSTEXPR(match_v4si(_mm_add_epi32((__m128i)(__v4si){+1, -2, +3, -4}, (__m128i)(__v4si){-10, +8, +6, -4}), -9, +6, +9, -8)); __m128i test_mm_add_epi64(__m128i A, __m128i B) { // CHECK-LABEL: test_mm_add_epi64 // CHECK: add <2 x i64> return _mm_add_epi64(A, B); } +TEST_CONSTEXPR(match_v2di(_mm_add_epi64((__m128i)(__v2di){+5, -3}, (__m128i)(__v2di){-9, +8}), -4, +5)); __m128d test_mm_add_pd(__m128d A, __m128d B) { // CHECK-LABEL: test_mm_add_pd @@ -1011,6 +1013,7 @@ __m128i test_mm_set_epi8(char A, char B, char C, char D, // CHECK: insertelement <16 x i8> %{{.*}}, i8 %{{.*}}, i32 15 return _mm_set_epi8(A, B, C, D, E, F, G, H, I, J, K, L, M, N, O, P); } +TEST_CONSTEXPR(match_v16qi(_mm_set_epi8(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15), 15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0)); __m128i test_mm_set_epi16(short A, short B, short C, short D, short E, short F, short G, short H) { @@ -1025,6 +1028,7 @@ __m128i test_mm_set_epi16(short A, short B, short C, short D, // CHECK: insertelement <8 x i16> %{{.*}}, i16 %{{.*}}, i32 7 return _mm_set_epi16(A, B, C, D, E, F, G, H); } +TEST_CONSTEXPR(match_v8hi(_mm_set_epi16(0, -1, -2, -3, -4, -5, -6, -7), -7, -6, -5, -4, -3, -2, -1, 0)); __m128i test_mm_set_epi32(int A, int B, int C, int D) { // CHECK-LABEL: test_mm_set_epi32 @@ -1034,6 +1038,7 @@ __m128i test_mm_set_epi32(int A, int B, int C, int D) { // CHECK: insertelement <4 x i32> %{{.*}}, i32 %{{.*}}, i32 3 return _mm_set_epi32(A, B, C, D); } +TEST_CONSTEXPR(match_v4si(_mm_set_epi32(1, -3, 5, -7), -7, 5, -3, 1)); __m128i test_mm_set_epi64(__m64 A, __m64 B) { // CHECK-LABEL: test_mm_set_epi64 @@ -1041,6 +1046,7 @@ __m128i test_mm_set_epi64(__m64 A, __m64 B) { // CHECK: insertelement <2 x i64> %{{.*}}, i64 %{{.*}}, i32 1 return _mm_set_epi64(A, B); } +TEST_CONSTEXPR(match_v2di(_mm_set_epi64((__m64){-1}, (__m64){42}), 42, -1)); __m128i test_mm_set_epi64x(long long A, long long B) { // CHECK-LABEL: test_mm_set_epi64x @@ -1048,6 +1054,7 @@ __m128i test_mm_set_epi64x(long long A, long long B) { // CHECK: insertelement <2 x i64> %{{.*}}, i64 %{{.*}}, i32 1 return _mm_set_epi64x(A, B); } +TEST_CONSTEXPR(match_v2di(_mm_set_epi64x(100, -1000), -1000, 100)); __m128d test_mm_set_pd(double A, double B) { // CHECK-LABEL: test_mm_set_pd @@ -1093,6 +1100,7 @@ __m128i test_mm_set1_epi8(char A) { // CHECK: insertelement <16 x i8> %{{.*}}, i8 %{{.*}}, i32 15 return _mm_set1_epi8(A); } +TEST_CONSTEXPR(match_v16qi(_mm_set1_epi8(99), 99, 99, 99, 99, 99, 99, 99, 99, 99, 99, 99, 99, 99, 99, 99, 99)); __m128i test_mm_set1_epi16(short A) { // CHECK-LABEL: test_mm_set1_epi16 @@ -1106,6 +1114,7 @@ __m128i test_mm_set1_epi16(short A) { // CHECK: insertelement <8 x i16> %{{.*}}, i16 %{{.*}}, i32 7 return _mm_set1_epi16(A); } +TEST_CONSTEXPR(match_v8hi(_mm_set1_epi16(-128), -128, -128, -128, -128, -128, -128, -128, -128)); __m128i test_mm_set1_epi32(int A) { // CHECK-LABEL: test_mm_set1_epi32 @@ -1115,6 +1124,7 @@ __m128i test_mm_set1_epi32(int A) { // CHECK: insertelement <4 x i32> %{{.*}}, i32 %{{.*}}, i32 3 return _mm_set1_epi32(A); } +TEST_CONSTEXPR(match_v4si(_mm_set1_epi32(55), 55, 55, 55, 55)); __m128i test_mm_set1_epi64(__m64 A) { // CHECK-LABEL: test_mm_set1_epi64 @@ -1122,6 +1132,7 @@ __m128i test_mm_set1_epi64(__m64 A) { // CHECK: insertelement <2 x i64> %{{.*}}, i64 %{{.*}}, i32 1 return _mm_set1_epi64(A); } +TEST_CONSTEXPR(match_v2di(_mm_set1_epi64((__m64){-65535}), -65535, -65535)); __m128i test_mm_set1_epi64x(long long A) { // CHECK-LABEL: test_mm_set1_epi64x @@ -1129,6 +1140,7 @@ __m128i test_mm_set1_epi64x(long long A) { // CHECK: insertelement <2 x i64> %{{.*}}, i64 %{{.*}}, i32 1 return _mm_set1_epi64x(A); } +TEST_CONSTEXPR(match_v2di(_mm_set1_epi64x(65536), 65536, 65536)); __m128d test_mm_set1_pd(double A) { // CHECK-LABEL: test_mm_set1_pd @@ -1161,6 +1173,7 @@ __m128i test_mm_setr_epi8(char A, char B, char C, char D, // CHECK: insertelement <16 x i8> %{{.*}}, i8 %{{.*}}, i32 15 return _mm_setr_epi8(A, B, C, D, E, F, G, H, I, J, K, L, M, N, O, P); } +TEST_CONSTEXPR(match_v16qi(_mm_setr_epi8(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15), 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15)); __m128i test_mm_setr_epi16(short A, short B, short C, short D, short E, short F, short G, short H) { @@ -1175,6 +1188,7 @@ __m128i test_mm_setr_epi16(short A, short B, short C, short D, // CHECK: insertelement <8 x i16> %{{.*}}, i16 %{{.*}}, i32 7 return _mm_setr_epi16(A, B, C, D, E, F, G, H); } +TEST_CONSTEXPR(match_v8hi(_mm_setr_epi16(0, -1, -2, -3, -4, -5, -6, -7), 0, -1, -2, -3, -4, -5, -6, -7)); __m128i test_mm_setr_epi32(int A, int B, int C, int D) { // CHECK-LABEL: test_mm_setr_epi32 @@ -1184,6 +1198,7 @@ __m128i test_mm_setr_epi32(int A, int B, int C, int D) { // CHECK: insertelement <4 x i32> %{{.*}}, i32 %{{.*}}, i32 3 return _mm_setr_epi32(A, B, C, D); } +TEST_CONSTEXPR(match_v4si(_mm_setr_epi32(1, -3, 5, -7), 1, -3, 5, -7)); __m128i test_mm_setr_epi64(__m64 A, __m64 B) { // CHECK-LABEL: test_mm_setr_epi64 @@ -1191,6 +1206,7 @@ __m128i test_mm_setr_epi64(__m64 A, __m64 B) { // CHECK: insertelement <2 x i64> %{{.*}}, i64 %{{.*}}, i32 1 return _mm_setr_epi64(A, B); } +TEST_CONSTEXPR(match_v2di(_mm_setr_epi64((__m64){-1}, (__m64){42}), -1, 42)); __m128d test_mm_setr_pd(double A, double B) { // CHECK-LABEL: test_mm_setr_pd @@ -1634,12 +1650,14 @@ __m128i test_mm_sub_epi32(__m128i A, __m128i B) { // CHECK: sub <4 x i32> return _mm_sub_epi32(A, B); } +TEST_CONSTEXPR(match_v4si(_mm_sub_epi32((__m128i)(__v4si){+1, -2, +3, -4}, (__m128i)(__v4si){-10, +8, +6, -4}), +11, -10, -3, 0)); __m128i test_mm_sub_epi64(__m128i A, __m128i B) { // CHECK-LABEL: test_mm_sub_epi64 // CHECK: sub <2 x i64> return _mm_sub_epi64(A, B); } +TEST_CONSTEXPR(match_v2di(_mm_sub_epi64((__m128i)(__v2di){+5, -3}, (__m128i)(__v2di){-9, +8}), +14, -11)); __m128d test_mm_sub_pd(__m128d A, __m128d B) { // CHECK-LABEL: test_mm_sub_pd diff --git a/clang/test/CodeGen/aarch64-cpu-supports-target.c b/clang/test/CodeGen/aarch64-cpu-supports-target.c index 5186cab92a921d..e3a75e9a1fc7d3 100644 --- a/clang/test/CodeGen/aarch64-cpu-supports-target.c +++ b/clang/test/CodeGen/aarch64-cpu-supports-target.c @@ -9,9 +9,9 @@ int check_all_feature() { return 3; else if (__builtin_cpu_supports("fcma+rcpc+rcpc2+rcpc3+frintts+dgh")) return 4; - else if (__builtin_cpu_supports("i8mm+bf16+ebf16+rpres+sve+sve-bf16")) + else if (__builtin_cpu_supports("i8mm+bf16+ebf16+rpres+sve")) return 5; - else if (__builtin_cpu_supports("sve-ebf16+sve-i8mm+f32mm+f64mm")) + else if (__builtin_cpu_supports("sve+ebf16+i8mm+f32mm+f64mm")) return 6; else if (__builtin_cpu_supports("sve2+sve2-aes+sve2-pmull128")) return 7; diff --git a/clang/test/CodeGen/aarch64-fmv-dependencies.c b/clang/test/CodeGen/aarch64-fmv-dependencies.c index 6d230007f91ff9..db6be423b99f78 100644 --- a/clang/test/CodeGen/aarch64-fmv-dependencies.c +++ b/clang/test/CodeGen/aarch64-fmv-dependencies.c @@ -135,15 +135,6 @@ __attribute__((target_version("ssbs"))) int fmv(void) { return 0; } // CHECK: define dso_local i32 @fmv._Msve() #[[sve:[0-9]+]] { __attribute__((target_version("sve"))) int fmv(void) { return 0; } -// CHECK: define dso_local i32 @fmv._Msve-bf16() #[[sve_bf16_ebf16:[0-9]+]] { -__attribute__((target_version("sve-bf16"))) int fmv(void) { return 0; } - -// CHECK: define dso_local i32 @fmv._Msve-ebf16() #[[sve_bf16_ebf16:[0-9]+]] { -__attribute__((target_version("sve-ebf16"))) int fmv(void) { return 0; } - -// CHECK: define dso_local i32 @fmv._Msve-i8mm() #[[sve_i8mm:[0-9]+]] { -__attribute__((target_version("sve-i8mm"))) int fmv(void) { return 0; } - // CHECK: define dso_local i32 @fmv._Msve2() #[[sve2:[0-9]+]] { __attribute__((target_version("sve2"))) int fmv(void) { return 0; } @@ -209,8 +200,6 @@ int caller() { // CHECK: attributes #[[sme2]] = { {{.*}} "target-features"="+bf16,+fp-armv8,+neon,+outline-atomics,+sme,+sme2,+v8a" // CHECK: attributes #[[ssbs]] = { {{.*}} "target-features"="+fp-armv8,+neon,+outline-atomics,+ssbs,+v8a" // CHECK: attributes #[[sve]] = { {{.*}} "target-features"="+fp-armv8,+fullfp16,+neon,+outline-atomics,+sve,+v8a" -// CHECK: attributes #[[sve_bf16_ebf16]] = { {{.*}} "target-features"="+bf16,+fp-armv8,+fullfp16,+neon,+outline-atomics,+sve,+v8a" -// CHECK: attributes #[[sve_i8mm]] = { {{.*}} "target-features"="+fp-armv8,+fullfp16,+i8mm,+neon,+outline-atomics,+sve,+v8a" // CHECK: attributes #[[sve2]] = { {{.*}} "target-features"="+fp-armv8,+fullfp16,+neon,+outline-atomics,+sve,+sve2,+v8a" // CHECK: attributes #[[sve2_aes]] = { {{.*}} "target-features"="+aes,+fp-armv8,+fullfp16,+neon,+outline-atomics,+sve,+sve2,+sve2-aes,+v8a" // CHECK: attributes #[[sve2_bitperm]] = { {{.*}} "target-features"="+fp-armv8,+fullfp16,+neon,+outline-atomics,+sve,+sve2,+sve2-bitperm,+v8a" diff --git a/clang/test/CodeGen/attr-target-version.c b/clang/test/CodeGen/attr-target-version.c index dc0cc429abffd1..cd09e05b25e4cd 100644 --- a/clang/test/CodeGen/attr-target-version.c +++ b/clang/test/CodeGen/attr-target-version.c @@ -27,11 +27,11 @@ int foo() { inline int __attribute__((target_version("sha2+aes+f64mm"))) fmv_inline(void) { return 1; } inline int __attribute__((target_version("fp16+fcma+rdma+sme+ fp16 "))) fmv_inline(void) { return 2; } inline int __attribute__((target_version("sha3+i8mm+f32mm"))) fmv_inline(void) { return 12; } -inline int __attribute__((target_version("dit+sve-ebf16"))) fmv_inline(void) { return 8; } +inline int __attribute__((target_version("dit+ebf16"))) fmv_inline(void) { return 8; } inline int __attribute__((target_version("dpb+rcpc2 "))) fmv_inline(void) { return 6; } inline int __attribute__((target_version(" dpb2 + jscvt"))) fmv_inline(void) { return 7; } inline int __attribute__((target_version("rcpc+frintts"))) fmv_inline(void) { return 3; } -inline int __attribute__((target_version("sve+sve-bf16"))) fmv_inline(void) { return 4; } +inline int __attribute__((target_version("sve+bf16"))) fmv_inline(void) { return 4; } inline int __attribute__((target_version("sve2-aes+sve2-sha3"))) fmv_inline(void) { return 5; } inline int __attribute__((target_version("sve2+sve2-aes+sve2-bitperm"))) fmv_inline(void) { return 9; } inline int __attribute__((target_version("sve2-sm4+memtag"))) fmv_inline(void) { return 10; } @@ -680,7 +680,7 @@ int caller(void) { return used_def_without_default_decl() + used_decl_without_de // // // CHECK: Function Attrs: noinline nounwind optnone -// CHECK-LABEL: define {{[^@]+}}@fmv_inline._MditMsve-ebf16 +// CHECK-LABEL: define {{[^@]+}}@fmv_inline._MditMebf16 // CHECK-SAME: () #[[ATTR28:[0-9]+]] { // CHECK-NEXT: entry: // CHECK-NEXT: ret i32 8 @@ -708,7 +708,7 @@ int caller(void) { return used_def_without_default_decl() + used_decl_without_de // // // CHECK: Function Attrs: noinline nounwind optnone -// CHECK-LABEL: define {{[^@]+}}@fmv_inline._MsveMsve-bf16 +// CHECK-LABEL: define {{[^@]+}}@fmv_inline._Mbf16Msve // CHECK-SAME: () #[[ATTR32:[0-9]+]] { // CHECK-NEXT: entry: // CHECK-NEXT: ret i32 4 @@ -837,20 +837,20 @@ int caller(void) { return used_def_without_default_decl() + used_decl_without_de // CHECK-NEXT: ret ptr @fmv_inline._Msve2-aesMsve2-sha3 // CHECK: resolver_else12: // CHECK-NEXT: [[TMP28:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8 -// CHECK-NEXT: [[TMP29:%.*]] = and i64 [[TMP28]], 4295098368 -// CHECK-NEXT: [[TMP30:%.*]] = icmp eq i64 [[TMP29]], 4295098368 +// CHECK-NEXT: [[TMP29:%.*]] = and i64 [[TMP28]], 1207959552 +// CHECK-NEXT: [[TMP30:%.*]] = icmp eq i64 [[TMP29]], 1207959552 // CHECK-NEXT: [[TMP31:%.*]] = and i1 true, [[TMP30]] // CHECK-NEXT: br i1 [[TMP31]], label [[RESOLVER_RETURN13:%.*]], label [[RESOLVER_ELSE14:%.*]] // CHECK: resolver_return13: -// CHECK-NEXT: ret ptr @fmv_inline._MditMsve-ebf16 +// CHECK-NEXT: ret ptr @fmv_inline._Mbf16Msve // CHECK: resolver_else14: // CHECK-NEXT: [[TMP32:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8 -// CHECK-NEXT: [[TMP33:%.*]] = and i64 [[TMP32]], 3221225472 -// CHECK-NEXT: [[TMP34:%.*]] = icmp eq i64 [[TMP33]], 3221225472 +// CHECK-NEXT: [[TMP33:%.*]] = and i64 [[TMP32]], 268566528 +// CHECK-NEXT: [[TMP34:%.*]] = icmp eq i64 [[TMP33]], 268566528 // CHECK-NEXT: [[TMP35:%.*]] = and i1 true, [[TMP34]] // CHECK-NEXT: br i1 [[TMP35]], label [[RESOLVER_RETURN15:%.*]], label [[RESOLVER_ELSE16:%.*]] // CHECK: resolver_return15: -// CHECK-NEXT: ret ptr @fmv_inline._MsveMsve-bf16 +// CHECK-NEXT: ret ptr @fmv_inline._MditMebf16 // CHECK: resolver_else16: // CHECK-NEXT: [[TMP36:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8 // CHECK-NEXT: [[TMP37:%.*]] = and i64 [[TMP36]], 20971520 diff --git a/clang/test/CodeGen/pgo-cold-function-coverage.c b/clang/test/CodeGen/pgo-cold-function-coverage.c index fd1e1e7e14cda5..3003cdc3e15e02 100644 --- a/clang/test/CodeGen/pgo-cold-function-coverage.c +++ b/clang/test/CodeGen/pgo-cold-function-coverage.c @@ -1,7 +1,7 @@ // Test -fprofile-generate-cold-function-coverage // RUN: rm -rf %t && split-file %s %t -// RUN: %clang -O2 -fprofile-generate-cold-function-coverage=/xxx/yyy/ -fprofile-sample-accurate -fprofile-sample-use=%t/pgo-cold-func.prof -S -emit-llvm -o - %t/pgo-cold-func.c | FileCheck %s +// RUN: %clang --target=x86_64 -O2 -fprofile-generate-cold-function-coverage=/xxx/yyy/ -fprofile-sample-accurate -fprofile-sample-use=%t/pgo-cold-func.prof -S -emit-llvm -o - %t/pgo-cold-func.c | FileCheck %s // CHECK: @__llvm_profile_filename = {{.*}} c"/xxx/yyy/default_%m.profraw\00" diff --git a/clang/test/CodeGenHLSL/builtins/countbits.hlsl b/clang/test/CodeGenHLSL/builtins/countbits.hlsl index 8dfe977bfae626..218d8dcd10f8d7 100644 --- a/clang/test/CodeGenHLSL/builtins/countbits.hlsl +++ b/clang/test/CodeGenHLSL/builtins/countbits.hlsl @@ -4,26 +4,37 @@ #ifdef __HLSL_ENABLE_16_BIT // CHECK-LABEL: test_countbits_ushort -// CHECK: call i16 @llvm.ctpop.i16 -uint16_t test_countbits_ushort(uint16_t p0) +// CHECK: [[A:%.*]] = call i16 @llvm.ctpop.i16 +// CHECK-NEXT: zext i16 [[A]] to i32 +uint test_countbits_ushort(uint16_t p0) +{ + return countbits(p0); +} +// CHECK-LABEL: test_countbits_short +// CHECK: [[A:%.*]] = call i16 @llvm.ctpop.i16 +// CHECK-NEXT: sext i16 [[A]] to i32 +uint test_countbits_short(int16_t p0) { return countbits(p0); } // CHECK-LABEL: test_countbits_ushort2 -// CHECK: call <2 x i16> @llvm.ctpop.v2i16 -uint16_t2 test_countbits_ushort2(uint16_t2 p0) +// CHECK: [[A:%.*]] = call <2 x i16> @llvm.ctpop.v2i16 +// CHECK-NEXT: zext <2 x i16> [[A]] to <2 x i32> +uint2 test_countbits_ushort2(uint16_t2 p0) { return countbits(p0); } // CHECK-LABEL: test_countbits_ushort3 -// CHECK: call <3 x i16> @llvm.ctpop.v3i16 -uint16_t3 test_countbits_ushort3(uint16_t3 p0) +// CHECK: [[A:%.*]] = call <3 x i16> @llvm.ctpop.v3i16 +// CHECK-NEXT: zext <3 x i16> [[A]] to <3 x i32> +uint3 test_countbits_ushort3(uint16_t3 p0) { return countbits(p0); } // CHECK-LABEL: test_countbits_ushort4 -// CHECK: call <4 x i16> @llvm.ctpop.v4i16 -uint16_t4 test_countbits_ushort4(uint16_t4 p0) +// CHECK: [[A:%.*]] = call <4 x i16> @llvm.ctpop.v4i16 +// CHECK-NEXT: zext <4 x i16> [[A]] to <4 x i32> +uint4 test_countbits_ushort4(uint16_t4 p0) { return countbits(p0); } @@ -31,7 +42,13 @@ uint16_t4 test_countbits_ushort4(uint16_t4 p0) // CHECK-LABEL: test_countbits_uint // CHECK: call i32 @llvm.ctpop.i32 -int test_countbits_uint(uint p0) +uint test_countbits_uint(uint p0) +{ + return countbits(p0); +} +// CHECK-LABEL: test_countbits_int +// CHECK: call i32 @llvm.ctpop.i32 +uint test_countbits_int(int p0) { return countbits(p0); } @@ -55,26 +72,37 @@ uint4 test_countbits_uint4(uint4 p0) } // CHECK-LABEL: test_countbits_long -// CHECK: call i64 @llvm.ctpop.i64 -uint64_t test_countbits_long(uint64_t p0) +// CHECK: [[A:%.*]] = call i64 @llvm.ctpop.i64 +// CHECK-NEXT: trunc i64 [[A]] to i32 +uint test_countbits_long(uint64_t p0) +{ + return countbits(p0); +} +// CHECK-LABEL: test_countbits_slong +// CHECK: [[A:%.*]] = call i64 @llvm.ctpop.i64 +// CHECK-NEXT: trunc i64 [[A]] to i32 +uint test_countbits_slong(int64_t p0) { return countbits(p0); } // CHECK-LABEL: test_countbits_long2 -// CHECK: call <2 x i64> @llvm.ctpop.v2i64 -uint64_t2 test_countbits_long2(uint64_t2 p0) +// CHECK: [[A:%.*]] = call <2 x i64> @llvm.ctpop.v2i64 +// CHECK-NEXT: trunc <2 x i64> [[A]] to <2 x i32> +uint2 test_countbits_long2(uint64_t2 p0) { return countbits(p0); } // CHECK-LABEL: test_countbits_long3 -// CHECK: call <3 x i64> @llvm.ctpop.v3i64 -uint64_t3 test_countbits_long3(uint64_t3 p0) +// CHECK: [[A:%.*]] = call <3 x i64> @llvm.ctpop.v3i64 +// CHECK-NEXT: trunc <3 x i64> [[A]] to <3 x i32> +uint3 test_countbits_long3(uint64_t3 p0) { return countbits(p0); } // CHECK-LABEL: test_countbits_long4 -// CHECK: call <4 x i64> @llvm.ctpop.v4i64 -uint64_t4 test_countbits_long4(uint64_t4 p0) +// CHECK: [[A:%.*]] = call <4 x i64> @llvm.ctpop.v4i64 +// CHECK-NEXT: trunc <4 x i64> [[A]] to <4 x i32> +uint4 test_countbits_long4(uint64_t4 p0) { return countbits(p0); } diff --git a/clang/test/CodeGenOpenCLCXX/local_addrspace_init.clcpp b/clang/test/CodeGenOpenCLCXX/local_addrspace_init.clcpp index bb9acf09d120be..0a6462e4262413 100644 --- a/clang/test/CodeGenOpenCLCXX/local_addrspace_init.clcpp +++ b/clang/test/CodeGenOpenCLCXX/local_addrspace_init.clcpp @@ -14,7 +14,7 @@ kernel void test() { // address space variables. User defined initialization could // make sense, but would it mean that all work items need to // execute it? Potentially disallowing any initialization would - // make things easier and assingments can be used to set specific + // make things easier and assignments can be used to set specific // values. This rules should make it consistent with OpenCL C. //__local C c(); } diff --git a/clang/test/Driver/XRay/xray-shared.cpp b/clang/test/Driver/XRay/xray-shared.cpp index 215854e1fc7cef..e331fefed1e0c9 100644 --- a/clang/test/Driver/XRay/xray-shared.cpp +++ b/clang/test/Driver/XRay/xray-shared.cpp @@ -1,6 +1,5 @@ // RUN: %clang -### --target=x86_64-unknown-linux-gnu -fPIC -fxray-instrument -fxray-shared -c %s -o /dev/null 2>&1 | FileCheck %s // RUN: %clang -### --target=x86_64-unknown-linux-gnu -fpic -fxray-instrument -fxray-shared -c %s -o /dev/null 2>&1 | FileCheck %s -// RUN: %clang -### --target=x86_64-unknown-linux-gnu -fxray-instrument -fxray-shared -c %s -o /dev/null 2>&1 | FileCheck %s // RUN: not %clang -### --target=x86_64-unknown-linux-gnu -fno-PIC -fxray-instrument -fxray-shared -c %s -o /dev/null 2>&1 | FileCheck %s --check-prefix=ERR-PIC // RUN: not %clang -### --target=x86_64-unknown-linux-gnu -fno-pic -fxray-instrument -fxray-shared -c %s -o /dev/null 2>&1 | FileCheck %s --check-prefix=ERR-PIC diff --git a/clang/test/Driver/nvlink-wrapper.c b/clang/test/Driver/nvlink-wrapper.c index 2b0993caee4248..79f4a6641732f7 100644 --- a/clang/test/Driver/nvlink-wrapper.c +++ b/clang/test/Driver/nvlink-wrapper.c @@ -21,12 +21,13 @@ int bar() { } #else extern int y; -int __attribute__((visibility("hidden"))) x = 999; +extern int x; int baz() { return y + x; } #endif // Create various inputs to test basic linking and LTO capabilities. Creating a // CUDA binary requires access to the `ptxas` executable, so we just use x64. +// RUN: %clang -cc1 %s -triple nvptx64-nvidia-cuda -emit-llvm-bc -o %t.o // RUN: %clang -cc1 %s -triple x86_64-unknown-linux-gnu -emit-obj -DX -o %t-x.o // RUN: %clang -cc1 %s -triple x86_64-unknown-linux-gnu -emit-obj -DY -o %t-y.o // RUN: %clang -cc1 %s -triple x86_64-unknown-linux-gnu -emit-obj -DZ -o %t-z.o @@ -36,6 +37,7 @@ int baz() { return y + x; } // RUN: llvm-ar rcs %t-y.a %t-y.o // RUN: llvm-ar rcs %t-z.a %t-z.o // RUN: llvm-ar rcs %t-w.a %t-w.o +// RUN: llvm-ar rcs %t-u.a %t-u.o // // Check that we forward any unrecognized argument to 'nvlink'. @@ -49,11 +51,16 @@ int baz() { return y + x; } // `libx.a` and `liby.a` because extern weak symbols do not extract and `libz.a` // is not used at all. // -// RUN: clang-nvlink-wrapper --dry-run %t-x.a %t-u.o %t-y.a %t-z.a %t-w.a \ +// RUN: clang-nvlink-wrapper --dry-run %t-x.a %t-u.a %t-y.a %t-z.a %t-w.a %t.o \ // RUN: -arch sm_52 -o a.out 2>&1 | FileCheck %s --check-prefix=LINK // LINK: nvlink{{.*}} -arch sm_52 -o a.out [[INPUT:.+]].cubin {{.*}}-x-{{.*}}.cubin{{.*}}-y-{{.*}}.cubin -// RUN: %clang -cc1 %s -triple nvptx64-nvidia-cuda -emit-llvm-bc -o %t.o +// +// Same as above but we use '--undefined' to forcibly extract 'libz.a' +// +// RUN: clang-nvlink-wrapper --dry-run %t-x.a %t-u.a %t-y.a %t-z.a %t-w.a %t.o \ +// RUN: -u z -arch sm_52 -o a.out 2>&1 | FileCheck %s --check-prefix=LINK +// UNDEFINED: nvlink{{.*}} -arch sm_52 -o a.out [[INPUT:.+]].cubin {{.*}}-x-{{.*}}.cubin{{.*}}-y-{{.*}}.cubin{{.*}}-z-{{.*}}.cubin // // Check that the LTO interface works and properly preserves symbols used in a diff --git a/clang/test/Driver/riscv-profiles.c b/clang/test/Driver/riscv-profiles.c index 2b4d19422874cf..67e09d0e69ebc3 100644 --- a/clang/test/Driver/riscv-profiles.c +++ b/clang/test/Driver/riscv-profiles.c @@ -147,6 +147,7 @@ // RVA23U64: "-target-feature" "+zvbb" // RVA23U64: "-target-feature" "+zvfhmin" // RVA23U64: "-target-feature" "+zvkt" +// RVA23U64: "-target-feature" "+supm" // RUN: %clang --target=riscv64 -### -c %s 2>&1 -march=rva23s64 \ // RUN: | FileCheck -check-prefix=RVA23S64 %s @@ -186,6 +187,7 @@ // RVA23S64: "-target-feature" "+zvbb" // RVA23S64: "-target-feature" "+zvfhmin" // RVA23S64: "-target-feature" "+zvkt" +// RVA23S64: "-target-feature" "+sha" // RVA23S64: "-target-feature" "+shcounterenw" // RVA23S64: "-target-feature" "+shgatpa" // RVA23S64: "-target-feature" "+shtvala" @@ -201,6 +203,7 @@ // RVA23S64: "-target-feature" "+sstvala" // RVA23S64: "-target-feature" "+sstvecd" // RVA23S64: "-target-feature" "+ssu64xl" +// RVA23S64: "-target-feature" "+supm" // RVA23S64: "-target-feature" "+svade" // RVA23S64: "-target-feature" "+svbare" // RVA23S64: "-target-feature" "+svinval" diff --git a/clang/test/Modules/static-initializer.cppm b/clang/test/Modules/static-initializer.cppm new file mode 100644 index 00000000000000..10d4854ee67fa6 --- /dev/null +++ b/clang/test/Modules/static-initializer.cppm @@ -0,0 +1,18 @@ +// RUN: rm -rf %t +// RUN: mkdir -p %t +// RUN: split-file %s %t +// +// RUN: %clang_cc1 -triple %itanium_abi_triple -std=c++20 %t/a.cppm -emit-module-interface -o %t/a.pcm +// RUN: %clang_cc1 -triple %itanium_abi_triple -std=c++20 %t/a.cpp -fmodule-file=a=%t/a.pcm -emit-llvm -o - | FileCheck %t/a.cpp + +//--- a.cppm +export module a; +int func(); +static int a = func(); + +//--- a.cpp +import a; + +// CHECK-NOT: internal global +// CHECK-NOT: __cxx_global_var_init + diff --git a/clang/test/Sema/attr-target-clones-aarch64.c b/clang/test/Sema/attr-target-clones-aarch64.c index a723c5965c5bcd..e101fefd2b67c4 100644 --- a/clang/test/Sema/attr-target-clones-aarch64.c +++ b/clang/test/Sema/attr-target-clones-aarch64.c @@ -7,7 +7,7 @@ void __attribute__((target_clones("default+sha3"))) warn1(void); // expected-error@+2 {{'target_clones' and 'target_version' attributes are not compatible}} // expected-note@+1 {{conflicting attribute is here}} -void __attribute__((target_version("sve-bf16"), target_clones("sme+memtag"))) not_compat(void); +void __attribute__((target_version("sve"), target_clones("sme+memtag"))) not_compat(void); int redecl(void); int __attribute__((target_clones("frintts", "simd+fp", "default"))) redecl(void) { return 1; } @@ -78,4 +78,4 @@ int useage(void) { // expected-error@+1 {{function declaration cannot become a multiversioned function after first usage}} int __attribute__((target_clones("sve2-sha3+ssbs", "sm4"))) mv_after_use(void) { return 1; } // expected-error@+1 {{'main' cannot be a multiversioned function}} -int __attribute__((target_clones("sve-i8mm"))) main() { return 1; } +int __attribute__((target_clones("i8mm"))) main() { return 1; } diff --git a/clang/test/SemaCXX/attr-target-version.cpp b/clang/test/SemaCXX/attr-target-version.cpp index 2c85f9735a87b1..c0a645713b2187 100644 --- a/clang/test/SemaCXX/attr-target-version.cpp +++ b/clang/test/SemaCXX/attr-target-version.cpp @@ -49,7 +49,7 @@ double __attribute__((target_version("rcpc"))) diff_type1(void); auto __attribute__((target_version("rcpc2"))) diff_type2(void) -> int { return 1; } //expected-error@+1 {{multiversioned function declaration has a different return type}} -auto __attribute__((target_version("sve-bf16"))) diff_type2(void) -> long { return (long)1; } +auto __attribute__((target_version("bf16"))) diff_type2(void) -> long { return (long)1; } int __attribute__((target_version("fp16fml"))) diff_type3(void) noexcept(false) { return 1; } //expected-error@+2 {{exception specification in declaration does not match previous declaration}} @@ -75,7 +75,7 @@ auto __attribute__((target_version("dpb2"))) ret3(void) -> int { return 1; } class Cls { __attribute__((target_version("rng"))) Cls(); // expected-error@-1 {{attribute 'target_version' multiversioned functions do not yet support constructors}} - __attribute__((target_version("sve-i8mm"))) ~Cls(); + __attribute__((target_version("i8mm"))) ~Cls(); // expected-error@-1 {{attribute 'target_version' multiversioned functions do not yet support destructors}} Cls &__attribute__((target_version("f32mm"))) operator=(const Cls &) = default; diff --git a/clang/test/SemaCXX/constexpr-string.cpp b/clang/test/SemaCXX/constexpr-string.cpp index 5448365489a514..c456740ef7551f 100644 --- a/clang/test/SemaCXX/constexpr-string.cpp +++ b/clang/test/SemaCXX/constexpr-string.cpp @@ -670,8 +670,6 @@ namespace MemcpyEtc { constexpr bool test_address_of_incomplete_struct_type() { // expected-error {{never produces a constant}} struct Incomplete; extern Incomplete x, y; - // expected-warning@+2 {{first argument in call to '__builtin_memcpy' is a pointer to non-trivially copyable type 'Incomplete'}} - // expected-note@+1 {{explicitly cast the pointer to silence this warning}} __builtin_memcpy(&x, &x, 4); // expected-note@-1 2{{cannot constant evaluate 'memcpy' between objects of incomplete type 'Incomplete'}} return true; diff --git a/clang/test/SemaCXX/gh113468.cpp b/clang/test/SemaCXX/gh113468.cpp new file mode 100644 index 00000000000000..94551986b0efaa --- /dev/null +++ b/clang/test/SemaCXX/gh113468.cpp @@ -0,0 +1,12 @@ +// RUN: %clang_cc1 -std=c++20 -fsyntax-only -verify %s + +constexpr int expr() { + if (({ + int f; + f = 0; + if (f) + break; // expected-error {{'break' statement not in loop or switch statement}} + })) + return 2; + return 1; +} diff --git a/clang/test/SemaCXX/warn-memaccess.cpp b/clang/test/SemaCXX/warn-memaccess.cpp index b4b7f6a6905b23..070b44891a91aa 100644 --- a/clang/test/SemaCXX/warn-memaccess.cpp +++ b/clang/test/SemaCXX/warn-memaccess.cpp @@ -7,12 +7,17 @@ extern "C" void *memcpy(void *s1, const void *s2, unsigned n); class TriviallyCopyable {}; class NonTriviallyCopyable { NonTriviallyCopyable(const NonTriviallyCopyable&);}; +struct Incomplete; void test_bzero(TriviallyCopyable* tc, - NonTriviallyCopyable *ntc) { + NonTriviallyCopyable *ntc, + Incomplete* i) { // OK bzero(tc, sizeof(*tc)); + // OK + bzero(i, 10); + // expected-warning@+2{{first argument in call to 'bzero' is a pointer to non-trivially copyable type 'NonTriviallyCopyable'}} // expected-note@+1{{explicitly cast the pointer to silence this warning}} bzero(ntc, sizeof(*ntc)); @@ -22,10 +27,14 @@ void test_bzero(TriviallyCopyable* tc, } void test_memset(TriviallyCopyable* tc, - NonTriviallyCopyable *ntc) { + NonTriviallyCopyable *ntc, + Incomplete* i) { // OK memset(tc, 0, sizeof(*tc)); + // OK + memset(i, 0, 10); + // expected-warning@+2{{first argument in call to 'memset' is a pointer to non-trivially copyable type 'NonTriviallyCopyable'}} // expected-note@+1{{explicitly cast the pointer to silence this warning}} memset(ntc, 0, sizeof(*ntc)); @@ -36,10 +45,14 @@ void test_memset(TriviallyCopyable* tc, void test_memcpy(TriviallyCopyable* tc0, TriviallyCopyable* tc1, - NonTriviallyCopyable *ntc0, NonTriviallyCopyable *ntc1) { + NonTriviallyCopyable *ntc0, NonTriviallyCopyable *ntc1, + Incomplete *i0, Incomplete *i1) { // OK memcpy(tc0, tc1, sizeof(*tc0)); + // OK + memcpy(i0, i1, 10); + // expected-warning@+2{{first argument in call to 'memcpy' is a pointer to non-trivially copyable type 'NonTriviallyCopyable'}} // expected-note@+1{{explicitly cast the pointer to silence this warning}} memcpy(ntc0, ntc1, sizeof(*ntc0)); @@ -52,10 +65,14 @@ void test_memcpy(TriviallyCopyable* tc0, TriviallyCopyable* tc1, } void test_memmove(TriviallyCopyable* tc0, TriviallyCopyable* tc1, - NonTriviallyCopyable *ntc0, NonTriviallyCopyable *ntc1) { + NonTriviallyCopyable *ntc0, NonTriviallyCopyable *ntc1, + Incomplete *i0, Incomplete *i1) { // OK memmove(tc0, tc1, sizeof(*tc0)); + // OK + memmove(i0, i1, 10); + // expected-warning@+2{{first argument in call to 'memmove' is a pointer to non-trivially copyable type 'NonTriviallyCopyable'}} // expected-note@+1{{explicitly cast the pointer to silence this warning}} memmove(ntc0, ntc1, sizeof(*ntc0)); diff --git a/clang/test/SemaHLSL/BuiltIns/countbits-errors.hlsl b/clang/test/SemaHLSL/BuiltIns/countbits-errors.hlsl index 8d5f0abb2860f8..5704165e1a4505 100644 --- a/clang/test/SemaHLSL/BuiltIns/countbits-errors.hlsl +++ b/clang/test/SemaHLSL/BuiltIns/countbits-errors.hlsl @@ -1,6 +1,4 @@ -// RUN: %clang_cc1 -finclude-default-header -// -triple dxil-pc-shadermodel6.6-library %s -fnative-half-type -emit-llvm-only -// -disable-llvm-passes -verify -verify-ignore-unexpected +// RUN: %clang_cc1 -finclude-default-header -triple dxil-pc-shadermodel6.6-library %s -fnative-half-type -emit-llvm-only -disable-llvm-passes -verify -verify-ignore-unexpected double test_int_builtin(double p0) { @@ -9,13 +7,11 @@ double test_int_builtin(double p0) { } double2 test_int_builtin_2(double2 p0) { - return __builtin_elementwise_popcount(p0); - // expected-error@-1 {{1st argument must be a vector of integers - // (was 'double2' (aka 'vector'))}} + return countbits(p0); + // expected-error@-1 {{call to 'countbits' is ambiguous}} } double test_int_builtin_3(float p0) { - return __builtin_elementwise_popcount(p0); - // expected-error@-1 {{1st argument must be a vector of integers - // (was 'float')}} + return countbits(p0); + // expected-error@-1 {{call to 'countbits' is ambiguous}} } diff --git a/clang/tools/clang-format/git-clang-format.bat b/clang/tools/clang-format/git-clang-format.bat index 19c82d8a04132b..a40276e63c5848 100644 --- a/clang/tools/clang-format/git-clang-format.bat +++ b/clang/tools/clang-format/git-clang-format.bat @@ -1 +1 @@ -py -3 "%~pn0" %* +py -3 "%~dpn0" %* diff --git a/clang/tools/clang-linker-wrapper/ClangLinkerWrapper.cpp b/clang/tools/clang-linker-wrapper/ClangLinkerWrapper.cpp index 9fcecaee318a79..561b73c73ad7df 100644 --- a/clang/tools/clang-linker-wrapper/ClangLinkerWrapper.cpp +++ b/clang/tools/clang-linker-wrapper/ClangLinkerWrapper.cpp @@ -140,9 +140,6 @@ static std::list> TempFiles; /// Codegen flags for LTO backend. static codegen::RegisterCodeGenFlags CodeGenFlags; -/// Global flag to indicate that the LTO pipeline threw an error. -static std::atomic LTOError; - using OffloadingImage = OffloadBinary::OffloadingImage; namespace llvm { @@ -293,12 +290,10 @@ Expected findProgram(StringRef Name, ArrayRef Paths) { return *Path; } -/// We will defer LTO to the target's linker if we are not doing JIT and it is -/// supported by the toolchain. bool linkerSupportsLTO(const ArgList &Args) { llvm::Triple Triple(Args.getLastArgValue(OPT_triple_EQ)); return Triple.isNVPTX() || Triple.isAMDGPU() || - Args.getLastArgValue(OPT_linker_path_EQ).ends_with("ld.lld"); + Args.getLastArgValue(OPT_linker_path_EQ).ends_with("lld"); } /// Returns the hashed value for a constant string. @@ -528,13 +523,11 @@ Expected clang(ArrayRef InputFiles, const ArgList &Args) { }; // Forward all of the `--offload-opt` and similar options to the device. - if (linkerSupportsLTO(Args)) { - CmdArgs.push_back("-flto"); - for (auto &Arg : Args.filtered(OPT_offload_opt_eq_minus, OPT_mllvm)) - CmdArgs.append( - {"-Xlinker", - Args.MakeArgString("--plugin-opt=" + StringRef(Arg->getValue()))}); - } + CmdArgs.push_back("-flto"); + for (auto &Arg : Args.filtered(OPT_offload_opt_eq_minus, OPT_mllvm)) + CmdArgs.append( + {"-Xlinker", + Args.MakeArgString("--plugin-opt=" + StringRef(Arg->getValue()))}); if (!Triple.isNVPTX()) CmdArgs.push_back("-Wl,--no-undefined"); @@ -646,357 +639,6 @@ Expected linkDevice(ArrayRef InputFiles, } } -void diagnosticHandler(const DiagnosticInfo &DI) { - std::string ErrStorage; - raw_string_ostream OS(ErrStorage); - DiagnosticPrinterRawOStream DP(OS); - DI.print(DP); - - switch (DI.getSeverity()) { - case DS_Error: - WithColor::error(errs(), LinkerExecutable) << ErrStorage << "\n"; - LTOError = true; - break; - case DS_Warning: - WithColor::warning(errs(), LinkerExecutable) << ErrStorage << "\n"; - break; - case DS_Note: - WithColor::note(errs(), LinkerExecutable) << ErrStorage << "\n"; - break; - case DS_Remark: - WithColor::remark(errs()) << ErrStorage << "\n"; - break; - } -} - -// Get the list of target features from the input file and unify them such that -// if there are multiple +xxx or -xxx features we only keep the last one. -std::vector getTargetFeatures(ArrayRef InputFiles) { - SmallVector Features; - for (const OffloadFile &File : InputFiles) { - for (auto Arg : llvm::split(File.getBinary()->getString("feature"), ",")) - Features.emplace_back(Arg); - } - - // Only add a feature if it hasn't been seen before starting from the end. - std::vector UnifiedFeatures; - DenseSet UsedFeatures; - for (StringRef Feature : llvm::reverse(Features)) { - if (UsedFeatures.insert(Feature.drop_front()).second) - UnifiedFeatures.push_back(Feature.str()); - } - - return UnifiedFeatures; -} - -template > -std::unique_ptr createLTO( - const ArgList &Args, const std::vector &Features, - ModuleHook Hook = [](size_t, const Module &) { return true; }) { - const llvm::Triple Triple(Args.getLastArgValue(OPT_triple_EQ)); - // We need to remove AMD's target-id from the processor if present. - StringRef TargetID = Args.getLastArgValue(OPT_arch_EQ); - StringRef Arch = clang::getProcessorFromTargetID(Triple, TargetID); - lto::Config Conf; - lto::ThinBackend Backend; - // TODO: Handle index-only thin-LTO - Backend = - lto::createInProcessThinBackend(llvm::heavyweight_hardware_concurrency()); - - Conf.CPU = Arch.str(); - Conf.Options = codegen::InitTargetOptionsFromCodeGenFlags(Triple); - - Conf.RemarksFilename = RemarksFilename; - Conf.RemarksPasses = RemarksPasses; - Conf.RemarksWithHotness = RemarksWithHotness; - Conf.RemarksHotnessThreshold = RemarksHotnessThreshold; - Conf.RemarksFormat = RemarksFormat; - - StringRef OptLevel = Args.getLastArgValue(OPT_opt_level, "O2"); - Conf.MAttrs = Features; - std::optional CGOptLevelOrNone = - CodeGenOpt::parseLevel(OptLevel[1]); - assert(CGOptLevelOrNone && "Invalid optimization level"); - Conf.CGOptLevel = *CGOptLevelOrNone; - Conf.OptLevel = OptLevel[1] - '0'; - Conf.DefaultTriple = Triple.getTriple(); - - // TODO: Should we complain about combining --opt-level and -passes, as opt - // does? That might be too limiting in clang-linker-wrapper, so for now we - // just warn in the help entry for -passes that the default corresponding - // to --opt-level=O? should be included there. The problem is that - // --opt-level produces effects in clang-linker-wrapper beyond what -passes - // appears to be able to achieve, so rejecting the combination of --opt-level - // and -passes would apparently make it impossible to combine those effects - // with a custom pass pipeline. - Conf.OptPipeline = PassPipeline; - Conf.PassPlugins = PassPlugins; - - LTOError = false; - Conf.DiagHandler = diagnosticHandler; - - Conf.PTO.LoopVectorization = Conf.OptLevel > 1; - Conf.PTO.SLPVectorization = Conf.OptLevel > 1; - - if (SaveTemps) { - std::string TempName = (sys::path::filename(ExecutableName) + "." + - Triple.getTriple() + "." + TargetID) - .str(); - Conf.PostInternalizeModuleHook = [=](size_t Task, const Module &M) { - std::string File = - !Task ? TempName + ".postlink.bc" - : TempName + "." + std::to_string(Task) + ".postlink.bc"; - error_code EC; - raw_fd_ostream LinkedBitcode(File, EC, sys::fs::OF_None); - if (EC) - reportError(errorCodeToError(EC)); - WriteBitcodeToFile(M, LinkedBitcode); - return true; - }; - Conf.PreCodeGenModuleHook = [=](size_t Task, const Module &M) { - std::string File = - !Task ? TempName + ".postopt.bc" - : TempName + "." + std::to_string(Task) + ".postopt.bc"; - error_code EC; - raw_fd_ostream LinkedBitcode(File, EC, sys::fs::OF_None); - if (EC) - reportError(errorCodeToError(EC)); - WriteBitcodeToFile(M, LinkedBitcode); - return true; - }; - } - Conf.PostOptModuleHook = Hook; - Conf.CGFileType = (Triple.isNVPTX() || SaveTemps) - ? CodeGenFileType::AssemblyFile - : CodeGenFileType::ObjectFile; - - // TODO: Handle remark files - Conf.HasWholeProgramVisibility = Args.hasArg(OPT_whole_program); - - return std::make_unique(std::move(Conf), Backend); -} - -// Returns true if \p S is valid as a C language identifier and will be given -// `__start_` and `__stop_` symbols. -bool isValidCIdentifier(StringRef S) { - return !S.empty() && (isAlpha(S[0]) || S[0] == '_') && - llvm::all_of(llvm::drop_begin(S), - [](char C) { return C == '_' || isAlnum(C); }); -} - -Error linkBitcodeFiles(SmallVectorImpl &InputFiles, - SmallVectorImpl &OutputFiles, - const ArgList &Args) { - llvm::TimeTraceScope TimeScope("Link bitcode files"); - const llvm::Triple Triple(Args.getLastArgValue(OPT_triple_EQ)); - StringRef Arch = Args.getLastArgValue(OPT_arch_EQ); - - SmallVector BitcodeInputFiles; - DenseSet StrongResolutions; - DenseSet UsedInRegularObj; - DenseSet UsedInSharedLib; - BumpPtrAllocator Alloc; - StringSaver Saver(Alloc); - - // Search for bitcode files in the input and create an LTO input file. If - // it is not a bitcode file, scan its symbol table for symbols we need to - // save. - for (OffloadFile &File : InputFiles) { - MemoryBufferRef Buffer = MemoryBufferRef(File.getBinary()->getImage(), ""); - - file_magic Type = identify_magic(Buffer.getBuffer()); - switch (Type) { - case file_magic::bitcode: { - Expected IRSymtabOrErr = readIRSymtab(Buffer); - if (!IRSymtabOrErr) - return IRSymtabOrErr.takeError(); - - // Check for any strong resolutions we need to preserve. - for (unsigned I = 0; I != IRSymtabOrErr->Mods.size(); ++I) { - for (const auto &Sym : IRSymtabOrErr->TheReader.module_symbols(I)) { - if (!Sym.isFormatSpecific() && Sym.isGlobal() && !Sym.isWeak() && - !Sym.isUndefined()) - StrongResolutions.insert(Saver.save(Sym.Name)); - } - } - BitcodeInputFiles.emplace_back(std::move(File)); - continue; - } - case file_magic::elf_relocatable: - case file_magic::elf_shared_object: { - Expected> ObjFile = - ObjectFile::createObjectFile(Buffer); - if (!ObjFile) - continue; - - for (SymbolRef Sym : (*ObjFile)->symbols()) { - Expected Name = Sym.getName(); - if (!Name) - return Name.takeError(); - - // Record if we've seen these symbols in any object or shared - // libraries. - if ((*ObjFile)->isRelocatableObject()) - UsedInRegularObj.insert(Saver.save(*Name)); - else - UsedInSharedLib.insert(Saver.save(*Name)); - } - continue; - } - default: - continue; - } - } - - if (BitcodeInputFiles.empty()) - return Error::success(); - - // Remove all the bitcode files that we moved from the original input. - llvm::erase_if(InputFiles, [](OffloadFile &F) { return !F.getBinary(); }); - - // LTO Module hook to output bitcode without running the backend. - SmallVector BitcodeOutput; - auto OutputBitcode = [&](size_t, const Module &M) { - auto TempFileOrErr = createOutputFile(sys::path::filename(ExecutableName) + - "-jit-" + Triple.getTriple(), - "bc"); - if (!TempFileOrErr) - reportError(TempFileOrErr.takeError()); - - std::error_code EC; - raw_fd_ostream LinkedBitcode(*TempFileOrErr, EC, sys::fs::OF_None); - if (EC) - reportError(errorCodeToError(EC)); - WriteBitcodeToFile(M, LinkedBitcode); - BitcodeOutput.push_back(*TempFileOrErr); - return false; - }; - - // We assume visibility of the whole program if every input file was - // bitcode. - auto Features = getTargetFeatures(BitcodeInputFiles); - auto LTOBackend = Args.hasArg(OPT_embed_bitcode) || - Args.hasArg(OPT_builtin_bitcode_EQ) || - Args.hasArg(OPT_clang_backend) - ? createLTO(Args, Features, OutputBitcode) - : createLTO(Args, Features); - - // We need to resolve the symbols so the LTO backend knows which symbols - // need to be kept or can be internalized. This is a simplified symbol - // resolution scheme to approximate the full resolution a linker would do. - uint64_t Idx = 0; - DenseSet PrevailingSymbols; - for (auto &BitcodeInput : BitcodeInputFiles) { - // Get a semi-unique buffer identifier for Thin-LTO. - StringRef Identifier = Saver.save( - std::to_string(Idx++) + "." + - BitcodeInput.getBinary()->getMemoryBufferRef().getBufferIdentifier()); - MemoryBufferRef Buffer = - MemoryBufferRef(BitcodeInput.getBinary()->getImage(), Identifier); - Expected> BitcodeFileOrErr = - llvm::lto::InputFile::create(Buffer); - if (!BitcodeFileOrErr) - return BitcodeFileOrErr.takeError(); - - // Save the input file and the buffer associated with its memory. - const auto Symbols = (*BitcodeFileOrErr)->symbols(); - SmallVector Resolutions(Symbols.size()); - size_t Idx = 0; - for (auto &Sym : Symbols) { - lto::SymbolResolution &Res = Resolutions[Idx++]; - - // We will use this as the prevailing symbol definition in LTO unless - // it is undefined or another definition has already been used. - Res.Prevailing = - !Sym.isUndefined() && - !(Sym.isWeak() && StrongResolutions.contains(Sym.getName())) && - PrevailingSymbols.insert(Saver.save(Sym.getName())).second; - - // We need LTO to preseve the following global symbols: - // 1) Symbols used in regular objects. - // 2) Sections that will be given a __start/__stop symbol. - // 3) Prevailing symbols that are needed visible to external - // libraries. - Res.VisibleToRegularObj = - UsedInRegularObj.contains(Sym.getName()) || - isValidCIdentifier(Sym.getSectionName()) || - (Res.Prevailing && - (Sym.getVisibility() != GlobalValue::HiddenVisibility && - !Sym.canBeOmittedFromSymbolTable())); - - // Identify symbols that must be exported dynamically and can be - // referenced by other files. - Res.ExportDynamic = - Sym.getVisibility() != GlobalValue::HiddenVisibility && - (UsedInSharedLib.contains(Sym.getName()) || - !Sym.canBeOmittedFromSymbolTable()); - - // The final definition will reside in this linkage unit if the symbol - // is defined and local to the module. This only checks for bitcode - // files, full assertion will require complete symbol resolution. - Res.FinalDefinitionInLinkageUnit = - Sym.getVisibility() != GlobalValue::DefaultVisibility && - (!Sym.isUndefined() && !Sym.isCommon()); - - // We do not support linker redefined symbols (e.g. --wrap) for device - // image linking, so the symbols will not be changed after LTO. - Res.LinkerRedefined = false; - } - - // Add the bitcode file with its resolved symbols to the LTO job. - if (Error Err = LTOBackend->add(std::move(*BitcodeFileOrErr), Resolutions)) - return Err; - } - - // Run the LTO job to compile the bitcode. - size_t MaxTasks = LTOBackend->getMaxTasks(); - SmallVector Files(MaxTasks); - auto AddStream = - [&](size_t Task, - const Twine &ModuleName) -> std::unique_ptr { - int FD = -1; - auto &TempFile = Files[Task]; - StringRef Extension = (Triple.isNVPTX() || SaveTemps) ? "s" : "o"; - std::string TaskStr = Task ? "." + std::to_string(Task) : ""; - auto TempFileOrErr = - createOutputFile(sys::path::filename(ExecutableName) + "." + - Triple.getTriple() + "." + Arch + TaskStr, - Extension); - if (!TempFileOrErr) - reportError(TempFileOrErr.takeError()); - TempFile = *TempFileOrErr; - if (std::error_code EC = sys::fs::openFileForWrite(TempFile, FD)) - reportError(errorCodeToError(EC)); - return std::make_unique( - std::make_unique(FD, true)); - }; - - if (Error Err = LTOBackend->run(AddStream)) - return Err; - - if (LTOError) - return createStringError("Errors encountered inside the LTO pipeline."); - - // If we are embedding bitcode we only need the intermediate output. - bool SingleOutput = Files.size() == 1; - if (Args.hasArg(OPT_embed_bitcode)) { - if (BitcodeOutput.size() != 1 || !SingleOutput) - return createStringError("Cannot embed bitcode with multiple files."); - OutputFiles.push_back(Args.MakeArgString(BitcodeOutput.front())); - return Error::success(); - } - - // Append the new inputs to the device linker input. If the user requested - // an internalizing link we need to pass the bitcode to clang. - for (StringRef File : - Args.hasArg(OPT_clang_backend) || Args.hasArg(OPT_builtin_bitcode_EQ) - ? BitcodeOutput - : Files) - OutputFiles.push_back(File); - - return Error::success(); -} - Expected writeOffloadFile(const OffloadFile &File) { const OffloadBinary &Binary = *File.getBinary(); @@ -1327,15 +969,8 @@ Expected> linkAndWrapDeviceFiles( if (File.getBinary()->getOffloadKind() != OFK_None) ActiveOffloadKinds.insert(File.getBinary()->getOffloadKind()); - // First link and remove all the input files containing bitcode if - // the target linker does not support it natively. + // Write any remaining device inputs to an output file. SmallVector InputFiles; - if (!linkerSupportsLTO(LinkerArgs)) - if (Error Err = linkBitcodeFiles(Input, InputFiles, LinkerArgs)) - return Err; - - // Write any remaining device inputs to an output file for the - // linker. for (const OffloadFile &File : Input) { auto FileNameOrErr = writeOffloadFile(File); if (!FileNameOrErr) @@ -1344,10 +979,7 @@ Expected> linkAndWrapDeviceFiles( } // Link the remaining device files using the device linker. - auto OutputOrErr = - !Args.hasArg(OPT_embed_bitcode) || linkerSupportsLTO(LinkerArgs) - ? linkDevice(InputFiles, LinkerArgs) - : InputFiles.front(); + auto OutputOrErr = linkDevice(InputFiles, LinkerArgs); if (!OutputOrErr) return OutputOrErr.takeError(); diff --git a/clang/tools/clang-nvlink-wrapper/ClangNVLinkWrapper.cpp b/clang/tools/clang-nvlink-wrapper/ClangNVLinkWrapper.cpp index b9767a7a03d0b5..bc191afdca739d 100644 --- a/clang/tools/clang-nvlink-wrapper/ClangNVLinkWrapper.cpp +++ b/clang/tools/clang-nvlink-wrapper/ClangNVLinkWrapper.cpp @@ -250,6 +250,7 @@ struct Symbol { }; Symbol() : File(), Flags(None), UsedInRegularObj(false) {} + Symbol(Symbol::Flags Flags) : File(), Flags(Flags), UsedInRegularObj(true) {} Symbol(MemoryBufferRef File, const irsymtab::Reader::SymbolRef Sym) : File(File), Flags(0), UsedInRegularObj(false) { @@ -535,6 +536,8 @@ Expected> getInput(const ArgList &Args) { bool Extracted = true; StringMap SymTab; + for (auto &Sym : Args.getAllArgValues(OPT_u)) + SymTab[Sym] = Symbol(Symbol::Undefined); SmallVector> LinkerInput; while (Extracted) { Extracted = false; diff --git a/clang/tools/clang-nvlink-wrapper/NVLinkOpts.td b/clang/tools/clang-nvlink-wrapper/NVLinkOpts.td index a80c5937b42992..6de1a25c14f8be 100644 --- a/clang/tools/clang-nvlink-wrapper/NVLinkOpts.td +++ b/clang/tools/clang-nvlink-wrapper/NVLinkOpts.td @@ -43,11 +43,11 @@ def plugin : JoinedOrSeparate<["--", "-"], "plugin">, Flags<[HelpHidden, WrapperOnlyOption]>; def arch : Separate<["--", "-"], "arch">, - HelpText<"Specify the 'sm_' name of the target architecture.">; + HelpText<"Specify the 'sm_' name of the target architecture">; def : Joined<["--", "-"], "plugin-opt=mcpu=">, Flags<[HelpHidden, WrapperOnlyOption]>, Alias; -def g : Flag<["-"], "g">, HelpText<"Specify that this was a debug compile.">; +def g : Flag<["-"], "g">, HelpText<"Specify that this was a debug compile">; def debug : Flag<["--"], "debug">, Alias; def lto_emit_llvm : Flag<["--"], "lto-emit-llvm">, Flags<[WrapperOnlyOption]>, @@ -55,6 +55,9 @@ def lto_emit_llvm : Flag<["--"], "lto-emit-llvm">, Flags<[WrapperOnlyOption]>, def lto_emit_asm : Flag<["--"], "lto-emit-asm">, Flags<[WrapperOnlyOption]>, HelpText<"Emit assembly code">; +def u : JoinedOrSeparate<["-"], "u">, HelpText<"Force undefined symbol during linking">; +def undefined : JoinedOrSeparate<["--"], "undefined">, Alias; + def O : Joined<["--", "-"], "plugin-opt=O">, Flags<[WrapperOnlyOption]>, MetaVarName<"">, HelpText<"Optimization level for LTO">; diff --git a/clang/utils/TableGen/ClangBuiltinsEmitter.cpp b/clang/utils/TableGen/ClangBuiltinsEmitter.cpp index 20231ee1502c12..57a1fc06b26b16 100644 --- a/clang/utils/TableGen/ClangBuiltinsEmitter.cpp +++ b/clang/utils/TableGen/ClangBuiltinsEmitter.cpp @@ -64,7 +64,8 @@ class PrototypeParser { // detecting the comma of the template class as a separator for // the parameters of the prototype. Note: the assumption is that // we cannot have nested _ExtVector. - if (Current.starts_with("_ExtVector<")) { + if (Current.starts_with("_ExtVector<") || + Current.starts_with("_Vector<")) { const size_t EndTemplate = Current.find('>', 0); ParseType(Current.substr(0, EndTemplate + 1)); // Move the prototype beyond _ExtVector<...> @@ -123,7 +124,8 @@ class PrototypeParser { if (Substitution.empty()) PrintFatalError(Loc, "Not a template"); ParseType(Substitution); - } else if (T.consume_front("_ExtVector")) { + } else if (auto IsExt = T.consume_front("_ExtVector"); + IsExt || T.consume_front("_Vector")) { // Clang extended vector types are mangled as follows: // // '_ExtVector<' ',' '>' @@ -135,7 +137,7 @@ class PrototypeParser { unsigned long long Lanes; if (consumeUnsignedInteger(T, 10, Lanes)) PrintFatalError(Loc, "Expected number of lanes after '_ExtVector<'"); - Type += "E" + std::to_string(Lanes); + Type += (IsExt ? "E" : "V") + std::to_string(Lanes); if (!T.consume_front(",")) PrintFatalError(Loc, "Expected ',' after number of lanes in '_ExtVector<'"); diff --git a/compiler-rt/lib/builtins/cpu_model/AArch64CPUFeatures.inc b/compiler-rt/lib/builtins/cpu_model/AArch64CPUFeatures.inc index 902fa8f79ab816..e454524c9cb6a2 100644 --- a/compiler-rt/lib/builtins/cpu_model/AArch64CPUFeatures.inc +++ b/compiler-rt/lib/builtins/cpu_model/AArch64CPUFeatures.inc @@ -53,9 +53,9 @@ enum CPUFeatures { FEAT_EBF16, FEAT_RPRES, FEAT_SVE, - FEAT_SVE_BF16, - FEAT_SVE_EBF16, - FEAT_SVE_I8MM, + RESERVED_FEAT_SVE_BF16, // previously used and now ABI legacy + RESERVED_FEAT_SVE_EBF16, // previously used and now ABI legacy + RESERVED_FEAT_SVE_I8MM, // previously used and now ABI legacy FEAT_SVE_F32MM, FEAT_SVE_F64MM, FEAT_SVE2, diff --git a/compiler-rt/lib/builtins/cpu_model/aarch64/fmv/mrs.inc b/compiler-rt/lib/builtins/cpu_model/aarch64/fmv/mrs.inc index 0c76a4fe9b9f2f..4e25feb2e90c63 100644 --- a/compiler-rt/lib/builtins/cpu_model/aarch64/fmv/mrs.inc +++ b/compiler-rt/lib/builtins/cpu_model/aarch64/fmv/mrs.inc @@ -65,14 +65,10 @@ static void __init_cpu_features_constructor(unsigned long hwcap, setCPUFeature(FEAT_I8MM); if (hwcap2 & HWCAP2_EBF16) setCPUFeature(FEAT_EBF16); - if (hwcap2 & HWCAP2_SVE_EBF16) - setCPUFeature(FEAT_SVE_EBF16); if (hwcap2 & HWCAP2_DGH) setCPUFeature(FEAT_DGH); if (hwcap2 & HWCAP2_FRINT) setCPUFeature(FEAT_FRINTTS); - if (hwcap2 & HWCAP2_SVEI8MM) - setCPUFeature(FEAT_SVE_I8MM); if (hwcap2 & HWCAP2_SVEF32MM) setCPUFeature(FEAT_SVE_F32MM); if (hwcap2 & HWCAP2_SVEF64MM) @@ -119,8 +115,6 @@ static void __init_cpu_features_constructor(unsigned long hwcap, setCPUFeature(FEAT_RCPC3); if (hwcap2 & HWCAP2_BF16) setCPUFeature(FEAT_BF16); - if (hwcap2 & HWCAP2_SVEBF16) - setCPUFeature(FEAT_SVE_BF16); if (hwcap & HWCAP_SVE) setCPUFeature(FEAT_SVE); if (hwcap2 & HWCAP2_SVE2) diff --git a/compiler-rt/test/hwasan/TestCases/many-threads-uaf.c b/compiler-rt/test/hwasan/TestCases/many-threads-uaf.c index 8fa07861371d56..e02ab5b28ce046 100644 --- a/compiler-rt/test/hwasan/TestCases/many-threads-uaf.c +++ b/compiler-rt/test/hwasan/TestCases/many-threads-uaf.c @@ -23,6 +23,7 @@ void *BoringThread(void *arg) { void *UAFThread(void *arg) { char * volatile x = (char*)malloc(10); fprintf(stderr, "ZZZ %p\n", x); + fflush(stderr); free(x); x[5] = 42; // CHECK: ERROR: HWAddressSanitizer: tag-mismatch on address diff --git a/compiler-rt/test/hwasan/TestCases/mem-intrinsics.c b/compiler-rt/test/hwasan/TestCases/mem-intrinsics.c index 78bef538af1161..da1cb686969206 100644 --- a/compiler-rt/test/hwasan/TestCases/mem-intrinsics.c +++ b/compiler-rt/test/hwasan/TestCases/mem-intrinsics.c @@ -21,6 +21,7 @@ int main() { memcpy(Q, P, 32); #endif write(STDOUT_FILENO, "recovered\n", 10); + fflush(stdout); // WRITE: ERROR: HWAddressSanitizer: tag-mismatch on address // WRITE: WRITE of size 32 at {{.*}} tags: [[PTR_TAG:..]]/[[MEM_TAG:..]] (ptr/mem) // WRITE: Invalid access starting at offset 16 diff --git a/compiler-rt/test/hwasan/TestCases/use-after-free.c b/compiler-rt/test/hwasan/TestCases/use-after-free.c index 070622f560a225..fe4f8b32ea1006 100644 --- a/compiler-rt/test/hwasan/TestCases/use-after-free.c +++ b/compiler-rt/test/hwasan/TestCases/use-after-free.c @@ -15,6 +15,7 @@ int main() { free(x); __hwasan_disable_allocator_tagging(); fprintf(stderr, ISREAD ? "Going to do a READ\n" : "Going to do a WRITE\n"); + fflush(stderr); // CHECK: Going to do a [[TYPE:[A-Z]*]] int r = 0; if (ISREAD) r = x[5]; else x[5] = 42; // should be on the same line. @@ -31,11 +32,11 @@ int main() { // // CHECK: freed by thread {{.*}} here: // CHECK: #0 {{.*}} in {{.*}}free{{.*}} {{.*}}hwasan_allocation_functions.cpp - // CHECK: #1 {{.*}} in main {{.*}}use-after-free.c:[[@LINE-19]] + // CHECK: #1 {{.*}} in main {{.*}}use-after-free.c:[[@LINE-20]] // CHECK: previously allocated by thread {{.*}} here: // CHECK: #0 {{.*}} in {{.*}}malloc{{.*}} {{.*}}hwasan_allocation_functions.cpp - // CHECK: #1 {{.*}} in main {{.*}}use-after-free.c:[[@LINE-24]] + // CHECK: #1 {{.*}} in main {{.*}}use-after-free.c:[[@LINE-25]] // CHECK: Memory tags around the buggy address (one tag corresponds to 16 bytes): // CHECK: =>{{.*}}[[MEM_TAG]] // CHECK: SUMMARY: HWAddressSanitizer: tag-mismatch {{.*}} in main diff --git a/compiler-rt/test/xray/TestCases/Posix/clang-xray-shared.cpp b/compiler-rt/test/xray/TestCases/Posix/clang-xray-shared.cpp index 92f3c29e970d42..0dd721571de9b8 100644 --- a/compiler-rt/test/xray/TestCases/Posix/clang-xray-shared.cpp +++ b/compiler-rt/test/xray/TestCases/Posix/clang-xray-shared.cpp @@ -1,6 +1,6 @@ // Test that the DSO-local runtime library has been linked if -fxray-shared is passed. // -// RUN: %clangxx -fxray-instrument -fxray-shared %s -shared -o %t.so +// RUN: %clangxx -fxray-instrument -fxray-shared -fPIC %s -shared -o %t.so // RUN: llvm-nm %t.so | FileCheck %s --check-prefix ENABLED // RUN: %clangxx -fxray-instrument %s -shared -o %t.so diff --git a/flang/include/flang/Frontend/TargetOptions.h b/flang/include/flang/Frontend/TargetOptions.h index 332adcbe6b6ac3..01c878067b921d 100644 --- a/flang/include/flang/Frontend/TargetOptions.h +++ b/flang/include/flang/Frontend/TargetOptions.h @@ -44,6 +44,9 @@ class TargetOptions { /// The integer KINDs disabled for this target std::vector disabledIntegerKinds; + + /// Extended Altivec ABI on AIX + bool EnableAIXExtendedAltivecABI; }; } // end namespace Fortran::frontend diff --git a/flang/include/flang/Optimizer/Builder/IntrinsicCall.h b/flang/include/flang/Optimizer/Builder/IntrinsicCall.h index 868a8b4e287424..f5fb272b4cc3ed 100644 --- a/flang/include/flang/Optimizer/Builder/IntrinsicCall.h +++ b/flang/include/flang/Optimizer/Builder/IntrinsicCall.h @@ -289,6 +289,7 @@ struct IntrinsicLibrary { template mlir::Value genIeeeQuietCompare(mlir::Type resultType, llvm::ArrayRef); + mlir::Value genIeeeReal(mlir::Type, llvm::ArrayRef); mlir::Value genIeeeRint(mlir::Type, llvm::ArrayRef); template void genIeeeSetFlagOrHaltingMode(llvm::ArrayRef); diff --git a/flang/include/flang/Parser/dump-parse-tree.h b/flang/include/flang/Parser/dump-parse-tree.h index 31ad1b7c6ce5b5..67f7e1aac40edb 100644 --- a/flang/include/flang/Parser/dump-parse-tree.h +++ b/flang/include/flang/Parser/dump-parse-tree.h @@ -517,6 +517,7 @@ class ParseTreeDumper { NODE_ENUM(OmpTaskDependenceType, Type) NODE(parser, OmpDependSinkVec) NODE(parser, OmpDependSinkVecLength) + NODE(parser, OmpDestroyClause) NODE(parser, OmpEndAllocators) NODE(parser, OmpEndAtomic) NODE(parser, OmpEndBlockDirective) @@ -571,6 +572,7 @@ class ParseTreeDumper { NODE_ENUM(OmpDeviceClause, DeviceModifier) NODE(parser, OmpDeviceTypeClause) NODE_ENUM(OmpDeviceTypeClause, Type) + NODE(parser, OmpUpdateClause) NODE(parser, OmpScheduleModifier) NODE(OmpScheduleModifier, Modifier1) NODE(OmpScheduleModifier, Modifier2) @@ -609,6 +611,7 @@ class ParseTreeDumper { NODE(parser, OmpAtomicClauseList) NODE(parser, OmpAtomicDefaultMemOrderClause) NODE_ENUM(common, OmpAtomicDefaultMemOrderType) + NODE(parser, OpenMPDepobjConstruct) NODE(parser, OpenMPFlushConstruct) NODE(parser, OpenMPLoopConstruct) NODE(parser, OpenMPExecutableAllocate) diff --git a/flang/include/flang/Parser/parse-tree.h b/flang/include/flang/Parser/parse-tree.h index 506a470c5557b7..13c3353512208b 100644 --- a/flang/include/flang/Parser/parse-tree.h +++ b/flang/include/flang/Parser/parse-tree.h @@ -3447,7 +3447,7 @@ WRAPPER_CLASS(OmpObjectList, std::list); // MUTEXINOUTSET | DEPOBJ | // since 5.0 // INOUTSET // since 5.2 struct OmpTaskDependenceType { - ENUM_CLASS(Type, In, Out, Inout, Source, Sink) + ENUM_CLASS(Type, In, Out, Inout, Source, Sink, Depobj) WRAPPER_CLASS_BOILERPLATE(OmpTaskDependenceType, Type); }; @@ -3527,19 +3527,6 @@ struct OmpDefaultmapClause { std::tuple> t; }; -// device([ device-modifier :] scalar-integer-expression) -struct OmpDeviceClause { - TUPLE_CLASS_BOILERPLATE(OmpDeviceClause); - ENUM_CLASS(DeviceModifier, Ancestor, Device_Num) - std::tuple, ScalarIntExpr> t; -}; - -// device_type(any | host | nohost) -struct OmpDeviceTypeClause { - ENUM_CLASS(Type, Any, Host, Nohost) - WRAPPER_CLASS_BOILERPLATE(OmpDeviceTypeClause, Type); -}; - // 2.13.9 depend-vec-length -> +/- non-negative-constant struct OmpDependSinkVecLength { TUPLE_CLASS_BOILERPLATE(OmpDependSinkVecLength); @@ -3561,16 +3548,40 @@ struct OmpDependSinkVec { // // depend-modifier -> iterator-modifier // since 5.0 struct OmpDependClause { + OmpTaskDependenceType::Type GetDepType() const; + UNION_CLASS_BOILERPLATE(OmpDependClause); EMPTY_CLASS(Source); WRAPPER_CLASS(Sink, std::list); struct InOut { TUPLE_CLASS_BOILERPLATE(InOut); - std::tuple t; + std::tuple, OmpTaskDependenceType, + OmpObjectList> + t; }; std::variant u; }; +// Ref: [5.0:254-255], [5.1:287-288], [5.2:73] +// +// destroy-clause -> +// DESTROY | // since 5.0, until 5.2 +// DESTROY(variable) // since 5.2 +WRAPPER_CLASS(OmpDestroyClause, OmpObject); + +// device([ device-modifier :] scalar-integer-expression) +struct OmpDeviceClause { + TUPLE_CLASS_BOILERPLATE(OmpDeviceClause); + ENUM_CLASS(DeviceModifier, Ancestor, Device_Num) + std::tuple, ScalarIntExpr> t; +}; + +// device_type(any | host | nohost) +struct OmpDeviceTypeClause { + ENUM_CLASS(Type, Any, Host, Nohost) + WRAPPER_CLASS_BOILERPLATE(OmpDeviceTypeClause, Type); +}; + // OMP 5.2 12.6.1 grainsize-clause -> grainsize ([prescriptiveness :] value) struct OmpGrainsizeClause { TUPLE_CLASS_BOILERPLATE(OmpGrainsizeClause); @@ -3714,6 +3725,11 @@ struct OmpNumTasksClause { std::tuple, ScalarIntExpr> t; }; +// Ref: [5.0:254-255], [5.1:287-288], [5.2:321-322] +// +// update-clause -> UPDATE(task-dependence-type) // since 5.0 +WRAPPER_CLASS(OmpUpdateClause, OmpTaskDependenceType); + // OpenMP Clauses struct OmpClause { UNION_CLASS_BOILERPLATE(OmpClause); @@ -4021,6 +4037,18 @@ struct OpenMPCancelConstruct { std::tuple> t; }; +// Ref: [5.0:254-255], [5.1:287-288], [5.2:322-323] +// +// depobj-construct -> DEPOBJ(depend-object) depobj-clause // since 5.0 +// depobj-clause -> depend-clause | // until 5.2 +// destroy-clause | +// update-clause +struct OpenMPDepobjConstruct { + TUPLE_CLASS_BOILERPLATE(OpenMPDepobjConstruct); + CharBlock source; + std::tuple t; +}; + // 2.17.8 flush -> FLUSH [memory-order-clause] [(variable-name-list)] struct OpenMPFlushConstruct { TUPLE_CLASS_BOILERPLATE(OpenMPFlushConstruct); @@ -4045,7 +4073,8 @@ struct OpenMPStandaloneConstruct { UNION_CLASS_BOILERPLATE(OpenMPStandaloneConstruct); CharBlock source; std::variant + OpenMPCancelConstruct, OpenMPCancellationPointConstruct, + OpenMPDepobjConstruct> u; }; diff --git a/flang/include/flang/Runtime/CUDA/kernel.h b/flang/include/flang/Runtime/CUDA/kernel.h index cf07d874a082c0..85afda09e347ae 100644 --- a/flang/include/flang/Runtime/CUDA/kernel.h +++ b/flang/include/flang/Runtime/CUDA/kernel.h @@ -15,13 +15,19 @@ extern "C" { -// This function uses intptr_t instead of CUDA's unsigned int to match +// These functions use intptr_t instead of CUDA's unsigned int to match // the type of MLIR's index type. This avoids the need for casts in the // generated MLIR code. + void RTDEF(CUFLaunchKernel)(const void *kernelName, intptr_t gridX, intptr_t gridY, intptr_t gridZ, intptr_t blockX, intptr_t blockY, intptr_t blockZ, int32_t smem, void **params, void **extra); +void RTDEF(CUFLaunchClusterKernel)(const void *kernelName, intptr_t clusterX, + intptr_t clusterY, intptr_t clusterZ, intptr_t gridX, intptr_t gridY, + intptr_t gridZ, intptr_t blockX, intptr_t blockY, intptr_t blockZ, + int32_t smem, void **params, void **extra); + } // extern "C" #endif // FORTRAN_RUNTIME_CUDA_KERNEL_H_ diff --git a/flang/include/flang/Semantics/openmp-directive-sets.h b/flang/include/flang/Semantics/openmp-directive-sets.h index 50d6d5b59ef7dd..55ef1e0ca61b9f 100644 --- a/flang/include/flang/Semantics/openmp-directive-sets.h +++ b/flang/include/flang/Semantics/openmp-directive-sets.h @@ -210,6 +210,7 @@ static const OmpDirectiveSet blockConstructSet{ Directive::OMPD_ordered, Directive::OMPD_parallel, Directive::OMPD_parallel_masked, + Directive::OMPD_parallel_master, Directive::OMPD_parallel_workshare, Directive::OMPD_scope, Directive::OMPD_single, diff --git a/flang/include/flang/Semantics/symbol.h b/flang/include/flang/Semantics/symbol.h index 0767d8ea84bc6b..b9512f33eaacd5 100644 --- a/flang/include/flang/Semantics/symbol.h +++ b/flang/include/flang/Semantics/symbol.h @@ -755,7 +755,7 @@ class Symbol { OmpDeclarativeAllocateDirective, OmpExecutableAllocateDirective, OmpDeclareSimd, OmpDeclareTarget, OmpThreadprivate, OmpDeclareReduction, OmpFlushed, OmpCriticalLock, OmpIfSpecified, OmpNone, OmpPreDetermined, - OmpImplicit); + OmpImplicit, OmpDependObject); using Flags = common::EnumSet; const Scope &owner() const { return *owner_; } diff --git a/flang/lib/Frontend/CompilerInstance.cpp b/flang/lib/Frontend/CompilerInstance.cpp index d37430e0e5773e..35c2ae3c73e69e 100644 --- a/flang/lib/Frontend/CompilerInstance.cpp +++ b/flang/lib/Frontend/CompilerInstance.cpp @@ -313,7 +313,6 @@ bool CompilerInstance::setUpTargetMachine() { << error; return false; } - // Create `TargetMachine` const auto &CGOpts = getInvocation().getCodeGenOpts(); std::optional OptLevelOrNone = @@ -322,9 +321,13 @@ bool CompilerInstance::setUpTargetMachine() { llvm::CodeGenOptLevel OptLevel = *OptLevelOrNone; std::string featuresStr = getTargetFeatures(); std::optional cm = getCodeModel(CGOpts.CodeModel); + + llvm::TargetOptions tOpts = llvm::TargetOptions(); + tOpts.EnableAIXExtendedAltivecABI = targetOpts.EnableAIXExtendedAltivecABI; + targetMachine.reset(theTarget->createTargetMachine( theTriple, /*CPU=*/targetOpts.cpu, - /*Features=*/featuresStr, llvm::TargetOptions(), + /*Features=*/featuresStr, /*Options=*/tOpts, /*Reloc::Model=*/CGOpts.getRelocationModel(), /*CodeModel::Model=*/cm, OptLevel)); assert(targetMachine && "Failed to create TargetMachine"); diff --git a/flang/lib/Frontend/CompilerInvocation.cpp b/flang/lib/Frontend/CompilerInvocation.cpp index 94d3d115417877..1214a2ea6bf1f3 100644 --- a/flang/lib/Frontend/CompilerInvocation.cpp +++ b/flang/lib/Frontend/CompilerInvocation.cpp @@ -457,6 +457,16 @@ static void parseTargetArgs(TargetOptions &opts, llvm::opt::ArgList &args) { if (args.hasArg(clang::driver::options::OPT_fdisable_integer_16)) opts.disabledIntegerKinds.push_back(16); + + if (const llvm::opt::Arg *a = + args.getLastArg(clang::driver::options::OPT_mabi_EQ)) { + llvm::StringRef V = a->getValue(); + if (V == "vec-extabi") { + opts.EnableAIXExtendedAltivecABI = true; + } else if (V == "vec-default") { + opts.EnableAIXExtendedAltivecABI = false; + } + } } // Tweak the frontend configuration based on the frontend action static void setUpFrontendBasedOnAction(FrontendOptions &opts) { diff --git a/flang/lib/Lower/OpenMP/ClauseProcessor.cpp b/flang/lib/Lower/OpenMP/ClauseProcessor.cpp index 8fb0dd4a1ec3a7..8eb1fdb4709178 100644 --- a/flang/lib/Lower/OpenMP/ClauseProcessor.cpp +++ b/flang/lib/Lower/OpenMP/ClauseProcessor.cpp @@ -137,6 +137,8 @@ genDependKindAttr(fir::FirOpBuilder &firOpBuilder, case omp::clause::Depend::TaskDependenceType::Mutexinoutset: case omp::clause::Depend::TaskDependenceType::Inoutset: case omp::clause::Depend::TaskDependenceType::Depobj: + case omp::clause::Depend::TaskDependenceType::Sink: + case omp::clause::Depend::TaskDependenceType::Source: llvm_unreachable("unhandled parser task dependence type"); break; } @@ -795,35 +797,43 @@ bool ClauseProcessor::processCopyprivate( bool ClauseProcessor::processDepend(mlir::omp::DependClauseOps &result) const { fir::FirOpBuilder &firOpBuilder = converter.getFirOpBuilder(); - return findRepeatableClause( - [&](const omp::clause::Depend &clause, const parser::CharBlock &) { - using Depend = omp::clause::Depend; - assert(std::holds_alternative(clause.u) && - "Only the form with dependence type is handled at the moment"); - auto &depType = std::get(clause.u); - auto kind = std::get(depType.t); - auto &objects = std::get(depType.t); - - mlir::omp::ClauseTaskDependAttr dependTypeOperand = - genDependKindAttr(firOpBuilder, kind); - result.dependKinds.append(objects.size(), dependTypeOperand); - - for (const omp::Object &object : objects) { - assert(object.ref() && "Expecting designator"); - - if (evaluate::ExtractSubstring(*object.ref())) { - TODO(converter.getCurrentLocation(), - "substring not supported for task depend"); - } else if (evaluate::IsArrayElement(*object.ref())) { - TODO(converter.getCurrentLocation(), - "array sections not supported for task depend"); - } + auto process = [&](const omp::clause::Depend &clause, + const parser::CharBlock &) { + using Depend = omp::clause::Depend; + if (!std::holds_alternative(clause.u)) { + TODO(converter.getCurrentLocation(), + "DEPEND clause with SINK or SOURCE is not supported yet"); + } + auto &depType = std::get(clause.u); + auto kind = std::get(depType.t); + auto &objects = std::get(depType.t); - semantics::Symbol *sym = object.sym(); - const mlir::Value variable = converter.getSymbolAddress(*sym); - result.dependVars.push_back(variable); - } - }); + if (std::get>(depType.t)) { + TODO(converter.getCurrentLocation(), + "Support for iterator modifiers is not implemented yet"); + } + mlir::omp::ClauseTaskDependAttr dependTypeOperand = + genDependKindAttr(firOpBuilder, kind); + result.dependKinds.append(objects.size(), dependTypeOperand); + + for (const omp::Object &object : objects) { + assert(object.ref() && "Expecting designator"); + + if (evaluate::ExtractSubstring(*object.ref())) { + TODO(converter.getCurrentLocation(), + "substring not supported for task depend"); + } else if (evaluate::IsArrayElement(*object.ref())) { + TODO(converter.getCurrentLocation(), + "array sections not supported for task depend"); + } + + semantics::Symbol *sym = object.sym(); + const mlir::Value variable = converter.getSymbolAddress(*sym); + result.dependVars.push_back(variable); + } + }; + + return findRepeatableClause(process); } bool ClauseProcessor::processHasDeviceAddr( diff --git a/flang/lib/Lower/OpenMP/Clauses.cpp b/flang/lib/Lower/OpenMP/Clauses.cpp index b1fa52751fbd7b..45b89de023a4bf 100644 --- a/flang/lib/Lower/OpenMP/Clauses.cpp +++ b/flang/lib/Lower/OpenMP/Clauses.cpp @@ -338,6 +338,27 @@ ReductionOperator makeReductionOperator(const parser::OmpReductionOperator &inp, inp.u); } +clause::TaskDependenceType +makeDepType(const parser::OmpTaskDependenceType &inp) { + switch (inp.v) { + case parser::OmpTaskDependenceType::Type::Depobj: + return clause::TaskDependenceType::Depobj; + case parser::OmpTaskDependenceType::Type::In: + return clause::TaskDependenceType::In; + case parser::OmpTaskDependenceType::Type::Inout: + return clause::TaskDependenceType::Inout; + // Inoutset // missing-in-parser + // Mutexinoutset // missing-in-parser + case parser::OmpTaskDependenceType::Type::Out: + return clause::TaskDependenceType::Out; + case parser::OmpTaskDependenceType::Type::Sink: + return clause::TaskDependenceType::Sink; + case parser::OmpTaskDependenceType::Type::Source: + return clause::TaskDependenceType::Source; + } + llvm_unreachable("Unexpected dependence type"); +} + // -------------------------------------------------------------------- // Actual clauses. Each T (where tomp::T exists in ClauseT) has its "make". @@ -554,18 +575,6 @@ Depend make(const parser::OmpClause::Depend &inp, // Iteration is the equivalent of parser::OmpDependSinkVec using Iteration = Doacross::Vector::value_type; // LoopIterationT - CLAUSET_ENUM_CONVERT( // - convert1, parser::OmpTaskDependenceType::Type, Depend::TaskDependenceType, - // clang-format off - MS(In, In) - MS(Out, Out) - MS(Inout, Inout) - // MS(, Mutexinoutset) // missing-in-parser - // MS(, Inputset) // missing-in-parser - // MS(, Depobj) // missing-in-parser - // clang-format on - ); - return Depend{Fortran::common::visit( // common::visitors{ // Doacross @@ -595,11 +604,16 @@ Depend make(const parser::OmpClause::Depend &inp, }, // Depend::DepType [&](const wrapped::InOut &s) -> Variant { - auto &t0 = std::get(s.t); - auto &t1 = std::get(s.t); - return Depend::DepType{{/*TaskDependenceType=*/convert1(t0.v), - /*Iterator=*/std::nullopt, - /*LocatorList=*/makeObjects(t1, semaCtx)}}; + auto &t0 = + std::get>(s.t); + auto &t1 = std::get(s.t); + auto &t2 = std::get(s.t); + + auto &&maybeIter = maybeApply( + [&](auto &&s) { return makeIterator(s, semaCtx); }, t0); + return Depend::DepType{{/*TaskDependenceType=*/makeDepType(t1), + /*Iterator=*/std::move(maybeIter), + /*LocatorList=*/makeObjects(t2, semaCtx)}}; }, }, inp.v.u)}; @@ -609,8 +623,14 @@ Depend make(const parser::OmpClause::Depend &inp, Destroy make(const parser::OmpClause::Destroy &inp, semantics::SemanticsContext &semaCtx) { - // inp -> empty - llvm_unreachable("Empty: destroy"); + // inp.v -> std::optional + auto &&maybeObject = maybeApply( + [&](const parser::OmpDestroyClause &c) { + return makeObject(c.v, semaCtx); + }, + inp.v); + + return Destroy{/*DestroyVar=*/std::move(maybeObject)}; } Detach make(const parser::OmpClause::Detach &inp, @@ -1274,8 +1294,8 @@ Uniform make(const parser::OmpClause::Uniform &inp, Update make(const parser::OmpClause::Update &inp, semantics::SemanticsContext &semaCtx) { - // inp -> empty - return Update{/*TaskDependenceType=*/std::nullopt}; + // inp.v -> parser::OmpUpdateClause + return Update{/*TaskDependenceType=*/makeDepType(inp.v.v)}; } Use make(const parser::OmpClause::Use &inp, diff --git a/flang/lib/Lower/OpenMP/Clauses.h b/flang/lib/Lower/OpenMP/Clauses.h index 1e911a20468575..51180ebfe5745e 100644 --- a/flang/lib/Lower/OpenMP/Clauses.h +++ b/flang/lib/Lower/OpenMP/Clauses.h @@ -152,6 +152,7 @@ using IteratorSpecifier = tomp::type::IteratorSpecifierT; using DefinedOperator = tomp::type::DefinedOperatorT; using ProcedureDesignator = tomp::type::ProcedureDesignatorT; using ReductionOperator = tomp::type::ReductionIdentifierT; +using TaskDependenceType = tomp::type::TaskDependenceType; // "Requires" clauses are handled early on, and the aggregated information // is stored in the Symbol details of modules, programs, and subprograms. diff --git a/flang/lib/Lower/OpenMP/OpenMP.cpp b/flang/lib/Lower/OpenMP/OpenMP.cpp index 01a40d6e2204ef..84985b880b1ec2 100644 --- a/flang/lib/Lower/OpenMP/OpenMP.cpp +++ b/flang/lib/Lower/OpenMP/OpenMP.cpp @@ -76,6 +76,18 @@ struct EntryBlockArgs { reduction.isValid() && taskReduction.isValid() && useDeviceAddr.isValid() && useDevicePtr.isValid(); } + + auto getSyms() const { + return llvm::concat( + inReduction.syms, map.syms, priv.syms, reduction.syms, + taskReduction.syms, useDeviceAddr.syms, useDevicePtr.syms); + } + + auto getVars() const { + return llvm::concat( + inReduction.vars, map.vars, priv.vars, reduction.vars, + taskReduction.vars, useDeviceAddr.vars, useDevicePtr.vars); + } }; } // namespace @@ -1506,8 +1518,7 @@ genParallelOp(lower::AbstractConverter &converter, lower::SymMap &symTable, genEntryBlock(converter, args, op->getRegion(0)); bindEntryBlockArgs( converter, llvm::cast(op), args); - return llvm::to_vector(llvm::concat( - args.priv.syms, args.reduction.syms)); + return llvm::to_vector(args.getSyms()); }; assert((!enableDelayedPrivatization || dsp) && @@ -1581,11 +1592,11 @@ genSectionsOp(lower::AbstractConverter &converter, lower::SymMap &symTable, mlir::Operation *terminator = lower::genOpenMPTerminator(builder, sectionsOp, loc); - auto reductionCallback = [&](mlir::Operation *op) { + auto genRegionEntryCB = [&](mlir::Operation *op) { genEntryBlock(converter, args, op->getRegion(0)); bindEntryBlockArgs( converter, llvm::cast(op), args); - return reductionSyms; + return llvm::to_vector(args.getSyms()); }; // Generate nested SECTION constructs. @@ -1611,7 +1622,7 @@ genSectionsOp(lower::AbstractConverter &converter, lower::SymMap &symTable, OpWithBodyGenInfo(converter, symTable, semaCtx, loc, nestedEval, llvm::omp::Directive::OMPD_section) .setClauses(§ionQueue.begin()->clauses) - .setGenRegionEntryCb(reductionCallback), + .setGenRegionEntryCb(genRegionEntryCB), sectionQueue, sectionQueue.begin()); } @@ -2699,6 +2710,21 @@ static void genOMP(lower::AbstractConverter &converter, lower::SymMap &symTable, TODO(converter.getCurrentLocation(), "OpenMPCancelConstruct"); } +static void genOMP(lower::AbstractConverter &converter, lower::SymMap &symTable, + semantics::SemanticsContext &semaCtx, + lower::pft::Evaluation &eval, + const parser::OpenMPDepobjConstruct &construct) { + // These values will be ignored until the construct itself is implemented, + // but run them anyway for the sake of testing (via a Todo test). + auto &ompObj = std::get(construct.t); + const Object &depObj = makeObject(ompObj, semaCtx); + Clause clause = makeClause(std::get(construct.t), semaCtx); + (void)depObj; + (void)clause; + + TODO(converter.getCurrentLocation(), "OpenMPDepobjConstruct"); +} + static void genOMP(lower::AbstractConverter &converter, lower::SymMap &symTable, semantics::SemanticsContext &semaCtx, lower::pft::Evaluation &eval, diff --git a/flang/lib/Optimizer/Builder/IntrinsicCall.cpp b/flang/lib/Optimizer/Builder/IntrinsicCall.cpp index 462193a850c487..7c7c8ee539111d 100644 --- a/flang/lib/Optimizer/Builder/IntrinsicCall.cpp +++ b/flang/lib/Optimizer/Builder/IntrinsicCall.cpp @@ -97,7 +97,6 @@ static bool isStaticallyPresent(const fir::ExtendedValue &exv) { /// IEEE module procedure names not yet implemented for genModuleProcTODO. static constexpr char ieee_get_underflow_mode[] = "ieee_get_underflow_mode"; -static constexpr char ieee_real[] = "ieee_real"; static constexpr char ieee_rem[] = "ieee_rem"; static constexpr char ieee_set_underflow_mode[] = "ieee_set_underflow_mode"; @@ -362,7 +361,7 @@ static constexpr IntrinsicHandler handlers[]{ {"ieee_quiet_le", &I::genIeeeQuietCompare}, {"ieee_quiet_lt", &I::genIeeeQuietCompare}, {"ieee_quiet_ne", &I::genIeeeQuietCompare}, - {"ieee_real", &I::genModuleProcTODO}, + {"ieee_real", &I::genIeeeReal}, {"ieee_rem", &I::genModuleProcTODO}, {"ieee_rint", &I::genIeeeRint}, {"ieee_round_eq", &I::genIeeeTypeCompare}, @@ -4799,6 +4798,238 @@ IntrinsicLibrary::genIeeeQuietCompare(mlir::Type resultType, return builder.create(loc, resultType, res); } +// IEEE_REAL +mlir::Value IntrinsicLibrary::genIeeeReal(mlir::Type resultType, + llvm::ArrayRef args) { + // Convert integer or real argument A to a real of a specified kind. + // Round according to the current rounding mode. + // Signal IEEE_INVALID if A is an sNaN, and return a qNaN. + // Signal IEEE_UNDERFLOW for an inexact subnormal or zero result. + // Signal IEEE_OVERFLOW if A is finite and the result is infinite. + // Signal IEEE_INEXACT for an inexact result. + // + // if (type(a) == resultType) { + // // Conversion to the same type is a nop except for sNaN processing. + // result = a + // } else { + // result = r = real(a, kind(result)) + // // Conversion to a larger type is exact. + // if (c_sizeof(a) >= c_sizeof(r)) { + // b = (a is integer) ? int(r, kind(a)) : real(r, kind(a)) + // if (a == b || isNaN(a)) { + // // a is {-0, +0, -inf, +inf, NaN} or exact; result is r + // } else { + // // odd(r) is true if the low bit of significand(r) is 1 + // // rounding mode ieee_other is an alias for mode ieee_nearest + // if (a < b) { + // if (mode == ieee_nearest && odd(r)) result = ieee_next_down(r) + // if (mode == ieee_other && odd(r)) result = ieee_next_down(r) + // if (mode == ieee_to_zero && a > 0) result = ieee_next_down(r) + // if (mode == ieee_away && a < 0) result = ieee_next_down(r) + // if (mode == ieee_down) result = ieee_next_down(r) + // } else { // a > b + // if (mode == ieee_nearest && odd(r)) result = ieee_next_up(r) + // if (mode == ieee_other && odd(r)) result = ieee_next_up(r) + // if (mode == ieee_to_zero && a < 0) result = ieee_next_up(r) + // if (mode == ieee_away && a > 0) result = ieee_next_up(r) + // if (mode == ieee_up) result = ieee_next_up(r) + // } + // } + // } + // } + + assert(args.size() == 2); + mlir::Type i1Ty = builder.getI1Type(); + mlir::Type f32Ty = mlir::FloatType::getF32(builder.getContext()); + mlir::Value a = args[0]; + mlir::Type aType = a.getType(); + + // If the argument is an sNaN, raise an invalid exception and return a qNaN. + // Otherwise return the argument. + auto processSnan = [&](mlir::Value x) { + fir::IfOp ifOp = builder.create(loc, resultType, + genIsFPClass(i1Ty, x, snanTest), + /*withElseRegion=*/true); + builder.setInsertionPointToStart(&ifOp.getThenRegion().front()); + genRaiseExcept(_FORTRAN_RUNTIME_IEEE_INVALID); + builder.create(loc, genQNan(resultType)); + builder.setInsertionPointToStart(&ifOp.getElseRegion().front()); + builder.create(loc, x); + builder.setInsertionPointAfter(ifOp); + return ifOp.getResult(0); + }; + + // Conversion is a nop, except that A may be an sNaN. + if (resultType == aType) + return processSnan(a); + + // Can't directly convert between kind=2 and kind=3. + mlir::Value r, r1; + if ((aType.isBF16() && resultType.isF16()) || + (aType.isF16() && resultType.isBF16())) { + a = builder.createConvert(loc, f32Ty, a); + aType = f32Ty; + } + r = builder.create(loc, resultType, a); + + mlir::IntegerType aIntType = mlir::dyn_cast(aType); + mlir::FloatType aFloatType = mlir::dyn_cast(aType); + mlir::FloatType resultFloatType = mlir::dyn_cast(resultType); + + // Conversion from a smaller type to a larger type is exact. + if ((aIntType ? aIntType.getWidth() : aFloatType.getWidth()) < + resultFloatType.getWidth()) + return aIntType ? r : processSnan(r); + + // A possibly inexact conversion result may need to be rounded up or down. + mlir::Value b = builder.create(loc, aType, r); + mlir::Value aEqB; + if (aIntType) + aEqB = builder.create( + loc, mlir::arith::CmpIPredicate::eq, a, b); + else + aEqB = builder.create( + loc, mlir::arith::CmpFPredicate::UEQ, a, b); + + // [a == b] a is a NaN or r is exact (a may be -0, +0, -inf, +inf) -- return r + fir::IfOp ifOp1 = builder.create(loc, resultType, aEqB, + /*withElseRegion=*/true); + builder.setInsertionPointToStart(&ifOp1.getThenRegion().front()); + builder.create(loc, aIntType ? r : processSnan(r)); + + // Code common to (a < b) and (a > b) branches. + builder.setInsertionPointToStart(&ifOp1.getElseRegion().front()); + mlir::func::FuncOp getRound = fir::factory::getLlvmGetRounding(builder); + mlir::Value mode = builder.create(loc, getRound).getResult(0); + mlir::Value aIsNegative, aIsPositive; + if (aIntType) { + mlir::Value zero = builder.createIntegerConstant(loc, aIntType, 0); + aIsNegative = builder.create( + loc, mlir::arith::CmpIPredicate::slt, a, zero); + aIsPositive = builder.create( + loc, mlir::arith::CmpIPredicate::sgt, a, zero); + } else { + mlir::Value zero = builder.createRealZeroConstant(loc, aFloatType); + aIsNegative = builder.create( + loc, mlir::arith::CmpFPredicate::OLT, a, zero); + aIsPositive = builder.create( + loc, mlir::arith::CmpFPredicate::OGT, a, zero); + } + mlir::Type resultIntType = builder.getIntegerType(resultFloatType.getWidth()); + mlir::Value resultCast = + builder.create(loc, resultIntType, r); + mlir::Value one = builder.createIntegerConstant(loc, resultIntType, 1); + mlir::Value rIsOdd = builder.create( + loc, i1Ty, builder.create(loc, resultCast, one)); + // Check for a rounding mode match. + auto match = [&](int m) { + return builder.create( + loc, mlir::arith::CmpIPredicate::eq, mode, + builder.createIntegerConstant(loc, mode.getType(), m)); + }; + mlir::Value roundToNearestBit = builder.create( + loc, + // IEEE_OTHER is an alias for IEEE_NEAREST. + match(_FORTRAN_RUNTIME_IEEE_NEAREST), match(_FORTRAN_RUNTIME_IEEE_OTHER)); + mlir::Value roundToNearest = + builder.create(loc, roundToNearestBit, rIsOdd); + mlir::Value roundToZeroBit = match(_FORTRAN_RUNTIME_IEEE_TO_ZERO); + mlir::Value roundAwayBit = match(_FORTRAN_RUNTIME_IEEE_AWAY); + mlir::Value roundToZero, roundAway, mustAdjust; + fir::IfOp adjustIfOp; + mlir::Value aLtB; + if (aIntType) + aLtB = builder.create( + loc, mlir::arith::CmpIPredicate::slt, a, b); + else + aLtB = builder.create( + loc, mlir::arith::CmpFPredicate::OLT, a, b); + mlir::Value upResult = + builder.create(loc, resultCast, one); + mlir::Value downResult = + builder.create(loc, resultCast, one); + + // (a < b): r is inexact -- return r or ieee_next_down(r) + fir::IfOp ifOp2 = builder.create(loc, resultType, aLtB, + /*withElseRegion=*/true); + builder.setInsertionPointToStart(&ifOp2.getThenRegion().front()); + roundToZero = + builder.create(loc, roundToZeroBit, aIsPositive); + roundAway = + builder.create(loc, roundAwayBit, aIsNegative); + mlir::Value roundDown = match(_FORTRAN_RUNTIME_IEEE_DOWN); + mustAdjust = + builder.create(loc, roundToNearest, roundToZero); + mustAdjust = builder.create(loc, mustAdjust, roundAway); + mustAdjust = builder.create(loc, mustAdjust, roundDown); + adjustIfOp = builder.create(loc, resultType, mustAdjust, + /*withElseRegion=*/true); + builder.setInsertionPointToStart(&adjustIfOp.getThenRegion().front()); + if (resultType.isF80()) + r1 = fir::runtime::genNearest(builder, loc, r, + builder.createBool(loc, false)); + else + r1 = builder.create( + loc, resultType, + builder.create(loc, aIsNegative, upResult, + downResult)); + builder.create(loc, r1); + builder.setInsertionPointToStart(&adjustIfOp.getElseRegion().front()); + builder.create(loc, r); + builder.setInsertionPointAfter(adjustIfOp); + builder.create(loc, adjustIfOp.getResult(0)); + + // (a > b): r is inexact -- return r or ieee_next_up(r) + builder.setInsertionPointToStart(&ifOp2.getElseRegion().front()); + roundToZero = + builder.create(loc, roundToZeroBit, aIsNegative); + roundAway = + builder.create(loc, roundAwayBit, aIsPositive); + mlir::Value roundUp = match(_FORTRAN_RUNTIME_IEEE_UP); + mustAdjust = + builder.create(loc, roundToNearest, roundToZero); + mustAdjust = builder.create(loc, mustAdjust, roundAway); + mustAdjust = builder.create(loc, mustAdjust, roundUp); + adjustIfOp = builder.create(loc, resultType, mustAdjust, + /*withElseRegion=*/true); + builder.setInsertionPointToStart(&adjustIfOp.getThenRegion().front()); + if (resultType.isF80()) + r1 = fir::runtime::genNearest(builder, loc, r, + builder.createBool(loc, true)); + else + r1 = builder.create( + loc, resultType, + builder.create(loc, aIsPositive, upResult, + downResult)); + builder.create(loc, r1); + builder.setInsertionPointToStart(&adjustIfOp.getElseRegion().front()); + builder.create(loc, r); + builder.setInsertionPointAfter(adjustIfOp); + builder.create(loc, adjustIfOp.getResult(0)); + + // Generate exceptions for (a < b) and (a > b) branches. + builder.setInsertionPointAfter(ifOp2); + r = ifOp2.getResult(0); + fir::IfOp exceptIfOp1 = builder.create( + loc, genIsFPClass(i1Ty, r, infiniteTest), /*withElseRegion=*/true); + builder.setInsertionPointToStart(&exceptIfOp1.getThenRegion().front()); + genRaiseExcept(_FORTRAN_RUNTIME_IEEE_OVERFLOW | + _FORTRAN_RUNTIME_IEEE_INEXACT); + builder.setInsertionPointToStart(&exceptIfOp1.getElseRegion().front()); + fir::IfOp exceptIfOp2 = builder.create( + loc, genIsFPClass(i1Ty, r, subnormalTest | zeroTest), + /*withElseRegion=*/true); + builder.setInsertionPointToStart(&exceptIfOp2.getThenRegion().front()); + genRaiseExcept(_FORTRAN_RUNTIME_IEEE_UNDERFLOW | + _FORTRAN_RUNTIME_IEEE_INEXACT); + builder.setInsertionPointToStart(&exceptIfOp2.getElseRegion().front()); + genRaiseExcept(_FORTRAN_RUNTIME_IEEE_INEXACT); + builder.setInsertionPointAfter(exceptIfOp1); + builder.create(loc, ifOp2.getResult(0)); + builder.setInsertionPointAfter(ifOp1); + return ifOp1.getResult(0); +} + // IEEE_RINT mlir::Value IntrinsicLibrary::genIeeeRint(mlir::Type resultType, llvm::ArrayRef args) { diff --git a/flang/lib/Optimizer/Transforms/CUFAddConstructor.cpp b/flang/lib/Optimizer/Transforms/CUFAddConstructor.cpp index 4da06be8ef7dd9..7cdb2f7ffe27d9 100644 --- a/flang/lib/Optimizer/Transforms/CUFAddConstructor.cpp +++ b/flang/lib/Optimizer/Transforms/CUFAddConstructor.cpp @@ -6,15 +6,23 @@ // //===----------------------------------------------------------------------===// +#include "flang/Optimizer/Builder/BoxValue.h" #include "flang/Optimizer/Builder/FIRBuilder.h" +#include "flang/Optimizer/Builder/Runtime/RTBuilder.h" +#include "flang/Optimizer/Builder/Todo.h" +#include "flang/Optimizer/CodeGen/Target.h" #include "flang/Optimizer/Dialect/CUF/CUFOps.h" #include "flang/Optimizer/Dialect/FIRAttr.h" #include "flang/Optimizer/Dialect/FIRDialect.h" +#include "flang/Optimizer/Dialect/FIROps.h" #include "flang/Optimizer/Dialect/FIROpsSupport.h" +#include "flang/Optimizer/Support/DataLayout.h" #include "flang/Optimizer/Transforms/CUFCommon.h" +#include "flang/Runtime/CUDA/registration.h" #include "flang/Runtime/entry-names.h" #include "mlir/Dialect/GPU/IR/GPUDialect.h" #include "mlir/Dialect/LLVMIR/LLVMDialect.h" +#include "mlir/IR/Value.h" #include "mlir/Pass/Pass.h" #include "llvm/ADT/SmallVector.h" @@ -23,6 +31,8 @@ namespace fir { #include "flang/Optimizer/Transforms/Passes.h.inc" } // namespace fir +using namespace Fortran::runtime::cuda; + namespace { static constexpr llvm::StringRef cudaFortranCtorName{ @@ -34,13 +44,23 @@ struct CUFAddConstructor void runOnOperation() override { mlir::ModuleOp mod = getOperation(); mlir::SymbolTable symTab(mod); - mlir::OpBuilder builder{mod.getBodyRegion()}; + mlir::OpBuilder opBuilder{mod.getBodyRegion()}; + fir::FirOpBuilder builder(opBuilder, mod); + fir::KindMapping kindMap{fir::getKindMapping(mod)}; builder.setInsertionPointToEnd(mod.getBody()); mlir::Location loc = mod.getLoc(); auto *ctx = mod.getContext(); auto voidTy = mlir::LLVM::LLVMVoidType::get(ctx); + auto idxTy = builder.getIndexType(); auto funcTy = mlir::LLVM::LLVMFunctionType::get(voidTy, {}, /*isVarArg=*/false); + std::optional dl = + fir::support::getOrSetDataLayout(mod, /*allowDefaultLayout=*/false); + if (!dl) { + mlir::emitError(mod.getLoc(), + "data layout attribute is required to perform " + + getName() + "pass"); + } // Symbol reference to CUFRegisterAllocator. builder.setInsertionPointToEnd(mod.getBody()); @@ -58,12 +78,13 @@ struct CUFAddConstructor builder.setInsertionPointToStart(func.addEntryBlock(builder)); builder.create(loc, funcTy, cufRegisterAllocatorRef); - // Register kernels auto gpuMod = symTab.lookup(cudaDeviceModuleName); if (gpuMod) { auto llvmPtrTy = mlir::LLVM::LLVMPointerType::get(ctx); auto registeredMod = builder.create( loc, llvmPtrTy, mlir::SymbolRefAttr::get(ctx, gpuMod.getName())); + + // Register kernels for (auto func : gpuMod.getOps()) { if (func.isKernel()) { auto kernelName = mlir::SymbolRefAttr::get( @@ -72,12 +93,55 @@ struct CUFAddConstructor builder.create(loc, kernelName, registeredMod); } } + + // Register variables + for (fir::GlobalOp globalOp : mod.getOps()) { + auto attr = globalOp.getDataAttrAttr(); + if (!attr) + continue; + + mlir::func::FuncOp func; + switch (attr.getValue()) { + case cuf::DataAttribute::Device: + case cuf::DataAttribute::Constant: { + func = fir::runtime::getRuntimeFunc( + loc, builder); + auto fTy = func.getFunctionType(); + + // Global variable name + std::string gblNameStr = globalOp.getSymbol().getValue().str(); + gblNameStr += '\0'; + mlir::Value gblName = fir::getBase( + fir::factory::createStringLiteral(builder, loc, gblNameStr)); + + // Global variable size + auto sizeAndAlign = fir::getTypeSizeAndAlignmentOrCrash( + loc, globalOp.getType(), *dl, kindMap); + auto size = + builder.createIntegerConstant(loc, idxTy, sizeAndAlign.first); + + // Global variable address + mlir::Value addr = builder.create( + loc, globalOp.resultType(), globalOp.getSymbol()); + + llvm::SmallVector args{fir::runtime::createArguments( + builder, loc, fTy, registeredMod, addr, gblName, size)}; + builder.create(loc, func, args); + } break; + case cuf::DataAttribute::Managed: + TODO(loc, "registration of managed variables"); + default: + break; + } + if (!func) + continue; + } } builder.create(loc, mlir::ValueRange{}); // Create the llvm.global_ctor with the function. - // TODO: We might want to have a utility that retrieve it if already created - // and adds new functions. + // TODO: We might want to have a utility that retrieve it if already + // created and adds new functions. builder.setInsertionPointToEnd(mod.getBody()); llvm::SmallVector funcs; funcs.push_back( diff --git a/flang/lib/Optimizer/Transforms/CUFGPUToLLVMConversion.cpp b/flang/lib/Optimizer/Transforms/CUFGPUToLLVMConversion.cpp index 5645ce6e6858c8..c64f35542a6e59 100644 --- a/flang/lib/Optimizer/Transforms/CUFGPUToLLVMConversion.cpp +++ b/flang/lib/Optimizer/Transforms/CUFGPUToLLVMConversion.cpp @@ -76,11 +76,6 @@ struct GPULaunchKernelConversion mlir::LogicalResult matchAndRewrite(mlir::gpu::LaunchFuncOp op, OpAdaptor adaptor, mlir::ConversionPatternRewriter &rewriter) const override { - - if (op.hasClusterSize()) { - return mlir::failure(); - } - mlir::Location loc = op.getLoc(); auto *ctx = rewriter.getContext(); mlir::ModuleOp mod = op->getParentOfType(); @@ -107,37 +102,65 @@ struct GPULaunchKernelConversion rewriter.create(loc, ptrTy, kernel.getName()); } - auto funcOp = mod.lookupSymbol( - RTNAME_STRING(CUFLaunchKernel)); - auto llvmIntPtrType = mlir::IntegerType::get( ctx, this->getTypeConverter()->getPointerBitwidth(0)); auto voidTy = mlir::LLVM::LLVMVoidType::get(ctx); - auto funcTy = mlir::LLVM::LLVMFunctionType::get( - voidTy, - {ptrTy, llvmIntPtrType, llvmIntPtrType, llvmIntPtrType, llvmIntPtrType, - llvmIntPtrType, llvmIntPtrType, i32Ty, ptrTy, ptrTy}, - /*isVarArg=*/false); - - auto cufLaunchKernel = mlir::SymbolRefAttr::get( - mod.getContext(), RTNAME_STRING(CUFLaunchKernel)); - if (!funcOp) { - mlir::OpBuilder::InsertionGuard insertGuard(rewriter); - rewriter.setInsertionPointToStart(mod.getBody()); - auto launchKernelFuncOp = rewriter.create( - loc, RTNAME_STRING(CUFLaunchKernel), funcTy); - launchKernelFuncOp.setVisibility(mlir::SymbolTable::Visibility::Private); - } mlir::Value nullPtr = rewriter.create(loc, ptrTy); - rewriter.replaceOpWithNewOp( - op, funcTy, cufLaunchKernel, - mlir::ValueRange{kernelPtr, adaptor.getGridSizeX(), - adaptor.getGridSizeY(), adaptor.getGridSizeZ(), - adaptor.getBlockSizeX(), adaptor.getBlockSizeY(), - adaptor.getBlockSizeZ(), dynamicMemorySize, kernelArgs, - nullPtr}); + if (op.hasClusterSize()) { + auto funcOp = mod.lookupSymbol( + RTNAME_STRING(CUFLaunchClusterKernel)); + auto funcTy = mlir::LLVM::LLVMFunctionType::get( + voidTy, + {ptrTy, llvmIntPtrType, llvmIntPtrType, llvmIntPtrType, + llvmIntPtrType, llvmIntPtrType, llvmIntPtrType, llvmIntPtrType, + llvmIntPtrType, llvmIntPtrType, i32Ty, ptrTy, ptrTy}, + /*isVarArg=*/false); + auto cufLaunchClusterKernel = mlir::SymbolRefAttr::get( + mod.getContext(), RTNAME_STRING(CUFLaunchClusterKernel)); + if (!funcOp) { + mlir::OpBuilder::InsertionGuard insertGuard(rewriter); + rewriter.setInsertionPointToStart(mod.getBody()); + auto launchKernelFuncOp = rewriter.create( + loc, RTNAME_STRING(CUFLaunchClusterKernel), funcTy); + launchKernelFuncOp.setVisibility( + mlir::SymbolTable::Visibility::Private); + } + rewriter.replaceOpWithNewOp( + op, funcTy, cufLaunchClusterKernel, + mlir::ValueRange{kernelPtr, adaptor.getClusterSizeX(), + adaptor.getClusterSizeY(), adaptor.getClusterSizeZ(), + adaptor.getGridSizeX(), adaptor.getGridSizeY(), + adaptor.getGridSizeZ(), adaptor.getBlockSizeX(), + adaptor.getBlockSizeY(), adaptor.getBlockSizeZ(), + dynamicMemorySize, kernelArgs, nullPtr}); + } else { + auto funcOp = mod.lookupSymbol( + RTNAME_STRING(CUFLaunchKernel)); + auto funcTy = mlir::LLVM::LLVMFunctionType::get( + voidTy, + {ptrTy, llvmIntPtrType, llvmIntPtrType, llvmIntPtrType, + llvmIntPtrType, llvmIntPtrType, llvmIntPtrType, i32Ty, ptrTy, ptrTy}, + /*isVarArg=*/false); + auto cufLaunchKernel = mlir::SymbolRefAttr::get( + mod.getContext(), RTNAME_STRING(CUFLaunchKernel)); + if (!funcOp) { + mlir::OpBuilder::InsertionGuard insertGuard(rewriter); + rewriter.setInsertionPointToStart(mod.getBody()); + auto launchKernelFuncOp = rewriter.create( + loc, RTNAME_STRING(CUFLaunchKernel), funcTy); + launchKernelFuncOp.setVisibility( + mlir::SymbolTable::Visibility::Private); + } + rewriter.replaceOpWithNewOp( + op, funcTy, cufLaunchKernel, + mlir::ValueRange{kernelPtr, adaptor.getGridSizeX(), + adaptor.getGridSizeY(), adaptor.getGridSizeZ(), + adaptor.getBlockSizeX(), adaptor.getBlockSizeY(), + adaptor.getBlockSizeZ(), dynamicMemorySize, + kernelArgs, nullPtr}); + } return mlir::success(); } diff --git a/flang/lib/Optimizer/Transforms/CUFOpConversion.cpp b/flang/lib/Optimizer/Transforms/CUFOpConversion.cpp index 9c2b882c7f46fe..f1f3a95b220df5 100644 --- a/flang/lib/Optimizer/Transforms/CUFOpConversion.cpp +++ b/flang/lib/Optimizer/Transforms/CUFOpConversion.cpp @@ -15,6 +15,7 @@ #include "flang/Optimizer/Dialect/FIROps.h" #include "flang/Optimizer/HLFIR/HLFIROps.h" #include "flang/Optimizer/Support/DataLayout.h" +#include "flang/Optimizer/Transforms/CUFCommon.h" #include "flang/Runtime/CUDA/allocatable.h" #include "flang/Runtime/CUDA/common.h" #include "flang/Runtime/CUDA/descriptor.h" @@ -111,7 +112,7 @@ mlir::Value getDeviceAddress(mlir::PatternRewriter &rewriter, switch (attr.getValue()) { case cuf::DataAttribute::Device: case cuf::DataAttribute::Managed: - case cuf::DataAttribute::Pinned: + case cuf::DataAttribute::Constant: isDevGlobal = true; break; default: @@ -172,7 +173,7 @@ static mlir::LogicalResult convertOpToCall(OpTy op, return mlir::success(); } -struct CufAllocateOpConversion +struct CUFAllocateOpConversion : public mlir::OpRewritePattern { using OpRewritePattern::OpRewritePattern; @@ -215,7 +216,7 @@ struct CufAllocateOpConversion } }; -struct CufDeallocateOpConversion +struct CUFDeallocateOpConversion : public mlir::OpRewritePattern { using OpRewritePattern::OpRewritePattern; @@ -283,10 +284,10 @@ static int computeWidth(mlir::Location loc, mlir::Type type, return width; } -struct CufAllocOpConversion : public mlir::OpRewritePattern { +struct CUFAllocOpConversion : public mlir::OpRewritePattern { using OpRewritePattern::OpRewritePattern; - CufAllocOpConversion(mlir::MLIRContext *context, mlir::DataLayout *dl, + CUFAllocOpConversion(mlir::MLIRContext *context, mlir::DataLayout *dl, const fir::LLVMTypeConverter *typeConverter) : OpRewritePattern(context), dl{dl}, typeConverter{typeConverter} {} @@ -379,7 +380,7 @@ struct CufAllocOpConversion : public mlir::OpRewritePattern { const fir::LLVMTypeConverter *typeConverter; }; -struct CufFreeOpConversion : public mlir::OpRewritePattern { +struct CUFFreeOpConversion : public mlir::OpRewritePattern { using OpRewritePattern::OpRewritePattern; mlir::LogicalResult @@ -428,11 +429,11 @@ struct CufFreeOpConversion : public mlir::OpRewritePattern { } }; -struct CufDataTransferOpConversion +struct CUFDataTransferOpConversion : public mlir::OpRewritePattern { using OpRewritePattern::OpRewritePattern; - CufDataTransferOpConversion(mlir::MLIRContext *context, + CUFDataTransferOpConversion(mlir::MLIRContext *context, const mlir::SymbolTable &symtab) : OpRewritePattern(context), symtab{symtab} {} @@ -620,6 +621,69 @@ struct CufDataTransferOpConversion const mlir::SymbolTable &symtab; }; +struct CUFLaunchOpConversion + : public mlir::OpRewritePattern { +public: + using OpRewritePattern::OpRewritePattern; + + CUFLaunchOpConversion(mlir::MLIRContext *context, + const mlir::SymbolTable &symTab) + : OpRewritePattern(context), symTab{symTab} {} + + mlir::LogicalResult + matchAndRewrite(cuf::KernelLaunchOp op, + mlir::PatternRewriter &rewriter) const override { + mlir::Location loc = op.getLoc(); + auto idxTy = mlir::IndexType::get(op.getContext()); + auto zero = rewriter.create( + loc, rewriter.getIntegerType(32), rewriter.getI32IntegerAttr(0)); + auto gridSizeX = + rewriter.create(loc, idxTy, op.getGridX()); + auto gridSizeY = + rewriter.create(loc, idxTy, op.getGridY()); + auto gridSizeZ = + rewriter.create(loc, idxTy, op.getGridZ()); + auto blockSizeX = + rewriter.create(loc, idxTy, op.getBlockX()); + auto blockSizeY = + rewriter.create(loc, idxTy, op.getBlockY()); + auto blockSizeZ = + rewriter.create(loc, idxTy, op.getBlockZ()); + auto kernelName = mlir::SymbolRefAttr::get( + rewriter.getStringAttr(cudaDeviceModuleName), + {mlir::SymbolRefAttr::get( + rewriter.getContext(), + op.getCallee().getLeafReference().getValue())}); + mlir::Value clusterDimX, clusterDimY, clusterDimZ; + if (auto funcOp = symTab.lookup( + op.getCallee().getLeafReference())) { + if (auto clusterDimsAttr = funcOp->getAttrOfType( + cuf::getClusterDimsAttrName())) { + clusterDimX = rewriter.create( + loc, clusterDimsAttr.getX().getInt()); + clusterDimY = rewriter.create( + loc, clusterDimsAttr.getY().getInt()); + clusterDimZ = rewriter.create( + loc, clusterDimsAttr.getZ().getInt()); + } + } + auto gpuLaunchOp = rewriter.create( + loc, kernelName, mlir::gpu::KernelDim3{gridSizeX, gridSizeY, gridSizeZ}, + mlir::gpu::KernelDim3{blockSizeX, blockSizeY, blockSizeZ}, zero, + op.getArgs()); + if (clusterDimX && clusterDimY && clusterDimZ) { + gpuLaunchOp.getClusterSizeXMutable().assign(clusterDimX); + gpuLaunchOp.getClusterSizeYMutable().assign(clusterDimY); + gpuLaunchOp.getClusterSizeZMutable().assign(clusterDimZ); + } + rewriter.replaceOp(op, gpuLaunchOp); + return mlir::success(); + } + +private: + const mlir::SymbolTable &symTab; +}; + class CUFOpConversion : public fir::impl::CUFOpConversionBase { public: void runOnOperation() override { @@ -637,7 +701,8 @@ class CUFOpConversion : public fir::impl::CUFOpConversionBase { fir::support::getOrSetDataLayout(module, /*allowDefaultLayout=*/false); fir::LLVMTypeConverter typeConverter(module, /*applyTBAA=*/false, /*forceUnifiedTBAATree=*/false, *dl); - target.addLegalDialect(); + target.addLegalDialect(); cuf::populateCUFToFIRConversionPatterns(typeConverter, *dl, symtab, patterns); if (mlir::failed(mlir::applyPartialConversion(getOperation(), target, @@ -653,8 +718,9 @@ class CUFOpConversion : public fir::impl::CUFOpConversionBase { void cuf::populateCUFToFIRConversionPatterns( const fir::LLVMTypeConverter &converter, mlir::DataLayout &dl, const mlir::SymbolTable &symtab, mlir::RewritePatternSet &patterns) { - patterns.insert(patterns.getContext(), &dl, &converter); - patterns.insert(patterns.getContext()); - patterns.insert(patterns.getContext(), symtab); + patterns.insert(patterns.getContext(), &dl, &converter); + patterns.insert(patterns.getContext()); + patterns.insert( + patterns.getContext(), symtab); } diff --git a/flang/lib/Optimizer/Transforms/DebugTypeGenerator.cpp b/flang/lib/Optimizer/Transforms/DebugTypeGenerator.cpp index 1ab6c76dae8eda..a070c87137fa16 100644 --- a/flang/lib/Optimizer/Transforms/DebugTypeGenerator.cpp +++ b/flang/lib/Optimizer/Transforms/DebugTypeGenerator.cpp @@ -271,6 +271,19 @@ static bool canCacheThisType(mlir::LLVM::DICompositeTypeAttr comTy) { return true; } +std::pair +DebugTypeGenerator::getFieldSizeAndAlign(mlir::Type fieldTy) { + mlir::Type llvmTy; + if (auto boxTy = mlir::dyn_cast_or_null(fieldTy)) + llvmTy = llvmTypeConverter.convertBoxTypeAsStruct(boxTy, getBoxRank(boxTy)); + else + llvmTy = llvmTypeConverter.convertType(fieldTy); + + uint64_t byteSize = dataLayout->getTypeSize(llvmTy); + unsigned short byteAlign = dataLayout->getTypeABIAlignment(llvmTy); + return std::pair{byteSize, byteAlign}; +} + mlir::LLVM::DITypeAttr DebugTypeGenerator::convertRecordType( fir::RecordType Ty, mlir::LLVM::DIFileAttr fileAttr, mlir::LLVM::DIScopeAttr scope, fir::cg::XDeclareOp declOp) { @@ -303,15 +316,7 @@ mlir::LLVM::DITypeAttr DebugTypeGenerator::convertRecordType( mlir::IntegerType intTy = mlir::IntegerType::get(context, 64); std::uint64_t offset = 0; for (auto [fieldName, fieldTy] : Ty.getTypeList()) { - mlir::Type llvmTy; - if (auto boxTy = mlir::dyn_cast_or_null(fieldTy)) - llvmTy = - llvmTypeConverter.convertBoxTypeAsStruct(boxTy, getBoxRank(boxTy)); - else - llvmTy = llvmTypeConverter.convertType(fieldTy); - - uint64_t byteSize = dataLayout->getTypeSize(llvmTy); - unsigned short byteAlign = dataLayout->getTypeABIAlignment(llvmTy); + auto [byteSize, byteAlign] = getFieldSizeAndAlign(fieldTy); std::optional> lowerBounds = fir::getComponentLowerBoundsIfNonDefault(Ty, fieldName, module, symbolTable); @@ -368,6 +373,42 @@ mlir::LLVM::DITypeAttr DebugTypeGenerator::convertRecordType( return finalAttr; } +mlir::LLVM::DITypeAttr DebugTypeGenerator::convertTupleType( + mlir::TupleType Ty, mlir::LLVM::DIFileAttr fileAttr, + mlir::LLVM::DIScopeAttr scope, fir::cg::XDeclareOp declOp) { + // Check if this type has already been converted. + auto iter = typeCache.find(Ty); + if (iter != typeCache.end()) + return iter->second; + + llvm::SmallVector elements; + mlir::MLIRContext *context = module.getContext(); + + std::uint64_t offset = 0; + for (auto fieldTy : Ty.getTypes()) { + auto [byteSize, byteAlign] = getFieldSizeAndAlign(fieldTy); + mlir::LLVM::DITypeAttr elemTy = + convertType(fieldTy, fileAttr, scope, /*declOp=*/nullptr); + offset = llvm::alignTo(offset, byteAlign); + mlir::LLVM::DIDerivedTypeAttr tyAttr = mlir::LLVM::DIDerivedTypeAttr::get( + context, llvm::dwarf::DW_TAG_member, mlir::StringAttr::get(context, ""), + elemTy, byteSize * 8, byteAlign * 8, offset * 8, + /*optional
=*/std::nullopt, + /*extra data=*/nullptr); + elements.push_back(tyAttr); + offset += llvm::alignTo(byteSize, byteAlign); + } + + auto typeAttr = mlir::LLVM::DICompositeTypeAttr::get( + context, llvm::dwarf::DW_TAG_structure_type, + mlir::StringAttr::get(context, ""), fileAttr, /*line=*/0, scope, + /*baseType=*/nullptr, mlir::LLVM::DIFlags::Zero, offset * 8, + /*alignInBits=*/0, elements, /*dataLocation=*/nullptr, /*rank=*/nullptr, + /*allocated=*/nullptr, /*associated=*/nullptr); + typeCache[Ty] = typeAttr; + return typeAttr; +} + mlir::LLVM::DITypeAttr DebugTypeGenerator::convertSequenceType( fir::SequenceType seqTy, mlir::LLVM::DIFileAttr fileAttr, mlir::LLVM::DIScopeAttr scope, fir::cg::XDeclareOp declOp) { @@ -574,6 +615,8 @@ DebugTypeGenerator::convertType(mlir::Type Ty, mlir::LLVM::DIFileAttr fileAttr, /*hasDescriptor=*/false); } else if (auto recTy = mlir::dyn_cast_or_null(Ty)) { return convertRecordType(recTy, fileAttr, scope, declOp); + } else if (auto tupleTy = mlir::dyn_cast_if_present(Ty)) { + return convertTupleType(tupleTy, fileAttr, scope, declOp); } else if (auto refTy = mlir::dyn_cast_if_present(Ty)) { auto elTy = refTy.getEleTy(); return convertPointerLikeType(elTy, fileAttr, scope, declOp, @@ -581,6 +624,10 @@ DebugTypeGenerator::convertType(mlir::Type Ty, mlir::LLVM::DIFileAttr fileAttr, /*genAssociated=*/false); } else if (auto vecTy = mlir::dyn_cast_or_null(Ty)) { return convertVectorType(vecTy, fileAttr, scope, declOp); + } else if (mlir::isa(Ty)) { + return genBasicType(context, mlir::StringAttr::get(context, "integer"), + llvmTypeConverter.getIndexTypeBitwidth(), + llvm::dwarf::DW_ATE_signed); } else if (auto boxTy = mlir::dyn_cast_or_null(Ty)) { auto elTy = boxTy.getElementType(); if (auto seqTy = mlir::dyn_cast_or_null(elTy)) diff --git a/flang/lib/Optimizer/Transforms/DebugTypeGenerator.h b/flang/lib/Optimizer/Transforms/DebugTypeGenerator.h index eeefb6c463d936..c1fce4bdae5ce5 100644 --- a/flang/lib/Optimizer/Transforms/DebugTypeGenerator.h +++ b/flang/lib/Optimizer/Transforms/DebugTypeGenerator.h @@ -39,6 +39,10 @@ class DebugTypeGenerator { mlir::LLVM::DIFileAttr fileAttr, mlir::LLVM::DIScopeAttr scope, fir::cg::XDeclareOp declOp); + mlir::LLVM::DITypeAttr convertTupleType(mlir::TupleType Ty, + mlir::LLVM::DIFileAttr fileAttr, + mlir::LLVM::DIScopeAttr scope, + fir::cg::XDeclareOp declOp); mlir::LLVM::DITypeAttr convertSequenceType(fir::SequenceType seqTy, mlir::LLVM::DIFileAttr fileAttr, mlir::LLVM::DIScopeAttr scope, @@ -73,6 +77,8 @@ class DebugTypeGenerator { mlir::LLVM::DIFileAttr fileAttr, mlir::LLVM::DIScopeAttr scope, fir::cg::XDeclareOp declOp); + std::pair + getFieldSizeAndAlign(mlir::Type fieldTy); mlir::ModuleOp module; mlir::SymbolTable *symbolTable; diff --git a/flang/lib/Parser/openmp-parsers.cpp b/flang/lib/Parser/openmp-parsers.cpp index 3ca4e93a6c9b93..6fde70fc5c3878 100644 --- a/flang/lib/Parser/openmp-parsers.cpp +++ b/flang/lib/Parser/openmp-parsers.cpp @@ -366,9 +366,12 @@ TYPE_PARSER( construct(name, maybe(Parser{}))) TYPE_PARSER(construct( + "DEPOBJ" >> pure(OmpTaskDependenceType::Type::Depobj) || "IN"_id >> pure(OmpTaskDependenceType::Type::In) || "INOUT" >> pure(OmpTaskDependenceType::Type::Inout) || - "OUT" >> pure(OmpTaskDependenceType::Type::Out))) + "OUT" >> pure(OmpTaskDependenceType::Type::Out) || + "SINK" >> pure(OmpTaskDependenceType::Type::Sink) || + "SOURCE" >> pure(OmpTaskDependenceType::Type::Source))) TYPE_CONTEXT_PARSER("Omp Depend clause"_en_US, construct(construct( @@ -376,7 +379,8 @@ TYPE_CONTEXT_PARSER("Omp Depend clause"_en_US, construct( construct("SOURCE"_tok)) || construct(construct( - Parser{}, ":" >> Parser{}))) + maybe(Parser{} / ","_tok), + Parser{} / ":", Parser{}))) // 2.15.3.7 LINEAR (linear-list: linear-step) // linear-list -> list | modifier(list) @@ -453,6 +457,9 @@ TYPE_PARSER( parenthesized(Parser{}))) || "DEPEND" >> construct(construct( parenthesized(Parser{}))) || + "DESTROY" >> + construct(construct(maybe(parenthesized( + construct(Parser{}))))) || "DEVICE" >> construct(construct( parenthesized(Parser{}))) || "DEVICE_TYPE" >> construct(construct( @@ -559,7 +566,9 @@ TYPE_PARSER( construct(construct()) || "UNIFORM" >> construct(construct( parenthesized(nonemptyList(name)))) || - "UNTIED" >> construct(construct())) + "UNTIED" >> construct(construct()) || + "UPDATE" >> construct(construct( + parenthesized(Parser{})))) // [Clause, [Clause], ...] TYPE_PARSER(sourced(construct( @@ -582,12 +591,19 @@ TYPE_PARSER(sourced(construct(first( "MASKED TASKLOOP SIMD" >> pure(llvm::omp::Directive::OMPD_masked_taskloop_simd), "MASKED TASKLOOP" >> pure(llvm::omp::Directive::OMPD_masked_taskloop), + "MASTER TASKLOOP SIMD" >> + pure(llvm::omp::Directive::OMPD_master_taskloop_simd), + "MASTER TASKLOOP" >> pure(llvm::omp::Directive::OMPD_master_taskloop), "PARALLEL DO SIMD" >> pure(llvm::omp::Directive::OMPD_parallel_do_simd), "PARALLEL DO" >> pure(llvm::omp::Directive::OMPD_parallel_do), "PARALLEL MASKED TASKLOOP SIMD" >> pure(llvm::omp::Directive::OMPD_parallel_masked_taskloop_simd), "PARALLEL MASKED TASKLOOP" >> pure(llvm::omp::Directive::OMPD_parallel_masked_taskloop), + "PARALLEL MASTER TASKLOOP SIMD" >> + pure(llvm::omp::Directive::OMPD_parallel_master_taskloop_simd), + "PARALLEL MASTER TASKLOOP" >> + pure(llvm::omp::Directive::OMPD_parallel_master_taskloop), "SIMD" >> pure(llvm::omp::Directive::OMPD_simd), "TARGET LOOP" >> pure(llvm::omp::Directive::OMPD_target_loop), "TARGET PARALLEL DO SIMD" >> @@ -672,6 +688,9 @@ TYPE_PARSER(sourced(construct( TYPE_PARSER(sourced(construct( many(maybe(","_tok) >> sourced(Parser{}))))) +TYPE_PARSER(sourced(construct(verbatim("DEPOBJ"_tok), + parenthesized(Parser{}), sourced(Parser{})))) + TYPE_PARSER(sourced(construct(verbatim("FLUSH"_tok), many(maybe(","_tok) >> sourced(Parser{})), maybe(parenthesized(Parser{}))))) @@ -696,7 +715,8 @@ TYPE_PARSER( construct(Parser{}) || construct(Parser{}) || construct( - Parser{})) / + Parser{}) || + construct(Parser{})) / endOfLine) // Directives enclosing structured-block @@ -705,6 +725,7 @@ TYPE_PARSER(construct(first( "MASTER" >> pure(llvm::omp::Directive::OMPD_master), "ORDERED" >> pure(llvm::omp::Directive::OMPD_ordered), "PARALLEL MASKED" >> pure(llvm::omp::Directive::OMPD_parallel_masked), + "PARALLEL MASTER" >> pure(llvm::omp::Directive::OMPD_parallel_master), "PARALLEL WORKSHARE" >> pure(llvm::omp::Directive::OMPD_parallel_workshare), "PARALLEL" >> pure(llvm::omp::Directive::OMPD_parallel), "SCOPE" >> pure(llvm::omp::Directive::OMPD_scope), diff --git a/flang/lib/Parser/parse-tree.cpp b/flang/lib/Parser/parse-tree.cpp index 948ad04a091a8c..60aef1666e9ba7 100644 --- a/flang/lib/Parser/parse-tree.cpp +++ b/flang/lib/Parser/parse-tree.cpp @@ -252,6 +252,23 @@ CharBlock Variable::GetSource() const { llvm::raw_ostream &operator<<(llvm::raw_ostream &os, const Name &x) { return os << x.ToString(); } + +OmpTaskDependenceType::Type OmpDependClause::GetDepType() const { + return common::visit( + common::visitors{ + [&](const parser::OmpDependClause::Source &) { + return parser::OmpTaskDependenceType::Type::Source; + }, + [&](const parser::OmpDependClause::Sink &) { + return parser::OmpTaskDependenceType::Type::Sink; + }, + [&](const parser::OmpDependClause::InOut &y) { + return std::get(y.t).v; + }, + }, + u); +} + } // namespace Fortran::parser template static llvm::omp::Clause getClauseIdForClass(C &&) { diff --git a/flang/lib/Parser/unparse.cpp b/flang/lib/Parser/unparse.cpp index 39fcb61609e33b..3b0824f80161f4 100644 --- a/flang/lib/Parser/unparse.cpp +++ b/flang/lib/Parser/unparse.cpp @@ -2215,11 +2215,9 @@ class UnparseVisitor { Walk(std::get>(x.t)); } void Unparse(const OmpDependClause::InOut &x) { - Put("("); Walk(std::get(x.t)); Put(":"); Walk(std::get(x.t)); - Put(")"); } bool Pre(const OmpDependClause &x) { return common::visit( @@ -2274,6 +2272,12 @@ class UnparseVisitor { case llvm::omp::Directive::OMPD_masked_taskloop: Word("MASKED TASKLOOP"); break; + case llvm::omp::Directive::OMPD_master_taskloop_simd: + Word("MASTER TASKLOOP SIMD"); + break; + case llvm::omp::Directive::OMPD_master_taskloop: + Word("MASTER TASKLOOP"); + break; case llvm::omp::Directive::OMPD_parallel_do: Word("PARALLEL DO "); break; @@ -2286,6 +2290,12 @@ class UnparseVisitor { case llvm::omp::Directive::OMPD_parallel_masked_taskloop: Word("PARALLEL MASKED TASKLOOP"); break; + case llvm::omp::Directive::OMPD_parallel_master_taskloop_simd: + Word("PARALLEL MASTER TASKLOOP SIMD"); + break; + case llvm::omp::Directive::OMPD_parallel_master_taskloop: + Word("PARALLEL MASTER TASKLOOP"); + break; case llvm::omp::Directive::OMPD_simd: Word("SIMD "); break; @@ -2390,6 +2400,9 @@ class UnparseVisitor { case llvm::omp::Directive::OMPD_parallel_masked: Word("PARALLEL MASKED"); break; + case llvm::omp::Directive::OMPD_parallel_master: + Word("PARALLEL MASTER"); + break; case llvm::omp::Directive::OMPD_parallel_workshare: Word("PARALLEL WORKSHARE "); break; @@ -2706,6 +2719,16 @@ class UnparseVisitor { }, x.u); } + void Unparse(const OpenMPDepobjConstruct &x) { + BeginOpenMP(); + Word("!$OMP DEPOBJ"); + Put("("); + Walk(std::get(x.t)); + Put(") "); + Walk(std::get(x.t)); + Put("\n"); + EndOpenMP(); + } void Unparse(const OpenMPFlushConstruct &x) { BeginOpenMP(); Word("!$OMP FLUSH "); diff --git a/flang/lib/Semantics/check-omp-structure.cpp b/flang/lib/Semantics/check-omp-structure.cpp index 0c3a0e76df6a6a..c813100b4b16c8 100644 --- a/flang/lib/Semantics/check-omp-structure.cpp +++ b/flang/lib/Semantics/check-omp-structure.cpp @@ -1261,6 +1261,39 @@ void OmpStructureChecker::Leave(const parser::OpenMPDeclareSimdConstruct &) { dirContext_.pop_back(); } +void OmpStructureChecker::Enter(const parser::OpenMPDepobjConstruct &x) { + const auto &dir{std::get(x.t)}; + PushContextAndClauseSets(dir.source, llvm::omp::Directive::OMPD_depobj); + + // [5.2:73:27-28] + // If the destroy clause appears on a depobj construct, destroy-var must + // refer to the same depend object as the depobj argument of the construct. + auto &clause{std::get(x.t)}; + if (clause.Id() == llvm::omp::Clause::OMPC_destroy) { + auto getSymbol{[&](const parser::OmpObject &obj) { + return common::visit( + [&](auto &&s) { return GetLastName(s).symbol; }, obj.u); + }}; + + auto &wrapper{std::get(clause.u)}; + if (const std::optional &destroy{wrapper.v}) { + const Symbol *constrSym{getSymbol(std::get(x.t))}; + const Symbol *clauseSym{getSymbol(destroy->v)}; + assert(constrSym && "Unresolved depobj construct symbol"); + assert(clauseSym && "Unresolved destroy symbol on depobj construct"); + if (constrSym != clauseSym) { + context_.Say(x.source, + "The DESTROY clause must refer to the same object as the " + "DEPOBJ construct"_err_en_US); + } + } + } +} + +void OmpStructureChecker::Leave(const parser::OpenMPDepobjConstruct &x) { + dirContext_.pop_back(); +} + void OmpStructureChecker::Enter(const parser::OpenMPRequiresConstruct &x) { const auto &dir{std::get(x.t)}; PushContextAndClauseSets(dir.source, llvm::omp::Directive::OMPD_requires); @@ -2476,7 +2509,6 @@ CHECK_SIMPLE_CLAUSE(Capture, OMPC_capture) CHECK_SIMPLE_CLAUSE(Contains, OMPC_contains) CHECK_SIMPLE_CLAUSE(Default, OMPC_default) CHECK_SIMPLE_CLAUSE(Depobj, OMPC_depobj) -CHECK_SIMPLE_CLAUSE(Destroy, OMPC_destroy) CHECK_SIMPLE_CLAUSE(Detach, OMPC_detach) CHECK_SIMPLE_CLAUSE(DeviceType, OMPC_device_type) CHECK_SIMPLE_CLAUSE(DistSchedule, OMPC_dist_schedule) @@ -2519,7 +2551,6 @@ CHECK_SIMPLE_CLAUSE(Uniform, OMPC_uniform) CHECK_SIMPLE_CLAUSE(Unknown, OMPC_unknown) CHECK_SIMPLE_CLAUSE(Untied, OMPC_untied) CHECK_SIMPLE_CLAUSE(UsesAllocators, OMPC_uses_allocators) -CHECK_SIMPLE_CLAUSE(Update, OMPC_update) CHECK_SIMPLE_CLAUSE(Write, OMPC_write) CHECK_SIMPLE_CLAUSE(Init, OMPC_init) CHECK_SIMPLE_CLAUSE(Use, OMPC_use) @@ -2555,6 +2586,22 @@ CHECK_REQ_CONSTANT_SCALAR_INT_CLAUSE(Simdlen, OMPC_simdlen) // Restrictions specific to each clause are implemented apart from the // generalized restrictions. + +void OmpStructureChecker::Enter(const parser::OmpClause::Destroy &x) { + CheckAllowedClause(llvm::omp::Clause::OMPC_destroy); + + llvm::omp::Directive dir{GetContext().directive}; + unsigned version{context_.langOptions().OpenMPVersion}; + if (dir == llvm::omp::Directive::OMPD_depobj) { + if (version < 52) { + context_.Say(GetContext().clauseSource, + "The object parameter in DESTROY clause in DEPOPJ construct " + "was introduced in %s"_port_en_US, + ThisVersion(52)); + } + } +} + void OmpStructureChecker::Enter(const parser::OmpClause::Reduction &x) { CheckAllowedClause(llvm::omp::Clause::OMPC_reduction); if (CheckReductionOperators(x)) { @@ -3285,16 +3332,63 @@ void OmpStructureChecker::Enter(const parser::OmpClause::Device &x) { void OmpStructureChecker::Enter(const parser::OmpClause::Depend &x) { CheckAllowedClause(llvm::omp::Clause::OMPC_depend); - if ((std::holds_alternative(x.v.u) || - std::holds_alternative(x.v.u)) && - GetContext().directive != llvm::omp::OMPD_ordered) { - context_.Say(GetContext().clauseSource, - "DEPEND(SOURCE) or DEPEND(SINK : vec) can be used only with the ordered" - " directive. Used here in the %s construct."_err_en_US, - parser::ToUpperCaseLetters(getDirectiveName(GetContext().directive))); + llvm::omp::Directive directive{GetContext().directive}; + unsigned version{context_.langOptions().OpenMPVersion}; + + using DepType = parser::OmpTaskDependenceType::Type; + DepType depType = x.v.GetDepType(); + + if (version >= 52) { + switch (depType) { + case DepType::Sink: + case DepType::Source: + context_.Say(GetContext().clauseSource, + "The %s task-dependence-type is deprecated in %s"_warn_en_US, + parser::ToUpperCaseLetters( + parser::OmpTaskDependenceType::EnumToString(depType)), + ThisVersion(version)); + break; + default: + break; + } + } + + if (directive == llvm::omp::OMPD_depobj) { + // [5.0:255:11], [5.1:288:3] + // A depend clause on a depobj construct must not have source, sink [or + // depobj](5.0) as dependence-type. + if (version >= 50) { + bool invalidDep{depType == DepType::Source || depType == DepType::Sink}; + if (version == 50) { + invalidDep = invalidDep || depType == DepType::Depobj; + } + if (invalidDep) { + context_.Say(GetContext().clauseSource, + "A DEPEND clause on a DEPOBJ construct must not have SOURCE%s " + "as dependence-type"_err_en_US, + version == 50 ? ", SINK or DEPOBJ" : " or SINK"); + } + } + } else if (directive != llvm::omp::OMPD_ordered) { + if (depType == DepType::Source || depType == DepType::Sink) { + context_.Say(GetContext().clauseSource, + "DEPEND(SOURCE) or DEPEND(SINK : vec) can be used only with the " + "ordered directive. Used here in the %s construct."_err_en_US, + parser::ToUpperCaseLetters(getDirectiveName(directive))); + } } if (const auto *inOut{std::get_if(&x.v.u)}) { - for (const auto &object : std::get(inOut->t).v) { + auto &objList{std::get(inOut->t)}; + if (directive == llvm::omp::OMPD_depobj) { + // [5.0:255:13], [5.1:288:6], [5.2:322:26] + // A depend clause on a depobj construct must only specify one locator. + if (objList.v.size() != 1) { + context_.Say(GetContext().clauseSource, + "A DEPEND clause on a DEPOBJ construct must only specify " + "one locator"_err_en_US); + } + } + for (const auto &object : objList.v) { if (const auto *name{std::get_if(&object.u)}) { context_.Say(GetContext().clauseSource, "Common block name ('%s') cannot appear in a DEPEND " @@ -3312,6 +3406,21 @@ void OmpStructureChecker::Enter(const parser::OmpClause::Depend &x) { } } } + if (std::get>(inOut->t)) { + unsigned allowedInVersion{50}; + if (version < allowedInVersion) { + context_.Say(GetContext().clauseSource, + "Iterator modifiers are not supported in %s, %s"_warn_en_US, + ThisVersion(version), TryVersion(allowedInVersion)); + } else { + if (directive == llvm::omp::OMPD_depobj) { + context_.Say(GetContext().clauseSource, + "An iterator-modifier may specify multiple locators, " + "a DEPEND clause on a DEPOBJ construct must only specify " + "one locator"_warn_en_US); + } + } + } } } @@ -3424,6 +3533,34 @@ void OmpStructureChecker::CheckStructureElement( return; } +void OmpStructureChecker::Enter(const parser::OmpClause::Update &x) { + CheckAllowedClause(llvm::omp::Clause::OMPC_update); + llvm::omp::Directive directive{GetContext().directive}; + unsigned version{context_.langOptions().OpenMPVersion}; + + // [5.1:288:4-5] + // An update clause on a depobj construct must not have source, sink or depobj + // as dependence-type. + // [5.2:322:3] + // task-dependence-type must not be depobj. + if (directive == llvm::omp::OMPD_depobj) { + if (version >= 51) { + // Update -> OmpUpdateClause -> OmpTaskDependenceType -> Type + switch (x.v.v.v) { + case parser::OmpTaskDependenceType::Type::Source: + case parser::OmpTaskDependenceType::Type::Sink: + case parser::OmpTaskDependenceType::Type::Depobj: + context_.Say(GetContext().clauseSource, + "An UPDATE clause on a DEPOBJ construct must not have SOURCE, " + "SINK or DEPOBJ as dependence-type"_err_en_US); + break; + default: + break; + } + } + } +} + void OmpStructureChecker::Enter(const parser::OmpClause::UseDevicePtr &x) { CheckStructureElement(x.v, llvm::omp::Clause::OMPC_use_device_ptr); CheckAllowedClause(llvm::omp::Clause::OMPC_use_device_ptr); @@ -3607,7 +3744,7 @@ void OmpStructureChecker::CheckDependList(const parser::DataRef &d) { context_.Say(GetContext().clauseSource, "Coarrays are not supported in DEPEND clause"_err_en_US); }, - [&](const parser::Name &) { return; }, + [&](const parser::Name &) {}, }, d.u); } diff --git a/flang/lib/Semantics/check-omp-structure.h b/flang/lib/Semantics/check-omp-structure.h index 237569bc40c483..d5fd558cea2372 100644 --- a/flang/lib/Semantics/check-omp-structure.h +++ b/flang/lib/Semantics/check-omp-structure.h @@ -92,6 +92,8 @@ class OmpStructureChecker void Leave(const parser::OpenMPDeclarativeAllocate &); void Enter(const parser::OpenMPDeclareTargetConstruct &); void Leave(const parser::OpenMPDeclareTargetConstruct &); + void Enter(const parser::OpenMPDepobjConstruct &); + void Leave(const parser::OpenMPDepobjConstruct &); void Enter(const parser::OmpDeclareTargetWithList &); void Enter(const parser::OmpDeclareTargetWithClause &); void Leave(const parser::OmpDeclareTargetWithClause &); diff --git a/flang/lib/Semantics/resolve-directives.cpp b/flang/lib/Semantics/resolve-directives.cpp index 014b7987a658bd..359dac911b8c7c 100644 --- a/flang/lib/Semantics/resolve-directives.cpp +++ b/flang/lib/Semantics/resolve-directives.cpp @@ -383,6 +383,14 @@ class OmpAttributeVisitor : DirectiveAttributeVisitor { } void Post(const parser::OpenMPDeclareSimdConstruct &) { PopContext(); } + bool Pre(const parser::OpenMPDepobjConstruct &x) { + PushContext(x.source, llvm::omp::Directive::OMPD_depobj); + auto &object{std::get(x.t)}; + ResolveOmpObject(object, Symbol::Flag::OmpDependObject); + return true; + } + void Post(const parser::OpenMPDepobjConstruct &) { PopContext(); } + bool Pre(const parser::OpenMPRequiresConstruct &x) { using Flags = WithOmpDeclarative::RequiresFlags; using Requires = WithOmpDeclarative::RequiresFlag; @@ -1531,6 +1539,7 @@ bool OmpAttributeVisitor::Pre(const parser::OpenMPBlockConstruct &x) { case llvm::omp::Directive::OMPD_masked: case llvm::omp::Directive::OMPD_parallel_masked: case llvm::omp::Directive::OMPD_master: + case llvm::omp::Directive::OMPD_parallel_master: case llvm::omp::Directive::OMPD_ordered: case llvm::omp::Directive::OMPD_parallel: case llvm::omp::Directive::OMPD_scope: @@ -1550,7 +1559,8 @@ bool OmpAttributeVisitor::Pre(const parser::OpenMPBlockConstruct &x) { // TODO others break; } - if (beginDir.v == llvm::omp::Directive::OMPD_master) + if (beginDir.v == llvm::omp::Directive::OMPD_master || + beginDir.v == llvm::omp::Directive::OMPD_parallel_master) IssueNonConformanceWarning(beginDir.v, beginDir.source); ClearDataSharingAttributeObjects(); ClearPrivateDataSharingAttributeObjects(); @@ -1563,7 +1573,9 @@ void OmpAttributeVisitor::Post(const parser::OpenMPBlockConstruct &x) { const auto &beginDir{std::get(beginBlockDir.t)}; switch (beginDir.v) { case llvm::omp::Directive::OMPD_masked: + case llvm::omp::Directive::OMPD_master: case llvm::omp::Directive::OMPD_parallel_masked: + case llvm::omp::Directive::OMPD_parallel_master: case llvm::omp::Directive::OMPD_parallel: case llvm::omp::Directive::OMPD_scope: case llvm::omp::Directive::OMPD_single: @@ -1634,10 +1646,14 @@ bool OmpAttributeVisitor::Pre(const parser::OpenMPLoopConstruct &x) { case llvm::omp::Directive::OMPD_loop: case llvm::omp::Directive::OMPD_masked_taskloop_simd: case llvm::omp::Directive::OMPD_masked_taskloop: + case llvm::omp::Directive::OMPD_master_taskloop_simd: + case llvm::omp::Directive::OMPD_master_taskloop: case llvm::omp::Directive::OMPD_parallel_do: case llvm::omp::Directive::OMPD_parallel_do_simd: case llvm::omp::Directive::OMPD_parallel_masked_taskloop_simd: case llvm::omp::Directive::OMPD_parallel_masked_taskloop: + case llvm::omp::Directive::OMPD_parallel_master_taskloop_simd: + case llvm::omp::Directive::OMPD_parallel_master_taskloop: case llvm::omp::Directive::OMPD_simd: case llvm::omp::Directive::OMPD_target_loop: case llvm::omp::Directive::OMPD_target_parallel_do: @@ -1662,7 +1678,11 @@ bool OmpAttributeVisitor::Pre(const parser::OpenMPLoopConstruct &x) { default: break; } - if (beginDir.v == llvm::omp::Directive::OMPD_target_loop) + if (beginDir.v == llvm::omp::OMPD_master_taskloop || + beginDir.v == llvm::omp::OMPD_master_taskloop_simd || + beginDir.v == llvm::omp::OMPD_parallel_master_taskloop || + beginDir.v == llvm::omp::OMPD_parallel_master_taskloop_simd || + beginDir.v == llvm::omp::Directive::OMPD_target_loop) IssueNonConformanceWarning(beginDir.v, beginDir.source); ClearDataSharingAttributeObjects(); SetContextAssociatedLoopLevel(GetAssociatedLoopLevelFromClauses(clauseList)); @@ -2891,18 +2911,39 @@ void OmpAttributeVisitor::AddOmpRequiresToScope(Scope &scope, void OmpAttributeVisitor::IssueNonConformanceWarning( llvm::omp::Directive D, parser::CharBlock source) { - std::string warnStr = ""; - std::string dirName = llvm::omp::getOpenMPDirectiveName(D).str(); + std::string warnStr; + llvm::raw_string_ostream warnStrOS(warnStr); + warnStrOS << "OpenMP directive " + << parser::ToUpperCaseLetters( + llvm::omp::getOpenMPDirectiveName(D).str()) + << " has been deprecated"; + + auto setAlternativeStr = [&warnStrOS](llvm::StringRef alt) { + warnStrOS << ", please use " << alt << " instead."; + }; switch (D) { case llvm::omp::OMPD_master: - warnStr = "OpenMP directive '" + dirName + - "' has been deprecated, please use 'masked' instead."; + setAlternativeStr("MASKED"); + break; + case llvm::omp::OMPD_master_taskloop: + setAlternativeStr("MASKED TASKLOOP"); + break; + case llvm::omp::OMPD_master_taskloop_simd: + setAlternativeStr("MASKED TASKLOOP SIMD"); + break; + case llvm::omp::OMPD_parallel_master: + setAlternativeStr("PARALLEL MASKED"); + break; + case llvm::omp::OMPD_parallel_master_taskloop: + setAlternativeStr("PARALLEL MASKED TASKLOOP"); + break; + case llvm::omp::OMPD_parallel_master_taskloop_simd: + setAlternativeStr("PARALLEL_MASKED TASKLOOP SIMD"); break; case llvm::omp::OMPD_target_loop: - default: - warnStr = "OpenMP directive '" + dirName + "' has been deprecated."; + default:; } - context_.Warn( - common::UsageWarning::OpenMPUsage, source, "%s"_warn_en_US, warnStr); + context_.Warn(common::UsageWarning::OpenMPUsage, source, "%s"_warn_en_US, + warnStrOS.str()); } } // namespace Fortran::semantics diff --git a/flang/lib/Semantics/resolve-names.cpp b/flang/lib/Semantics/resolve-names.cpp index add4e4befd3a2b..e0a8246ebc752e 100644 --- a/flang/lib/Semantics/resolve-names.cpp +++ b/flang/lib/Semantics/resolve-names.cpp @@ -1538,6 +1538,13 @@ class OmpVisitor : public virtual DeclarationVisitor { void Post(const parser::OpenMPDeclarativeConstruct &) { messageHandler().set_currStmtSource(std::nullopt); } + bool Pre(const parser::OpenMPDepobjConstruct &x) { + AddOmpSourceRange(x.source); + return true; + } + void Post(const parser::OpenMPDepobjConstruct &x) { + messageHandler().set_currStmtSource(std::nullopt); + } bool Pre(const parser::OpenMPAtomicConstruct &x) { return common::visit(common::visitors{[&](const auto &u) -> bool { AddOmpSourceRange(u.source); diff --git a/flang/runtime/CUDA/kernel.cpp b/flang/runtime/CUDA/kernel.cpp index f81153a1af4bc7..abb7ebb72e5923 100644 --- a/flang/runtime/CUDA/kernel.cpp +++ b/flang/runtime/CUDA/kernel.cpp @@ -25,9 +25,32 @@ void RTDEF(CUFLaunchKernel)(const void *kernel, intptr_t gridX, intptr_t gridY, blockDim.x = blockX; blockDim.y = blockY; blockDim.z = blockZ; - cudaStream_t stream = 0; + cudaStream_t stream = 0; // TODO stream managment CUDA_REPORT_IF_ERROR( cudaLaunchKernel(kernel, gridDim, blockDim, params, smem, stream)); } +void RTDEF(CUFLaunchClusterKernel)(const void *kernel, intptr_t clusterX, + intptr_t clusterY, intptr_t clusterZ, intptr_t gridX, intptr_t gridY, + intptr_t gridZ, intptr_t blockX, intptr_t blockY, intptr_t blockZ, + int32_t smem, void **params, void **extra) { + cudaLaunchConfig_t config; + config.gridDim.x = gridX; + config.gridDim.y = gridY; + config.gridDim.z = gridZ; + config.blockDim.x = blockX; + config.blockDim.y = blockY; + config.blockDim.z = blockZ; + config.dynamicSmemBytes = smem; + config.stream = 0; // TODO stream managment + cudaLaunchAttribute launchAttr[1]; + launchAttr[0].id = cudaLaunchAttributeClusterDimension; + launchAttr[0].val.clusterDim.x = clusterX; + launchAttr[0].val.clusterDim.y = clusterY; + launchAttr[0].val.clusterDim.z = clusterZ; + config.numAttrs = 1; + config.attrs = launchAttr; + CUDA_REPORT_IF_ERROR(cudaLaunchKernelExC(&config, kernel, params)); +} + } // extern "C" diff --git a/flang/test/Driver/mabi.f90 b/flang/test/Driver/mabi.f90 new file mode 100644 index 00000000000000..88fd4d2a993fb0 --- /dev/null +++ b/flang/test/Driver/mabi.f90 @@ -0,0 +1,17 @@ +! RUN: not %flang -### -c --target=powerpc64le-unknown-linux -mabi=vec-extabi %s 2>&1 | FileCheck --check-prefix=INVALID1 %s +! RUN: not %flang -### -c --target=x86_64-unknown-linux -mabi=vec-extabi %s 2>&1 | FileCheck --check-prefix=INVALID2 %s +! RUN: not %flang -### -c --target=powerpc-unknown-aix -mabi=abc %s 2>&1 | FileCheck --check-prefix=INVALID3 %s +! RUN: %flang -### -c -target powerpc-unknown-aix %s 2>&1 | FileCheck --implicit-check-not=vec-extabi %s +! RUN: %flang -### -c -target powerpc-unknown-aix -mabi=vec-default %s 2>&1 | FileCheck --implicit-check-not=vec-extabi %s +! RUN: %flang -### -c -target powerpc-unknown-aix -mabi=vec-extabi %s 2>&1 | FileCheck --check-prefix=EXTABI %s + +! REQUIRES: target=powerpc{{.*}} + +! INVALID1: error: unsupported option '-mabi=vec-extabi' for target '{{.*}}' +! INVALID2: error: unsupported option '-mabi=' for target '{{.*}}' +! INVALID3: error: unsupported argument 'abc' to option '-mabi=' + +! EXTABI: "-fc1" +! EXTABI-SAME: "-mabi=vec-extabi" + + diff --git a/flang/test/Fir/CUDA/cuda-constructor-2.f90 b/flang/test/Fir/CUDA/cuda-constructor-2.f90 new file mode 100644 index 00000000000000..378dabbb7c7e7d --- /dev/null +++ b/flang/test/Fir/CUDA/cuda-constructor-2.f90 @@ -0,0 +1,22 @@ +// RUN: fir-opt --split-input-file --cuf-add-constructor %s | FileCheck %s + +module attributes {dlti.dl_spec = #dlti.dl_spec<#dlti.dl_entry : vector<4xi64>>, #dlti.dl_entry, dense<32> : vector<4xi64>>, #dlti.dl_entry, dense<32> : vector<4xi64>>, #dlti.dl_entry : vector<2xi64>>, #dlti.dl_entry : vector<2xi64>>, #dlti.dl_entry : vector<2xi64>>, #dlti.dl_entry : vector<2xi64>>, #dlti.dl_entry : vector<2xi64>>, #dlti.dl_entry : vector<2xi64>>, #dlti.dl_entry : vector<2xi64>>, #dlti.dl_entry : vector<2xi64>>, #dlti.dl_entry, dense<64> : vector<4xi64>>, #dlti.dl_entry : vector<2xi64>>, #dlti.dl_entry : vector<2xi64>>, #dlti.dl_entry<"dlti.endianness", "little">, #dlti.dl_entry<"dlti.stack_alignment", 128 : i64>>, fir.defaultkind = "a1c4d8i4l4r4", fir.kindmap = "", gpu.container_module, llvm.data_layout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128", llvm.ident = "flang version 20.0.0 (https://github.com/llvm/llvm-project.git cae351f3453a0a26ec8eb2ddaf773c24a29d929e)", llvm.target_triple = "x86_64-unknown-linux-gnu"} { + + fir.global @_QMmtestsEn(dense<[3, 4, 5, 6, 7]> : tensor<5xi32>) {data_attr = #cuf.cuda} : !fir.array<5xi32> + + gpu.module @cuda_device_mod [#nvvm.target] { + } +} + +// CHECK: gpu.module @cuda_device_mod [#nvvm.target] + +// CHECK: llvm.func internal @__cudaFortranConstructor() { +// CHECK-DAG: %[[MODULE:.*]] = cuf.register_module @cuda_device_mod -> !llvm.ptr +// CHECK-DAG: %[[VAR_NAME:.*]] = fir.address_of(@_QQ{{.*}}) : !fir.ref> +// CHECK-DAG: %[[VAR_ADDR:.*]] = fir.address_of(@_QMmtestsEn) : !fir.ref> +// CHECK-DAG: %[[MODULE2:.*]] = fir.convert %[[MODULE]] : (!llvm.ptr) -> !fir.ref> +// CHECK-DAG: %[[VAR_ADDR2:.*]] = fir.convert %[[VAR_ADDR]] : (!fir.ref>) -> !fir.ref +// CHECK-DAG: %[[VAR_NAME2:.*]] = fir.convert %[[VAR_NAME]] : (!fir.ref>) -> !fir.ref +// CHECK-DAG: %[[CST:.*]] = arith.constant 20 : index +// CHECK-DAG %[[CST2:.*]] = fir.convert %[[CST]] : (index) -> i64 +// CHECK fir.call @_FortranACUFRegisterVariable(%[[MODULE2]], %[[VAR_ADDR2]], %[[VAR_NAME2]], %[[CST2]]) : (!fir.ref>, !fir.ref, !fir.ref, i64) -> none diff --git a/flang/test/Fir/CUDA/cuda-gpu-launch-func.mlir b/flang/test/Fir/CUDA/cuda-gpu-launch-func.mlir index f10bd82f978dc4..7fede7c6c17b78 100644 --- a/flang/test/Fir/CUDA/cuda-gpu-launch-func.mlir +++ b/flang/test/Fir/CUDA/cuda-gpu-launch-func.mlir @@ -1,4 +1,4 @@ -// RUN: fir-opt --cuf-gpu-convert-to-llvm %s | FileCheck %s +// RUN: fir-opt --split-input-file --cuf-gpu-convert-to-llvm %s | FileCheck %s module attributes {dlti.dl_spec = #dlti.dl_spec<#dlti.dl_entry : vector<2xi64>>, #dlti.dl_entry : vector<4xi64>>, #dlti.dl_entry, dense<32> : vector<4xi64>>, #dlti.dl_entry, dense<32> : vector<4xi64>>, #dlti.dl_entry : vector<2xi64>>, #dlti.dl_entry : vector<2xi64>>, #dlti.dl_entry, dense<64> : vector<4xi64>>, #dlti.dl_entry : vector<2xi64>>, #dlti.dl_entry : vector<2xi64>>, #dlti.dl_entry : vector<2xi64>>, #dlti.dl_entry : vector<2xi64>>, #dlti.dl_entry : vector<2xi64>>, #dlti.dl_entry : vector<2xi64>>, #dlti.dl_entry : vector<2xi64>>, #dlti.dl_entry<"dlti.endianness", "little">, #dlti.dl_entry<"dlti.stack_alignment", 128 : i64>>, fir.defaultkind = "a1c4d8i4l4r4", fir.kindmap = "", gpu.container_module, llvm.data_layout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128", llvm.ident = "flang version 20.0.0 (git@github.com:clementval/llvm-project.git ddcfd4d2dc17bf66cee8c3ef6284118684a2b0e6)", llvm.target_triple = "x86_64-unknown-linux-gnu"} { llvm.func @_QMmod1Phost_sub() { @@ -102,3 +102,25 @@ module attributes {dlti.dl_spec = #dlti.dl_spec<#dlti.dl_entry : ve // CHECK: %[[KERNEL_PTR:.*]] = llvm.mlir.addressof @_QMmod1Psub1 : !llvm.ptr // CHECK: llvm.call @_FortranACUFLaunchKernel(%[[KERNEL_PTR]], {{.*}}) + +// ----- + +module attributes {dlti.dl_spec = #dlti.dl_spec<#dlti.dl_entry, dense<64> : vector<4xi64>>, #dlti.dl_entry : vector<4xi64>>, #dlti.dl_entry : vector<2xi64>>, #dlti.dl_entry, dense<32> : vector<4xi64>>, #dlti.dl_entry, dense<32> : vector<4xi64>>, #dlti.dl_entry : vector<2xi64>>, #dlti.dl_entry : vector<2xi64>>, #dlti.dl_entry : vector<2xi64>>, #dlti.dl_entry : vector<2xi64>>, #dlti.dl_entry : vector<2xi64>>, #dlti.dl_entry : vector<2xi64>>, #dlti.dl_entry : vector<2xi64>>, #dlti.dl_entry : vector<2xi64>>, #dlti.dl_entry : vector<2xi64>>, #dlti.dl_entry<"dlti.endianness", "little">, #dlti.dl_entry<"dlti.stack_alignment", 128 : i64>>, fir.defaultkind = "a1c4d8i4l4r4", fir.kindmap = "", gpu.container_module, llvm.data_layout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128", llvm.ident = "flang version 20.0.0 (git@github.com:clementval/llvm-project.git 4116c1370ff76adf1e58eb3c39d0a14721794c70)", llvm.target_triple = "x86_64-unknown-linux-gnu"} { + llvm.func @_FortranACUFLaunchClusterKernel(!llvm.ptr, i64, i64, i64, i64, i64, i64, i64, i64, i64, i32, !llvm.ptr, !llvm.ptr) attributes {sym_visibility = "private"} + llvm.func @_QMmod1Psub1() attributes {cuf.cluster_dims = #cuf.cluster_dims} { + llvm.return + } + llvm.func @_QQmain() attributes {fir.bindc_name = "test"} { + %0 = llvm.mlir.constant(1 : index) : i64 + %1 = llvm.mlir.constant(2 : index) : i64 + %2 = llvm.mlir.constant(0 : i32) : i32 + %3 = llvm.mlir.constant(10 : index) : i64 + gpu.launch_func @cuda_device_mod::@_QMmod1Psub1 clusters in (%1, %1, %0) blocks in (%3, %3, %0) threads in (%3, %3, %0) : i64 dynamic_shared_memory_size %2 + llvm.return + } + gpu.binary @cuda_device_mod [#gpu.object<#nvvm.target, "">] +} + +// CHECK-LABEL: llvm.func @_QQmain() +// CHECK: %[[KERNEL_PTR:.*]] = llvm.mlir.addressof @_QMmod1Psub1 +// CHECK: llvm.call @_FortranACUFLaunchClusterKernel(%[[KERNEL_PTR]], {{.*}}) diff --git a/flang/test/Fir/CUDA/cuda-launch.fir b/flang/test/Fir/CUDA/cuda-launch.fir new file mode 100644 index 00000000000000..f11bcbdb7fce55 --- /dev/null +++ b/flang/test/Fir/CUDA/cuda-launch.fir @@ -0,0 +1,64 @@ +// RUN: fir-opt --split-input-file --cuf-convert %s | FileCheck %s + + +module attributes {gpu.container_module, dlti.dl_spec = #dlti.dl_spec<#dlti.dl_entry : vector<2xi64>>, #dlti.dl_entry : vector<2xi64>>, #dlti.dl_entry : vector<2xi64>>, #dlti.dl_entry, dense<64> : vector<4xi64>>, #dlti.dl_entry, dense<32> : vector<4xi64>>, #dlti.dl_entry, dense<32> : vector<4xi64>>, #dlti.dl_entry : vector<2xi64>>, #dlti.dl_entry : vector<2xi64>>, #dlti.dl_entry : vector<2xi64>>, #dlti.dl_entry : vector<2xi64>>, #dlti.dl_entry : vector<2xi64>>, #dlti.dl_entry : vector<2xi64>>, #dlti.dl_entry : vector<2xi64>>, #dlti.dl_entry : vector<4xi64>>, #dlti.dl_entry<"dlti.endianness", "little">, #dlti.dl_entry<"dlti.stack_alignment", 128 : i64>>} { + gpu.module @cuda_device_mod { + gpu.func @_QPsub_device1() kernel { + cf.br ^bb1 + ^bb1: // pred: ^bb0 + gpu.return + } + gpu.func @_QPsub_device2(%arg0: !fir.ref) kernel { + cf.br ^bb1(%arg0 : !fir.ref) + ^bb1(%0: !fir.ref): // pred: ^bb0 + %1 = fir.declare %0 {uniq_name = "_QFsub1Ei"} : (!fir.ref) -> !fir.ref + %cst = arith.constant 2.000000e+00 : f32 + fir.store %cst to %1 : !fir.ref + gpu.return + } + } + + func.func @_QQmain() attributes {fir.bindc_name = "main"} { + %0 = fir.alloca f32 + // CHECK: %[[ALLOCA:.*]] = fir.alloca f32 + %c1 = arith.constant 1 : index + %c11_i32 = arith.constant 11 : i32 + %c6_i32 = arith.constant 6 : i32 + %c1_i32 = arith.constant 1 : i32 + // CHECK: gpu.launch_func @cuda_device_mod::@_QPsub_device1 blocks in (%{{.*}}, %{{.*}}, %{{.*}}) threads in (%{{.*}}, %{{.*}}, %{{.*}}) dynamic_shared_memory_size %c0{{.*}} + cuf.kernel_launch @cuda_device_mod::@_QPsub_device1<<<%c1_i32, %c1_i32, %c1_i32, %c1_i32, %c1_i32, %c1_i32>>>() + + // CHECK: gpu.launch_func @cuda_device_mod::@_QPsub_device2 blocks in (%{{.*}}, %{{.*}}, %{{.*}}) threads in (%{{.*}}, %{{.*}}, %{{.*}}) dynamic_shared_memory_size %c0{{.*}} args(%[[ALLOCA]] : !fir.ref) + cuf.kernel_launch @cuda_device_mod::@_QPsub_device2<<<%c1_i32, %c1_i32, %c1_i32, %c1_i32, %c1_i32, %c1_i32>>>(%0) : (!fir.ref) + return + } + +} + +// ----- + +module attributes {gpu.container_module, dlti.dl_spec = #dlti.dl_spec<#dlti.dl_entry : vector<2xi64>>, #dlti.dl_entry : vector<2xi64>>, #dlti.dl_entry : vector<2xi64>>, #dlti.dl_entry, dense<64> : vector<4xi64>>, #dlti.dl_entry, dense<32> : vector<4xi64>>, #dlti.dl_entry, dense<32> : vector<4xi64>>, #dlti.dl_entry : vector<2xi64>>, #dlti.dl_entry : vector<2xi64>>, #dlti.dl_entry : vector<2xi64>>, #dlti.dl_entry : vector<2xi64>>, #dlti.dl_entry : vector<2xi64>>, #dlti.dl_entry : vector<2xi64>>, #dlti.dl_entry : vector<2xi64>>, #dlti.dl_entry : vector<4xi64>>, #dlti.dl_entry<"dlti.endianness", "little">, #dlti.dl_entry<"dlti.stack_alignment", 128 : i64>>} { + gpu.module @cuda_device_mod { + gpu.func @_QMmod1Psub1(%arg0: !fir.ref>) kernel { + gpu.return + } + } + + func.func @_QMmod1Psub1(%arg0: !fir.ref> {cuf.data_attr = #cuf.cuda, fir.bindc_name = "adev"}) attributes {cuf.cluster_dims = #cuf.cluster_dims, cuf.proc_attr = #cuf.cuda_proc} { + return + } + func.func @_QMmod1Phost_sub() { + %c10 = arith.constant 10 : index + %0 = cuf.alloc !fir.array<10xi32> {bindc_name = "adev", data_attr = #cuf.cuda, uniq_name = "_QMmod1Fhost_subEadev"} -> !fir.ref> + %1 = fir.shape %c10 : (index) -> !fir.shape<1> + %2:2 = hlfir.declare %0(%1) {data_attr = #cuf.cuda, uniq_name = "_QMmod1Fhost_subEadev"} : (!fir.ref>, !fir.shape<1>) -> (!fir.ref>, !fir.ref>) + %c1_i32 = arith.constant 1 : i32 + %c10_i32 = arith.constant 10 : i32 + cuf.kernel_launch @_QMmod1Psub1<<<%c1_i32, %c1_i32, %c1_i32, %c10_i32, %c1_i32, %c1_i32>>>(%2#1) : (!fir.ref>) + return + } +} + +// CHECK-LABEL: func.func @_QMmod1Phost_sub() +// CHECK: gpu.launch_func @cuda_device_mod::@_QMmod1Psub1 clusters in (%c2{{.*}}, %c2{{.*}}, %c1{{.*}}) + diff --git a/flang/test/Lower/Intrinsics/ieee_real.f90 b/flang/test/Lower/Intrinsics/ieee_real.f90 new file mode 100644 index 00000000000000..20b7441e6e3a2a --- /dev/null +++ b/flang/test/Lower/Intrinsics/ieee_real.f90 @@ -0,0 +1,217 @@ +! RUN: bbc -emit-hlfir -o - %s | FileCheck %s + +! CHECK-LABEL: c.func @_QQmain +program p + use ieee_arithmetic, only: ieee_real + + ! CHECK: %[[V_0:[0-9]+]] = fir.alloca i16 {bindc_name = "j2", uniq_name = "_QFEj2"} + ! CHECK: %[[V_1:[0-9]+]]:2 = hlfir.declare %[[V_0]] {uniq_name = "_QFEj2"} : (!fir.ref) -> (!fir.ref, !fir.ref) + ! CHECK: %[[V_2:[0-9]+]] = fir.alloca i64 {bindc_name = "j8", uniq_name = "_QFEj8"} + ! CHECK: %[[V_3:[0-9]+]]:2 = hlfir.declare %[[V_2]] {uniq_name = "_QFEj8"} : (!fir.ref) -> (!fir.ref, !fir.ref) + ! CHECK: %[[V_4:[0-9]+]] = fir.alloca f16 {bindc_name = "x2", uniq_name = "_QFEx2"} + ! CHECK: %[[V_5:[0-9]+]]:2 = hlfir.declare %[[V_4]] {uniq_name = "_QFEx2"} : (!fir.ref) -> (!fir.ref, !fir.ref) + ! CHECK: %[[V_6:[0-9]+]] = fir.alloca f32 {bindc_name = "x4", uniq_name = "_QFEx4"} + ! CHECK: %[[V_7:[0-9]+]]:2 = hlfir.declare %[[V_6]] {uniq_name = "_QFEx4"} : (!fir.ref) -> (!fir.ref, !fir.ref) + ! CHECK: %[[V_8:[0-9]+]] = fir.alloca f64 {bindc_name = "x8", uniq_name = "_QFEx8"} + ! CHECK: %[[V_9:[0-9]+]]:2 = hlfir.declare %[[V_8]] {uniq_name = "_QFEx8"} : (!fir.ref) -> (!fir.ref, !fir.ref) + integer(2) :: j2 + integer(8) :: j8 + real(2) :: x2 + real(4) :: x4 + real(8) :: x8 + + ! CHECK: hlfir.assign %c-32768{{.*}} to %[[V_1]]#0 : i16, !fir.ref + j2 = -huge(j2) - 1 + + ! CHECK: %[[V_10:[0-9]+]] = fir.load %[[V_1]]#0 : !fir.ref + ! CHECK: %[[V_11:[0-9]+]] = fir.convert %[[V_10]] : (i16) -> f32 + ! CHECK: hlfir.assign %[[V_11]] to %[[V_7]]#0 : f32, !fir.ref + x4 = ieee_real(j2,4) ! exact +! print*, j2, ' -> ', x4 + + ! CHECK: hlfir.assign %c33{{.*}} to %[[V_3]]#0 : i64, !fir.ref + j8 = 33 + + ! CHECK: %[[V_12:[0-9]+]] = fir.load %[[V_3]]#0 : !fir.ref + ! CHECK: %[[V_13:[0-9]+]] = fir.convert %[[V_12]] : (i64) -> f32 + ! CHECK: %[[V_14:[0-9]+]] = fir.convert %[[V_13]] : (f32) -> i64 + ! CHECK: %[[V_15:[0-9]+]] = arith.cmpi eq, %[[V_12]], %[[V_14]] : i64 + ! CHECK: %[[V_16:[0-9]+]] = fir.if %[[V_15]] -> (f32) { + ! CHECK: fir.result %[[V_13]] : f32 + ! CHECK: } else { + ! CHECK: %[[V_27:[0-9]+]] = fir.call @llvm.get.rounding() fastmath : () -> i32 + ! CHECK-DAG: %[[V_28:[0-9]+]] = arith.cmpi slt, %[[V_12]], %c0{{.*}} : i64 + ! CHECK-DAG: %[[V_29:[0-9]+]] = arith.cmpi sgt, %[[V_12]], %c0{{.*}} : i64 + ! CHECK-DAG: %[[V_30:[0-9]+]] = arith.bitcast %[[V_13]] : f32 to i32 + ! CHECK-DAG: %[[V_31:[0-9]+]] = arith.andi %[[V_30]], %c1{{.*}} : i32 + ! CHECK-DAG: %[[V_32:[0-9]+]] = fir.convert %[[V_31]] : (i32) -> i1 + ! CHECK-DAG: %[[V_33:[0-9]+]] = arith.cmpi eq, %[[V_27]], %c5{{.*}} : i32 + ! CHECK-DAG: %[[V_34:[0-9]+]] = arith.cmpi eq, %[[V_27]], %c1{{.*}} : i32 + ! CHECK-DAG: %[[V_35:[0-9]+]] = arith.ori %[[V_34]], %[[V_33]] : i1 + ! CHECK-DAG: %[[V_36:[0-9]+]] = arith.andi %[[V_35]], %[[V_32]] : i1 + ! CHECK-DAG: %[[V_37:[0-9]+]] = arith.cmpi eq, %[[V_27]], %c0{{.*}} : i32 + ! CHECK-DAG: %[[V_38:[0-9]+]] = arith.cmpi eq, %[[V_27]], %c4{{.*}} : i32 + ! CHECK-DAG: %[[V_39:[0-9]+]] = arith.cmpi slt, %[[V_12]], %[[V_14]] : i64 + ! CHECK-DAG: %[[V_40:[0-9]+]] = arith.addi %[[V_30]], %c1{{.*}} : i32 + ! CHECK-DAG: %[[V_41:[0-9]+]] = arith.subi %[[V_30]], %c1{{.*}} : i32 + ! CHECK: %[[V_42:[0-9]+]] = fir.if %[[V_39]] -> (f32) { + ! CHECK-DAG: %[[V_44:[0-9]+]] = arith.andi %[[V_37]], %[[V_29]] : i1 + ! CHECK-DAG: %[[V_45:[0-9]+]] = arith.andi %[[V_38]], %[[V_28]] : i1 + ! CHECK-DAG: %[[V_46:[0-9]+]] = arith.cmpi eq, %[[V_27]], %c3{{.*}} : i32 + ! CHECK-DAG: %[[V_47:[0-9]+]] = arith.ori %[[V_36]], %[[V_44]] : i1 + ! CHECK-DAG: %[[V_48:[0-9]+]] = arith.ori %[[V_47]], %[[V_45]] : i1 + ! CHECK-DAG: %[[V_49:[0-9]+]] = arith.ori %[[V_48]], %[[V_46]] : i1 + ! CHECK: %[[V_50:[0-9]+]] = fir.if %[[V_49]] -> (f32) { + ! CHECK: %[[V_51:[0-9]+]] = arith.select %[[V_28]], %[[V_40]], %[[V_41]] : i32 + ! CHECK: %[[V_52:[0-9]+]] = arith.bitcast %[[V_51]] : i32 to f32 + ! CHECK: fir.result %[[V_52]] : f32 + ! CHECK: } else { + ! CHECK: fir.result %[[V_13]] : f32 + ! CHECK: } + ! CHECK: fir.result %[[V_50]] : f32 + ! CHECK: } else { + ! CHECK-DAG: %[[V_44:[0-9]+]] = arith.andi %[[V_37]], %[[V_28]] : i1 + ! CHECK-DAG: %[[V_45:[0-9]+]] = arith.andi %[[V_38]], %[[V_29]] : i1 + ! CHECK-DAG: %[[V_46:[0-9]+]] = arith.cmpi eq, %[[V_27]], %c2{{.*}} : i32 + ! CHECK-DAG: %[[V_47:[0-9]+]] = arith.ori %[[V_36]], %[[V_44]] : i1 + ! CHECK-DAG: %[[V_48:[0-9]+]] = arith.ori %[[V_47]], %[[V_45]] : i1 + ! CHECK-DAG: %[[V_49:[0-9]+]] = arith.ori %[[V_48]], %[[V_46]] : i1 + ! CHECK: %[[V_50:[0-9]+]] = fir.if %[[V_49]] -> (f32) { + ! CHECK: %[[V_51:[0-9]+]] = arith.select %[[V_29]], %[[V_40]], %[[V_41]] : i32 + ! CHECK: %[[V_52:[0-9]+]] = arith.bitcast %[[V_51]] : i32 to f32 + ! CHECK: fir.result %[[V_52]] : f32 + ! CHECK: } else { + ! CHECK: fir.result %[[V_13]] : f32 + ! CHECK: } + ! CHECK: fir.result %[[V_50]] : f32 + ! CHECK: } + ! CHECK: %[[V_43:[0-9]+]] = "llvm.intr.is.fpclass"(%[[V_42]]) <{bit = 516 : i32}> : (f32) -> i1 + ! CHECK: fir.if %[[V_43]] { + ! CHECK: %[[V_44:[0-9]+]] = fir.call @_FortranAMapException(%c40{{.*}}) fastmath : (i32) -> i32 + ! CHECK: %[[V_45:[0-9]+]] = fir.call @feraiseexcept(%[[V_44]]) fastmath : (i32) -> i32 + ! CHECK: } else { + ! CHECK: %[[V_44:[0-9]+]] = "llvm.intr.is.fpclass"(%[[V_42]]) <{bit = 240 : i32}> : (f32) -> i1 + ! CHECK: fir.if %[[V_44]] { + ! CHECK: %[[V_45:[0-9]+]] = fir.call @_FortranAMapException(%c48{{.*}}) fastmath : (i32) -> i32 + ! CHECK: %[[V_46:[0-9]+]] = fir.call @feraiseexcept(%[[V_45]]) fastmath : (i32) -> i32 + ! CHECK: } else { + ! CHECK: %[[V_45:[0-9]+]] = fir.call @_FortranAMapException(%c32{{.*}}) fastmath : (i32) -> i32 + ! CHECK: %[[V_46:[0-9]+]] = fir.call @feraiseexcept(%[[V_45]]) fastmath : (i32) -> i32 + ! CHECK: } + ! CHECK: } + ! CHECK: fir.result %[[V_42]] : f32 + ! CHECK: } + ! CHECK: hlfir.assign %[[V_16]] to %[[V_7]]#0 : f32, !fir.ref + x4 = ieee_real(j8,4) +! print*, j8, ' -> ', x4 + + ! CHECK: hlfir.assign %cst{{[_0-9]*}} to %[[V_5]]#0 : f16, !fir.ref + x2 = 3.33 + + ! CHECK: %[[V_17:[0-9]+]] = fir.load %[[V_5]]#0 : !fir.ref + ! CHECK: %[[V_18:[0-9]+]] = fir.convert %[[V_17]] : (f16) -> f32 + ! CHECK: %[[V_19:[0-9]+]] = "llvm.intr.is.fpclass"(%[[V_18]]) <{bit = 1 : i32}> : (f32) -> i1 + ! CHECK: %[[V_20:[0-9]+]] = fir.if %[[V_19]] -> (f32) { + ! CHECK: %[[V_27:[0-9]+]] = fir.call @_FortranAMapException(%c1{{.*}}) fastmath : (i32) -> i32 + ! CHECK: %[[V_28:[0-9]+]] = fir.call @feraiseexcept(%[[V_27]]) fastmath : (i32) -> i32 + ! CHECK: %[[V_29:[0-9]+]] = fir.address_of(@_FortranAIeeeValueTable_4) : !fir.ref> + ! CHECK: %[[V_30:[0-9]+]] = fir.coordinate_of %[[V_29]], %c2{{.*}} : (!fir.ref>, i8) -> !fir.ref + ! CHECK: %[[V_31:[0-9]+]] = fir.load %[[V_30]] : !fir.ref + ! CHECK: %[[V_32:[0-9]+]] = arith.bitcast %[[V_31]] : i32 to f32 + ! CHECK: fir.result %[[V_32]] : f32 + ! CHECK: } else { + ! CHECK: fir.result %[[V_18]] : f32 + ! CHECK: } + ! CHECK: %[[V_21:[0-9]+]] = fir.convert %[[V_20]] : (f32) -> f16 + ! CHECK: hlfir.assign %[[V_21]] to %[[V_5]]#0 : f16, !fir.ref + x2 = ieee_real(x2,4) ! exact +! print*, x2, ' -> ', x2 + + ! CHECK: hlfir.assign %cst{{[_0-9]*}} to %[[V_9]]#0 : f64, !fir.ref + x8 = -0. + + ! CHECK: %[[V_22:[0-9]+]] = fir.load %[[V_9]]#0 : !fir.ref + ! CHECK: %[[V_23:[0-9]+]] = fir.convert %[[V_22]] : (f64) -> f32 + ! CHECK: %[[V_24:[0-9]+]] = fir.convert %[[V_23]] : (f32) -> f64 + ! CHECK: %[[V_25:[0-9]+]] = arith.cmpf ueq, %[[V_22]], %[[V_24]] fastmath : f64 + ! CHECK: %[[V_26:[0-9]+]] = fir.if %[[V_25]] -> (f32) { + ! CHECK: %[[V_27:[0-9]+]] = "llvm.intr.is.fpclass"(%[[V_23]]) <{bit = 1 : i32}> : (f32) -> i1 + ! CHECK: %[[V_28:[0-9]+]] = fir.if %[[V_27]] -> (f32) { + ! CHECK: %[[V_29:[0-9]+]] = fir.call @_FortranAMapException(%c1{{.*}}) fastmath : (i32) -> i32 + ! CHECK: %[[V_30:[0-9]+]] = fir.call @feraiseexcept(%[[V_29]]) fastmath : (i32) -> i32 + ! CHECK: %[[V_31:[0-9]+]] = fir.address_of(@_FortranAIeeeValueTable_4) : !fir.ref> + ! CHECK: %[[V_32:[0-9]+]] = fir.coordinate_of %[[V_31]], %c2{{.*}} : (!fir.ref>, i8) -> !fir.ref + ! CHECK: %[[V_33:[0-9]+]] = fir.load %[[V_32]] : !fir.ref + ! CHECK: %[[V_34:[0-9]+]] = arith.bitcast %[[V_33]] : i32 to f32 + ! CHECK: fir.result %[[V_34]] : f32 + ! CHECK: } else { + ! CHECK: fir.result %[[V_23]] : f32 + ! CHECK: } + ! CHECK: fir.result %[[V_28]] : f32 + ! CHECK: } else { + ! CHECK-DAG: %[[V_27:[0-9]+]] = fir.call @llvm.get.rounding() fastmath : () -> i32 + ! CHECK-DAG: %[[V_28:[0-9]+]] = arith.cmpf olt, %[[V_22]], %cst{{[_0-9]*}} fastmath : f64 + ! CHECK-DAG: %[[V_29:[0-9]+]] = arith.cmpf ogt, %[[V_22]], %cst{{[_0-9]*}} fastmath : f64 + ! CHECK-DAG: %[[V_30:[0-9]+]] = arith.bitcast %[[V_23]] : f32 to i32 + ! CHECK-DAG: %[[V_31:[0-9]+]] = arith.andi %[[V_30]], %c1{{.*}} : i32 + ! CHECK-DAG: %[[V_32:[0-9]+]] = fir.convert %[[V_31]] : (i32) -> i1 + ! CHECK-DAG: %[[V_33:[0-9]+]] = arith.cmpi eq, %[[V_27]], %c5{{.*}} : i32 + ! CHECK-DAG: %[[V_34:[0-9]+]] = arith.cmpi eq, %[[V_27]], %c1{{.*}} : i32 + ! CHECK-DAG: %[[V_35:[0-9]+]] = arith.ori %[[V_34]], %[[V_33]] : i1 + ! CHECK-DAG: %[[V_36:[0-9]+]] = arith.andi %[[V_35]], %[[V_32]] : i1 + ! CHECK-DAG: %[[V_37:[0-9]+]] = arith.cmpi eq, %[[V_27]], %c0{{.*}} : i32 + ! CHECK-DAG: %[[V_38:[0-9]+]] = arith.cmpi eq, %[[V_27]], %c4{{.*}} : i32 + ! CHECK-DAG: %[[V_39:[0-9]+]] = arith.cmpf olt, %[[V_22]], %[[V_24]] fastmath : f64 + ! CHECK-DAG: %[[V_40:[0-9]+]] = arith.addi %[[V_30]], %c1{{.*}} : i32 + ! CHECK-DAG: %[[V_41:[0-9]+]] = arith.subi %[[V_30]], %c1{{.*}} : i32 + ! CHECK: %[[V_42:[0-9]+]] = fir.if %[[V_39]] -> (f32) { + ! CHECK-DAG: %[[V_44:[0-9]+]] = arith.andi %[[V_37]], %[[V_29]] : i1 + ! CHECK-DAG: %[[V_45:[0-9]+]] = arith.andi %[[V_38]], %[[V_28]] : i1 + ! CHECK-DAG: %[[V_46:[0-9]+]] = arith.cmpi eq, %[[V_27]], %c3{{.*}} : i32 + ! CHECK-DAG: %[[V_47:[0-9]+]] = arith.ori %[[V_36]], %[[V_44]] : i1 + ! CHECK-DAG: %[[V_48:[0-9]+]] = arith.ori %[[V_47]], %[[V_45]] : i1 + ! CHECK-DAG: %[[V_49:[0-9]+]] = arith.ori %[[V_48]], %[[V_46]] : i1 + ! CHECK: %[[V_50:[0-9]+]] = fir.if %[[V_49]] -> (f32) { + ! CHECK: %[[V_51:[0-9]+]] = arith.select %[[V_28]], %[[V_40]], %[[V_41]] : i32 + ! CHECK: %[[V_52:[0-9]+]] = arith.bitcast %[[V_51]] : i32 to f32 + ! CHECK: fir.result %[[V_52]] : f32 + ! CHECK: } else { + ! CHECK: fir.result %[[V_23]] : f32 + ! CHECK: } + ! CHECK: fir.result %[[V_50]] : f32 + ! CHECK: } else { + ! CHECK-DAG: %[[V_44:[0-9]+]] = arith.andi %[[V_37]], %[[V_28]] : i1 + ! CHECK-DAG: %[[V_45:[0-9]+]] = arith.andi %[[V_38]], %[[V_29]] : i1 + ! CHECK-DAG: %[[V_46:[0-9]+]] = arith.cmpi eq, %[[V_27]], %c2{{.*}} : i32 + ! CHECK-DAG: %[[V_47:[0-9]+]] = arith.ori %[[V_36]], %[[V_44]] : i1 + ! CHECK-DAG: %[[V_48:[0-9]+]] = arith.ori %[[V_47]], %[[V_45]] : i1 + ! CHECK-DAG: %[[V_49:[0-9]+]] = arith.ori %[[V_48]], %[[V_46]] : i1 + ! CHECK: %[[V_50:[0-9]+]] = fir.if %[[V_49]] -> (f32) { + ! CHECK: %[[V_51:[0-9]+]] = arith.select %[[V_29]], %[[V_40]], %[[V_41]] : i32 + ! CHECK: %[[V_52:[0-9]+]] = arith.bitcast %[[V_51]] : i32 to f32 + ! CHECK: fir.result %[[V_52]] : f32 + ! CHECK: } else { + ! CHECK: fir.result %[[V_23]] : f32 + ! CHECK: } + ! CHECK: fir.result %[[V_50]] : f32 + ! CHECK: } + ! CHECK: %[[V_43:[0-9]+]] = "llvm.intr.is.fpclass"(%[[V_42]]) <{bit = 516 : i32}> : (f32) -> i1 + ! CHECK: fir.if %[[V_43]] { + ! CHECK: %[[V_44:[0-9]+]] = fir.call @_FortranAMapException(%c40{{.*}}) fastmath : (i32) -> i32 + ! CHECK: %[[V_45:[0-9]+]] = fir.call @feraiseexcept(%[[V_44]]) fastmath : (i32) -> i32 + ! CHECK: } else { + ! CHECK: %[[V_44:[0-9]+]] = "llvm.intr.is.fpclass"(%[[V_42]]) <{bit = 240 : i32}> : (f32) -> i1 + ! CHECK: fir.if %[[V_44]] { + ! CHECK: %[[V_45:[0-9]+]] = fir.call @_FortranAMapException(%c48{{.*}}) fastmath : (i32) -> i32 + ! CHECK: %[[V_46:[0-9]+]] = fir.call @feraiseexcept(%[[V_45]]) fastmath : (i32) -> i32 + ! CHECK: } else { + ! CHECK: %[[V_45:[0-9]+]] = fir.call @_FortranAMapException(%c32{{.*}}) fastmath : (i32) -> i32 + ! CHECK: %[[V_46:[0-9]+]] = fir.call @feraiseexcept(%[[V_45]]) fastmath : (i32) -> i32 + ! CHECK: } + ! CHECK: } + ! CHECK: fir.result %[[V_42]] : f32 + ! CHECK: } + ! CHECK: hlfir.assign %[[V_26]] to %[[V_7]]#0 : f32, !fir.ref + x4 = ieee_real(x8,4) +! print*, x8, ' -> ', x4 +end diff --git a/flang/test/Lower/OpenMP/Todo/depend-clause.f90 b/flang/test/Lower/OpenMP/Todo/depend-clause.f90 new file mode 100644 index 00000000000000..74525888c91d6d --- /dev/null +++ b/flang/test/Lower/OpenMP/Todo/depend-clause.f90 @@ -0,0 +1,10 @@ +!RUN: %not_todo_cmd bbc -emit-hlfir -fopenmp -fopenmp-version=50 -o - %s 2>&1 | FileCheck %s +!RUN: %not_todo_cmd %flang_fc1 -emit-hlfir -fopenmp -fopenmp-version=50 -o - %s 2>&1 | FileCheck %s + +!CHECK: Support for iterator modifiers is not implemented yet +subroutine f00(x) + integer :: x(10) + !$omp task depend(iterator(i = 1:10), in: x(i)) + x = 0 + !$omp end task +end diff --git a/flang/test/Lower/OpenMP/Todo/depobj-construct.f90 b/flang/test/Lower/OpenMP/Todo/depobj-construct.f90 new file mode 100644 index 00000000000000..2b3c4d92c4a4f8 --- /dev/null +++ b/flang/test/Lower/OpenMP/Todo/depobj-construct.f90 @@ -0,0 +1,9 @@ +!RUN: %not_todo_cmd bbc -emit-hlfir -fopenmp -fopenmp-version=50 -o - %s 2>&1 | FileCheck %s +!RUN: %not_todo_cmd %flang_fc1 -emit-hlfir -fopenmp -fopenmp-version=50 -o - %s 2>&1 | FileCheck %s + +!CHECK: not yet implemented: OpenMPDepobjConstruct +subroutine f00() + integer :: obj + integer :: x + !$omp depobj(obj) depend(in: x) +end diff --git a/flang/test/Lower/OpenMP/master_taskloop.f90 b/flang/test/Lower/OpenMP/master_taskloop.f90 new file mode 100644 index 00000000000000..26f664b2662dcb --- /dev/null +++ b/flang/test/Lower/OpenMP/master_taskloop.f90 @@ -0,0 +1,14 @@ +! This test checks lowering of OpenMP master taskloop Directive. + +! RUN: %not_todo_cmd bbc -emit-fir -fopenmp -o - %s 2>&1 | FileCheck %s +! RUN: %not_todo_cmd %flang_fc1 -emit-fir -fopenmp -o - %s 2>&1 | FileCheck %s + +subroutine test_master_taskloop + integer :: i, j = 1 + !CHECK: not yet implemented: Taskloop construct + !$omp master taskloop + do i=1,10 + j = j + 1 + end do + !$omp end master taskloop +end subroutine diff --git a/flang/test/Lower/OpenMP/master_taskloop_simd.f90 b/flang/test/Lower/OpenMP/master_taskloop_simd.f90 new file mode 100644 index 00000000000000..e928afd65244a4 --- /dev/null +++ b/flang/test/Lower/OpenMP/master_taskloop_simd.f90 @@ -0,0 +1,14 @@ +! This test checks lowering of OpenMP master taskloop simd Directive. + +! RUN: %not_todo_cmd bbc -emit-fir -fopenmp -o - %s 2>&1 | FileCheck %s +! RUN: %not_todo_cmd %flang_fc1 -emit-fir -fopenmp -o - %s 2>&1 | FileCheck %s + +subroutine test_master_taskloop_simd() + integer :: i, j = 1 + !CHECK: not yet implemented: Composite TASKLOOP SIMD + !$omp master taskloop simd + do i=1,10 + j = j + 1 + end do + !$omp end master taskloop simd +end subroutine diff --git a/flang/test/Lower/OpenMP/parallel-master-taskloop-simd.f90 b/flang/test/Lower/OpenMP/parallel-master-taskloop-simd.f90 new file mode 100644 index 00000000000000..086ed01d16d364 --- /dev/null +++ b/flang/test/Lower/OpenMP/parallel-master-taskloop-simd.f90 @@ -0,0 +1,14 @@ +! This test checks lowering of OpenMP parallel master taskloop simd Directive. + +! RUN: %not_todo_cmd bbc -emit-fir -fopenmp -o - %s 2>&1 | FileCheck %s +! RUN: %not_todo_cmd %flang_fc1 -emit-fir -fopenmp -o - %s 2>&1 | FileCheck %s + +subroutine test_parallel_master_taskloop_simd + integer :: i, j = 1 + !CHECK: not yet implemented: Composite TASKLOOP SIMD + !$omp parallel master taskloop simd + do i=1,10 + j = j + 1 + end do + !$omp end parallel master taskloop simd +end subroutine diff --git a/flang/test/Lower/OpenMP/parallel-master-taskloop.f90 b/flang/test/Lower/OpenMP/parallel-master-taskloop.f90 new file mode 100644 index 00000000000000..17ceb9496c8d34 --- /dev/null +++ b/flang/test/Lower/OpenMP/parallel-master-taskloop.f90 @@ -0,0 +1,14 @@ +! This test checks lowering of OpenMP parallel master taskloop Directive. + +! RUN: %not_todo_cmd bbc -emit-fir -fopenmp -o - %s 2>&1 | FileCheck %s +! RUN: %not_todo_cmd %flang_fc1 -emit-fir -fopenmp -o - %s 2>&1 | FileCheck %s + +subroutine test_parallel_master_taskloop + integer :: i, j = 1 + !CHECK: not yet implemented: Taskloop construct + !$omp parallel master taskloop + do i=1,10 + j = j + 1 + end do + !$omp end parallel master taskloop +end subroutine diff --git a/flang/test/Lower/OpenMP/parallel-master.f90 b/flang/test/Lower/OpenMP/parallel-master.f90 new file mode 100644 index 00000000000000..8f3ee31b328537 --- /dev/null +++ b/flang/test/Lower/OpenMP/parallel-master.f90 @@ -0,0 +1,16 @@ +! This test checks lowering of the parallel master combined construct. + +! RUN: bbc -fopenmp -emit-hlfir %s -o - | FileCheck %s +! RUN: %flang_fc1 -fopenmp -emit-hlfir %s -o - | FileCheck %s + +! CHECK-LABEL: func @_QPparallel_master +subroutine parallel_master(x) + integer :: x + !CHECK: omp.parallel { + !CHECK: omp.master { + !$omp parallel master + x = 1 + !$omp end parallel master + !CHECK: } + !CHECK: } +end subroutine parallel_master diff --git a/flang/test/Parser/OpenMP/depobj-construct.f90 b/flang/test/Parser/OpenMP/depobj-construct.f90 new file mode 100644 index 00000000000000..7c474071bc1e67 --- /dev/null +++ b/flang/test/Parser/OpenMP/depobj-construct.f90 @@ -0,0 +1,64 @@ +!RUN: %flang_fc1 -fdebug-unparse -fopenmp -fopenmp-version=52 %s | FileCheck --ignore-case --check-prefix="UNPARSE" %s +!RUN: %flang_fc1 -fdebug-dump-parse-tree -fopenmp -fopenmp-version=52 %s | FileCheck --check-prefix="PARSE-TREE" %s + +subroutine f00 + integer :: x, y + !$omp depobj(x) depend(in: y) +end + +!UNPARSE: SUBROUTINE f00 +!UNPARSE: INTEGER x, y +!UNPARSE: !$OMP DEPOBJ(x) DEPEND(IN:y) +!UNPARSE: END SUBROUTINE + +!PARSE-TREE: ExecutionPartConstruct -> ExecutableConstruct -> OpenMPConstruct -> OpenMPStandaloneConstruct -> OpenMPDepobjConstruct +!PARSE-TREE: | Verbatim +!PARSE-TREE: | OmpObject -> Designator -> DataRef -> Name = 'x' +!PARSE-TREE: | OmpClause -> Depend -> OmpDependClause -> InOut +!PARSE-TREE: | | OmpTaskDependenceType -> Type = In +!PARSE-TREE: | | OmpObjectList -> OmpObject -> Designator -> DataRef -> Name = 'y' + +subroutine f01 + integer :: x + !$omp depobj(x) update(out) +end + +!UNPARSE: SUBROUTINE f01 +!UNPARSE: INTEGER x +!UNPARSE: !$OMP DEPOBJ(x) UPDATE(OUT) +!UNPARSE: END SUBROUTINE + +!PARSE-TREE: ExecutionPartConstruct -> ExecutableConstruct -> OpenMPConstruct -> OpenMPStandaloneConstruct -> OpenMPDepobjConstruct +!PARSE-TREE: | Verbatim +!PARSE-TREE: | OmpObject -> Designator -> DataRef -> Name = 'x' +!PARSE-TREE: | OmpClause -> Update -> OmpUpdateClause -> OmpTaskDependenceType -> Type = Out + +subroutine f02 + integer :: x + !$omp depobj(x) destroy(x) +end + +!UNPARSE: SUBROUTINE f02 +!UNPARSE: INTEGER x +!UNPARSE: !$OMP DEPOBJ(x) DESTROY(x) +!UNPARSE: END SUBROUTINE + +!PARSE-TREE: ExecutionPartConstruct -> ExecutableConstruct -> OpenMPConstruct -> OpenMPStandaloneConstruct -> OpenMPDepobjConstruct +!PARSE-TREE: | Verbatim +!PARSE-TREE: | OmpObject -> Designator -> DataRef -> Name = 'x' +!PARSE-TREE: | OmpClause -> Destroy -> OmpDestroyClause -> OmpObject -> Designator -> DataRef -> Name = 'x' + +subroutine f03 + integer :: x + !$omp depobj(x) destroy +end + +!UNPARSE: SUBROUTINE f03 +!UNPARSE: INTEGER x +!UNPARSE: !$OMP DEPOBJ(x) DESTROY +!UNPARSE: END SUBROUTINE + +!PARSE-TREE: ExecutionPartConstruct -> ExecutableConstruct -> OpenMPConstruct -> OpenMPStandaloneConstruct -> OpenMPDepobjConstruct +!PARSE-TREE: | Verbatim +!PARSE-TREE: | OmpObject -> Designator -> DataRef -> Name = 'x' +!PARSE-TREE: | OmpClause -> Destroy -> diff --git a/flang/test/Parser/OpenMP/master-unparse.f90 b/flang/test/Parser/OpenMP/master-unparse.f90 new file mode 100644 index 00000000000000..30c293a521b5d1 --- /dev/null +++ b/flang/test/Parser/OpenMP/master-unparse.f90 @@ -0,0 +1,73 @@ +! RUN: %flang_fc1 -fdebug-unparse -fopenmp %s | FileCheck --ignore-case %s +! RUN: %flang_fc1 -fdebug-dump-parse-tree -fopenmp %s | FileCheck --check-prefix="PARSE-TREE" %s + +! Check for parsing of master directive + + +subroutine test_master() + integer :: c = 1 + !PARSE-TREE: OmpBeginBlockDirective + !PARSE-TREE-NEXT: OmpBlockDirective -> llvm::omp::Directive = master + !CHECK: !$omp master + !$omp master + c = c + 1 + !$omp end master +end subroutine + +subroutine test_master_taskloop_simd() + integer :: i, j = 1 + !PARSE-TREE: OmpBeginLoopDirective + !PARSE-TREE-NEXT: OmpLoopDirective -> llvm::omp::Directive = master taskloop simd + !CHECK: !$omp master taskloop simd + !$omp master taskloop simd + do i=1,10 + j = j + 1 + end do + !$omp end master taskloop simd +end subroutine + +subroutine test_master_taskloop + integer :: i, j = 1 + !PARSE-TREE: OmpBeginLoopDirective + !PARSE-TREE-NEXT: OmpLoopDirective -> llvm::omp::Directive = master taskloop + !CHECK: !$omp master taskloop + !$omp master taskloop + do i=1,10 + j = j + 1 + end do + !$omp end master taskloop +end subroutine + +subroutine test_parallel_master + integer :: c = 2 + !PARSE-TREE: OmpBeginBlockDirective + !PARSE-TREE-NEXT: OmpBlockDirective -> llvm::omp::Directive = parallel master + !CHECK: !$omp parallel master + !$omp parallel master + c = c + 2 + !$omp end parallel master +end subroutine + +subroutine test_parallel_master_taskloop_simd + integer :: i, j = 1 + !PARSE-TREE: OmpBeginLoopDirective + !PARSE-TREE-NEXT: OmpLoopDirective -> llvm::omp::Directive = parallel master taskloop simd + !CHECK: !$omp parallel master taskloop simd + !$omp parallel master taskloop simd + do i=1,10 + j = j + 1 + end do + !$omp end parallel master taskloop simd +end subroutine + +subroutine test_parallel_master_taskloop + integer :: i, j = 1 + !PARSE-TREE: OmpBeginLoopDirective + !PARSE-TREE-NEXT: OmpLoopDirective -> llvm::omp::Directive = parallel master taskloop + !CHECK: !$omp parallel master taskloop + !$omp parallel master taskloop + do i=1,10 + j = j + 1 + end do + !$omp end parallel master taskloop +end subroutine diff --git a/flang/test/Semantics/OpenMP/clause-validity01.f90 b/flang/test/Semantics/OpenMP/clause-validity01.f90 index 1a7a57b124e9bd..124f1a02d99fba 100644 --- a/flang/test/Semantics/OpenMP/clause-validity01.f90 +++ b/flang/test/Semantics/OpenMP/clause-validity01.f90 @@ -476,14 +476,14 @@ ! 2.13.1 master !$omp parallel - !WARNING: OpenMP directive 'master' has been deprecated, please use 'masked' instead. + !WARNING: OpenMP directive MASTER has been deprecated, please use MASKED instead. !$omp master a=3.14 !$omp end master !$omp end parallel !$omp parallel - !WARNING: OpenMP directive 'master' has been deprecated, please use 'masked' instead. + !WARNING: OpenMP directive MASTER has been deprecated, please use MASKED instead. !ERROR: NUM_THREADS clause is not allowed on the MASTER directive !$omp master num_threads(4) a=3.14 diff --git a/flang/test/Semantics/OpenMP/depend05.f90 b/flang/test/Semantics/OpenMP/depend05.f90 new file mode 100644 index 00000000000000..53fd82bd08a9eb --- /dev/null +++ b/flang/test/Semantics/OpenMP/depend05.f90 @@ -0,0 +1,9 @@ +!RUN: %python %S/../test_errors.py %s %flang -fopenmp -fopenmp-version=45 -Werror + +subroutine f00(x) + integer :: x(10) +!WARNING: Iterator modifiers are not supported in OpenMP v4.5, try -fopenmp-version=50 + !$omp task depend(iterator(i = 1:10), in: x(i)) + x = 0 + !$omp end task +end diff --git a/flang/test/Semantics/OpenMP/depobj-construct-v50.f90 b/flang/test/Semantics/OpenMP/depobj-construct-v50.f90 new file mode 100644 index 00000000000000..e7fa24d521b63b --- /dev/null +++ b/flang/test/Semantics/OpenMP/depobj-construct-v50.f90 @@ -0,0 +1,28 @@ +!RUN: %python %S/../test_errors.py %s %flang -fopenmp -fopenmp-version=50 + +subroutine f00 + integer :: obj +!ERROR: A DEPEND clause on a DEPOBJ construct must not have SOURCE, SINK or DEPOBJ as dependence-type + !$omp depobj(obj) depend(source) +end + +subroutine f01 + integer :: obj + integer :: x, y +!ERROR: A DEPEND clause on a DEPOBJ construct must only specify one locator + !$omp depobj(obj) depend(in: x, y) +end + +subroutine f02 + integer :: obj + integer :: x(10) +!WARNING: An iterator-modifier may specify multiple locators, a DEPEND clause on a DEPOBJ construct must only specify one locator + !$omp depobj(obj) depend(iterator(i = 1:10), in: x(i)) +end + +subroutine f03 + integer :: obj, jbo +!ERROR: The DESTROY clause must refer to the same object as the DEPOBJ construct +!PORTABILITY: The object parameter in DESTROY clause in DEPOPJ construct was introduced in OpenMP v5.2 + !$omp depobj(obj) destroy(jbo) +end diff --git a/flang/test/Semantics/OpenMP/depobj-construct-v51.f90 b/flang/test/Semantics/OpenMP/depobj-construct-v51.f90 new file mode 100644 index 00000000000000..fa0c025a110100 --- /dev/null +++ b/flang/test/Semantics/OpenMP/depobj-construct-v51.f90 @@ -0,0 +1,13 @@ +!RUN: %python %S/../test_errors.py %s %flang -fopenmp -fopenmp-version=51 + +subroutine f04 + integer :: obj +!ERROR: An UPDATE clause on a DEPOBJ construct must not have SOURCE, SINK or DEPOBJ as dependence-type + !$omp depobj(obj) update(source) +end + +subroutine f05 + integer :: obj +!ERROR: An UPDATE clause on a DEPOBJ construct must not have SOURCE, SINK or DEPOBJ as dependence-type + !$omp depobj(obj) update(depobj) +end diff --git a/flang/test/Semantics/OpenMP/depobj-construct-v52.f90 b/flang/test/Semantics/OpenMP/depobj-construct-v52.f90 new file mode 100644 index 00000000000000..f2e66485c6c801 --- /dev/null +++ b/flang/test/Semantics/OpenMP/depobj-construct-v52.f90 @@ -0,0 +1,15 @@ +!RUN: %python %S/../test_errors.py %s %flang -fopenmp -fopenmp-version=52 + +subroutine f00 + integer :: obj +!WARNING: The SOURCE task-dependence-type is deprecated in OpenMP v5.2 +!ERROR: A DEPEND clause on a DEPOBJ construct must not have SOURCE or SINK as dependence-type + !$omp depobj(obj) depend(source) +end + +subroutine f03 + integer :: obj, jbo +!Note: no portability message +!ERROR: The DESTROY clause must refer to the same object as the DEPOBJ construct + !$omp depobj(obj) destroy(jbo) +end diff --git a/flang/test/Semantics/OpenMP/deprecation.f90 b/flang/test/Semantics/OpenMP/deprecation.f90 new file mode 100644 index 00000000000000..e04f43026bbce2 --- /dev/null +++ b/flang/test/Semantics/OpenMP/deprecation.f90 @@ -0,0 +1,59 @@ +! RUN: %python %S/../test_errors.py %s %flang_fc1 -fopenmp -Werror + +! Check for deprecation of master directive and its combined/composite variants + +subroutine test_master() + integer :: c = 1 +!WARNING: OpenMP directive MASTER has been deprecated, please use MASKED instead. + !$omp master + c = c + 1 + !$omp end master +end subroutine + +subroutine test_parallel_master + integer :: c = 2 +!WARNING: OpenMP directive PARALLEL MASTER has been deprecated, please use PARALLEL MASKED instead. + !$omp parallel master + c = c + 2 + !$omp end parallel master +end subroutine + +subroutine test_master_taskloop_simd() + integer :: i, j = 1 +!WARNING: OpenMP directive MASTER TASKLOOP SIMD has been deprecated, please use MASKED TASKLOOP SIMD instead. + !$omp master taskloop simd + do i=1,10 + j = j + 1 + end do + !$omp end master taskloop simd +end subroutine + +subroutine test_master_taskloop + integer :: i, j = 1 +!WARNING: OpenMP directive MASTER TASKLOOP has been deprecated, please use MASKED TASKLOOP instead. + !$omp master taskloop + do i=1,10 + j = j + 1 + end do + !$omp end master taskloop +end subroutine + +subroutine test_parallel_master_taskloop_simd + integer :: i, j = 1 +!WARNING: OpenMP directive PARALLEL MASTER TASKLOOP SIMD has been deprecated, please use PARALLEL_MASKED TASKLOOP SIMD instead. + !$omp parallel master taskloop simd + do i=1,10 + j = j + 1 + end do + !$omp end parallel master taskloop simd +end subroutine + +subroutine test_parallel_master_taskloop + integer :: i, j = 1 +!WARNING: OpenMP directive PARALLEL MASTER TASKLOOP has been deprecated, please use PARALLEL MASKED TASKLOOP instead. + !$omp parallel master taskloop + do i=1,10 + j = j + 1 + end do + !$omp end parallel master taskloop +end subroutine diff --git a/flang/test/Semantics/OpenMP/flush02.f90 b/flang/test/Semantics/OpenMP/flush02.f90 index f06719f302fd7a..ed0cf6602d574a 100644 --- a/flang/test/Semantics/OpenMP/flush02.f90 +++ b/flang/test/Semantics/OpenMP/flush02.f90 @@ -80,7 +80,7 @@ !$omp parallel num_threads(4) array = (/1, 2, 3, 4, 5, 6, 7, 8, 9, 10/) - !WARNING: OpenMP directive 'master' has been deprecated, please use 'masked' instead. + !WARNING: OpenMP directive MASTER has been deprecated, please use MASKED instead. !$omp master !$omp flush (array) !$omp end master diff --git a/flang/test/Semantics/OpenMP/nested-barrier.f90 b/flang/test/Semantics/OpenMP/nested-barrier.f90 index aae283229e330d..7c635d8e23cc0d 100644 --- a/flang/test/Semantics/OpenMP/nested-barrier.f90 +++ b/flang/test/Semantics/OpenMP/nested-barrier.f90 @@ -75,7 +75,7 @@ program omp_nest_barrier end do !$omp end critical - !WARNING: OpenMP directive 'master' has been deprecated, please use 'masked' instead. + !WARNING: OpenMP directive MASTER has been deprecated, please use MASKED instead. !$omp master do i = 1, 10 k = k + 1 @@ -108,7 +108,7 @@ program omp_nest_barrier end do !$omp end ordered - !WARNING: OpenMP directive 'master' has been deprecated, please use 'masked' instead. + !WARNING: OpenMP directive MASTER has been deprecated, please use MASKED instead. !$omp master do i = 1, 10 !ERROR: `DISTRIBUTE` region has to be strictly nested inside `TEAMS` region. diff --git a/flang/test/Semantics/OpenMP/nested-master.f90 b/flang/test/Semantics/OpenMP/nested-master.f90 index 069de67cafae28..b21ca5d1415931 100644 --- a/flang/test/Semantics/OpenMP/nested-master.f90 +++ b/flang/test/Semantics/OpenMP/nested-master.f90 @@ -9,7 +9,7 @@ program omp_nest_master !$omp do do i = 1, 10 k = k + 1 - !WARNING: OpenMP directive 'master' has been deprecated, please use 'masked' instead. + !WARNING: OpenMP directive MASTER has been deprecated, please use MASKED instead. !ERROR: `MASTER` region may not be closely nested inside of `WORKSHARING`, `LOOP`, `TASK`, `TASKLOOP`, or `ATOMIC` region. !$omp master j = j -1 @@ -17,7 +17,7 @@ program omp_nest_master end do !$omp sections - !WARNING: OpenMP directive 'master' has been deprecated, please use 'masked' instead. + !WARNING: OpenMP directive MASTER has been deprecated, please use MASKED instead. !ERROR: `MASTER` region may not be closely nested inside of `WORKSHARING`, `LOOP`, `TASK`, `TASKLOOP`, or `ATOMIC` region. !$omp master do i = 1, 10 @@ -27,7 +27,7 @@ program omp_nest_master !$omp end sections !$omp single - !WARNING: OpenMP directive 'master' has been deprecated, please use 'masked' instead. + !WARNING: OpenMP directive MASTER has been deprecated, please use MASKED instead. !ERROR: `MASTER` region may not be closely nested inside of `WORKSHARING`, `LOOP`, `TASK`, `TASKLOOP`, or `ATOMIC` region. !$omp master do i = 1, 10 @@ -41,7 +41,7 @@ program omp_nest_master !$omp task do i = 1, 10 k = k + 1 - !WARNING: OpenMP directive 'master' has been deprecated, please use 'masked' instead. + !WARNING: OpenMP directive MASTER has been deprecated, please use MASKED instead. !ERROR: `MASTER` region may not be closely nested inside of `WORKSHARING`, `LOOP`, `TASK`, `TASKLOOP`, or `ATOMIC` region. !$omp master j = j -1 @@ -52,7 +52,7 @@ program omp_nest_master !$omp taskloop do i = 1, 10 k = k + 1 - !WARNING: OpenMP directive 'master' has been deprecated, please use 'masked' instead. + !WARNING: OpenMP directive MASTER has been deprecated, please use MASKED instead. !ERROR: `MASTER` region may not be closely nested inside of `WORKSHARING`, `LOOP`, `TASK`, `TASKLOOP`, or `ATOMIC` region. !$omp master j = j -1 @@ -63,7 +63,7 @@ program omp_nest_master !$omp target parallel do simd do i = 1, 10 k = k + 1 - !WARNING: OpenMP directive 'master' has been deprecated, please use 'masked' instead. + !WARNING: OpenMP directive MASTER has been deprecated, please use MASKED instead. !ERROR: The only OpenMP constructs that can be encountered during execution of a 'SIMD' region are the `ATOMIC` construct, the `LOOP` construct, the `SIMD` construct and the `ORDERED` construct with the `SIMD` clause. !ERROR: `MASTER` region may not be closely nested inside of `WORKSHARING`, `LOOP`, `TASK`, `TASKLOOP`, or `ATOMIC` region. !$omp master @@ -75,7 +75,7 @@ program omp_nest_master !$omp critical do i = 1, 10 k = k + 1 - !WARNING: OpenMP directive 'master' has been deprecated, please use 'masked' instead. + !WARNING: OpenMP directive MASTER has been deprecated, please use MASKED instead. !$omp master j = j -1 !$omp end master @@ -85,7 +85,7 @@ program omp_nest_master !$omp ordered do i = 1, 10 k = k + 1 - !WARNING: OpenMP directive 'master' has been deprecated, please use 'masked' instead. + !WARNING: OpenMP directive MASTER has been deprecated, please use MASKED instead. !$omp master j = j -1 !$omp end master @@ -99,7 +99,7 @@ program omp_nest_master !$omp distribute do k =1, 10 print *, "hello" - !WARNING: OpenMP directive 'master' has been deprecated, please use 'masked' instead. + !WARNING: OpenMP directive MASTER has been deprecated, please use MASKED instead. !$omp master j = j -1 !$omp end master @@ -116,7 +116,7 @@ program omp_nest_master !$omp distribute do k =1, 10 print *, "hello" - !WARNING: OpenMP directive 'master' has been deprecated, please use 'masked' instead. + !WARNING: OpenMP directive MASTER has been deprecated, please use MASKED instead. !$omp master j = j -1 !$omp end master @@ -133,7 +133,7 @@ program omp_nest_master !$omp distribute do k =1, 10 print *, "hello" - !WARNING: OpenMP directive 'master' has been deprecated, please use 'masked' instead. + !WARNING: OpenMP directive MASTER has been deprecated, please use MASKED instead. !ERROR: `MASTER` region may not be closely nested inside of `WORKSHARING`, `LOOP`, `TASK`, `TASKLOOP`, or `ATOMIC` region. !$omp master j = j -1 @@ -151,7 +151,7 @@ program omp_nest_master !$omp distribute do k =1, 10 print *, "hello" - !WARNING: OpenMP directive 'master' has been deprecated, please use 'masked' instead. + !WARNING: OpenMP directive MASTER has been deprecated, please use MASKED instead. !ERROR: `MASTER` region may not be closely nested inside of `WORKSHARING`, `LOOP`, `TASK`, `TASKLOOP`, or `ATOMIC` region. !$omp master j = j -1 diff --git a/flang/test/Semantics/OpenMP/nested-teams.f90 b/flang/test/Semantics/OpenMP/nested-teams.f90 index f3b96b0ab43903..06eea12aba5595 100644 --- a/flang/test/Semantics/OpenMP/nested-teams.f90 +++ b/flang/test/Semantics/OpenMP/nested-teams.f90 @@ -42,7 +42,7 @@ program main !$omp end teams end do - !WARNING: OpenMP directive 'master' has been deprecated, please use 'masked' instead. + !WARNING: OpenMP directive MASTER has been deprecated, please use MASKED instead. !$omp master !ERROR: TEAMS region can only be strictly nested within the implicit parallel region or TARGET region !$omp teams diff --git a/flang/test/Semantics/OpenMP/ordered-simd.f90 b/flang/test/Semantics/OpenMP/ordered-simd.f90 index ed52b759491002..716dc42c28bb64 100644 --- a/flang/test/Semantics/OpenMP/ordered-simd.f90 +++ b/flang/test/Semantics/OpenMP/ordered-simd.f90 @@ -95,7 +95,7 @@ SUBROUTINE ORDERED_BAD(N) !$OMP CRITICAL C = C - A * B - !WARNING: OpenMP directive 'master' has been deprecated, please use 'masked' instead. + !WARNING: OpenMP directive MASTER has been deprecated, please use MASKED instead. !$OMP MASTER DO I = 1,N !ERROR: `ORDERED` region may not be closely nested inside of `CRITICAL`, `ORDERED`, explicit `TASK` or `TASKLOOP` region. @@ -108,7 +108,7 @@ SUBROUTINE ORDERED_BAD(N) !$OMP ORDERED C = C - A * B - !WARNING: OpenMP directive 'master' has been deprecated, please use 'masked' instead. + !WARNING: OpenMP directive MASTER has been deprecated, please use MASKED instead. !$OMP MASTER DO I = 1,N !ERROR: `ORDERED` region may not be closely nested inside of `CRITICAL`, `ORDERED`, explicit `TASK` or `TASKLOOP` region. @@ -121,7 +121,7 @@ SUBROUTINE ORDERED_BAD(N) !$OMP TASK C = C - A * B - !WARNING: OpenMP directive 'master' has been deprecated, please use 'masked' instead. + !WARNING: OpenMP directive MASTER has been deprecated, please use MASKED instead. !ERROR: `MASTER` region may not be closely nested inside of `WORKSHARING`, `LOOP`, `TASK`, `TASKLOOP`, or `ATOMIC` region. !$OMP MASTER DO I = 1,N @@ -136,7 +136,7 @@ SUBROUTINE ORDERED_BAD(N) !$OMP TASKLOOP DO J= 1,N C = C - A * B - !WARNING: OpenMP directive 'master' has been deprecated, please use 'masked' instead. + !WARNING: OpenMP directive MASTER has been deprecated, please use MASKED instead. !ERROR: `MASTER` region may not be closely nested inside of `WORKSHARING`, `LOOP`, `TASK`, `TASKLOOP`, or `ATOMIC` region. !$OMP MASTER DO I = 1,N diff --git a/flang/test/Transforms/debug-index-type.fir b/flang/test/Transforms/debug-index-type.fir new file mode 100644 index 00000000000000..20bd8471d7cf64 --- /dev/null +++ b/flang/test/Transforms/debug-index-type.fir @@ -0,0 +1,10 @@ +// RUN: fir-opt --add-debug-info --mlir-print-debuginfo %s | FileCheck %s + +module attributes {dlti.dl_spec = #dlti.dl_spec<>} { + func.func private @str(%arg0: index) -> i32 loc(#loc1) +} +#loc1 = loc("test.f90":5:1) + +// CHECK: #[[INT32_TY:.*]] = #llvm.di_basic_type +// CHECK: #[[INT64_TY:.*]] = #llvm.di_basic_type +// CHECK: #llvm.di_subroutine_type<{{.*}}types = #[[INT32_TY]], #[[INT64_TY]]> diff --git a/flang/test/Transforms/debug-tuple-type.fir b/flang/test/Transforms/debug-tuple-type.fir new file mode 100644 index 00000000000000..c9b0d16c06e1ae --- /dev/null +++ b/flang/test/Transforms/debug-tuple-type.fir @@ -0,0 +1,15 @@ +// RUN: fir-opt --add-debug-info --mlir-print-debuginfo %s | FileCheck %s + +module attributes {dlti.dl_spec = #dlti.dl_spec<>} { + func.func private @fn1(!fir.ref>) + func.func private @_FortranAioOutputDerivedType(!fir.ref>) +} + +// CHECK: #[[F64:.*]] = #llvm.di_basic_type +// CHECK: #[[CU:.*]] = #llvm.di_compile_unit<{{.*}}> +// CHECK: #[[DTY1:.*]] = #llvm.di_derived_type +// CHECK: #[[DTY2:.*]] = #llvm.di_derived_type +// CHECK: #[[COM_TY1:.*]] = #llvm.di_composite_type +// CHECK: #[[COM_TY2:.*]] = #llvm.di_composite_type +// CHECK: #llvm.di_subroutine_type +// CHECK: #llvm.di_subroutine_type diff --git a/flang/tools/CMakeLists.txt b/flang/tools/CMakeLists.txt index 337545ae0d4d7a..1d2d2c608faf95 100644 --- a/flang/tools/CMakeLists.txt +++ b/flang/tools/CMakeLists.txt @@ -12,3 +12,4 @@ add_subdirectory(flang-driver) add_subdirectory(tco) add_subdirectory(f18-parse-demo) add_subdirectory(fir-opt) +add_subdirectory(fir-lsp-server) diff --git a/flang/tools/fir-lsp-server/CMakeLists.txt b/flang/tools/fir-lsp-server/CMakeLists.txt new file mode 100644 index 00000000000000..ff0ced6693b97f --- /dev/null +++ b/flang/tools/fir-lsp-server/CMakeLists.txt @@ -0,0 +1,17 @@ +set(LLVM_LINK_COMPONENTS + Core + Support + AsmParser + ) + +add_flang_tool(fir-lsp-server fir-lsp-server.cpp) + +get_property(dialect_libs GLOBAL PROPERTY MLIR_DIALECT_LIBS) +get_property(extension_libs GLOBAL PROPERTY MLIR_EXTENSION_LIBS) +target_link_libraries(fir-lsp-server PRIVATE + CUFDialect + FIRDialect + HLFIRDialect + MLIRLspServerLib + ${dialect_libs} + ${extension_libs}) diff --git a/flang/tools/fir-lsp-server/fir-lsp-server.cpp b/flang/tools/fir-lsp-server/fir-lsp-server.cpp new file mode 100644 index 00000000000000..8b724e292b5abb --- /dev/null +++ b/flang/tools/fir-lsp-server/fir-lsp-server.cpp @@ -0,0 +1,9 @@ +#include "mlir/Tools/mlir-lsp-server/MlirLspServerMain.h" +#include "flang/Optimizer/Support/InitFIR.h" + +int main(int argc, char **argv) { + mlir::DialectRegistry registry; + fir::support::registerNonCodegenDialects(registry); + fir::support::addFIRExtensions(registry); + return mlir::failed(mlir::MlirLspServerMain(argc, argv, registry)); +} diff --git a/libc/test/src/math/exhaustive/sinpif_test.cpp b/libc/test/src/math/exhaustive/sinpif_test.cpp index 8bc1d81eb7e3d2..81abac0b73f27a 100644 --- a/libc/test/src/math/exhaustive/sinpif_test.cpp +++ b/libc/test/src/math/exhaustive/sinpif_test.cpp @@ -7,10 +7,8 @@ //===----------------------------------------------------------------------===// #include "exhaustive_test.h" -#include "mpfr.h" #include "src/math/sinpif.h" #include "utils/MPFRWrapper/MPFRUtils.h" -#include namespace mpfr = LIBC_NAMESPACE::testing::mpfr; diff --git a/libclc/CMakeLists.txt b/libclc/CMakeLists.txt index 3d7c3591a556e5..16d74e53295cc1 100644 --- a/libclc/CMakeLists.txt +++ b/libclc/CMakeLists.txt @@ -29,7 +29,13 @@ set_property(DIRECTORY APPEND PROPERTY CMAKE_CONFIGURE_DEPENDS ptx-nvidiacl/lib/SOURCES; r600/lib/SOURCES; spirv/lib/SOURCES; - spirv64/lib/SOURCES + spirv64/lib/SOURCES; + # CLC internal libraries + clc/lib/generic/SOURCES; + clc/lib/clspv/SOURCES; + clc/lib/clspv64/SOURCES; + clc/lib/spirv/SOURCES; + clc/lib/spirv64/SOURCES; ) set( LIBCLC_MIN_LLVM 3.9.0 ) @@ -278,49 +284,30 @@ foreach( t ${LIBCLC_TARGETS_TO_BUILD} ) set( DARCH ${ARCH} ) endif() - # Enumerate SOURCES* files - set( source_list ) - foreach( l ${dirs} ${DARCH} ${DARCH}-${OS} ${DARCH}-${VENDOR}-${OS} ) - foreach( s "SOURCES" "SOURCES_${LLVM_MAJOR}.${LLVM_MINOR}" ) - file( TO_CMAKE_PATH ${l}/lib/${s} file_loc ) - file( TO_CMAKE_PATH ${CMAKE_CURRENT_SOURCE_DIR}/${file_loc} loc ) - # Prepend the location to give higher priority to - # specialized implementation - if( EXISTS ${loc} ) - set( source_list ${file_loc} ${source_list} ) - endif() - endforeach() - endforeach() - - # Add the generated convert.cl here to prevent adding the one listed in - # SOURCES - set( objects ) # A "set" of already-added input files - set( rel_files ) # Source directory input files, relative to the root dir - set( gen_files ) # Generated binary input files, relative to the binary dir - if( NOT ${ARCH} STREQUAL "spirv" AND NOT ${ARCH} STREQUAL "spirv64" ) - if( NOT ENABLE_RUNTIME_SUBNORMAL AND NOT ${ARCH} STREQUAL "clspv" AND - NOT ${ARCH} STREQUAL "clspv64" ) - list( APPEND gen_files convert.cl ) - list( APPEND objects convert.cl ) - list( APPEND rel_files generic/lib/subnormal_use_default.ll ) - elseif(${ARCH} STREQUAL "clspv" OR ${ARCH} STREQUAL "clspv64") - list( APPEND gen_files clspv-convert.cl ) - list( APPEND objects clspv-convert.cl ) + set( clc_lib_files ) + libclc_configure_lib_source( + clc_lib_files + CLC_INTERNAL + LIB_ROOT_DIR clc + DIRS ${dirs} ${DARCH} ${DARCH}-${OS} ${DARCH}-${VENDOR}-${OS} + ) + + set( opencl_lib_files ) + set( opencl_gen_files ) + + if( NOT ARCH STREQUAL spirv AND NOT ARCH STREQUAL spirv64 ) + if( ARCH STREQUAL clspv OR ARCH STREQUAL clspv64 ) + list( APPEND opencl_gen_files clspv-convert.cl ) + elseif ( NOT ENABLE_RUNTIME_SUBNORMAL ) + list( APPEND opencl_gen_files convert.cl ) + list( APPEND opencl_lib_files generic/lib/subnormal_use_default.ll ) endif() endif() - foreach( l ${source_list} ) - file( READ ${l} file_list ) - string( REPLACE "\n" ";" file_list ${file_list} ) - get_filename_component( dir ${l} DIRECTORY ) - foreach( f ${file_list} ) - # Only add each file once, so that targets can 'specialize' builtins - if( NOT ${f} IN_LIST objects ) - list( APPEND objects ${f} ) - list( APPEND rel_files ${dir}/${f} ) - endif() - endforeach() - endforeach() + libclc_configure_lib_source( + opencl_lib_files + DIRS ${dirs} ${DARCH} ${DARCH}-${OS} ${DARCH}-${VENDOR}-${OS} + ) foreach( d ${${t}_devices} ) get_libclc_device_info( @@ -331,11 +318,6 @@ foreach( t ${LIBCLC_TARGETS_TO_BUILD} ) CLANG_TRIPLE clang_triple ) - set( mcpu ) - if( NOT "${cpu}" STREQUAL "" ) - set( mcpu "-mcpu=${cpu}" ) - endif() - message( STATUS " device: ${d} ( ${${d}_aliases} )" ) if ( ARCH STREQUAL spirv OR ARCH STREQUAL spirv64 ) @@ -358,114 +340,41 @@ foreach( t ${LIBCLC_TARGETS_TO_BUILD} ) list( APPEND build_flags -D__CLC_INTERNAL -D${CLC_TARGET_DEFINE} - -I${CMAKE_CURRENT_SOURCE_DIR}/generic/include + # All libclc builtin libraries see CLC headers + -I${CMAKE_CURRENT_SOURCE_DIR}/clc/include # FIXME: Fix libclc to not require disabling this noisy warning -Wno-bitwise-conditional-parentheses ) - set( bytecode_files "" ) - foreach( file IN LISTS gen_files rel_files ) - # We need to take each file and produce an absolute input file, as well - # as a unique architecture-specific output file. We deal with a mix of - # different input files, which makes this trickier. - if( ${file} IN_LIST gen_files ) - # Generated files are given just as file names, which we must make - # absolute to the binary directory. - set( input_file ${CMAKE_CURRENT_BINARY_DIR}/${file} ) - set( output_file "${LIBCLC_ARCH_OBJFILE_DIR}/${file}.bc" ) - else() - # Other files are originally relative to each SOURCE file, which are - # then make relative to the libclc root directory. We must normalize - # the path (e.g., ironing out any ".."), then make it relative to the - # root directory again, and use that relative path component for the - # binary path. - get_filename_component( abs_path ${file} ABSOLUTE BASE_DIR ${CMAKE_CURRENT_SOURCE_DIR} ) - file( RELATIVE_PATH root_rel_path ${CMAKE_CURRENT_SOURCE_DIR} ${abs_path} ) - set( input_file ${CMAKE_CURRENT_SOURCE_DIR}/${file} ) - set( output_file "${LIBCLC_ARCH_OBJFILE_DIR}/${root_rel_path}.bc" ) - endif() - - get_filename_component( file_dir ${file} DIRECTORY ) - - compile_to_bc( - TRIPLE ${clang_triple} - INPUT ${input_file} - OUTPUT ${output_file} - EXTRA_OPTS "${mcpu}" -fno-builtin -nostdlib - "${build_flags}" -I${CMAKE_CURRENT_SOURCE_DIR}/${file_dir} - DEPENDENCIES generate_convert.cl clspv-generate_convert.cl - ) - list( APPEND bytecode_files ${output_file} ) - endforeach() + if( NOT "${cpu}" STREQUAL "" ) + list( APPEND build_flags -mcpu=${cpu} ) + endif() - set( builtins_comp_lib_tgt builtins.comp.${arch_suffix} ) - add_custom_target( ${builtins_comp_lib_tgt} - DEPENDS ${bytecode_files} + add_libclc_builtin_set( + CLC_INTERNAL + ARCH ${ARCH} + ARCH_SUFFIX clc-${arch_suffix} + TRIPLE ${clang_triple} + COMPILE_FLAGS ${build_flags} + OPT_FLAGS ${opt_flags} + LIB_FILES ${clc_lib_files} ) - set_target_properties( ${builtins_comp_lib_tgt} PROPERTIES FOLDER "libclc/Device IR/Comp" ) - set( builtins_link_lib_tgt builtins.link.${arch_suffix} ) - link_bc( - TARGET ${builtins_link_lib_tgt} - INPUTS ${bytecode_files} - DEPENDENCIES ${builtins_comp_lib_tgt} + list( APPEND build_flags + -I${CMAKE_CURRENT_SOURCE_DIR}/generic/include ) - set( builtins_link_lib $ ) - - if( ARCH STREQUAL spirv OR ARCH STREQUAL spirv64 ) - set( spv_suffix ${arch_suffix}.spv ) - add_custom_command( OUTPUT ${spv_suffix} - COMMAND ${llvm-spirv_exe} ${spvflags} -o ${spv_suffix} ${builtins_link_lib} - DEPENDS ${llvm-spirv_target} ${builtins_link_lib} ${builtins_link_lib_tgt} - ) - add_custom_target( "prepare-${spv_suffix}" ALL DEPENDS "${spv_suffix}" ) - set_target_properties( "prepare-${spv_suffix}" PROPERTIES FOLDER "libclc/Device IR/Prepare" ) - install( FILES ${CMAKE_CURRENT_BINARY_DIR}/${spv_suffix} - DESTINATION "${CMAKE_INSTALL_DATADIR}/clc" ) - else() - set( builtins_opt_lib_tgt builtins.opt.${arch_suffix} ) - - # Add opt target - add_custom_command( OUTPUT ${builtins_opt_lib_tgt}.bc - COMMAND ${opt_exe} ${opt_flags} -o ${builtins_opt_lib_tgt}.bc - ${builtins_link_lib} - DEPENDS ${opt_target} ${builtins_link_lib} ${builtins_link_lib_tgt} - ) - add_custom_target( ${builtins_opt_lib_tgt} - ALL DEPENDS ${builtins_opt_lib_tgt}.bc - ) - set_target_properties( ${builtins_opt_lib_tgt} PROPERTIES - TARGET_FILE ${CMAKE_CURRENT_BINARY_DIR}/${builtins_opt_lib_tgt}.bc - FOLDER "libclc/Device IR/Opt" - ) - - set( builtins_opt_lib $ ) - - # Add prepare target - set( obj_suffix ${arch_suffix}.bc ) - add_custom_command( OUTPUT ${obj_suffix} - COMMAND ${prepare_builtins_exe} -o ${obj_suffix} ${builtins_opt_lib} - DEPENDS ${builtins_opt_lib} ${builtins_opt_lib_tgt} ${prepare_builtins_target} ) - add_custom_target( prepare-${obj_suffix} ALL DEPENDS ${obj_suffix} ) - set_target_properties( "prepare-${obj_suffix}" PROPERTIES FOLDER "libclc/Device IR/Prepare" ) - - # nvptx-- targets don't include workitem builtins - if( NOT clang_triple MATCHES ".*ptx.*--$" ) - add_test( NAME external-calls-${obj_suffix} - COMMAND ./check_external_calls.sh ${CMAKE_CURRENT_BINARY_DIR}/${obj_suffix} ${LLVM_TOOLS_BINARY_DIR} - WORKING_DIRECTORY ${CMAKE_CURRENT_SOURCE_DIR} ) - endif() - - install( FILES ${CMAKE_CURRENT_BINARY_DIR}/${obj_suffix} DESTINATION "${CMAKE_INSTALL_DATADIR}/clc" ) - foreach( a ${${d}_aliases} ) - set( alias_suffix "${a}-${clang_triple}.bc" ) - add_custom_target( ${alias_suffix} ALL - COMMAND ${CMAKE_COMMAND} -E create_symlink ${obj_suffix} ${alias_suffix} - DEPENDS prepare-${obj_suffix} ) - set_target_properties( "${alias_suffix}" PROPERTIES FOLDER "libclc/Device IR/Aliases" ) - install( FILES ${CMAKE_CURRENT_BINARY_DIR}/${alias_suffix} DESTINATION "${CMAKE_INSTALL_DATADIR}/clc" ) - endforeach( a ) - endif() + add_libclc_builtin_set( + ARCH ${ARCH} + ARCH_SUFFIX ${arch_suffix} + TRIPLE ${clang_triple} + COMPILE_FLAGS ${build_flags} + OPT_FLAGS ${opt_flags} + LIB_FILES ${opencl_lib_files} + GEN_FILES ${opencl_gen_files} + ALIASES ${${d}_aliases} + # Link in the CLC builtins and internalize their symbols + INTERNAL_LINK_DEPENDENCIES $ + ) endforeach( d ) endforeach( t ) diff --git a/libclc/generic/include/clc/clcfunc.h b/libclc/clc/include/clc/clcfunc.h similarity index 85% rename from libclc/generic/include/clc/clcfunc.h rename to libclc/clc/include/clc/clcfunc.h index 086d780b970859..fe3406f64fecb8 100644 --- a/libclc/generic/include/clc/clcfunc.h +++ b/libclc/clc/include/clc/clcfunc.h @@ -1,3 +1,6 @@ +#ifndef __CLC_CLCFUNC_H_ +#define __CLC_CLCFUNC_H_ + #define _CLC_OVERLOAD __attribute__((overloadable)) #define _CLC_DECL #define _CLC_INLINE __attribute__((always_inline)) inline @@ -11,3 +14,5 @@ #else #define _CLC_DEF __attribute__((always_inline)) #endif + +#endif // __CLC_CLCFUNC_H_ diff --git a/libclc/generic/include/clc/clctypes.h b/libclc/clc/include/clc/clctypes.h similarity index 94% rename from libclc/generic/include/clc/clctypes.h rename to libclc/clc/include/clc/clctypes.h index 76b816d395c288..8ededd967e0033 100644 --- a/libclc/generic/include/clc/clctypes.h +++ b/libclc/clc/include/clc/clctypes.h @@ -1,3 +1,6 @@ +#ifndef __CLC_CLCTYPES_H_ +#define __CLC_CLCTYPES_H_ + /* 6.1.1 Built-in Scalar Data Types */ typedef unsigned char uchar; @@ -8,12 +11,12 @@ typedef unsigned long ulong; typedef __SIZE_TYPE__ size_t; typedef __PTRDIFF_TYPE__ ptrdiff_t; -#define __stdint_join3(a,b,c) a ## b ## c +#define __stdint_join3(a, b, c) a##b##c -#define __intn_t(n) __stdint_join3(__INT, n, _TYPE__) +#define __intn_t(n) __stdint_join3(__INT, n, _TYPE__) #define __uintn_t(n) __stdint_join3(unsigned __INT, n, _TYPE__) -typedef __intn_t(__INTPTR_WIDTH__) intptr_t; +typedef __intn_t(__INTPTR_WIDTH__) intptr_t; typedef __uintn_t(__INTPTR_WIDTH__) uintptr_t; #undef __uintn_t @@ -93,3 +96,5 @@ typedef __attribute__((ext_vector_type(4))) half half4; typedef __attribute__((ext_vector_type(8))) half half8; typedef __attribute__((ext_vector_type(16))) half half16; #endif + +#endif // __CLC_CLCTYPES_H_ diff --git a/libclc/clc/include/clc/geometric/clc_dot.h b/libclc/clc/include/clc/geometric/clc_dot.h new file mode 100644 index 00000000000000..e0e47ab2093efd --- /dev/null +++ b/libclc/clc/include/clc/geometric/clc_dot.h @@ -0,0 +1,2 @@ +#define __CLC_BODY +#include diff --git a/libclc/clc/include/clc/geometric/clc_dot.inc b/libclc/clc/include/clc/geometric/clc_dot.inc new file mode 100644 index 00000000000000..016b564df362d2 --- /dev/null +++ b/libclc/clc/include/clc/geometric/clc_dot.inc @@ -0,0 +1 @@ +_CLC_OVERLOAD _CLC_DECL __CLC_FLOAT __clc_dot(__CLC_FLOATN p0, __CLC_FLOATN p1); diff --git a/libclc/clc/include/clc/internal/clc.h b/libclc/clc/include/clc/internal/clc.h new file mode 100644 index 00000000000000..c3bdfd754105f7 --- /dev/null +++ b/libclc/clc/include/clc/internal/clc.h @@ -0,0 +1,26 @@ +#ifndef __CLC_INTERNAL_CLC_H_ +#define __CLC_INTERNAL_CLC_H_ + +#ifndef cl_clang_storage_class_specifiers +#error Implementation requires cl_clang_storage_class_specifiers extension! +#endif + +#pragma OPENCL EXTENSION cl_clang_storage_class_specifiers : enable + +#ifdef cl_khr_fp64 +#pragma OPENCL EXTENSION cl_khr_fp64 : enable +#endif + +#ifdef cl_khr_fp16 +#pragma OPENCL EXTENSION cl_khr_fp16 : enable +#endif + +/* Function Attributes */ +#include + +/* 6.1 Supported Data Types */ +#include + +#pragma OPENCL EXTENSION all : disable + +#endif // __CLC_INTERNAL_CLC_H_ diff --git a/libclc/clc/lib/clspv/SOURCES b/libclc/clc/lib/clspv/SOURCES new file mode 100644 index 00000000000000..75a3130357c345 --- /dev/null +++ b/libclc/clc/lib/clspv/SOURCES @@ -0,0 +1 @@ +dummy.cl diff --git a/libclc/clc/lib/clspv/dummy.cl b/libclc/clc/lib/clspv/dummy.cl new file mode 100644 index 00000000000000..fab17ac780e375 --- /dev/null +++ b/libclc/clc/lib/clspv/dummy.cl @@ -0,0 +1 @@ +// Empty file diff --git a/libclc/clc/lib/clspv64 b/libclc/clc/lib/clspv64 new file mode 120000 index 00000000000000..ea01ba94bc6368 --- /dev/null +++ b/libclc/clc/lib/clspv64 @@ -0,0 +1 @@ +clspv \ No newline at end of file diff --git a/libclc/clc/lib/generic/SOURCES b/libclc/clc/lib/generic/SOURCES new file mode 100644 index 00000000000000..fa2e4f50b99cd7 --- /dev/null +++ b/libclc/clc/lib/generic/SOURCES @@ -0,0 +1 @@ +geometric/clc_dot.cl diff --git a/libclc/clc/lib/generic/geometric/clc_dot.cl b/libclc/clc/lib/generic/geometric/clc_dot.cl new file mode 100644 index 00000000000000..bf0f19b51bc05e --- /dev/null +++ b/libclc/clc/lib/generic/geometric/clc_dot.cl @@ -0,0 +1,57 @@ +#include + +_CLC_OVERLOAD _CLC_DEF float __clc_dot(float p0, float p1) { return p0 * p1; } + +_CLC_OVERLOAD _CLC_DEF float __clc_dot(float2 p0, float2 p1) { + return p0.x * p1.x + p0.y * p1.y; +} + +_CLC_OVERLOAD _CLC_DEF float __clc_dot(float3 p0, float3 p1) { + return p0.x * p1.x + p0.y * p1.y + p0.z * p1.z; +} + +_CLC_OVERLOAD _CLC_DEF float __clc_dot(float4 p0, float4 p1) { + return p0.x * p1.x + p0.y * p1.y + p0.z * p1.z + p0.w * p1.w; +} + +#ifdef cl_khr_fp64 + +#pragma OPENCL EXTENSION cl_khr_fp64 : enable + +_CLC_OVERLOAD _CLC_DEF double __clc_dot(double p0, double p1) { + return p0 * p1; +} + +_CLC_OVERLOAD _CLC_DEF double __clc_dot(double2 p0, double2 p1) { + return p0.x * p1.x + p0.y * p1.y; +} + +_CLC_OVERLOAD _CLC_DEF double __clc_dot(double3 p0, double3 p1) { + return p0.x * p1.x + p0.y * p1.y + p0.z * p1.z; +} + +_CLC_OVERLOAD _CLC_DEF double __clc_dot(double4 p0, double4 p1) { + return p0.x * p1.x + p0.y * p1.y + p0.z * p1.z + p0.w * p1.w; +} + +#endif + +#ifdef cl_khr_fp16 + +#pragma OPENCL EXTENSION cl_khr_fp16 : enable + +_CLC_OVERLOAD _CLC_DEF half __clc_dot(half p0, half p1) { return p0 * p1; } + +_CLC_OVERLOAD _CLC_DEF half __clc_dot(half2 p0, half2 p1) { + return p0.x * p1.x + p0.y * p1.y; +} + +_CLC_OVERLOAD _CLC_DEF half __clc_dot(half3 p0, half3 p1) { + return p0.x * p1.x + p0.y * p1.y + p0.z * p1.z; +} + +_CLC_OVERLOAD _CLC_DEF half __clc_dot(half4 p0, half4 p1) { + return p0.x * p1.x + p0.y * p1.y + p0.z * p1.z + p0.w * p1.w; +} + +#endif diff --git a/libclc/clc/lib/spirv/SOURCES b/libclc/clc/lib/spirv/SOURCES new file mode 100644 index 00000000000000..d8effd19613c8b --- /dev/null +++ b/libclc/clc/lib/spirv/SOURCES @@ -0,0 +1,2 @@ +../generic/geometric/clc_dot.cl + diff --git a/libclc/clc/lib/spirv64/SOURCES b/libclc/clc/lib/spirv64/SOURCES new file mode 100644 index 00000000000000..9200810ace38e7 --- /dev/null +++ b/libclc/clc/lib/spirv64/SOURCES @@ -0,0 +1 @@ +../generic/geometric/clc_dot.cl diff --git a/libclc/cmake/modules/AddLibclc.cmake b/libclc/cmake/modules/AddLibclc.cmake index f2032660ba99b0..ee7c8500c8359f 100644 --- a/libclc/cmake/modules/AddLibclc.cmake +++ b/libclc/cmake/modules/AddLibclc.cmake @@ -76,6 +76,8 @@ endfunction() # Links together one or more bytecode files # # Arguments: +# * INTERNALIZE +# Set if -internalize flag should be passed when linking # * TARGET # Custom target to create # * INPUT ... @@ -84,7 +86,7 @@ endfunction() # List of extra dependencies to inject function(link_bc) cmake_parse_arguments(ARG - "" + "INTERNALIZE" "TARGET" "INPUTS;DEPENDENCIES" ${ARGN} @@ -97,7 +99,7 @@ function(link_bc) file( TO_CMAKE_PATH ${LIBCLC_ARCH_OBJFILE_DIR}/${ARG_TARGET}.rsp RSP_FILE ) # Turn it into a space-separate list of input files list( JOIN ARG_INPUTS " " RSP_INPUT ) - file( WRITE ${RSP_FILE} ${RSP_INPUT} ) + file( GENERATE OUTPUT ${RSP_FILE} CONTENT ${RSP_INPUT} ) # Ensure that if this file is removed, we re-run CMake set_property( DIRECTORY APPEND PROPERTY CMAKE_CONFIGURE_DEPENDS ${RSP_FILE} @@ -107,7 +109,7 @@ function(link_bc) add_custom_command( OUTPUT ${ARG_TARGET}.bc - COMMAND ${llvm-link_exe} -o ${ARG_TARGET}.bc ${LINK_INPUT_ARG} + COMMAND ${llvm-link_exe} $<$:--internalize> -o ${ARG_TARGET}.bc ${LINK_INPUT_ARG} DEPENDS ${llvm-link_target} ${ARG_DEPENDENCIES} ${ARG_INPUTS} ${RSP_FILE} ) @@ -178,3 +180,251 @@ function(get_libclc_device_info) set( ${ARG_CLANG_TRIPLE} ${ARG_TRIPLE} PARENT_SCOPE ) endif() endfunction() + +# Compiles a list of library source files (provided by LIB_FILES/GEN_FILES) and +# compiles them to LLVM bytecode (or SPIR-V), links them together and optimizes +# them. +# +# For bytecode libraries, a list of ALIASES may optionally be provided to +# produce additional symlinks. +# +# Arguments: +# * ARCH +# libclc architecture being built +# * ARCH_SUFFIX +# libclc architecture/triple suffix +# * TRIPLE +# Triple used to compile +# +# Optional Arguments: +# * CLC_INTERNAL +# Pass if compiling the internal CLC builtin libraries, which are not +# optimized and do not have aliases created. +# * LIB_FILES ... +# List of files that should be built for this library +# * GEN_FILES ... +# List of generated files (in build dir) that should be built for this library +# * COMPILE_FLAGS ... +# Compilation options (for clang) +# * OPT_FLAGS ... +# Optimization options (for opt) +# * ALIASES ... +# List of aliases +# * INTERNAL_LINK_DEPENDENCIES ... +# A list of extra bytecode files to link into the builtin library. Symbols +# from these link dependencies will be internalized during linking. +function(add_libclc_builtin_set) + cmake_parse_arguments(ARG + "CLC_INTERNAL" + "ARCH;TRIPLE;ARCH_SUFFIX" + "LIB_FILES;GEN_FILES;COMPILE_FLAGS;OPT_FLAGS;ALIASES;INTERNAL_LINK_DEPENDENCIES" + ${ARGN} + ) + + if( NOT ARG_ARCH OR NOT ARG_ARCH_SUFFIX OR NOT ARG_TRIPLE ) + message( FATAL_ERROR "Must provide ARCH, ARCH_SUFFIX, and TRIPLE" ) + endif() + + set( bytecode_files "" ) + foreach( file IN LISTS ARG_GEN_FILES ARG_LIB_FILES ) + # We need to take each file and produce an absolute input file, as well + # as a unique architecture-specific output file. We deal with a mix of + # different input files, which makes this trickier. + if( ${file} IN_LIST ARG_GEN_FILES ) + # Generated files are given just as file names, which we must make + # absolute to the binary directory. + set( input_file ${CMAKE_CURRENT_BINARY_DIR}/${file} ) + set( output_file "${LIBCLC_ARCH_OBJFILE_DIR}/${file}.bc" ) + else() + # Other files are originally relative to each SOURCE file, which are + # then make relative to the libclc root directory. We must normalize + # the path (e.g., ironing out any ".."), then make it relative to the + # root directory again, and use that relative path component for the + # binary path. + get_filename_component( abs_path ${file} ABSOLUTE BASE_DIR ${CMAKE_CURRENT_SOURCE_DIR} ) + file( RELATIVE_PATH root_rel_path ${CMAKE_CURRENT_SOURCE_DIR} ${abs_path} ) + set( input_file ${CMAKE_CURRENT_SOURCE_DIR}/${file} ) + set( output_file "${LIBCLC_ARCH_OBJFILE_DIR}/${root_rel_path}.bc" ) + endif() + + get_filename_component( file_dir ${file} DIRECTORY ) + + compile_to_bc( + TRIPLE ${ARG_TRIPLE} + INPUT ${input_file} + OUTPUT ${output_file} + EXTRA_OPTS -fno-builtin -nostdlib + "${ARG_COMPILE_FLAGS}" -I${CMAKE_CURRENT_SOURCE_DIR}/${file_dir} + DEPENDENCIES generate_convert.cl clspv-generate_convert.cl + ) + list( APPEND bytecode_files ${output_file} ) + endforeach() + + set( builtins_comp_lib_tgt builtins.comp.${ARG_ARCH_SUFFIX} ) + add_custom_target( ${builtins_comp_lib_tgt} + DEPENDS ${bytecode_files} + ) + set_target_properties( ${builtins_comp_lib_tgt} PROPERTIES FOLDER "libclc/Device IR/Comp" ) + + if( NOT bytecode_files ) + message(FATAL_ERROR "Cannot create an empty builtins library") + endif() + + set( builtins_link_lib_tgt builtins.link.${ARG_ARCH_SUFFIX} ) + + if( NOT ARG_INTERNAL_LINK_DEPENDENCIES ) + link_bc( + TARGET ${builtins_link_lib_tgt} + INPUTS ${bytecode_files} + DEPENDENCIES ${builtins_comp_lib_tgt} + ) + else() + # If we have libraries to link while internalizing their symbols, we need + # two separate link steps; the --internalize flag applies to all link + # inputs but the first. + set( builtins_link_lib_tmp_tgt builtins.link.pre-deps.${ARG_ARCH_SUFFIX} ) + link_bc( + TARGET ${builtins_link_lib_tmp_tgt} + INPUTS ${bytecode_files} + DEPENDENCIES ${builtins_comp_lib_tgt} + ) + link_bc( + INTERNALIZE + TARGET ${builtins_link_lib_tgt} + INPUTS $ + ${ARG_INTERNAL_LINK_DEPENDENCIES} + DEPENDENCIES ${builtins_link_lib_tmp_tgt} + ) + endif() + + # For the CLC internal builtins, exit here - we only optimize the targets' + # entry points once we've linked the CLC buitins into them + if( ARG_CLC_INTERNAL ) + return() + endif() + + set( builtins_link_lib $ ) + + if( ARG_ARCH STREQUAL spirv OR ARG_ARCH STREQUAL spirv64 ) + set( spv_suffix ${ARG_ARCH_SUFFIX}.spv ) + add_custom_command( OUTPUT ${spv_suffix} + COMMAND ${llvm-spirv_exe} ${spvflags} -o ${spv_suffix} ${builtins_link_lib} + DEPENDS ${llvm-spirv_target} ${builtins_link_lib} ${builtins_link_lib_tgt} + ) + add_custom_target( "prepare-${spv_suffix}" ALL DEPENDS "${spv_suffix}" ) + set_target_properties( "prepare-${spv_suffix}" PROPERTIES FOLDER "libclc/Device IR/Prepare" ) + install( FILES ${CMAKE_CURRENT_BINARY_DIR}/${spv_suffix} + DESTINATION "${CMAKE_INSTALL_DATADIR}/clc" ) + + return() + endif() + + set( builtins_opt_lib_tgt builtins.opt.${ARG_ARCH_SUFFIX} ) + + # Add opt target + add_custom_command( OUTPUT ${builtins_opt_lib_tgt}.bc + COMMAND ${opt_exe} ${ARG_OPT_FLAGS} -o ${builtins_opt_lib_tgt}.bc + ${builtins_link_lib} + DEPENDS ${opt_target} ${builtins_link_lib} ${builtins_link_lib_tgt} + ) + add_custom_target( ${builtins_opt_lib_tgt} + ALL DEPENDS ${builtins_opt_lib_tgt}.bc + ) + set_target_properties( ${builtins_opt_lib_tgt} PROPERTIES + TARGET_FILE ${CMAKE_CURRENT_BINARY_DIR}/${builtins_opt_lib_tgt}.bc + FOLDER "libclc/Device IR/Opt" + ) + + set( builtins_opt_lib $ ) + + # Add prepare target + set( obj_suffix ${ARG_ARCH_SUFFIX}.bc ) + add_custom_command( OUTPUT ${obj_suffix} + COMMAND ${prepare_builtins_exe} -o ${obj_suffix} ${builtins_opt_lib} + DEPENDS ${builtins_opt_lib} ${builtins_opt_lib_tgt} ${prepare_builtins_target} ) + add_custom_target( prepare-${obj_suffix} ALL DEPENDS ${obj_suffix} ) + set_target_properties( "prepare-${obj_suffix}" PROPERTIES FOLDER "libclc/Device IR/Prepare" ) + + # nvptx-- targets don't include workitem builtins + if( NOT ARG_TRIPLE MATCHES ".*ptx.*--$" ) + add_test( NAME external-calls-${obj_suffix} + COMMAND ./check_external_calls.sh ${CMAKE_CURRENT_BINARY_DIR}/${obj_suffix} ${LLVM_TOOLS_BINARY_DIR} + WORKING_DIRECTORY ${CMAKE_CURRENT_SOURCE_DIR} ) + endif() + + install( FILES ${CMAKE_CURRENT_BINARY_DIR}/${obj_suffix} DESTINATION "${CMAKE_INSTALL_DATADIR}/clc" ) + foreach( a ${ARG_ALIASES} ) + set( alias_suffix "${a}-${ARG_TRIPLE}.bc" ) + add_custom_target( ${alias_suffix} ALL + COMMAND ${CMAKE_COMMAND} -E create_symlink ${obj_suffix} ${alias_suffix} + DEPENDS prepare-${obj_suffix} ) + set_target_properties( "${alias_suffix}" PROPERTIES FOLDER "libclc/Device IR/Aliases" ) + install( FILES ${CMAKE_CURRENT_BINARY_DIR}/${alias_suffix} DESTINATION "${CMAKE_INSTALL_DATADIR}/clc" ) + endforeach( a ) +endfunction(add_libclc_builtin_set) + +# Produces a list of libclc source files by walking over SOURCES files in a +# given directory. Outputs the list of files in LIB_FILE_LIST. +# +# LIB_FILE_LIST may be pre-populated and is appended to. +# +# Arguments: +# * CLC_INTERNAL +# Pass if compiling the internal CLC builtin libraries, which have a +# different directory structure. +# * LIB_ROOT_DIR +# Root directory containing target's lib files, relative to libclc root +# directory. If not provided, is set to '.'. +# * DIRS ... +# List of directories under LIB_ROOT_DIR to walk over searching for SOURCES +# files +function(libclc_configure_lib_source LIB_FILE_LIST) + cmake_parse_arguments(ARG + "CLC_INTERNAL" + "LIB_ROOT_DIR" + "DIRS" + ${ARGN} + ) + + if( NOT ARG_LIB_ROOT_DIR ) + set(ARG_LIB_ROOT_DIR ".") + endif() + + # Enumerate SOURCES* files + set( source_list ) + foreach( l ${ARG_DIRS} ) + foreach( s "SOURCES" "SOURCES_${LLVM_VERSION_MAJOR}.${LLVM_VERSION_MINOR}" ) + if( ARG_CLC_INTERNAL ) + file( TO_CMAKE_PATH ${ARG_LIB_ROOT_DIR}/lib/${l}/${s} file_loc ) + else() + file( TO_CMAKE_PATH ${ARG_LIB_ROOT_DIR}/${l}/lib/${s} file_loc ) + endif() + file( TO_CMAKE_PATH ${CMAKE_CURRENT_SOURCE_DIR}/${file_loc} loc ) + # Prepend the location to give higher priority to + # specialized implementation + if( EXISTS ${loc} ) + set( source_list ${file_loc} ${source_list} ) + endif() + endforeach() + endforeach() + + ## Add the generated convert files here to prevent adding the ones listed in + ## SOURCES + set( rel_files ${${LIB_FILE_LIST}} ) # Source directory input files, relative to the root dir + set( objects ${${LIB_FILE_LIST}} ) # A "set" of already-added input files + + foreach( l ${source_list} ) + file( READ ${l} file_list ) + string( REPLACE "\n" ";" file_list ${file_list} ) + get_filename_component( dir ${l} DIRECTORY ) + foreach( f ${file_list} ) + # Only add each file once, so that targets can 'specialize' builtins + if( NOT ${f} IN_LIST objects ) + list( APPEND objects ${f} ) + list( APPEND rel_files ${dir}/${f} ) + endif() + endforeach() + endforeach() + + set( ${LIB_FILE_LIST} ${rel_files} PARENT_SCOPE ) +endfunction(libclc_configure_lib_source LIB_FILE_LIST) diff --git a/libclc/generic/lib/geometric/dot.cl b/libclc/generic/lib/geometric/dot.cl index e58bc26f4333a7..e790d02636563c 100644 --- a/libclc/generic/lib/geometric/dot.cl +++ b/libclc/generic/lib/geometric/dot.cl @@ -1,19 +1,20 @@ #include +#include _CLC_OVERLOAD _CLC_DEF float dot(float p0, float p1) { - return p0*p1; + return __clc_dot(p0, p1); } _CLC_OVERLOAD _CLC_DEF float dot(float2 p0, float2 p1) { - return p0.x*p1.x + p0.y*p1.y; + return __clc_dot(p0, p1); } _CLC_OVERLOAD _CLC_DEF float dot(float3 p0, float3 p1) { - return p0.x*p1.x + p0.y*p1.y + p0.z*p1.z; + return __clc_dot(p0, p1); } _CLC_OVERLOAD _CLC_DEF float dot(float4 p0, float4 p1) { - return p0.x*p1.x + p0.y*p1.y + p0.z*p1.z + p0.w*p1.w; + return __clc_dot(p0, p1); } #ifdef cl_khr_fp64 @@ -21,19 +22,19 @@ _CLC_OVERLOAD _CLC_DEF float dot(float4 p0, float4 p1) { #pragma OPENCL EXTENSION cl_khr_fp64 : enable _CLC_OVERLOAD _CLC_DEF double dot(double p0, double p1) { - return p0*p1; + return __clc_dot(p0, p1); } _CLC_OVERLOAD _CLC_DEF double dot(double2 p0, double2 p1) { - return p0.x*p1.x + p0.y*p1.y; + return __clc_dot(p0, p1); } _CLC_OVERLOAD _CLC_DEF double dot(double3 p0, double3 p1) { - return p0.x*p1.x + p0.y*p1.y + p0.z*p1.z; + return __clc_dot(p0, p1); } _CLC_OVERLOAD _CLC_DEF double dot(double4 p0, double4 p1) { - return p0.x*p1.x + p0.y*p1.y + p0.z*p1.z + p0.w*p1.w; + return __clc_dot(p0, p1); } #endif @@ -42,20 +43,18 @@ _CLC_OVERLOAD _CLC_DEF double dot(double4 p0, double4 p1) { #pragma OPENCL EXTENSION cl_khr_fp16 : enable -_CLC_OVERLOAD _CLC_DEF half dot(half p0, half p1) { - return p0*p1; -} +_CLC_OVERLOAD _CLC_DEF half dot(half p0, half p1) { return __clc_dot(p0, p1); } _CLC_OVERLOAD _CLC_DEF half dot(half2 p0, half2 p1) { - return p0.x*p1.x + p0.y*p1.y; + return __clc_dot(p0, p1); } _CLC_OVERLOAD _CLC_DEF half dot(half3 p0, half3 p1) { - return p0.x*p1.x + p0.y*p1.y + p0.z*p1.z; + return __clc_dot(p0, p1); } _CLC_OVERLOAD _CLC_DEF half dot(half4 p0, half4 p1) { - return p0.x*p1.x + p0.y*p1.y + p0.z*p1.z + p0.w*p1.w; + return __clc_dot(p0, p1); } #endif diff --git a/libcxx/CMakeLists.txt b/libcxx/CMakeLists.txt index 574b262018cd3a..95a7d10f055ea7 100644 --- a/libcxx/CMakeLists.txt +++ b/libcxx/CMakeLists.txt @@ -45,10 +45,6 @@ include(CMakeDependentOption) include(HandleCompilerRT) # Basic options --------------------------------------------------------------- -option(LIBCXX_ENABLE_ASSERTIONS - "Enable assertions inside the compiled library, and at the same time make it the - default when compiling user code. Note that assertions can be enabled or disabled - by users in their own code regardless of this option." OFF) option(LIBCXX_ENABLE_SHARED "Build libc++ as a shared library." ON) option(LIBCXX_ENABLE_STATIC "Build libc++ as a static library." ON) option(LIBCXX_ENABLE_FILESYSTEM @@ -759,9 +755,9 @@ config_define_if_not(LIBCXX_ENABLE_WIDE_CHARACTERS _LIBCPP_HAS_NO_WIDE_CHARACTER config_define_if_not(LIBCXX_ENABLE_TIME_ZONE_DATABASE _LIBCPP_HAS_NO_TIME_ZONE_DATABASE) config_define_if_not(LIBCXX_ENABLE_VENDOR_AVAILABILITY_ANNOTATIONS _LIBCPP_HAS_NO_VENDOR_AVAILABILITY_ANNOTATIONS) +# TODO: Remove in LLVM 21. We're leaving an error to make this fail explicitly. if (LIBCXX_ENABLE_ASSERTIONS) - message(DEPRECATION "LIBCXX_ENABLE_ASSERTIONS is deprecated and will be removed in LLVM 20. Please use LIBCXX_HARDENING_MODE instead.") - set(LIBCXX_HARDENING_MODE "extensive") + message(FATAL_ERROR "LIBCXX_ENABLE_ASSERTIONS has been removed. Please use LIBCXX_HARDENING_MODE instead.") endif() if (LIBCXX_HARDENING_MODE STREQUAL "none") config_define(2 _LIBCPP_HARDENING_MODE_DEFAULT) diff --git a/libcxx/docs/ReleaseNotes/20.rst b/libcxx/docs/ReleaseNotes/20.rst index 84080e7cbafe2c..bf3aafe6139ee9 100644 --- a/libcxx/docs/ReleaseNotes/20.rst +++ b/libcxx/docs/ReleaseNotes/20.rst @@ -38,6 +38,7 @@ What's New in Libc++ 20.0.0? Implemented Papers ------------------ +- P0619R4: Reviewing Deprecated Facilities of C++17 for C++20 (`Github `__) - P2747R2: ``constexpr`` placement new (`Github `__) - P2609R3: Relaxing Ranges Just A Smidge (`Github `__) - P2985R0: A type trait for detecting virtual base classes (`Github `__) @@ -64,8 +65,9 @@ Improvements and New Features Deprecations and Removals ------------------------- -- TODO: The ``LIBCXX_ENABLE_ASSERTIONS`` CMake variable and the ``_LIBCPP_ENABLE_ASSERTIONS`` macro that were used to - enable the safe mode will be removed in LLVM 20. +- The ``LIBCXX_ENABLE_ASSERTIONS`` CMake variable and the ``_LIBCPP_ENABLE_ASSERTIONS`` macro that were used to + enable the safe mode have been removed in LLVM 20. Please use :ref:`support for hardening ` + instead. - Support for the C++20 synchronization library (````, ````, ``atomic::wait``, etc.) has been removed in language modes prior to C++20. If you are using these features prior to C++20, you will need to @@ -88,15 +90,14 @@ Deprecations and Removals the ``_LIBCPP_VERBOSE_ABORT_NOT_NOEXCEPT`` macro can be defined to make the function non-``noexcept``. That macro will be removed in LLVM 21. +- ````, ```` (previously missing), ````, and ```` are deprecated since C++17 as + specified by the standard. They, together with ````, are removed in C++20, but libc++ still provides these + headers as an extension and only deprecates them. The ``_LIBCPP_DISABLE_DEPRECATION_WARNINGS`` macro can be defined to + suppress deprecation for these headers. + Upcoming Deprecations and Removals ---------------------------------- -LLVM 20 -~~~~~~~ - -- TODO - - LLVM 21 ~~~~~~~ diff --git a/libcxx/docs/Status/Cxx20Papers.csv b/libcxx/docs/Status/Cxx20Papers.csv index 9a057be8ad0519..5cd77be4d58def 100644 --- a/libcxx/docs/Status/Cxx20Papers.csv +++ b/libcxx/docs/Status/Cxx20Papers.csv @@ -34,7 +34,7 @@ "`P0528R3 `__","The Curious Case of Padding Bits, Featuring Atomic Compare-and-Exchange","2018-06 (Rapperswil)","","","" "`P0542R5 `__","Support for contract based programming in C++","2018-06 (Rapperswil)","|Nothing To Do|","n/a","Pulled at the 2019-07 meeting in Cologne" "`P0556R3 `__","Integral power-of-2 operations","2018-06 (Rapperswil)","|Complete|","9.0","" -"`P0619R4 `__","Reviewing Deprecated Facilities of C++17 for C++20","2018-06 (Rapperswil)","|Partial|","","Only sections D.7, D.8, D.9, D.10, D.11, D.12, and D.13 are implemented. Section D.4 remains undone." +"`P0619R4 `__","Reviewing Deprecated Facilities of C++17 for C++20","2018-06 (Rapperswil)","|Complete|","20.0","Removed headers are still provided as an extension, but with deprecation warnings" "`P0646R1 `__","Improving the Return Value of Erase-Like Algorithms","2018-06 (Rapperswil)","|Complete|","10.0","" "`P0722R3 `__","Efficient sized delete for variable sized classes","2018-06 (Rapperswil)","|Complete|","9.0","" "`P0758R1 `__","Implicit conversion traits and utility functions","2018-06 (Rapperswil)","|Complete|","","" diff --git a/libcxx/include/CMakeLists.txt b/libcxx/include/CMakeLists.txt index e84a55e25f2fa4..87eaf64b245017 100644 --- a/libcxx/include/CMakeLists.txt +++ b/libcxx/include/CMakeLists.txt @@ -923,6 +923,7 @@ set(files coroutine csetjmp csignal + cstdalign cstdarg cstdbool cstddef diff --git a/libcxx/include/__algorithm/comp.h b/libcxx/include/__algorithm/comp.h index 1f38f5d2d99b43..ab3c598418828a 100644 --- a/libcxx/include/__algorithm/comp.h +++ b/libcxx/include/__algorithm/comp.h @@ -42,6 +42,9 @@ struct __less { } }; +template +inline const bool __desugars_to_v<__less_tag, __less<>, _Tp, _Tp> = true; + template inline const bool __desugars_to_v<__totally_ordered_less_tag, __less<>, _Tp, _Tp> = is_integral<_Tp>::value; diff --git a/libcxx/include/__algorithm/ranges_minmax.h b/libcxx/include/__algorithm/ranges_minmax.h index 4f2b2bf26382da..5f2e5cb2a1eeab 100644 --- a/libcxx/include/__algorithm/ranges_minmax.h +++ b/libcxx/include/__algorithm/ranges_minmax.h @@ -89,7 +89,7 @@ struct __minmax { // vectorize the code. if constexpr (contiguous_range<_Range> && is_integral_v<_ValueT> && __is_cheap_to_copy<_ValueT> & __is_identity<_Proj>::value && - __desugars_to_v<__totally_ordered_less_tag, _Comp, _ValueT, _ValueT>) { + __desugars_to_v<__less_tag, _Comp, _ValueT, _ValueT>) { minmax_result<_ValueT> __result = {__r[0], __r[0]}; for (auto __e : __r) { if (__e < __result.min) diff --git a/libcxx/include/__algorithm/sort.h b/libcxx/include/__algorithm/sort.h index 0b2137dee2f77e..39868b8b6a30ae 100644 --- a/libcxx/include/__algorithm/sort.h +++ b/libcxx/include/__algorithm/sort.h @@ -27,11 +27,13 @@ #include <__functional/ranges_operations.h> #include <__iterator/iterator_traits.h> #include <__type_traits/conditional.h> +#include <__type_traits/desugars_to.h> #include <__type_traits/disjunction.h> #include <__type_traits/enable_if.h> #include <__type_traits/is_arithmetic.h> #include <__type_traits/is_constant_evaluated.h> #include <__type_traits/is_same.h> +#include <__type_traits/is_trivially_copyable.h> #include <__type_traits/remove_cvref.h> #include <__utility/move.h> #include <__utility/pair.h> @@ -47,110 +49,11 @@ _LIBCPP_PUSH_MACROS _LIBCPP_BEGIN_NAMESPACE_STD -// stable, 2-3 compares, 0-2 swaps - -template -_LIBCPP_HIDE_FROM_ABI _LIBCPP_CONSTEXPR_SINCE_CXX14 unsigned -__sort3(_ForwardIterator __x, _ForwardIterator __y, _ForwardIterator __z, _Compare __c) { - using _Ops = _IterOps<_AlgPolicy>; - - unsigned __r = 0; - if (!__c(*__y, *__x)) // if x <= y - { - if (!__c(*__z, *__y)) // if y <= z - return __r; // x <= y && y <= z - // x <= y && y > z - _Ops::iter_swap(__y, __z); // x <= z && y < z - __r = 1; - if (__c(*__y, *__x)) // if x > y - { - _Ops::iter_swap(__x, __y); // x < y && y <= z - __r = 2; - } - return __r; // x <= y && y < z - } - if (__c(*__z, *__y)) // x > y, if y > z - { - _Ops::iter_swap(__x, __z); // x < y && y < z - __r = 1; - return __r; - } - _Ops::iter_swap(__x, __y); // x > y && y <= z - __r = 1; // x < y && x <= z - if (__c(*__z, *__y)) // if y > z - { - _Ops::iter_swap(__y, __z); // x <= y && y < z - __r = 2; - } - return __r; -} // x <= y && y <= z - -// stable, 3-6 compares, 0-5 swaps - -template -_LIBCPP_HIDE_FROM_ABI void -__sort4(_ForwardIterator __x1, _ForwardIterator __x2, _ForwardIterator __x3, _ForwardIterator __x4, _Compare __c) { - using _Ops = _IterOps<_AlgPolicy>; - std::__sort3<_AlgPolicy, _Compare>(__x1, __x2, __x3, __c); - if (__c(*__x4, *__x3)) { - _Ops::iter_swap(__x3, __x4); - if (__c(*__x3, *__x2)) { - _Ops::iter_swap(__x2, __x3); - if (__c(*__x2, *__x1)) { - _Ops::iter_swap(__x1, __x2); - } - } - } -} - -// stable, 4-10 compares, 0-9 swaps - -template -_LIBCPP_HIDE_FROM_ABI void -__sort5(_ForwardIterator __x1, - _ForwardIterator __x2, - _ForwardIterator __x3, - _ForwardIterator __x4, - _ForwardIterator __x5, - _Comp __comp) { - using _Ops = _IterOps<_AlgPolicy>; - - std::__sort4<_AlgPolicy, _Comp>(__x1, __x2, __x3, __x4, __comp); - if (__comp(*__x5, *__x4)) { - _Ops::iter_swap(__x4, __x5); - if (__comp(*__x4, *__x3)) { - _Ops::iter_swap(__x3, __x4); - if (__comp(*__x3, *__x2)) { - _Ops::iter_swap(__x2, __x3); - if (__comp(*__x2, *__x1)) { - _Ops::iter_swap(__x1, __x2); - } - } - } - } -} - -// The comparator being simple is a prerequisite for using the branchless optimization. -template -struct __is_simple_comparator : false_type {}; -template <> -struct __is_simple_comparator<__less<>&> : true_type {}; -template -struct __is_simple_comparator&> : true_type {}; -template -struct __is_simple_comparator&> : true_type {}; -#if _LIBCPP_STD_VER >= 20 -template <> -struct __is_simple_comparator : true_type {}; -template <> -struct __is_simple_comparator : true_type {}; -#endif - template ::value_type> -using __use_branchless_sort = - integral_constant::value && sizeof(_Tp) <= sizeof(void*) && - is_arithmetic<_Tp>::value && __is_simple_comparator<_Compare>::value>; +inline const bool __use_branchless_sort = + __libcpp_is_contiguous_iterator<_Iter>::value && __is_cheap_to_copy<_Tp> && is_arithmetic<_Tp>::value && + (__desugars_to_v<__less_tag, __remove_cvref_t<_Compare>, _Tp, _Tp> || + __desugars_to_v<__greater_tag, __remove_cvref_t<_Compare>, _Tp, _Tp>); namespace __detail { @@ -161,59 +64,88 @@ enum { __block_size = sizeof(uint64_t) * 8 }; // Ensures that __c(*__x, *__y) is true by swapping *__x and *__y if necessary. template -inline _LIBCPP_HIDE_FROM_ABI void __cond_swap(_RandomAccessIterator __x, _RandomAccessIterator __y, _Compare __c) { +inline _LIBCPP_HIDE_FROM_ABI _LIBCPP_CONSTEXPR_SINCE_CXX14 bool +__cond_swap(_RandomAccessIterator __x, _RandomAccessIterator __y, _Compare __c) { // Note: this function behaves correctly even with proxy iterators (because it relies on `value_type`). using value_type = typename iterator_traits<_RandomAccessIterator>::value_type; bool __r = __c(*__x, *__y); value_type __tmp = __r ? *__x : *__y; *__y = __r ? *__y : *__x; *__x = __tmp; + return !__r; } // Ensures that *__x, *__y and *__z are ordered according to the comparator __c, // under the assumption that *__y and *__z are already ordered. template -inline _LIBCPP_HIDE_FROM_ABI void +inline _LIBCPP_HIDE_FROM_ABI _LIBCPP_CONSTEXPR_SINCE_CXX14 bool __partially_sorted_swap(_RandomAccessIterator __x, _RandomAccessIterator __y, _RandomAccessIterator __z, _Compare __c) { // Note: this function behaves correctly even with proxy iterators (because it relies on `value_type`). using value_type = typename iterator_traits<_RandomAccessIterator>::value_type; - bool __r = __c(*__z, *__x); - value_type __tmp = __r ? *__z : *__x; - *__z = __r ? *__x : *__z; - __r = __c(__tmp, *__y); - *__x = __r ? *__x : *__y; - *__y = __r ? *__y : __tmp; + bool __r1 = __c(*__z, *__x); + value_type __tmp = __r1 ? *__z : *__x; + *__z = __r1 ? *__x : *__z; + bool __r2 = __c(__tmp, *__y); + *__x = __r2 ? *__x : *__y; + *__y = __r2 ? *__y : __tmp; + return !__r1 || !__r2; } +// stable, 2-3 compares, 0-2 swaps + template ::value, int> = 0> -inline _LIBCPP_HIDE_FROM_ABI void __sort3_maybe_branchless( - _RandomAccessIterator __x1, _RandomAccessIterator __x2, _RandomAccessIterator __x3, _Compare __c) { - std::__cond_swap<_Compare>(__x2, __x3, __c); - std::__partially_sorted_swap<_Compare>(__x1, __x2, __x3, __c); + __enable_if_t<__use_branchless_sort<_Compare, _RandomAccessIterator>, int> = 0> +inline _LIBCPP_HIDE_FROM_ABI _LIBCPP_CONSTEXPR_SINCE_CXX14 bool +__sort3(_RandomAccessIterator __x1, _RandomAccessIterator __x2, _RandomAccessIterator __x3, _Compare __c) { + bool __swapped1 = std::__cond_swap<_Compare>(__x2, __x3, __c); + bool __swapped2 = std::__partially_sorted_swap<_Compare>(__x1, __x2, __x3, __c); + return __swapped1 || __swapped2; } template ::value, int> = 0> -inline _LIBCPP_HIDE_FROM_ABI void __sort3_maybe_branchless( - _RandomAccessIterator __x1, _RandomAccessIterator __x2, _RandomAccessIterator __x3, _Compare __c) { - std::__sort3<_AlgPolicy, _Compare>(__x1, __x2, __x3, __c); -} + __enable_if_t, int> = 0> +inline _LIBCPP_HIDE_FROM_ABI _LIBCPP_CONSTEXPR_SINCE_CXX14 bool +__sort3(_RandomAccessIterator __x, _RandomAccessIterator __y, _RandomAccessIterator __z, _Compare __c) { + using _Ops = _IterOps<_AlgPolicy>; + + if (!__c(*__y, *__x)) // if x <= y + { + if (!__c(*__z, *__y)) // if y <= z + return false; // x <= y && y <= z + // x <= y && y > z + _Ops::iter_swap(__y, __z); // x <= z && y < z + if (__c(*__y, *__x)) // if x > y + _Ops::iter_swap(__x, __y); // x < y && y <= z + return true; // x <= y && y < z + } + if (__c(*__z, *__y)) // x > y, if y > z + { + _Ops::iter_swap(__x, __z); // x < y && y < z + return true; + } + _Ops::iter_swap(__x, __y); // x > y && y <= z + // x < y && x <= z + if (__c(*__z, *__y)) // if y > z + _Ops::iter_swap(__y, __z); // x <= y && y < z + return true; +} // x <= y && y <= z + +// stable, 3-6 compares, 0-5 swaps template ::value, int> = 0> -inline _LIBCPP_HIDE_FROM_ABI void __sort4_maybe_branchless( - _RandomAccessIterator __x1, - _RandomAccessIterator __x2, - _RandomAccessIterator __x3, - _RandomAccessIterator __x4, - _Compare __c) { + __enable_if_t<__use_branchless_sort<_Compare, _RandomAccessIterator>, int> = 0> +inline _LIBCPP_HIDE_FROM_ABI void +__sort4(_RandomAccessIterator __x1, + _RandomAccessIterator __x2, + _RandomAccessIterator __x3, + _RandomAccessIterator __x4, + _Compare __c) { std::__cond_swap<_Compare>(__x1, __x3, __c); std::__cond_swap<_Compare>(__x2, __x4, __c); std::__cond_swap<_Compare>(__x1, __x2, __c); @@ -224,27 +156,39 @@ inline _LIBCPP_HIDE_FROM_ABI void __sort4_maybe_branchless( template ::value, int> = 0> -inline _LIBCPP_HIDE_FROM_ABI void __sort4_maybe_branchless( - _RandomAccessIterator __x1, - _RandomAccessIterator __x2, - _RandomAccessIterator __x3, - _RandomAccessIterator __x4, - _Compare __c) { - std::__sort4<_AlgPolicy, _Compare>(__x1, __x2, __x3, __x4, __c); + __enable_if_t, int> = 0> +inline _LIBCPP_HIDE_FROM_ABI void +__sort4(_RandomAccessIterator __x1, + _RandomAccessIterator __x2, + _RandomAccessIterator __x3, + _RandomAccessIterator __x4, + _Compare __c) { + using _Ops = _IterOps<_AlgPolicy>; + std::__sort3<_AlgPolicy, _Compare>(__x1, __x2, __x3, __c); + if (__c(*__x4, *__x3)) { + _Ops::iter_swap(__x3, __x4); + if (__c(*__x3, *__x2)) { + _Ops::iter_swap(__x2, __x3); + if (__c(*__x2, *__x1)) { + _Ops::iter_swap(__x1, __x2); + } + } + } } +// stable, 4-10 compares, 0-9 swaps + template ::value, int> = 0> -inline _LIBCPP_HIDE_FROM_ABI void __sort5_maybe_branchless( - _RandomAccessIterator __x1, - _RandomAccessIterator __x2, - _RandomAccessIterator __x3, - _RandomAccessIterator __x4, - _RandomAccessIterator __x5, - _Compare __c) { + __enable_if_t<__use_branchless_sort<_Compare, _RandomAccessIterator>, int> = 0> +inline _LIBCPP_HIDE_FROM_ABI void +__sort5(_RandomAccessIterator __x1, + _RandomAccessIterator __x2, + _RandomAccessIterator __x3, + _RandomAccessIterator __x4, + _RandomAccessIterator __x5, + _Compare __c) { std::__cond_swap<_Compare>(__x1, __x2, __c); std::__cond_swap<_Compare>(__x4, __x5, __c); std::__partially_sorted_swap<_Compare>(__x3, __x4, __x5, __c); @@ -256,16 +200,29 @@ inline _LIBCPP_HIDE_FROM_ABI void __sort5_maybe_branchless( template ::value, int> = 0> -inline _LIBCPP_HIDE_FROM_ABI void __sort5_maybe_branchless( - _RandomAccessIterator __x1, - _RandomAccessIterator __x2, - _RandomAccessIterator __x3, - _RandomAccessIterator __x4, - _RandomAccessIterator __x5, - _Compare __c) { - std::__sort5<_AlgPolicy, _Compare, _RandomAccessIterator>( - std::move(__x1), std::move(__x2), std::move(__x3), std::move(__x4), std::move(__x5), __c); + __enable_if_t, int> = 0> +inline _LIBCPP_HIDE_FROM_ABI void +__sort5(_RandomAccessIterator __x1, + _RandomAccessIterator __x2, + _RandomAccessIterator __x3, + _RandomAccessIterator __x4, + _RandomAccessIterator __x5, + _Compare __comp) { + using _Ops = _IterOps<_AlgPolicy>; + + std::__sort4<_AlgPolicy, _Compare>(__x1, __x2, __x3, __x4, __comp); + if (__comp(*__x5, *__x4)) { + _Ops::iter_swap(__x4, __x5); + if (__comp(*__x4, *__x3)) { + _Ops::iter_swap(__x3, __x4); + if (__comp(*__x3, *__x2)) { + _Ops::iter_swap(__x2, __x3); + if (__comp(*__x2, *__x1)) { + _Ops::iter_swap(__x1, __x2); + } + } + } + } } // Assumes size > 0 @@ -355,14 +312,14 @@ __insertion_sort_incomplete(_RandomAccessIterator __first, _RandomAccessIterator _Ops::iter_swap(__first, __last); return true; case 3: - std::__sort3_maybe_branchless<_AlgPolicy, _Comp>(__first, __first + difference_type(1), --__last, __comp); + std::__sort3<_AlgPolicy, _Comp>(__first, __first + difference_type(1), --__last, __comp); return true; case 4: - std::__sort4_maybe_branchless<_AlgPolicy, _Comp>( + std::__sort4<_AlgPolicy, _Comp>( __first, __first + difference_type(1), __first + difference_type(2), --__last, __comp); return true; case 5: - std::__sort5_maybe_branchless<_AlgPolicy, _Comp>( + std::__sort5<_AlgPolicy, _Comp>( __first, __first + difference_type(1), __first + difference_type(2), @@ -373,7 +330,7 @@ __insertion_sort_incomplete(_RandomAccessIterator __first, _RandomAccessIterator } typedef typename iterator_traits<_RandomAccessIterator>::value_type value_type; _RandomAccessIterator __j = __first + difference_type(2); - std::__sort3_maybe_branchless<_AlgPolicy, _Comp>(__first, __first + difference_type(1), __j, __comp); + std::__sort3<_AlgPolicy, _Comp>(__first, __first + difference_type(1), __j, __comp); const unsigned __limit = 8; unsigned __count = 0; for (_RandomAccessIterator __i = __j + difference_type(1); __i != __last; ++__i) { @@ -780,14 +737,14 @@ void __introsort(_RandomAccessIterator __first, _Ops::iter_swap(__first, __last); return; case 3: - std::__sort3_maybe_branchless<_AlgPolicy, _Compare>(__first, __first + difference_type(1), --__last, __comp); + std::__sort3<_AlgPolicy, _Compare>(__first, __first + difference_type(1), --__last, __comp); return; case 4: - std::__sort4_maybe_branchless<_AlgPolicy, _Compare>( + std::__sort4<_AlgPolicy, _Compare>( __first, __first + difference_type(1), __first + difference_type(2), --__last, __comp); return; case 5: - std::__sort5_maybe_branchless<_AlgPolicy, _Compare>( + std::__sort5<_AlgPolicy, _Compare>( __first, __first + difference_type(1), __first + difference_type(2), @@ -928,10 +885,8 @@ __sort_dispatch(_RandomAccessIterator __first, _RandomAccessIterator __last, _Co // Only use bitset partitioning for arithmetic types. We should also check // that the default comparator is in use so that we are sure that there are no // branches in the comparator. - std::__introsort<_AlgPolicy, - _Comp&, - _RandomAccessIterator, - __use_branchless_sort<_Comp, _RandomAccessIterator>::value>(__first, __last, __comp, __depth_limit); + std::__introsort<_AlgPolicy, _Comp&, _RandomAccessIterator, __use_branchless_sort<_Comp, _RandomAccessIterator> >( + __first, __last, __comp, __depth_limit); } template diff --git a/libcxx/include/__config b/libcxx/include/__config index fc09a97274d7c7..1cf80a46686ab9 100644 --- a/libcxx/include/__config +++ b/libcxx/include/__config @@ -39,16 +39,9 @@ // HARDENING { -// This is for backward compatibility -- make enabling `_LIBCPP_ENABLE_ASSERTIONS` (which predates hardening modes) -// equivalent to setting the extensive mode. This is deprecated and will be removed in LLVM 20. +// TODO: Remove in LLVM 21. We're making this an error to catch folks who might not have migrated. # ifdef _LIBCPP_ENABLE_ASSERTIONS -# warning "_LIBCPP_ENABLE_ASSERTIONS is deprecated, please use _LIBCPP_HARDENING_MODE instead" -# if _LIBCPP_ENABLE_ASSERTIONS != 0 && _LIBCPP_ENABLE_ASSERTIONS != 1 -# error "_LIBCPP_ENABLE_ASSERTIONS must be set to 0 or 1" -# endif -# if _LIBCPP_ENABLE_ASSERTIONS -# define _LIBCPP_HARDENING_MODE _LIBCPP_HARDENING_MODE_EXTENSIVE -# endif +# error "_LIBCPP_ENABLE_ASSERTIONS has been removed, please use _LIBCPP_HARDENING_MODE instead" # endif // The library provides the macro `_LIBCPP_HARDENING_MODE` which can be set to one of the following values: diff --git a/libcxx/include/__functional/operations.h b/libcxx/include/__functional/operations.h index 6022bd679ed3e3..67d9da289aead3 100644 --- a/libcxx/include/__functional/operations.h +++ b/libcxx/include/__functional/operations.h @@ -362,6 +362,9 @@ struct _LIBCPP_TEMPLATE_VIS less : __binary_function<_Tp, _Tp, bool> { }; _LIBCPP_CTAD_SUPPORTED_FOR_TYPE(less); +template +inline const bool __desugars_to_v<__less_tag, less<_Tp>, _Tp, _Tp> = true; + template inline const bool __desugars_to_v<__totally_ordered_less_tag, less<_Tp>, _Tp, _Tp> = is_integral<_Tp>::value; @@ -377,6 +380,9 @@ struct _LIBCPP_TEMPLATE_VIS less { typedef void is_transparent; }; +template +inline const bool __desugars_to_v<__less_tag, less<>, _Tp, _Up> = true; + template inline const bool __desugars_to_v<__totally_ordered_less_tag, less<>, _Tp, _Tp> = is_integral<_Tp>::value; #endif @@ -446,6 +452,9 @@ struct _LIBCPP_TEMPLATE_VIS greater : __binary_function<_Tp, _Tp, bool> { }; _LIBCPP_CTAD_SUPPORTED_FOR_TYPE(greater); +template +inline const bool __desugars_to_v<__greater_tag, greater<_Tp>, _Tp, _Tp> = true; + #if _LIBCPP_STD_VER >= 14 template <> struct _LIBCPP_TEMPLATE_VIS greater { @@ -457,6 +466,9 @@ struct _LIBCPP_TEMPLATE_VIS greater { } typedef void is_transparent; }; + +template +inline const bool __desugars_to_v<__greater_tag, greater<>, _Tp, _Up> = true; #endif // Logical operations diff --git a/libcxx/include/__functional/ranges_operations.h b/libcxx/include/__functional/ranges_operations.h index f023d765a6c8ab..df95843e7c9af6 100644 --- a/libcxx/include/__functional/ranges_operations.h +++ b/libcxx/include/__functional/ranges_operations.h @@ -102,6 +102,12 @@ inline const bool __desugars_to_v<__equal_tag, ranges::equal_to, _Tp, _Up> = tru template inline const bool __desugars_to_v<__totally_ordered_less_tag, ranges::less, _Tp, _Up> = true; +template +inline const bool __desugars_to_v<__less_tag, ranges::less, _Tp, _Up> = true; + +template +inline const bool __desugars_to_v<__greater_tag, ranges::greater, _Tp, _Up> = true; + #endif // _LIBCPP_STD_VER >= 20 _LIBCPP_END_NAMESPACE_STD diff --git a/libcxx/include/__type_traits/desugars_to.h b/libcxx/include/__type_traits/desugars_to.h index b0ce7c414e5d77..452c70bfbad66d 100644 --- a/libcxx/include/__type_traits/desugars_to.h +++ b/libcxx/include/__type_traits/desugars_to.h @@ -25,6 +25,12 @@ struct __equal_tag {}; // syntactically, the operation is equivalent to calling `a + b` struct __plus_tag {}; +// syntactically, the operation is equivalent to calling `a < b` +struct __less_tag {}; + +// syntactically, the operation is equivalent to calling `a > b` +struct __greater_tag {}; + // syntactically, the operation is equivalent to calling `a < b`, and these expressions // have to be true for any `a` and `b`: // - `(a < b) == (b > a)` diff --git a/libcxx/include/__type_traits/is_trivially_copyable.h b/libcxx/include/__type_traits/is_trivially_copyable.h index e92af126ee94d9..8eb3ba7581af15 100644 --- a/libcxx/include/__type_traits/is_trivially_copyable.h +++ b/libcxx/include/__type_traits/is_trivially_copyable.h @@ -27,10 +27,8 @@ template inline constexpr bool is_trivially_copyable_v = __is_trivially_copyable(_Tp); #endif -#if _LIBCPP_STD_VER >= 20 template -inline constexpr bool __is_cheap_to_copy = is_trivially_copyable_v<_Tp> && sizeof(_Tp) <= sizeof(std::intmax_t); -#endif +inline const bool __is_cheap_to_copy = __is_trivially_copyable(_Tp) && sizeof(_Tp) <= sizeof(std::intmax_t); _LIBCPP_END_NAMESPACE_STD diff --git a/libcxx/include/ccomplex b/libcxx/include/ccomplex index 94d2c8d7d003d4..d379c9e7f0174a 100644 --- a/libcxx/include/ccomplex +++ b/libcxx/include/ccomplex @@ -23,4 +23,16 @@ # pragma GCC system_header #endif +#if _LIBCPP_STD_VER >= 20 + +using __standard_header_ccomplex _LIBCPP_DEPRECATED_("removed in C++20. Include instead.") = void; +using __use_standard_header_ccomplex = __standard_header_ccomplex; + +#elif _LIBCPP_STD_VER >= 17 + +using __standard_header_ccomplex _LIBCPP_DEPRECATED_("Include instead.") = void; +using __use_standard_header_ccomplex = __standard_header_ccomplex; + +#endif + #endif // _LIBCPP_CCOMPLEX diff --git a/libcxx/include/ciso646 b/libcxx/include/ciso646 index 1d859f08fac572..5fcac79e38a7f2 100644 --- a/libcxx/include/ciso646 +++ b/libcxx/include/ciso646 @@ -21,4 +21,11 @@ # pragma GCC system_header #endif +#if _LIBCPP_STD_VER >= 20 + +using __standard_header_ciso646 _LIBCPP_DEPRECATED_("removed in C++20. Include instead.") = void; +using __use_standard_header_ciso646 = __standard_header_ciso646; + +#endif + #endif // _LIBCPP_CISO646 diff --git a/libcxx/include/complex b/libcxx/include/complex index 4030d96b003d56..15e42800fbfa0a 100644 --- a/libcxx/include/complex +++ b/libcxx/include/complex @@ -1097,20 +1097,20 @@ inline _LIBCPP_HIDE_FROM_ABI complex<_Tp> pow(const complex<_Tp>& __x, const com return std::exp(__y * std::log(__x)); } -template +template ::value && is_floating_point<_Up>::value, int> = 0> inline _LIBCPP_HIDE_FROM_ABI complex::type> pow(const complex<_Tp>& __x, const complex<_Up>& __y) { typedef complex::type> result_type; return std::pow(result_type(__x), result_type(__y)); } -template ::value, int> = 0> +template ::value && is_arithmetic<_Up>::value, int> = 0> inline _LIBCPP_HIDE_FROM_ABI complex::type> pow(const complex<_Tp>& __x, const _Up& __y) { typedef complex::type> result_type; return std::pow(result_type(__x), result_type(__y)); } -template ::value, int> = 0> +template ::value && is_floating_point<_Up>::value, int> = 0> inline _LIBCPP_HIDE_FROM_ABI complex::type> pow(const _Tp& __x, const complex<_Up>& __y) { typedef complex::type> result_type; return std::pow(result_type(__x), result_type(__y)); diff --git a/libcxx/include/complex.h b/libcxx/include/complex.h index a3da21c843f365..89595ae2068a64 100644 --- a/libcxx/include/complex.h +++ b/libcxx/include/complex.h @@ -24,7 +24,7 @@ #endif #ifdef __cplusplus -# include +# include #elif __has_include_next() # include_next #endif diff --git a/libcxx/include/cstdalign b/libcxx/include/cstdalign new file mode 100644 index 00000000000000..e6a2a3c7177422 --- /dev/null +++ b/libcxx/include/cstdalign @@ -0,0 +1,55 @@ +// -*- C++ -*- +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +#ifndef _LIBCPP_CSTDALIGN +#define _LIBCPP_CSTDALIGN + +/* + cstdalign synopsis + +Macros: + + __alignas_is_defined + __alignof_is_defined + +*/ + +#include <__config> + +// is not provided by libc++ +#if __has_include() +# include +# ifdef _LIBCPP_STDALIGN_H +# error "If libc++ starts defining , the __has_include check should move to libc++'s " +# endif +#endif + +#if !defined(_LIBCPP_HAS_NO_PRAGMA_SYSTEM_HEADER) +# pragma GCC system_header +#endif + +#undef __alignas_is_defined +#define __alignas_is_defined 1 + +#undef __alignof_is_defined +#define __alignof_is_defined 1 + +#if _LIBCPP_STD_VER >= 20 + +using __standard_header_cstdalign _LIBCPP_DEPRECATED_("removed in C++20.") = void; +using __use_standard_header_cstdalign = __standard_header_cstdalign; + +#elif _LIBCPP_STD_VER >= 17 + +using __standard_header_cstdalign _LIBCPP_DEPRECATED = void; +using __use_standard_header_cstdalign = __standard_header_cstdalign; + +#endif + +#endif // _LIBCPP_CSTDALIGN diff --git a/libcxx/include/cstdbool b/libcxx/include/cstdbool index ef731c021a4ab8..1d627258e10c09 100644 --- a/libcxx/include/cstdbool +++ b/libcxx/include/cstdbool @@ -28,4 +28,16 @@ Macros: #undef __bool_true_false_are_defined #define __bool_true_false_are_defined 1 +#if _LIBCPP_STD_VER >= 20 + +using __standard_header_cstdbool _LIBCPP_DEPRECATED_("removed in C++20.") = void; +using __use_standard_header_cstdbool = __standard_header_cstdbool; + +#elif _LIBCPP_STD_VER >= 17 + +using __standard_header_cstdbool _LIBCPP_DEPRECATED = void; +using __use_standard_header_cstdbool = __standard_header_cstdbool; + +#endif + #endif // _LIBCPP_CSTDBOOL diff --git a/libcxx/include/ctgmath b/libcxx/include/ctgmath index 6237979be4906c..7dbe952f021b74 100644 --- a/libcxx/include/ctgmath +++ b/libcxx/include/ctgmath @@ -18,11 +18,23 @@ */ -#include #include +#include #if !defined(_LIBCPP_HAS_NO_PRAGMA_SYSTEM_HEADER) # pragma GCC system_header #endif +#if _LIBCPP_STD_VER >= 20 + +using __standard_header_ctgmath _LIBCPP_DEPRECATED_("removed in C++20. Include and instead.") = void; +using __use_standard_header_ctgmath = __standard_header_ctgmath; + +#elif _LIBCPP_STD_VER >= 17 + +using __standard_header_ctgmath _LIBCPP_DEPRECATED_("Include and instead.") = void; +using __use_standard_header_ctgmath = __standard_header_ctgmath; + +#endif + #endif // _LIBCPP_CTGMATH diff --git a/libcxx/include/module.modulemap b/libcxx/include/module.modulemap index c3561590e06d8a..af8c3c15eb2767 100644 --- a/libcxx/include/module.modulemap +++ b/libcxx/include/module.modulemap @@ -1109,6 +1109,11 @@ module std [system] { export * } + module cstdalign { + header "cstdalign" + export * + } + module cstdarg { header "cstdarg" export * @@ -1229,7 +1234,7 @@ module std [system] { header "flat_map" export * } - + module format { module buffer { header "__format/buffer.h" } module concepts { header "__format/concepts.h" } diff --git a/libcxx/include/tgmath.h b/libcxx/include/tgmath.h index e6f0a4ab2611fa..1c5058cb065a91 100644 --- a/libcxx/include/tgmath.h +++ b/libcxx/include/tgmath.h @@ -24,7 +24,8 @@ #endif #ifdef __cplusplus -# include +# include +# include #else # if __has_include_next() # include_next diff --git a/libcxx/src/algorithm.cpp b/libcxx/src/algorithm.cpp index af9d60a8e271e8..a7c39b5e5183a4 100644 --- a/libcxx/src/algorithm.cpp +++ b/libcxx/src/algorithm.cpp @@ -21,8 +21,7 @@ void __sort(RandomAccessIterator first, RandomAccessIterator last, Comp comp) { std::__introsort<_ClassicAlgPolicy, ranges::less, RandomAccessIterator, - __use_branchless_sort::value>( - first, last, ranges::less{}, depth_limit); + __use_branchless_sort>(first, last, ranges::less{}, depth_limit); } // clang-format off diff --git a/libcxx/test/libcxx/assertions/modes/enabling_assertions_enables_extensive_mode.pass.cpp b/libcxx/test/libcxx/assertions/modes/enabling_assertions_enables_extensive_mode.pass.cpp deleted file mode 100644 index c496fc32dc939f..00000000000000 --- a/libcxx/test/libcxx/assertions/modes/enabling_assertions_enables_extensive_mode.pass.cpp +++ /dev/null @@ -1,35 +0,0 @@ -//===----------------------------------------------------------------------===// -// -// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. -// See https://llvm.org/LICENSE.txt for license information. -// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception -// -//===----------------------------------------------------------------------===// - -// TODO(hardening): remove in LLVM 20. -// This test ensures that enabling assertions with the legacy `_LIBCPP_ENABLE_ASSERTIONS` now enables the extensive -// hardening mode. - -// `check_assertion.h` is only available starting from C++11 and requires Unix headers and regex support. -// REQUIRES: has-unix-headers -// UNSUPPORTED: c++03, no-localization -// The ability to set a custom abort message is required to compare the assertion message (which only happens in the -// debug mode). -// XFAIL: libcpp-hardening-mode=debug && availability-verbose_abort-missing -// HWASAN replaces TRAP with abort or error exit code. -// XFAIL: hwasan -// Note that GCC doesn't support `-Wno-macro-redefined`. -// ADDITIONAL_COMPILE_FLAGS: -U_LIBCPP_HARDENING_MODE -D_LIBCPP_ENABLE_ASSERTIONS=1 -Wno-#warnings -Wno-cpp - -#include -#include "check_assertion.h" - -int main(int, char**) { - static_assert(_LIBCPP_HARDENING_MODE == _LIBCPP_HARDENING_MODE_EXTENSIVE, - "The extensive hardening mode should be implicitly enabled"); - - _LIBCPP_ASSERT_VALID_ELEMENT_ACCESS(true, "Should not fire"); - TEST_LIBCPP_ASSERT_FAILURE([] { _LIBCPP_ASSERT_VALID_ELEMENT_ACCESS(false, "Should fire"); }(), "Should fire"); - - return 0; -} diff --git a/libcxx/test/libcxx/clang_modules_include.gen.py b/libcxx/test/libcxx/clang_modules_include.gen.py index bc028f2a0809aa..b897984f898819 100644 --- a/libcxx/test/libcxx/clang_modules_include.gen.py +++ b/libcxx/test/libcxx/clang_modules_include.gen.py @@ -17,10 +17,15 @@ import sys sys.path.append(sys.argv[1]) -from libcxx.header_information import lit_header_restrictions, public_headers +from libcxx.header_information import ( + lit_header_restrictions, + lit_header_undeprecations, + public_headers, +) for header in public_headers: - print(f"""\ + print( + f"""\ //--- {header}.compile.pass.cpp // RUN: %{{cxx}} %s %{{flags}} %{{compile_flags}} -fmodules -fcxx-modules -fmodules-cache-path=%t -fsyntax-only @@ -41,9 +46,11 @@ // UNSUPPORTED: LIBCXX-PICOLIBC-FIXME {lit_header_restrictions.get(header, '')} +{lit_header_undeprecations.get(header, '')} #include <{header}> -""") +""" + ) print( f"""\ diff --git a/libcxx/test/libcxx/double_include.gen.py b/libcxx/test/libcxx/double_include.gen.py index afc2947dbece94..f58e72f94a3533 100644 --- a/libcxx/test/libcxx/double_include.gen.py +++ b/libcxx/test/libcxx/double_include.gen.py @@ -15,12 +15,18 @@ import sys sys.path.append(sys.argv[1]) -from libcxx.header_information import lit_header_restrictions, public_headers +from libcxx.header_information import ( + lit_header_restrictions, + lit_header_undeprecations, + public_headers, +) for header in public_headers: - print(f"""\ + print( + f"""\ //--- {header}.sh.cpp {lit_header_restrictions.get(header, '')} +{lit_header_undeprecations.get(header, '')} // RUN: %{{cxx}} -c %s -o %t.first.o %{{flags}} %{{compile_flags}} // RUN: %{{cxx}} -c %s -o %t.second.o -DWITH_MAIN %{{flags}} %{{compile_flags}} @@ -32,4 +38,5 @@ #if defined(WITH_MAIN) int main(int, char**) {{ return 0; }} #endif -""") +""" + ) diff --git a/libcxx/test/libcxx/header_inclusions.gen.py b/libcxx/test/libcxx/header_inclusions.gen.py index e5def1ad4cb70d..739caf915c09a0 100644 --- a/libcxx/test/libcxx/header_inclusions.gen.py +++ b/libcxx/test/libcxx/header_inclusions.gen.py @@ -12,32 +12,43 @@ # RUN: %{python} %s %{libcxx-dir}/utils import sys + sys.path.append(sys.argv[1]) -from libcxx.header_information import lit_header_restrictions, public_headers, mandatory_inclusions +from libcxx.header_information import ( + lit_header_restrictions, + lit_header_undeprecations, + public_headers, + mandatory_inclusions, +) for header in public_headers: - header_guard = lambda h: f"_LIBCPP_{str(h).upper().replace('.', '_').replace('/', '_')}" + header_guard = ( + lambda h: f"_LIBCPP_{str(h).upper().replace('.', '_').replace('/', '_')}" + ) - # has no header guards - if header == 'cassert': - checks = '' - else: - checks = f''' + # has no header guards + if header == "cassert": + checks = "" + else: + checks = f""" #ifndef {header_guard(header)} # error <{header}> was expected to define a header guard {header_guard(header)} #endif -''' - for includee in mandatory_inclusions.get(header, []): - checks += f''' +""" + for includee in mandatory_inclusions.get(header, []): + checks += f""" #ifndef {header_guard(includee)} # error <{header}> was expected to include <{includee}> #endif -''' +""" - print(f"""\ + print( + f"""\ //--- {header}.compile.pass.cpp {lit_header_restrictions.get(header, '')} +{lit_header_undeprecations.get(header, '')} #include <{header}> {checks} -""") +""" + ) diff --git a/libcxx/test/libcxx/include_as_c.sh.cpp b/libcxx/test/libcxx/include_as_c.sh.cpp index c9f8dfd9a5a922..204b830462cf94 100644 --- a/libcxx/test/libcxx/include_as_c.sh.cpp +++ b/libcxx/test/libcxx/include_as_c.sh.cpp @@ -34,6 +34,7 @@ #endif #include #include +#include #include #include #include diff --git a/libcxx/test/libcxx/libcpp_version.gen.py b/libcxx/test/libcxx/libcpp_version.gen.py index a9995295e21e4f..b30623fe2c388b 100644 --- a/libcxx/test/libcxx/libcpp_version.gen.py +++ b/libcxx/test/libcxx/libcpp_version.gen.py @@ -12,16 +12,23 @@ import sys sys.path.append(sys.argv[1]) -from libcxx.header_information import lit_header_restrictions, public_headers +from libcxx.header_information import ( + lit_header_restrictions, + lit_header_undeprecations, + public_headers, +) for header in public_headers: - print(f"""\ + print( + f"""\ //--- {header}.compile.pass.cpp {lit_header_restrictions.get(header, '')} +{lit_header_undeprecations.get(header, '')} #include <{header}> #ifndef _LIBCPP_VERSION # error <{header}> does not seem to define _LIBCPP_VERSION #endif -""") +""" + ) diff --git a/libcxx/test/libcxx/no_assert_include.gen.py b/libcxx/test/libcxx/no_assert_include.gen.py index 67ab98603ca8fd..e0dbc3d815f31b 100644 --- a/libcxx/test/libcxx/no_assert_include.gen.py +++ b/libcxx/test/libcxx/no_assert_include.gen.py @@ -12,20 +12,28 @@ # RUN: %{python} %s %{libcxx-dir}/utils import sys + sys.path.append(sys.argv[1]) -from libcxx.header_information import lit_header_restrictions, public_headers +from libcxx.header_information import ( + lit_header_restrictions, + lit_header_undeprecations, + public_headers, +) for header in public_headers: - if header == 'cassert': - continue + if header == "cassert": + continue - print(f"""\ + print( + f"""\ //--- {header}.compile.pass.cpp {lit_header_restrictions.get(header, '')} +{lit_header_undeprecations.get(header, '')} #include <{header}> #ifdef assert # error "Do not include cassert or assert.h in standard header files" #endif -""") +""" + ) diff --git a/libcxx/test/libcxx/numerics/complex.number/cmplx.over.pow.pass.cpp b/libcxx/test/libcxx/numerics/complex.number/cmplx.over.pow.pass.cpp new file mode 100644 index 00000000000000..1c790c283e4387 --- /dev/null +++ b/libcxx/test/libcxx/numerics/complex.number/cmplx.over.pow.pass.cpp @@ -0,0 +1,84 @@ +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// + +// template complex<__promote::type> pow(const complex&, const U&); +// template complex<__promote::type> pow(const complex&, const complex&); +// template complex<__promote::type> pow(const T&, const complex&); + +// Test that these additional overloads are free from catching std::complex, +// which is expected by several 3rd party libraries, see https://github.com/llvm/llvm-project/issues/109858. +// +// Note that we reserve the right to break this in the future if we have a reason to, but for the time being, +// make sure we don't break this property unintentionally. +#include +#include +#include +#include + +#include "test_macros.h" + +namespace usr { +struct usr_tag {}; + +template +typename std::enable_if<(std::is_same::value && std::is_floating_point::value) || + (std::is_floating_point::value && std::is_same::value), + int>::type +pow(const T&, const std::complex&) { + return std::is_same::value ? 0 : 1; +} + +template +typename std::enable_if<(std::is_same::value && std::is_floating_point::value) || + (std::is_floating_point::value && std::is_same::value), + int>::type +pow(const std::complex&, const U&) { + return std::is_same::value ? 2 : 3; +} + +template +typename std::enable_if<(std::is_same::value && std::is_floating_point::value) || + (std::is_floating_point::value && std::is_same::value), + int>::type +pow(const std::complex&, const std::complex&) { + return std::is_same::value ? 4 : 5; +} +} // namespace usr + +int main(int, char**) { + using std::pow; + using usr::pow; + + usr::usr_tag tag; + const std::complex ctag; + + assert(pow(tag, std::complex(1.0f)) == 0); + assert(pow(std::complex(1.0f), tag) == 2); + assert(pow(tag, std::complex(1.0)) == 0); + assert(pow(std::complex(1.0), tag) == 2); + assert(pow(tag, std::complex(1.0l)) == 0); + assert(pow(std::complex(1.0l), tag) == 2); + + assert(pow(1.0f, ctag) == 1); + assert(pow(ctag, 1.0f) == 3); + assert(pow(1.0, ctag) == 1); + assert(pow(ctag, 1.0) == 3); + assert(pow(1.0l, ctag) == 1); + assert(pow(ctag, 1.0l) == 3); + + assert(pow(ctag, std::complex(1.0f)) == 4); + assert(pow(std::complex(1.0f), ctag) == 5); + assert(pow(ctag, std::complex(1.0)) == 4); + assert(pow(std::complex(1.0), ctag) == 5); + assert(pow(ctag, std::complex(1.0l)) == 4); + assert(pow(std::complex(1.0l), ctag) == 5); + + return 0; +} diff --git a/libcxx/test/libcxx/system_reserved_names.gen.py b/libcxx/test/libcxx/system_reserved_names.gen.py index e29e7a2cdd6144..f01126249c8817 100644 --- a/libcxx/test/libcxx/system_reserved_names.gen.py +++ b/libcxx/test/libcxx/system_reserved_names.gen.py @@ -13,14 +13,20 @@ # RUN: %{python} %s %{libcxx-dir}/utils import sys + sys.path.append(sys.argv[1]) -from libcxx.header_information import lit_header_restrictions, public_headers +from libcxx.header_information import ( + lit_header_restrictions, + lit_header_undeprecations, + public_headers, +) for header in public_headers: print( f"""\ //--- {header}.compile.pass.cpp {lit_header_restrictions.get(header, '')} +{lit_header_undeprecations.get(header, '')} #define SYSTEM_RESERVED_NAME This name should not be used in libc++ diff --git a/libcxx/test/libcxx/transitive_includes/cxx03.csv b/libcxx/test/libcxx/transitive_includes/cxx03.csv index 2dc84963f0891e..48c501863cb76c 100644 --- a/libcxx/test/libcxx/transitive_includes/cxx03.csv +++ b/libcxx/test/libcxx/transitive_includes/cxx03.csv @@ -458,7 +458,6 @@ ctgmath array ctgmath atomic ctgmath bit ctgmath bitset -ctgmath ccomplex ctgmath cctype ctgmath cerrno ctgmath climits diff --git a/libcxx/test/libcxx/transitive_includes/cxx11.csv b/libcxx/test/libcxx/transitive_includes/cxx11.csv index 2dc84963f0891e..48c501863cb76c 100644 --- a/libcxx/test/libcxx/transitive_includes/cxx11.csv +++ b/libcxx/test/libcxx/transitive_includes/cxx11.csv @@ -458,7 +458,6 @@ ctgmath array ctgmath atomic ctgmath bit ctgmath bitset -ctgmath ccomplex ctgmath cctype ctgmath cerrno ctgmath climits diff --git a/libcxx/test/libcxx/transitive_includes/cxx14.csv b/libcxx/test/libcxx/transitive_includes/cxx14.csv index 27e22975573584..6191c9012c631b 100644 --- a/libcxx/test/libcxx/transitive_includes/cxx14.csv +++ b/libcxx/test/libcxx/transitive_includes/cxx14.csv @@ -467,7 +467,6 @@ ctgmath array ctgmath atomic ctgmath bit ctgmath bitset -ctgmath ccomplex ctgmath cctype ctgmath cerrno ctgmath climits diff --git a/libcxx/test/libcxx/transitive_includes/cxx17.csv b/libcxx/test/libcxx/transitive_includes/cxx17.csv index b17eb1f2347a86..5d46162e3f8996 100644 --- a/libcxx/test/libcxx/transitive_includes/cxx17.csv +++ b/libcxx/test/libcxx/transitive_includes/cxx17.csv @@ -458,7 +458,6 @@ ctgmath array ctgmath atomic ctgmath bit ctgmath bitset -ctgmath ccomplex ctgmath cctype ctgmath cerrno ctgmath climits diff --git a/libcxx/test/libcxx/transitive_includes/cxx20.csv b/libcxx/test/libcxx/transitive_includes/cxx20.csv index 9efec327889c1d..20fe9878ce3eae 100644 --- a/libcxx/test/libcxx/transitive_includes/cxx20.csv +++ b/libcxx/test/libcxx/transitive_includes/cxx20.csv @@ -446,7 +446,6 @@ ctgmath array ctgmath atomic ctgmath bit ctgmath bitset -ctgmath ccomplex ctgmath cctype ctgmath cerrno ctgmath climits diff --git a/libcxx/test/libcxx/transitive_includes/cxx23.csv b/libcxx/test/libcxx/transitive_includes/cxx23.csv index e17f732663a9b2..5ee89ec307cc29 100644 --- a/libcxx/test/libcxx/transitive_includes/cxx23.csv +++ b/libcxx/test/libcxx/transitive_includes/cxx23.csv @@ -238,7 +238,6 @@ coroutine limits coroutine version cstddef version ctgmath bitset -ctgmath ccomplex ctgmath cctype ctgmath cerrno ctgmath climits diff --git a/libcxx/test/libcxx/transitive_includes/cxx26.csv b/libcxx/test/libcxx/transitive_includes/cxx26.csv index c56f5cdfad0072..ee17223e66bee4 100644 --- a/libcxx/test/libcxx/transitive_includes/cxx26.csv +++ b/libcxx/test/libcxx/transitive_includes/cxx26.csv @@ -238,7 +238,6 @@ coroutine limits coroutine version cstddef version ctgmath bitset -ctgmath ccomplex ctgmath cctype ctgmath cerrno ctgmath climits diff --git a/libcxx/test/std/depr/depr.c.headers/ciso646.compile.pass.cpp b/libcxx/test/std/depr/depr.c.headers/ciso646.compile.pass.cpp index 4dff57f84f202c..764f4d02f44f44 100644 --- a/libcxx/test/std/depr/depr.c.headers/ciso646.compile.pass.cpp +++ b/libcxx/test/std/depr/depr.c.headers/ciso646.compile.pass.cpp @@ -6,6 +6,8 @@ // //===----------------------------------------------------------------------===// -// +// // removed in C++20, but still provided by libc++ as an extension + +// ADDITIONAL_COMPILE_FLAGS: -D_LIBCPP_DISABLE_DEPRECATION_WARNINGS #include diff --git a/libcxx/test/std/depr/depr.c.headers/stdalign_h.compile.pass.cpp b/libcxx/test/std/depr/depr.c.headers/stdalign_h.compile.pass.cpp new file mode 100644 index 00000000000000..e7290aab2c6616 --- /dev/null +++ b/libcxx/test/std/depr/depr.c.headers/stdalign_h.compile.pass.cpp @@ -0,0 +1,33 @@ +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// test +// +// Even though is not provided by libc++, +// we still test that using it with libc++ on the search path will work. + +// TODO: GCC doesn't provide a proper for C++ until 15. +// UNSUPPORTED: gcc + +#include + +#ifndef __alignas_is_defined +# error __alignas_is_defined not defined +#endif + +#ifndef __alignof_is_defined +# error __alignof_is_defined not defined +#endif + +#ifdef alignas +# error alignas should not be defined +#endif + +#ifdef alignof +# error alignof should not be defined +#endif diff --git a/libcxx/test/std/depr/depr.cpp.headers/ccomplex.verify.cpp b/libcxx/test/std/depr/depr.cpp.headers/ccomplex.verify.cpp new file mode 100644 index 00000000000000..0eaf82ce5cef01 --- /dev/null +++ b/libcxx/test/std/depr/depr.cpp.headers/ccomplex.verify.cpp @@ -0,0 +1,25 @@ +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// + +// check that is deprecated in C++17 and removed in C++20 +// When built with modules, should be omitted. + +// UNSUPPORTED: c++03, c++11, c++14 +// UNSUPPORTED: clang-modules-build + +#include "test_macros.h" + +#include + +#if TEST_STD_VER >= 20 +// expected-warning@ccomplex:* {{'__standard_header_ccomplex' is deprecated: removed in C++20. Include instead.}} +#else +// expected-warning@ccomplex:* {{'__standard_header_ccomplex' is deprecated: Include instead.}} +#endif diff --git a/libcxx/test/std/depr/depr.cpp.headers/ciso646.verify.cpp b/libcxx/test/std/depr/depr.cpp.headers/ciso646.verify.cpp new file mode 100644 index 00000000000000..04acd100815485 --- /dev/null +++ b/libcxx/test/std/depr/depr.cpp.headers/ciso646.verify.cpp @@ -0,0 +1,18 @@ +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// + +// check that is removed in C++20 +// When built with modules, should be omitted. + +// UNSUPPORTED: c++03, c++11, c++14, c++17 +// UNSUPPORTED: clang-modules-build + +#include +// expected-warning@ciso646:* {{'__standard_header_ciso646' is deprecated: removed in C++20. Include instead.}} diff --git a/libcxx/test/std/depr/depr.cpp.headers/cstdalign.verify.cpp b/libcxx/test/std/depr/depr.cpp.headers/cstdalign.verify.cpp new file mode 100644 index 00000000000000..dc9f1af55b3f14 --- /dev/null +++ b/libcxx/test/std/depr/depr.cpp.headers/cstdalign.verify.cpp @@ -0,0 +1,25 @@ +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// + +// check that is deprecated in C++17 and removed in C++20 +// When built with modules, should be omitted. + +// UNSUPPORTED: c++03, c++11, c++14 +// UNSUPPORTED: clang-modules-build + +#include "test_macros.h" + +#include + +#if TEST_STD_VER >= 20 +// expected-warning@cstdalign:* {{'__standard_header_cstdalign' is deprecated: removed in C++20.}} +#else +// expected-warning@cstdalign:* {{'__standard_header_cstdalign' is deprecated}} +#endif diff --git a/libcxx/test/std/depr/depr.cpp.headers/cstdbool.verify.cpp b/libcxx/test/std/depr/depr.cpp.headers/cstdbool.verify.cpp new file mode 100644 index 00000000000000..eddefe14d35eac --- /dev/null +++ b/libcxx/test/std/depr/depr.cpp.headers/cstdbool.verify.cpp @@ -0,0 +1,25 @@ +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// + +// check that is deprecated in C++17 and removed in C++20 +// When built with modules, should be omitted. + +// UNSUPPORTED: c++03, c++11, c++14 +// UNSUPPORTED: clang-modules-build + +#include "test_macros.h" + +#include + +#if TEST_STD_VER >= 20 +// expected-warning@cstdbool:* {{'__standard_header_cstdbool' is deprecated: removed in C++20.}} +#else +// expected-warning@cstdbool:* {{'__standard_header_cstdbool' is deprecated}} +#endif diff --git a/libcxx/test/std/depr/depr.cpp.headers/ctgmath.verify.cpp b/libcxx/test/std/depr/depr.cpp.headers/ctgmath.verify.cpp new file mode 100644 index 00000000000000..097ab1643d15af --- /dev/null +++ b/libcxx/test/std/depr/depr.cpp.headers/ctgmath.verify.cpp @@ -0,0 +1,25 @@ +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// + +// check that is deprecated in C++17 and removed in C++20 +// When built with modules, should be omitted. + +// UNSUPPORTED: c++03, c++11, c++14 +// UNSUPPORTED: clang-modules-build + +#include "test_macros.h" + +#include + +#if TEST_STD_VER >= 20 +// expected-warning@ctgmath:* {{'__standard_header_ctgmath' is deprecated: removed in C++20. Include and instead.}} +#else +// expected-warning@ctgmath:* {{'__standard_header_ctgmath' is deprecated: Include and instead.}} +#endif diff --git a/libcxx/test/std/language.support/support.runtime/cstdalign.compile.pass.cpp b/libcxx/test/std/language.support/support.runtime/cstdalign.compile.pass.cpp new file mode 100644 index 00000000000000..fbbaf9b2d136f9 --- /dev/null +++ b/libcxx/test/std/language.support/support.runtime/cstdalign.compile.pass.cpp @@ -0,0 +1,29 @@ +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// test // deprecated in C++17, removed in C++20, but still provided by libc++ as an extension + +// ADDITIONAL_COMPILE_FLAGS: -D_LIBCPP_DISABLE_DEPRECATION_WARNINGS + +#include + +#ifndef __alignas_is_defined +# error __alignas_is_defined not defined +#endif + +#ifndef __alignof_is_defined +# error __alignof_is_defined not defined +#endif + +#ifdef alignas +# error alignas should not be defined +#endif + +#ifdef alignof +# error alignof should not be defined +#endif diff --git a/libcxx/test/std/language.support/support.runtime/cstdbool.pass.cpp b/libcxx/test/std/language.support/support.runtime/cstdbool.pass.cpp index 1d0e9b06a43d2e..9a35eea507c40a 100644 --- a/libcxx/test/std/language.support/support.runtime/cstdbool.pass.cpp +++ b/libcxx/test/std/language.support/support.runtime/cstdbool.pass.cpp @@ -6,7 +6,9 @@ // //===----------------------------------------------------------------------===// -// test +// test // deprecated in C++17, removed in C++20, but still provided by libc++ as an extension + +// ADDITIONAL_COMPILE_FLAGS: -D_LIBCPP_DISABLE_DEPRECATION_WARNINGS #include diff --git a/libcxx/test/std/numerics/c.math/ctgmath.pass.cpp b/libcxx/test/std/numerics/c.math/ctgmath.pass.cpp index 2c8d054fbc527d..2e4679980577a9 100644 --- a/libcxx/test/std/numerics/c.math/ctgmath.pass.cpp +++ b/libcxx/test/std/numerics/c.math/ctgmath.pass.cpp @@ -6,7 +6,9 @@ // //===----------------------------------------------------------------------===// -// +// // deprecated in C++17, removed in C++20, but still provided by libc++ as an extension + +// ADDITIONAL_COMPILE_FLAGS: -D_LIBCPP_DISABLE_DEPRECATION_WARNINGS #include diff --git a/libcxx/test/std/numerics/complex.number/ccmplx/ccomplex.pass.cpp b/libcxx/test/std/numerics/complex.number/ccmplx/ccomplex.pass.cpp index cc3f8cd6a9beb9..0ed116c6410639 100644 --- a/libcxx/test/std/numerics/complex.number/ccmplx/ccomplex.pass.cpp +++ b/libcxx/test/std/numerics/complex.number/ccmplx/ccomplex.pass.cpp @@ -6,7 +6,9 @@ // //===----------------------------------------------------------------------===// -// +// // deprecated in C++17, removed in C++20, but still provided by libc++ as an extension + +// ADDITIONAL_COMPILE_FLAGS: -D_LIBCPP_DISABLE_DEPRECATION_WARNINGS #include diff --git a/libcxx/test/std/strings/basic.string/string.capacity/deallocate_size.pass.cpp b/libcxx/test/std/strings/basic.string/string.capacity/deallocate_size.pass.cpp index 1203b2f3ec18f9..00f9e2b8467837 100644 --- a/libcxx/test/std/strings/basic.string/string.capacity/deallocate_size.pass.cpp +++ b/libcxx/test/std/strings/basic.string/string.capacity/deallocate_size.pass.cpp @@ -34,15 +34,32 @@ struct test_alloc { typedef test_alloc other; }; - TEST_CONSTEXPR_CXX14 pointer allocate(size_type n, const void* = nullptr) { + TEST_CONSTEXPR test_alloc() TEST_NOEXCEPT {} + + template + TEST_CONSTEXPR test_alloc(const test_alloc&) TEST_NOEXCEPT {} + + pointer allocate(size_type n, const void* = nullptr) { allocated_ += n; return std::allocator().allocate(n); } - TEST_CONSTEXPR_CXX14 void deallocate(pointer p, size_type s) { + void deallocate(pointer p, size_type s) { allocated_ -= s; std::allocator().deallocate(p, s); } + + template + friend TEST_CONSTEXPR bool operator==(const test_alloc&, const test_alloc&) TEST_NOEXCEPT { + return true; + } + +#if TEST_STD_VER < 20 + template + friend TEST_CONSTEXPR bool operator!=(const test_alloc&, const test_alloc&) TEST_NOEXCEPT { + return false; + } +#endif }; template diff --git a/libcxx/utils/libcxx/header_information.py b/libcxx/utils/libcxx/header_information.py index 3b12dcb9f56c0b..cac620e4f1fe77 100644 --- a/libcxx/utils/libcxx/header_information.py +++ b/libcxx/utils/libcxx/header_information.py @@ -66,6 +66,7 @@ def is_cstd(self) -> bool: "cmath", "csetjmp", "csignal", + "cstdalign", "cstdarg", "cstdbool", "cstddef", @@ -92,7 +93,7 @@ def has_cxx20_module(self) -> bool: experimental headers. """ # These headers have been removed in C++20 so are never part of a module. - removed_in_20 = ["ccomplex", "ciso646", "cstdbool", "ctgmath"] + removed_in_20 = ["ccomplex", "ciso646", "cstdalign", "cstdbool", "ctgmath"] return self.is_public() and not self.is_experimental() and not self.is_C_compatibility() and not self._name in removed_in_20 def is_cxx03_frozen_header(self) -> bool: @@ -236,6 +237,15 @@ def __hash__(self) -> int: "wctype.h": "// UNSUPPORTED: no-wide-characters", } +# Undeprecate headers that are deprecated in C++17 and removed in C++20. +lit_header_undeprecations = { + "ccomplex": "// ADDITIONAL_COMPILE_FLAGS: -D_LIBCPP_DISABLE_DEPRECATION_WARNINGS", + "ciso646": "// ADDITIONAL_COMPILE_FLAGS: -D_LIBCPP_DISABLE_DEPRECATION_WARNINGS", + "cstdalign": "// ADDITIONAL_COMPILE_FLAGS: -D_LIBCPP_DISABLE_DEPRECATION_WARNINGS", + "cstdbool": "// ADDITIONAL_COMPILE_FLAGS: -D_LIBCPP_DISABLE_DEPRECATION_WARNINGS", + "ctgmath": "// ADDITIONAL_COMPILE_FLAGS: -D_LIBCPP_DISABLE_DEPRECATION_WARNINGS", +} + # This table was produced manually, by grepping the TeX source of the Standard's # library clauses for the string "#include". Each header's synopsis contains # explicit "#include" directives for its mandatory inclusions. diff --git a/lld/ELF/Options.td b/lld/ELF/Options.td index c80c4017d3512c..ebe77204264210 100644 --- a/lld/ELF/Options.td +++ b/lld/ELF/Options.td @@ -720,7 +720,7 @@ def: J<"plugin-opt=opt-remarks-format=">, HelpText<"Alias for --opt-remarks-format">; def: F<"plugin-opt=opt-remarks-with-hotness">, Alias, - HelpText<"Alias for --opt-remarks-with_hotness">; + HelpText<"Alias for --opt-remarks-with-hotness">; def: J<"plugin-opt=opt-remarks-hotness-threshold=">, Alias, HelpText<"Alias for --opt-remarks-hotness-threshold">; diff --git a/lldb/docs/resources/test.rst b/lldb/docs/resources/test.rst index 715d3772fe2787..5f1bd0d5738305 100644 --- a/lldb/docs/resources/test.rst +++ b/lldb/docs/resources/test.rst @@ -418,8 +418,8 @@ An overview of all LLDB builders can be found here: `https://lab.llvm.org/buildbot/#/builders?tags=lldb `_ Building and testing for macOS uses a different platform called GreenDragon. It -has a dedicated tab for LLDB: `https://green.lab.llvm.org/green/view/LLDB/ -`_ +has a dedicated tab for LLDB: `https://green.lab.llvm.org/job/llvm.org/view/LLDB/ +`_ Running The Tests diff --git a/lldb/packages/Python/lldbsuite/test/tools/lldb-dap/dap_server.py b/lldb/packages/Python/lldbsuite/test/tools/lldb-dap/dap_server.py index 63748a71f1122d..c29992ce9c7848 100644 --- a/lldb/packages/Python/lldbsuite/test/tools/lldb-dap/dap_server.py +++ b/lldb/packages/Python/lldbsuite/test/tools/lldb-dap/dap_server.py @@ -793,8 +793,6 @@ def request_launch( args_dict["env"] = env if stopOnEntry: args_dict["stopOnEntry"] = stopOnEntry - if disableASLR: - args_dict["disableASLR"] = disableASLR if disableSTDIO: args_dict["disableSTDIO"] = disableSTDIO if shellExpandArguments: @@ -829,6 +827,7 @@ def request_launch( if customThreadFormat: args_dict["customThreadFormat"] = customThreadFormat + args_dict["disableASLR"] = disableASLR args_dict["enableAutoVariableSummaries"] = enableAutoVariableSummaries args_dict["enableSyntheticChildDebugging"] = enableSyntheticChildDebugging args_dict["displayExtendedBacktrace"] = displayExtendedBacktrace diff --git a/lldb/source/Core/SourceManager.cpp b/lldb/source/Core/SourceManager.cpp index fd5b49946c6a92..27a9edeef4249e 100644 --- a/lldb/source/Core/SourceManager.cpp +++ b/lldb/source/Core/SourceManager.cpp @@ -430,7 +430,7 @@ SourceManager::GetDefaultFileAndLine() { false; // Force it to be a debug symbol. function_options.include_inlines = true; executable_ptr->FindFunctions(main_name, CompilerDeclContext(), - lldb::eFunctionNameTypeBase, + lldb::eFunctionNameTypeFull, function_options, sc_list); for (const SymbolContext &sc : sc_list) { if (sc.function) { diff --git a/lldb/source/Host/common/FileAction.cpp b/lldb/source/Host/common/FileAction.cpp index f980d3224640e0..e1c3e14a165ea9 100644 --- a/lldb/source/Host/common/FileAction.cpp +++ b/lldb/source/Host/common/FileAction.cpp @@ -41,7 +41,7 @@ bool FileAction::Open(int fd, const FileSpec &file_spec, bool read, else if (read) m_arg = O_NOCTTY | O_RDONLY; else - m_arg = O_NOCTTY | O_CREAT | O_WRONLY; + m_arg = O_NOCTTY | O_CREAT | O_WRONLY | O_TRUNC; m_file_spec = file_spec; return true; } else { diff --git a/lldb/source/Plugins/ScriptInterpreter/Python/ScriptInterpreterPython.cpp b/lldb/source/Plugins/ScriptInterpreter/Python/ScriptInterpreterPython.cpp index 7cc38da6a6a94b..6158083a982801 100644 --- a/lldb/source/Plugins/ScriptInterpreter/Python/ScriptInterpreterPython.cpp +++ b/lldb/source/Plugins/ScriptInterpreter/Python/ScriptInterpreterPython.cpp @@ -92,7 +92,38 @@ namespace { struct InitializePythonRAII { public: InitializePythonRAII() { - InitializePythonHome(); +#if (PY_MAJOR_VERSION == 3 && PY_MINOR_VERSION >= 8) || (PY_MAJOR_VERSION > 3) + PyConfig config; + PyConfig_InitPythonConfig(&config); +#endif + +#if LLDB_EMBED_PYTHON_HOME + typedef wchar_t *str_type; + static str_type g_python_home = []() -> str_type { + const char *lldb_python_home = LLDB_PYTHON_HOME; + const char *absolute_python_home = nullptr; + llvm::SmallString<64> path; + if (llvm::sys::path::is_absolute(lldb_python_home)) { + absolute_python_home = lldb_python_home; + } else { + FileSpec spec = HostInfo::GetShlibDir(); + if (!spec) + return nullptr; + spec.GetPath(path); + llvm::sys::path::append(path, lldb_python_home); + absolute_python_home = path.c_str(); + } + size_t size = 0; + return Py_DecodeLocale(absolute_python_home, &size); + }(); + if (g_python_home != nullptr) { +#if (PY_MAJOR_VERSION == 3 && PY_MINOR_VERSION >= 8) || (PY_MAJOR_VERSION > 3) + PyConfig_SetBytesString(&config, &config.home, g_python_home); +#else + Py_SetPythonHome(g_python_home); +#endif + } +#endif // The table of built-in modules can only be extended before Python is // initialized. @@ -117,15 +148,22 @@ struct InitializePythonRAII { PyImport_AppendInittab("_lldb", LLDBSwigPyInit); } +#if (PY_MAJOR_VERSION == 3 && PY_MINOR_VERSION >= 8) || (PY_MAJOR_VERSION > 3) + config.install_signal_handlers = 0; + Py_InitializeFromConfig(&config); + PyConfig_Clear(&config); + InitializeThreadsPrivate(); +#else // Python < 3.2 and Python >= 3.2 reversed the ordering requirements for // calling `Py_Initialize` and `PyEval_InitThreads`. < 3.2 requires that you // call `PyEval_InitThreads` first, and >= 3.2 requires that you call it last. -#if (PY_MAJOR_VERSION == 3 && PY_MINOR_VERSION >= 2) || (PY_MAJOR_VERSION > 3) +#if (PY_MAJOR_VERSION == 3 && PY_MINOR_VERSION >= 2) Py_InitializeEx(0); InitializeThreadsPrivate(); #else InitializeThreadsPrivate(); Py_InitializeEx(0); +#endif #endif } @@ -142,32 +180,6 @@ struct InitializePythonRAII { } private: - void InitializePythonHome() { -#if LLDB_EMBED_PYTHON_HOME - typedef wchar_t *str_type; - static str_type g_python_home = []() -> str_type { - const char *lldb_python_home = LLDB_PYTHON_HOME; - const char *absolute_python_home = nullptr; - llvm::SmallString<64> path; - if (llvm::sys::path::is_absolute(lldb_python_home)) { - absolute_python_home = lldb_python_home; - } else { - FileSpec spec = HostInfo::GetShlibDir(); - if (!spec) - return nullptr; - spec.GetPath(path); - llvm::sys::path::append(path, lldb_python_home); - absolute_python_home = path.c_str(); - } - size_t size = 0; - return Py_DecodeLocale(absolute_python_home, &size); - }(); - if (g_python_home != nullptr) { - Py_SetPythonHome(g_python_home); - } -#endif - } - void InitializeThreadsPrivate() { // Since Python 3.7 `Py_Initialize` calls `PyEval_InitThreads` inside itself, // so there is no way to determine whether the embedded interpreter diff --git a/lldb/source/Plugins/SymbolFile/DWARF/DWARFIndex.cpp b/lldb/source/Plugins/SymbolFile/DWARF/DWARFIndex.cpp index dee90804c52584..c18edd10b96819 100644 --- a/lldb/source/Plugins/SymbolFile/DWARF/DWARFIndex.cpp +++ b/lldb/source/Plugins/SymbolFile/DWARF/DWARFIndex.cpp @@ -151,3 +151,19 @@ bool DWARFIndex::ProcessTypeDIEMatchQuery( return true; return callback(die); } + +void DWARFIndex::GetNamespacesWithParents( + ConstString name, const CompilerDeclContext &parent_decl_ctx, + llvm::function_ref callback) { + GetNamespaces(name, [&](DWARFDIE die) { + return ProcessNamespaceDieMatchParents(parent_decl_ctx, die, callback); + }); +} + +bool DWARFIndex::ProcessNamespaceDieMatchParents( + const CompilerDeclContext &parent_decl_ctx, DWARFDIE die, + llvm::function_ref callback) { + if (!SymbolFileDWARF::DIEInDeclContext(parent_decl_ctx, die)) + return true; + return callback(die); +} diff --git a/lldb/source/Plugins/SymbolFile/DWARF/DWARFIndex.h b/lldb/source/Plugins/SymbolFile/DWARF/DWARFIndex.h index fea3a4fd697389..ac1f75e91c2195 100644 --- a/lldb/source/Plugins/SymbolFile/DWARF/DWARFIndex.h +++ b/lldb/source/Plugins/SymbolFile/DWARF/DWARFIndex.h @@ -71,6 +71,14 @@ class DWARFIndex { virtual void GetTypesWithQuery(TypeQuery &query, llvm::function_ref callback); + /// Get namespace DIEs whose base name match \param name with \param + /// parent_decl_ctx in its decl parent chain. A base implementation + /// is provided. Specializations should override this if they are able to + /// provide a faster implementation. + virtual void + GetNamespacesWithParents(ConstString name, + const CompilerDeclContext &parent_decl_ctx, + llvm::function_ref callback); virtual void GetFunctions(const Module::LookupInfo &lookup_info, SymbolFileDWARF &dwarf, const CompilerDeclContext &parent_decl_ctx, @@ -127,6 +135,9 @@ class DWARFIndex { bool ProcessTypeDIEMatchQuery(TypeQuery &query, DWARFDIE die, llvm::function_ref callback); + bool ProcessNamespaceDieMatchParents( + const CompilerDeclContext &parent_decl_ctx, DWARFDIE die, + llvm::function_ref callback); }; } // namespace dwarf } // namespace lldb_private::plugin diff --git a/lldb/source/Plugins/SymbolFile/DWARF/DebugNamesDWARFIndex.cpp b/lldb/source/Plugins/SymbolFile/DWARF/DebugNamesDWARFIndex.cpp index c809e5ff7f8535..6f2cb455ec00e1 100644 --- a/lldb/source/Plugins/SymbolFile/DWARF/DebugNamesDWARFIndex.cpp +++ b/lldb/source/Plugins/SymbolFile/DWARF/DebugNamesDWARFIndex.cpp @@ -368,9 +368,10 @@ void DebugNamesDWARFIndex::GetFullyQualifiedType( continue; } - if (SameParentChain(parent_names, *parent_chain) && - !ProcessEntry(entry, callback)) - return; + if (SameParentChain(parent_names, *parent_chain)) { + if (!ProcessEntry(entry, callback)) + return; + } } m_fallback.GetFullyQualifiedType(context, callback); } @@ -554,17 +555,60 @@ void DebugNamesDWARFIndex::GetTypesWithQuery( continue; } - if (WithinParentChain(parent_contexts, *parent_chain) && - !ProcessEntry(entry, [&](DWARFDIE die) { - // After .debug_names filtering still sending to base class for - // further filtering before calling the callback. - return ProcessTypeDIEMatchQuery(query, die, callback); - })) - return; + if (WithinParentChain(parent_contexts, *parent_chain)) { + if (!ProcessEntry(entry, [&](DWARFDIE die) { + // After .debug_names filtering still sending to base class for + // further filtering before calling the callback. + return ProcessTypeDIEMatchQuery(query, die, callback); + })) + // If the callback returns false, we're done. + return; + } } m_fallback.GetTypesWithQuery(query, callback); } +void DebugNamesDWARFIndex::GetNamespacesWithParents( + ConstString name, const CompilerDeclContext &parent_decl_ctx, + llvm::function_ref callback) { + std::vector parent_contexts = + parent_decl_ctx.GetCompilerContext(); + llvm::SmallVector parent_named_contexts; + std::copy_if(parent_contexts.rbegin(), parent_contexts.rend(), + std::back_inserter(parent_named_contexts), + [](const CompilerContext &ctx) { return !ctx.name.IsEmpty(); }); + for (const DebugNames::Entry &entry : + m_debug_names_up->equal_range(name.GetStringRef())) { + lldb_private::dwarf::Tag entry_tag = entry.tag(); + if (entry_tag == DW_TAG_namespace || + entry_tag == DW_TAG_imported_declaration) { + std::optional> parent_chain = + getParentChain(entry); + if (!parent_chain) { + // Fallback: use the base class implementation. + if (!ProcessEntry(entry, [&](DWARFDIE die) { + return ProcessNamespaceDieMatchParents(parent_decl_ctx, die, + callback); + })) + return; + continue; + } + + if (WithinParentChain(parent_named_contexts, *parent_chain)) { + if (!ProcessEntry(entry, [&](DWARFDIE die) { + // After .debug_names filtering still sending to base class for + // further filtering before calling the callback. + return ProcessNamespaceDieMatchParents(parent_decl_ctx, die, + callback); + })) + // If the callback returns false, we're done. + return; + } + } + } + m_fallback.GetNamespacesWithParents(name, parent_decl_ctx, callback); +} + void DebugNamesDWARFIndex::GetFunctions( const Module::LookupInfo &lookup_info, SymbolFileDWARF &dwarf, const CompilerDeclContext &parent_decl_ctx, diff --git a/lldb/source/Plugins/SymbolFile/DWARF/DebugNamesDWARFIndex.h b/lldb/source/Plugins/SymbolFile/DWARF/DebugNamesDWARFIndex.h index 074f68a8c55963..ab6cde12623f6a 100644 --- a/lldb/source/Plugins/SymbolFile/DWARF/DebugNamesDWARFIndex.h +++ b/lldb/source/Plugins/SymbolFile/DWARF/DebugNamesDWARFIndex.h @@ -55,7 +55,9 @@ class DebugNamesDWARFIndex : public DWARFIndex { void GetTypesWithQuery(TypeQuery &query, llvm::function_ref callback) override; - + void GetNamespacesWithParents( + ConstString name, const CompilerDeclContext &parent_decl_ctx, + llvm::function_ref callback) override; void GetFunctions(const Module::LookupInfo &lookup_info, SymbolFileDWARF &dwarf, const CompilerDeclContext &parent_decl_ctx, diff --git a/lldb/source/Plugins/SymbolFile/DWARF/SymbolFileDWARF.cpp b/lldb/source/Plugins/SymbolFile/DWARF/SymbolFileDWARF.cpp index e5b8eee8d08c24..f23f8cc3d781d0 100644 --- a/lldb/source/Plugins/SymbolFile/DWARF/SymbolFileDWARF.cpp +++ b/lldb/source/Plugins/SymbolFile/DWARF/SymbolFileDWARF.cpp @@ -2900,7 +2900,7 @@ SymbolFileDWARF::FindNamespace(ConstString name, if (!DeclContextMatchesThisSymbolFile(parent_decl_ctx)) return namespace_decl_ctx; - m_index->GetNamespaces(name, [&](DWARFDIE die) { + m_index->GetNamespacesWithParents(name, parent_decl_ctx, [&](DWARFDIE die) { if (!DIEInDeclContext(parent_decl_ctx, die, only_root_namespaces)) return true; // The containing decl contexts don't match diff --git a/lldb/test/API/commands/settings/TestSettings.py b/lldb/test/API/commands/settings/TestSettings.py index 385acceb7a8b5c..2dd813f6b155b3 100644 --- a/lldb/test/API/commands/settings/TestSettings.py +++ b/lldb/test/API/commands/settings/TestSettings.py @@ -528,6 +528,59 @@ def test_set_error_output_path(self): output, exe=False, startstr="This message should go to standard out." ) + @skipIfDarwinEmbedded # debugserver on ios etc can't write files + def test_same_error_output_path(self): + """Test that setting target.error and output-path to the same file path for the launched process works.""" + self.build() + + exe = self.getBuildArtifact("a.out") + self.runCmd("file " + exe, CURRENT_EXECUTABLE_SET) + + # Set the error-path and output-path and verify both are set. + self.runCmd( + "settings set target.error-path '{0}'".format( + lldbutil.append_to_process_working_directory(self, "output.txt") + ) + ) + self.runCmd( + "settings set target.output-path '{0}".format( + lldbutil.append_to_process_working_directory(self, "output.txt") + ) + ) + # And add hooks to restore the original settings during tearDown(). + self.addTearDownHook(lambda: self.runCmd("settings clear target.output-path")) + self.addTearDownHook(lambda: self.runCmd("settings clear target.error-path")) + + self.expect( + "settings show target.error-path", + SETTING_MSG("target.error-path"), + substrs=["target.error-path (file)", 'output.txt"'], + ) + + self.expect( + "settings show target.output-path", + SETTING_MSG("target.output-path"), + substrs=["target.output-path (file)", 'output.txt"'], + ) + + self.runCmd( + "process launch --working-dir '{0}'".format( + self.get_process_working_directory() + ), + RUN_SUCCEEDED, + ) + + output = lldbutil.read_file_from_process_wd(self, "output.txt") + err_message = "This message should go to standard error." + out_message = "This message should go to standard out." + # Error msg should get flushed by the output msg + self.expect(output, exe=False, substrs=[out_message]) + self.assertNotIn( + err_message, + output, + "Race condition when both stderr/stdout redirects to the same file", + ) + def test_print_dictionary_setting(self): self.runCmd("settings clear target.env-vars") self.runCmd('settings set target.env-vars ["MY_VAR"]=some-value') diff --git a/lldb/test/API/python_api/process/io/TestProcessIO.py b/lldb/test/API/python_api/process/io/TestProcessIO.py index 5bb91d2758312d..3b5c7c48c51f4d 100644 --- a/lldb/test/API/python_api/process/io/TestProcessIO.py +++ b/lldb/test/API/python_api/process/io/TestProcessIO.py @@ -95,6 +95,36 @@ def test_stdout_stderr_redirection(self): error = self.read_error_file_and_delete() self.check_process_output(output, error) + @skipIfWindows # stdio manipulation unsupported on Windows + @expectedFlakeyLinux(bugnumber="llvm.org/pr26437") + @skipIfDarwinEmbedded # debugserver can't create/write files on the device + def test_stdout_stderr_redirection_to_existing_files(self): + """Exercise SBLaunchInfo::AddOpenFileAction() for STDOUT and STDERR without redirecting STDIN to output files already exist.""" + self.setup_test() + self.build() + self.create_target() + self.write_file_with_placeholder(self.output_file) + self.write_file_with_placeholder(self.error_file) + self.redirect_stdout() + self.redirect_stderr() + self.run_process(True) + output = self.read_output_file_and_delete() + error = self.read_error_file_and_delete() + self.check_process_output(output, error) + + def write_file_with_placeholder(self, target_file): + placeholder = "This content should be overwritten." + if lldb.remote_platform: + self.runCmd( + 'platform file write "{target}" -d "{data}"'.format( + target=target_file, data=placeholder + ) + ) + else: + f = open(target_file, "w") + f.write(placeholder) + f.close() + # target_file - path on local file system or remote file system if running remote # local_file - path on local system def read_file_and_delete(self, target_file, local_file): diff --git a/lldb/tools/lldb-dap/ProgressEvent.cpp b/lldb/tools/lldb-dap/ProgressEvent.cpp index 8a660b50af1205..0dcc2ee81001d5 100644 --- a/lldb/tools/lldb-dap/ProgressEvent.cpp +++ b/lldb/tools/lldb-dap/ProgressEvent.cpp @@ -110,7 +110,6 @@ json::Value ProgressEvent::ToJSON() const { std::string progress_id_str; llvm::raw_string_ostream progress_id_strm(progress_id_str); progress_id_strm << m_progress_id; - progress_id_strm.flush(); body.try_emplace("progressId", progress_id_str); if (m_event_type == progressStart) { diff --git a/lldb/unittests/Expression/DWARFExpressionTest.cpp b/lldb/unittests/Expression/DWARFExpressionTest.cpp index f9e0605fce29d6..fdc9bfae1876c5 100644 --- a/lldb/unittests/Expression/DWARFExpressionTest.cpp +++ b/lldb/unittests/Expression/DWARFExpressionTest.cpp @@ -181,6 +181,9 @@ TEST(DWARFExpression, DW_OP_bra) { }), // clang-format on llvm::HasValue(0x42)); + + EXPECT_THAT_ERROR(Evaluate({DW_OP_bra, 0x01, 0x00}).takeError(), + llvm::Failed()); } TEST(DWARFExpression, DW_OP_convert) { diff --git a/lldb/unittests/Host/FileActionTest.cpp b/lldb/unittests/Host/FileActionTest.cpp index b208169aac20e6..56227cd587e5bb 100644 --- a/lldb/unittests/Host/FileActionTest.cpp +++ b/lldb/unittests/Host/FileActionTest.cpp @@ -6,8 +6,13 @@ // //===----------------------------------------------------------------------===// +#include + #include "lldb/Host/FileAction.h" #include "gtest/gtest.h" +#if defined(_WIN32) +#include "lldb/Host/windows/PosixApi.h" +#endif using namespace lldb_private; @@ -17,3 +22,26 @@ TEST(FileActionTest, Open) { EXPECT_EQ(Action.GetAction(), FileAction::eFileActionOpen); EXPECT_EQ(Action.GetFileSpec(), FileSpec("/tmp")); } + +TEST(FileActionTest, OpenReadWrite) { + FileAction Action; + Action.Open(48, FileSpec("/tmp_0"), /*read*/ true, /*write*/ true); + EXPECT_TRUE(Action.GetActionArgument() & (O_NOCTTY | O_CREAT | O_RDWR)); + EXPECT_FALSE(Action.GetActionArgument() & O_RDONLY); + EXPECT_FALSE(Action.GetActionArgument() & O_WRONLY); +} + +TEST(FileActionTest, OpenReadOnly) { + FileAction Action; + Action.Open(49, FileSpec("/tmp_1"), /*read*/ true, /*write*/ false); + EXPECT_TRUE(Action.GetActionArgument() & (O_NOCTTY | O_RDONLY)); + EXPECT_FALSE(Action.GetActionArgument() & O_WRONLY); +} + +TEST(FileActionTest, OpenWriteOnly) { + FileAction Action; + Action.Open(50, FileSpec("/tmp_2"), /*read*/ false, /*write*/ true); + EXPECT_TRUE(Action.GetActionArgument() & + (O_NOCTTY | O_CREAT | O_WRONLY | O_TRUNC)); + EXPECT_FALSE(Action.GetActionArgument() & O_RDONLY); +} diff --git a/llvm/docs/ReleaseNotes.md b/llvm/docs/ReleaseNotes.md index 92a45d845f1db8..d5c650e74eeb28 100644 --- a/llvm/docs/ReleaseNotes.md +++ b/llvm/docs/ReleaseNotes.md @@ -301,6 +301,8 @@ Changes to LLDB * LLDB can now read the `fpmr` register from AArch64 Linux processes and core files. +* Program stdout/stderr redirection will now open the file with O_TRUNC flag, make sure to truncate the file if path already exists. + * eg. `settings set target.output-path/target.error-path ` Changes to BOLT --------------------------------- diff --git a/llvm/include/llvm/ADT/StringRef.h b/llvm/include/llvm/ADT/StringRef.h index 0dcd4d90086eff..5b525c8e56ecc9 100644 --- a/llvm/include/llvm/ADT/StringRef.h +++ b/llvm/include/llvm/ADT/StringRef.h @@ -60,7 +60,11 @@ namespace llvm { using const_reverse_iterator = std::reverse_iterator; private: - std::string_view View; + /// The start of the string, in an external buffer. + const char *Data = nullptr; + + /// The length of the string. + size_t Length = 0; // Workaround memcmp issue with null pointers (undefined behavior) // by providing a specialized version @@ -82,26 +86,28 @@ namespace llvm { /// Construct a string ref from a cstring. /*implicit*/ constexpr StringRef(const char *Str LLVM_LIFETIME_BOUND) - : View(Str, Str ? + : Data(Str), Length(Str ? // GCC 7 doesn't have constexpr char_traits. Fall back to __builtin_strlen. #if defined(_GLIBCXX_RELEASE) && _GLIBCXX_RELEASE < 8 - __builtin_strlen(Str) + __builtin_strlen(Str) #else - std::char_traits::length(Str) + std::char_traits::length(Str) #endif - : 0) { + : 0) { } /// Construct a string ref from a pointer and length. /*implicit*/ constexpr StringRef(const char *data LLVM_LIFETIME_BOUND, size_t length) - : View(data, length) {} + : Data(data), Length(length) {} /// Construct a string ref from an std::string. - /*implicit*/ StringRef(const std::string &Str) : View(Str) {} + /*implicit*/ StringRef(const std::string &Str) + : Data(Str.data()), Length(Str.length()) {} /// Construct a string ref from an std::string_view. - /*implicit*/ constexpr StringRef(std::string_view Str) : View(Str) {} + /*implicit*/ constexpr StringRef(std::string_view Str) + : Data(Str.data()), Length(Str.size()) {} /// @} /// @name Iterators @@ -135,13 +141,13 @@ namespace llvm { /// data - Get a pointer to the start of the string (which may not be null /// terminated). - [[nodiscard]] constexpr const char *data() const { return View.data(); } + [[nodiscard]] constexpr const char *data() const { return Data; } /// empty - Check if the string is empty. [[nodiscard]] constexpr bool empty() const { return size() == 0; } /// size - Get the string size. - [[nodiscard]] constexpr size_t size() const { return View.size(); } + [[nodiscard]] constexpr size_t size() const { return Length; } /// front - Get the first character in the string. [[nodiscard]] char front() const { diff --git a/llvm/include/llvm/ADT/TrieHashIndexGenerator.h b/llvm/include/llvm/ADT/TrieHashIndexGenerator.h new file mode 100644 index 00000000000000..6f7e53b6b11b53 --- /dev/null +++ b/llvm/include/llvm/ADT/TrieHashIndexGenerator.h @@ -0,0 +1,122 @@ +//===- TrieHashIndexGenerator.h ---------------------------------*- C++ -*-===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +#ifndef LLVM_ADT_TRIEHASHINDEXGENERATOR_H +#define LLVM_ADT_TRIEHASHINDEXGENERATOR_H + +#include "llvm/ADT/ArrayRef.h" +#include + +namespace llvm { + +/// The utility class that helps computing the index of the object inside trie +/// from its hash. The generator can be configured with the number of bits +/// used for each level of trie structure with \c NumRootsBits and \c +/// NumSubtrieBits. +/// For example, try computing indexes for a 16-bit hash 0x1234 with 8-bit root +/// and 4-bit sub-trie: +/// +/// IndexGenerator IndexGen{8, 4, Hash}; +/// size_t index1 = IndexGen.next(); // index 18 in root node. +/// size_t index2 = IndexGen.next(); // index 3 in sub-trie level 1. +/// size_t index3 = IndexGen.next(); // index 4 in sub-tire level 2. +/// +/// This is used by different trie implementation to figure out where to +/// insert/find the object in the data structure. +struct TrieHashIndexGenerator { + size_t NumRootBits; + size_t NumSubtrieBits; + ArrayRef Bytes; + std::optional StartBit = std::nullopt; + + // Get the number of bits used to generate current index. + size_t getNumBits() const { + assert(StartBit); + size_t TotalNumBits = Bytes.size() * 8; + assert(*StartBit <= TotalNumBits); + return std::min(*StartBit ? NumSubtrieBits : NumRootBits, + TotalNumBits - *StartBit); + } + + // Get the index of the object in the next level of trie. + size_t next() { + if (!StartBit) { + // Compute index for root when StartBit is not set. + StartBit = 0; + return getIndex(Bytes, *StartBit, NumRootBits); + } + if (*StartBit < Bytes.size() * 8) { + // Compute index for sub-trie. + *StartBit += *StartBit ? NumSubtrieBits : NumRootBits; + assert((*StartBit - NumRootBits) % NumSubtrieBits == 0); + return getIndex(Bytes, *StartBit, NumSubtrieBits); + } + // All the bits are consumed. + return end(); + } + + // Provide a hint to speed up the index generation by providing the + // information of the hash in current level. For example, if the object is + // known to have \c Index on a level that already consumes first n \c Bits of + // the hash, it can start index generation from this level by calling \c hint + // function. + size_t hint(unsigned Index, unsigned Bit) { + assert(Bit < Bytes.size() * 8); + assert(Bit == 0 || (Bit - NumRootBits) % NumSubtrieBits == 0); + StartBit = Bit; + return Index; + } + + // Utility function for looking up the index in the trie for an object that + // has colliding hash bits in the front as the hash of the object that is + // currently being computed. + size_t getCollidingBits(ArrayRef CollidingBits) const { + assert(StartBit); + return getIndex(CollidingBits, *StartBit, NumSubtrieBits); + } + + size_t end() const { return SIZE_MAX; } + + // Compute the index for the object from its hash, current start bits, and + // the number of bits used for current level. + static size_t getIndex(ArrayRef Bytes, size_t StartBit, + size_t NumBits) { + assert(StartBit < Bytes.size() * 8); + // Drop all the bits before StartBit. + Bytes = Bytes.drop_front(StartBit / 8u); + StartBit %= 8u; + size_t Index = 0; + // Compute the index using the bits in range [StartBit, StartBit + NumBits), + // note the range can spread across few `uint8_t` in the array. + for (uint8_t Byte : Bytes) { + size_t ByteStart = 0, ByteEnd = 8; + if (StartBit) { + ByteStart = StartBit; + Byte &= (1u << (8 - StartBit)) - 1u; + StartBit = 0; + } + size_t CurrentNumBits = ByteEnd - ByteStart; + if (CurrentNumBits > NumBits) { + Byte >>= CurrentNumBits - NumBits; + CurrentNumBits = NumBits; + } + Index <<= CurrentNumBits; + Index |= Byte & ((1u << CurrentNumBits) - 1u); + + assert(NumBits >= CurrentNumBits); + NumBits -= CurrentNumBits; + if (!NumBits) + break; + } + return Index; + } +}; + +} // namespace llvm + +#endif // LLVM_ADT_TRIEHASHINDEXGENERATOR_H diff --git a/llvm/include/llvm/ADT/TrieRawHashMap.h b/llvm/include/llvm/ADT/TrieRawHashMap.h new file mode 100644 index 00000000000000..5bfe5c9e6a0f49 --- /dev/null +++ b/llvm/include/llvm/ADT/TrieRawHashMap.h @@ -0,0 +1,377 @@ +//===- TrieRawHashMap.h -----------------------------------------*- C++ -*-===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +#ifndef LLVM_ADT_TRIERAWHASHMAP_H +#define LLVM_ADT_TRIERAWHASHMAP_H + +#include "llvm/ADT/ArrayRef.h" +#include +#include + +namespace llvm { + +class raw_ostream; + +/// TrieRawHashMap - is a lock-free thread-safe trie that is can be used to +/// store/index data based on a hash value. It can be customized to work with +/// any hash algorithm or store any data. +/// +/// Data structure: +/// Data node stored in the Trie contains both hash and data: +/// struct { +/// HashT Hash; +/// DataT Data; +/// }; +/// +/// Data is stored/indexed via a prefix tree, where each node in the tree can be +/// either the root, a sub-trie or a data node. Assuming a 4-bit hash and two +/// data objects {0001, A} and {0100, B}, it can be stored in a trie +/// (assuming Root has 2 bits, SubTrie has 1 bit): +/// +--------+ +/// |Root[00]| -> {0001, A} +/// | [01]| -> {0100, B} +/// | [10]| (empty) +/// | [11]| (empty) +/// +--------+ +/// +/// Inserting a new object {0010, C} will result in: +/// +--------+ +----------+ +/// |Root[00]| -> |SubTrie[0]| -> {0001, A} +/// | | | [1]| -> {0010, C} +/// | | +----------+ +/// | [01]| -> {0100, B} +/// | [10]| (empty) +/// | [11]| (empty) +/// +--------+ +/// Note object A is sunk down to a sub-trie during the insertion. All the +/// nodes are inserted through compare-exchange to ensure thread-safe and +/// lock-free. +/// +/// To find an object in the trie, walk the tree with prefix of the hash until +/// the data node is found. Then the hash is compared with the hash stored in +/// the data node to see if the is the same object. +/// +/// Hash collision is not allowed so it is recommended to use trie with a +/// "strong" hashing algorithm. A well-distributed hash can also result in +/// better performance and memory usage. +/// +/// It currently does not support iteration and deletion. + +/// Base class for a lock-free thread-safe hash-mapped trie. +class ThreadSafeTrieRawHashMapBase { +public: + static constexpr size_t TrieContentBaseSize = 4; + static constexpr size_t DefaultNumRootBits = 6; + static constexpr size_t DefaultNumSubtrieBits = 4; + +private: + template struct AllocValueType { + char Base[TrieContentBaseSize]; + std::aligned_union_t Content; + }; + +protected: + template + static constexpr size_t DefaultContentAllocSize = sizeof(AllocValueType); + + template + static constexpr size_t DefaultContentAllocAlign = alignof(AllocValueType); + + template + static constexpr size_t DefaultContentOffset = + offsetof(AllocValueType, Content); + +public: + static void *operator new(size_t Size) { return ::operator new(Size); } + void operator delete(void *Ptr) { ::operator delete(Ptr); } + + LLVM_DUMP_METHOD void dump() const; + void print(raw_ostream &OS) const; + +protected: + /// Result of a lookup. Suitable for an insertion hint. Maybe could be + /// expanded into an iterator of sorts, but likely not useful (visiting + /// everything in the trie should probably be done some way other than + /// through an iterator pattern). + class PointerBase { + protected: + void *get() const { return I == -2u ? P : nullptr; } + + public: + PointerBase() noexcept = default; + + private: + friend class ThreadSafeTrieRawHashMapBase; + explicit PointerBase(void *Content) : P(Content), I(-2u) {} + PointerBase(void *P, unsigned I, unsigned B) : P(P), I(I), B(B) {} + + bool isHint() const { return I != -1u && I != -2u; } + + void *P = nullptr; + unsigned I = -1u; + unsigned B = 0; + }; + + /// Find the stored content with hash. + PointerBase find(ArrayRef Hash) const; + + /// Insert and return the stored content. + PointerBase + insert(PointerBase Hint, ArrayRef Hash, + function_ref Hash)> + Constructor); + + ThreadSafeTrieRawHashMapBase() = delete; + + ThreadSafeTrieRawHashMapBase( + size_t ContentAllocSize, size_t ContentAllocAlign, size_t ContentOffset, + std::optional NumRootBits = std::nullopt, + std::optional NumSubtrieBits = std::nullopt); + + /// Destructor, which asserts if there's anything to do. Subclasses should + /// call \a destroyImpl(). + /// + /// \pre \a destroyImpl() was already called. + ~ThreadSafeTrieRawHashMapBase(); + void destroyImpl(function_ref Destructor); + + ThreadSafeTrieRawHashMapBase(ThreadSafeTrieRawHashMapBase &&RHS); + + // Move assignment is not supported as it is not thread-safe. + ThreadSafeTrieRawHashMapBase & + operator=(ThreadSafeTrieRawHashMapBase &&RHS) = delete; + + // No copy. + ThreadSafeTrieRawHashMapBase(const ThreadSafeTrieRawHashMapBase &) = delete; + ThreadSafeTrieRawHashMapBase & + operator=(const ThreadSafeTrieRawHashMapBase &) = delete; + + // Debug functions. Implementation details and not guaranteed to be + // thread-safe. + PointerBase getRoot() const; + unsigned getStartBit(PointerBase P) const; + unsigned getNumBits(PointerBase P) const; + unsigned getNumSlotUsed(PointerBase P) const; + std::string getTriePrefixAsString(PointerBase P) const; + unsigned getNumTries() const; + // Visit next trie in the allocation chain. + PointerBase getNextTrie(PointerBase P) const; + +private: + friend class TrieRawHashMapTestHelper; + const unsigned short ContentAllocSize; + const unsigned short ContentAllocAlign; + const unsigned short ContentOffset; + unsigned short NumRootBits; + unsigned short NumSubtrieBits; + class ImplType; + // ImplPtr is owned by ThreadSafeTrieRawHashMapBase and needs to be freed in + // destroyImpl. + std::atomic ImplPtr; + ImplType &getOrCreateImpl(); + ImplType *getImpl() const; +}; + +/// Lock-free thread-safe hash-mapped trie. +template +class ThreadSafeTrieRawHashMap : public ThreadSafeTrieRawHashMapBase { +public: + using HashT = std::array; + + class LazyValueConstructor; + struct value_type { + const HashT Hash; + T Data; + + value_type(value_type &&) = default; + value_type(const value_type &) = default; + + value_type(ArrayRef Hash, const T &Data) + : Hash(makeHash(Hash)), Data(Data) {} + value_type(ArrayRef Hash, T &&Data) + : Hash(makeHash(Hash)), Data(std::move(Data)) {} + + private: + friend class LazyValueConstructor; + + struct EmplaceTag {}; + template + value_type(ArrayRef Hash, EmplaceTag, ArgsT &&...Args) + : Hash(makeHash(Hash)), Data(std::forward(Args)...) {} + + static HashT makeHash(ArrayRef HashRef) { + HashT Hash; + std::copy(HashRef.begin(), HashRef.end(), Hash.data()); + return Hash; + } + }; + + using ThreadSafeTrieRawHashMapBase::operator delete; + using HashType = HashT; + + using ThreadSafeTrieRawHashMapBase::dump; + using ThreadSafeTrieRawHashMapBase::print; + +private: + template class PointerImpl : PointerBase { + friend class ThreadSafeTrieRawHashMap; + + ValueT *get() const { + return reinterpret_cast(PointerBase::get()); + } + + public: + ValueT &operator*() const { + assert(get()); + return *get(); + } + ValueT *operator->() const { + assert(get()); + return get(); + } + explicit operator bool() const { return get(); } + + PointerImpl() = default; + + protected: + PointerImpl(PointerBase Result) : PointerBase(Result) {} + }; + +public: + class pointer; + class const_pointer; + class pointer : public PointerImpl { + friend class ThreadSafeTrieRawHashMap; + friend class const_pointer; + + public: + pointer() = default; + + private: + pointer(PointerBase Result) : pointer::PointerImpl(Result) {} + }; + + class const_pointer : public PointerImpl { + friend class ThreadSafeTrieRawHashMap; + + public: + const_pointer() = default; + const_pointer(const pointer &P) : const_pointer::PointerImpl(P) {} + + private: + const_pointer(PointerBase Result) : const_pointer::PointerImpl(Result) {} + }; + + class LazyValueConstructor { + public: + value_type &operator()(T &&RHS) { + assert(Mem && "Constructor already called, or moved away"); + return assign(::new (Mem) value_type(Hash, std::move(RHS))); + } + value_type &operator()(const T &RHS) { + assert(Mem && "Constructor already called, or moved away"); + return assign(::new (Mem) value_type(Hash, RHS)); + } + template value_type &emplace(ArgsT &&...Args) { + assert(Mem && "Constructor already called, or moved away"); + return assign(::new (Mem) + value_type(Hash, typename value_type::EmplaceTag{}, + std::forward(Args)...)); + } + + LazyValueConstructor(LazyValueConstructor &&RHS) + : Mem(RHS.Mem), Result(RHS.Result), Hash(RHS.Hash) { + RHS.Mem = nullptr; // Moved away, cannot call. + } + ~LazyValueConstructor() { assert(!Mem && "Constructor never called!"); } + + private: + value_type &assign(value_type *V) { + Mem = nullptr; + Result = V; + return *V; + } + friend class ThreadSafeTrieRawHashMap; + LazyValueConstructor() = delete; + LazyValueConstructor(void *Mem, value_type *&Result, ArrayRef Hash) + : Mem(Mem), Result(Result), Hash(Hash) { + assert(Hash.size() == sizeof(HashT) && "Invalid hash"); + assert(Mem && "Invalid memory for construction"); + } + void *Mem; + value_type *&Result; + ArrayRef Hash; + }; + + /// Insert with a hint. Default-constructed hint will work, but it's + /// recommended to start with a lookup to avoid overhead in object creation + /// if it already exists. + pointer insertLazy(const_pointer Hint, ArrayRef Hash, + function_ref OnConstruct) { + return pointer(ThreadSafeTrieRawHashMapBase::insert( + Hint, Hash, [&](void *Mem, ArrayRef Hash) { + value_type *Result = nullptr; + OnConstruct(LazyValueConstructor(Mem, Result, Hash)); + return Result->Hash.data(); + })); + } + + pointer insertLazy(ArrayRef Hash, + function_ref OnConstruct) { + return insertLazy(const_pointer(), Hash, OnConstruct); + } + + pointer insert(const_pointer Hint, value_type &&HashedData) { + return insertLazy(Hint, HashedData.Hash, [&](LazyValueConstructor C) { + C(std::move(HashedData.Data)); + }); + } + + pointer insert(const_pointer Hint, const value_type &HashedData) { + return insertLazy(Hint, HashedData.Hash, + [&](LazyValueConstructor C) { C(HashedData.Data); }); + } + + pointer find(ArrayRef Hash) { + assert(Hash.size() == std::tuple_size::value); + return ThreadSafeTrieRawHashMapBase::find(Hash); + } + + const_pointer find(ArrayRef Hash) const { + assert(Hash.size() == std::tuple_size::value); + return ThreadSafeTrieRawHashMapBase::find(Hash); + } + + ThreadSafeTrieRawHashMap(std::optional NumRootBits = std::nullopt, + std::optional NumSubtrieBits = std::nullopt) + : ThreadSafeTrieRawHashMapBase(DefaultContentAllocSize, + DefaultContentAllocAlign, + DefaultContentOffset, + NumRootBits, NumSubtrieBits) {} + + ~ThreadSafeTrieRawHashMap() { + if constexpr (std::is_trivially_destructible::value) + this->destroyImpl(nullptr); + else + this->destroyImpl( + [](void *P) { static_cast(P)->~value_type(); }); + } + + // Move constructor okay. + ThreadSafeTrieRawHashMap(ThreadSafeTrieRawHashMap &&) = default; + + // No move assignment or any copy. + ThreadSafeTrieRawHashMap &operator=(ThreadSafeTrieRawHashMap &&) = delete; + ThreadSafeTrieRawHashMap(const ThreadSafeTrieRawHashMap &) = delete; + ThreadSafeTrieRawHashMap & + operator=(const ThreadSafeTrieRawHashMap &) = delete; +}; + +} // namespace llvm + +#endif // LLVM_ADT_TRIERAWHASHMAP_H diff --git a/llvm/include/llvm/BinaryFormat/Dwarf.def b/llvm/include/llvm/BinaryFormat/Dwarf.def index 9336f2a454ae47..0cbbbe823c06b5 100644 --- a/llvm/include/llvm/BinaryFormat/Dwarf.def +++ b/llvm/include/llvm/BinaryFormat/Dwarf.def @@ -728,7 +728,7 @@ HANDLE_DW_OP(0x24, shl, 0, 2, 2, DWARF) HANDLE_DW_OP(0x25, shr, 0, 2, 2, DWARF) HANDLE_DW_OP(0x26, shra, 0, 2, 2, DWARF) HANDLE_DW_OP(0x27, xor, 0, 2, 2, DWARF) -HANDLE_DW_OP(0x28, bra, 1, 0, 2, DWARF) +HANDLE_DW_OP(0x28, bra, 1, 1, 2, DWARF) HANDLE_DW_OP(0x29, eq, 0, 2, 2, DWARF) HANDLE_DW_OP(0x2a, ge, 0, 2, 2, DWARF) HANDLE_DW_OP(0x2b, gt, 0, 2, 2, DWARF) diff --git a/llvm/include/llvm/CodeGen/GlobalISel/CSEInfo.h b/llvm/include/llvm/CodeGen/GlobalISel/CSEInfo.h index 816e94362f0262..8ce6eaa69c4ab7 100644 --- a/llvm/include/llvm/CodeGen/GlobalISel/CSEInfo.h +++ b/llvm/include/llvm/CodeGen/GlobalISel/CSEInfo.h @@ -17,6 +17,7 @@ #include "llvm/CodeGen/GlobalISel/GISelChangeObserver.h" #include "llvm/CodeGen/GlobalISel/GISelWorkList.h" #include "llvm/CodeGen/MachineFunctionPass.h" +#include "llvm/CodeGen/MachineRegisterInfo.h" #include "llvm/Support/Allocator.h" #include "llvm/Support/CodeGen.h" @@ -177,6 +178,8 @@ class GISelInstProfileBuilder { const GISelInstProfileBuilder &addNodeIDOpcode(unsigned Opc) const; const GISelInstProfileBuilder &addNodeIDRegType(const LLT Ty) const; const GISelInstProfileBuilder &addNodeIDRegType(const Register) const; + const GISelInstProfileBuilder & + addNodeIDRegType(MachineRegisterInfo::VRegAttrs) const; const GISelInstProfileBuilder & addNodeIDRegType(const TargetRegisterClass *RC) const; diff --git a/llvm/include/llvm/CodeGen/GlobalISel/GIMatchTableExecutor.h b/llvm/include/llvm/CodeGen/GlobalISel/GIMatchTableExecutor.h index 7b42722ca8d4f1..b4ff4cd178d757 100644 --- a/llvm/include/llvm/CodeGen/GlobalISel/GIMatchTableExecutor.h +++ b/llvm/include/llvm/CodeGen/GlobalISel/GIMatchTableExecutor.h @@ -24,6 +24,7 @@ #include "llvm/CodeGen/MachineInstr.h" #include "llvm/CodeGenTypes/LowLevelType.h" #include "llvm/IR/Function.h" +#include "llvm/Transforms/Utils/SizeOpts.h" #include #include #include @@ -635,8 +636,12 @@ class GIMatchTableExecutor { bool shouldOptForSize(const MachineFunction *MF) const { const auto &F = MF->getFunction(); - return F.hasOptSize() || F.hasMinSize() || - (PSI && BFI && CurMBB && llvm::shouldOptForSize(*CurMBB, PSI, BFI)); + if (F.hasOptSize()) + return true; + if (CurMBB) + if (auto *BB = CurMBB->getBasicBlock()) + return llvm::shouldOptimizeForSize(BB, PSI, BFI); + return false; } public: diff --git a/llvm/include/llvm/CodeGen/GlobalISel/GenericMachineInstrs.h b/llvm/include/llvm/CodeGen/GlobalISel/GenericMachineInstrs.h index b6309a9ea0ec78..cd7ebcf54c9e1e 100644 --- a/llvm/include/llvm/CodeGen/GlobalISel/GenericMachineInstrs.h +++ b/llvm/include/llvm/CodeGen/GlobalISel/GenericMachineInstrs.h @@ -28,7 +28,7 @@ namespace llvm { class GenericMachineInstr : public MachineInstr { constexpr static unsigned PoisonFlags = NoUWrap | NoSWrap | NoUSWrap | IsExact | Disjoint | NonNeg | - FmNoNans | FmNoInfs; + FmNoNans | FmNoInfs | SameSign; public: GenericMachineInstr() = delete; diff --git a/llvm/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h b/llvm/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h index ab3025e4923cd0..a38dd34a17097a 100644 --- a/llvm/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h +++ b/llvm/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h @@ -72,15 +72,20 @@ class DstOp { LLT LLTTy; Register Reg; const TargetRegisterClass *RC; + MachineRegisterInfo::VRegAttrs Attrs; }; public: - enum class DstType { Ty_LLT, Ty_Reg, Ty_RC }; + enum class DstType { Ty_LLT, Ty_Reg, Ty_RC, Ty_VRegAttrs }; DstOp(unsigned R) : Reg(R), Ty(DstType::Ty_Reg) {} DstOp(Register R) : Reg(R), Ty(DstType::Ty_Reg) {} DstOp(const MachineOperand &Op) : Reg(Op.getReg()), Ty(DstType::Ty_Reg) {} DstOp(const LLT T) : LLTTy(T), Ty(DstType::Ty_LLT) {} DstOp(const TargetRegisterClass *TRC) : RC(TRC), Ty(DstType::Ty_RC) {} + DstOp(MachineRegisterInfo::VRegAttrs Attrs) + : Attrs(Attrs), Ty(DstType::Ty_VRegAttrs) {} + DstOp(RegClassOrRegBank RCOrRB, LLT Ty) + : Attrs({RCOrRB, Ty}), Ty(DstType::Ty_VRegAttrs) {} void addDefToMIB(MachineRegisterInfo &MRI, MachineInstrBuilder &MIB) const { switch (Ty) { @@ -93,6 +98,9 @@ class DstOp { case DstType::Ty_RC: MIB.addDef(MRI.createVirtualRegister(RC)); break; + case DstType::Ty_VRegAttrs: + MIB.addDef(MRI.createVirtualRegister(Attrs)); + break; } } @@ -104,6 +112,8 @@ class DstOp { return LLTTy; case DstType::Ty_Reg: return MRI.getType(Reg); + case DstType::Ty_VRegAttrs: + return Attrs.Ty; } llvm_unreachable("Unrecognised DstOp::DstType enum"); } @@ -114,12 +124,13 @@ class DstOp { } const TargetRegisterClass *getRegClass() const { - switch (Ty) { - case DstType::Ty_RC: - return RC; - default: - llvm_unreachable("Not a RC Operand"); - } + assert(Ty == DstType::Ty_RC && "Not a RC Operand"); + return RC; + } + + MachineRegisterInfo::VRegAttrs getVRegAttrs() const { + assert(Ty == DstType::Ty_VRegAttrs && "Not a VRegAttrs Operand"); + return Attrs; } DstType getDstOpKind() const { return Ty; } @@ -1255,7 +1266,8 @@ class MachineIRBuilder { /// /// \return a MachineInstrBuilder for the newly created instruction. MachineInstrBuilder buildICmp(CmpInst::Predicate Pred, const DstOp &Res, - const SrcOp &Op0, const SrcOp &Op1); + const SrcOp &Op0, const SrcOp &Op1, + std::optional Flags = std::nullopt); /// Build and insert a \p Res = G_FCMP \p Pred\p Op0, \p Op1 /// diff --git a/llvm/include/llvm/CodeGen/GlobalISel/Utils.h b/llvm/include/llvm/CodeGen/GlobalISel/Utils.h index 95a8234d3c6080..4016247376c4f6 100644 --- a/llvm/include/llvm/CodeGen/GlobalISel/Utils.h +++ b/llvm/include/llvm/CodeGen/GlobalISel/Utils.h @@ -542,10 +542,6 @@ bool isConstFalseVal(const TargetLowering &TLI, int64_t Val, bool IsVector, /// TargetBooleanContents. int64_t getICmpTrueVal(const TargetLowering &TLI, bool IsVector, bool IsFP); -/// Returns true if the given block should be optimized for size. -bool shouldOptForSize(const MachineBasicBlock &MBB, ProfileSummaryInfo *PSI, - BlockFrequencyInfo *BFI); - using SmallInstListTy = GISelWorkList<4>; void saveUsesAndErase(MachineInstr &MI, MachineRegisterInfo &MRI, LostDebugLocObserver *LocObserver, diff --git a/llvm/include/llvm/CodeGen/MachineInstr.h b/llvm/include/llvm/CodeGen/MachineInstr.h index 76a7b8662bae66..ead6bbe1d5f641 100644 --- a/llvm/include/llvm/CodeGen/MachineInstr.h +++ b/llvm/include/llvm/CodeGen/MachineInstr.h @@ -119,6 +119,7 @@ class MachineInstr Disjoint = 1 << 19, // Each bit is zero in at least one of the inputs. NoUSWrap = 1 << 20, // Instruction supports geps // no unsigned signed wrap. + SameSign = 1 << 21 // Both operands have the same sign. }; private: @@ -1764,8 +1765,8 @@ class MachineInstr bool isDereferenceableInvariantLoad() const; /// If the specified instruction is a PHI that always merges together the - /// same virtual register, return the register, otherwise return 0. - unsigned isConstantValuePHI() const; + /// same virtual register, return the register, otherwise return Register(). + Register isConstantValuePHI() const; /// Return true if this instruction has side effects that are not modeled /// by mayLoad / mayStore, etc. diff --git a/llvm/include/llvm/CodeGen/MachineRegisterInfo.h b/llvm/include/llvm/CodeGen/MachineRegisterInfo.h index 7a2c23c13a3ce6..5dc51aaed81c7b 100644 --- a/llvm/include/llvm/CodeGen/MachineRegisterInfo.h +++ b/llvm/include/llvm/CodeGen/MachineRegisterInfo.h @@ -754,7 +754,7 @@ class MachineRegisterInfo { /// Returns register class or bank and low level type of \p Reg. Always safe /// to use. Special values are returned when \p Reg does not have some of the /// attributes. - VRegAttrs getVRegAttrs(Register Reg) { + VRegAttrs getVRegAttrs(Register Reg) const { return {getRegClassOrRegBank(Reg), getType(Reg)}; } diff --git a/llvm/include/llvm/CodeGen/Passes.h b/llvm/include/llvm/CodeGen/Passes.h index e12c1f076f133c..d1c71fc95818c8 100644 --- a/llvm/include/llvm/CodeGen/Passes.h +++ b/llvm/include/llvm/CodeGen/Passes.h @@ -261,11 +261,11 @@ namespace llvm { /// TailDuplicate - Duplicate blocks with unconditional branches /// into tails of their predecessors. - extern char &TailDuplicateID; + extern char &TailDuplicateLegacyID; /// Duplicate blocks with unconditional branches into tails of their /// predecessors. Variant that works before register allocation. - extern char &EarlyTailDuplicateID; + extern char &EarlyTailDuplicateLegacyID; /// MachineTraceMetrics - This pass computes critical path and CPU resource /// usage in an ensemble of traces. diff --git a/llvm/include/llvm/CodeGen/SelectionDAGNodes.h b/llvm/include/llvm/CodeGen/SelectionDAGNodes.h index bda0120a2df4aa..26488413fe5826 100644 --- a/llvm/include/llvm/CodeGen/SelectionDAGNodes.h +++ b/llvm/include/llvm/CodeGen/SelectionDAGNodes.h @@ -378,36 +378,48 @@ template<> struct simplify_type { /// the backend. struct SDNodeFlags { private: - bool NoUnsignedWrap : 1; - bool NoSignedWrap : 1; - bool Exact : 1; - bool Disjoint : 1; - bool NonNeg : 1; - bool NoNaNs : 1; - bool NoInfs : 1; - bool NoSignedZeros : 1; - bool AllowReciprocal : 1; - bool AllowContract : 1; - bool ApproximateFuncs : 1; - bool AllowReassociation : 1; - - // We assume instructions do not raise floating-point exceptions by default, - // and only those marked explicitly may do so. We could choose to represent - // this via a positive "FPExcept" flags like on the MI level, but having a - // negative "NoFPExcept" flag here makes the flag intersection logic more - // straightforward. - bool NoFPExcept : 1; - // Instructions with attached 'unpredictable' metadata on IR level. - bool Unpredictable : 1; + friend class SDNode; + + unsigned Flags = 0; + + template void setFlag(bool B) { + Flags = (Flags & ~Flag) | (B ? Flag : 0); + } public: + enum : unsigned { + None = 0, + NoUnsignedWrap = 1 << 0, + NoSignedWrap = 1 << 1, + Exact = 1 << 2, + Disjoint = 1 << 3, + NonNeg = 1 << 4, + NoNaNs = 1 << 5, + NoInfs = 1 << 6, + NoSignedZeros = 1 << 7, + AllowReciprocal = 1 << 8, + AllowContract = 1 << 9, + ApproximateFuncs = 1 << 10, + AllowReassociation = 1 << 11, + + // We assume instructions do not raise floating-point exceptions by default, + // and only those marked explicitly may do so. We could choose to represent + // this via a positive "FPExcept" flags like on the MI level, but having a + // negative "NoFPExcept" flag here makes the flag intersection logic more + // straightforward. + NoFPExcept = 1 << 12, + // Instructions with attached 'unpredictable' metadata on IR level. + Unpredictable = 1 << 13, + + // NOTE: Please update LargestValue in LLVM_DECLARE_ENUM_AS_BITMASK below + // the class definition when adding new flags. + + PoisonGeneratingFlags = NoUnsignedWrap | NoSignedWrap | Exact | Disjoint | + NonNeg | NoNaNs | NoInfs, + }; + /// Default constructor turns off all optimization flags. - SDNodeFlags() - : NoUnsignedWrap(false), NoSignedWrap(false), Exact(false), - Disjoint(false), NonNeg(false), NoNaNs(false), NoInfs(false), - NoSignedZeros(false), AllowReciprocal(false), AllowContract(false), - ApproximateFuncs(false), AllowReassociation(false), NoFPExcept(false), - Unpredictable(false) {} + SDNodeFlags() : Flags(0) {} /// Propagate the fast-math-flags from an IR FPMathOperator. void copyFMF(const FPMathOperator &FPMO) { @@ -421,71 +433,49 @@ struct SDNodeFlags { } // These are mutators for each flag. - void setNoUnsignedWrap(bool b) { NoUnsignedWrap = b; } - void setNoSignedWrap(bool b) { NoSignedWrap = b; } - void setExact(bool b) { Exact = b; } - void setDisjoint(bool b) { Disjoint = b; } - void setNonNeg(bool b) { NonNeg = b; } - void setNoNaNs(bool b) { NoNaNs = b; } - void setNoInfs(bool b) { NoInfs = b; } - void setNoSignedZeros(bool b) { NoSignedZeros = b; } - void setAllowReciprocal(bool b) { AllowReciprocal = b; } - void setAllowContract(bool b) { AllowContract = b; } - void setApproximateFuncs(bool b) { ApproximateFuncs = b; } - void setAllowReassociation(bool b) { AllowReassociation = b; } - void setNoFPExcept(bool b) { NoFPExcept = b; } - void setUnpredictable(bool b) { Unpredictable = b; } + void setNoUnsignedWrap(bool b) { setFlag(b); } + void setNoSignedWrap(bool b) { setFlag(b); } + void setExact(bool b) { setFlag(b); } + void setDisjoint(bool b) { setFlag(b); } + void setNonNeg(bool b) { setFlag(b); } + void setNoNaNs(bool b) { setFlag(b); } + void setNoInfs(bool b) { setFlag(b); } + void setNoSignedZeros(bool b) { setFlag(b); } + void setAllowReciprocal(bool b) { setFlag(b); } + void setAllowContract(bool b) { setFlag(b); } + void setApproximateFuncs(bool b) { setFlag(b); } + void setAllowReassociation(bool b) { setFlag(b); } + void setNoFPExcept(bool b) { setFlag(b); } + void setUnpredictable(bool b) { setFlag(b); } // These are accessors for each flag. - bool hasNoUnsignedWrap() const { return NoUnsignedWrap; } - bool hasNoSignedWrap() const { return NoSignedWrap; } - bool hasExact() const { return Exact; } - bool hasDisjoint() const { return Disjoint; } - bool hasNonNeg() const { return NonNeg; } - bool hasNoNaNs() const { return NoNaNs; } - bool hasNoInfs() const { return NoInfs; } - bool hasNoSignedZeros() const { return NoSignedZeros; } - bool hasAllowReciprocal() const { return AllowReciprocal; } - bool hasAllowContract() const { return AllowContract; } - bool hasApproximateFuncs() const { return ApproximateFuncs; } - bool hasAllowReassociation() const { return AllowReassociation; } - bool hasNoFPExcept() const { return NoFPExcept; } - bool hasUnpredictable() const { return Unpredictable; } + bool hasNoUnsignedWrap() const { return Flags & NoUnsignedWrap; } + bool hasNoSignedWrap() const { return Flags & NoSignedWrap; } + bool hasExact() const { return Flags & Exact; } + bool hasDisjoint() const { return Flags & Disjoint; } + bool hasNonNeg() const { return Flags & NonNeg; } + bool hasNoNaNs() const { return Flags & NoNaNs; } + bool hasNoInfs() const { return Flags & NoInfs; } + bool hasNoSignedZeros() const { return Flags & NoSignedZeros; } + bool hasAllowReciprocal() const { return Flags & AllowReciprocal; } + bool hasAllowContract() const { return Flags & AllowContract; } + bool hasApproximateFuncs() const { return Flags & ApproximateFuncs; } + bool hasAllowReassociation() const { return Flags & AllowReassociation; } + bool hasNoFPExcept() const { return Flags & NoFPExcept; } + bool hasUnpredictable() const { return Flags & Unpredictable; } bool operator==(const SDNodeFlags &Other) const { - return NoUnsignedWrap == Other.NoUnsignedWrap && - NoSignedWrap == Other.NoSignedWrap && Exact == Other.Exact && - Disjoint == Other.Disjoint && NonNeg == Other.NonNeg && - NoNaNs == Other.NoNaNs && NoInfs == Other.NoInfs && - NoSignedZeros == Other.NoSignedZeros && - AllowReciprocal == Other.AllowReciprocal && - AllowContract == Other.AllowContract && - ApproximateFuncs == Other.ApproximateFuncs && - AllowReassociation == Other.AllowReassociation && - NoFPExcept == Other.NoFPExcept && - Unpredictable == Other.Unpredictable; + return Flags == Other.Flags; } /// Clear any flags in this flag set that aren't also set in Flags. All /// flags will be cleared if Flags are undefined. - void intersectWith(const SDNodeFlags Flags) { - NoUnsignedWrap &= Flags.NoUnsignedWrap; - NoSignedWrap &= Flags.NoSignedWrap; - Exact &= Flags.Exact; - Disjoint &= Flags.Disjoint; - NonNeg &= Flags.NonNeg; - NoNaNs &= Flags.NoNaNs; - NoInfs &= Flags.NoInfs; - NoSignedZeros &= Flags.NoSignedZeros; - AllowReciprocal &= Flags.AllowReciprocal; - AllowContract &= Flags.AllowContract; - ApproximateFuncs &= Flags.ApproximateFuncs; - AllowReassociation &= Flags.AllowReassociation; - NoFPExcept &= Flags.NoFPExcept; - Unpredictable &= Flags.Unpredictable; - } + void intersectWith(const SDNodeFlags Flags) { this->Flags &= Flags.Flags; } }; +LLVM_DECLARE_ENUM_AS_BITMASK(decltype(SDNodeFlags::None), + SDNodeFlags::Unpredictable); + /// Represents one node in the SelectionDAG. /// class SDNode : public FoldingSetNode, public ilist_node { @@ -1029,10 +1019,7 @@ END_TWO_BYTE_PACK() void intersectFlagsWith(const SDNodeFlags Flags); bool hasPoisonGeneratingFlags() const { - SDNodeFlags Flags = getFlags(); - return Flags.hasNoUnsignedWrap() || Flags.hasNoSignedWrap() || - Flags.hasExact() || Flags.hasDisjoint() || Flags.hasNonNeg() || - Flags.hasNoNaNs() || Flags.hasNoInfs(); + return Flags.Flags & SDNodeFlags::PoisonGeneratingFlags; } void setCFIType(uint32_t Type) { CFIType = Type; } diff --git a/llvm/include/llvm/CodeGen/TailDuplication.h b/llvm/include/llvm/CodeGen/TailDuplication.h new file mode 100644 index 00000000000000..687a592ccf2fbf --- /dev/null +++ b/llvm/include/llvm/CodeGen/TailDuplication.h @@ -0,0 +1,47 @@ +//===- llvm/CodeGen/TailDuplication.h ---------------------------*- C++ -*-===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +#ifndef LLVM_CODEGEN_TAILDUPLICATIONPASS_H +#define LLVM_CODEGEN_TAILDUPLICATIONPASS_H + +#include "llvm/CodeGen/MBFIWrapper.h" +#include "llvm/CodeGen/MachineFunction.h" +#include "llvm/CodeGen/MachinePassManager.h" + +namespace llvm { + +template +class TailDuplicatePassBase : public PassInfoMixin { +private: + std::unique_ptr MBFIW; + +public: + PreservedAnalyses run(MachineFunction &MF, + MachineFunctionAnalysisManager &MFAM); +}; + +class EarlyTailDuplicatePass + : public TailDuplicatePassBase { +public: + MachineFunctionProperties getClearedProperties() const { + return MachineFunctionProperties().set( + MachineFunctionProperties::Property::NoPHIs); + } +}; + +class TailDuplicatePass + : public TailDuplicatePassBase {}; + +} // namespace llvm + +extern template class llvm::TailDuplicatePassBase; +extern template class llvm::TailDuplicatePassBase; + +#endif // LLVM_CODEGEN_TAILDUPLICATIONPASS_H diff --git a/llvm/include/llvm/CodeGen/ValueTypes.h b/llvm/include/llvm/CodeGen/ValueTypes.h index 3db6f33a8093f0..4de109739227ad 100644 --- a/llvm/include/llvm/CodeGen/ValueTypes.h +++ b/llvm/include/llvm/CodeGen/ValueTypes.h @@ -230,7 +230,8 @@ namespace llvm { /// Return true if this is an overloaded type for TableGen. bool isOverloaded() const { - return (V==MVT::iAny || V==MVT::fAny || V==MVT::vAny || V==MVT::iPTRAny); + return (V == MVT::iAny || V == MVT::fAny || V == MVT::vAny || + V == MVT::pAny); } /// Return true if the bit size is a multiple of 8. diff --git a/llvm/include/llvm/CodeGen/ValueTypes.td b/llvm/include/llvm/CodeGen/ValueTypes.td index 493c0cfcab60ce..6d6b92958b4321 100644 --- a/llvm/include/llvm/CodeGen/ValueTypes.td +++ b/llvm/include/llvm/CodeGen/ValueTypes.td @@ -338,9 +338,9 @@ def MetadataVT : ValueType<0, 505> { // Metadata let LLVMName = "Metadata"; } -// Pseudo valuetype mapped to the current pointer size to any address space. +// Pseudo valuetype to represent "pointer to any address space" // Should only be used in TableGen. -def iPTRAny : VTAny<506>; +def pAny : VTAny<506>; // Pseudo valuetype to represent "vector of any size" // Should only be used in TableGen. diff --git a/llvm/include/llvm/CodeGenTypes/MachineValueType.h b/llvm/include/llvm/CodeGenTypes/MachineValueType.h index c9a5098ef1623e..5c47ad4824a791 100644 --- a/llvm/include/llvm/CodeGenTypes/MachineValueType.h +++ b/llvm/include/llvm/CodeGenTypes/MachineValueType.h @@ -320,7 +320,7 @@ namespace llvm { llvm_unreachable("Value type is non-standard value, Other."); case iPTR: llvm_unreachable("Value type size is target-dependent. Ask TLI."); - case iPTRAny: + case pAny: case iAny: case fAny: case vAny: diff --git a/llvm/include/llvm/ExecutionEngine/Orc/RedirectionManager.h b/llvm/include/llvm/ExecutionEngine/Orc/RedirectionManager.h index 4004c42d914684..f2ea1f5b64c533 100644 --- a/llvm/include/llvm/ExecutionEngine/Orc/RedirectionManager.h +++ b/llvm/include/llvm/ExecutionEngine/Orc/RedirectionManager.h @@ -32,8 +32,8 @@ class RedirectionManager { /// Change the redirection destination of given symbol to new destination /// symbol. - virtual Error redirect(JITDylib &JD, SymbolStringPtr Symbol, - ExecutorSymbolDef NewDest) { + Error redirect(JITDylib &JD, SymbolStringPtr Symbol, + ExecutorSymbolDef NewDest) { return redirect(JD, {{Symbol, NewDest}}); } diff --git a/llvm/include/llvm/Frontend/OpenMP/ClauseT.h b/llvm/include/llvm/Frontend/OpenMP/ClauseT.h index 2a890905dc6323..8ff15b51f1abdf 100644 --- a/llvm/include/llvm/Frontend/OpenMP/ClauseT.h +++ b/llvm/include/llvm/Frontend/OpenMP/ClauseT.h @@ -239,7 +239,8 @@ struct MapperT { ENUM(MemoryOrder, AcqRel, Acquire, Relaxed, Release, SeqCst); ENUM(MotionExpectation, Present); // V5.2: [15.9.1] `task-dependence-type` modifier -ENUM(TaskDependenceType, In, Out, Inout, Mutexinoutset, Inoutset, Depobj); +ENUM(TaskDependenceType, Depobj, In, Inout, Inoutset, Mutexinoutset, Out, Sink, + Source); template // struct LoopIterationT { diff --git a/llvm/include/llvm/Frontend/OpenMP/OMP.td b/llvm/include/llvm/Frontend/OpenMP/OMP.td index 70179bab475779..97496d4aae5ae2 100644 --- a/llvm/include/llvm/Frontend/OpenMP/OMP.td +++ b/llvm/include/llvm/Frontend/OpenMP/OMP.td @@ -130,6 +130,8 @@ def OMPC_Depobj : Clause<"depobj"> { } def OMPC_Destroy : Clause<"destroy"> { let clangClass = "OMPDestroyClause"; + let flangClass = "OmpDestroyClause"; + let isValueOptional = true; } def OMPC_Detach : Clause<"detach"> { let clangClass = "OMPDetachClause"; @@ -481,6 +483,7 @@ def OMPC_Untied : Clause<"untied"> { } def OMPC_Update : Clause<"update"> { let clangClass = "OMPUpdateClause"; + let flangClass = "OmpUpdateClause"; } def OMPC_Use : Clause<"use"> { let clangClass = "OMPUseClause"; diff --git a/llvm/include/llvm/IR/Intrinsics.h b/llvm/include/llvm/IR/Intrinsics.h index e893295e3272b9..89dfff256e0c43 100644 --- a/llvm/include/llvm/IR/Intrinsics.h +++ b/llvm/include/llvm/IR/Intrinsics.h @@ -92,7 +92,7 @@ namespace Intrinsic { /// return the existing declaration. /// /// The \p Tys parameter is for intrinsics with overloaded types (e.g., those - /// using iAny, fAny, vAny, or iPTRAny). For a declaration of an overloaded + /// using iAny, fAny, vAny, or pAny). For a declaration of an overloaded /// intrinsic, Tys must provide exactly one type for each overloaded type in /// the intrinsic. Function *getOrInsertDeclaration(Module *M, ID id, ArrayRef Tys = {}); diff --git a/llvm/include/llvm/IR/Intrinsics.td b/llvm/include/llvm/IR/Intrinsics.td index e91758ed34eb38..8ed57f818d6006 100644 --- a/llvm/include/llvm/IR/Intrinsics.td +++ b/llvm/include/llvm/IR/Intrinsics.td @@ -388,7 +388,7 @@ class LLVMAnyType : LLVMType { !eq(vt, iAny) : ArgKind.AnyInteger, !eq(vt, fAny) : ArgKind.AnyFloat, !eq(vt, vAny) : ArgKind.AnyVector, - !eq(vt, iPTRAny) : ArgKind.AnyPointer, + !eq(vt, pAny) : ArgKind.AnyPointer, ); let Sig = [ IIT_ARG.Number, @@ -412,8 +412,8 @@ class LLVMQualPointerType ]); } -class LLVMAnyPointerType : LLVMAnyType { - assert isAny, "iPTRAny should have isOverloaded"; +class LLVMAnyPointerType : LLVMAnyType { + assert isAny, "pAny should have isOverloaded"; } // Match the type of another intrinsic parameter. Number is an index into the diff --git a/llvm/include/llvm/IR/IntrinsicsDirectX.td b/llvm/include/llvm/IR/IntrinsicsDirectX.td index e30d37f69f781e..dada426368995d 100644 --- a/llvm/include/llvm/IR/IntrinsicsDirectX.td +++ b/llvm/include/llvm/IR/IntrinsicsDirectX.td @@ -92,4 +92,6 @@ def int_dx_step : DefaultAttrsIntrinsic<[LLVMMatchType<0>], [llvm_anyfloat_ty, L def int_dx_splitdouble : DefaultAttrsIntrinsic<[llvm_anyint_ty, LLVMMatchType<0>], [LLVMScalarOrSameVectorWidth<0, llvm_double_ty>], [IntrNoMem]>; def int_dx_radians : DefaultAttrsIntrinsic<[llvm_anyfloat_ty], [LLVMMatchType<0>], [IntrNoMem]>; + +def int_dx_group_memory_barrier_with_group_sync : DefaultAttrsIntrinsic<[], [], []>; } diff --git a/llvm/include/llvm/IR/IntrinsicsSPIRV.td b/llvm/include/llvm/IR/IntrinsicsSPIRV.td index 6df2eb156a0774..ddb47390537412 100644 --- a/llvm/include/llvm/IR/IntrinsicsSPIRV.td +++ b/llvm/include/llvm/IR/IntrinsicsSPIRV.td @@ -87,6 +87,7 @@ let TargetPrefix = "spv" in { def int_spv_wave_readlane : DefaultAttrsIntrinsic<[llvm_any_ty], [LLVMMatchType<0>, llvm_i32_ty], [IntrConvergent, IntrNoMem]>; def int_spv_sign : DefaultAttrsIntrinsic<[LLVMScalarOrSameVectorWidth<0, llvm_i32_ty>], [llvm_any_ty], [IntrNoMem]>; def int_spv_radians : DefaultAttrsIntrinsic<[LLVMMatchType<0>], [llvm_anyfloat_ty], [IntrNoMem]>; + def int_spv_group_memory_barrier_with_group_sync : DefaultAttrsIntrinsic<[], [], []>; // Create resource handle given the binding information. Returns a // type appropriate for the kind of resource given the set id, binding id, diff --git a/llvm/include/llvm/InitializePasses.h b/llvm/include/llvm/InitializePasses.h index 26f5d63553c5a8..54c070401ec8a4 100644 --- a/llvm/include/llvm/InitializePasses.h +++ b/llvm/include/llvm/InitializePasses.h @@ -101,7 +101,7 @@ void initializeEarlyCSEMemSSALegacyPassPass(PassRegistry &); void initializeEarlyIfConverterLegacyPass(PassRegistry &); void initializeEarlyIfPredicatorPass(PassRegistry &); void initializeEarlyMachineLICMPass(PassRegistry &); -void initializeEarlyTailDuplicatePass(PassRegistry &); +void initializeEarlyTailDuplicateLegacyPass(PassRegistry &); void initializeEdgeBundlesPass(PassRegistry &); void initializeEHContGuardCatchretPass(PassRegistry &); void initializeExpandLargeFpConvertLegacyPassPass(PassRegistry &); @@ -300,7 +300,7 @@ void initializeStraightLineStrengthReduceLegacyPassPass(PassRegistry &); void initializeStripDebugMachineModulePass(PassRegistry &); void initializeStructurizeCFGLegacyPassPass(PassRegistry &); void initializeTailCallElimPass(PassRegistry &); -void initializeTailDuplicatePass(PassRegistry &); +void initializeTailDuplicateLegacyPass(PassRegistry &); void initializeTargetLibraryInfoWrapperPassPass(PassRegistry &); void initializeTargetPassConfigPass(PassRegistry &); void initializeTargetTransformInfoWrapperPassPass(PassRegistry &); diff --git a/llvm/include/llvm/MC/MCInstPrinter.h b/llvm/include/llvm/MC/MCInstPrinter.h index 60a901e3d0deae..e825c04a6dba6f 100644 --- a/llvm/include/llvm/MC/MCInstPrinter.h +++ b/llvm/include/llvm/MC/MCInstPrinter.h @@ -9,8 +9,10 @@ #ifndef LLVM_MC_MCINSTPRINTER_H #define LLVM_MC_MCINSTPRINTER_H +#include "llvm/ADT/SmallVector.h" #include "llvm/Support/Compiler.h" #include "llvm/Support/Format.h" +#include "llvm/Support/raw_ostream.h" #include namespace llvm { @@ -24,7 +26,6 @@ class MCRegister; class MCRegisterInfo; class MCSubtargetInfo; class StringRef; -class raw_ostream; /// Convert `Bytes' to a hex string and output to `OS' void dumpBytes(ArrayRef Bytes, raw_ostream &OS); @@ -76,6 +77,8 @@ class MCInstPrinter { /// If true, symbolize branch target and memory reference operands. bool SymbolizeOperands = false; + SmallVector ColorStack{raw_ostream::Colors::RESET}; + /// Utility function for printing annotations. void printAnnotation(raw_ostream &OS, StringRef Annot); @@ -98,8 +101,8 @@ class MCInstPrinter { class WithMarkup { public: - LLVM_CTOR_NODISCARD WithMarkup(raw_ostream &OS, Markup M, bool EnableMarkup, - bool EnableColor); + LLVM_CTOR_NODISCARD WithMarkup(MCInstPrinter &IP, raw_ostream &OS, Markup M, + bool EnableMarkup, bool EnableColor); ~WithMarkup(); template WithMarkup &operator<<(T &O) { @@ -113,6 +116,7 @@ class MCInstPrinter { } private: + MCInstPrinter &IP; raw_ostream &OS; bool EnableMarkup; bool EnableColor; @@ -144,7 +148,7 @@ class MCInstPrinter { StringRef getOpcodeName(unsigned Opcode) const; /// Print the assembler register name. - virtual void printRegName(raw_ostream &OS, MCRegister Reg) const; + virtual void printRegName(raw_ostream &OS, MCRegister Reg); bool getUseMarkup() const { return UseMarkup; } void setUseMarkup(bool Value) { UseMarkup = Value; } @@ -152,7 +156,7 @@ class MCInstPrinter { bool getUseColor() const { return UseColor; } void setUseColor(bool Value) { UseColor = Value; } - WithMarkup markup(raw_ostream &OS, Markup M) const; + WithMarkup markup(raw_ostream &OS, Markup M); bool getPrintImmHex() const { return PrintImmHex; } void setPrintImmHex(bool Value) { PrintImmHex = Value; } diff --git a/llvm/include/llvm/MC/MCParser/MCAsmParser.h b/llvm/include/llvm/MC/MCParser/MCAsmParser.h index faa72d5f3144c4..70fba69778536e 100644 --- a/llvm/include/llvm/MC/MCParser/MCAsmParser.h +++ b/llvm/include/llvm/MC/MCParser/MCAsmParser.h @@ -206,7 +206,7 @@ class MCAsmParser { SmallVectorImpl> &OpDecls, SmallVectorImpl &Constraints, SmallVectorImpl &Clobbers, const MCInstrInfo *MII, - const MCInstPrinter *IP, MCAsmParserSemaCallback &SI) = 0; + MCInstPrinter *IP, MCAsmParserSemaCallback &SI) = 0; /// Emit a note at the location \p L, with the message \p Msg. virtual void Note(SMLoc L, const Twine &Msg, diff --git a/llvm/include/llvm/Passes/CodeGenPassBuilder.h b/llvm/include/llvm/Passes/CodeGenPassBuilder.h index ad80c661147d6f..9e95625fd1d881 100644 --- a/llvm/include/llvm/Passes/CodeGenPassBuilder.h +++ b/llvm/include/llvm/Passes/CodeGenPassBuilder.h @@ -60,6 +60,7 @@ #include "llvm/CodeGen/SjLjEHPrepare.h" #include "llvm/CodeGen/StackColoring.h" #include "llvm/CodeGen/StackProtector.h" +#include "llvm/CodeGen/TailDuplication.h" #include "llvm/CodeGen/TargetPassConfig.h" #include "llvm/CodeGen/TwoAddressInstructionPass.h" #include "llvm/CodeGen/UnreachableBlockElim.h" diff --git a/llvm/include/llvm/Passes/MachinePassRegistry.def b/llvm/include/llvm/Passes/MachinePassRegistry.def index 4f32a917738c13..9d12a120ff7ac6 100644 --- a/llvm/include/llvm/Passes/MachinePassRegistry.def +++ b/llvm/include/llvm/Passes/MachinePassRegistry.def @@ -133,6 +133,7 @@ MACHINE_FUNCTION_ANALYSIS("virtregmap", VirtRegMapAnalysis()) MACHINE_FUNCTION_PASS("dead-mi-elimination", DeadMachineInstructionElimPass()) MACHINE_FUNCTION_PASS("early-ifcvt", EarlyIfConverterPass()) MACHINE_FUNCTION_PASS("early-machinelicm", EarlyMachineLICMPass()) +MACHINE_FUNCTION_PASS("early-tailduplication", EarlyTailDuplicatePass()) MACHINE_FUNCTION_PASS("finalize-isel", FinalizeISelPass()) MACHINE_FUNCTION_PASS("localstackalloc", LocalStackSlotAllocationPass()) MACHINE_FUNCTION_PASS("machine-cse", MachineCSEPass()) @@ -157,6 +158,7 @@ MACHINE_FUNCTION_PASS("print", VirtRegMapPrinterPass(dbgs())) MACHINE_FUNCTION_PASS("require-all-machine-function-properties", RequireAllMachineFunctionPropertiesPass()) MACHINE_FUNCTION_PASS("stack-coloring", StackColoringPass()) +MACHINE_FUNCTION_PASS("tailduplication", TailDuplicatePass()) MACHINE_FUNCTION_PASS("trigger-verifier-error", TriggerVerifierErrorPass()) MACHINE_FUNCTION_PASS("two-address-instruction", TwoAddressInstructionPass()) MACHINE_FUNCTION_PASS("verify", MachineVerifierPass()) @@ -210,7 +212,6 @@ DUMMY_MACHINE_FUNCTION_PASS("cfi-fixup", CFIFixupPass) DUMMY_MACHINE_FUNCTION_PASS("cfi-instr-inserter", CFIInstrInserterPass) DUMMY_MACHINE_FUNCTION_PASS("detect-dead-lanes", DetectDeadLanesPass) DUMMY_MACHINE_FUNCTION_PASS("dot-machine-cfg", MachineCFGPrinter) -DUMMY_MACHINE_FUNCTION_PASS("early-tailduplication", EarlyTailDuplicatePass) DUMMY_MACHINE_FUNCTION_PASS("fentry-insert", FEntryInserterPass) DUMMY_MACHINE_FUNCTION_PASS("fixup-statepoint-caller-saved", FixupStatepointCallerSavedPass) DUMMY_MACHINE_FUNCTION_PASS("fs-profile-loader", MIRProfileLoaderNewPass) @@ -262,7 +263,6 @@ DUMMY_MACHINE_FUNCTION_PASS("simple-register-coalescing", RegisterCoalescerPass) DUMMY_MACHINE_FUNCTION_PASS("stack-frame-layout", StackFrameLayoutAnalysisPass) DUMMY_MACHINE_FUNCTION_PASS("stack-slot-coloring", StackSlotColoringPass) DUMMY_MACHINE_FUNCTION_PASS("stackmap-liveness", StackMapLivenessPass) -DUMMY_MACHINE_FUNCTION_PASS("tailduplication", TailDuplicatePass) DUMMY_MACHINE_FUNCTION_PASS("unpack-mi-bundles", UnpackMachineBundlesPass) DUMMY_MACHINE_FUNCTION_PASS("virtregrewriter", VirtRegRewriterPass) DUMMY_MACHINE_FUNCTION_PASS("xray-instrumentation", XRayInstrumentationPass) diff --git a/llvm/include/llvm/ProfileData/InstrProfWriter.h b/llvm/include/llvm/ProfileData/InstrProfWriter.h index b8b6c684717b05..559549b0a22cc9 100644 --- a/llvm/include/llvm/ProfileData/InstrProfWriter.h +++ b/llvm/include/llvm/ProfileData/InstrProfWriter.h @@ -78,12 +78,20 @@ class InstrProfWriter { // Whether to serialize the full schema. bool MemProfFullSchema; + // Whether to generated random memprof hotness for testing. + bool MemprofGenerateRandomHotness; + public: + // For memprof testing, random hotness can be assigned to the contexts if + // MemprofGenerateRandomHotness is enabled. The random seed can be either + // provided by MemprofGenerateRandomHotnessSeed, or if that is 0, one will be + // generated in the writer using the current time. InstrProfWriter( bool Sparse = false, uint64_t TemporalProfTraceReservoirSize = 0, uint64_t MaxTemporalProfTraceLength = 0, bool WritePrevVersion = false, memprof::IndexedVersion MemProfVersionRequested = memprof::Version0, - bool MemProfFullSchema = false); + bool MemProfFullSchema = false, bool MemprofGenerateRandomHotness = false, + unsigned MemprofGenerateRandomHotnessSeed = 0); ~InstrProfWriter(); StringMap &getProfileData() { return FunctionData; } diff --git a/llvm/include/llvm/ProfileData/MemProf.h b/llvm/include/llvm/ProfileData/MemProf.h index f8121d35732518..da2cc807370095 100644 --- a/llvm/include/llvm/ProfileData/MemProf.h +++ b/llvm/include/llvm/ProfileData/MemProf.h @@ -147,6 +147,15 @@ struct PortableMemInfoBlock { return Name; \ } #include "llvm/ProfileData/MIBEntryDef.inc" +#undef MIBEntryDef + + // Define setters for each type which can be called by the writer. +#define MIBEntryDef(NameTag, Name, Type) \ + void set##Name(Type NewVal) { \ + assert(Schema[llvm::to_underlying(Meta::Name)]); \ + Name = NewVal; \ + } +#include "llvm/ProfileData/MIBEntryDef.inc" #undef MIBEntryDef void clear() { *this = PortableMemInfoBlock(); } diff --git a/llvm/include/llvm/SandboxIR/Context.h b/llvm/include/llvm/SandboxIR/Context.h index 1285598a1c0282..f2056de87cb946 100644 --- a/llvm/include/llvm/SandboxIR/Context.h +++ b/llvm/include/llvm/SandboxIR/Context.h @@ -9,18 +9,39 @@ #ifndef LLVM_SANDBOXIR_CONTEXT_H #define LLVM_SANDBOXIR_CONTEXT_H +#include "llvm/ADT/DenseMap.h" +#include "llvm/ADT/MapVector.h" +#include "llvm/ADT/SmallVector.h" #include "llvm/IR/LLVMContext.h" #include "llvm/SandboxIR/Tracker.h" #include "llvm/SandboxIR/Type.h" +#include + namespace llvm::sandboxir { -class Module; -class Value; class Argument; +class BBIterator; class Constant; +class Module; +class Value; class Context { +public: + // A EraseInstrCallback receives the instruction about to be erased. + using EraseInstrCallback = std::function; + // A CreateInstrCallback receives the instruction about to be created. + using CreateInstrCallback = std::function; + // A MoveInstrCallback receives the instruction about to be moved, the + // destination BB and an iterator pointing to the insertion position. + using MoveInstrCallback = + std::function; + + /// An ID for a registered callback. Used for deregistration. Using a 64-bit + /// integer so we don't have to worry about the unlikely case of overflowing + /// a 32-bit counter. + using CallbackID = uint64_t; + protected: LLVMContext &LLVMCtx; friend class Type; // For LLVMCtx. @@ -48,6 +69,21 @@ class Context { /// Type objects. DenseMap> LLVMTypeToTypeMap; + /// Callbacks called when an IR instruction is about to get erased. Keys are + /// used as IDs for deregistration. + MapVector EraseInstrCallbacks; + /// Callbacks called when an IR instruction is about to get created. Keys are + /// used as IDs for deregistration. + MapVector CreateInstrCallbacks; + /// Callbacks called when an IR instruction is about to get moved. Keys are + /// used as IDs for deregistration. + MapVector MoveInstrCallbacks; + + /// A counter used for assigning callback IDs during registration. The same + /// counter is used for all kinds of callbacks so we can detect mismatched + /// registration/deregistration. + CallbackID NextCallbackID = 0; + /// Remove \p V from the maps and returns the unique_ptr. std::unique_ptr detachLLVMValue(llvm::Value *V); /// Remove \p SBV from all SandboxIR maps and stop owning it. This effectively @@ -70,6 +106,10 @@ class Context { Constant *getOrCreateConstant(llvm::Constant *LLVMC); friend class Utils; // For getMemoryBase + void runEraseInstrCallbacks(Instruction *I); + void runCreateInstrCallbacks(Instruction *I); + void runMoveInstrCallbacks(Instruction *I, const BBIterator &Where); + // Friends for getOrCreateConstant(). #define DEF_CONST(ID, CLASS) friend class CLASS; #include "llvm/SandboxIR/Values.def" @@ -198,6 +238,28 @@ class Context { /// \Returns the number of values registered with Context. size_t getNumValues() const { return LLVMValueToValueMap.size(); } + + /// Register a callback that gets called when a SandboxIR instruction is about + /// to be removed from its parent. Note that this will also be called when + /// reverting the creation of an instruction. + /// \Returns a callback ID for later deregistration. + CallbackID registerEraseInstrCallback(EraseInstrCallback CB); + void unregisterEraseInstrCallback(CallbackID ID); + + /// Register a callback that gets called right after a SandboxIR instruction + /// is created. Note that this will also be called when reverting the removal + /// of an instruction. + /// \Returns a callback ID for later deregistration. + CallbackID registerCreateInstrCallback(CreateInstrCallback CB); + void unregisterCreateInstrCallback(CallbackID ID); + + /// Register a callback that gets called when a SandboxIR instruction is about + /// to be moved. Note that this will also be called when reverting a move. + /// \Returns a callback ID for later deregistration. + CallbackID registerMoveInstrCallback(MoveInstrCallback CB); + void unregisterMoveInstrCallback(CallbackID ID); + + // TODO: Add callbacks for instructions inserted/removed if needed. }; } // namespace llvm::sandboxir diff --git a/llvm/include/llvm/TargetParser/AArch64CPUFeatures.inc b/llvm/include/llvm/TargetParser/AArch64CPUFeatures.inc index 902fa8f79ab816..e454524c9cb6a2 100644 --- a/llvm/include/llvm/TargetParser/AArch64CPUFeatures.inc +++ b/llvm/include/llvm/TargetParser/AArch64CPUFeatures.inc @@ -53,9 +53,9 @@ enum CPUFeatures { FEAT_EBF16, FEAT_RPRES, FEAT_SVE, - FEAT_SVE_BF16, - FEAT_SVE_EBF16, - FEAT_SVE_I8MM, + RESERVED_FEAT_SVE_BF16, // previously used and now ABI legacy + RESERVED_FEAT_SVE_EBF16, // previously used and now ABI legacy + RESERVED_FEAT_SVE_I8MM, // previously used and now ABI legacy FEAT_SVE_F32MM, FEAT_SVE_F64MM, FEAT_SVE2, diff --git a/llvm/include/llvm/Transforms/IPO/FunctionSpecialization.h b/llvm/include/llvm/Transforms/IPO/FunctionSpecialization.h index f20b01c186306d..e82155a6c72974 100644 --- a/llvm/include/llvm/Transforms/IPO/FunctionSpecialization.h +++ b/llvm/include/llvm/Transforms/IPO/FunctionSpecialization.h @@ -138,13 +138,16 @@ struct Spec { // Profitability of the specialization. unsigned Score; + // Number of instructions in the specialization. + unsigned CodeSize; + // List of call sites, matching this specialization. SmallVector CallSites; - Spec(Function *F, const SpecSig &S, unsigned Score) - : F(F), Sig(S), Score(Score) {} - Spec(Function *F, const SpecSig &&S, unsigned Score) - : F(F), Sig(S), Score(Score) {} + Spec(Function *F, const SpecSig &S, unsigned Score, unsigned CodeSize) + : F(F), Sig(S), Score(Score), CodeSize(CodeSize) {} + Spec(Function *F, const SpecSig &&S, unsigned Score, unsigned CodeSize) + : F(F), Sig(S), Score(Score), CodeSize(CodeSize) {} }; class InstCostVisitor : public InstVisitor { diff --git a/llvm/include/llvm/Transforms/Vectorize/SandboxVectorizer/Legality.h b/llvm/include/llvm/Transforms/Vectorize/SandboxVectorizer/Legality.h index 49dcec26dbc559..77ba5cd7f002e9 100644 --- a/llvm/include/llvm/Transforms/Vectorize/SandboxVectorizer/Legality.h +++ b/llvm/include/llvm/Transforms/Vectorize/SandboxVectorizer/Legality.h @@ -32,6 +32,7 @@ enum class ResultReason { DiffOpcodes, DiffTypes, DiffMathFlags, + DiffWrapFlags, }; #ifndef NDEBUG @@ -56,6 +57,8 @@ struct ToStr { return "DiffTypes"; case ResultReason::DiffMathFlags: return "DiffMathFlags"; + case ResultReason::DiffWrapFlags: + return "DiffWrapFlags"; } llvm_unreachable("Unknown ResultReason enum"); } diff --git a/llvm/lib/Analysis/StackSafetyAnalysis.cpp b/llvm/lib/Analysis/StackSafetyAnalysis.cpp index 27360d0e84cb2b..5d81658409dae8 100644 --- a/llvm/lib/Analysis/StackSafetyAnalysis.cpp +++ b/llvm/lib/Analysis/StackSafetyAnalysis.cpp @@ -528,7 +528,7 @@ void StackSafetyLocalAnalysis::analyzeAllUses(Value *Ptr, // dso_preemptable aliases or aliases with interposable linkage. const GlobalValue *Callee = dyn_cast(CB.getCalledOperand()->stripPointerCasts()); - if (!Callee) { + if (!Callee || isa(Callee)) { US.addRange(I, UnknownRange, /*IsSafe=*/false); break; } diff --git a/llvm/lib/AsmParser/LLLexer.cpp b/llvm/lib/AsmParser/LLLexer.cpp index 759db6db60774c..56abd03d623541 100644 --- a/llvm/lib/AsmParser/LLLexer.cpp +++ b/llvm/lib/AsmParser/LLLexer.cpp @@ -60,8 +60,8 @@ uint64_t LLLexer::atoull(const char *Buffer, const char *End) { uint64_t OldRes = Result; Result *= 10; Result += *Buffer-'0'; - if (Result < OldRes) { // Uh, oh, overflow detected!!! - LexError("constant bigger than 64 bits detected!"); + if (Result < OldRes) { // overflow detected. + LexError("constant bigger than 64 bits detected"); return 0; } } @@ -75,8 +75,8 @@ uint64_t LLLexer::HexIntToVal(const char *Buffer, const char *End) { Result *= 16; Result += hexDigitValue(*Buffer); - if (Result < OldRes) { // Uh, oh, overflow detected!!! - LexError("constant bigger than 64 bits detected!"); + if (Result < OldRes) { // overflow detected. + LexError("constant bigger than 64 bits detected"); return 0; } } @@ -99,7 +99,7 @@ void LLLexer::HexToIntPair(const char *Buffer, const char *End, Pair[1] += hexDigitValue(*Buffer); } if (Buffer != End) - LexError("constant bigger than 128 bits detected!"); + LexError("constant bigger than 128 bits detected"); } /// FP80HexToIntPair - translate an 80 bit FP80 number (20 hexits) into @@ -118,7 +118,7 @@ void LLLexer::FP80HexToIntPair(const char *Buffer, const char *End, Pair[0] += hexDigitValue(*Buffer); } if (Buffer != End) - LexError("constant bigger than 128 bits detected!"); + LexError("constant bigger than 128 bits detected"); } // UnEscapeLexed - Run through the specified buffer and change \xx codes to the @@ -292,7 +292,7 @@ lltok::Kind LLLexer::LexDollar() { StrVal.assign(TokStart + 2, CurPtr - 1); UnEscapeLexed(StrVal); if (StringRef(StrVal).contains(0)) { - LexError("Null bytes are not allowed in names"); + LexError("NUL character is not allowed in names"); return lltok::Error; } return lltok::ComdatVar; @@ -354,7 +354,7 @@ lltok::Kind LLLexer::LexUIntID(lltok::Kind Token) { uint64_t Val = atoull(TokStart + 1, CurPtr); if ((unsigned)Val != Val) - LexError("invalid value number (too large)!"); + LexError("invalid value number (too large)"); UIntVal = unsigned(Val); return Token; } @@ -375,7 +375,7 @@ lltok::Kind LLLexer::LexVar(lltok::Kind Var, lltok::Kind VarID) { StrVal.assign(TokStart+2, CurPtr-1); UnEscapeLexed(StrVal); if (StringRef(StrVal).contains(0)) { - LexError("Null bytes are not allowed in names"); + LexError("NUL character is not allowed in names"); return lltok::Error; } return Var; @@ -410,7 +410,7 @@ lltok::Kind LLLexer::LexQuote() { if (CurPtr[0] == ':') { ++CurPtr; if (StringRef(StrVal).contains(0)) { - LexError("Null bytes are not allowed in names"); + LexError("NUL character is not allowed in names"); kind = lltok::Error; } else { kind = lltok::LabelStr; @@ -492,7 +492,7 @@ lltok::Kind LLLexer::LexIdentifier() { uint64_t NumBits = atoull(StartChar, CurPtr); if (NumBits < IntegerType::MIN_INT_BITS || NumBits > IntegerType::MAX_INT_BITS) { - LexError("bitwidth for integer type out of range!"); + LexError("bitwidth for integer type out of range"); return lltok::Error; } TyVal = IntegerType::get(Context, NumBits); @@ -1122,7 +1122,7 @@ lltok::Kind LLLexer::LexDigitOrNegative() { uint64_t Val = atoull(TokStart, CurPtr); ++CurPtr; // Skip the colon. if ((unsigned)Val != Val) - LexError("invalid value number (too large)!"); + LexError("invalid value number (too large)"); UIntVal = unsigned(Val); return lltok::LabelID; } diff --git a/llvm/lib/CodeGen/CodeGen.cpp b/llvm/lib/CodeGen/CodeGen.cpp index cf5c35fe81b4c7..39fba1d0b527ef 100644 --- a/llvm/lib/CodeGen/CodeGen.cpp +++ b/llvm/lib/CodeGen/CodeGen.cpp @@ -38,7 +38,7 @@ void llvm::initializeCodeGen(PassRegistry &Registry) { initializeEarlyIfConverterLegacyPass(Registry); initializeEarlyIfPredicatorPass(Registry); initializeEarlyMachineLICMPass(Registry); - initializeEarlyTailDuplicatePass(Registry); + initializeEarlyTailDuplicateLegacyPass(Registry); initializeExpandLargeDivRemLegacyPassPass(Registry); initializeExpandLargeFpConvertLegacyPassPass(Registry); initializeExpandMemCmpLegacyPassPass(Registry); @@ -131,7 +131,7 @@ void llvm::initializeCodeGen(PassRegistry &Registry) { initializeStackProtectorPass(Registry); initializeStackSlotColoringPass(Registry); initializeStripDebugMachineModulePass(Registry); - initializeTailDuplicatePass(Registry); + initializeTailDuplicateLegacyPass(Registry); initializeTargetPassConfigPass(Registry); initializeTwoAddressInstructionLegacyPassPass(Registry); initializeTypePromotionLegacyPass(Registry); diff --git a/llvm/lib/CodeGen/GlobalISel/CSEInfo.cpp b/llvm/lib/CodeGen/GlobalISel/CSEInfo.cpp index ca4d0986b4426c..cfb4ae85aa4f77 100644 --- a/llvm/lib/CodeGen/GlobalISel/CSEInfo.cpp +++ b/llvm/lib/CodeGen/GlobalISel/CSEInfo.cpp @@ -356,6 +356,20 @@ GISelInstProfileBuilder::addNodeIDRegType(const RegisterBank *RB) const { return *this; } +const GISelInstProfileBuilder &GISelInstProfileBuilder::addNodeIDRegType( + MachineRegisterInfo::VRegAttrs Attrs) const { + addNodeIDRegType(Attrs.Ty); + + const RegClassOrRegBank &RCOrRB = Attrs.RCOrRB; + if (RCOrRB) { + if (const auto *RB = dyn_cast_if_present(RCOrRB)) + addNodeIDRegType(RB); + else + addNodeIDRegType(cast(RCOrRB)); + } + return *this; +} + const GISelInstProfileBuilder & GISelInstProfileBuilder::addNodeIDImmediate(int64_t Imm) const { ID.AddInteger(Imm); @@ -389,17 +403,7 @@ GISelInstProfileBuilder::addNodeIDFlag(unsigned Flag) const { const GISelInstProfileBuilder & GISelInstProfileBuilder::addNodeIDReg(Register Reg) const { - LLT Ty = MRI.getType(Reg); - if (Ty.isValid()) - addNodeIDRegType(Ty); - - if (const RegClassOrRegBank &RCOrRB = MRI.getRegClassOrRegBank(Reg)) { - if (const auto *RB = dyn_cast_if_present(RCOrRB)) - addNodeIDRegType(RB); - else if (const auto *RC = - dyn_cast_if_present(RCOrRB)) - addNodeIDRegType(RC); - } + addNodeIDRegType(MRI.getVRegAttrs(Reg)); return *this; } diff --git a/llvm/lib/CodeGen/GlobalISel/CSEMIRBuilder.cpp b/llvm/lib/CodeGen/GlobalISel/CSEMIRBuilder.cpp index 547529bbe699ab..bf8e847011d7c1 100644 --- a/llvm/lib/CodeGen/GlobalISel/CSEMIRBuilder.cpp +++ b/llvm/lib/CodeGen/GlobalISel/CSEMIRBuilder.cpp @@ -73,18 +73,24 @@ bool CSEMIRBuilder::canPerformCSEForOpc(unsigned Opc) const { void CSEMIRBuilder::profileDstOp(const DstOp &Op, GISelInstProfileBuilder &B) const { switch (Op.getDstOpKind()) { - case DstOp::DstType::Ty_RC: + case DstOp::DstType::Ty_RC: { B.addNodeIDRegType(Op.getRegClass()); break; + } case DstOp::DstType::Ty_Reg: { // Regs can have LLT&(RB|RC). If those exist, profile them as well. B.addNodeIDReg(Op.getReg()); break; } - default: + case DstOp::DstType::Ty_LLT: { B.addNodeIDRegType(Op.getLLTTy(*getMRI())); break; } + case DstOp::DstType::Ty_VRegAttrs: { + B.addNodeIDRegType(Op.getVRegAttrs()); + break; + } + } } void CSEMIRBuilder::profileSrcOp(const SrcOp &Op, diff --git a/llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp b/llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp index 5381dce58f9e65..a87754389cc8ed 100644 --- a/llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp +++ b/llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp @@ -340,20 +340,17 @@ bool IRTranslator::translateCompare(const User &U, Register Op1 = getOrCreateVReg(*U.getOperand(1)); Register Res = getOrCreateVReg(U); CmpInst::Predicate Pred = CI->getPredicate(); + uint32_t Flags = MachineInstr::copyFlagsFromInstruction(*CI); if (CmpInst::isIntPredicate(Pred)) - MIRBuilder.buildICmp(Pred, Res, Op0, Op1); + MIRBuilder.buildICmp(Pred, Res, Op0, Op1, Flags); else if (Pred == CmpInst::FCMP_FALSE) MIRBuilder.buildCopy( Res, getOrCreateVReg(*Constant::getNullValue(U.getType()))); else if (Pred == CmpInst::FCMP_TRUE) MIRBuilder.buildCopy( Res, getOrCreateVReg(*Constant::getAllOnesValue(U.getType()))); - else { - uint32_t Flags = 0; - if (CI) - Flags = MachineInstr::copyFlagsFromInstruction(*CI); + else MIRBuilder.buildFCmp(Pred, Res, Op0, Op1, Flags); - } return true; } diff --git a/llvm/lib/CodeGen/GlobalISel/MachineIRBuilder.cpp b/llvm/lib/CodeGen/GlobalISel/MachineIRBuilder.cpp index 59f2fc633f5de7..15b9164247846c 100644 --- a/llvm/lib/CodeGen/GlobalISel/MachineIRBuilder.cpp +++ b/llvm/lib/CodeGen/GlobalISel/MachineIRBuilder.cpp @@ -898,8 +898,9 @@ MachineIRBuilder::buildFPTrunc(const DstOp &Res, const SrcOp &Op, MachineInstrBuilder MachineIRBuilder::buildICmp(CmpInst::Predicate Pred, const DstOp &Res, const SrcOp &Op0, - const SrcOp &Op1) { - return buildInstr(TargetOpcode::G_ICMP, Res, {Pred, Op0, Op1}); + const SrcOp &Op1, + std::optional Flags) { + return buildInstr(TargetOpcode::G_ICMP, Res, {Pred, Op0, Op1}, Flags); } MachineInstrBuilder MachineIRBuilder::buildFCmp(CmpInst::Predicate Pred, diff --git a/llvm/lib/CodeGen/GlobalISel/Utils.cpp b/llvm/lib/CodeGen/GlobalISel/Utils.cpp index 513a49b4fc2e4d..dcbbb0871a8445 100644 --- a/llvm/lib/CodeGen/GlobalISel/Utils.cpp +++ b/llvm/lib/CodeGen/GlobalISel/Utils.cpp @@ -1619,11 +1619,6 @@ int64_t llvm::getICmpTrueVal(const TargetLowering &TLI, bool IsVector, llvm_unreachable("Invalid boolean contents"); } -bool llvm::shouldOptForSize(const MachineBasicBlock &MBB, - ProfileSummaryInfo *PSI, BlockFrequencyInfo *BFI) { - return llvm::shouldOptimizeForSize(MBB.getBasicBlock(), PSI, BFI); -} - void llvm::saveUsesAndErase(MachineInstr &MI, MachineRegisterInfo &MRI, LostDebugLocObserver *LocObserver, SmallInstListTy &DeadInstChain) { diff --git a/llvm/lib/CodeGen/MIRParser/MILexer.cpp b/llvm/lib/CodeGen/MIRParser/MILexer.cpp index 5a3806ce57335a..1c450b05f49e93 100644 --- a/llvm/lib/CodeGen/MIRParser/MILexer.cpp +++ b/llvm/lib/CodeGen/MIRParser/MILexer.cpp @@ -216,6 +216,7 @@ static MIToken::TokenKind getIdentifierKind(StringRef Identifier) { .Case("exact", MIToken::kw_exact) .Case("nneg", MIToken::kw_nneg) .Case("disjoint", MIToken::kw_disjoint) + .Case("samesign", MIToken::kw_samesign) .Case("nofpexcept", MIToken::kw_nofpexcept) .Case("unpredictable", MIToken::kw_unpredictable) .Case("debug-location", MIToken::kw_debug_location) diff --git a/llvm/lib/CodeGen/MIRParser/MILexer.h b/llvm/lib/CodeGen/MIRParser/MILexer.h index 3931da3eaae1d3..d7cd06759cfbb8 100644 --- a/llvm/lib/CodeGen/MIRParser/MILexer.h +++ b/llvm/lib/CodeGen/MIRParser/MILexer.h @@ -77,6 +77,7 @@ struct MIToken { kw_unpredictable, kw_nneg, kw_disjoint, + kw_samesign, kw_debug_location, kw_debug_instr_number, kw_dbg_instr_ref, diff --git a/llvm/lib/CodeGen/MIRParser/MIParser.cpp b/llvm/lib/CodeGen/MIRParser/MIParser.cpp index 45847b5830da65..059814c70f828d 100644 --- a/llvm/lib/CodeGen/MIRParser/MIParser.cpp +++ b/llvm/lib/CodeGen/MIRParser/MIParser.cpp @@ -1476,7 +1476,8 @@ bool MIParser::parseInstruction(unsigned &OpCode, unsigned &Flags) { Token.is(MIToken::kw_noconvergent) || Token.is(MIToken::kw_unpredictable) || Token.is(MIToken::kw_nneg) || - Token.is(MIToken::kw_disjoint)) { + Token.is(MIToken::kw_disjoint) || + Token.is(MIToken::kw_samesign)) { // clang-format on // Mine frame and fast math flags if (Token.is(MIToken::kw_frame_setup)) @@ -1513,6 +1514,8 @@ bool MIParser::parseInstruction(unsigned &OpCode, unsigned &Flags) { Flags |= MachineInstr::NonNeg; if (Token.is(MIToken::kw_disjoint)) Flags |= MachineInstr::Disjoint; + if (Token.is(MIToken::kw_samesign)) + Flags |= MachineInstr::SameSign; lex(); } diff --git a/llvm/lib/CodeGen/MIRPrinter.cpp b/llvm/lib/CodeGen/MIRPrinter.cpp index a015cd3c2a55f9..658bbe0e577e5c 100644 --- a/llvm/lib/CodeGen/MIRPrinter.cpp +++ b/llvm/lib/CodeGen/MIRPrinter.cpp @@ -837,6 +837,8 @@ void MIPrinter::print(const MachineInstr &MI) { OS << "disjoint "; if (MI.getFlag(MachineInstr::NoUSWrap)) OS << "nusw "; + if (MI.getFlag(MachineInstr::SameSign)) + OS << "samesign "; OS << TII->getName(MI.getOpcode()); if (I < E) diff --git a/llvm/lib/CodeGen/MachineInstr.cpp b/llvm/lib/CodeGen/MachineInstr.cpp index 0d78c2cafbaf63..941861da5c5693 100644 --- a/llvm/lib/CodeGen/MachineInstr.cpp +++ b/llvm/lib/CodeGen/MachineInstr.cpp @@ -596,6 +596,11 @@ uint32_t MachineInstr::copyFlagsFromInstruction(const Instruction &I) { MIFlags |= MachineInstr::MIFlag::Disjoint; } + // Copy the samesign flag. + if (const ICmpInst *ICmp = dyn_cast(&I)) + if (ICmp->hasSameSign()) + MIFlags |= MachineInstr::MIFlag::SameSign; + // Copy the exact flag. if (const PossiblyExactOperator *PE = dyn_cast(&I)) if (PE->isExact()) @@ -1535,19 +1540,16 @@ bool MachineInstr::isDereferenceableInvariantLoad() const { return true; } -/// isConstantValuePHI - If the specified instruction is a PHI that always -/// merges together the same virtual register, return the register, otherwise -/// return 0. -unsigned MachineInstr::isConstantValuePHI() const { +Register MachineInstr::isConstantValuePHI() const { if (!isPHI()) - return 0; + return {}; assert(getNumOperands() >= 3 && "It's illegal to have a PHI without source operands"); Register Reg = getOperand(1).getReg(); for (unsigned i = 3, e = getNumOperands(); i < e; i += 2) if (getOperand(i).getReg() != Reg) - return 0; + return {}; return Reg; } @@ -1773,6 +1775,8 @@ void MachineInstr::print(raw_ostream &OS, ModuleSlotTracker &MST, OS << "nneg "; if (getFlag(MachineInstr::Disjoint)) OS << "disjoint "; + if (getFlag(MachineInstr::SameSign)) + OS << "samesign "; // Print the opcode name. if (TII) diff --git a/llvm/lib/CodeGen/MachineSSAUpdater.cpp b/llvm/lib/CodeGen/MachineSSAUpdater.cpp index c7a673b12d8c50..f0a136751bbffa 100644 --- a/llvm/lib/CodeGen/MachineSSAUpdater.cpp +++ b/llvm/lib/CodeGen/MachineSSAUpdater.cpp @@ -201,7 +201,7 @@ Register MachineSSAUpdater::GetValueInMiddleOfBlock(MachineBasicBlock *BB, // See if the PHI node can be merged to a single value. This can happen in // loop cases when we get a PHI of itself and one other value. - if (unsigned ConstVal = InsertedPHI->isConstantValuePHI()) { + if (Register ConstVal = InsertedPHI->isConstantValuePHI()) { InsertedPHI->eraseFromParent(); return ConstVal; } diff --git a/llvm/lib/CodeGen/MachineStripDebug.cpp b/llvm/lib/CodeGen/MachineStripDebug.cpp index 6128248a028e3e..ea291f64bff432 100644 --- a/llvm/lib/CodeGen/MachineStripDebug.cpp +++ b/llvm/lib/CodeGen/MachineStripDebug.cpp @@ -50,7 +50,7 @@ struct StripDebugMachineModule : public ModulePass { continue; MachineFunction &MF = *MaybeMF; for (MachineBasicBlock &MBB : MF) { - for (MachineInstr &MI : llvm::make_early_inc_range(MBB)) { + for (MachineInstr &MI : llvm::make_early_inc_range(MBB.instrs())) { if (MI.isDebugInstr()) { // FIXME: We should remove all of them. However, AArch64 emits an // invalid `DBG_VALUE $lr` with only one operand instead of diff --git a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp index b800204d917503..ceaf5d664131c3 100644 --- a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp +++ b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp @@ -7355,7 +7355,7 @@ SDValue DAGCombiner::visitAND(SDNode *N) { // Fold (and X, (bswap (not Y))) -> (and X, (not (bswap Y))) // Fold (and X, (bitreverse (not Y))) -> (and X, (not (bitreverse Y))) - SDValue X, Y, NotY; + SDValue X, Y, Z, NotY; for (unsigned Opc : {ISD::BSWAP, ISD::BITREVERSE}) if (sd_match(N, m_And(m_Value(X), m_OneUse(m_UnaryOp(Opc, m_Value(NotY))))) && @@ -7364,6 +7364,15 @@ SDValue DAGCombiner::visitAND(SDNode *N) { return DAG.getNode(ISD::AND, DL, VT, X, DAG.getNOT(DL, DAG.getNode(Opc, DL, VT, Y), VT)); + // Fold (and X, (rot (not Y), Z)) -> (and X, (not (rot Y, Z))) + for (unsigned Opc : {ISD::ROTL, ISD::ROTR}) + if (sd_match(N, m_And(m_Value(X), + m_OneUse(m_BinOp(Opc, m_Value(NotY), m_Value(Z))))) && + sd_match(NotY, m_Not(m_Value(Y))) && + (TLI.hasAndNot(SDValue(N, 0)) || NotY->hasOneUse())) + return DAG.getNode(ISD::AND, DL, VT, X, + DAG.getNOT(DL, DAG.getNode(Opc, DL, VT, Y, Z), VT)); + // Masking the negated extension of a boolean is just the zero-extended // boolean: // and (sub 0, zext(bool X)), 1 --> zext(bool X) diff --git a/llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp b/llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp index 47a9ae12248ccb..6ba12cfb8c5148 100644 --- a/llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp +++ b/llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp @@ -4375,6 +4375,9 @@ bool SelectionDAGLegalize::ExpandNode(SDNode *Node) { Results.push_back(DAG.getNode(ISD::FP_TO_SINT, dl, ResVT, RoundNode)); break; } + case ISD::ADDRSPACECAST: + Results.push_back(DAG.UnrollVectorOp(Node)); + break; case ISD::GLOBAL_OFFSET_TABLE: case ISD::GlobalAddress: case ISD::GlobalTLSAddress: diff --git a/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp b/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp index 8f255cce1fe15d..5403d787861d46 100644 --- a/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp +++ b/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp @@ -12590,6 +12590,14 @@ SDValue SelectionDAG::UnrollVectorOp(SDNode *N, unsigned ResNE) { Scalars.push_back(getNode(N->getOpcode(), dl, EltVT, Operands[0], getValueType(ExtVT))); + break; + } + case ISD::ADDRSPACECAST: { + const auto *ASC = cast(N); + Scalars.push_back(getAddrSpaceCast(dl, EltVT, Operands[0], + ASC->getSrcAddressSpace(), + ASC->getDestAddressSpace())); + break; } } } diff --git a/llvm/lib/CodeGen/TailDuplication.cpp b/llvm/lib/CodeGen/TailDuplication.cpp index 25f20d9c899bb0..b698ca675b65e2 100644 --- a/llvm/lib/CodeGen/TailDuplication.cpp +++ b/llvm/lib/CodeGen/TailDuplication.cpp @@ -12,13 +12,16 @@ // //===----------------------------------------------------------------------===// +#include "llvm/CodeGen/TailDuplication.h" #include "llvm/Analysis/ProfileSummaryInfo.h" #include "llvm/CodeGen/LazyMachineBlockFrequencyInfo.h" #include "llvm/CodeGen/MBFIWrapper.h" #include "llvm/CodeGen/MachineBranchProbabilityInfo.h" #include "llvm/CodeGen/MachineFunction.h" #include "llvm/CodeGen/MachineFunctionPass.h" +#include "llvm/CodeGen/MachinePassManager.h" #include "llvm/CodeGen/TailDuplicator.h" +#include "llvm/IR/Analysis.h" #include "llvm/InitializePasses.h" #include "llvm/Pass.h" #include "llvm/PassRegistry.h" @@ -29,13 +32,13 @@ using namespace llvm; namespace { -class TailDuplicateBase : public MachineFunctionPass { +class TailDuplicateBaseLegacy : public MachineFunctionPass { TailDuplicator Duplicator; std::unique_ptr MBFIW; bool PreRegAlloc; public: - TailDuplicateBase(char &PassID, bool PreRegAlloc) - : MachineFunctionPass(PassID), PreRegAlloc(PreRegAlloc) {} + TailDuplicateBaseLegacy(char &PassID, bool PreRegAlloc) + : MachineFunctionPass(PassID), PreRegAlloc(PreRegAlloc) {} bool runOnMachineFunction(MachineFunction &MF) override; @@ -47,19 +50,19 @@ class TailDuplicateBase : public MachineFunctionPass { } }; -class TailDuplicate : public TailDuplicateBase { +class TailDuplicateLegacy : public TailDuplicateBaseLegacy { public: static char ID; - TailDuplicate() : TailDuplicateBase(ID, false) { - initializeTailDuplicatePass(*PassRegistry::getPassRegistry()); + TailDuplicateLegacy() : TailDuplicateBaseLegacy(ID, false) { + initializeTailDuplicateLegacyPass(*PassRegistry::getPassRegistry()); } }; -class EarlyTailDuplicate : public TailDuplicateBase { +class EarlyTailDuplicateLegacy : public TailDuplicateBaseLegacy { public: static char ID; - EarlyTailDuplicate() : TailDuplicateBase(ID, true) { - initializeEarlyTailDuplicatePass(*PassRegistry::getPassRegistry()); + EarlyTailDuplicateLegacy() : TailDuplicateBaseLegacy(ID, true) { + initializeEarlyTailDuplicateLegacyPass(*PassRegistry::getPassRegistry()); } MachineFunctionProperties getClearedProperties() const override { @@ -70,17 +73,18 @@ class EarlyTailDuplicate : public TailDuplicateBase { } // end anonymous namespace -char TailDuplicate::ID; -char EarlyTailDuplicate::ID; +char TailDuplicateLegacy::ID; +char EarlyTailDuplicateLegacy::ID; -char &llvm::TailDuplicateID = TailDuplicate::ID; -char &llvm::EarlyTailDuplicateID = EarlyTailDuplicate::ID; +char &llvm::TailDuplicateLegacyID = TailDuplicateLegacy::ID; +char &llvm::EarlyTailDuplicateLegacyID = EarlyTailDuplicateLegacy::ID; -INITIALIZE_PASS(TailDuplicate, DEBUG_TYPE, "Tail Duplication", false, false) -INITIALIZE_PASS(EarlyTailDuplicate, "early-tailduplication", +INITIALIZE_PASS(TailDuplicateLegacy, DEBUG_TYPE, "Tail Duplication", false, + false) +INITIALIZE_PASS(EarlyTailDuplicateLegacy, "early-tailduplication", "Early Tail Duplication", false, false) -bool TailDuplicateBase::runOnMachineFunction(MachineFunction &MF) { +bool TailDuplicateBaseLegacy::runOnMachineFunction(MachineFunction &MF) { if (skipFunction(MF.getFunction())) return false; @@ -100,3 +104,36 @@ bool TailDuplicateBase::runOnMachineFunction(MachineFunction &MF) { return MadeChange; } + +template +PreservedAnalyses TailDuplicatePassBase::run( + MachineFunction &MF, MachineFunctionAnalysisManager &MFAM) { + MFPropsModifier _(static_cast(*this), MF); + + if (MF.getFunction().hasOptNone()) + return PreservedAnalyses::all(); + + auto *MBPI = &MFAM.getResult(MF); + auto *PSI = MFAM.getResult(MF) + .getCachedResult( + *MF.getFunction().getParent()); + auto *MBFI = (PSI && PSI->hasProfileSummary() + ? &MFAM.getResult(MF) + : nullptr); + if (MBFI) + MBFIW = std::make_unique(*MBFI); + + TailDuplicator Duplicator; + Duplicator.initMF(MF, PreRegAlloc, MBPI, MBFI ? MBFIW.get() : nullptr, PSI, + /*LayoutMode=*/false); + bool MadeChange = false; + while (Duplicator.tailDuplicateBlocks()) + MadeChange = true; + + if (!MadeChange) + return PreservedAnalyses::all(); + return getMachineFunctionPassPreservedAnalyses(); +} + +template class llvm::TailDuplicatePassBase; +template class llvm::TailDuplicatePassBase; diff --git a/llvm/lib/CodeGen/TargetPassConfig.cpp b/llvm/lib/CodeGen/TargetPassConfig.cpp index 12225c9946e9fc..aff74104006e5a 100644 --- a/llvm/lib/CodeGen/TargetPassConfig.cpp +++ b/llvm/lib/CodeGen/TargetPassConfig.cpp @@ -290,10 +290,10 @@ static IdentifyingPassPtr overridePass(AnalysisID StandardID, if (StandardID == &BranchFolderPassID) return applyDisable(TargetID, DisableBranchFold); - if (StandardID == &TailDuplicateID) + if (StandardID == &TailDuplicateLegacyID) return applyDisable(TargetID, DisableTailDuplicate); - if (StandardID == &EarlyTailDuplicateID) + if (StandardID == &EarlyTailDuplicateLegacyID) return applyDisable(TargetID, DisableEarlyTailDup); if (StandardID == &MachineBlockPlacementID) @@ -1279,7 +1279,7 @@ void TargetPassConfig::addMachinePasses() { /// Add passes that optimize machine instructions in SSA form. void TargetPassConfig::addMachineSSAOptimization() { // Pre-ra tail duplication. - addPass(&EarlyTailDuplicateID); + addPass(&EarlyTailDuplicateLegacyID); // Optimize PHIs before DCE: removing dead PHI cycles may make more // instructions dead. @@ -1507,7 +1507,7 @@ void TargetPassConfig::addMachineLateOptimization() { // performance for targets that require Structured Control Flow. // In addition it can also make CFG irreducible. Thus we disable it. if (!TM->requiresStructuredCFG()) - addPass(&TailDuplicateID); + addPass(&TailDuplicateLegacyID); // Copy propagation. addPass(&MachineCopyPropagationID); diff --git a/llvm/lib/ExecutionEngine/Orc/JITLinkRedirectableSymbolManager.cpp b/llvm/lib/ExecutionEngine/Orc/JITLinkRedirectableSymbolManager.cpp index 4ef217e6c562db..81294cad4d7d42 100644 --- a/llvm/lib/ExecutionEngine/Orc/JITLinkRedirectableSymbolManager.cpp +++ b/llvm/lib/ExecutionEngine/Orc/JITLinkRedirectableSymbolManager.cpp @@ -52,17 +52,18 @@ void JITLinkRedirectableSymbolManager::emitRedirectableSymbols( return; } + // FIXME: return stubs to the pool here too. if (auto Err = R->replace(absoluteSymbols(NewSymbolDefs))) { ES.reportError(std::move(Err)); R->failMaterialization(); return; } - auto Err = R->withResourceKeyDo([&](ResourceKey Key) { - TrackedResources[Key].insert(TrackedResources[Key].end(), Symbols.begin(), - Symbols.end()); - }); - if (Err) { + // FIXME: return stubs to the pool here too. + if (auto Err = R->withResourceKeyDo([&](ResourceKey Key) { + TrackedResources[Key].insert(TrackedResources[Key].end(), + Symbols.begin(), Symbols.end()); + })) { ES.reportError(std::move(Err)); R->failMaterialization(); return; diff --git a/llvm/lib/ExecutionEngine/Orc/ObjectLinkingLayer.cpp b/llvm/lib/ExecutionEngine/Orc/ObjectLinkingLayer.cpp index 25ab154a01d674..86c08cbdee5f32 100644 --- a/llvm/lib/ExecutionEngine/Orc/ObjectLinkingLayer.cpp +++ b/llvm/lib/ExecutionEngine/Orc/ObjectLinkingLayer.cpp @@ -701,16 +701,15 @@ Error ObjectLinkingLayer::handleRemoveResources(JITDylib &JD, ResourceKey K) { void ObjectLinkingLayer::handleTransferResources(JITDylib &JD, ResourceKey DstKey, ResourceKey SrcKey) { - auto I = Allocs.find(SrcKey); - if (I != Allocs.end()) { - auto &SrcAllocs = I->second; + if (Allocs.contains(SrcKey)) { + // DstKey may not be in the DenseMap yet, so the following line may resize + // the container and invalidate iterators and value references. auto &DstAllocs = Allocs[DstKey]; + auto &SrcAllocs = Allocs[SrcKey]; DstAllocs.reserve(DstAllocs.size() + SrcAllocs.size()); for (auto &Alloc : SrcAllocs) DstAllocs.push_back(std::move(Alloc)); - // Erase SrcKey entry using value rather than iterator I: I may have been - // invalidated when we looked up DstKey. Allocs.erase(SrcKey); } diff --git a/llvm/lib/ExecutionEngine/Orc/RTDyldObjectLinkingLayer.cpp b/llvm/lib/ExecutionEngine/Orc/RTDyldObjectLinkingLayer.cpp index bc3433d011551c..a73b2310d193aa 100644 --- a/llvm/lib/ExecutionEngine/Orc/RTDyldObjectLinkingLayer.cpp +++ b/llvm/lib/ExecutionEngine/Orc/RTDyldObjectLinkingLayer.cpp @@ -430,16 +430,15 @@ Error RTDyldObjectLinkingLayer::handleRemoveResources(JITDylib &JD, void RTDyldObjectLinkingLayer::handleTransferResources(JITDylib &JD, ResourceKey DstKey, ResourceKey SrcKey) { - auto I = MemMgrs.find(SrcKey); - if (I != MemMgrs.end()) { - auto &SrcMemMgrs = I->second; + if (MemMgrs.contains(SrcKey)) { + // DstKey may not be in the DenseMap yet, so the following line may resize + // the container and invalidate iterators and value references. auto &DstMemMgrs = MemMgrs[DstKey]; + auto &SrcMemMgrs = MemMgrs[SrcKey]; DstMemMgrs.reserve(DstMemMgrs.size() + SrcMemMgrs.size()); for (auto &MemMgr : SrcMemMgrs) DstMemMgrs.push_back(std::move(MemMgr)); - // Erase SrcKey entry using value rather than iterator I: I may have been - // invalidated when we looked up DstKey. MemMgrs.erase(SrcKey); } } diff --git a/llvm/lib/IR/Verifier.cpp b/llvm/lib/IR/Verifier.cpp index ee807ca13787d5..ffcab98db9aa02 100644 --- a/llvm/lib/IR/Verifier.cpp +++ b/llvm/lib/IR/Verifier.cpp @@ -4121,8 +4121,9 @@ void Verifier::visitGetElementPtrInst(GetElementPtrInst &GEP) { GetElementPtrInst::getIndexedType(GEP.getSourceElementType(), Idxs); Check(ElTy, "Invalid indices for GEP pointer type!", &GEP); - Check(GEP.getType()->isPtrOrPtrVectorTy() && - GEP.getResultElementType() == ElTy, + PointerType *PtrTy = dyn_cast(GEP.getType()->getScalarType()); + + Check(PtrTy && GEP.getResultElementType() == ElTy, "GEP is not of right type for indices!", &GEP, ElTy); if (auto *GEPVTy = dyn_cast(GEP.getType())) { @@ -4144,10 +4145,8 @@ void Verifier::visitGetElementPtrInst(GetElementPtrInst &GEP) { } } - if (auto *PTy = dyn_cast(GEP.getType())) { - Check(GEP.getAddressSpace() == PTy->getAddressSpace(), - "GEP address space doesn't match type", &GEP); - } + Check(GEP.getAddressSpace() == PtrTy->getAddressSpace(), + "GEP address space doesn't match type", &GEP); visitInstruction(GEP); } diff --git a/llvm/lib/MC/MCInstPrinter.cpp b/llvm/lib/MC/MCInstPrinter.cpp index e4faeba04a8fd7..069716a3ecf9b7 100644 --- a/llvm/lib/MC/MCInstPrinter.cpp +++ b/llvm/lib/MC/MCInstPrinter.cpp @@ -43,7 +43,7 @@ StringRef MCInstPrinter::getOpcodeName(unsigned Opcode) const { return MII.getName(Opcode); } -void MCInstPrinter::printRegName(raw_ostream &OS, MCRegister Reg) const { +void MCInstPrinter::printRegName(raw_ostream &OS, MCRegister Reg) { llvm_unreachable("Target should implement this"); } @@ -224,29 +224,32 @@ format_object MCInstPrinter::formatHex(uint64_t Value) const { llvm_unreachable("unsupported print style"); } -MCInstPrinter::WithMarkup MCInstPrinter::markup(raw_ostream &OS, - Markup S) const { - return WithMarkup(OS, S, getUseMarkup(), getUseColor()); +MCInstPrinter::WithMarkup MCInstPrinter::markup(raw_ostream &OS, Markup S) { + return WithMarkup(*this, OS, S, getUseMarkup(), getUseColor()); } -MCInstPrinter::WithMarkup::WithMarkup(raw_ostream &OS, Markup M, - bool EnableMarkup, bool EnableColor) - : OS(OS), EnableMarkup(EnableMarkup), EnableColor(EnableColor) { +MCInstPrinter::WithMarkup::WithMarkup(MCInstPrinter &IP, raw_ostream &OS, + Markup M, bool EnableMarkup, + bool EnableColor) + : IP(IP), OS(OS), EnableMarkup(EnableMarkup), EnableColor(EnableColor) { if (EnableColor) { + raw_ostream::Colors Color = raw_ostream::Colors::RESET; switch (M) { case Markup::Immediate: - OS.changeColor(raw_ostream::RED); + Color = raw_ostream::RED; break; case Markup::Register: - OS.changeColor(raw_ostream::CYAN); + Color = raw_ostream::CYAN; break; case Markup::Target: - OS.changeColor(raw_ostream::YELLOW); + Color = raw_ostream::YELLOW; break; case Markup::Memory: - OS.changeColor(raw_ostream::GREEN); + Color = raw_ostream::GREEN; break; } + IP.ColorStack.push_back(Color); + OS.changeColor(Color); } if (EnableMarkup) { @@ -270,6 +273,8 @@ MCInstPrinter::WithMarkup::WithMarkup(raw_ostream &OS, Markup M, MCInstPrinter::WithMarkup::~WithMarkup() { if (EnableMarkup) OS << '>'; - if (EnableColor) - OS.resetColor(); + if (!EnableColor) + return; + IP.ColorStack.pop_back(); + OS << IP.ColorStack.back(); } diff --git a/llvm/lib/MC/MCParser/AsmParser.cpp b/llvm/lib/MC/MCParser/AsmParser.cpp index 4774e5112af535..ecccb228c8c387 100644 --- a/llvm/lib/MC/MCParser/AsmParser.cpp +++ b/llvm/lib/MC/MCParser/AsmParser.cpp @@ -264,7 +264,7 @@ class AsmParser : public MCAsmParser { SmallVectorImpl> &OpDecls, SmallVectorImpl &Constraints, SmallVectorImpl &Clobbers, - const MCInstrInfo *MII, const MCInstPrinter *IP, + const MCInstrInfo *MII, MCInstPrinter *IP, MCAsmParserSemaCallback &SI) override; bool parseExpression(const MCExpr *&Res); @@ -6006,7 +6006,7 @@ bool AsmParser::parseMSInlineAsm( SmallVectorImpl> &OpDecls, SmallVectorImpl &Constraints, SmallVectorImpl &Clobbers, const MCInstrInfo *MII, - const MCInstPrinter *IP, MCAsmParserSemaCallback &SI) { + MCInstPrinter *IP, MCAsmParserSemaCallback &SI) { SmallVector InputDecls; SmallVector OutputDecls; SmallVector InputDeclsAddressOf; diff --git a/llvm/lib/MC/MCParser/MasmParser.cpp b/llvm/lib/MC/MCParser/MasmParser.cpp index d88fd09a1aa07c..a7f37d81f64092 100644 --- a/llvm/lib/MC/MCParser/MasmParser.cpp +++ b/llvm/lib/MC/MCParser/MasmParser.cpp @@ -539,7 +539,7 @@ class MasmParser : public MCAsmParser { SmallVectorImpl> &OpDecls, SmallVectorImpl &Constraints, SmallVectorImpl &Clobbers, - const MCInstrInfo *MII, const MCInstPrinter *IP, + const MCInstrInfo *MII, MCInstPrinter *IP, MCAsmParserSemaCallback &SI) override; bool parseExpression(const MCExpr *&Res); @@ -7340,7 +7340,7 @@ bool MasmParser::parseMSInlineAsm( SmallVectorImpl> &OpDecls, SmallVectorImpl &Constraints, SmallVectorImpl &Clobbers, const MCInstrInfo *MII, - const MCInstPrinter *IP, MCAsmParserSemaCallback &SI) { + MCInstPrinter *IP, MCAsmParserSemaCallback &SI) { SmallVector InputDecls; SmallVector OutputDecls; SmallVector InputDeclsAddressOf; diff --git a/llvm/lib/Passes/PassBuilder.cpp b/llvm/lib/Passes/PassBuilder.cpp index d1f75dfb5350a0..a879918005cad8 100644 --- a/llvm/lib/Passes/PassBuilder.cpp +++ b/llvm/lib/Passes/PassBuilder.cpp @@ -125,6 +125,7 @@ #include "llvm/CodeGen/SlotIndexes.h" #include "llvm/CodeGen/StackColoring.h" #include "llvm/CodeGen/StackProtector.h" +#include "llvm/CodeGen/TailDuplication.h" #include "llvm/CodeGen/TargetPassConfig.h" #include "llvm/CodeGen/TwoAddressInstructionPass.h" #include "llvm/CodeGen/TypePromotion.h" diff --git a/llvm/lib/ProfileData/InstrProfWriter.cpp b/llvm/lib/ProfileData/InstrProfWriter.cpp index 1a3721bf103503..0ab9f942a08589 100644 --- a/llvm/lib/ProfileData/InstrProfWriter.cpp +++ b/llvm/lib/ProfileData/InstrProfWriter.cpp @@ -19,6 +19,7 @@ #include "llvm/ProfileData/InstrProf.h" #include "llvm/ProfileData/MemProf.h" #include "llvm/ProfileData/ProfileCommon.h" +#include "llvm/Support/CommandLine.h" #include "llvm/Support/Compression.h" #include "llvm/Support/Endian.h" #include "llvm/Support/EndianStream.h" @@ -28,6 +29,7 @@ #include "llvm/Support/OnDiskHashTable.h" #include "llvm/Support/raw_ostream.h" #include +#include #include #include #include @@ -184,13 +186,25 @@ class InstrProfRecordWriterTrait { InstrProfWriter::InstrProfWriter( bool Sparse, uint64_t TemporalProfTraceReservoirSize, uint64_t MaxTemporalProfTraceLength, bool WritePrevVersion, - memprof::IndexedVersion MemProfVersionRequested, bool MemProfFullSchema) + memprof::IndexedVersion MemProfVersionRequested, bool MemProfFullSchema, + bool MemprofGenerateRandomHotness, + unsigned MemprofGenerateRandomHotnessSeed) : Sparse(Sparse), MaxTemporalProfTraceLength(MaxTemporalProfTraceLength), TemporalProfTraceReservoirSize(TemporalProfTraceReservoirSize), InfoObj(new InstrProfRecordWriterTrait()), WritePrevVersion(WritePrevVersion), MemProfVersionRequested(MemProfVersionRequested), - MemProfFullSchema(MemProfFullSchema) {} + MemProfFullSchema(MemProfFullSchema), + MemprofGenerateRandomHotness(MemprofGenerateRandomHotness) { + // Set up the random number seed if requested. + if (MemprofGenerateRandomHotness) { + unsigned seed = MemprofGenerateRandomHotnessSeed + ? MemprofGenerateRandomHotnessSeed + : std::time(nullptr); + errs() << "random hotness seed = " << seed << "\n"; + std::srand(seed); + } +} InstrProfWriter::~InstrProfWriter() { delete InfoObj; } @@ -273,13 +287,34 @@ void InstrProfWriter::addRecord(StringRef Name, uint64_t Hash, void InstrProfWriter::addMemProfRecord( const Function::GUID Id, const memprof::IndexedMemProfRecord &Record) { - auto [Iter, Inserted] = MemProfData.Records.insert({Id, Record}); + auto NewRecord = Record; + // Provoke random hotness values if requested. We specify the lifetime access + // density and lifetime length that will result in a cold or not cold hotness. + // See the logic in getAllocType() in Analysis/MemoryProfileInfo.cpp. + if (MemprofGenerateRandomHotness) { + for (auto &Alloc : NewRecord.AllocSites) { + // To get a not cold context, set the lifetime access density to the + // maximum value and the lifetime to 0. + uint64_t NewTLAD = std::numeric_limits::max(); + uint64_t NewTL = 0; + bool IsCold = std::rand() % 2; + if (IsCold) { + // To get a cold context, set the lifetime access density to 0 and the + // lifetime to the maximum value. + NewTLAD = 0; + NewTL = std::numeric_limits::max(); + } + Alloc.Info.setTotalLifetimeAccessDensity(NewTLAD); + Alloc.Info.setTotalLifetime(NewTL); + } + } + auto [Iter, Inserted] = MemProfData.Records.insert({Id, NewRecord}); // If we inserted a new record then we are done. if (Inserted) { return; } memprof::IndexedMemProfRecord &Existing = Iter->second; - Existing.merge(Record); + Existing.merge(NewRecord); } bool InstrProfWriter::addMemProfFrame(const memprof::FrameId Id, diff --git a/llvm/lib/SandboxIR/Context.cpp b/llvm/lib/SandboxIR/Context.cpp index 486e935bc35fba..b86ed5864c1ac1 100644 --- a/llvm/lib/SandboxIR/Context.cpp +++ b/llvm/lib/SandboxIR/Context.cpp @@ -35,17 +35,20 @@ Value *Context::registerValue(std::unique_ptr &&VPtr) { assert(VPtr->getSubclassID() != Value::ClassID::User && "Can't register a user!"); + Value *V = VPtr.get(); + [[maybe_unused]] auto Pair = + LLVMValueToValueMap.insert({VPtr->Val, std::move(VPtr)}); + assert(Pair.second && "Already exists!"); + // Track creation of instructions. // Please note that we don't allow the creation of detached instructions, // meaning that the instructions need to be inserted into a block upon // creation. This is why the tracker class combines creation and insertion. - if (auto *I = dyn_cast(VPtr.get())) + if (auto *I = dyn_cast(V)) { getTracker().emplaceIfTracking(I); + runCreateInstrCallbacks(I); + } - Value *V = VPtr.get(); - [[maybe_unused]] auto Pair = - LLVMValueToValueMap.insert({VPtr->Val, std::move(VPtr)}); - assert(Pair.second && "Already exists!"); return V; } @@ -660,4 +663,64 @@ Module *Context::createModule(llvm::Module *LLVMM) { return M; } +void Context::runEraseInstrCallbacks(Instruction *I) { + for (const auto &CBEntry : EraseInstrCallbacks) + CBEntry.second(I); +} + +void Context::runCreateInstrCallbacks(Instruction *I) { + for (auto &CBEntry : CreateInstrCallbacks) + CBEntry.second(I); +} + +void Context::runMoveInstrCallbacks(Instruction *I, const BBIterator &WhereIt) { + for (auto &CBEntry : MoveInstrCallbacks) + CBEntry.second(I, WhereIt); +} + +// An arbitrary limit, to check for accidental misuse. We expect a small number +// of callbacks to be registered at a time, but we can increase this number if +// we discover we needed more. +[[maybe_unused]] static constexpr int MaxRegisteredCallbacks = 16; + +Context::CallbackID Context::registerEraseInstrCallback(EraseInstrCallback CB) { + assert(EraseInstrCallbacks.size() <= MaxRegisteredCallbacks && + "EraseInstrCallbacks size limit exceeded"); + CallbackID ID = NextCallbackID++; + EraseInstrCallbacks[ID] = CB; + return ID; +} +void Context::unregisterEraseInstrCallback(CallbackID ID) { + [[maybe_unused]] bool Erased = EraseInstrCallbacks.erase(ID); + assert(Erased && + "Callback ID not found in EraseInstrCallbacks during deregistration"); +} + +Context::CallbackID +Context::registerCreateInstrCallback(CreateInstrCallback CB) { + assert(CreateInstrCallbacks.size() <= MaxRegisteredCallbacks && + "CreateInstrCallbacks size limit exceeded"); + CallbackID ID = NextCallbackID++; + CreateInstrCallbacks[ID] = CB; + return ID; +} +void Context::unregisterCreateInstrCallback(CallbackID ID) { + [[maybe_unused]] bool Erased = CreateInstrCallbacks.erase(ID); + assert(Erased && + "Callback ID not found in CreateInstrCallbacks during deregistration"); +} + +Context::CallbackID Context::registerMoveInstrCallback(MoveInstrCallback CB) { + assert(MoveInstrCallbacks.size() <= MaxRegisteredCallbacks && + "MoveInstrCallbacks size limit exceeded"); + CallbackID ID = NextCallbackID++; + MoveInstrCallbacks[ID] = CB; + return ID; +} +void Context::unregisterMoveInstrCallback(CallbackID ID) { + [[maybe_unused]] bool Erased = MoveInstrCallbacks.erase(ID); + assert(Erased && + "Callback ID not found in MoveInstrCallbacks during deregistration"); +} + } // namespace llvm::sandboxir diff --git a/llvm/lib/SandboxIR/Instruction.cpp b/llvm/lib/SandboxIR/Instruction.cpp index d80d10370e32d8..096b827541eeaf 100644 --- a/llvm/lib/SandboxIR/Instruction.cpp +++ b/llvm/lib/SandboxIR/Instruction.cpp @@ -73,6 +73,8 @@ void Instruction::removeFromParent() { void Instruction::eraseFromParent() { assert(users().empty() && "Still connected to users, can't erase!"); + + Ctx.runEraseInstrCallbacks(this); std::unique_ptr Detached = Ctx.detach(this); auto LLVMInstrs = getLLVMInstrs(); @@ -100,6 +102,7 @@ void Instruction::moveBefore(BasicBlock &BB, const BBIterator &WhereIt) { // Destination is same as origin, nothing to do. return; + Ctx.runMoveInstrCallbacks(this, WhereIt); Ctx.getTracker().emplaceIfTracking(this); auto *LLVMBB = cast(BB.Val); diff --git a/llvm/lib/Support/CMakeLists.txt b/llvm/lib/Support/CMakeLists.txt index 531bdeaca12614..2ecaea4b02bf61 100644 --- a/llvm/lib/Support/CMakeLists.txt +++ b/llvm/lib/Support/CMakeLists.txt @@ -256,6 +256,7 @@ add_llvm_component_library(LLVMSupport TimeProfiler.cpp Timer.cpp ToolOutputFile.cpp + TrieRawHashMap.cpp Twine.cpp TypeSize.cpp Unicode.cpp diff --git a/llvm/lib/Support/TrieRawHashMap.cpp b/llvm/lib/Support/TrieRawHashMap.cpp new file mode 100644 index 00000000000000..11d79a62d011dd --- /dev/null +++ b/llvm/lib/Support/TrieRawHashMap.cpp @@ -0,0 +1,515 @@ +//===- TrieRawHashMap.cpp -------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +#include "llvm/ADT/TrieRawHashMap.h" +#include "llvm/ADT/LazyAtomicPointer.h" +#include "llvm/ADT/StringExtras.h" +#include "llvm/ADT/TrieHashIndexGenerator.h" +#include "llvm/Support/Allocator.h" +#include "llvm/Support/Casting.h" +#include "llvm/Support/Debug.h" +#include "llvm/Support/ThreadSafeAllocator.h" +#include "llvm/Support/TrailingObjects.h" +#include "llvm/Support/raw_ostream.h" +#include + +using namespace llvm; + +namespace { +struct TrieNode { + const bool IsSubtrie = false; + + TrieNode(bool IsSubtrie) : IsSubtrie(IsSubtrie) {} + + static void *operator new(size_t Size) { return ::operator new(Size); } + void operator delete(void *Ptr) { ::operator delete(Ptr); } +}; + +struct TrieContent final : public TrieNode { + const uint8_t ContentOffset; + const uint8_t HashSize; + const uint8_t HashOffset; + + void *getValuePointer() const { + auto *Content = reinterpret_cast(this) + ContentOffset; + return const_cast(Content); + } + + ArrayRef getHash() const { + auto *Begin = reinterpret_cast(this) + HashOffset; + return ArrayRef(Begin, Begin + HashSize); + } + + TrieContent(size_t ContentOffset, size_t HashSize, size_t HashOffset) + : TrieNode(/*IsSubtrie=*/false), ContentOffset(ContentOffset), + HashSize(HashSize), HashOffset(HashOffset) {} + + static bool classof(const TrieNode *TN) { return !TN->IsSubtrie; } +}; + +static_assert(sizeof(TrieContent) == + ThreadSafeTrieRawHashMapBase::TrieContentBaseSize, + "Check header assumption!"); + +class TrieSubtrie final + : public TrieNode, + private TrailingObjects> { +public: + using Slot = LazyAtomicPointer; + + Slot &get(size_t I) { return getTrailingObjects()[I]; } + TrieNode *load(size_t I) { return get(I).load(); } + + unsigned size() const { return Size; } + + TrieSubtrie * + sink(size_t I, TrieContent &Content, size_t NumSubtrieBits, size_t NewI, + function_ref)> Saver); + + static std::unique_ptr create(size_t StartBit, size_t NumBits); + + explicit TrieSubtrie(size_t StartBit, size_t NumBits); + + static bool classof(const TrieNode *TN) { return TN->IsSubtrie; } + + static constexpr size_t sizeToAlloc(unsigned NumBits) { + assert(NumBits < 20 && "Tries should have fewer than ~1M slots"); + unsigned Count = 1u << NumBits; + return totalSizeToAlloc>(Count); + } + +private: + // FIXME: Use a bitset to speed up access: + // + // std::array, NumSlots/64> IsSet; + // + // This will avoid needing to visit sparsely filled slots in + // \a ThreadSafeTrieRawHashMapBase::destroyImpl() when there's a non-trivial + // destructor. + // + // It would also greatly speed up iteration, if we add that some day, and + // allow get() to return one level sooner. + // + // This would be the algorithm for updating IsSet (after updating Slots): + // + // std::atomic &Bits = IsSet[I.High]; + // const uint64_t NewBit = 1ULL << I.Low; + // uint64_t Old = 0; + // while (!Bits.compare_exchange_weak(Old, Old | NewBit)) + // ; + + // For debugging. + unsigned StartBit = 0; + unsigned NumBits = 0; + unsigned Size = 0; + friend class llvm::ThreadSafeTrieRawHashMapBase; + friend class TrailingObjects; + +public: + /// Linked list for ownership of tries. The pointer is owned by TrieSubtrie. + std::atomic Next; +}; +} // end namespace + +std::unique_ptr TrieSubtrie::create(size_t StartBit, + size_t NumBits) { + void *Memory = ::operator new(sizeToAlloc(NumBits)); + TrieSubtrie *S = ::new (Memory) TrieSubtrie(StartBit, NumBits); + return std::unique_ptr(S); +} + +TrieSubtrie::TrieSubtrie(size_t StartBit, size_t NumBits) + : TrieNode(true), StartBit(StartBit), NumBits(NumBits), Size(1u << NumBits), + Next(nullptr) { + for (unsigned I = 0; I < Size; ++I) + new (&get(I)) Slot(nullptr); + + static_assert( + std::is_trivially_destructible>::value, + "Expected no work in destructor for TrieNode"); +} + +// Sink the nodes down sub-trie when the object being inserted collides with +// the index of existing object in the trie. In this case, a new sub-trie needs +// to be allocated to hold existing object. +TrieSubtrie *TrieSubtrie::sink( + size_t I, TrieContent &Content, size_t NumSubtrieBits, size_t NewI, + function_ref)> Saver) { + // Create a new sub-trie that points to the existing object with the new + // index for the next level. + assert(NumSubtrieBits > 0); + std::unique_ptr S = create(StartBit + NumBits, NumSubtrieBits); + + assert(NewI < Size); + S->get(NewI).store(&Content); + + // Using compare_exchange to atomically add back the new sub-trie to the trie + // in the place of the exsiting object. + TrieNode *ExistingNode = &Content; + assert(I < Size); + if (get(I).compare_exchange_strong(ExistingNode, S.get())) + return Saver(std::move(S)); + + // Another thread created a subtrie already. Return it and let "S" be + // destructed. + return cast(ExistingNode); +} + +class ThreadSafeTrieRawHashMapBase::ImplType final + : private TrailingObjects { +public: + static std::unique_ptr create(size_t StartBit, size_t NumBits) { + size_t Size = sizeof(ImplType) + TrieSubtrie::sizeToAlloc(NumBits); + void *Memory = ::operator new(Size); + ImplType *Impl = ::new (Memory) ImplType(StartBit, NumBits); + return std::unique_ptr(Impl); + } + + // Save the Subtrie into the ownship list of the trie structure in a + // thread-safe way. The ownership transfer is done by compare_exchange the + // pointer value inside the unique_ptr. + TrieSubtrie *save(std::unique_ptr S) { + assert(!S->Next && "Expected S to a freshly-constructed leaf"); + + TrieSubtrie *CurrentHead = nullptr; + // Add ownership of "S" to front of the list, so that Root -> S -> + // Root.Next. This works by repeatedly setting S->Next to a candidate value + // of Root.Next (initially nullptr), then setting Root.Next to S once the + // candidate matches reality. + while (!getRoot()->Next.compare_exchange_weak(CurrentHead, S.get())) + S->Next.exchange(CurrentHead); + + // Ownership transferred to subtrie successfully. Release the unique_ptr. + return S.release(); + } + + // Get the root which is the trailing object. + TrieSubtrie *getRoot() { return getTrailingObjects(); } + + static void *operator new(size_t Size) { return ::operator new(Size); } + void operator delete(void *Ptr) { ::operator delete(Ptr); } + + /// FIXME: This should take a function that allocates and constructs the + /// content lazily (taking the hash as a separate parameter), in case of + /// collision. + ThreadSafeAllocator ContentAlloc; + +private: + friend class TrailingObjects; + + ImplType(size_t StartBit, size_t NumBits) { + ::new (getRoot()) TrieSubtrie(StartBit, NumBits); + } +}; + +ThreadSafeTrieRawHashMapBase::ImplType & +ThreadSafeTrieRawHashMapBase::getOrCreateImpl() { + if (ImplType *Impl = ImplPtr.load()) + return *Impl; + + // Create a new ImplType and store it if another thread doesn't do so first. + // If another thread wins this one is destroyed locally. + std::unique_ptr Impl = ImplType::create(0, NumRootBits); + ImplType *ExistingImpl = nullptr; + + // If the ownership transferred succesfully, release unique_ptr and return + // the pointer to the new ImplType. + if (ImplPtr.compare_exchange_strong(ExistingImpl, Impl.get())) + return *Impl.release(); + + // Already created, return the existing ImplType. + return *ExistingImpl; +} + +ThreadSafeTrieRawHashMapBase::PointerBase +ThreadSafeTrieRawHashMapBase::find(ArrayRef Hash) const { + assert(!Hash.empty() && "Uninitialized hash"); + + ImplType *Impl = ImplPtr.load(); + if (!Impl) + return PointerBase(); + + TrieSubtrie *S = Impl->getRoot(); + TrieHashIndexGenerator IndexGen{NumRootBits, NumSubtrieBits, Hash}; + size_t Index = IndexGen.next(); + while (Index != IndexGen.end()) { + // Try to set the content. + TrieNode *Existing = S->get(Index); + if (!Existing) + return PointerBase(S, Index, *IndexGen.StartBit); + + // Check for an exact match. + if (auto *ExistingContent = dyn_cast(Existing)) + return ExistingContent->getHash() == Hash + ? PointerBase(ExistingContent->getValuePointer()) + : PointerBase(S, Index, *IndexGen.StartBit); + + Index = IndexGen.next(); + S = cast(Existing); + } + llvm_unreachable("failed to locate the node after consuming all hash bytes"); +} + +ThreadSafeTrieRawHashMapBase::PointerBase ThreadSafeTrieRawHashMapBase::insert( + PointerBase Hint, ArrayRef Hash, + function_ref Hash)> + Constructor) { + assert(!Hash.empty() && "Uninitialized hash"); + + ImplType &Impl = getOrCreateImpl(); + TrieSubtrie *S = Impl.getRoot(); + TrieHashIndexGenerator IndexGen{NumRootBits, NumSubtrieBits, Hash}; + size_t Index; + if (Hint.isHint()) { + S = static_cast(Hint.P); + Index = IndexGen.hint(Hint.I, Hint.B); + } else { + Index = IndexGen.next(); + } + + while (Index != IndexGen.end()) { + // Load the node from the slot, allocating and calling the constructor if + // the slot is empty. + bool Generated = false; + TrieNode &Existing = S->get(Index).loadOrGenerate([&]() { + Generated = true; + + // Construct the value itself at the tail. + uint8_t *Memory = reinterpret_cast( + Impl.ContentAlloc.Allocate(ContentAllocSize, ContentAllocAlign)); + const uint8_t *HashStorage = Constructor(Memory + ContentOffset, Hash); + + // Construct the TrieContent header, passing in the offset to the hash. + TrieContent *Content = ::new (Memory) + TrieContent(ContentOffset, Hash.size(), HashStorage - Memory); + assert(Hash == Content->getHash() && "Hash not properly initialized"); + return Content; + }); + // If we just generated it, return it! + if (Generated) + return PointerBase(cast(Existing).getValuePointer()); + + if (auto *ST = dyn_cast(&Existing)) { + S = ST; + Index = IndexGen.next(); + continue; + } + + // Return the existing content if it's an exact match! + auto &ExistingContent = cast(Existing); + if (ExistingContent.getHash() == Hash) + return PointerBase(ExistingContent.getValuePointer()); + + // Sink the existing content as long as the indexes match. + size_t NextIndex = IndexGen.next(); + while (NextIndex != IndexGen.end()) { + size_t NewIndexForExistingContent = + IndexGen.getCollidingBits(ExistingContent.getHash()); + S = S->sink(Index, ExistingContent, IndexGen.getNumBits(), + NewIndexForExistingContent, + [&Impl](std::unique_ptr S) { + return Impl.save(std::move(S)); + }); + Index = NextIndex; + + // Found the difference. + if (NextIndex != NewIndexForExistingContent) + break; + + NextIndex = IndexGen.next(); + } + } + llvm_unreachable("failed to insert the node after consuming all hash bytes"); +} + +ThreadSafeTrieRawHashMapBase::ThreadSafeTrieRawHashMapBase( + size_t ContentAllocSize, size_t ContentAllocAlign, size_t ContentOffset, + std::optional NumRootBits, std::optional NumSubtrieBits) + : ContentAllocSize(ContentAllocSize), ContentAllocAlign(ContentAllocAlign), + ContentOffset(ContentOffset), + NumRootBits(NumRootBits ? *NumRootBits : DefaultNumRootBits), + NumSubtrieBits(NumSubtrieBits ? *NumSubtrieBits : DefaultNumSubtrieBits), + ImplPtr(nullptr) { + // Assertion checks for reasonable configuration. The settings below are not + // hard limits on most platforms, but a reasonable configuration should fall + // within those limits. + assert((!NumRootBits || *NumRootBits < 20) && + "Root should have fewer than ~1M slots"); + assert((!NumSubtrieBits || *NumSubtrieBits < 10) && + "Subtries should have fewer than ~1K slots"); +} + +ThreadSafeTrieRawHashMapBase::ThreadSafeTrieRawHashMapBase( + ThreadSafeTrieRawHashMapBase &&RHS) + : ContentAllocSize(RHS.ContentAllocSize), + ContentAllocAlign(RHS.ContentAllocAlign), + ContentOffset(RHS.ContentOffset), NumRootBits(RHS.NumRootBits), + NumSubtrieBits(RHS.NumSubtrieBits) { + // Steal the root from RHS. + ImplPtr = RHS.ImplPtr.exchange(nullptr); +} + +ThreadSafeTrieRawHashMapBase::~ThreadSafeTrieRawHashMapBase() { + assert(!ImplPtr.load() && "Expected subclass to call destroyImpl()"); +} + +void ThreadSafeTrieRawHashMapBase::destroyImpl( + function_ref Destructor) { + std::unique_ptr Impl(ImplPtr.exchange(nullptr)); + if (!Impl) + return; + + // Destroy content nodes throughout trie. Avoid destroying any subtries since + // we need TrieNode::classof() to find the content nodes. + // + // FIXME: Once we have bitsets (see FIXME in TrieSubtrie class), use them + // facilitate sparse iteration here. + if (Destructor) + for (TrieSubtrie *Trie = Impl->getRoot(); Trie; Trie = Trie->Next.load()) + for (unsigned I = 0; I < Trie->size(); ++I) + if (auto *Content = dyn_cast_or_null(Trie->load(I))) + Destructor(Content->getValuePointer()); + + // Destroy the subtries. Incidentally, this destroys them in the reverse order + // of saving. + TrieSubtrie *Trie = Impl->getRoot()->Next; + while (Trie) { + TrieSubtrie *Next = Trie->Next.exchange(nullptr); + delete Trie; + Trie = Next; + } +} + +ThreadSafeTrieRawHashMapBase::PointerBase +ThreadSafeTrieRawHashMapBase::getRoot() const { + ImplType *Impl = ImplPtr.load(); + if (!Impl) + return PointerBase(); + return PointerBase(Impl->getRoot()); +} + +unsigned ThreadSafeTrieRawHashMapBase::getStartBit( + ThreadSafeTrieRawHashMapBase::PointerBase P) const { + assert(!P.isHint() && "Not a valid trie"); + if (!P.P) + return 0; + if (auto *S = dyn_cast((TrieNode *)P.P)) + return S->StartBit; + return 0; +} + +unsigned ThreadSafeTrieRawHashMapBase::getNumBits( + ThreadSafeTrieRawHashMapBase::PointerBase P) const { + assert(!P.isHint() && "Not a valid trie"); + if (!P.P) + return 0; + if (auto *S = dyn_cast((TrieNode *)P.P)) + return S->NumBits; + return 0; +} + +unsigned ThreadSafeTrieRawHashMapBase::getNumSlotUsed( + ThreadSafeTrieRawHashMapBase::PointerBase P) const { + assert(!P.isHint() && "Not a valid trie"); + if (!P.P) + return 0; + auto *S = dyn_cast((TrieNode *)P.P); + if (!S) + return 0; + unsigned Num = 0; + for (unsigned I = 0, E = S->size(); I < E; ++I) + if (S->load(I)) + ++Num; + return Num; +} + +std::string ThreadSafeTrieRawHashMapBase::getTriePrefixAsString( + ThreadSafeTrieRawHashMapBase::PointerBase P) const { + assert(!P.isHint() && "Not a valid trie"); + if (!P.P) + return ""; + + auto *S = dyn_cast((TrieNode *)P.P); + if (!S || !S->IsSubtrie) + return ""; + + // Find a TrieContent node which has hash stored. Depth search following the + // first used slot until a TrieContent node is found. + TrieSubtrie *Current = S; + TrieContent *Node = nullptr; + while (Current) { + TrieSubtrie *Next = nullptr; + // Find first used slot in the trie. + for (unsigned I = 0, E = Current->size(); I < E; ++I) { + auto *S = Current->load(I); + if (!S) + continue; + + if (auto *Content = dyn_cast(S)) + Node = Content; + else if (auto *Sub = dyn_cast(S)) + Next = Sub; + break; + } + + // Found the node. + if (Node) + break; + + // Continue to the next level if the node is not found. + Current = Next; + } + + assert(Node && "malformed trie, cannot find TrieContent on leaf node"); + // The prefix for the current trie is the first `StartBit` of the content + // stored underneath this subtrie. + std::string Str; + raw_string_ostream SS(Str); + + unsigned StartFullBytes = (S->StartBit + 1) / 8 - 1; + SS << toHex(toStringRef(Node->getHash()).take_front(StartFullBytes), + /*LowerCase=*/true); + + // For the part of the prefix that doesn't fill a byte, print raw bit values. + std::string Bits; + for (unsigned I = StartFullBytes * 8, E = S->StartBit; I < E; ++I) { + unsigned Index = I / 8; + unsigned Offset = 7 - I % 8; + Bits.push_back('0' + ((Node->getHash()[Index] >> Offset) & 1)); + } + + if (!Bits.empty()) + SS << "[" << Bits << "]"; + + return SS.str(); +} + +unsigned ThreadSafeTrieRawHashMapBase::getNumTries() const { + ImplType *Impl = ImplPtr.load(); + if (!Impl) + return 0; + unsigned Num = 0; + for (TrieSubtrie *Trie = Impl->getRoot(); Trie; Trie = Trie->Next.load()) + ++Num; + return Num; +} + +ThreadSafeTrieRawHashMapBase::PointerBase +ThreadSafeTrieRawHashMapBase::getNextTrie( + ThreadSafeTrieRawHashMapBase::PointerBase P) const { + assert(!P.isHint() && "Not a valid trie"); + if (!P.P) + return PointerBase(); + auto *S = dyn_cast((TrieNode *)P.P); + if (!S) + return PointerBase(); + if (auto *E = S->Next.load()) + return PointerBase(E); + return PointerBase(); +} diff --git a/llvm/lib/TableGen/TGLexer.cpp b/llvm/lib/TableGen/TGLexer.cpp index 8fe7f69ecf8e59..1e93b2c160ba58 100644 --- a/llvm/lib/TableGen/TGLexer.cpp +++ b/llvm/lib/TableGen/TGLexer.cpp @@ -89,7 +89,7 @@ TGLexer::TGLexer(SourceMgr &SM, ArrayRef Macros) : SrcMgr(SM) { for (StringRef MacroName : Macros) { const char *End = lexMacroName(MacroName); if (End != MacroName.end()) - PrintFatalError("Invalid macro name `" + MacroName + + PrintFatalError("invalid macro name `" + MacroName + "` specified on command line"); DefinedMacros.insert(MacroName); @@ -188,7 +188,7 @@ tgtok::TokKind TGLexer::LexToken(bool FileOrLineStart) { return LexIdentifier(); // Unknown character, emit an error. - return ReturnError(TokStart, "Unexpected character"); + return ReturnError(TokStart, "unexpected character"); case EOF: // Lex next token, if we just left an include file. // Note that leaving an include file means that the next @@ -231,7 +231,7 @@ tgtok::TokKind TGLexer::LexToken(bool FileOrLineStart) { ++CurPtr; // Eat third dot. return tgtok::dotdotdot; } - return ReturnError(TokStart, "Invalid '..' punctuation"); + return ReturnError(TokStart, "invalid '..' punctuation"); } return tgtok::dot; @@ -255,7 +255,7 @@ tgtok::TokKind TGLexer::LexToken(bool FileOrLineStart) { if (SkipCComment()) return tgtok::Error; } else // Otherwise, this is an error. - return ReturnError(TokStart, "Unexpected character"); + return ReturnError(TokStart, "unexpected character"); return LexToken(FileOrLineStart); case '-': case '+': case '0': case '1': case '2': case '3': case '4': case '5': case '6': @@ -313,10 +313,10 @@ tgtok::TokKind TGLexer::LexString() { while (*CurPtr != '"') { // If we hit the end of the buffer, report an error. if (*CurPtr == 0 && CurPtr == CurBuf.end()) - return ReturnError(StrStart, "End of file in string literal"); + return ReturnError(StrStart, "end of file in string literal"); if (*CurPtr == '\n' || *CurPtr == '\r') - return ReturnError(StrStart, "End of line in string literal"); + return ReturnError(StrStart, "end of line in string literal"); if (*CurPtr != '\\') { CurStrVal += *CurPtr++; @@ -346,7 +346,7 @@ tgtok::TokKind TGLexer::LexString() { // If we hit the end of the buffer, report an error. case '\0': if (CurPtr == CurBuf.end()) - return ReturnError(StrStart, "End of file in string literal"); + return ReturnError(StrStart, "end of file in string literal"); [[fallthrough]]; default: return ReturnError(CurPtr, "invalid escape in string literal"); @@ -359,7 +359,7 @@ tgtok::TokKind TGLexer::LexString() { tgtok::TokKind TGLexer::LexVarName() { if (!isValidIDChar(CurPtr[0], /*First=*/true)) - return ReturnError(TokStart, "Invalid variable name"); + return ReturnError(TokStart, "invalid variable name"); // Otherwise, we're ok, consume the rest of the characters. const char *VarNameStart = CurPtr++; @@ -433,7 +433,7 @@ bool TGLexer::LexInclude() { tgtok::TokKind Tok = LexToken(); if (Tok == tgtok::Error) return true; if (Tok != tgtok::StrVal) { - PrintError(getLoc(), "Expected filename after include"); + PrintError(getLoc(), "expected filename after include"); return true; } @@ -444,7 +444,7 @@ bool TGLexer::LexInclude() { CurBuffer = SrcMgr.AddIncludeFile(Filename, SMLoc::getFromPointer(CurPtr), IncludedFile); if (!CurBuffer) { - PrintError(getLoc(), "Could not find include file '" + Filename + "'"); + PrintError(getLoc(), "could not find include file '" + Filename + "'"); return true; } @@ -476,7 +476,7 @@ bool TGLexer::SkipCComment() { int CurChar = getNextChar(); switch (CurChar) { case EOF: - PrintError(TokStart, "Unterminated comment!"); + PrintError(TokStart, "unterminated comment"); return true; case '*': // End of the comment? @@ -543,7 +543,7 @@ tgtok::TokKind TGLexer::LexNumber() { // Requires at least one digit. if (CurPtr == NumStart) - return ReturnError(TokStart, "Invalid number"); + return ReturnError(TokStart, "invalid number"); errno = 0; if (IsMinus) @@ -552,9 +552,9 @@ tgtok::TokKind TGLexer::LexNumber() { CurIntVal = strtoull(NumStart, nullptr, Base); if (errno == EINVAL) - return ReturnError(TokStart, "Invalid number"); + return ReturnError(TokStart, "invalid number"); if (errno == ERANGE) - return ReturnError(TokStart, "Number out of range"); + return ReturnError(TokStart, "number out of range"); return Base == 2 ? tgtok::BinaryIntVal : tgtok::IntVal; } @@ -580,13 +580,13 @@ tgtok::TokKind TGLexer::LexBracket() { } } - return ReturnError(CodeStart - 2, "Unterminated code block"); + return ReturnError(CodeStart - 2, "unterminated code block"); } /// LexExclaim - Lex '!' and '![a-zA-Z]+'. tgtok::TokKind TGLexer::LexExclaim() { if (!isAlpha(*CurPtr)) - return ReturnError(CurPtr - 1, "Invalid \"!operator\""); + return ReturnError(CurPtr - 1, "invalid \"!operator\""); const char *Start = CurPtr++; while (isAlpha(*CurPtr)) @@ -648,7 +648,8 @@ tgtok::TokKind TGLexer::LexExclaim() { .Case("repr", tgtok::XRepr) .Default(tgtok::Error); - return Kind != tgtok::Error ? Kind : ReturnError(Start-1, "Unknown operator"); + return Kind != tgtok::Error ? Kind + : ReturnError(Start - 1, "unknown operator"); } bool TGLexer::prepExitInclude(bool IncludeStackMustBeEmpty) { @@ -662,17 +663,17 @@ bool TGLexer::prepExitInclude(bool IncludeStackMustBeEmpty) { // Pop the preprocessing controls from the include stack. if (PrepIncludeStack.empty()) { - PrintFatalError("Preprocessor include stack is empty"); + PrintFatalError("preprocessor include stack is empty"); } PrepIncludeStack.pop_back(); if (IncludeStackMustBeEmpty) { if (!PrepIncludeStack.empty()) - PrintFatalError("Preprocessor include stack is not empty"); + PrintFatalError("preprocessor include stack is not empty"); } else { if (PrepIncludeStack.empty()) - PrintFatalError("Preprocessor include stack is empty"); + PrintFatalError("preprocessor include stack is empty"); } return true; @@ -732,7 +733,7 @@ bool TGLexer::prepEatPreprocessorDirective(tgtok::TokKind Kind) { return true; } - PrintFatalError("Unsupported preprocessing token in " + PrintFatalError("unsupported preprocessing token in " "prepEatPreprocessorDirective()"); return false; } @@ -748,7 +749,7 @@ tgtok::TokKind TGLexer::lexPreprocessor(tgtok::TokKind Kind, StringRef MacroName = prepLexMacroName(); StringRef IfTokName = Kind == tgtok::Ifdef ? "#ifdef" : "#ifndef"; if (MacroName.empty()) - return ReturnError(TokStart, "Expected macro name after " + IfTokName); + return ReturnError(TokStart, "expected macro name after " + IfTokName); bool MacroIsDefined = DefinedMacros.count(MacroName) != 0; @@ -763,7 +764,7 @@ tgtok::TokKind TGLexer::lexPreprocessor(tgtok::TokKind Kind, {tgtok::Ifdef, MacroIsDefined, SMLoc::getFromPointer(TokStart)}); if (!prepSkipDirectiveEnd()) - return ReturnError(CurPtr, "Only comments are supported after " + + return ReturnError(CurPtr, "only comments are supported after " + IfTokName + " NAME"); // If we were not processing tokens before this #ifdef, @@ -794,7 +795,7 @@ tgtok::TokKind TGLexer::lexPreprocessor(tgtok::TokKind Kind, if (IfdefEntry.Kind != tgtok::Ifdef) { PrintError(TokStart, "double #else"); - return ReturnError(IfdefEntry.SrcPos, "Previous #else is here"); + return ReturnError(IfdefEntry.SrcPos, "previous #else is here"); } // Replace the corresponding #ifdef's control with its negation @@ -804,7 +805,7 @@ tgtok::TokKind TGLexer::lexPreprocessor(tgtok::TokKind Kind, {Kind, !IfdefEntry.IsDefined, SMLoc::getFromPointer(TokStart)}); if (!prepSkipDirectiveEnd()) - return ReturnError(CurPtr, "Only comments are supported after #else"); + return ReturnError(CurPtr, "only comments are supported after #else"); // If we were processing tokens before this #else, // we have to start skipping lines until the matching #endif. @@ -827,12 +828,12 @@ tgtok::TokKind TGLexer::lexPreprocessor(tgtok::TokKind Kind, if (IfdefOrElseEntry.Kind != tgtok::Ifdef && IfdefOrElseEntry.Kind != tgtok::Else) { - PrintFatalError("Invalid preprocessor control on the stack"); + PrintFatalError("invalid preprocessor control on the stack"); return tgtok::Error; } if (!prepSkipDirectiveEnd()) - return ReturnError(CurPtr, "Only comments are supported after #endif"); + return ReturnError(CurPtr, "only comments are supported after #endif"); PrepIncludeStack.back()->pop_back(); @@ -847,15 +848,15 @@ tgtok::TokKind TGLexer::lexPreprocessor(tgtok::TokKind Kind, } else if (Kind == tgtok::Define) { StringRef MacroName = prepLexMacroName(); if (MacroName.empty()) - return ReturnError(TokStart, "Expected macro name after #define"); + return ReturnError(TokStart, "expected macro name after #define"); if (!DefinedMacros.insert(MacroName).second) PrintWarning(getLoc(), - "Duplicate definition of macro: " + Twine(MacroName)); + "duplicate definition of macro: " + Twine(MacroName)); if (!prepSkipDirectiveEnd()) return ReturnError(CurPtr, - "Only comments are supported after #define NAME"); + "only comments are supported after #define NAME"); if (!ReturnNextLiveToken) { PrintFatalError("#define must be ignored during the lines skipping"); @@ -865,13 +866,13 @@ tgtok::TokKind TGLexer::lexPreprocessor(tgtok::TokKind Kind, return LexToken(); } - PrintFatalError("Preprocessing directive is not supported"); + PrintFatalError("preprocessing directive is not supported"); return tgtok::Error; } bool TGLexer::prepSkipRegion(bool MustNeverBeFalse) { if (!MustNeverBeFalse) - PrintFatalError("Invalid recursion."); + PrintFatalError("invalid recursion."); do { // Skip all symbols to the line end. @@ -917,7 +918,7 @@ bool TGLexer::prepSkipRegion(bool MustNeverBeFalse) { // due to #else or #endif. if (prepIsProcessingEnabled()) { if (Kind != tgtok::Else && Kind != tgtok::Endif) { - PrintFatalError("Tokens processing was enabled by an unexpected " + PrintFatalError("tokens processing was enabled by an unexpected " "preprocessing directive"); return false; } @@ -1032,7 +1033,7 @@ bool TGLexer::prepSkipDirectiveEnd() { return false; } else { TokStart = CurPtr; - PrintError(CurPtr, "Unexpected character"); + PrintError(CurPtr, "unexpected character"); return false; } @@ -1067,8 +1068,8 @@ void TGLexer::prepReportPreprocessorStackError() { "empty control stack"); auto &PrepControl = PrepIncludeStack.back()->back(); - PrintError(CurBuf.end(), "Reached EOF without matching #endif"); - PrintError(PrepControl.SrcPos, "The latest preprocessor control is here"); + PrintError(CurBuf.end(), "reached EOF without matching #endif"); + PrintError(PrepControl.SrcPos, "the latest preprocessor control is here"); TokStart = CurPtr; } diff --git a/llvm/lib/Target/AArch64/AArch64.td b/llvm/lib/Target/AArch64/AArch64.td index 9bb508b783c36a..6854cccaafa1d7 100644 --- a/llvm/lib/Target/AArch64/AArch64.td +++ b/llvm/lib/Target/AArch64/AArch64.td @@ -73,7 +73,8 @@ def SVEUnsupported : AArch64Unsupported { SVE2Unsupported.F); } -let F = [HasSME2p2, HasSVE2p2orSME2p2] in +let F = [HasSME2p2, HasSVE2p2orSME2p2, HasNonStreamingSVEorSME2p2, + HasNonStreamingSVE2p2orSME2p2] in def SME2p2Unsupported : AArch64Unsupported; def SME2p1Unsupported : AArch64Unsupported { diff --git a/llvm/lib/Target/AArch64/AArch64FMV.td b/llvm/lib/Target/AArch64/AArch64FMV.td index 7146b041fe5d15..12d841445b80f7 100644 --- a/llvm/lib/Target/AArch64/AArch64FMV.td +++ b/llvm/lib/Target/AArch64/AArch64FMV.td @@ -81,9 +81,6 @@ def : FMVExtension<"sme-i16i64", "FEAT_SME_I64", "+sme,+sme-i16i64,+bf16", 570>; def : FMVExtension<"sme2", "FEAT_SME2", "+sme2,+sme,+bf16", 580>; def : FMVExtension<"ssbs", "FEAT_SSBS2", "+ssbs", 490>; def : FMVExtension<"sve", "FEAT_SVE", "+sve,+fullfp16,+fp-armv8,+neon", 310>; -def : FMVExtension<"sve-bf16", "FEAT_SVE_BF16", "+sve,+bf16,+fullfp16,+fp-armv8,+neon", 320>; -def : FMVExtension<"sve-ebf16", "FEAT_SVE_EBF16", "+sve,+bf16,+fullfp16,+fp-armv8,+neon", 330>; -def : FMVExtension<"sve-i8mm", "FEAT_SVE_I8MM", "+sve,+i8mm,+fullfp16,+fp-armv8,+neon", 340>; def : FMVExtension<"sve2", "FEAT_SVE2", "+sve2,+sve,+fullfp16,+fp-armv8,+neon", 370>; def : FMVExtension<"sve2-aes", "FEAT_SVE_PMULL128", "+sve2,+sve,+aes,+sve2-aes,+fullfp16,+fp-armv8,+neon", 380>; def : FMVExtension<"sve2-bitperm", "FEAT_SVE_BITPERM", "+sve2,+sve,+sve2-bitperm,+fullfp16,+fp-armv8,+neon", 400>; diff --git a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp index 32ba2866ac8180..31a720ed7b5c77 100644 --- a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp +++ b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp @@ -2536,6 +2536,11 @@ unsigned AArch64TargetLowering::ComputeNumSignBitsForTargetNode( case AArch64ISD::FCMLTz: // Compares return either 0 or all-ones return VTBits; + case AArch64ISD::VASHR: { + unsigned Tmp = + DAG.ComputeNumSignBits(Op.getOperand(0), DemandedElts, Depth + 1); + return std::min(Tmp + Op.getConstantOperandVal(1), VTBits); + } } return 1; diff --git a/llvm/lib/Target/AArch64/AArch64InstrInfo.td b/llvm/lib/Target/AArch64/AArch64InstrInfo.td index 6194de2d56b630..457e918728ae27 100644 --- a/llvm/lib/Target/AArch64/AArch64InstrInfo.td +++ b/llvm/lib/Target/AArch64/AArch64InstrInfo.td @@ -244,7 +244,7 @@ def HasSVEorSME : Predicate<"Subtarget->hasSVE() || (Subtarget->isStreaming() && Subtarget->hasSME())">, AssemblerPredicateWithAll<(any_of FeatureSVE, FeatureSME), "sve or sme">; -def HasSVEorSME2p2 +def HasNonStreamingSVEorSME2p2 : Predicate<"(Subtarget->isSVEAvailable() && Subtarget->hasSVE()) ||" "(Subtarget->isSVEorStreamingSVEAvailable() && Subtarget->hasSME2p2())">, AssemblerPredicateWithAll<(any_of FeatureSVE, FeatureSME2p2), @@ -281,6 +281,11 @@ def HasSMEF16F16orSMEF8F16 : Predicate<"Subtarget->isStreaming() && (Subtarget->hasSMEF16F16() || Subtarget->hasSMEF8F16())">, AssemblerPredicateWithAll<(any_of FeatureSMEF16F16, FeatureSMEF8F16), "sme-f16f16 or sme-f8f16">; +def HasNonStreamingSVE2p2orSME2p2 + : Predicate<"(Subtarget->isSVEAvailable() && Subtarget->hasSVE2p2()) ||" + "(Subtarget->isSVEorStreamingSVEAvailable() && Subtarget->hasSME2p2())">, + AssemblerPredicateWithAll<(any_of FeatureSVE2p2, FeatureSME2p2), + "sme2p2 or sve2p2">; // A subset of NEON instructions are legal in Streaming SVE execution mode, // so don't need the additional check for 'isNeonAvailable'. diff --git a/llvm/lib/Target/AArch64/AArch64SMEInstrInfo.td b/llvm/lib/Target/AArch64/AArch64SMEInstrInfo.td index b0ce9e1a1b406f..e78cd7146df2aa 100644 --- a/llvm/lib/Target/AArch64/AArch64SMEInstrInfo.td +++ b/llvm/lib/Target/AArch64/AArch64SMEInstrInfo.td @@ -1033,9 +1033,22 @@ let Predicates = [HasSME2p2, HasSMEF8F16], Uses = [FPMR, FPCR] in { let Predicates = [HasSME2p2, HasSMEF16F16] in { def FTMOPA_M2ZZZI_HtoH : sme_tmopa_16b<0b10001, ZZ_h_mul_r, ZPR16, "ftmopa">; + defm FMOP4A : sme2_fmop4as_fp16_non_widening<0, "fmop4a">; + defm FMOP4S : sme2_fmop4as_fp16_non_widening<1, "fmop4s">; } // [HasSME2p2, HasSMEF16F16] let Predicates = [HasSME2, HasSVEBFSCALE] in { defm BFMUL : sme2_bfmul_single<"bfmul">; defm BFMUL : sme2_bfmul_multi<"bfmul">; } //[HasSME2, HasSVEBFSCALE] + +let Uses = [FPMR, FPCR] in { +let Predicates = [HasSME2p2, HasSMEF8F32] in { + defm FMOP4A : sme2_fmop4a_fp8_fp32_4way<"fmop4a">; +} +} + +let Predicates = [HasSME2p2, HasSMEB16B16] in { + defm BFMOP4A : sme2_bfmop4as_non_widening<0, "bfmop4a">; + defm BFMOP4S : sme2_bfmop4as_non_widening<1, "bfmop4s">; +} diff --git a/llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td b/llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td index 2b69903b133fe3..d6662d15617fab 100644 --- a/llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td +++ b/llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td @@ -928,9 +928,10 @@ let Predicates = [HasSVEorSME] in { defm SPLICE_ZPZ : sve_int_perm_splice<"splice", AArch64splice>; } // End HasSVEorSME -let Predicates = [HasSVE] in { - defm COMPACT_ZPZ : sve_int_perm_compact<"compact", int_aarch64_sve_compact>; -} // End HasSVE +// COMPACT - word and doubleword +let Predicates = [HasNonStreamingSVEorSME2p2] in { + defm COMPACT_ZPZ : sve_int_perm_compact_sd<"compact", int_aarch64_sve_compact>; +} let Predicates = [HasSVEorSME] in { defm INSR_ZR : sve_int_perm_insrs<"insr", AArch64insr>; @@ -2128,7 +2129,7 @@ let Predicates = [HasSVEorSME] in { defm CNTH_XPiI : sve_int_count<0b010, "cnth", int_aarch64_sve_cnth>; defm CNTW_XPiI : sve_int_count<0b100, "cntw", int_aarch64_sve_cntw>; defm CNTD_XPiI : sve_int_count<0b110, "cntd", int_aarch64_sve_cntd>; - defm CNTP_XPP : sve_int_pcount_pred<0b0000, "cntp", int_aarch64_sve_cntp>; + defm CNTP_XPP : sve_int_pcount_pred<0b000, "cntp", int_aarch64_sve_cntp>; def : Pat<(i64 (AArch64CttzElts nxv16i1:$Op1)), (CNTP_XPP_B (BRKB_PPzP (PTRUE_B 31), PPR:$Op1), @@ -2427,7 +2428,7 @@ let Predicates = [HasBF16, HasSVEorSME] in { } // End HasBF16, HasSVEorSME let Predicates = [HasBF16, HasSVE] in { - defm BFMMLA_ZZZ : sve_bfloat_matmul<"bfmmla", int_aarch64_sve_bfmmla>; + defm BFMMLA_ZZZ : sve_fp_matrix_mla<0b01, "bfmmla", ZPR32, ZPR16, int_aarch64_sve_bfmmla, nxv4f32, nxv8bf16>; } // End HasBF16, HasSVE let Predicates = [HasBF16, HasSVEorSME] in { @@ -3449,11 +3450,15 @@ let Predicates = [HasSVEorSME, HasMatMulInt8] in { } // End HasSVEorSME, HasMatMulInt8 let Predicates = [HasSVE, HasMatMulFP32] in { - defm FMMLA_ZZZ_S : sve_fp_matrix_mla<0, "fmmla", ZPR32, int_aarch64_sve_fmmla, nxv4f32>; + defm FMMLA_ZZZ_S : sve_fp_matrix_mla<0b10, "fmmla", ZPR32, ZPR32, int_aarch64_sve_fmmla, nxv4f32, nxv4f32>; } // End HasSVE, HasMatMulFP32 +let Predicates = [HasSVE_F16F32MM] in { + def FMLLA_ZZZ_HtoS : sve_fp_matrix_mla<0b00, "fmmla", ZPR32, ZPR16>; +} // End HasSVE_F16F32MM + let Predicates = [HasSVE, HasMatMulFP64] in { - defm FMMLA_ZZZ_D : sve_fp_matrix_mla<1, "fmmla", ZPR64, int_aarch64_sve_fmmla, nxv2f64>; + defm FMMLA_ZZZ_D : sve_fp_matrix_mla<0b11, "fmmla", ZPR64, ZPR64, int_aarch64_sve_fmmla, nxv2f64, nxv2f64>; defm LD1RO_B_IMM : sve_mem_ldor_si<0b00, "ld1rob", Z_b, ZPR8, nxv16i8, nxv16i1, AArch64ld1ro_z>; defm LD1RO_H_IMM : sve_mem_ldor_si<0b01, "ld1roh", Z_h, ZPR16, nxv8i16, nxv8i1, AArch64ld1ro_z>; defm LD1RO_W_IMM : sve_mem_ldor_si<0b10, "ld1row", Z_s, ZPR32, nxv4i32, nxv4i1, AArch64ld1ro_z>; @@ -3846,7 +3851,7 @@ let Predicates = [HasSVE2] in { let Predicates = [HasSVE2orSME] in { // SVE2 vector splice (constructive) - defm SPLICE_ZPZZ : sve2_int_perm_splice_cons<"splice">; + defm SPLICE_ZPZZ : sve2_int_perm_splice_cons<"splice", AArch64splice>; } // End HasSVE2orSME let Predicates = [HasSVE2] in { @@ -4221,15 +4226,22 @@ defm TBLQ_ZZZ : sve2p1_tblq<"tblq", int_aarch64_sve_tblq>; // SME2.2 or SVE2.2 instructions //===----------------------------------------------------------------------===// let Predicates = [HasSVE2p2orSME2p2] in { + // SVE Floating-point convert precision, zeroing predicate + defm FCVT_ZPzZ : sve_fp_z2op_p_zd_b_0<"fcvt">; + // SVE2p2 floating-point convert precision down (placing odd), zeroing predicate defm FCVTNT_ZPzZ : sve_fp_fcvtntz<"fcvtnt">; def FCVTXNT_ZPzZ_DtoS : sve_fp_fcvt2z<0b0010, "fcvtxnt", ZPR32, ZPR64>; + // Placing even + def FCVTX_ZPzZ_DtoS : sve_fp_z2op_p_zd<0b0001010, "fcvtx", ZPR64, ZPR32>; // SVE2p2 floating-point convert precision up, zeroing predicate defm FCVTLT_ZPzZ : sve_fp_fcvtltz<"fcvtlt">; // SVE2p2 floating-point convert single-to-bf (placing odd), zeroing predicate def BFCVTNT_ZPzZ : sve_fp_fcvt2z<0b1010, "bfcvtnt", ZPR16, ZPR32>; + // Placing corresponding + def BFCVT_ZPzZ_StoH : sve_fp_z2op_p_zd<0b1001010, "bfcvt", ZPR32, ZPR16>; // Floating-point convert to integer, zeroing predicate defm FCVTZS_ZPzZ : sve_fp_z2op_p_zd_d<0b0, "fcvtzs">; @@ -4292,8 +4304,21 @@ let Predicates = [HasSVE2p2orSME2p2] in { def SXTW_ZPzZ_D : sve_int_un_pred_arit_z<0b11, 0b1000, "sxtw", ZPR64>; def UXTW_ZPzZ_D : sve_int_un_pred_arit_z<0b11, 0b1010, "uxtw", ZPR64>; + // SVE predicate count + defm FIRSTP_XPP : sve_int_pcount_pred_tmp<0b001, "firstp">; + defm LASTP_XPP : sve_int_pcount_pred_tmp<0b010, "lastp">; } // End HasSME2p2orSVE2p2 +//===----------------------------------------------------------------------===// +// SME2.2 or SVE2.2 instructions - Legal in streaming mode iff target has SME2p2 +//===----------------------------------------------------------------------===// +let Predicates = [HasNonStreamingSVE2p2orSME2p2] in { + // SVE2 EXPAND + defm EXPAND_ZPZ : sve2_int_perm_expand<"expand">; + // SVE COMPACT - byte and halfword + defm COMPACT_ZPZ : sve_int_perm_compact_bh<"compact">; +} + //===----------------------------------------------------------------------===// // SVE2 FP8 instructions //===----------------------------------------------------------------------===// @@ -4342,6 +4367,14 @@ def FMLALLTB_ZZZ : sve2_fp8_mla<0b010, ZPR32, "fmlalltb">; def FMLALLTT_ZZZ : sve2_fp8_mla<0b011, ZPR32, "fmlalltt">; } // End HasSSVE_FP8FMA +let Predicates = [HasSVE2, HasF8F32MM] in { + def FMMLA_ZZZ_BtoS : sve2_fp8_mmla<0b0, ZPR32, "fmmla">; +} + +let Predicates = [HasSVE2, HasF8F16MM] in { + def FMMLA_ZZZ_BtoH : sve2_fp8_mmla<0b1, ZPR16, "fmmla">; +} + let Predicates = [HasSSVE_FP8DOT2] in { // FP8 Widening Dot-Product - Indexed Group defm FDOT_ZZZI_BtoH : sve2_fp8_dot_indexed_h<"fdot">; diff --git a/llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp b/llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp index 8e267e65862210..5a487be5723ce9 100644 --- a/llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp +++ b/llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp @@ -6262,6 +6262,8 @@ bool AArch64AsmParser::showMatchError(SMLoc Loc, unsigned ErrCode, case Match_InvalidMatrixTileVectorV128: return Error(Loc, "invalid matrix operand, expected za[0-15]h.q or za[0-15]v.q"); + case Match_InvalidMatrixTile16: + return Error(Loc, "invalid matrix operand, expected za[0-1].h"); case Match_InvalidMatrixTile32: return Error(Loc, "invalid matrix operand, expected za[0-3].s"); case Match_InvalidMatrixTile64: @@ -6882,6 +6884,7 @@ bool AArch64AsmParser::matchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode, case Match_InvalidSVEExactFPImmOperandHalfOne: case Match_InvalidSVEExactFPImmOperandHalfTwo: case Match_InvalidSVEExactFPImmOperandZeroOne: + case Match_InvalidMatrixTile16: case Match_InvalidMatrixTile32: case Match_InvalidMatrixTile64: case Match_InvalidMatrix: diff --git a/llvm/lib/Target/AArch64/MCTargetDesc/AArch64InstPrinter.cpp b/llvm/lib/Target/AArch64/MCTargetDesc/AArch64InstPrinter.cpp index 762a7af8c3ddb3..2ee2ee5a6fa500 100644 --- a/llvm/lib/Target/AArch64/MCTargetDesc/AArch64InstPrinter.cpp +++ b/llvm/lib/Target/AArch64/MCTargetDesc/AArch64InstPrinter.cpp @@ -59,12 +59,12 @@ bool AArch64InstPrinter::applyTargetSpecificCLOption(StringRef Opt) { return false; } -void AArch64InstPrinter::printRegName(raw_ostream &OS, MCRegister Reg) const { +void AArch64InstPrinter::printRegName(raw_ostream &OS, MCRegister Reg) { markup(OS, Markup::Register) << getRegisterName(Reg); } void AArch64InstPrinter::printRegName(raw_ostream &OS, MCRegister Reg, - unsigned AltIdx) const { + unsigned AltIdx) { markup(OS, Markup::Register) << getRegisterName(Reg, AltIdx); } diff --git a/llvm/lib/Target/AArch64/MCTargetDesc/AArch64InstPrinter.h b/llvm/lib/Target/AArch64/MCTargetDesc/AArch64InstPrinter.h index e7b62b3203681b..9cf2674ae943aa 100644 --- a/llvm/lib/Target/AArch64/MCTargetDesc/AArch64InstPrinter.h +++ b/llvm/lib/Target/AArch64/MCTargetDesc/AArch64InstPrinter.h @@ -29,8 +29,8 @@ class AArch64InstPrinter : public MCInstPrinter { void printInst(const MCInst *MI, uint64_t Address, StringRef Annot, const MCSubtargetInfo &STI, raw_ostream &O) override; - void printRegName(raw_ostream &OS, MCRegister Reg) const override; - void printRegName(raw_ostream &OS, MCRegister Reg, unsigned AltIdx) const; + void printRegName(raw_ostream &OS, MCRegister Reg) override; + void printRegName(raw_ostream &OS, MCRegister Reg, unsigned AltIdx); // Autogenerated by tblgen. std::pair getMnemonic(const MCInst *MI) override; diff --git a/llvm/lib/Target/AArch64/SMEInstrFormats.td b/llvm/lib/Target/AArch64/SMEInstrFormats.td index 62a0c2e83d4a2e..b31bea712a76d0 100644 --- a/llvm/lib/Target/AArch64/SMEInstrFormats.td +++ b/llvm/lib/Target/AArch64/SMEInstrFormats.td @@ -5344,4 +5344,113 @@ multiclass sme2_multi4_fmul_mm { multiclass sme2_bfmul_multi { def _2Z2Z : sme2_multi2_fmul_mm<0b00, mnemonic, ZZ_h_mul_r>; def _4Z4Z : sme2_multi4_fmul_mm<0b00, mnemonic, ZZZZ_h_mul_r>; -} \ No newline at end of file +} + +class sme2_fp16_quarter_tile_outer_product + : I<(outs TileOp16:$ZAda), + (ins TileOp16:$_ZAda, zn_ty:$Zn, zm_ty:$Zm), + mnemonic, "\t$ZAda, $Zn, $Zm", + "", []>, Sched<[]> { + bit ZAda; + bits<3> Zn; + bits<3> Zm; + + let Inst{31-21} = 0b10000001000; + let Inst{20} = M; + let Inst{19-17} = Zm; + let Inst{16-10} = 0b0000000; + let Inst{9} = N; + let Inst{8-6} = Zn; + let Inst{5} = 0; + let Inst{4} = S; + let Inst{3-1} = 0b100; + let Inst{0} = ZAda; + + let Constraints = "$ZAda = $_ZAda"; +} + +multiclass sme2_fmop4as_fp16_non_widening { + // Single vectors + def _MZZ_H : sme2_fp16_quarter_tile_outer_product<0, 0, S, mnemonic, ZPR16Mul2_Lo, ZPR16Mul2_Hi>; + + // Multiple and single vectors + def _M2ZZ_H : sme2_fp16_quarter_tile_outer_product<0, 1, S, mnemonic, ZZ_h_mul_r_Lo, ZPR16Mul2_Hi>; + + // Single and multiple vectors + def _MZ2Z_H : sme2_fp16_quarter_tile_outer_product<1, 0, S, mnemonic, ZPR16Mul2_Lo, ZZ_h_mul_r_Hi>; + + // Multiple vectors + def _M2Z2Z_H : sme2_fp16_quarter_tile_outer_product<1, 1, S, mnemonic, ZZ_h_mul_r_Lo, ZZ_h_mul_r_Hi>; +} + +class sme2_fp8_fp32_quarter_tile_outer_product + : I<(outs TileOp32:$ZAda), + (ins TileOp32:$_ZAda, zn_ty:$Zn, zm_ty:$Zm), + mnemonic, "\t$ZAda, $Zn, $Zm", + "", []>, Sched<[]> { + bits<2> ZAda; + bits<3> Zn; + bits<3> Zm; + + let Inst{31-21} = 0b10000000001; + let Inst{20} = M; + let Inst{19-17} = Zm; + let Inst{16-10} = 0b0000000; + let Inst{9} = N; + let Inst{8-6} = Zn; + let Inst{5-2} = 0b0000; + let Inst{1-0} = ZAda; + + let Constraints = "$ZAda = $_ZAda"; +} + +multiclass sme2_fmop4a_fp8_fp32_4way { + // Single vectors + def _MZZ_BtoS : sme2_fp8_fp32_quarter_tile_outer_product<0, 0, mnemonic, ZPR8Mul2_Lo, ZPR8Mul2_Hi>; + + // Multiple and single vectors + def _M2ZZ_BtoS : sme2_fp8_fp32_quarter_tile_outer_product<0, 1, mnemonic, ZZ_b_mul_r_Lo, ZPR8Mul2_Hi>; + + // Single and multiple vectors + def _MZ2Z_BtoS : sme2_fp8_fp32_quarter_tile_outer_product<1, 0, mnemonic, ZPR8Mul2_Lo, ZZ_b_mul_r_Hi>; + + // Multiple vectors + def _M2Z2Z_BtoS : sme2_fp8_fp32_quarter_tile_outer_product<1, 1, mnemonic, ZZ_b_mul_r_Lo, ZZ_b_mul_r_Hi>; +} + +class sme2_bf16_fp16_quarter_tile_outer_product + : I<(outs TileOp16:$ZAda), + (ins TileOp16:$_ZAda, zn_ty:$Zn, zm_ty:$Zm), + mnemonic, "\t$ZAda, $Zn, $Zm", + "", []>, Sched<[]> { + bit ZAda; + bits<3> Zn; + bits<3> Zm; + + let Inst{31-21} = 0b10000001001; + let Inst{20} = M; + let Inst{19-17} = Zm; + let Inst{16-10} = 0b0000000; + let Inst{9} = N; + let Inst{8-6} = Zn; + let Inst{5} = 0; + let Inst{4} = S; + let Inst{3-1} = 0b100; + let Inst{0} = ZAda; + + let Constraints = "$ZAda = $_ZAda"; +} + +multiclass sme2_bfmop4as_non_widening { + // Single vectors + def _MZZ_H : sme2_bf16_fp16_quarter_tile_outer_product<0, 0, S, mnemonic, ZPR16Mul2_Lo, ZPR16Mul2_Hi>; + + // Multiple and single vectors + def _M2ZZ_H : sme2_bf16_fp16_quarter_tile_outer_product<0, 1, S, mnemonic, ZZ_h_mul_r_Lo, ZPR16Mul2_Hi>; + + // Single and multiple vectors + def _MZ2Z_H : sme2_bf16_fp16_quarter_tile_outer_product<1, 0, S, mnemonic, ZPR16Mul2_Lo, ZZ_h_mul_r_Hi>; + + // Multiple vectors + def _M2Z2Z_H : sme2_bf16_fp16_quarter_tile_outer_product<1, 1, S, mnemonic, ZZ_h_mul_r_Lo, ZZ_h_mul_r_Hi>; +} diff --git a/llvm/lib/Target/AArch64/SVEInstrFormats.td b/llvm/lib/Target/AArch64/SVEInstrFormats.td index 31312e00b919e2..552d5b9b23a7e4 100644 --- a/llvm/lib/Target/AArch64/SVEInstrFormats.td +++ b/llvm/lib/Target/AArch64/SVEInstrFormats.td @@ -1046,7 +1046,7 @@ multiclass sve_int_count_v opc, string asm, (!cast(NAME # "_D") ZPR64:$Zdn, PPRAny:$Pm), 0>; } -class sve_int_pcount_pred sz8_64, bits<4> opc, string asm, +class sve_int_pcount_pred sz8_64, bits<3> opc, string asm, PPRRegOp pprty> : I<(outs GPR64:$Rd), (ins PPRAny:$Pg, pprty:$Pn), asm, "\t$Rd, $Pg, $Pn", @@ -1058,17 +1058,17 @@ class sve_int_pcount_pred sz8_64, bits<4> opc, string asm, let Inst{31-24} = 0b00100101; let Inst{23-22} = sz8_64; let Inst{21-19} = 0b100; - let Inst{18-16} = opc{3-1}; + let Inst{18-16} = opc{2-0}; let Inst{15-14} = 0b10; let Inst{13-10} = Pg; - let Inst{9} = opc{0}; + let Inst{9} = 0b0; let Inst{8-5} = Pn; let Inst{4-0} = Rd; let hasSideEffects = 0; } -multiclass sve_int_pcount_pred opc, string asm, +multiclass sve_int_pcount_pred opc, string asm, SDPatternOperator int_op> { def _B : sve_int_pcount_pred<0b00, opc, asm, PPR8>; def _H : sve_int_pcount_pred<0b01, opc, asm, PPR16>; @@ -1081,6 +1081,12 @@ multiclass sve_int_pcount_pred opc, string asm, def : SVE_2_Op_Pat(NAME # _D)>; } +multiclass sve_int_pcount_pred_tmp opc, string asm> { + def _B : sve_int_pcount_pred<0b00, opc, asm, PPR8>; + def _H : sve_int_pcount_pred<0b01, opc, asm, PPR16>; + def _S : sve_int_pcount_pred<0b10, opc, asm, PPR32>; + def _D : sve_int_pcount_pred<0b11, opc, asm, PPR64>; +} //===----------------------------------------------------------------------===// // SVE Element Count Group //===----------------------------------------------------------------------===// @@ -3207,6 +3213,15 @@ multiclass sve_fp_z2op_p_zd_d_flogb { def _D : sve_fp_z2op_p_zd<0b0011011, asm, ZPR64, ZPR64>; } +multiclass sve_fp_z2op_p_zd_b_0 { + def _StoH : sve_fp_z2op_p_zd<0b1001000, asm, ZPR32, ZPR16>; + def _HtoS : sve_fp_z2op_p_zd<0b1001001, asm, ZPR16, ZPR32>; + def _DtoH : sve_fp_z2op_p_zd<0b1101000, asm, ZPR64, ZPR16>; + def _HtoD : sve_fp_z2op_p_zd<0b1101001, asm, ZPR16, ZPR64>; + def _DtoS : sve_fp_z2op_p_zd<0b1101010, asm, ZPR64, ZPR32>; + def _StoD : sve_fp_z2op_p_zd<0b1101011, asm, ZPR32, ZPR64>; +} + //===----------------------------------------------------------------------===// // SVE Integer Arithmetic - Binary Predicated Group //===----------------------------------------------------------------------===// @@ -7299,11 +7314,59 @@ class sve2_int_perm_splice_cons sz8_64, string asm, let hasSideEffects = 0; } -multiclass sve2_int_perm_splice_cons { +multiclass sve2_int_perm_splice_cons { def _B : sve2_int_perm_splice_cons<0b00, asm, ZPR8, ZZ_b>; def _H : sve2_int_perm_splice_cons<0b01, asm, ZPR16, ZZ_h>; def _S : sve2_int_perm_splice_cons<0b10, asm, ZPR32, ZZ_s>; def _D : sve2_int_perm_splice_cons<0b11, asm, ZPR64, ZZ_d>; + + let AddedComplexity = 2 in { + foreach VT = [nxv16i8] in + def : Pat<(VT (op nxv16i1:$pred, VT:$zn1, VT:$zn2)), + (!cast(NAME # _B) + nxv16i1:$pred, (REG_SEQUENCE ZPR2, VT:$zn1, zsub0, VT:$zn2, zsub1))>; + + foreach VT = [nxv8i16, nxv8f16, nxv8bf16] in + def : Pat<(VT (op nxv8i1:$pred, VT:$zn1, VT:$zn2)), + (!cast(NAME # _H) + nxv8i1:$pred, (REG_SEQUENCE ZPR2, VT:$zn1, zsub0, VT:$zn2, zsub1))>; + + foreach VT = [nxv4i32, nxv4f16, nxv4f32, nxv4bf16] in + def : Pat<(VT (op nxv4i1:$pred, VT:$zn1, VT:$zn2)), + (!cast(NAME # _S) + nxv4i1:$pred, (REG_SEQUENCE ZPR2, VT:$zn1, zsub0, VT:$zn2, zsub1))>; + + foreach VT = [nxv2i64, nxv2f16, nxv2f32, nxv2f64, nxv2bf16] in + def : Pat<(VT (op nxv2i1:$pred, VT:$zn1, VT:$zn2)), + (!cast(NAME # _D) + nxv2i1:$pred, (REG_SEQUENCE ZPR2, VT:$zn1, zsub0, VT:$zn2, zsub1))>; + } +} + +class sve2_int_perm_expand sz, string asm, + ZPRRegOp zprty> +: I<(outs zprty:$Zd), (ins PPR3bAny:$Pg, zprty:$Zn), + asm, "\t$Zd, $Pg, $Zn", + "", + []>, Sched<[]> { + bits<3> Pg; + bits<5> Zn; + bits<5> Zd; + let Inst{31-24} = 0b00000101; + let Inst{23-22} = sz; + let Inst{21-13} = 0b110001100; + let Inst{12-10} = Pg; + let Inst{9-5} = Zn; + let Inst{4-0} = Zd; + + let hasSideEffects = 0; +} + +multiclass sve2_int_perm_expand { + def _B : sve2_int_perm_expand<0b00, asm, ZPR8>; + def _H : sve2_int_perm_expand<0b01, asm, ZPR16>; + def _S : sve2_int_perm_expand<0b10, asm, ZPR32>; + def _D : sve2_int_perm_expand<0b11, asm, ZPR64>; } class sve_int_perm_rev sz8_64, bits<2> opc, string asm, @@ -7467,7 +7530,7 @@ multiclass sve_int_perm_cpy_v { (!cast(NAME # _H) $passthru, $pg, $splat)>; } -class sve_int_perm_compact +class sve_int_perm_compact sz, string asm, ZPRRegOp zprty> : I<(outs zprty:$Zd), (ins PPR3bAny:$Pg, zprty:$Zn), asm, "\t$Zd, $Pg, $Zn", "", @@ -7475,8 +7538,8 @@ class sve_int_perm_compact bits<3> Pg; bits<5> Zd; bits<5> Zn; - let Inst{31-23} = 0b000001011; - let Inst{22} = sz; + let Inst{31-24} = 0b00000101; + let Inst{23-22} = sz; let Inst{21-13} = 0b100001100; let Inst{12-10} = Pg; let Inst{9-5} = Zn; @@ -7485,9 +7548,9 @@ class sve_int_perm_compact let hasSideEffects = 0; } -multiclass sve_int_perm_compact { - def _S : sve_int_perm_compact<0b0, asm, ZPR32>; - def _D : sve_int_perm_compact<0b1, asm, ZPR64>; +multiclass sve_int_perm_compact_sd { + def _S : sve_int_perm_compact<0b10, asm, ZPR32>; + def _D : sve_int_perm_compact<0b11, asm, ZPR64>; def : SVE_2_Op_Pat(NAME # _S)>; def : SVE_2_Op_Pat(NAME # _S)>; @@ -7495,6 +7558,11 @@ multiclass sve_int_perm_compact { def : SVE_2_Op_Pat(NAME # _D)>; } +multiclass sve_int_perm_compact_bh { + def _B : sve_int_perm_compact<0b00, asm, ZPR8>; + def _H : sve_int_perm_compact<0b01, asm, ZPR16>; +} + //===----------------------------------------------------------------------===// // SVE Memory - Contiguous Load Group //===----------------------------------------------------------------------===// @@ -9042,30 +9110,6 @@ multiclass sve_float_dot_indexed opc, ZPRRegOp src1_ty, def : SVE_4_Op_Imm_Pat(NAME)>; } -class sve_bfloat_matmul -: I<(outs ZPR32:$Zda), (ins ZPR32:$_Zda, ZPR16:$Zn, ZPR16:$Zm), - asm, "\t$Zda, $Zn, $Zm", "", []>, Sched<[]> { - bits<5> Zm; - bits<5> Zda; - bits<5> Zn; - let Inst{31-21} = 0b01100100011; - let Inst{20-16} = Zm; - let Inst{15-10} = 0b111001; - let Inst{9-5} = Zn; - let Inst{4-0} = Zda; - - let Constraints = "$Zda = $_Zda"; - let DestructiveInstType = DestructiveOther; - let ElementSize = ElementSizeH; - let hasSideEffects = 0; - let mayRaiseFPException = 1; -} - -multiclass sve_bfloat_matmul { - def NAME : sve_bfloat_matmul; - def : SVE_3_Op_Pat(NAME)>; -} - class sve_bfloat_convert : I<(outs ZPR16:$Zd), (ins ZPR16:$_Zd, PPR3bAny:$Pg, ZPR32:$Zn), asm, "\t$Zd, $Pg/m, $Zn", "", []>, Sched<[]> { @@ -9188,14 +9232,14 @@ multiclass sve_int_dot_mixed_indexed { // SVE Floating Point Matrix Multiply Accumulate Group //===----------------------------------------------------------------------===// -class sve_fp_matrix_mla -: I<(outs zprty:$Zda), (ins zprty:$_Zda, zprty:$Zn, zprty:$Zm), +class sve_fp_matrix_mla opc, string asm, ZPRRegOp zda_ty, ZPRRegOp reg_ty> +: I<(outs zda_ty:$Zda), (ins zda_ty:$_Zda, reg_ty:$Zn, reg_ty:$Zm), asm, "\t$Zda, $Zn, $Zm", "", []>, Sched<[]> { bits<5> Zda; bits<5> Zn; bits<5> Zm; - let Inst{31-23} = 0b011001001; - let Inst{22} = sz; + let Inst{31-24} = 0b01100100; + let Inst{23-22} = opc; let Inst{21} = 1; let Inst{20-16} = Zm; let Inst{15-10} = 0b111001; @@ -9204,15 +9248,14 @@ class sve_fp_matrix_mla let Constraints = "$Zda = $_Zda"; let DestructiveInstType = DestructiveOther; - let ElementSize = zprty.ElementSize; let hasSideEffects = 0; let mayRaiseFPException = 1; } -multiclass sve_fp_matrix_mla { - def NAME : sve_fp_matrix_mla; +multiclass sve_fp_matrix_mla opc, string asm, ZPRRegOp zda_ty, ZPRRegOp reg_ty, SDPatternOperator op, ValueType zda_vt, ValueType reg_vt> { + def NAME : sve_fp_matrix_mla; - def : SVE_3_Op_Pat(NAME)>; + def : SVE_3_Op_Pat(NAME)>; } //===----------------------------------------------------------------------===// @@ -10632,6 +10675,28 @@ class sve2_fp8_mla_long_long_by_indexed_elem TT, string mnemonic> let Uses = [FPMR, FPCR]; } +// FP8 Matrix Multiply-accumulate Group +class sve2_fp8_mmla + : I<(outs dst_ty:$Zda), + (ins dst_ty:$_Zda, ZPR8:$Zn, ZPR8:$Zm), + mnemonic, "\t$Zda, $Zn, $Zm", + "", []>, Sched<[]>{ + bits<5> Zda; + bits<5> Zn; + bits<5> Zm; + let Inst{31-23} = 0b011001000; + let Inst{22} = opc; + let Inst{21} = 0b1; + let Inst{20-16} = Zm; + let Inst{15-10} = 0b111000; + let Inst{9-5} = Zn; + let Inst{4-0} = Zda; + let Constraints = "$Zda = $_Zda"; + let DestructiveInstType = DestructiveOther; + let ElementSize = dst_ty.ElementSize; + let Uses = [FPMR, FPCR]; +} + class sve_fp8_dot_indexed opc, ZPRRegOp dst_ty, Operand iop_ty, string mnemonic> : I<(outs dst_ty:$Zda), (ins dst_ty:$_Zda, ZPR8:$Zn, ZPR3b8:$Zm, iop_ty:$iop), mnemonic, "\t$Zda, $Zn, $Zm$iop", "", []>, Sched<[]> { diff --git a/llvm/lib/Target/AMDGPU/AMDGPUAttributor.cpp b/llvm/lib/Target/AMDGPU/AMDGPUAttributor.cpp index 687a7339da379d..6a69b9d2bfc716 100644 --- a/llvm/lib/Target/AMDGPU/AMDGPUAttributor.cpp +++ b/llvm/lib/Target/AMDGPU/AMDGPUAttributor.cpp @@ -358,7 +358,7 @@ struct AAUniformWorkGroupSizeFunction : public AAUniformWorkGroupSize { const auto *CallerInfo = A.getAAFor( *this, IRPosition::function(*Caller), DepClassTy::REQUIRED); - if (!CallerInfo) + if (!CallerInfo || !CallerInfo->isValidState()) return false; Change = Change | clampStateAndIndicateChange(this->getState(), @@ -449,7 +449,8 @@ struct AAAMDAttributesFunction : public AAAMDAttributes { // Check for Intrinsics and propagate attributes. const AACallEdges *AAEdges = A.getAAFor( *this, this->getIRPosition(), DepClassTy::REQUIRED); - if (!AAEdges || AAEdges->hasNonAsmUnknownCallee()) + if (!AAEdges || !AAEdges->isValidState() || + AAEdges->hasNonAsmUnknownCallee()) return indicatePessimisticFixpoint(); bool IsNonEntryFunc = !AMDGPU::isEntryFunctionCC(F->getCallingConv()); @@ -465,7 +466,7 @@ struct AAAMDAttributesFunction : public AAAMDAttributes { if (IID == Intrinsic::not_intrinsic) { const AAAMDAttributes *AAAMD = A.getAAFor( *this, IRPosition::function(*Callee), DepClassTy::REQUIRED); - if (!AAAMD) + if (!AAAMD || !AAAMD->isValidState()) return indicatePessimisticFixpoint(); *this &= *AAAMD; continue; @@ -660,7 +661,7 @@ struct AAAMDAttributesFunction : public AAAMDAttributes { const auto *PointerInfoAA = A.getAAFor( *this, IRPosition::callsite_returned(Call), DepClassTy::REQUIRED); - if (!PointerInfoAA) + if (!PointerInfoAA || !PointerInfoAA->getState().isValidState()) return false; return PointerInfoAA->forallInterferingAccesses( @@ -717,7 +718,7 @@ struct AAAMDSizeRangeAttribute const auto *CallerInfo = A.getAAFor( *this, IRPosition::function(*Caller), DepClassTy::REQUIRED); - if (!CallerInfo) + if (!CallerInfo || !CallerInfo->isValidState()) return false; Change |= @@ -835,7 +836,8 @@ struct AAAMDWavesPerEU : public AAAMDSizeRangeAttribute { auto &InfoCache = static_cast(A.getInfoCache()); if (const auto *AssumedGroupSize = A.getAAFor( - *this, IRPosition::function(*F), DepClassTy::REQUIRED)) { + *this, IRPosition::function(*F), DepClassTy::REQUIRED); + AssumedGroupSize->isValidState()) { unsigned Min, Max; std::tie(Min, Max) = InfoCache.getWavesPerEU( @@ -864,7 +866,8 @@ struct AAAMDWavesPerEU : public AAAMDSizeRangeAttribute { *this, IRPosition::function(*Caller), DepClassTy::REQUIRED); const auto *AssumedGroupSize = A.getAAFor( *this, IRPosition::function(*Func), DepClassTy::REQUIRED); - if (!CallerInfo || !AssumedGroupSize) + if (!CallerInfo || !AssumedGroupSize || !CallerInfo->isValidState() || + !AssumedGroupSize->isValidState()) return false; unsigned Min, Max; @@ -982,7 +985,8 @@ struct AAAMDGPUNoAGPR // TODO: Handle callsite attributes const auto *CalleeInfo = A.getAAFor( *this, IRPosition::function(*Callee), DepClassTy::REQUIRED); - return CalleeInfo && CalleeInfo->getAssumed(); + return CalleeInfo && CalleeInfo->isValidState() && + CalleeInfo->getAssumed(); }; bool UsedAssumedInformation = false; diff --git a/llvm/lib/Target/AMDGPU/AMDGPUCallingConv.td b/llvm/lib/Target/AMDGPU/AMDGPUCallingConv.td index 21412044d5a013..80969fce3d77fb 100644 --- a/llvm/lib/Target/AMDGPU/AMDGPUCallingConv.td +++ b/llvm/lib/Target/AMDGPU/AMDGPUCallingConv.td @@ -22,19 +22,13 @@ def CC_SI_Gfx : CallingConv<[ // 32 is reserved for the stack pointer // 33 is reserved for the frame pointer // 34 is reserved for the base pointer - CCIfInReg>>, - - CCIfNotInReg>>, + CCIfInReg("SGPR"#i)) // SGPR4-29 + >>>, + + CCIfNotInReg("VGPR"#i)) // VGPR0-31 + >>>, CCIfType<[i32, f32, v2i16, v2f16, i16, f16, i1, bf16, v2bf16], CCAssignToStack<4, 4>> ]>; @@ -43,93 +37,35 @@ def RetCC_SI_Gfx : CallingConv<[ CCIfType<[i1], CCPromoteToType>, CCIfType<[i1, i16], CCIfExtend>>, - CCIfNotInReg>>, + CCIfNotInReg("VGPR"#i)) // VGPR0-135 + >>>, ]>; def CC_SI_SHADER : CallingConv<[ CCIfType<[i1], CCPromoteToType>, - - CCIfInReg>>, + + CCIfInReg("SGPR"#i)) // SGPR0-43 + >>>, // 32*4 + 4 is the minimum for a fetch shader consumer with 32 inputs. - CCIfNotInReg>> + CCIfNotInReg("VGPR"#i)) // VGPR0-135 + >>> ]>; def RetCC_SI_Shader : CallingConv<[ CCIfType<[i1, i16], CCIfExtend>>, - CCIfType<[i32, i16, v2i16] , CCAssignToReg<[ - SGPR0, SGPR1, SGPR2, SGPR3, SGPR4, SGPR5, SGPR6, SGPR7, - SGPR8, SGPR9, SGPR10, SGPR11, SGPR12, SGPR13, SGPR14, SGPR15, - SGPR16, SGPR17, SGPR18, SGPR19, SGPR20, SGPR21, SGPR22, SGPR23, - SGPR24, SGPR25, SGPR26, SGPR27, SGPR28, SGPR29, SGPR30, SGPR31, - SGPR32, SGPR33, SGPR34, SGPR35, SGPR36, SGPR37, SGPR38, SGPR39, - SGPR40, SGPR41, SGPR42, SGPR43 - ]>>, + CCIfType<[i32, i16, v2i16] , CCAssignToReg< + !foreach(i, !range(0, 44), !cast("SGPR"#i)) // SGPR0-43 + >>, // 32*4 + 4 is the minimum for a fetch shader with 32 outputs. - CCIfType<[f32, f16, v2f16, bf16, v2bf16] , CCAssignToReg<[ - VGPR0, VGPR1, VGPR2, VGPR3, VGPR4, VGPR5, VGPR6, VGPR7, - VGPR8, VGPR9, VGPR10, VGPR11, VGPR12, VGPR13, VGPR14, VGPR15, - VGPR16, VGPR17, VGPR18, VGPR19, VGPR20, VGPR21, VGPR22, VGPR23, - VGPR24, VGPR25, VGPR26, VGPR27, VGPR28, VGPR29, VGPR30, VGPR31, - VGPR32, VGPR33, VGPR34, VGPR35, VGPR36, VGPR37, VGPR38, VGPR39, - VGPR40, VGPR41, VGPR42, VGPR43, VGPR44, VGPR45, VGPR46, VGPR47, - VGPR48, VGPR49, VGPR50, VGPR51, VGPR52, VGPR53, VGPR54, VGPR55, - VGPR56, VGPR57, VGPR58, VGPR59, VGPR60, VGPR61, VGPR62, VGPR63, - VGPR64, VGPR65, VGPR66, VGPR67, VGPR68, VGPR69, VGPR70, VGPR71, - VGPR72, VGPR73, VGPR74, VGPR75, VGPR76, VGPR77, VGPR78, VGPR79, - VGPR80, VGPR81, VGPR82, VGPR83, VGPR84, VGPR85, VGPR86, VGPR87, - VGPR88, VGPR89, VGPR90, VGPR91, VGPR92, VGPR93, VGPR94, VGPR95, - VGPR96, VGPR97, VGPR98, VGPR99, VGPR100, VGPR101, VGPR102, VGPR103, - VGPR104, VGPR105, VGPR106, VGPR107, VGPR108, VGPR109, VGPR110, VGPR111, - VGPR112, VGPR113, VGPR114, VGPR115, VGPR116, VGPR117, VGPR118, VGPR119, - VGPR120, VGPR121, VGPR122, VGPR123, VGPR124, VGPR125, VGPR126, VGPR127, - VGPR128, VGPR129, VGPR130, VGPR131, VGPR132, VGPR133, VGPR134, VGPR135 - ]>> + CCIfType<[f32, f16, v2f16, bf16, v2bf16] , CCAssignToReg< + !foreach(i, !range(0, 136), !cast("VGPR"#i)) // VGPR0-135 + >> ]>; def CSR_AMDGPU_VGPRs : CalleeSavedRegs< @@ -194,11 +130,9 @@ def CC_AMDGPU_Func : CallingConv<[ !foreach(i, !range(0, 30), !cast("SGPR"#i)) // SGPR0-29 >>>, - CCIfType<[i32, f32, i16, f16, v2i16, v2f16, i1, bf16, v2bf16], CCAssignToReg<[ - VGPR0, VGPR1, VGPR2, VGPR3, VGPR4, VGPR5, VGPR6, VGPR7, - VGPR8, VGPR9, VGPR10, VGPR11, VGPR12, VGPR13, VGPR14, VGPR15, - VGPR16, VGPR17, VGPR18, VGPR19, VGPR20, VGPR21, VGPR22, VGPR23, - VGPR24, VGPR25, VGPR26, VGPR27, VGPR28, VGPR29, VGPR30, VGPR31]>>, + CCIfType<[i32, f32, i16, f16, v2i16, v2f16, i1, bf16, v2bf16], CCAssignToReg< + !foreach(i, !range(0, 32), !cast("VGPR"#i)) // VGPR0-31 + >>, CCIfType<[i32, f32, v2i16, v2f16, i16, f16, i1, bf16, v2bf16], CCAssignToStack<4, 4>> ]>; @@ -206,11 +140,9 @@ def CC_AMDGPU_Func : CallingConv<[ def RetCC_AMDGPU_Func : CallingConv<[ CCIfType<[i1], CCPromoteToType>, CCIfType<[i1, i16], CCIfExtend>>, - CCIfType<[i32, f32, i16, f16, v2i16, v2f16, bf16, v2bf16], CCAssignToReg<[ - VGPR0, VGPR1, VGPR2, VGPR3, VGPR4, VGPR5, VGPR6, VGPR7, - VGPR8, VGPR9, VGPR10, VGPR11, VGPR12, VGPR13, VGPR14, VGPR15, - VGPR16, VGPR17, VGPR18, VGPR19, VGPR20, VGPR21, VGPR22, VGPR23, - VGPR24, VGPR25, VGPR26, VGPR27, VGPR28, VGPR29, VGPR30, VGPR31]>>, + CCIfType<[i32, f32, i16, f16, v2i16, v2f16, bf16, v2bf16], CCAssignToReg< + !foreach(i, !range(0, 32), !cast("VGPR"#i)) // VGPR0-31 + >>, ]>; def CC_AMDGPU : CallingConv<[ diff --git a/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp b/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp index 0f65df0763cc83..e4b54c7d72b083 100644 --- a/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp +++ b/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp @@ -512,18 +512,18 @@ AMDGPUTargetLowering::AMDGPUTargetLowering(const TargetMachine &TM, for (MVT VT : VectorIntTypes) { // Expand the following operations for the current type by default. - setOperationAction({ISD::ADD, ISD::AND, ISD::FP_TO_SINT, - ISD::FP_TO_UINT, ISD::MUL, ISD::MULHU, - ISD::MULHS, ISD::OR, ISD::SHL, - ISD::SRA, ISD::SRL, ISD::ROTL, - ISD::ROTR, ISD::SUB, ISD::SINT_TO_FP, - ISD::UINT_TO_FP, ISD::SDIV, ISD::UDIV, - ISD::SREM, ISD::UREM, ISD::SMUL_LOHI, - ISD::UMUL_LOHI, ISD::SDIVREM, ISD::UDIVREM, - ISD::SELECT, ISD::VSELECT, ISD::SELECT_CC, - ISD::XOR, ISD::BSWAP, ISD::CTPOP, - ISD::CTTZ, ISD::CTLZ, ISD::VECTOR_SHUFFLE, - ISD::SETCC}, + setOperationAction({ISD::ADD, ISD::AND, ISD::FP_TO_SINT, + ISD::FP_TO_UINT, ISD::MUL, ISD::MULHU, + ISD::MULHS, ISD::OR, ISD::SHL, + ISD::SRA, ISD::SRL, ISD::ROTL, + ISD::ROTR, ISD::SUB, ISD::SINT_TO_FP, + ISD::UINT_TO_FP, ISD::SDIV, ISD::UDIV, + ISD::SREM, ISD::UREM, ISD::SMUL_LOHI, + ISD::UMUL_LOHI, ISD::SDIVREM, ISD::UDIVREM, + ISD::SELECT, ISD::VSELECT, ISD::SELECT_CC, + ISD::XOR, ISD::BSWAP, ISD::CTPOP, + ISD::CTTZ, ISD::CTLZ, ISD::VECTOR_SHUFFLE, + ISD::SETCC, ISD::ADDRSPACECAST}, VT, Expand); } diff --git a/llvm/lib/Target/AMDGPU/AMDGPUPromoteAlloca.cpp b/llvm/lib/Target/AMDGPU/AMDGPUPromoteAlloca.cpp index f8744d6a483cff..7dd7388376f474 100644 --- a/llvm/lib/Target/AMDGPU/AMDGPUPromoteAlloca.cpp +++ b/llvm/lib/Target/AMDGPU/AMDGPUPromoteAlloca.cpp @@ -1159,7 +1159,6 @@ bool AMDGPUPromoteAllocaImpl::collectUsesWithPtrTypes( if (LoadInst *LI = dyn_cast(UseInst)) { if (LI->isVolatile()) return false; - continue; } @@ -1170,12 +1169,19 @@ bool AMDGPUPromoteAllocaImpl::collectUsesWithPtrTypes( // Reject if the stored value is not the pointer operand. if (SI->getPointerOperand() != Val) return false; - } else if (AtomicRMWInst *RMW = dyn_cast(UseInst)) { + continue; + } + + if (AtomicRMWInst *RMW = dyn_cast(UseInst)) { if (RMW->isVolatile()) return false; - } else if (AtomicCmpXchgInst *CAS = dyn_cast(UseInst)) { + continue; + } + + if (AtomicCmpXchgInst *CAS = dyn_cast(UseInst)) { if (CAS->isVolatile()) return false; + continue; } // Only promote a select if we know that the other select operand @@ -1186,6 +1192,7 @@ bool AMDGPUPromoteAllocaImpl::collectUsesWithPtrTypes( // May need to rewrite constant operands. WorkList.push_back(ICmp); + continue; } // TODO: If we know the address is only observed through flat pointers, we @@ -1198,8 +1205,9 @@ bool AMDGPUPromoteAllocaImpl::collectUsesWithPtrTypes( if (isa(User) || isa(User)) return false; + // TODO: Handle vectors of pointers. if (!User->getType()->isPointerTy()) - continue; + return false; if (GetElementPtrInst *GEP = dyn_cast(UseInst)) { // Be conservative if an address could be computed outside the bounds of @@ -1504,6 +1512,8 @@ bool AMDGPUPromoteAllocaImpl::tryPromoteAllocaToLDS(AllocaInst &I, PointerType *NewTy = PointerType::get(Context, AMDGPUAS::LOCAL_ADDRESS); + assert(isa(V->getType())); + // FIXME: It doesn't really make sense to try to do this for all // instructions. V->mutateType(NewTy); diff --git a/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUInstPrinter.cpp b/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUInstPrinter.cpp index dd8d93c3f0b72a..88caf8196b3c90 100644 --- a/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUInstPrinter.cpp +++ b/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUInstPrinter.cpp @@ -24,7 +24,7 @@ using namespace llvm; using namespace llvm::AMDGPU; -void AMDGPUInstPrinter::printRegName(raw_ostream &OS, MCRegister Reg) const { +void AMDGPUInstPrinter::printRegName(raw_ostream &OS, MCRegister Reg) { // FIXME: The current implementation of // AsmParser::parseRegisterOrRegisterNumber in MC implies we either emit this // as an integer or we provide a name which represents a physical register. diff --git a/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUInstPrinter.h b/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUInstPrinter.h index a72e0fe6ea769f..4729b8a6aa6f40 100644 --- a/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUInstPrinter.h +++ b/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUInstPrinter.h @@ -29,7 +29,7 @@ class AMDGPUInstPrinter : public MCInstPrinter { const MCSubtargetInfo &STI, raw_ostream &O); static const char *getRegisterName(MCRegister Reg); - void printRegName(raw_ostream &OS, MCRegister Reg) const override; + void printRegName(raw_ostream &OS, MCRegister Reg) override; void printInst(const MCInst *MI, uint64_t Address, StringRef Annot, const MCSubtargetInfo &STI, raw_ostream &O) override; static void printRegOperand(MCRegister Reg, raw_ostream &O, diff --git a/llvm/lib/Target/AMDGPU/SIFoldOperands.cpp b/llvm/lib/Target/AMDGPU/SIFoldOperands.cpp index c912a580854c1c..f0c7837e0bb75a 100644 --- a/llvm/lib/Target/AMDGPU/SIFoldOperands.cpp +++ b/llvm/lib/Target/AMDGPU/SIFoldOperands.cpp @@ -1793,6 +1793,9 @@ bool SIFoldOperandsImpl::tryFoldOMod(MachineInstr &MI) { DefOMod->setImm(OMod); MRI->replaceRegWith(MI.getOperand(0).getReg(), Def->getOperand(0).getReg()); + // Kill flags can be wrong if we replaced a def inside a loop with a def + // outside the loop. + MRI->clearKillFlags(Def->getOperand(0).getReg()); MI.eraseFromParent(); // Use of output modifiers forces VOP3 encoding for a VOP2 mac/fmac diff --git a/llvm/lib/Target/ARC/MCTargetDesc/ARCInstPrinter.cpp b/llvm/lib/Target/ARC/MCTargetDesc/ARCInstPrinter.cpp index d76c2810c39f8c..e669b9479369d6 100644 --- a/llvm/lib/Target/ARC/MCTargetDesc/ARCInstPrinter.cpp +++ b/llvm/lib/Target/ARC/MCTargetDesc/ARCInstPrinter.cpp @@ -93,7 +93,7 @@ static const char *ARCCondCodeToString(ARCCC::CondCode CC) { return BadConditionCode(CC); } -void ARCInstPrinter::printRegName(raw_ostream &OS, MCRegister Reg) const { +void ARCInstPrinter::printRegName(raw_ostream &OS, MCRegister Reg) { OS << StringRef(getRegisterName(Reg)).lower(); } diff --git a/llvm/lib/Target/ARC/MCTargetDesc/ARCInstPrinter.h b/llvm/lib/Target/ARC/MCTargetDesc/ARCInstPrinter.h index baf4a6915b7065..c4bd73448ca71b 100644 --- a/llvm/lib/Target/ARC/MCTargetDesc/ARCInstPrinter.h +++ b/llvm/lib/Target/ARC/MCTargetDesc/ARCInstPrinter.h @@ -30,7 +30,7 @@ class ARCInstPrinter : public MCInstPrinter { void printInstruction(const MCInst *MI, uint64_t Address, raw_ostream &O); static const char *getRegisterName(MCRegister Reg); - void printRegName(raw_ostream &OS, MCRegister Reg) const override; + void printRegName(raw_ostream &OS, MCRegister Reg) override; void printInst(const MCInst *MI, uint64_t Address, StringRef Annot, const MCSubtargetInfo &STI, raw_ostream &O) override; void printCCOperand(const MCInst *MI, int OpNum, raw_ostream &O); diff --git a/llvm/lib/Target/ARM/MCTargetDesc/ARMInstPrinter.cpp b/llvm/lib/Target/ARM/MCTargetDesc/ARMInstPrinter.cpp index e4a2f8c8f2ea0c..5a6895a4ab84ef 100644 --- a/llvm/lib/Target/ARM/MCTargetDesc/ARMInstPrinter.cpp +++ b/llvm/lib/Target/ARM/MCTargetDesc/ARMInstPrinter.cpp @@ -50,7 +50,7 @@ static unsigned translateShiftImm(unsigned imm) { } static void printRegImmShift(raw_ostream &O, ARM_AM::ShiftOpc ShOpc, - unsigned ShImm, const ARMInstPrinter &printer) { + unsigned ShImm, ARMInstPrinter &printer) { if (ShOpc == ARM_AM::no_shift || (ShOpc == ARM_AM::lsl && !ShImm)) return; O << ", "; @@ -81,7 +81,7 @@ bool ARMInstPrinter::applyTargetSpecificCLOption(StringRef Opt) { return false; } -void ARMInstPrinter::printRegName(raw_ostream &OS, MCRegister Reg) const { +void ARMInstPrinter::printRegName(raw_ostream &OS, MCRegister Reg) { markup(OS, Markup::Register) << getRegisterName(Reg, DefaultAltIdx); } diff --git a/llvm/lib/Target/ARM/MCTargetDesc/ARMInstPrinter.h b/llvm/lib/Target/ARM/MCTargetDesc/ARMInstPrinter.h index 494a644cf54546..cd1dddc5f331a3 100644 --- a/llvm/lib/Target/ARM/MCTargetDesc/ARMInstPrinter.h +++ b/llvm/lib/Target/ARM/MCTargetDesc/ARMInstPrinter.h @@ -27,7 +27,7 @@ class ARMInstPrinter : public MCInstPrinter { void printInst(const MCInst *MI, uint64_t Address, StringRef Annot, const MCSubtargetInfo &STI, raw_ostream &O) override; - void printRegName(raw_ostream &OS, MCRegister Reg) const override; + void printRegName(raw_ostream &OS, MCRegister Reg) override; // Autogenerated by tblgen. std::pair getMnemonic(const MCInst *MI) override; diff --git a/llvm/lib/Target/CSKY/CSKY.td b/llvm/lib/Target/CSKY/CSKY.td index 9809caa8bd8f65..f88daeed8d4215 100644 --- a/llvm/lib/Target/CSKY/CSKY.td +++ b/llvm/lib/Target/CSKY/CSKY.td @@ -97,28 +97,28 @@ def iHasFLOAT7E60 : Predicate<"Subtarget->hasFLOAT7E60()">, "Support CSKY float7e60 instructions">; def FeatureHWDiv : SubtargetFeature<"hwdiv", "HasHardwareDivide", "true", - "Enable divide instrutions">; + "Enable divide instructions">; def HasHWDiv : Predicate<"Subtarget->hasHardwareDivide()">, AssemblerPredicate<(all_of FeatureHWDiv), - "Enable divide instrutions">; + "Enable divide instructions">; def FeatureSTM : SubtargetFeature<"multiple_stld", "HasSTM", "true", - "Enable multiple load/store instrutions">; + "Enable multiple load/store instructions">; def HasSTM : Predicate<"Subtarget->hasSTM()">, AssemblerPredicate<(all_of FeatureSTM), - "Enable multiple load/store instrutions">; + "Enable multiple load/store instructions">; def FeaturePushPop : SubtargetFeature<"pushpop", "HasPushPop", "true", - "Enable push/pop instrutions">; + "Enable push/pop instructions">; def HasPushPop : Predicate<"Subtarget->hasPushPop()">, AssemblerPredicate<(all_of FeaturePushPop), - "Enable push/pop instrutions">; + "Enable push/pop instructions">; def FeatureDSP - : SubtargetFeature<"edsp", "HasDSP", "true", "Enable DSP instrutions">; + : SubtargetFeature<"edsp", "HasDSP", "true", "Enable DSP instructions">; def HasDSP : Predicate<"Subtarget->hasDSP()">, AssemblerPredicate<(all_of FeatureDSP), - "Enable DSP instrutions">; + "Enable DSP instructions">; def HasDSP1E2 : SubtargetFeature<"dsp1e2", "HasDSP1E2", "true", "Support CSKY dsp1e2 instructions">; @@ -133,16 +133,16 @@ def iHasDSPE60 : Predicate<"Subtarget->hasDSPE60()">, "Support CSKY dspe60 instructions">; def FeatureDSPV2 : SubtargetFeature<"dspv2", "HasDSPV2", "true", - "Enable DSP V2.0 instrutions">; + "Enable DSP V2.0 instructions">; def HasDSPV2 : Predicate<"Subtarget->hasDSPV2()">, AssemblerPredicate<(all_of FeatureDSPV2), - "Enable DSP V2.0 instrutions">; + "Enable DSP V2.0 instructions">; def FeatureDSP_Silan : SubtargetFeature<"dsp_silan", "HasDSP_Silan", "true", - "Enable DSP Silan instrutions">; + "Enable DSP Silan instructions">; def HasDSP_Silan : Predicate<"Subtarget->hasDSP_Silan()">, AssemblerPredicate<(all_of FeatureDSP_Silan), - "Enable DSP Silan instrutions">; + "Enable DSP Silan instructions">; // Atomic Support def FeatureBTST16 : SubtargetFeature<"btst16", "HasBTST16", "true", @@ -232,11 +232,11 @@ def FeatureSoftTP : SubtargetFeature<"soft-tp", "ReadTPHard", "false", "Disable TLS Pointer register">; def FeatureIstack : SubtargetFeature<"istack", "EnableInterruptAttribute", - "true", "Enable interrput attribute">; + "true", "Enable interrupt attribute">; def EnableInterruptAttribute : Predicate<"Subtarget->enableInterruptAttribute()">, AssemblerPredicate<(all_of FeatureIstack), - "Enable interrput attribute">; + "Enable interrupt attribute">; def FeatureConstPool : SubtargetFeature<"constpool", "DumpConstPool", "true", "Dump the constant pool by compiler">; diff --git a/llvm/lib/Target/CSKY/MCTargetDesc/CSKYInstPrinter.cpp b/llvm/lib/Target/CSKY/MCTargetDesc/CSKYInstPrinter.cpp index 9af7958112fce3..a4b0d8488cf53b 100644 --- a/llvm/lib/Target/CSKY/MCTargetDesc/CSKYInstPrinter.cpp +++ b/llvm/lib/Target/CSKY/MCTargetDesc/CSKYInstPrinter.cpp @@ -82,7 +82,7 @@ void CSKYInstPrinter::printInst(const MCInst *MI, uint64_t Address, printAnnotation(O, Annot); } -void CSKYInstPrinter::printRegName(raw_ostream &O, MCRegister Reg) const { +void CSKYInstPrinter::printRegName(raw_ostream &O, MCRegister Reg) { if (PrintBranchImmAsAddress) O << getRegisterName(Reg, ABIRegNames ? CSKY::ABIRegAltName : CSKY::NoRegAltName); diff --git a/llvm/lib/Target/CSKY/MCTargetDesc/CSKYInstPrinter.h b/llvm/lib/Target/CSKY/MCTargetDesc/CSKYInstPrinter.h index 461d7f6f12b371..16eccfdfb5ce5b 100644 --- a/llvm/lib/Target/CSKY/MCTargetDesc/CSKYInstPrinter.h +++ b/llvm/lib/Target/CSKY/MCTargetDesc/CSKYInstPrinter.h @@ -31,7 +31,7 @@ class CSKYInstPrinter : public MCInstPrinter { void printInst(const MCInst *MI, uint64_t Address, StringRef Annot, const MCSubtargetInfo &STI, raw_ostream &O) override; - void printRegName(raw_ostream &O, MCRegister Reg) const override; + void printRegName(raw_ostream &O, MCRegister Reg) override; void printOperand(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI, raw_ostream &O, const char *Modifier = nullptr); diff --git a/llvm/lib/Target/DirectX/DXIL.td b/llvm/lib/Target/DirectX/DXIL.td index 68ae5de06423c2..263ca50011aa7b 100644 --- a/llvm/lib/Target/DirectX/DXIL.td +++ b/llvm/lib/Target/DirectX/DXIL.td @@ -294,6 +294,43 @@ class Attributes attrs> { list op_attrs = attrs; } +class DXILConstant { + int value = value_; +} + +defset list BarrierModes = { + def BarrierMode_DeviceMemoryBarrier : DXILConstant<2>; + def BarrierMode_DeviceMemoryBarrierWithGroupSync : DXILConstant<3>; + def BarrierMode_GroupMemoryBarrier : DXILConstant<8>; + def BarrierMode_GroupMemoryBarrierWithGroupSync : DXILConstant<9>; + def BarrierMode_AllMemoryBarrier : DXILConstant<10>; + def BarrierMode_AllMemoryBarrierWithGroupSync : DXILConstant<11>; +} + +// Intrinsic arg selection +class Arg { + int index = -1; + DXILConstant value; + bit is_i8 = 0; + bit is_i32 = 0; +} +class ArgSelect : Arg { + let index = index_; +} +class ArgI32 : Arg { + let value = value_; + let is_i32 = 1; +} +class ArgI8 : Arg { + let value = value_; + let is_i8 = 1; +} + +class IntrinsicSelect args_> { + Intrinsic intrinsic = intrinsic_; + list args = args_; +} + // Abstraction DXIL Operation class DXILOp { // A short description of the operation @@ -308,6 +345,9 @@ class DXILOp { // LLVM Intrinsic DXIL Operation maps to Intrinsic LLVMIntrinsic = ?; + // Non-trivial LLVM Intrinsics DXIL Operation maps to + list intrinsic_selects = []; + // Result type of the op DXILOpParamType result; @@ -554,11 +594,10 @@ def Rbits : DXILOp<30, unary> { let attributes = [Attributes]; } -def CBits : DXILOp<31, unary> { +def CountBits : DXILOp<31, unaryBits> { let Doc = "Returns the number of 1 bits in the specified value."; - let LLVMIntrinsic = int_ctpop; let arguments = [OverloadTy]; - let result = OverloadTy; + let result = Int32Ty; let overloads = [Overloads]; let stages = [Stages]; @@ -830,3 +869,17 @@ def WaveGetLaneIndex : DXILOp<111, waveGetLaneIndex> { let stages = [Stages]; let attributes = [Attributes]; } + +def Barrier : DXILOp<80, barrier> { + let Doc = "inserts a memory barrier in the shader"; + let intrinsic_selects = [ + IntrinsicSelect< + int_dx_group_memory_barrier_with_group_sync, + [ ArgI32 ]>, + ]; + + let arguments = [Int32Ty]; + let result = VoidTy; + let stages = [Stages]; + let attributes = [Attributes]; +} diff --git a/llvm/lib/Target/DirectX/DXILOpLowering.cpp b/llvm/lib/Target/DirectX/DXILOpLowering.cpp index f7722d77074764..b5cf1654181c6c 100644 --- a/llvm/lib/Target/DirectX/DXILOpLowering.cpp +++ b/llvm/lib/Target/DirectX/DXILOpLowering.cpp @@ -106,17 +106,43 @@ class OpLowerer { return false; } - [[nodiscard]] - bool replaceFunctionWithOp(Function &F, dxil::OpCode DXILOp) { + struct ArgSelect { + enum class Type { + Index, + I8, + I32, + }; + Type Type = Type::Index; + int Value = -1; + }; + + [[nodiscard]] bool replaceFunctionWithOp(Function &F, dxil::OpCode DXILOp, + ArrayRef ArgSelects) { bool IsVectorArgExpansion = isVectorArgExpansion(F); return replaceFunction(F, [&](CallInst *CI) -> Error { - SmallVector Args; OpBuilder.getIRB().SetInsertPoint(CI); - if (IsVectorArgExpansion) { - SmallVector NewArgs = argVectorFlatten(CI, OpBuilder.getIRB()); - Args.append(NewArgs.begin(), NewArgs.end()); - } else + SmallVector Args; + if (ArgSelects.size()) { + for (const ArgSelect &A : ArgSelects) { + switch (A.Type) { + case ArgSelect::Type::Index: + Args.push_back(CI->getArgOperand(A.Value)); + break; + case ArgSelect::Type::I8: + Args.push_back(OpBuilder.getIRB().getInt8((uint8_t)A.Value)); + break; + case ArgSelect::Type::I32: + Args.push_back(OpBuilder.getIRB().getInt32(A.Value)); + break; + default: + llvm_unreachable("Invalid type of intrinsic arg select."); + } + } + } else if (IsVectorArgExpansion) { + Args = argVectorFlatten(CI, OpBuilder.getIRB()); + } else { Args.append(CI->arg_begin(), CI->arg_end()); + } Expected OpCall = OpBuilder.tryCreateOp(DXILOp, Args, CI->getName(), F.getReturnType()); @@ -505,6 +531,73 @@ class OpLowerer { }); } + [[nodiscard]] bool lowerCtpopToCountBits(Function &F) { + IRBuilder<> &IRB = OpBuilder.getIRB(); + Type *Int32Ty = IRB.getInt32Ty(); + + return replaceFunction(F, [&](CallInst *CI) -> Error { + IRB.SetInsertPoint(CI); + SmallVector Args; + Args.append(CI->arg_begin(), CI->arg_end()); + + Type *RetTy = Int32Ty; + Type *FRT = F.getReturnType(); + if (const auto *VT = dyn_cast(FRT)) + RetTy = VectorType::get(RetTy, VT); + + Expected OpCall = OpBuilder.tryCreateOp( + dxil::OpCode::CountBits, Args, CI->getName(), RetTy); + if (Error E = OpCall.takeError()) + return E; + + // If the result type is 32 bits we can do a direct replacement. + if (FRT->isIntOrIntVectorTy(32)) { + CI->replaceAllUsesWith(*OpCall); + CI->eraseFromParent(); + return Error::success(); + } + + unsigned CastOp; + unsigned CastOp2; + if (FRT->isIntOrIntVectorTy(16)) { + CastOp = Instruction::ZExt; + CastOp2 = Instruction::SExt; + } else { // must be 64 bits + assert(FRT->isIntOrIntVectorTy(64) && + "Currently only lowering 16, 32, or 64 bit ctpop to CountBits \ + is supported."); + CastOp = Instruction::Trunc; + CastOp2 = Instruction::Trunc; + } + + // It is correct to replace the ctpop with the dxil op and + // remove all casts to i32 + bool NeedsCast = false; + for (User *User : make_early_inc_range(CI->users())) { + Instruction *I = dyn_cast(User); + if (I && (I->getOpcode() == CastOp || I->getOpcode() == CastOp2) && + I->getType() == RetTy) { + I->replaceAllUsesWith(*OpCall); + I->eraseFromParent(); + } else + NeedsCast = true; + } + + // It is correct to replace a ctpop with the dxil op and + // a cast from i32 to the return type of the ctpop + // the cast is emitted here if there is a non-cast to i32 + // instr which uses the ctpop + if (NeedsCast) { + Value *Cast = + IRB.CreateZExtOrTrunc(*OpCall, F.getReturnType(), "ctpop.cast"); + CI->replaceAllUsesWith(Cast); + } + + CI->eraseFromParent(); + return Error::success(); + }); + } + bool lowerIntrinsics() { bool Updated = false; bool HasErrors = false; @@ -516,9 +609,10 @@ class OpLowerer { switch (ID) { default: continue; -#define DXIL_OP_INTRINSIC(OpCode, Intrin) \ +#define DXIL_OP_INTRINSIC(OpCode, Intrin, ...) \ case Intrin: \ - HasErrors |= replaceFunctionWithOp(F, OpCode); \ + HasErrors |= \ + replaceFunctionWithOp(F, OpCode, ArrayRef{__VA_ARGS__}); \ break; #include "DXILOperation.inc" case Intrinsic::dx_handle_fromBinding: @@ -543,6 +637,9 @@ class OpLowerer { return replaceSplitDoubleCallUsages(CI, Op); }); break; + case Intrinsic::ctpop: + HasErrors |= lowerCtpopToCountBits(F); + break; } Updated = true; } diff --git a/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonInstPrinter.cpp b/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonInstPrinter.cpp index de5c8b86978a82..e4e84a80b5d0bc 100644 --- a/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonInstPrinter.cpp +++ b/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonInstPrinter.cpp @@ -26,7 +26,7 @@ using namespace llvm; #define GET_INSTRUCTION_NAME #include "HexagonGenAsmWriter.inc" -void HexagonInstPrinter::printRegName(raw_ostream &O, MCRegister Reg) const { +void HexagonInstPrinter::printRegName(raw_ostream &O, MCRegister Reg) { O << getRegisterName(Reg); } diff --git a/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonInstPrinter.h b/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonInstPrinter.h index 38a9081c93fe79..fe37cd91dabc6a 100644 --- a/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonInstPrinter.h +++ b/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonInstPrinter.h @@ -30,7 +30,7 @@ class HexagonInstPrinter : public MCInstPrinter { void printInst(MCInst const *MI, uint64_t Address, StringRef Annot, const MCSubtargetInfo &STI, raw_ostream &O) override; - void printRegName(raw_ostream &O, MCRegister Reg) const override; + void printRegName(raw_ostream &O, MCRegister Reg) override; static char const *getRegisterName(MCRegister Reg); diff --git a/llvm/lib/Target/Lanai/MCTargetDesc/LanaiInstPrinter.cpp b/llvm/lib/Target/Lanai/MCTargetDesc/LanaiInstPrinter.cpp index 0265a75fb346c9..4b5751eaedda05 100644 --- a/llvm/lib/Target/Lanai/MCTargetDesc/LanaiInstPrinter.cpp +++ b/llvm/lib/Target/Lanai/MCTargetDesc/LanaiInstPrinter.cpp @@ -31,7 +31,7 @@ using namespace llvm; #define PRINT_ALIAS_INSTR #include "LanaiGenAsmWriter.inc" -void LanaiInstPrinter::printRegName(raw_ostream &OS, MCRegister Reg) const { +void LanaiInstPrinter::printRegName(raw_ostream &OS, MCRegister Reg) { OS << StringRef(getRegisterName(Reg)).lower(); } diff --git a/llvm/lib/Target/Lanai/MCTargetDesc/LanaiInstPrinter.h b/llvm/lib/Target/Lanai/MCTargetDesc/LanaiInstPrinter.h index 55a254036fee5b..851613b27e3dd9 100644 --- a/llvm/lib/Target/Lanai/MCTargetDesc/LanaiInstPrinter.h +++ b/llvm/lib/Target/Lanai/MCTargetDesc/LanaiInstPrinter.h @@ -49,7 +49,7 @@ class LanaiInstPrinter : public MCInstPrinter { unsigned OpIdx, unsigned PrintMethodIdx, raw_ostream &O); static const char *getRegisterName(MCRegister Reg); - void printRegName(raw_ostream &OS, MCRegister Reg) const override; + void printRegName(raw_ostream &OS, MCRegister Reg) override; private: bool printAlias(const MCInst *MI, raw_ostream &Ostream); diff --git a/llvm/lib/Target/LoongArch/MCTargetDesc/LoongArchInstPrinter.cpp b/llvm/lib/Target/LoongArch/MCTargetDesc/LoongArchInstPrinter.cpp index cb2521db5217e8..e3007cfe3d401b 100644 --- a/llvm/lib/Target/LoongArch/MCTargetDesc/LoongArchInstPrinter.cpp +++ b/llvm/lib/Target/LoongArch/MCTargetDesc/LoongArchInstPrinter.cpp @@ -56,7 +56,7 @@ void LoongArchInstPrinter::printInst(const MCInst *MI, uint64_t Address, printAnnotation(O, Annot); } -void LoongArchInstPrinter::printRegName(raw_ostream &O, MCRegister Reg) const { +void LoongArchInstPrinter::printRegName(raw_ostream &O, MCRegister Reg) { O << '$' << getRegisterName(Reg); } diff --git a/llvm/lib/Target/LoongArch/MCTargetDesc/LoongArchInstPrinter.h b/llvm/lib/Target/LoongArch/MCTargetDesc/LoongArchInstPrinter.h index 4e6092bfcb1282..8cda3fdb4510e5 100644 --- a/llvm/lib/Target/LoongArch/MCTargetDesc/LoongArchInstPrinter.h +++ b/llvm/lib/Target/LoongArch/MCTargetDesc/LoongArchInstPrinter.h @@ -28,7 +28,7 @@ class LoongArchInstPrinter : public MCInstPrinter { void printInst(const MCInst *MI, uint64_t Address, StringRef Annot, const MCSubtargetInfo &STI, raw_ostream &O) override; - void printRegName(raw_ostream &O, MCRegister Reg) const override; + void printRegName(raw_ostream &O, MCRegister Reg) override; void printAtomicMemOp(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI, raw_ostream &O); diff --git a/llvm/lib/Target/M68k/MCTargetDesc/M68kInstPrinter.cpp b/llvm/lib/Target/M68k/MCTargetDesc/M68kInstPrinter.cpp index 84800fc762cbb8..68ac15b57508c1 100644 --- a/llvm/lib/Target/M68k/MCTargetDesc/M68kInstPrinter.cpp +++ b/llvm/lib/Target/M68k/MCTargetDesc/M68kInstPrinter.cpp @@ -41,7 +41,7 @@ using namespace llvm; #define PRINT_ALIAS_INSTR #include "M68kGenAsmWriter.inc" -void M68kInstPrinter::printRegName(raw_ostream &OS, MCRegister Reg) const { +void M68kInstPrinter::printRegName(raw_ostream &OS, MCRegister Reg) { OS << "%" << getRegisterName(Reg); } diff --git a/llvm/lib/Target/M68k/MCTargetDesc/M68kInstPrinter.h b/llvm/lib/Target/M68k/MCTargetDesc/M68kInstPrinter.h index 0963176304587c..d6d17ca9568e02 100644 --- a/llvm/lib/Target/M68k/MCTargetDesc/M68kInstPrinter.h +++ b/llvm/lib/Target/M68k/MCTargetDesc/M68kInstPrinter.h @@ -34,7 +34,7 @@ class M68kInstPrinter : public MCInstPrinter, void printInstruction(const MCInst *MI, uint64_t Address, raw_ostream &O); static const char *getRegisterName(MCRegister Reg); - void printRegName(raw_ostream &OS, MCRegister Reg) const override; + void printRegName(raw_ostream &OS, MCRegister Reg) override; void printInst(const MCInst *MI, uint64_t Address, StringRef Annot, const MCSubtargetInfo &STI, raw_ostream &O) override; diff --git a/llvm/lib/Target/MSP430/MCTargetDesc/MSP430InstPrinter.cpp b/llvm/lib/Target/MSP430/MCTargetDesc/MSP430InstPrinter.cpp index 3726c600f4a7b8..d8a27f34c6fd13 100644 --- a/llvm/lib/Target/MSP430/MCTargetDesc/MSP430InstPrinter.cpp +++ b/llvm/lib/Target/MSP430/MCTargetDesc/MSP430InstPrinter.cpp @@ -26,7 +26,7 @@ using namespace llvm; #define PRINT_ALIAS_INSTR #include "MSP430GenAsmWriter.inc" -void MSP430InstPrinter::printRegName(raw_ostream &O, MCRegister Reg) const { +void MSP430InstPrinter::printRegName(raw_ostream &O, MCRegister Reg) { O << getRegisterName(Reg); } diff --git a/llvm/lib/Target/MSP430/MCTargetDesc/MSP430InstPrinter.h b/llvm/lib/Target/MSP430/MCTargetDesc/MSP430InstPrinter.h index 40605b92bcb01a..413492b8efeeda 100644 --- a/llvm/lib/Target/MSP430/MCTargetDesc/MSP430InstPrinter.h +++ b/llvm/lib/Target/MSP430/MCTargetDesc/MSP430InstPrinter.h @@ -22,7 +22,7 @@ namespace llvm { const MCRegisterInfo &MRI) : MCInstPrinter(MAI, MII, MRI) {} - void printRegName(raw_ostream &O, MCRegister Reg) const override; + void printRegName(raw_ostream &O, MCRegister Reg) override; void printInst(const MCInst *MI, uint64_t Address, StringRef Annot, const MCSubtargetInfo &STI, raw_ostream &O) override; diff --git a/llvm/lib/Target/Mips/MCTargetDesc/MipsInstPrinter.cpp b/llvm/lib/Target/Mips/MCTargetDesc/MipsInstPrinter.cpp index 1518a539782efb..2fd1b344eb687e 100644 --- a/llvm/lib/Target/Mips/MCTargetDesc/MipsInstPrinter.cpp +++ b/llvm/lib/Target/Mips/MCTargetDesc/MipsInstPrinter.cpp @@ -72,7 +72,7 @@ const char* Mips::MipsFCCToString(Mips::CondCode CC) { llvm_unreachable("Impossible condition code!"); } -void MipsInstPrinter::printRegName(raw_ostream &OS, MCRegister Reg) const { +void MipsInstPrinter::printRegName(raw_ostream &OS, MCRegister Reg) { markup(OS, Markup::Register) << '$' << StringRef(getRegisterName(Reg)).lower(); } diff --git a/llvm/lib/Target/Mips/MCTargetDesc/MipsInstPrinter.h b/llvm/lib/Target/Mips/MCTargetDesc/MipsInstPrinter.h index 0652b237509fe3..8e3b4614a4aade 100644 --- a/llvm/lib/Target/Mips/MCTargetDesc/MipsInstPrinter.h +++ b/llvm/lib/Target/Mips/MCTargetDesc/MipsInstPrinter.h @@ -84,7 +84,7 @@ class MipsInstPrinter : public MCInstPrinter { const MCSubtargetInfo &STI, raw_ostream &O); static const char *getRegisterName(MCRegister Reg); - void printRegName(raw_ostream &OS, MCRegister Reg) const override; + void printRegName(raw_ostream &OS, MCRegister Reg) override; void printInst(const MCInst *MI, uint64_t Address, StringRef Annot, const MCSubtargetInfo &STI, raw_ostream &O) override; diff --git a/llvm/lib/Target/NVPTX/MCTargetDesc/NVPTXInstPrinter.cpp b/llvm/lib/Target/NVPTX/MCTargetDesc/NVPTXInstPrinter.cpp index 9b589284463294..4211ae5a2eebcd 100644 --- a/llvm/lib/Target/NVPTX/MCTargetDesc/NVPTXInstPrinter.cpp +++ b/llvm/lib/Target/NVPTX/MCTargetDesc/NVPTXInstPrinter.cpp @@ -34,7 +34,7 @@ NVPTXInstPrinter::NVPTXInstPrinter(const MCAsmInfo &MAI, const MCInstrInfo &MII, const MCRegisterInfo &MRI) : MCInstPrinter(MAI, MII, MRI) {} -void NVPTXInstPrinter::printRegName(raw_ostream &OS, MCRegister Reg) const { +void NVPTXInstPrinter::printRegName(raw_ostream &OS, MCRegister Reg) { // Decode the virtual register // Must be kept in sync with NVPTXAsmPrinter::encodeVirtualRegister unsigned RCId = (Reg.id() >> 28); diff --git a/llvm/lib/Target/NVPTX/MCTargetDesc/NVPTXInstPrinter.h b/llvm/lib/Target/NVPTX/MCTargetDesc/NVPTXInstPrinter.h index e8a4a6dbdd5324..63207e8a975ace 100644 --- a/llvm/lib/Target/NVPTX/MCTargetDesc/NVPTXInstPrinter.h +++ b/llvm/lib/Target/NVPTX/MCTargetDesc/NVPTXInstPrinter.h @@ -24,7 +24,7 @@ class NVPTXInstPrinter : public MCInstPrinter { NVPTXInstPrinter(const MCAsmInfo &MAI, const MCInstrInfo &MII, const MCRegisterInfo &MRI); - void printRegName(raw_ostream &OS, MCRegister Reg) const override; + void printRegName(raw_ostream &OS, MCRegister Reg) override; void printInst(const MCInst *MI, uint64_t Address, StringRef Annot, const MCSubtargetInfo &STI, raw_ostream &OS) override; diff --git a/llvm/lib/Target/NVPTX/NVPTXInstrInfo.td b/llvm/lib/Target/NVPTX/NVPTXInstrInfo.td index 5f6cba397c5352..1ca3aefb0b0934 100644 --- a/llvm/lib/Target/NVPTX/NVPTXInstrInfo.td +++ b/llvm/lib/Target/NVPTX/NVPTXInstrInfo.td @@ -1922,7 +1922,7 @@ def imem : Operand { let PrintMethod = "printOperand"; } -def imemAny : Operand { +def imemAny : Operand { let PrintMethod = "printOperand"; } diff --git a/llvm/lib/Target/NVPTX/NVPTXTargetMachine.cpp b/llvm/lib/Target/NVPTX/NVPTXTargetMachine.cpp index 1d6f39b290536a..a5a147da8da1c5 100644 --- a/llvm/lib/Target/NVPTX/NVPTXTargetMachine.cpp +++ b/llvm/lib/Target/NVPTX/NVPTXTargetMachine.cpp @@ -332,7 +332,7 @@ void NVPTXPassConfig::addIRPasses() { disablePass(&PrologEpilogCodeInserterID); disablePass(&MachineLateInstrsCleanupID); disablePass(&MachineCopyPropagationID); - disablePass(&TailDuplicateID); + disablePass(&TailDuplicateLegacyID); disablePass(&StackMapLivenessID); disablePass(&PostRAMachineSinkingID); disablePass(&PostRASchedulerID); @@ -461,7 +461,7 @@ void NVPTXPassConfig::addOptimizedRegAlloc() { void NVPTXPassConfig::addMachineSSAOptimization() { // Pre-ra tail duplication. - if (addPass(&EarlyTailDuplicateID)) + if (addPass(&EarlyTailDuplicateLegacyID)) printAndVerify("After Pre-RegAlloc TailDuplicate"); // Optimize PHIs before DCE: removing dead PHI cycles may make more diff --git a/llvm/lib/Target/PowerPC/MCTargetDesc/PPCInstPrinter.cpp b/llvm/lib/Target/PowerPC/MCTargetDesc/PPCInstPrinter.cpp index 9a4291c90408d6..7511e24f705c18 100644 --- a/llvm/lib/Target/PowerPC/MCTargetDesc/PPCInstPrinter.cpp +++ b/llvm/lib/Target/PowerPC/MCTargetDesc/PPCInstPrinter.cpp @@ -47,7 +47,7 @@ FullRegNamesWithPercent("ppc-reg-with-percent-prefix", cl::Hidden, #define PRINT_ALIAS_INSTR #include "PPCGenAsmWriter.inc" -void PPCInstPrinter::printRegName(raw_ostream &OS, MCRegister Reg) const { +void PPCInstPrinter::printRegName(raw_ostream &OS, MCRegister Reg) { const char *RegName = getRegisterName(Reg); OS << RegName; } diff --git a/llvm/lib/Target/PowerPC/MCTargetDesc/PPCInstPrinter.h b/llvm/lib/Target/PowerPC/MCTargetDesc/PPCInstPrinter.h index 6ba3eb4c79dc99..1b9365fa04961c 100644 --- a/llvm/lib/Target/PowerPC/MCTargetDesc/PPCInstPrinter.h +++ b/llvm/lib/Target/PowerPC/MCTargetDesc/PPCInstPrinter.h @@ -31,7 +31,7 @@ class PPCInstPrinter : public MCInstPrinter { const MCRegisterInfo &MRI, Triple T) : MCInstPrinter(MAI, MII, MRI), TT(T) {} - void printRegName(raw_ostream &OS, MCRegister Reg) const override; + void printRegName(raw_ostream &OS, MCRegister Reg) override; void printInst(const MCInst *MI, uint64_t Address, StringRef Annot, const MCSubtargetInfo &STI, raw_ostream &O) override; diff --git a/llvm/lib/Target/PowerPC/PPCISelLowering.cpp b/llvm/lib/Target/PowerPC/PPCISelLowering.cpp index ab31898e262e7e..d8f3095ed7fb68 100644 --- a/llvm/lib/Target/PowerPC/PPCISelLowering.cpp +++ b/llvm/lib/Target/PowerPC/PPCISelLowering.cpp @@ -200,6 +200,11 @@ PPCTargetLowering::PPCTargetLowering(const PPCTargetMachine &TM, setOperationAction(ISD::UADDO, isPPC64 ? MVT::i64 : MVT::i32, Custom); + // On P10, the default lowering generates better code using the + // setbc instruction. + if (!Subtarget.hasP10Vector() && isPPC64) + setOperationAction(ISD::SSUBO, MVT::i32, Custom); + // Match BITREVERSE to customized fast code sequence in the td file. setOperationAction(ISD::BITREVERSE, MVT::i32, Legal); setOperationAction(ISD::BITREVERSE, MVT::i64, Legal); @@ -12016,6 +12021,36 @@ SDValue PPCTargetLowering::LowerUaddo(SDValue Op, SelectionDAG &DAG) const { return Res; } +SDValue PPCTargetLowering::LowerSSUBO(SDValue Op, SelectionDAG &DAG) const { + + SDLoc dl(Op); + + SDValue LHS64 = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i64, Op.getOperand(0)); + SDValue RHS64 = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i64, Op.getOperand(1)); + + SDValue Sub = DAG.getNode(ISD::SUB, dl, MVT::i64, LHS64, RHS64); + + SDValue Extsw = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, MVT::i64, Sub, + DAG.getValueType(MVT::i32)); + + SDValue Xor = DAG.getNode(ISD::XOR, dl, MVT::i64, Extsw, Sub); + + SDValue Addic = DAG.getNode(ISD::ADDC, dl, DAG.getVTList(MVT::i64, MVT::Glue), + Xor, DAG.getConstant(-1, dl, MVT::i64)); + + SDValue Overflow = + DAG.getNode(ISD::SUBE, dl, DAG.getVTList(MVT::i64, MVT::Glue), Xor, Addic, + Addic.getValue(1)); + + SDValue OverflowTrunc = + DAG.getNode(ISD::TRUNCATE, dl, Op.getNode()->getValueType(1), Overflow); + SDValue SubTrunc = + (Sub->getValueType(0) != Op.getNode()->getValueType(0)) + ? DAG.getNode(ISD::TRUNCATE, dl, Op.getNode()->getValueType(0), Sub) + : Sub; + return DAG.getMergeValues({SubTrunc, OverflowTrunc}, dl); +} + /// LowerOperation - Provide custom lowering hooks for some operations. /// SDValue PPCTargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const { @@ -12038,6 +12073,8 @@ SDValue PPCTargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const { case ISD::SETCC: return LowerSETCC(Op, DAG); case ISD::INIT_TRAMPOLINE: return LowerINIT_TRAMPOLINE(Op, DAG); case ISD::ADJUST_TRAMPOLINE: return LowerADJUST_TRAMPOLINE(Op, DAG); + case ISD::SSUBO: + return LowerSSUBO(Op, DAG); case ISD::INLINEASM: case ISD::INLINEASM_BR: return LowerINLINEASM(Op, DAG); diff --git a/llvm/lib/Target/PowerPC/PPCISelLowering.h b/llvm/lib/Target/PowerPC/PPCISelLowering.h index 0adbad86845973..dde45e4cf6f4ae 100644 --- a/llvm/lib/Target/PowerPC/PPCISelLowering.h +++ b/llvm/lib/Target/PowerPC/PPCISelLowering.h @@ -1279,6 +1279,7 @@ namespace llvm { SDValue LowerJumpTable(SDValue Op, SelectionDAG &DAG) const; SDValue LowerUaddo(SDValue Op, SelectionDAG &DAG) const; SDValue LowerSETCC(SDValue Op, SelectionDAG &DAG) const; + SDValue LowerSSUBO(SDValue Op, SelectionDAG &DAG) const; SDValue LowerINIT_TRAMPOLINE(SDValue Op, SelectionDAG &DAG) const; SDValue LowerADJUST_TRAMPOLINE(SDValue Op, SelectionDAG &DAG) const; SDValue LowerINLINEASM(SDValue Op, SelectionDAG &DAG) const; diff --git a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h index d82f78498418da..b3a6cd40ea039b 100644 --- a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h +++ b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h @@ -330,7 +330,18 @@ enum OperandType : unsigned { OPERAND_RVKRNUM_1_10, OPERAND_RVKRNUM_2_14, OPERAND_SPIMM, - OPERAND_LAST_RISCV_IMM = OPERAND_SPIMM, + // Operand is a 3-bit rounding mode, '111' indicates FRM register. + // Represents 'frm' argument passing to floating-point operations. + OPERAND_FRMARG, + // Operand is a 3-bit rounding mode where only RTZ is valid. + OPERAND_RTZARG, + // Condition code used by select and short forward branch pseudos. + OPERAND_COND_CODE, + // Vector policy operand. + OPERAND_VEC_POLICY, + // Vector SEW operand. + OPERAND_SEW, + OPERAND_LAST_RISCV_IMM = OPERAND_SEW, // Operand is either a register or uimm5, this is used by V extension pseudo // instructions to represent a value that be passed as AVL to either vsetvli // or vsetivli. diff --git a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVInstPrinter.cpp b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVInstPrinter.cpp index 1f27c934baf0dc..1445e9da4a622d 100644 --- a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVInstPrinter.cpp +++ b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVInstPrinter.cpp @@ -75,7 +75,7 @@ void RISCVInstPrinter::printInst(const MCInst *MI, uint64_t Address, printAnnotation(O, Annot); } -void RISCVInstPrinter::printRegName(raw_ostream &O, MCRegister Reg) const { +void RISCVInstPrinter::printRegName(raw_ostream &O, MCRegister Reg) { markup(O, Markup::Register) << getRegisterName(Reg); } diff --git a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVInstPrinter.h b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVInstPrinter.h index 77cc7a67e88920..c15fd591b9e956 100644 --- a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVInstPrinter.h +++ b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVInstPrinter.h @@ -28,7 +28,7 @@ class RISCVInstPrinter : public MCInstPrinter { void printInst(const MCInst *MI, uint64_t Address, StringRef Annot, const MCSubtargetInfo &STI, raw_ostream &O) override; - void printRegName(raw_ostream &O, MCRegister Reg) const override; + void printRegName(raw_ostream &O, MCRegister Reg) override; void printOperand(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI, raw_ostream &O, const char *Modifier = nullptr); diff --git a/llvm/lib/Target/RISCV/RISCVFeatures.td b/llvm/lib/Target/RISCV/RISCVFeatures.td index 608782d7839a9f..1e4bf1b8830bcc 100644 --- a/llvm/lib/Target/RISCV/RISCVFeatures.td +++ b/llvm/lib/Target/RISCV/RISCVFeatures.td @@ -733,7 +733,8 @@ def HasStdExtZfhOrZvfh def FeatureStdExtZvkb : RISCVExtension<"zvkb", 1, 0, - "'Zvkb' (Vector Bit-manipulation used in Cryptography)">, + "'Zvkb' (Vector Bit-manipulation used in Cryptography)", + [FeatureStdExtZve32x]>, RISCVExtensionBitmask<0, 52>; def HasStdExtZvkb : Predicate<"Subtarget->hasStdExtZvkb()">, AssemblerPredicate<(all_of FeatureStdExtZvkb), @@ -750,7 +751,8 @@ def HasStdExtZvbb : Predicate<"Subtarget->hasStdExtZvbb()">, def FeatureStdExtZvbc : RISCVExtension<"zvbc", 1, 0, - "'Zvbc' (Vector Carryless Multiplication)">, + "'Zvbc' (Vector Carryless Multiplication)", + [FeatureStdExtZve64x]>, RISCVExtensionBitmask<0, 49>; def HasStdExtZvbc : Predicate<"Subtarget->hasStdExtZvbc()">, AssemblerPredicate<(all_of FeatureStdExtZvbc), @@ -758,7 +760,8 @@ def HasStdExtZvbc : Predicate<"Subtarget->hasStdExtZvbc()">, def FeatureStdExtZvbc32e : RISCVExperimentalExtension<"zvbc32e", 0, 7, - "'Zvbc32e' (Vector Carryless Multiplication with 32-bits elements)">; + "'Zvbc32e' (Vector Carryless Multiplication with 32-bits elements)", + [FeatureStdExtZve32x]>; def HasStdExtZvbcOrZvbc32e : Predicate<"Subtarget->hasStdExtZvbc() || Subtarget->hasStdExtZvbc32e()">, AssemblerPredicate<(any_of FeatureStdExtZvbc, FeatureStdExtZvbc32e), @@ -766,7 +769,8 @@ def HasStdExtZvbcOrZvbc32e : Predicate<"Subtarget->hasStdExtZvbc() || Subtarget- def FeatureStdExtZvkg : RISCVExtension<"zvkg", 1, 0, - "'Zvkg' (Vector GCM instructions for Cryptography)">, + "'Zvkg' (Vector GCM instructions for Cryptography)", + [FeatureStdExtZve32x]>, RISCVExtensionBitmask<0, 53>; def HasStdExtZvkg : Predicate<"Subtarget->hasStdExtZvkg()">, AssemblerPredicate<(all_of FeatureStdExtZvkg), @@ -782,7 +786,8 @@ def HasStdExtZvkgs : Predicate<"Subtarget->hasStdExtZvkgs()">, def FeatureStdExtZvkned : RISCVExtension<"zvkned", 1, 0, - "'Zvkned' (Vector AES Encryption & Decryption (Single Round))">, + "'Zvkned' (Vector AES Encryption & Decryption (Single Round))", + [FeatureStdExtZve32x]>, RISCVExtensionBitmask<0, 54>; def HasStdExtZvkned : Predicate<"Subtarget->hasStdExtZvkned()">, AssemblerPredicate<(all_of FeatureStdExtZvkned), @@ -790,7 +795,8 @@ def HasStdExtZvkned : Predicate<"Subtarget->hasStdExtZvkned()">, def FeatureStdExtZvknha : RISCVExtension<"zvknha", 1, 0, - "'Zvknha' (Vector SHA-2 (SHA-256 only))">, + "'Zvknha' (Vector SHA-2 (SHA-256 only))", + [FeatureStdExtZve32x]>, RISCVExtensionBitmask<0, 55>; def HasStdExtZvknha : Predicate<"Subtarget->hasStdExtZvknha()">, AssemblerPredicate<(all_of FeatureStdExtZvknha), @@ -798,7 +804,8 @@ def HasStdExtZvknha : Predicate<"Subtarget->hasStdExtZvknha()">, def FeatureStdExtZvknhb : RISCVExtension<"zvknhb", 1, 0, - "'Zvknhb' (Vector SHA-2 (SHA-256 and SHA-512))">, + "'Zvknhb' (Vector SHA-2 (SHA-256 and SHA-512))", + [FeatureStdExtZve64x]>, RISCVExtensionBitmask<0, 56>; def HasStdExtZvknhb : Predicate<"Subtarget->hasStdExtZvknhb()">, AssemblerPredicate<(all_of FeatureStdExtZvknhb), @@ -810,7 +817,8 @@ def HasStdExtZvknhaOrZvknhb : Predicate<"Subtarget->hasStdExtZvknha() || Subtarg def FeatureStdExtZvksed : RISCVExtension<"zvksed", 1, 0, - "'Zvksed' (SM4 Block Cipher Instructions)">, + "'Zvksed' (SM4 Block Cipher Instructions)", + [FeatureStdExtZve32x]>, RISCVExtensionBitmask<0, 57>; def HasStdExtZvksed : Predicate<"Subtarget->hasStdExtZvksed()">, AssemblerPredicate<(all_of FeatureStdExtZvksed), @@ -818,7 +826,8 @@ def HasStdExtZvksed : Predicate<"Subtarget->hasStdExtZvksed()">, def FeatureStdExtZvksh : RISCVExtension<"zvksh", 1, 0, - "'Zvksh' (SM3 Hash Function Instructions)">, + "'Zvksh' (SM3 Hash Function Instructions)", + [FeatureStdExtZve32x]>, RISCVExtensionBitmask<0, 58>; def HasStdExtZvksh : Predicate<"Subtarget->hasStdExtZvksh()">, AssemblerPredicate<(all_of FeatureStdExtZvksh), @@ -1031,7 +1040,7 @@ def FeatureStdExtSvpbmt def FeatureStdExtSvvptc : RISCVExtension<"svvptc", 1, 0, - "'svvptc' (Obviating Memory-Management Instructions after Marking PTEs Valid)">; + "'svvptc' (Obviating Memory-Management Instructions after Marking PTEs Valid)">; def FeatureStdExtSha : RISCVExtension<"sha", 1, 0, diff --git a/llvm/lib/Target/RISCV/RISCVFrameLowering.cpp b/llvm/lib/Target/RISCV/RISCVFrameLowering.cpp index b49cbab1876d79..f5851f37154519 100644 --- a/llvm/lib/Target/RISCV/RISCVFrameLowering.cpp +++ b/llvm/lib/Target/RISCV/RISCVFrameLowering.cpp @@ -42,10 +42,19 @@ RISCVFrameLowering::RISCVFrameLowering(const RISCVSubtarget &STI) /*TransientStackAlignment=*/getABIStackAlignment(STI.getTargetABI())), STI(STI) {} +// The register used to hold the frame pointer. +static constexpr Register FPReg = RISCV::X8; + +// The register used to hold the stack pointer. +static constexpr Register SPReg = RISCV::X2; + +// The register used to hold the return address. +static constexpr Register RAReg = RISCV::X1; + // Offsets which need to be scale by XLen representing locations of CSRs which // are given a fixed location by save/restore libcalls or Zcmp Push/Pop. static const std::pair FixedCSRFIMap[] = { - {/*ra*/ RISCV::X1, -1}, {/*s0*/ RISCV::X8, -2}, + {/*ra*/ RAReg, -1}, {/*s0*/ FPReg, -2}, {/*s1*/ RISCV::X9, -3}, {/*s2*/ RISCV::X18, -4}, {/*s3*/ RISCV::X19, -5}, {/*s4*/ RISCV::X20, -6}, {/*s5*/ RISCV::X21, -7}, {/*s6*/ RISCV::X22, -8}, @@ -187,6 +196,7 @@ static int getLibCallID(const MachineFunction &MF, switch (MaxReg) { default: llvm_unreachable("Something has gone wrong!"); + // clang-format off case /*s11*/ RISCV::X27: return 12; case /*s10*/ RISCV::X26: return 11; case /*s9*/ RISCV::X25: return 10; @@ -198,8 +208,9 @@ static int getLibCallID(const MachineFunction &MF, case /*s3*/ RISCV::X19: return 4; case /*s2*/ RISCV::X18: return 3; case /*s1*/ RISCV::X9: return 2; - case /*s0*/ RISCV::X8: return 1; - case /*ra*/ RISCV::X1: return 0; + case /*s0*/ FPReg: return 1; + case /*ra*/ RAReg: return 0; + // clang-format on } } @@ -284,9 +295,9 @@ getPushPopEncodingAndNum(const Register MaxReg) { return std::make_pair(llvm::RISCVZC::RLISTENCODE::RA_S0_S2, 4); case RISCV::X9: /*s1*/ return std::make_pair(llvm::RISCVZC::RLISTENCODE::RA_S0_S1, 3); - case RISCV::X8: /*s0*/ + case FPReg: /*s0*/ return std::make_pair(llvm::RISCVZC::RLISTENCODE::RA_S0, 2); - case RISCV::X1: /*ra*/ + case RAReg: /*ra*/ return std::make_pair(llvm::RISCVZC::RLISTENCODE::RA, 1); } } @@ -372,12 +383,6 @@ uint64_t RISCVFrameLowering::getStackSizeWithRVVPadding( return alignTo(MFI.getStackSize() + RVFI->getRVVPadding(), getStackAlign()); } -// Returns the register used to hold the frame pointer. -static Register getFPReg(const RISCVSubtarget &STI) { return RISCV::X8; } - -// Returns the register used to hold the stack pointer. -static Register getSPReg(const RISCVSubtarget &STI) { return RISCV::X2; } - static SmallVector getUnmanagedCSI(const MachineFunction &MF, const std::vector &CSI) { @@ -415,8 +420,6 @@ void RISCVFrameLowering::adjustStackForRVV(MachineFunction &MF, MachineInstr::MIFlag Flag) const { assert(Amount != 0 && "Did not need to adjust stack pointer for RVV."); - const Register SPReg = getSPReg(STI); - // Optimize compile time offset case StackOffset Offset = StackOffset::getScalable(Amount); if (auto VLEN = STI.getRealVLen()) { @@ -479,7 +482,7 @@ static MCCFIInstruction createDefCFAExpression(const TargetRegisterInfo &TRI, unsigned DwarfReg = TRI.getDwarfRegNum(Reg, true); Expr.push_back((uint8_t)(dwarf::DW_OP_breg0 + DwarfReg)); Expr.push_back(0); - if (Reg == RISCV::X2) + if (Reg == SPReg) Comment << "sp"; else Comment << printReg(Reg, &TRI); @@ -530,8 +533,6 @@ void RISCVFrameLowering::emitPrologue(MachineFunction &MF, const RISCVInstrInfo *TII = STI.getInstrInfo(); MachineBasicBlock::iterator MBBI = MBB.begin(); - Register FPReg = getFPReg(STI); - Register SPReg = getSPReg(STI); Register BPReg = RISCVABI::getBPReg(); // Debug location must be unknown since the first debug location is used @@ -762,8 +763,6 @@ void RISCVFrameLowering::deallocateStack(MachineFunction &MF, int64_t CFAOffset) const { const RISCVRegisterInfo *RI = STI.getRegisterInfo(); - Register SPReg = getSPReg(STI); - RI->adjustReg(MBB, MBBI, DL, SPReg, SPReg, StackOffset::getFixed(StackSize), MachineInstr::FrameDestroy, getStackAlign()); } @@ -773,8 +772,6 @@ void RISCVFrameLowering::emitEpilogue(MachineFunction &MF, const RISCVRegisterInfo *RI = STI.getRegisterInfo(); MachineFrameInfo &MFI = MF.getFrameInfo(); auto *RVFI = MF.getInfo(); - Register FPReg = getFPReg(STI); - Register SPReg = getSPReg(STI); // All calls are tail calls in GHC calling conv, and functions have no // prologue/epilogue. @@ -922,7 +919,7 @@ RISCVFrameLowering::getFrameIndexReference(const MachineFunction &MF, int FI, } if (FI >= MinCSFI && FI <= MaxCSFI) { - FrameReg = RISCV::X2; + FrameReg = SPReg; if (FirstSPAdjustAmount) Offset += StackOffset::getFixed(FirstSPAdjustAmount); @@ -969,13 +966,13 @@ RISCVFrameLowering::getFrameIndexReference(const MachineFunction &MF, int FI, } else { // VarSize objects must be empty in this case! assert(!MFI.hasVarSizedObjects()); - FrameReg = RISCV::X2; + FrameReg = SPReg; } } else { FrameReg = RI->getFrameRegister(MF); } - if (FrameReg == getFPReg(STI)) { + if (FrameReg == FPReg) { Offset += StackOffset::getFixed(RVFI->getVarArgsSaveSize()); // When using FP to access scalable vector objects, we need to minus // the frame size. @@ -1067,8 +1064,8 @@ void RISCVFrameLowering::determineCalleeSaves(MachineFunction &MF, // Unconditionally spill RA and FP only if the function uses a frame // pointer. if (hasFP(MF)) { - SavedRegs.set(RISCV::X1); - SavedRegs.set(RISCV::X8); + SavedRegs.set(RAReg); + SavedRegs.set(FPReg); } // Mark BP as used if function has dedicated base pointer. if (hasBP(MF)) @@ -1133,23 +1130,23 @@ RISCVFrameLowering::assignRVVStackObjectOffsets(MachineFunction &MF) const { uint64_t StackSize = Offset; - // Multiply by vscale. - if (ST.getRealMinVLen() >= RISCV::RVVBitsPerBlock) - StackSize *= ST.getRealMinVLen() / RISCV::RVVBitsPerBlock; - // Ensure the alignment of the RVV stack. Since we want the most-aligned // object right at the bottom (i.e., any padding at the top of the frame), // readjust all RVV objects down by the alignment padding. - if (auto AlignmentPadding = offsetToAlignment(StackSize, RVVStackAlign)) { - StackSize += AlignmentPadding; - for (int FI : ObjectsToAllocate) - MFI.setObjectOffset(FI, MFI.getObjectOffset(FI) - AlignmentPadding); + // Stack size and offsets are multiples of vscale, stack alignment is in + // bytes, we can divide stack alignment by minimum vscale to get a maximum + // stack alignment multiple of vscale. + auto VScale = + std::max(ST.getRealMinVLen() / RISCV::RVVBitsPerBlock, 1); + if (auto RVVStackAlignVScale = RVVStackAlign.value() / VScale) { + if (auto AlignmentPadding = + offsetToAlignment(StackSize, Align(RVVStackAlignVScale))) { + StackSize += AlignmentPadding; + for (int FI : ObjectsToAllocate) + MFI.setObjectOffset(FI, MFI.getObjectOffset(FI) - AlignmentPadding); + } } - // Remove vscale. - if (ST.getRealMinVLen() >= RISCV::RVVBitsPerBlock) - StackSize /= ST.getRealMinVLen() / RISCV::RVVBitsPerBlock; - return std::make_pair(StackSize, RVVStackAlign); } @@ -1328,7 +1325,6 @@ bool RISCVFrameLowering::hasReservedCallFrame(const MachineFunction &MF) const { MachineBasicBlock::iterator RISCVFrameLowering::eliminateCallFramePseudoInstr( MachineFunction &MF, MachineBasicBlock &MBB, MachineBasicBlock::iterator MI) const { - Register SPReg = RISCV::X2; DebugLoc DL = MI->getDebugLoc(); if (!hasReservedCallFrame(MF)) { diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp b/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp index a3963fadf3e417..d5b086861d71e6 100644 --- a/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp +++ b/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp @@ -2536,6 +2536,21 @@ bool RISCVInstrInfo::verifyInstruction(const MachineInstr &MI, case RISCVOp::OPERAND_SPIMM: Ok = (Imm & 0xf) == 0; break; + case RISCVOp::OPERAND_FRMARG: + Ok = RISCVFPRndMode::isValidRoundingMode(Imm); + break; + case RISCVOp::OPERAND_RTZARG: + Ok = Imm == RISCVFPRndMode::RTZ; + break; + case RISCVOp::OPERAND_COND_CODE: + Ok = Imm >= 0 && Imm < RISCVCC::COND_INVALID; + break; + case RISCVOp::OPERAND_VEC_POLICY: + Ok = (Imm & (RISCVII::TAIL_AGNOSTIC | RISCVII::MASK_AGNOSTIC)) == Imm; + break; + case RISCVOp::OPERAND_SEW: + Ok = Imm == 0 || (Imm >= 3 && Imm <= 6); + break; } if (!Ok) { ErrInfo = "Invalid immediate"; diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfo.td b/llvm/lib/Target/RISCV/RISCVInstrInfo.td index 86cc638fd04ac2..a867368235584c 100644 --- a/llvm/lib/Target/RISCV/RISCVInstrInfo.td +++ b/llvm/lib/Target/RISCV/RISCVInstrInfo.td @@ -387,6 +387,11 @@ def csr_sysreg : RISCVOp, TImmLeaf(Imm);"> { // A parameterized register class alternative to i32imm/i64imm from Target.td. def ixlenimm : Operand; +// Condition code used by select and short forward branch pseudos. +def cond_code : RISCVOp { + let OperandType = "OPERAND_COND_CODE"; +} + def ixlenimm_li : Operand { let ParserMatchClass = ImmXLenAsmOperand<"", "LI">; } @@ -1450,7 +1455,7 @@ def riscv_selectcc_frag : PatFrag<(ops node:$lhs, node:$rhs, node:$cc, multiclass SelectCC_GPR_rrirr { let usesCustomInserter = 1 in def _Using_CC_GPR : Pseudo<(outs valty:$dst), - (ins GPR:$lhs, GPR:$rhs, ixlenimm:$cc, + (ins GPR:$lhs, GPR:$rhs, cond_code:$cc, valty:$truev, valty:$falsev), [(set valty:$dst, (riscv_selectcc_frag:$cc (XLenVT GPR:$lhs), GPR:$rhs, cond, diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoF.td b/llvm/lib/Target/RISCV/RISCVInstrInfoF.td index a134f37c774954..da3f207a2faf72 100644 --- a/llvm/lib/Target/RISCV/RISCVInstrInfoF.td +++ b/llvm/lib/Target/RISCV/RISCVInstrInfoF.td @@ -134,6 +134,8 @@ def frmarg : Operand { let ParserMatchClass = FRMArg; let PrintMethod = "printFRMArg"; let DecoderMethod = "decodeFRMArg"; + let OperandType = "OPERAND_FRMARG"; + let OperandNamespace = "RISCVOp"; } // Variants of the rounding mode operand that default to 'rne'. This is used @@ -154,6 +156,8 @@ def frmarglegacy : Operand { let ParserMatchClass = FRMArgLegacy; let PrintMethod = "printFRMArgLegacy"; let DecoderMethod = "decodeFRMArg"; + let OperandType = "OPERAND_FRMARG"; + let OperandNamespace = "RISCVOp"; } //===----------------------------------------------------------------------===// diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoSFB.td b/llvm/lib/Target/RISCV/RISCVInstrInfoSFB.td index f25dc7302608ba..16cc0e5a61f0bc 100644 --- a/llvm/lib/Target/RISCV/RISCVInstrInfoSFB.td +++ b/llvm/lib/Target/RISCV/RISCVInstrInfoSFB.td @@ -15,7 +15,7 @@ let Predicates = [HasShortForwardBranchOpt], isSelect = 1, // This instruction moves $truev to $dst when the condition is true. It will // be expanded to control flow in RISCVExpandPseudoInsts. def PseudoCCMOVGPR : Pseudo<(outs GPR:$dst), - (ins GPR:$lhs, GPR:$rhs, ixlenimm:$cc, + (ins GPR:$lhs, GPR:$rhs, cond_code:$cc, GPR:$falsev, GPR:$truev), [(set GPR:$dst, (riscv_selectcc_frag:$cc (XLenVT GPR:$lhs), @@ -34,7 +34,7 @@ let Predicates = [HasConditionalMoveFusion, NoShortForwardBranchOpt], // be expanded to control flow in RISCVExpandPseudoInsts. // We use GPRNoX0 because c.mv cannot encode X0. def PseudoCCMOVGPRNoX0 : Pseudo<(outs GPRNoX0:$dst), - (ins GPR:$lhs, GPR:$rhs, ixlenimm:$cc, + (ins GPR:$lhs, GPR:$rhs, cond_code:$cc, GPRNoX0:$falsev, GPRNoX0:$truev), [(set GPRNoX0:$dst, (riscv_selectcc_frag:$cc (XLenVT GPR:$lhs), @@ -51,143 +51,143 @@ def PseudoCCMOVGPRNoX0 : Pseudo<(outs GPRNoX0:$dst), let Predicates = [HasShortForwardBranchOpt], hasSideEffects = 0, mayLoad = 0, mayStore = 0, Size = 8, Constraints = "$dst = $falsev" in { def PseudoCCADD : Pseudo<(outs GPR:$dst), - (ins GPR:$lhs, GPR:$rhs, ixlenimm:$cc, + (ins GPR:$lhs, GPR:$rhs, cond_code:$cc, GPR:$falsev, GPR:$rs1, GPR:$rs2), []>, Sched<[WriteSFB, ReadSFBJmp, ReadSFBJmp, ReadSFBALU, ReadSFBALU, ReadSFBALU]>; def PseudoCCSUB : Pseudo<(outs GPR:$dst), - (ins GPR:$lhs, GPR:$rhs, ixlenimm:$cc, + (ins GPR:$lhs, GPR:$rhs, cond_code:$cc, GPR:$falsev, GPR:$rs1, GPR:$rs2), []>, Sched<[WriteSFB, ReadSFBJmp, ReadSFBJmp, ReadSFBALU, ReadSFBALU, ReadSFBALU]>; def PseudoCCSLL : Pseudo<(outs GPR:$dst), - (ins GPR:$lhs, GPR:$rhs, ixlenimm:$cc, + (ins GPR:$lhs, GPR:$rhs, cond_code:$cc, GPR:$falsev, GPR:$rs1, GPR:$rs2), []>, Sched<[WriteSFB, ReadSFBJmp, ReadSFBJmp, ReadSFBALU, ReadSFBALU, ReadSFBALU]>; def PseudoCCSRL : Pseudo<(outs GPR:$dst), - (ins GPR:$lhs, GPR:$rhs, ixlenimm:$cc, + (ins GPR:$lhs, GPR:$rhs, cond_code:$cc, GPR:$falsev, GPR:$rs1, GPR:$rs2), []>, Sched<[WriteSFB, ReadSFBJmp, ReadSFBJmp, ReadSFBALU, ReadSFBALU, ReadSFBALU]>; def PseudoCCSRA : Pseudo<(outs GPR:$dst), - (ins GPR:$lhs, GPR:$rhs, ixlenimm:$cc, + (ins GPR:$lhs, GPR:$rhs, cond_code:$cc, GPR:$falsev, GPR:$rs1, GPR:$rs2), []>, Sched<[WriteSFB, ReadSFBJmp, ReadSFBJmp, ReadSFBALU, ReadSFBALU, ReadSFBALU]>; def PseudoCCAND : Pseudo<(outs GPR:$dst), - (ins GPR:$lhs, GPR:$rhs, ixlenimm:$cc, + (ins GPR:$lhs, GPR:$rhs, cond_code:$cc, GPR:$falsev, GPR:$rs1, GPR:$rs2), []>, Sched<[WriteSFB, ReadSFBJmp, ReadSFBJmp, ReadSFBALU, ReadSFBALU, ReadSFBALU]>; def PseudoCCOR : Pseudo<(outs GPR:$dst), - (ins GPR:$lhs, GPR:$rhs, ixlenimm:$cc, + (ins GPR:$lhs, GPR:$rhs, cond_code:$cc, GPR:$falsev, GPR:$rs1, GPR:$rs2), []>, Sched<[WriteSFB, ReadSFBJmp, ReadSFBJmp, ReadSFBALU, ReadSFBALU, ReadSFBALU]>; def PseudoCCXOR : Pseudo<(outs GPR:$dst), - (ins GPR:$lhs, GPR:$rhs, ixlenimm:$cc, + (ins GPR:$lhs, GPR:$rhs, cond_code:$cc, GPR:$falsev, GPR:$rs1, GPR:$rs2), []>, Sched<[WriteSFB, ReadSFBJmp, ReadSFBJmp, ReadSFBALU, ReadSFBALU, ReadSFBALU]>; def PseudoCCADDI : Pseudo<(outs GPR:$dst), - (ins GPR:$lhs, GPR:$rhs, ixlenimm:$cc, + (ins GPR:$lhs, GPR:$rhs, cond_code:$cc, GPR:$falsev, GPR:$rs1, simm12:$rs2), []>, Sched<[WriteSFB, ReadSFBJmp, ReadSFBJmp, ReadSFBALU, ReadSFBALU]>; def PseudoCCSLLI : Pseudo<(outs GPR:$dst), - (ins GPR:$lhs, GPR:$rhs, ixlenimm:$cc, + (ins GPR:$lhs, GPR:$rhs, cond_code:$cc, GPR:$falsev, GPR:$rs1, simm12:$rs2), []>, Sched<[WriteSFB, ReadSFBJmp, ReadSFBJmp, ReadSFBALU, ReadSFBALU]>; def PseudoCCSRLI : Pseudo<(outs GPR:$dst), - (ins GPR:$lhs, GPR:$rhs, ixlenimm:$cc, + (ins GPR:$lhs, GPR:$rhs, cond_code:$cc, GPR:$falsev, GPR:$rs1, simm12:$rs2), []>, Sched<[WriteSFB, ReadSFBJmp, ReadSFBJmp, ReadSFBALU, ReadSFBALU]>; def PseudoCCSRAI : Pseudo<(outs GPR:$dst), - (ins GPR:$lhs, GPR:$rhs, ixlenimm:$cc, + (ins GPR:$lhs, GPR:$rhs, cond_code:$cc, GPR:$falsev, GPR:$rs1, simm12:$rs2), []>, Sched<[WriteSFB, ReadSFBJmp, ReadSFBJmp, ReadSFBALU, ReadSFBALU]>; def PseudoCCANDI : Pseudo<(outs GPR:$dst), - (ins GPR:$lhs, GPR:$rhs, ixlenimm:$cc, + (ins GPR:$lhs, GPR:$rhs, cond_code:$cc, GPR:$falsev, GPR:$rs1, simm12:$rs2), []>, Sched<[WriteSFB, ReadSFBJmp, ReadSFBJmp, ReadSFBALU, ReadSFBALU]>; def PseudoCCORI : Pseudo<(outs GPR:$dst), - (ins GPR:$lhs, GPR:$rhs, ixlenimm:$cc, + (ins GPR:$lhs, GPR:$rhs, cond_code:$cc, GPR:$falsev, GPR:$rs1, simm12:$rs2), []>, Sched<[WriteSFB, ReadSFBJmp, ReadSFBJmp, ReadSFBALU, ReadSFBALU]>; def PseudoCCXORI : Pseudo<(outs GPR:$dst), - (ins GPR:$lhs, GPR:$rhs, ixlenimm:$cc, + (ins GPR:$lhs, GPR:$rhs, cond_code:$cc, GPR:$falsev, GPR:$rs1, simm12:$rs2), []>, Sched<[WriteSFB, ReadSFBJmp, ReadSFBJmp, ReadSFBALU, ReadSFBALU]>; // RV64I instructions def PseudoCCADDW : Pseudo<(outs GPR:$dst), - (ins GPR:$lhs, GPR:$rhs, ixlenimm:$cc, + (ins GPR:$lhs, GPR:$rhs, cond_code:$cc, GPR:$falsev, GPR:$rs1, GPR:$rs2), []>, Sched<[WriteSFB, ReadSFBJmp, ReadSFBJmp, ReadSFBALU, ReadSFBALU, ReadSFBALU]>; def PseudoCCSUBW : Pseudo<(outs GPR:$dst), - (ins GPR:$lhs, GPR:$rhs, ixlenimm:$cc, + (ins GPR:$lhs, GPR:$rhs, cond_code:$cc, GPR:$falsev, GPR:$rs1, GPR:$rs2), []>, Sched<[WriteSFB, ReadSFBJmp, ReadSFBJmp, ReadSFBALU, ReadSFBALU, ReadSFBALU]>; def PseudoCCSLLW : Pseudo<(outs GPR:$dst), - (ins GPR:$lhs, GPR:$rhs, ixlenimm:$cc, + (ins GPR:$lhs, GPR:$rhs, cond_code:$cc, GPR:$falsev, GPR:$rs1, GPR:$rs2), []>, Sched<[WriteSFB, ReadSFBJmp, ReadSFBJmp, ReadSFBALU, ReadSFBALU, ReadSFBALU]>; def PseudoCCSRLW : Pseudo<(outs GPR:$dst), - (ins GPR:$lhs, GPR:$rhs, ixlenimm:$cc, + (ins GPR:$lhs, GPR:$rhs, cond_code:$cc, GPR:$falsev, GPR:$rs1, GPR:$rs2), []>, Sched<[WriteSFB, ReadSFBJmp, ReadSFBJmp, ReadSFBALU, ReadSFBALU, ReadSFBALU]>; def PseudoCCSRAW : Pseudo<(outs GPR:$dst), - (ins GPR:$lhs, GPR:$rhs, ixlenimm:$cc, + (ins GPR:$lhs, GPR:$rhs, cond_code:$cc, GPR:$falsev, GPR:$rs1, GPR:$rs2), []>, Sched<[WriteSFB, ReadSFBJmp, ReadSFBJmp, ReadSFBALU, ReadSFBALU, ReadSFBALU]>; def PseudoCCADDIW : Pseudo<(outs GPR:$dst), - (ins GPR:$lhs, GPR:$rhs, ixlenimm:$cc, + (ins GPR:$lhs, GPR:$rhs, cond_code:$cc, GPR:$falsev, GPR:$rs1, simm12:$rs2), []>, Sched<[WriteSFB, ReadSFBJmp, ReadSFBJmp, ReadSFBALU, ReadSFBALU]>; def PseudoCCSLLIW : Pseudo<(outs GPR:$dst), - (ins GPR:$lhs, GPR:$rhs, ixlenimm:$cc, + (ins GPR:$lhs, GPR:$rhs, cond_code:$cc, GPR:$falsev, GPR:$rs1, simm12:$rs2), []>, Sched<[WriteSFB, ReadSFBJmp, ReadSFBJmp, ReadSFBALU, ReadSFBALU]>; def PseudoCCSRLIW : Pseudo<(outs GPR:$dst), - (ins GPR:$lhs, GPR:$rhs, ixlenimm:$cc, + (ins GPR:$lhs, GPR:$rhs, cond_code:$cc, GPR:$falsev, GPR:$rs1, simm12:$rs2), []>, Sched<[WriteSFB, ReadSFBJmp, ReadSFBJmp, ReadSFBALU, ReadSFBALU]>; def PseudoCCSRAIW : Pseudo<(outs GPR:$dst), - (ins GPR:$lhs, GPR:$rhs, ixlenimm:$cc, + (ins GPR:$lhs, GPR:$rhs, cond_code:$cc, GPR:$falsev, GPR:$rs1, simm12:$rs2), []>, Sched<[WriteSFB, ReadSFBJmp, ReadSFBJmp, ReadSFBALU, ReadSFBALU]>; // Zbb/Zbkb instructions def PseudoCCANDN : Pseudo<(outs GPR:$dst), - (ins GPR:$lhs, GPR:$rhs, ixlenimm:$cc, + (ins GPR:$lhs, GPR:$rhs, cond_code:$cc, GPR:$falsev, GPR:$rs1, GPR:$rs2), []>, Sched<[WriteSFB, ReadSFBJmp, ReadSFBJmp, ReadSFBALU, ReadSFBALU, ReadSFBALU]>; def PseudoCCORN : Pseudo<(outs GPR:$dst), - (ins GPR:$lhs, GPR:$rhs, ixlenimm:$cc, + (ins GPR:$lhs, GPR:$rhs, cond_code:$cc, GPR:$falsev, GPR:$rs1, GPR:$rs2), []>, Sched<[WriteSFB, ReadSFBJmp, ReadSFBJmp, ReadSFBALU, ReadSFBALU, ReadSFBALU]>; def PseudoCCXNOR : Pseudo<(outs GPR:$dst), - (ins GPR:$lhs, GPR:$rhs, ixlenimm:$cc, + (ins GPR:$lhs, GPR:$rhs, cond_code:$cc, GPR:$falsev, GPR:$rs1, GPR:$rs2), []>, Sched<[WriteSFB, ReadSFBJmp, ReadSFBJmp, ReadSFBALU, ReadSFBALU, ReadSFBALU]>; diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoV.td b/llvm/lib/Target/RISCV/RISCVInstrInfoV.td index 4e8619c5ec2392..8e0c4826ac00de 100644 --- a/llvm/lib/Target/RISCV/RISCVInstrInfoV.td +++ b/llvm/lib/Target/RISCV/RISCVInstrInfoV.td @@ -104,13 +104,28 @@ class SchedCommon writes, list reads, string mx = "WorstCase", int sew = 0, bit forceMasked = 0, bit forcePassthruRead = 0> : Sched<[]> { defvar isMasked = !ne(!find(NAME, "_MASK"), -1); + defvar isTied = !ne(!find(NAME, "_TIED"), -1); defvar isMaskedOrForceMasked = !or(forceMasked, isMasked); + defvar isTiedMasked = !and(isMaskedOrForceMasked, isTied); defvar passthruRead = !if(!or(!eq(mx, "WorstCase"), !eq(sew, 0)), !cast("ReadVPassthru_" # mx), !cast("ReadVPassthru_" # mx # "_E" #sew)); - defvar needsPassthruRead = !or(isMaskedOrForceMasked, forcePassthruRead); + // We don't need passthru operand if it's already _TIED without mask. + defvar needsForcePassthruRead = !and(forcePassthruRead, !not(isTied)); + defvar needsPassthruRead = !or(isMaskedOrForceMasked, needsForcePassthruRead); + // If this is a _TIED + masked operation, $rs2 (i.e. the first operand) is + // merged with the mask. + // NOTE: the following if statement is written in such a weird way because + // should we want to write something like + // `!if(!and(!not(!empty(reads), isTiedMasked), !tail(reads), reads)` + // since `!if` doesn't have a proper short-circuit behavior, if the + // condition of this `!if` cannot be resolved right away, `!tail(reads)` will + // be immediately evaluated anyway even when `reads` is empty, which leads to + // an assertion failure. + defvar readsWithTiedMask = + !if(isTiedMasked, !if(!not(!empty(reads)), !tail(reads), reads), reads); defvar readsWithMask = - !if(isMaskedOrForceMasked, !listconcat(reads, [ReadVMask]), reads); + !if(isMaskedOrForceMasked, !listconcat(readsWithTiedMask, [ReadVMask]), reads); defvar allReads = !if(needsPassthruRead, !listconcat([passthruRead], readsWithMask), reads); let SchedRW = !listconcat(writes, allReads); diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td b/llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td index af4f653f57afd5..6ffdae1d7df2ae 100644 --- a/llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td +++ b/llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td @@ -84,6 +84,14 @@ def AVL : RegisterOperand { let OperandType = "OPERAND_AVL"; } +def vec_policy : RISCVOp { + let OperandType = "OPERAND_VEC_POLICY"; +} + +def sew : RISCVOp { + let OperandType = "OPERAND_SEW"; +} + // X0 has special meaning for vsetvl/vsetvli. // rd | rs1 | AVL value | Effect on vl //-------------------------------------------------------------- @@ -764,8 +772,8 @@ class GetVTypePredicates { class VPseudoUSLoadNoMask : Pseudo<(outs RetClass:$rd), - (ins RetClass:$dest, GPRMem:$rs1, AVL:$vl, ixlenimm:$sew, - ixlenimm:$policy), []>, + (ins RetClass:$dest, GPRMem:$rs1, AVL:$vl, sew:$sew, + vec_policy:$policy), []>, RISCVVPseudo, RISCVVLE { let mayLoad = 1; @@ -782,7 +790,7 @@ class VPseudoUSLoadMask.R:$rd), (ins GetVRegNoV0.R:$passthru, GPRMem:$rs1, - VMaskOp:$vm, AVL:$vl, ixlenimm:$sew, ixlenimm:$policy), []>, + VMaskOp:$vm, AVL:$vl, sew:$sew, vec_policy:$policy), []>, RISCVVPseudo, RISCVVLE { let mayLoad = 1; @@ -799,7 +807,7 @@ class VPseudoUSLoadFFNoMask : Pseudo<(outs RetClass:$rd, GPR:$vl), (ins RetClass:$dest, GPRMem:$rs1, AVL:$avl, - ixlenimm:$sew, ixlenimm:$policy), []>, + sew:$sew, vec_policy:$policy), []>, RISCVVPseudo, RISCVVLE { let mayLoad = 1; @@ -816,7 +824,7 @@ class VPseudoUSLoadFFMask.R:$rd, GPR:$vl), (ins GetVRegNoV0.R:$passthru, GPRMem:$rs1, - VMaskOp:$vm, AVL:$avl, ixlenimm:$sew, ixlenimm:$policy), []>, + VMaskOp:$vm, AVL:$avl, sew:$sew, vec_policy:$policy), []>, RISCVVPseudo, RISCVVLE { let mayLoad = 1; @@ -833,7 +841,7 @@ class VPseudoSLoadNoMask : Pseudo<(outs RetClass:$rd), (ins RetClass:$dest, GPRMem:$rs1, GPR:$rs2, AVL:$vl, - ixlenimm:$sew, ixlenimm:$policy), []>, + sew:$sew, vec_policy:$policy), []>, RISCVVPseudo, RISCVVLE { let mayLoad = 1; @@ -850,7 +858,7 @@ class VPseudoSLoadMask.R:$rd), (ins GetVRegNoV0.R:$passthru, GPRMem:$rs1, GPR:$rs2, - VMaskOp:$vm, AVL:$vl, ixlenimm:$sew, ixlenimm:$policy), []>, + VMaskOp:$vm, AVL:$vl, sew:$sew, vec_policy:$policy), []>, RISCVVPseudo, RISCVVLE { let mayLoad = 1; @@ -872,7 +880,7 @@ class VPseudoILoadNoMask : Pseudo<(outs RetClass:$rd), (ins RetClass:$dest, GPRMem:$rs1, IdxClass:$rs2, AVL:$vl, - ixlenimm:$sew, ixlenimm:$policy), []>, + sew:$sew, vec_policy:$policy), []>, RISCVVPseudo, RISCVVLX { let mayLoad = 1; @@ -895,7 +903,7 @@ class VPseudoILoadMask.R:$rd), (ins GetVRegNoV0.R:$passthru, GPRMem:$rs1, IdxClass:$rs2, - VMaskOp:$vm, AVL:$vl, ixlenimm:$sew, ixlenimm:$policy), []>, + VMaskOp:$vm, AVL:$vl, sew:$sew, vec_policy:$policy), []>, RISCVVPseudo, RISCVVLX { let mayLoad = 1; @@ -912,7 +920,7 @@ class VPseudoILoadMask : Pseudo<(outs), - (ins StClass:$rd, GPRMem:$rs1, AVL:$vl, ixlenimm:$sew), []>, + (ins StClass:$rd, GPRMem:$rs1, AVL:$vl, sew:$sew), []>, RISCVVPseudo, RISCVVSE { let mayLoad = 0; @@ -926,7 +934,7 @@ class VPseudoUSStoreMask : Pseudo<(outs), (ins StClass:$rd, GPRMem:$rs1, - VMaskOp:$vm, AVL:$vl, ixlenimm:$sew), []>, + VMaskOp:$vm, AVL:$vl, sew:$sew), []>, RISCVVPseudo, RISCVVSE { let mayLoad = 0; @@ -940,7 +948,7 @@ class VPseudoSStoreNoMask : Pseudo<(outs), (ins StClass:$rd, GPRMem:$rs1, GPR:$rs2, - AVL:$vl, ixlenimm:$sew), []>, + AVL:$vl, sew:$sew), []>, RISCVVPseudo, RISCVVSE { let mayLoad = 0; @@ -954,7 +962,7 @@ class VPseudoSStoreMask : Pseudo<(outs), (ins StClass:$rd, GPRMem:$rs1, GPR:$rs2, - VMaskOp:$vm, AVL:$vl, ixlenimm:$sew), []>, + VMaskOp:$vm, AVL:$vl, sew:$sew), []>, RISCVVPseudo, RISCVVSE { let mayLoad = 0; @@ -967,7 +975,7 @@ class VPseudoSStoreMask : Pseudo<(outs RegClass:$rd), (ins RegClass:$passthru, - AVL:$vl, ixlenimm:$sew, ixlenimm:$policy), []>, + AVL:$vl, sew:$sew, vec_policy:$policy), []>, RISCVVPseudo { let mayLoad = 0; let mayStore = 0; @@ -981,7 +989,7 @@ class VPseudoNullaryNoMask : class VPseudoNullaryMask : Pseudo<(outs GetVRegNoV0.R:$rd), (ins GetVRegNoV0.R:$passthru, - VMaskOp:$vm, AVL:$vl, ixlenimm:$sew, ixlenimm:$policy), []>, + VMaskOp:$vm, AVL:$vl, sew:$sew, vec_policy:$policy), []>, RISCVVPseudo { let mayLoad = 0; let mayStore = 0; @@ -996,7 +1004,7 @@ class VPseudoNullaryMask : // Nullary for pseudo instructions. They are expanded in // RISCVExpandPseudoInsts pass. class VPseudoNullaryPseudoM : - Pseudo<(outs VR:$rd), (ins AVL:$vl, ixlenimm:$sew), []>, + Pseudo<(outs VR:$rd), (ins AVL:$vl, sew:$sew), []>, RISCVVPseudo { let mayLoad = 0; let mayStore = 0; @@ -1016,7 +1024,7 @@ class VPseudoUnaryNoMask : Pseudo<(outs RetClass:$rd), (ins RetClass:$passthru, OpClass:$rs2, - AVL:$vl, ixlenimm:$sew, ixlenimm:$policy), []>, + AVL:$vl, sew:$sew, vec_policy:$policy), []>, RISCVVPseudo { let mayLoad = 0; let mayStore = 0; @@ -1033,7 +1041,7 @@ class VPseudoUnaryNoMaskNoPolicy : Pseudo<(outs RetClass:$rd), - (ins OpClass:$rs2, AVL:$vl, ixlenimm:$sew), []>, + (ins OpClass:$rs2, AVL:$vl, sew:$sew), []>, RISCVVPseudo { let mayLoad = 0; let mayStore = 0; @@ -1050,7 +1058,7 @@ class VPseudoUnaryNoMaskRoundingMode : Pseudo<(outs RetClass:$rd), (ins RetClass:$passthru, OpClass:$rs2, ixlenimm:$rm, - AVL:$vl, ixlenimm:$sew, ixlenimm:$policy), []>, + AVL:$vl, sew:$sew, vec_policy:$policy), []>, RISCVVPseudo { let mayLoad = 0; let mayStore = 0; @@ -1070,7 +1078,7 @@ class VPseudoUnaryMask : Pseudo<(outs GetVRegNoV0.R:$rd), (ins GetVRegNoV0.R:$passthru, OpClass:$rs2, - VMaskOp:$vm, AVL:$vl, ixlenimm:$sew, ixlenimm:$policy), []>, + VMaskOp:$vm, AVL:$vl, sew:$sew, vec_policy:$policy), []>, RISCVVPseudo { let mayLoad = 0; let mayStore = 0; @@ -1090,7 +1098,7 @@ class VPseudoUnaryMaskRoundingMode.R:$rd), (ins GetVRegNoV0.R:$passthru, OpClass:$rs2, VMaskOp:$vm, ixlenimm:$rm, - AVL:$vl, ixlenimm:$sew, ixlenimm:$policy), []>, + AVL:$vl, sew:$sew, vec_policy:$policy), []>, RISCVVPseudo { let mayLoad = 0; let mayStore = 0; @@ -1110,7 +1118,7 @@ class VPseudoUnaryMask_NoExcept : Pseudo<(outs GetVRegNoV0.R:$rd), (ins GetVRegNoV0.R:$passthru, OpClass:$rs2, - VMaskOp:$vm, AVL:$vl, ixlenimm:$sew, ixlenimm:$policy), []> { + VMaskOp:$vm, AVL:$vl, sew:$sew, vec_policy:$policy), []> { let mayLoad = 0; let mayStore = 0; let hasSideEffects = 0; @@ -1128,7 +1136,7 @@ class VPseudoUnaryNoMask_FRM : Pseudo<(outs RetClass:$rd), (ins RetClass:$passthru, OpClass:$rs2, ixlenimm:$frm, - AVL:$vl, ixlenimm:$sew, ixlenimm:$policy), []>, + AVL:$vl, sew:$sew, vec_policy:$policy), []>, RISCVVPseudo { let mayLoad = 0; let mayStore = 0; @@ -1148,7 +1156,7 @@ class VPseudoUnaryMask_FRM.R:$rd), (ins GetVRegNoV0.R:$passthru, OpClass:$rs2, VMaskOp:$vm, ixlenimm:$frm, - AVL:$vl, ixlenimm:$sew, ixlenimm:$policy), []>, + AVL:$vl, sew:$sew, vec_policy:$policy), []>, RISCVVPseudo { let mayLoad = 0; let mayStore = 0; @@ -1164,7 +1172,7 @@ class VPseudoUnaryMask_FRM, + (ins VR:$rs2, AVL:$vl, sew:$sew), []>, RISCVVPseudo { let mayLoad = 0; let mayStore = 0; @@ -1175,7 +1183,7 @@ class VPseudoUnaryNoMaskGPROut : class VPseudoUnaryMaskGPROut : Pseudo<(outs GPR:$rd), - (ins VR:$rs1, VMaskOp:$vm, AVL:$vl, ixlenimm:$sew), []>, + (ins VR:$rs1, VMaskOp:$vm, AVL:$vl, sew:$sew), []>, RISCVVPseudo { let mayLoad = 0; let mayStore = 0; @@ -1189,7 +1197,7 @@ class VPseudoUnaryAnyMask : Pseudo<(outs RetClass:$rd), (ins RetClass:$passthru, Op1Class:$rs2, - VR:$vm, AVL:$vl, ixlenimm:$sew), []>, + VR:$vm, AVL:$vl, sew:$sew), []>, RISCVVPseudo { let mayLoad = 0; let mayStore = 0; @@ -1205,7 +1213,7 @@ class VPseudoBinaryNoMask : Pseudo<(outs RetClass:$rd), - (ins Op1Class:$rs2, Op2Class:$rs1, AVL:$vl, ixlenimm:$sew), []>, + (ins Op1Class:$rs2, Op2Class:$rs1, AVL:$vl, sew:$sew), []>, RISCVVPseudo { let mayLoad = 0; let mayStore = 0; @@ -1223,7 +1231,7 @@ class VPseudoBinaryNoMaskPolicy : Pseudo<(outs RetClass:$rd), (ins RetClass:$passthru, Op1Class:$rs2, Op2Class:$rs1, AVL:$vl, - ixlenimm:$sew, ixlenimm:$policy), []>, + sew:$sew, vec_policy:$policy), []>, RISCVVPseudo { let mayLoad = 0; let mayStore = 0; @@ -1243,7 +1251,7 @@ class VPseudoBinaryNoMaskRoundingMode : Pseudo<(outs RetClass:$rd), (ins RetClass:$passthru, Op1Class:$rs2, Op2Class:$rs1, ixlenimm:$rm, - AVL:$vl, ixlenimm:$sew, ixlenimm:$policy), []>, + AVL:$vl, sew:$sew, vec_policy:$policy), []>, RISCVVPseudo { let mayLoad = 0; let mayStore = 0; @@ -1266,7 +1274,7 @@ class VPseudoBinaryMaskPolicyRoundingMode.R:$passthru, Op1Class:$rs2, Op2Class:$rs1, VMaskOp:$vm, ixlenimm:$rm, AVL:$vl, - ixlenimm:$sew, ixlenimm:$policy), []>, + sew:$sew, vec_policy:$policy), []>, RISCVVPseudo { let mayLoad = 0; let mayStore = 0; @@ -1288,8 +1296,8 @@ class VPseudoTiedBinaryNoMask : Pseudo<(outs RetClass:$rd), - (ins RetClass:$rs2, Op2Class:$rs1, AVL:$vl, ixlenimm:$sew, - ixlenimm:$policy), []>, + (ins RetClass:$rs2, Op2Class:$rs1, AVL:$vl, sew:$sew, + vec_policy:$policy), []>, RISCVVPseudo { let mayLoad = 0; let mayStore = 0; @@ -1310,8 +1318,8 @@ class VPseudoTiedBinaryNoMaskRoundingMode, + AVL:$vl, sew:$sew, + vec_policy:$policy), []>, RISCVVPseudo { let mayLoad = 0; let mayStore = 0; @@ -1331,7 +1339,7 @@ class VPseudoIStoreNoMask LMUL, bit Ordered>: Pseudo<(outs), (ins StClass:$rd, GPRMem:$rs1, IdxClass:$rs2, AVL:$vl, - ixlenimm:$sew),[]>, + sew:$sew),[]>, RISCVVPseudo, RISCVVSX { let mayLoad = 0; @@ -1345,7 +1353,7 @@ class VPseudoIStoreMask LMUL, bit Ordered>: Pseudo<(outs), (ins StClass:$rd, GPRMem:$rs1, IdxClass:$rs2, - VMaskOp:$vm, AVL:$vl, ixlenimm:$sew),[]>, + VMaskOp:$vm, AVL:$vl, sew:$sew),[]>, RISCVVPseudo, RISCVVSX { let mayLoad = 0; @@ -1363,7 +1371,7 @@ class VPseudoBinaryMaskPolicy.R:$rd), (ins GetVRegNoV0.R:$passthru, Op1Class:$rs2, Op2Class:$rs1, - VMaskOp:$vm, AVL:$vl, ixlenimm:$sew, ixlenimm:$policy), []>, + VMaskOp:$vm, AVL:$vl, sew:$sew, vec_policy:$policy), []>, RISCVVPseudo { let mayLoad = 0; let mayStore = 0; @@ -1382,7 +1390,7 @@ class VPseudoTernaryMaskPolicy.R:$rd), (ins GetVRegNoV0.R:$passthru, Op1Class:$rs2, Op2Class:$rs1, - VMaskOp:$vm, AVL:$vl, ixlenimm:$sew, ixlenimm:$policy), []>, + VMaskOp:$vm, AVL:$vl, sew:$sew, vec_policy:$policy), []>, RISCVVPseudo { let mayLoad = 0; let mayStore = 0; @@ -1401,7 +1409,7 @@ class VPseudoTernaryMaskPolicyRoundingMode, + AVL:$vl, sew:$sew, vec_policy:$policy), []>, RISCVVPseudo { let mayLoad = 0; let mayStore = 0; @@ -1423,7 +1431,7 @@ class VPseudoBinaryMOutMask, + VMaskOp:$vm, AVL:$vl, sew:$sew), []>, RISCVVPseudo { let mayLoad = 0; let mayStore = 0; @@ -1445,7 +1453,7 @@ class VPseudoTiedBinaryMask.R:$rd), (ins GetVRegNoV0.R:$passthru, Op2Class:$rs1, - VMaskOp:$vm, AVL:$vl, ixlenimm:$sew, ixlenimm:$policy), []>, + VMaskOp:$vm, AVL:$vl, sew:$sew, vec_policy:$policy), []>, RISCVVPseudo { let mayLoad = 0; let mayStore = 0; @@ -1468,7 +1476,7 @@ class VPseudoTiedBinaryMaskRoundingMode, + AVL:$vl, sew:$sew, vec_policy:$policy), []>, RISCVVPseudo { let mayLoad = 0; let mayStore = 0; @@ -1494,9 +1502,9 @@ class VPseudoBinaryCarry, + AVL:$vl, sew:$sew)), []>, RISCVVPseudo { let mayLoad = 0; let mayStore = 0; @@ -1515,7 +1523,7 @@ class VPseudoTiedBinaryCarryIn : Pseudo<(outs RetClass:$rd), (ins RetClass:$passthru, Op1Class:$rs2, Op2Class:$rs1, - VMV0:$carry, AVL:$vl, ixlenimm:$sew), []>, + VMV0:$carry, AVL:$vl, sew:$sew), []>, RISCVVPseudo { let mayLoad = 0; let mayStore = 0; @@ -1534,7 +1542,7 @@ class VPseudoTernaryNoMask : Pseudo<(outs RetClass:$rd), (ins RetClass:$rs3, Op1Class:$rs1, Op2Class:$rs2, - AVL:$vl, ixlenimm:$sew), []>, + AVL:$vl, sew:$sew), []>, RISCVVPseudo { let mayLoad = 0; let mayStore = 0; @@ -1551,7 +1559,7 @@ class VPseudoTernaryNoMaskWithPolicy : Pseudo<(outs RetClass:$rd), (ins RetClass:$rs3, Op1Class:$rs1, Op2Class:$rs2, - AVL:$vl, ixlenimm:$sew, ixlenimm:$policy), []>, + AVL:$vl, sew:$sew, vec_policy:$policy), []>, RISCVVPseudo { let mayLoad = 0; let mayStore = 0; @@ -1570,7 +1578,7 @@ class VPseudoTernaryNoMaskWithPolicyRoundingMode : Pseudo<(outs RetClass:$rd), (ins RetClass:$rs3, Op1Class:$rs1, Op2Class:$rs2, - ixlenimm:$rm, AVL:$vl, ixlenimm:$sew, ixlenimm:$policy), []>, + ixlenimm:$rm, AVL:$vl, sew:$sew, vec_policy:$policy), []>, RISCVVPseudo { let mayLoad = 0; let mayStore = 0; @@ -1589,7 +1597,7 @@ class VPseudoUSSegLoadNoMask NF> : Pseudo<(outs RetClass:$rd), (ins RetClass:$dest, GPRMem:$rs1, AVL:$vl, - ixlenimm:$sew, ixlenimm:$policy), []>, + sew:$sew, vec_policy:$policy), []>, RISCVVPseudo, RISCVVLSEG { let mayLoad = 1; @@ -1606,7 +1614,7 @@ class VPseudoUSSegLoadMask NF> : Pseudo<(outs GetVRegNoV0.R:$rd), (ins GetVRegNoV0.R:$passthru, GPRMem:$rs1, - VMaskOp:$vm, AVL:$vl, ixlenimm:$sew, ixlenimm:$policy), []>, + VMaskOp:$vm, AVL:$vl, sew:$sew, vec_policy:$policy), []>, RISCVVPseudo, RISCVVLSEG { let mayLoad = 1; @@ -1624,7 +1632,7 @@ class VPseudoUSSegLoadFFNoMask NF> : Pseudo<(outs RetClass:$rd, GPR:$vl), (ins RetClass:$dest, GPRMem:$rs1, AVL:$avl, - ixlenimm:$sew, ixlenimm:$policy), []>, + sew:$sew, vec_policy:$policy), []>, RISCVVPseudo, RISCVVLSEG { let mayLoad = 1; @@ -1641,7 +1649,7 @@ class VPseudoUSSegLoadFFMask NF> : Pseudo<(outs GetVRegNoV0.R:$rd, GPR:$vl), (ins GetVRegNoV0.R:$passthru, GPRMem:$rs1, - VMaskOp:$vm, AVL:$avl, ixlenimm:$sew, ixlenimm:$policy), []>, + VMaskOp:$vm, AVL:$avl, sew:$sew, vec_policy:$policy), []>, RISCVVPseudo, RISCVVLSEG { let mayLoad = 1; @@ -1659,7 +1667,7 @@ class VPseudoSSegLoadNoMask NF> : Pseudo<(outs RetClass:$rd), (ins RetClass:$passthru, GPRMem:$rs1, GPR:$offset, AVL:$vl, - ixlenimm:$sew, ixlenimm:$policy), []>, + sew:$sew, vec_policy:$policy), []>, RISCVVPseudo, RISCVVLSEG { let mayLoad = 1; @@ -1676,8 +1684,8 @@ class VPseudoSSegLoadMask NF> : Pseudo<(outs GetVRegNoV0.R:$rd), (ins GetVRegNoV0.R:$passthru, GPRMem:$rs1, - GPR:$offset, VMaskOp:$vm, AVL:$vl, ixlenimm:$sew, - ixlenimm:$policy), []>, + GPR:$offset, VMaskOp:$vm, AVL:$vl, sew:$sew, + vec_policy:$policy), []>, RISCVVPseudo, RISCVVLSEG { let mayLoad = 1; @@ -1698,7 +1706,7 @@ class VPseudoISegLoadNoMask : Pseudo<(outs RetClass:$rd), (ins RetClass:$passthru, GPRMem:$rs1, IdxClass:$offset, AVL:$vl, - ixlenimm:$sew, ixlenimm:$policy), []>, + sew:$sew, vec_policy:$policy), []>, RISCVVPseudo, RISCVVLXSEG { let mayLoad = 1; @@ -1720,8 +1728,8 @@ class VPseudoISegLoadMask : Pseudo<(outs GetVRegNoV0.R:$rd), (ins GetVRegNoV0.R:$passthru, GPRMem:$rs1, - IdxClass:$offset, VMaskOp:$vm, AVL:$vl, ixlenimm:$sew, - ixlenimm:$policy), []>, + IdxClass:$offset, VMaskOp:$vm, AVL:$vl, sew:$sew, + vec_policy:$policy), []>, RISCVVPseudo, RISCVVLXSEG { let mayLoad = 1; @@ -1740,7 +1748,7 @@ class VPseudoUSSegStoreNoMask NF> : Pseudo<(outs), - (ins ValClass:$rd, GPRMem:$rs1, AVL:$vl, ixlenimm:$sew), []>, + (ins ValClass:$rd, GPRMem:$rs1, AVL:$vl, sew:$sew), []>, RISCVVPseudo, RISCVVSSEG { let mayLoad = 0; @@ -1755,7 +1763,7 @@ class VPseudoUSSegStoreMask NF> : Pseudo<(outs), (ins ValClass:$rd, GPRMem:$rs1, - VMaskOp:$vm, AVL:$vl, ixlenimm:$sew), []>, + VMaskOp:$vm, AVL:$vl, sew:$sew), []>, RISCVVPseudo, RISCVVSSEG { let mayLoad = 0; @@ -1770,7 +1778,7 @@ class VPseudoSSegStoreNoMask NF> : Pseudo<(outs), (ins ValClass:$rd, GPRMem:$rs1, GPR:$offset, - AVL:$vl, ixlenimm:$sew), []>, + AVL:$vl, sew:$sew), []>, RISCVVPseudo, RISCVVSSEG { let mayLoad = 0; @@ -1785,7 +1793,7 @@ class VPseudoSSegStoreMask NF> : Pseudo<(outs), (ins ValClass:$rd, GPRMem:$rs1, GPR: $offset, - VMaskOp:$vm, AVL:$vl, ixlenimm:$sew), []>, + VMaskOp:$vm, AVL:$vl, sew:$sew), []>, RISCVVPseudo, RISCVVSSEG { let mayLoad = 0; @@ -1803,7 +1811,7 @@ class VPseudoISegStoreNoMask : Pseudo<(outs), (ins ValClass:$rd, GPRMem:$rs1, IdxClass: $index, - AVL:$vl, ixlenimm:$sew), []>, + AVL:$vl, sew:$sew), []>, RISCVVPseudo, RISCVVSXSEG { let mayLoad = 0; @@ -1821,7 +1829,7 @@ class VPseudoISegStoreMask : Pseudo<(outs), (ins ValClass:$rd, GPRMem:$rs1, IdxClass: $index, - VMaskOp:$vm, AVL:$vl, ixlenimm:$sew), []>, + VMaskOp:$vm, AVL:$vl, sew:$sew), []>, RISCVVPseudo, RISCVVSXSEG { let mayLoad = 0; @@ -6762,13 +6770,13 @@ let Predicates = [HasVInstructions] in { let mayLoad = 0, mayStore = 0, hasSideEffects = 0 in { let HasSEWOp = 1, BaseInstr = VMV_X_S in def PseudoVMV_X_S: - Pseudo<(outs GPR:$rd), (ins VR:$rs2, ixlenimm:$sew), []>, + Pseudo<(outs GPR:$rd), (ins VR:$rs2, sew:$sew), []>, Sched<[WriteVMovXS, ReadVMovXS]>, RISCVVPseudo; let HasVLOp = 1, HasSEWOp = 1, BaseInstr = VMV_S_X, isReMaterializable = 1, Constraints = "$rd = $rs1" in def PseudoVMV_S_X: Pseudo<(outs VR:$rd), - (ins VR:$rs1, GPR:$rs2, AVL:$vl, ixlenimm:$sew), + (ins VR:$rs1, GPR:$rs2, AVL:$vl, sew:$sew), []>, Sched<[WriteVMovSX, ReadVMovSX_V, ReadVMovSX_X]>, RISCVVPseudo; @@ -6785,14 +6793,14 @@ let mayLoad = 0, mayStore = 0, hasSideEffects = 0 in { let HasSEWOp = 1, BaseInstr = VFMV_F_S in def "PseudoVFMV_" # f.FX # "_S" : Pseudo<(outs f.fprclass:$rd), - (ins VR:$rs2, ixlenimm:$sew), []>, + (ins VR:$rs2, sew:$sew), []>, Sched<[WriteVMovFS, ReadVMovFS]>, RISCVVPseudo; let HasVLOp = 1, HasSEWOp = 1, BaseInstr = VFMV_S_F, isReMaterializable = 1, Constraints = "$rd = $rs1" in def "PseudoVFMV_S_" # f.FX : Pseudo<(outs VR:$rd), - (ins VR:$rs1, f.fprclass:$rs2, AVL:$vl, ixlenimm:$sew), + (ins VR:$rs1, f.fprclass:$rs2, AVL:$vl, sew:$sew), []>, Sched<[WriteVMovSF, ReadVMovSF_V, ReadVMovSF_F]>, RISCVVPseudo; diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoXCV.td b/llvm/lib/Target/RISCV/RISCVInstrInfoXCV.td index b54baa16d9286b..4478e246111080 100644 --- a/llvm/lib/Target/RISCV/RISCVInstrInfoXCV.td +++ b/llvm/lib/Target/RISCV/RISCVInstrInfoXCV.td @@ -818,7 +818,7 @@ let Predicates = [HasVendorXCVbi, IsRV32], AddedComplexity = 2 in { let usesCustomInserter = 1 in def Select_GPR_Using_CC_Imm : Pseudo<(outs GPR:$dst), - (ins GPR:$lhs, simm5:$imm5, ixlenimm:$cc, + (ins GPR:$lhs, simm5:$imm5, cond_code:$cc, GPR:$truev, GPR:$falsev), []>; diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoXSf.td b/llvm/lib/Target/RISCV/RISCVInstrInfoXSf.td index 5068d0be0fb49b..81467ada004487 100644 --- a/llvm/lib/Target/RISCV/RISCVInstrInfoXSf.td +++ b/llvm/lib/Target/RISCV/RISCVInstrInfoXSf.td @@ -230,7 +230,7 @@ let Predicates = [HasVendorXSfvfnrclipxfqf], DecoderNamespace = "XSfvfnrclipxfqf class VPseudoVC_X : Pseudo<(outs), (ins OpClass:$op1, payload5:$rs2, payload5:$rd, RS1Class:$r1, - AVL:$vl, ixlenimm:$sew), []>, + AVL:$vl, sew:$sew), []>, RISCVVPseudo { let mayLoad = 0; let mayStore = 0; @@ -243,7 +243,7 @@ class VPseudoVC_X : class VPseudoVC_XV : Pseudo<(outs), (ins OpClass:$op1, payload5:$rd, RS2Class:$rs2, RS1Class:$r1, - AVL:$vl, ixlenimm:$sew), []>, + AVL:$vl, sew:$sew), []>, RISCVVPseudo { let mayLoad = 0; let mayStore = 0; @@ -257,7 +257,7 @@ class VPseudoVC_XVV : Pseudo<(outs), (ins OpClass:$op1, RDClass:$rd, RS2Class:$rs2, RS1Class:$r1, - AVL:$vl, ixlenimm:$sew), []>, + AVL:$vl, sew:$sew), []>, RISCVVPseudo { let mayLoad = 0; let mayStore = 0; @@ -270,7 +270,7 @@ class VPseudoVC_XVV : Pseudo<(outs RDClass:$rd), (ins OpClass:$op1, payload5:$rs2, RS1Class:$r1, - AVL:$vl, ixlenimm:$sew), []>, + AVL:$vl, sew:$sew), []>, RISCVVPseudo { let mayLoad = 0; let mayStore = 0; @@ -284,7 +284,7 @@ class VPseudoVC_V_XV : Pseudo<(outs RDClass:$rd), (ins OpClass:$op1, RS2Class:$rs2, RS1Class:$r1, - AVL:$vl, ixlenimm:$sew), []>, + AVL:$vl, sew:$sew), []>, RISCVVPseudo { let mayLoad = 0; let mayStore = 0; @@ -298,7 +298,7 @@ class VPseudoVC_V_XVV : Pseudo<(outs RDClass:$rd), (ins OpClass:$op1, RDClass:$rs3, RS2Class:$rs2, RS1Class:$r1, - AVL:$vl, ixlenimm:$sew), []>, + AVL:$vl, sew:$sew), []>, RISCVVPseudo { let mayLoad = 0; let mayStore = 0; diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoZfa.td b/llvm/lib/Target/RISCV/RISCVInstrInfoZfa.td index f62a7e1221122b..f13b3e69f84f89 100644 --- a/llvm/lib/Target/RISCV/RISCVInstrInfoZfa.td +++ b/llvm/lib/Target/RISCV/RISCVInstrInfoZfa.td @@ -35,6 +35,8 @@ def LoadFPImmOperand : AsmOperandClass { def loadfpimm : Operand { let ParserMatchClass = LoadFPImmOperand; let PrintMethod = "printFPImmOperand"; + let OperandType = "OPERAND_UIMM5"; + let OperandNamespace = "RISCVOp"; } def RTZArg : AsmOperandClass { @@ -48,6 +50,8 @@ def rtzarg : Operand { let ParserMatchClass = RTZArg; let PrintMethod = "printFRMArg"; let DecoderMethod = "decodeRTZArg"; + let OperandType = "OPERAND_RTZARG"; + let OperandNamespace = "RISCVOp"; } //===----------------------------------------------------------------------===// diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoZvk.td b/llvm/lib/Target/RISCV/RISCVInstrInfoZvk.td index 7ec13e4eaafa7d..782651fd6d0197 100644 --- a/llvm/lib/Target/RISCV/RISCVInstrInfoZvk.td +++ b/llvm/lib/Target/RISCV/RISCVInstrInfoZvk.td @@ -231,7 +231,7 @@ class ZvkMxSet { class VPseudoBinaryNoMask_Zvk : Pseudo<(outs RetClass:$rd_wb), - (ins RetClass:$rd, OpClass:$rs2, AVL:$vl, ixlenimm:$sew, ixlenimm:$policy), []>, + (ins RetClass:$rd, OpClass:$rs2, AVL:$vl, sew:$sew, vec_policy:$policy), []>, RISCVVPseudo { let mayLoad = 0; let mayStore = 0; @@ -248,7 +248,7 @@ class VPseudoTernaryNoMask_Zvk : Pseudo<(outs RetClass:$rd_wb), (ins RetClass:$rd, Op1Class:$rs2, Op2Class:$rs1, - AVL:$vl, ixlenimm:$sew, ixlenimm:$policy), []>, + AVL:$vl, sew:$sew, vec_policy:$policy), []>, RISCVVPseudo { let mayLoad = 0; let mayStore = 0; diff --git a/llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp b/llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp index 395baa5f1aab99..988cb194cd6035 100644 --- a/llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp +++ b/llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp @@ -948,12 +948,17 @@ RISCVTTIImpl::getIntrinsicInstrCost(const IntrinsicCostAttributes &ICA, TTI::TargetCostKind CostKind) { auto *RetTy = ICA.getReturnType(); switch (ICA.getID()) { + case Intrinsic::lrint: + case Intrinsic::llrint: + // We can't currently lower half or bfloat vector lrint/llrint. + if (auto *VecTy = dyn_cast(ICA.getArgTypes()[0]); + VecTy && VecTy->getElementType()->is16bitFPTy()) + return InstructionCost::getInvalid(); + [[fallthrough]]; case Intrinsic::ceil: case Intrinsic::floor: case Intrinsic::trunc: case Intrinsic::rint: - case Intrinsic::lrint: - case Intrinsic::llrint: case Intrinsic::round: case Intrinsic::roundeven: { // These all use the same code. diff --git a/llvm/lib/Target/SPIRV/SPIRVInstructionSelector.cpp b/llvm/lib/Target/SPIRV/SPIRVInstructionSelector.cpp index d9377fe4b91a1a..11ed7d660be09e 100644 --- a/llvm/lib/Target/SPIRV/SPIRVInstructionSelector.cpp +++ b/llvm/lib/Target/SPIRV/SPIRVInstructionSelector.cpp @@ -2547,6 +2547,17 @@ bool SPIRVInstructionSelector::selectIntrinsic(Register ResVReg, return selectExtInst(ResVReg, ResType, I, CL::rsqrt, GL::InverseSqrt); case Intrinsic::spv_sign: return selectSign(ResVReg, ResType, I); + case Intrinsic::spv_group_memory_barrier_with_group_sync: { + Register MemSemReg = + buildI32Constant(SPIRV::MemorySemantics::SequentiallyConsistent, I); + Register ScopeReg = buildI32Constant(SPIRV::Scope::Workgroup, I); + MachineBasicBlock &BB = *I.getParent(); + return BuildMI(BB, I, I.getDebugLoc(), TII.get(SPIRV::OpControlBarrier)) + .addUse(ScopeReg) + .addUse(ScopeReg) + .addUse(MemSemReg) + .constrainAllUses(TII, TRI, RBI); + } break; case Intrinsic::spv_lifetime_start: case Intrinsic::spv_lifetime_end: { unsigned Op = IID == Intrinsic::spv_lifetime_start ? SPIRV::OpLifetimeStart diff --git a/llvm/lib/Target/SPIRV/SPIRVMergeRegionExitTargets.cpp b/llvm/lib/Target/SPIRV/SPIRVMergeRegionExitTargets.cpp index 9930d067173df7..c22492ec43b095 100644 --- a/llvm/lib/Target/SPIRV/SPIRVMergeRegionExitTargets.cpp +++ b/llvm/lib/Target/SPIRV/SPIRVMergeRegionExitTargets.cpp @@ -130,6 +130,13 @@ class SPIRVMergeRegionExitTargets : public FunctionPass { assert(false && "Unhandled terminator type."); } + AllocaInst *CreateVariable(Function &F, Type *Type, + BasicBlock::iterator Position) { + const DataLayout &DL = F.getDataLayout(); + return new AllocaInst(Type, DL.getAllocaAddrSpace(), nullptr, "reg", + Position); + } + // Run the pass on the given convergence region, ignoring the sub-regions. // Returns true if the CFG changed, false otherwise. bool runOnConvergenceRegionNoRecurse(LoopInfo &LI, @@ -152,6 +159,9 @@ class SPIRVMergeRegionExitTargets : public FunctionPass { auto NewExitTarget = BasicBlock::Create(F->getContext(), "new.exit", F); IRBuilder<> Builder(NewExitTarget); + AllocaInst *Variable = CreateVariable(*F, Builder.getInt32Ty(), + F->begin()->getFirstInsertionPt()); + // CodeGen output needs to be stable. Using the set as-is would order // the targets differently depending on the allocation pattern. // Sorting per basic-block ordering in the function. @@ -176,18 +186,16 @@ class SPIRVMergeRegionExitTargets : public FunctionPass { std::vector> ExitToVariable; for (auto Exit : SortedExits) { llvm::Value *Value = createExitVariable(Exit, TargetToValue); + IRBuilder<> B2(Exit); + B2.SetInsertPoint(Exit->getFirstInsertionPt()); + B2.CreateStore(Value, Variable); ExitToVariable.emplace_back(std::make_pair(Exit, Value)); } - // Gather the correct value depending on the exit we came from. - llvm::PHINode *node = - Builder.CreatePHI(Builder.getInt32Ty(), ExitToVariable.size()); - for (auto [BB, Value] : ExitToVariable) { - node->addIncoming(Value, BB); - } + llvm::Value *Load = Builder.CreateLoad(Builder.getInt32Ty(), Variable); // Creating the switch to jump to the correct exit target. - llvm::SwitchInst *Sw = Builder.CreateSwitch(node, SortedExitTargets[0], + llvm::SwitchInst *Sw = Builder.CreateSwitch(Load, SortedExitTargets[0], SortedExitTargets.size() - 1); for (size_t i = 1; i < SortedExitTargets.size(); i++) { BasicBlock *BB = SortedExitTargets[i]; diff --git a/llvm/lib/Target/SPIRV/SPIRVStructurizer.cpp b/llvm/lib/Target/SPIRV/SPIRVStructurizer.cpp index 211a060ee103bc..13e05b67927518 100644 --- a/llvm/lib/Target/SPIRV/SPIRVStructurizer.cpp +++ b/llvm/lib/Target/SPIRV/SPIRVStructurizer.cpp @@ -87,7 +87,7 @@ BasicBlock *getExitFor(const ConvergenceRegion *CR) { // Returns the merge block designated by I if I is a merge instruction, nullptr // otherwise. BasicBlock *getDesignatedMergeBlock(Instruction *I) { - IntrinsicInst *II = dyn_cast(I); + IntrinsicInst *II = dyn_cast_or_null(I); if (II == nullptr) return nullptr; @@ -102,7 +102,7 @@ BasicBlock *getDesignatedMergeBlock(Instruction *I) { // Returns the continue block designated by I if I is an OpLoopMerge, nullptr // otherwise. BasicBlock *getDesignatedContinueBlock(Instruction *I) { - IntrinsicInst *II = dyn_cast(I); + IntrinsicInst *II = dyn_cast_or_null(I); if (II == nullptr) return nullptr; @@ -284,18 +284,6 @@ void replaceBranchTargets(BasicBlock *BB, BasicBlock *OldTarget, assert(false && "Unhandled terminator type."); } -// Replaces basic bloc operands |OldSrc| or OpPhi instructions in |BB| by -// |NewSrc|. This function does not simplify the OpPhi instruction once -// transformed. -void replacePhiTargets(BasicBlock *BB, BasicBlock *OldSrc, BasicBlock *NewSrc) { - for (PHINode &Phi : BB->phis()) { - int index = Phi.getBasicBlockIndex(OldSrc); - if (index == -1) - continue; - Phi.setIncomingBlock(index, NewSrc); - } -} - } // anonymous namespace // Given a reducible CFG, produces a structurized CFG in the SPIR-V sense, @@ -423,7 +411,7 @@ class SPIRVStructurizer : public FunctionPass { } // Splits the given edges by recreating proxy nodes so that the destination - // OpPhi instruction can still be viable. + // has unique incoming edges from this region. // // clang-format off // @@ -436,66 +424,58 @@ class SPIRVStructurizer : public FunctionPass { // A -> D -> C // B -> D -> C // - // But if C had a phi node, adding such proxy-block breaks it. In such case, we must add 1 new block per - // exit, and patchup the phi node: + // This is fine (assuming C has no PHI nodes), but requires handling the merge instruction here. + // By adding a proxy node, we create a regular divergent shape which can easily be regularized later on. // A -> D -> D1 -> C // B -> D -> D2 -> C // - // A, B, D belongs to the construct. D is the exit. D1 and D2 are empty, just used as - // source operands for C's phi node. + // A, B, D belongs to the construct. D is the exit. D1 and D2 are empty. // // clang-format on std::vector createAliasBlocksForComplexEdges(std::vector Edges) { - std::unordered_map Seen; + std::unordered_set Seen; std::vector Output; Output.reserve(Edges.size()); for (auto &[Src, Dst] : Edges) { - auto [iterator, inserted] = Seen.insert({Src, Dst}); - if (inserted) { - Output.emplace_back(Src, Dst); - continue; + auto [Iterator, Inserted] = Seen.insert(Src); + if (!Inserted) { + // Src already a source node. Cannot have 2 edges from A to B. + // Creating alias source block. + BasicBlock *NewSrc = BasicBlock::Create( + F.getContext(), Src->getName() + ".new.src", &F); + replaceBranchTargets(Src, Dst, NewSrc); + IRBuilder<> Builder(NewSrc); + Builder.CreateBr(Dst); + Src = NewSrc; } - // The exact same edge was already seen. Ignoring. - if (iterator->second == Dst) - continue; - - // The same Src block branches to 2 distinct blocks. This will be an - // issue for the generated OpPhi. Creating alias block. - BasicBlock *NewSrc = - BasicBlock::Create(F.getContext(), "new.exit.src", &F); - replaceBranchTargets(Src, Dst, NewSrc); - replacePhiTargets(Dst, Src, NewSrc); - - IRBuilder<> Builder(NewSrc); - Builder.CreateBr(Dst); - - Seen.emplace(NewSrc, Dst); - Output.emplace_back(NewSrc, Dst); + Output.emplace_back(Src, Dst); } return Output; } + AllocaInst *CreateVariable(Function &F, Type *Type, + BasicBlock::iterator Position) { + const DataLayout &DL = F.getDataLayout(); + return new AllocaInst(Type, DL.getAllocaAddrSpace(), nullptr, "reg", + Position); + } + // Given a construct defined by |Header|, and a list of exiting edges // |Edges|, creates a new single exit node, fixing up those edges. BasicBlock *createSingleExitNode(BasicBlock *Header, std::vector &Edges) { - auto NewExit = BasicBlock::Create(F.getContext(), "new.exit", &F); - IRBuilder<> ExitBuilder(NewExit); - std::vector Dsts; - std::unordered_map DstToIndex; - - // Given 2 edges: Src1 -> Dst, Src2 -> Dst: - // If Dst has an PHI node, and Src1 and Src2 are both operands, both Src1 - // and Src2 cannot be hidden by NewExit. Create 2 new nodes: Alias1, - // Alias2 to which NewExit will branch before going to Dst. Then, patchup - // Dst PHI node to look for Alias1 and Alias2. std::vector FixedEdges = createAliasBlocksForComplexEdges(Edges); + std::vector Dsts; + std::unordered_map DstToIndex; + auto NewExit = BasicBlock::Create(F.getContext(), + Header->getName() + ".new.exit", &F); + IRBuilder<> ExitBuilder(NewExit); for (auto &[Src, Dst] : FixedEdges) { if (DstToIndex.count(Dst) != 0) continue; @@ -506,33 +486,34 @@ class SPIRVStructurizer : public FunctionPass { if (Dsts.size() == 1) { for (auto &[Src, Dst] : FixedEdges) { replaceBranchTargets(Src, Dst, NewExit); - replacePhiTargets(Dst, Src, NewExit); } ExitBuilder.CreateBr(Dsts[0]); return NewExit; } - PHINode *PhiNode = - ExitBuilder.CreatePHI(ExitBuilder.getInt32Ty(), FixedEdges.size()); - + AllocaInst *Variable = CreateVariable(F, ExitBuilder.getInt32Ty(), + F.begin()->getFirstInsertionPt()); for (auto &[Src, Dst] : FixedEdges) { - PhiNode->addIncoming(DstToIndex[Dst], Src); + IRBuilder<> B2(Src); + B2.SetInsertPoint(Src->getFirstInsertionPt()); + B2.CreateStore(DstToIndex[Dst], Variable); replaceBranchTargets(Src, Dst, NewExit); - replacePhiTargets(Dst, Src, NewExit); } + llvm::Value *Load = + ExitBuilder.CreateLoad(ExitBuilder.getInt32Ty(), Variable); + // If we can avoid an OpSwitch, generate an OpBranch. Reason is some // OpBranch are allowed to exist without a new OpSelectionMerge if one of // the branch is the parent's merge node, while OpSwitches are not. if (Dsts.size() == 2) { - Value *Condition = ExitBuilder.CreateCmp(CmpInst::ICMP_EQ, - DstToIndex[Dsts[0]], PhiNode); + Value *Condition = + ExitBuilder.CreateCmp(CmpInst::ICMP_EQ, DstToIndex[Dsts[0]], Load); ExitBuilder.CreateCondBr(Condition, Dsts[0], Dsts[1]); return NewExit; } - SwitchInst *Sw = - ExitBuilder.CreateSwitch(PhiNode, Dsts[0], Dsts.size() - 1); + SwitchInst *Sw = ExitBuilder.CreateSwitch(Load, Dsts[0], Dsts.size() - 1); for (auto It = Dsts.begin() + 1; It != Dsts.end(); ++It) { Sw->addCase(DstToIndex[*It], *It); } @@ -576,7 +557,7 @@ class SPIRVStructurizer : public FunctionPass { // Creates a new basic block in F with a single OpUnreachable instruction. BasicBlock *CreateUnreachable(Function &F) { - BasicBlock *BB = BasicBlock::Create(F.getContext(), "new.exit", &F); + BasicBlock *BB = BasicBlock::Create(F.getContext(), "unreachable", &F); IRBuilder<> Builder(BB); Builder.CreateUnreachable(); return BB; @@ -1027,17 +1008,8 @@ class SPIRVStructurizer : public FunctionPass { return Modified; } - bool IsRequiredForPhiNode(BasicBlock *BB) { - for (BasicBlock *Successor : successors(BB)) { - for (PHINode &Phi : Successor->phis()) { - if (Phi.getBasicBlockIndex(BB) != -1) - return true; - } - } - - return false; - } - + // Removes blocks not contributing to any structured CFG. This assumes there + // is no PHI nodes. bool removeUselessBlocks(Function &F) { std::vector ToRemove; @@ -1054,9 +1026,6 @@ class SPIRVStructurizer : public FunctionPass { if (MergeBlocks.count(&BB) != 0 || ContinueBlocks.count(&BB) != 0) continue; - if (IsRequiredForPhiNode(&BB)) - continue; - if (BB.getUniqueSuccessor() == nullptr) continue; @@ -1127,6 +1096,18 @@ class SPIRVStructurizer : public FunctionPass { continue; Modified = true; + + if (Merge == nullptr) { + Merge = *successors(Header).begin(); + IRBuilder<> Builder(Header); + Builder.SetInsertPoint(Header->getTerminator()); + + auto MergeAddress = BlockAddress::get(Merge->getParent(), Merge); + SmallVector Args = {MergeAddress}; + Builder.CreateIntrinsic(Intrinsic::spv_selection_merge, {}, {Args}); + continue; + } + Instruction *SplitInstruction = Merge->getTerminator(); if (isMergeInstruction(SplitInstruction->getPrevNode())) SplitInstruction = SplitInstruction->getPrevNode(); diff --git a/llvm/lib/Target/SPIRV/SPIRVTargetMachine.cpp b/llvm/lib/Target/SPIRV/SPIRVTargetMachine.cpp index e5384b2eb2c2c1..34854f31b3e387 100644 --- a/llvm/lib/Target/SPIRV/SPIRVTargetMachine.cpp +++ b/llvm/lib/Target/SPIRV/SPIRVTargetMachine.cpp @@ -29,6 +29,7 @@ #include "llvm/MC/TargetRegistry.h" #include "llvm/Pass.h" #include "llvm/Target/TargetOptions.h" +#include "llvm/Transforms/Scalar/Reg2Mem.h" #include "llvm/Transforms/Utils.h" #include @@ -169,13 +170,21 @@ void SPIRVPassConfig::addIRPasses() { // - loops have a single back-edge. addPass(createLoopSimplifyPass()); - // 2. Merge the convergence region exit nodes into one. After this step, + // 2. Removes registers whose lifetime spans across basic blocks. Also + // removes phi nodes. This will greatly simplify the next steps. + addPass(createRegToMemWrapperPass()); + + // 3. Merge the convergence region exit nodes into one. After this step, // regions are single-entry, single-exit. This will help determine the // correct merge block. addPass(createSPIRVMergeRegionExitTargetsPass()); - // 3. Structurize. + // 4. Structurize. addPass(createSPIRVStructurizerPass()); + + // 5. Reduce the amount of variables required by pushing some operations + // back to virtual registers. + addPass(createPromoteMemoryToRegisterPass()); } addPass(createSPIRVRegularizerPass()); diff --git a/llvm/lib/Target/SPIRV/SPIRVUtils.cpp b/llvm/lib/Target/SPIRV/SPIRVUtils.cpp index dff33b16b9cfcf..f9b361e163c909 100644 --- a/llvm/lib/Target/SPIRV/SPIRVUtils.cpp +++ b/llvm/lib/Target/SPIRV/SPIRVUtils.cpp @@ -460,53 +460,98 @@ PartialOrderingVisitor::getReachableFrom(BasicBlock *Start) { return Output; } -size_t PartialOrderingVisitor::visit(BasicBlock *BB, size_t Rank) { - if (Visited.count(BB) != 0) - return Rank; +bool PartialOrderingVisitor::CanBeVisited(BasicBlock *BB) const { + for (BasicBlock *P : predecessors(BB)) { + // Ignore back-edges. + if (DT.dominates(BB, P)) + continue; - Loop *L = LI.getLoopFor(BB); - const bool isLoopHeader = LI.isLoopHeader(BB); + // One of the predecessor hasn't been visited. Not ready yet. + if (BlockToOrder.count(P) == 0) + return false; - if (BlockToOrder.count(BB) == 0) { - OrderInfo Info = {Rank, Visited.size()}; - BlockToOrder.emplace(BB, Info); - } else { - BlockToOrder[BB].Rank = std::max(BlockToOrder[BB].Rank, Rank); + // If the block is a loop exit, the loop must be finished before + // we can continue. + Loop *L = LI.getLoopFor(P); + if (L == nullptr || L->contains(BB)) + continue; + + // SPIR-V requires a single back-edge. And the backend first + // step transforms loops into the simplified format. If we have + // more than 1 back-edge, something is wrong. + assert(L->getNumBackEdges() <= 1); + + // If the loop has no latch, loop's rank won't matter, so we can + // proceed. + BasicBlock *Latch = L->getLoopLatch(); + assert(Latch); + if (Latch == nullptr) + continue; + + // The latch is not ready yet, let's wait. + if (BlockToOrder.count(Latch) == 0) + return false; } - for (BasicBlock *Predecessor : predecessors(BB)) { - if (isLoopHeader && L->contains(Predecessor)) { + return true; +} + +size_t PartialOrderingVisitor::GetNodeRank(BasicBlock *BB) const { + size_t result = 0; + + for (BasicBlock *P : predecessors(BB)) { + // Ignore back-edges. + if (DT.dominates(BB, P)) continue; - } - if (BlockToOrder.count(Predecessor) == 0) { - return Rank; + auto Iterator = BlockToOrder.end(); + Loop *L = LI.getLoopFor(P); + BasicBlock *Latch = L ? L->getLoopLatch() : nullptr; + + // If the predecessor is either outside a loop, or part of + // the same loop, simply take its rank + 1. + if (L == nullptr || L->contains(BB) || Latch == nullptr) { + Iterator = BlockToOrder.find(P); + } else { + // Otherwise, take the loop's rank (highest rank in the loop) as base. + // Since loops have a single latch, highest rank is easy to find. + // If the loop has no latch, then it doesn't matter. + Iterator = BlockToOrder.find(Latch); } + + assert(Iterator != BlockToOrder.end()); + result = std::max(result, Iterator->second.Rank + 1); } - Visited.insert(BB); + return result; +} + +size_t PartialOrderingVisitor::visit(BasicBlock *BB, size_t Unused) { + ToVisit.push(BB); + Queued.insert(BB); - SmallVector OtherSuccessors; - SmallVector LoopSuccessors; + while (ToVisit.size() != 0) { + BasicBlock *BB = ToVisit.front(); + ToVisit.pop(); - for (BasicBlock *Successor : successors(BB)) { - // Ignoring back-edges. - if (DT.dominates(Successor, BB)) + if (!CanBeVisited(BB)) { + ToVisit.push(BB); continue; + } - if (isLoopHeader && L->contains(Successor)) { - LoopSuccessors.push_back(Successor); - } else - OtherSuccessors.push_back(Successor); - } + size_t Rank = GetNodeRank(BB); + OrderInfo Info = {Rank, BlockToOrder.size()}; + BlockToOrder.emplace(BB, Info); - for (BasicBlock *BB : LoopSuccessors) - Rank = std::max(Rank, visit(BB, Rank + 1)); + for (BasicBlock *S : successors(BB)) { + if (Queued.count(S) != 0) + continue; + ToVisit.push(S); + Queued.insert(S); + } + } - size_t OutputRank = Rank; - for (BasicBlock *Item : OtherSuccessors) - OutputRank = std::max(OutputRank, visit(Item, Rank + 1)); - return OutputRank; + return 0; } PartialOrderingVisitor::PartialOrderingVisitor(Function &F) { diff --git a/llvm/lib/Target/SPIRV/SPIRVUtils.h b/llvm/lib/Target/SPIRV/SPIRVUtils.h index 83e717e6ea58fd..11fd3a5c61dcae 100644 --- a/llvm/lib/Target/SPIRV/SPIRVUtils.h +++ b/llvm/lib/Target/SPIRV/SPIRVUtils.h @@ -18,6 +18,7 @@ #include "llvm/IR/Dominators.h" #include "llvm/IR/IRBuilder.h" #include "llvm/IR/TypedPointerType.h" +#include #include #include @@ -62,7 +63,9 @@ class SPIRVSubtarget; class PartialOrderingVisitor { DomTreeBuilder::BBDomTree DT; LoopInfo LI; - std::unordered_set Visited = {}; + + std::unordered_set Queued = {}; + std::queue ToVisit = {}; struct OrderInfo { size_t Rank; @@ -80,6 +83,9 @@ class PartialOrderingVisitor { // Visits |BB| with the current rank being |Rank|. size_t visit(BasicBlock *BB, size_t Rank); + size_t GetNodeRank(BasicBlock *BB) const; + bool CanBeVisited(BasicBlock *BB) const; + public: // Build the visitor to operate on the function F. PartialOrderingVisitor(Function &F); diff --git a/llvm/lib/Target/Sparc/MCTargetDesc/SparcInstPrinter.cpp b/llvm/lib/Target/Sparc/MCTargetDesc/SparcInstPrinter.cpp index 5b407a8b6f54a0..4bba54463103bc 100644 --- a/llvm/lib/Target/Sparc/MCTargetDesc/SparcInstPrinter.cpp +++ b/llvm/lib/Target/Sparc/MCTargetDesc/SparcInstPrinter.cpp @@ -38,7 +38,7 @@ bool SparcInstPrinter::isV9(const MCSubtargetInfo &STI) const { return (STI.hasFeature(Sparc::FeatureV9)) != 0; } -void SparcInstPrinter::printRegName(raw_ostream &OS, MCRegister Reg) const { +void SparcInstPrinter::printRegName(raw_ostream &OS, MCRegister Reg) { OS << '%' << getRegisterName(Reg); } diff --git a/llvm/lib/Target/Sparc/MCTargetDesc/SparcInstPrinter.h b/llvm/lib/Target/Sparc/MCTargetDesc/SparcInstPrinter.h index 207a970228058d..52321d56211858 100644 --- a/llvm/lib/Target/Sparc/MCTargetDesc/SparcInstPrinter.h +++ b/llvm/lib/Target/Sparc/MCTargetDesc/SparcInstPrinter.h @@ -24,7 +24,7 @@ class SparcInstPrinter : public MCInstPrinter { const MCRegisterInfo &MRI) : MCInstPrinter(MAI, MII, MRI) {} - void printRegName(raw_ostream &OS, MCRegister Reg) const override; + void printRegName(raw_ostream &OS, MCRegister Reg) override; void printRegName(raw_ostream &OS, MCRegister Reg, unsigned AltIdx) const; void printInst(const MCInst *MI, uint64_t Address, StringRef Annot, const MCSubtargetInfo &STI, raw_ostream &O) override; diff --git a/llvm/lib/Target/SystemZ/MCTargetDesc/SystemZGNUInstPrinter.cpp b/llvm/lib/Target/SystemZ/MCTargetDesc/SystemZGNUInstPrinter.cpp index 05113010794e0b..72b7bd60276a7a 100644 --- a/llvm/lib/Target/SystemZ/MCTargetDesc/SystemZGNUInstPrinter.cpp +++ b/llvm/lib/Target/SystemZ/MCTargetDesc/SystemZGNUInstPrinter.cpp @@ -19,7 +19,7 @@ using namespace llvm; void SystemZGNUInstPrinter::printFormattedRegName(const MCAsmInfo *MAI, MCRegister Reg, - raw_ostream &O) const { + raw_ostream &O) { const char *RegName = getRegisterName(Reg); markup(O, Markup::Register) << '%' << RegName; } diff --git a/llvm/lib/Target/SystemZ/MCTargetDesc/SystemZGNUInstPrinter.h b/llvm/lib/Target/SystemZ/MCTargetDesc/SystemZGNUInstPrinter.h index 8f62ae0e16c006..7095e325c70bc0 100644 --- a/llvm/lib/Target/SystemZ/MCTargetDesc/SystemZGNUInstPrinter.h +++ b/llvm/lib/Target/SystemZ/MCTargetDesc/SystemZGNUInstPrinter.h @@ -38,7 +38,7 @@ class SystemZGNUInstPrinter : public SystemZInstPrinterCommon { private: void printFormattedRegName(const MCAsmInfo *MAI, MCRegister Reg, - raw_ostream &O) const override; + raw_ostream &O) override; }; } // end namespace llvm diff --git a/llvm/lib/Target/SystemZ/MCTargetDesc/SystemZHLASMInstPrinter.cpp b/llvm/lib/Target/SystemZ/MCTargetDesc/SystemZHLASMInstPrinter.cpp index 9abd408324c067..ef9881932f7c08 100644 --- a/llvm/lib/Target/SystemZ/MCTargetDesc/SystemZHLASMInstPrinter.cpp +++ b/llvm/lib/Target/SystemZ/MCTargetDesc/SystemZHLASMInstPrinter.cpp @@ -19,7 +19,7 @@ using namespace llvm; void SystemZHLASMInstPrinter::printFormattedRegName(const MCAsmInfo *MAI, MCRegister Reg, - raw_ostream &O) const { + raw_ostream &O) { const char *RegName = getRegisterName(Reg); // Skip register prefix so that only register number is left assert(isalpha(RegName[0]) && isdigit(RegName[1])); diff --git a/llvm/lib/Target/SystemZ/MCTargetDesc/SystemZHLASMInstPrinter.h b/llvm/lib/Target/SystemZ/MCTargetDesc/SystemZHLASMInstPrinter.h index 9a69e012c72942..ffccbec36c7491 100644 --- a/llvm/lib/Target/SystemZ/MCTargetDesc/SystemZHLASMInstPrinter.h +++ b/llvm/lib/Target/SystemZ/MCTargetDesc/SystemZHLASMInstPrinter.h @@ -37,7 +37,7 @@ class SystemZHLASMInstPrinter : public SystemZInstPrinterCommon { private: void printFormattedRegName(const MCAsmInfo *MAI, MCRegister Reg, - raw_ostream &O) const override; + raw_ostream &O) override; }; } // end namespace llvm diff --git a/llvm/lib/Target/SystemZ/MCTargetDesc/SystemZInstPrinterCommon.cpp b/llvm/lib/Target/SystemZ/MCTargetDesc/SystemZInstPrinterCommon.cpp index 00560ab1f4b18d..fe0f3874765614 100644 --- a/llvm/lib/Target/SystemZ/MCTargetDesc/SystemZInstPrinterCommon.cpp +++ b/llvm/lib/Target/SystemZ/MCTargetDesc/SystemZInstPrinterCommon.cpp @@ -57,8 +57,7 @@ void SystemZInstPrinterCommon::printOperand(const MCOperand &MO, llvm_unreachable("Invalid operand"); } -void SystemZInstPrinterCommon::printRegName(raw_ostream &O, - MCRegister Reg) const { +void SystemZInstPrinterCommon::printRegName(raw_ostream &O, MCRegister Reg) { printFormattedRegName(&MAI, Reg, O); } diff --git a/llvm/lib/Target/SystemZ/MCTargetDesc/SystemZInstPrinterCommon.h b/llvm/lib/Target/SystemZ/MCTargetDesc/SystemZInstPrinterCommon.h index 9a972824f7ffb5..1a11e421691ae3 100644 --- a/llvm/lib/Target/SystemZ/MCTargetDesc/SystemZInstPrinterCommon.h +++ b/llvm/lib/Target/SystemZ/MCTargetDesc/SystemZInstPrinterCommon.h @@ -36,10 +36,10 @@ class SystemZInstPrinterCommon : public MCInstPrinter { void printOperand(const MCOperand &MO, const MCAsmInfo *MAI, raw_ostream &O); virtual void printFormattedRegName(const MCAsmInfo *MAI, MCRegister Reg, - raw_ostream &O) const {} + raw_ostream &O) {} // Override MCInstPrinter. - void printRegName(raw_ostream &O, MCRegister Reg) const override; + void printRegName(raw_ostream &O, MCRegister Reg) override; protected: template diff --git a/llvm/lib/Target/VE/MCTargetDesc/VEInstPrinter.cpp b/llvm/lib/Target/VE/MCTargetDesc/VEInstPrinter.cpp index 8261b5aa7b4e13..47455a9a0274c2 100644 --- a/llvm/lib/Target/VE/MCTargetDesc/VEInstPrinter.cpp +++ b/llvm/lib/Target/VE/MCTargetDesc/VEInstPrinter.cpp @@ -27,7 +27,7 @@ using namespace llvm; #define PRINT_ALIAS_INSTR #include "VEGenAsmWriter.inc" -void VEInstPrinter::printRegName(raw_ostream &OS, MCRegister Reg) const { +void VEInstPrinter::printRegName(raw_ostream &OS, MCRegister Reg) { // Generic registers have identical register name among register classes. unsigned AltIdx = VE::AsmName; // Misc registers have each own name, so no use alt-names. diff --git a/llvm/lib/Target/VE/MCTargetDesc/VEInstPrinter.h b/llvm/lib/Target/VE/MCTargetDesc/VEInstPrinter.h index 65660a49c5e4dd..d5e0ebd3596ca8 100644 --- a/llvm/lib/Target/VE/MCTargetDesc/VEInstPrinter.h +++ b/llvm/lib/Target/VE/MCTargetDesc/VEInstPrinter.h @@ -24,7 +24,7 @@ class VEInstPrinter : public MCInstPrinter { const MCRegisterInfo &MRI) : MCInstPrinter(MAI, MII, MRI) {} - void printRegName(raw_ostream &OS, MCRegister Reg) const override; + void printRegName(raw_ostream &OS, MCRegister Reg) override; void printInst(const MCInst *MI, uint64_t Address, StringRef Annot, const MCSubtargetInfo &STI, raw_ostream &OS) override; diff --git a/llvm/lib/Target/WebAssembly/MCTargetDesc/WebAssemblyInstPrinter.cpp b/llvm/lib/Target/WebAssembly/MCTargetDesc/WebAssemblyInstPrinter.cpp index 4c29b59b3302e4..026f859b15d715 100644 --- a/llvm/lib/Target/WebAssembly/MCTargetDesc/WebAssemblyInstPrinter.cpp +++ b/llvm/lib/Target/WebAssembly/MCTargetDesc/WebAssemblyInstPrinter.cpp @@ -38,8 +38,7 @@ WebAssemblyInstPrinter::WebAssemblyInstPrinter(const MCAsmInfo &MAI, const MCRegisterInfo &MRI) : MCInstPrinter(MAI, MII, MRI) {} -void WebAssemblyInstPrinter::printRegName(raw_ostream &OS, - MCRegister Reg) const { +void WebAssemblyInstPrinter::printRegName(raw_ostream &OS, MCRegister Reg) { assert(Reg.id() != WebAssembly::UnusedReg); // Note that there's an implicit local.get/local.set here! OS << "$" << Reg.id(); diff --git a/llvm/lib/Target/WebAssembly/MCTargetDesc/WebAssemblyInstPrinter.h b/llvm/lib/Target/WebAssembly/MCTargetDesc/WebAssemblyInstPrinter.h index b499926ab82965..e7c5e14973b630 100644 --- a/llvm/lib/Target/WebAssembly/MCTargetDesc/WebAssemblyInstPrinter.h +++ b/llvm/lib/Target/WebAssembly/MCTargetDesc/WebAssemblyInstPrinter.h @@ -35,7 +35,7 @@ class WebAssemblyInstPrinter final : public MCInstPrinter { WebAssemblyInstPrinter(const MCAsmInfo &MAI, const MCInstrInfo &MII, const MCRegisterInfo &MRI); - void printRegName(raw_ostream &OS, MCRegister Reg) const override; + void printRegName(raw_ostream &OS, MCRegister Reg) override; void printInst(const MCInst *MI, uint64_t Address, StringRef Annot, const MCSubtargetInfo &STI, raw_ostream &OS) override; diff --git a/llvm/lib/Target/X86/MCTargetDesc/X86ATTInstPrinter.cpp b/llvm/lib/Target/X86/MCTargetDesc/X86ATTInstPrinter.cpp index 58b4527af6557b..c811d621e60eb7 100644 --- a/llvm/lib/Target/X86/MCTargetDesc/X86ATTInstPrinter.cpp +++ b/llvm/lib/Target/X86/MCTargetDesc/X86ATTInstPrinter.cpp @@ -35,7 +35,7 @@ using namespace llvm; #define PRINT_ALIAS_INSTR #include "X86GenAsmWriter.inc" -void X86ATTInstPrinter::printRegName(raw_ostream &OS, MCRegister Reg) const { +void X86ATTInstPrinter::printRegName(raw_ostream &OS, MCRegister Reg) { markup(OS, Markup::Register) << '%' << getRegisterName(Reg); } diff --git a/llvm/lib/Target/X86/MCTargetDesc/X86ATTInstPrinter.h b/llvm/lib/Target/X86/MCTargetDesc/X86ATTInstPrinter.h index 83040c112b6885..7e525e23236229 100644 --- a/llvm/lib/Target/X86/MCTargetDesc/X86ATTInstPrinter.h +++ b/llvm/lib/Target/X86/MCTargetDesc/X86ATTInstPrinter.h @@ -23,7 +23,7 @@ class X86ATTInstPrinter final : public X86InstPrinterCommon { const MCRegisterInfo &MRI) : X86InstPrinterCommon(MAI, MII, MRI), HasCustomInstComment(false) {} - void printRegName(raw_ostream &OS, MCRegister Reg) const override; + void printRegName(raw_ostream &OS, MCRegister Reg) override; void printInst(const MCInst *MI, uint64_t Address, StringRef Annot, const MCSubtargetInfo &STI, raw_ostream &OS) override; bool printVecCompareInstr(const MCInst *MI, raw_ostream &OS); diff --git a/llvm/lib/Target/X86/MCTargetDesc/X86InstComments.cpp b/llvm/lib/Target/X86/MCTargetDesc/X86InstComments.cpp index 587f923e789f02..49e8bab4c0363d 100644 --- a/llvm/lib/Target/X86/MCTargetDesc/X86InstComments.cpp +++ b/llvm/lib/Target/X86/MCTargetDesc/X86InstComments.cpp @@ -40,6 +40,20 @@ using namespace llvm; CASE_MASK_INS_COMMON(Inst, Suffix, src) \ CASE_MASKZ_INS_COMMON(Inst, Suffix, src) +#define CASE_FPCLASS_PACKED(Inst, src) \ + CASE_AVX_INS_COMMON(Inst, Z, r##src) \ + CASE_AVX_INS_COMMON(Inst, Z256, r##src) \ + CASE_AVX_INS_COMMON(Inst, Z128, r##src) \ + CASE_MASK_INS_COMMON(Inst, Z, r##src) + +#define CASE_FPCLASS_PACKED_MEM(Inst) \ + CASE_FPCLASS_PACKED(Inst, m) \ + CASE_FPCLASS_PACKED(Inst, mb) + +#define CASE_FPCLASS_SCALAR(Inst, src) \ + CASE_AVX_INS_COMMON(Inst, Z, r##src) \ + CASE_MASK_INS_COMMON(Inst, Z, r##src) + #define CASE_PTERNLOG(Inst, src) \ CASE_AVX512_INS_COMMON(Inst, Z, r##src##i) \ CASE_AVX512_INS_COMMON(Inst, Z256, r##src##i) \ @@ -949,6 +963,70 @@ static bool printPTERNLOGComments(const MCInst *MI, raw_ostream &OS, return true; } +static bool printFPCLASSComments(const MCInst *MI, raw_ostream &OS, + const MCInstrInfo &MCII) { + unsigned NumOperands = MI->getNumOperands(); + int SrcIdx; + switch (MI->getOpcode()) { + CASE_FPCLASS_PACKED(FPCLASSPBF16, r) + CASE_FPCLASS_PACKED(FPCLASSPH, r) + CASE_FPCLASS_PACKED(FPCLASSPS, r) + CASE_FPCLASS_PACKED(FPCLASSPD, r) + CASE_FPCLASS_SCALAR(FPCLASSSH, r) + CASE_FPCLASS_SCALAR(FPCLASSSS, r) + CASE_FPCLASS_SCALAR(FPCLASSSD, r) { + SrcIdx = NumOperands - 2; + break; + } + CASE_FPCLASS_PACKED_MEM(FPCLASSPBF16) + CASE_FPCLASS_PACKED_MEM(FPCLASSPH) + CASE_FPCLASS_PACKED_MEM(FPCLASSPS) + CASE_FPCLASS_PACKED_MEM(FPCLASSPD) + CASE_FPCLASS_SCALAR(FPCLASSSH, m) + CASE_FPCLASS_SCALAR(FPCLASSSS, m) + CASE_FPCLASS_SCALAR(FPCLASSSD, m) { + SrcIdx = -1; + break; + } + default: + return false; + } + StringRef DestName = getRegName(MI->getOperand(0).getReg()); + StringRef SrcName = + SrcIdx != -1 ? getRegName(MI->getOperand(SrcIdx).getReg()) : "mem"; + + OS << DestName; + printMasking(OS, MI, MCII); + OS << " = "; + + uint8_t Categories = MI->getOperand(NumOperands - 1).getImm(); + if (Categories == 0) { + OS << "false"; + } else { + static constexpr StringLiteral CategoryNames[] = { + "QuietNaN", + "PositiveZero", + "NegativeZero", + "PositiveInfinity", + "NegativeInfinity", + "Subnormal", + "Negative", + "SignalingNaN", + }; + bool Conjoin = false; + for (size_t I = 0, E = std::size(CategoryNames); I != E; ++I) { + if (Categories & (1 << I)) { + if (Conjoin) + OS << " | "; + Conjoin = true; + OS << "is" << CategoryNames[I] << '(' << SrcName << ')'; + } + } + } + OS << '\n'; + return true; +} + //===----------------------------------------------------------------------===// // Top Level Entrypoint //===----------------------------------------------------------------------===// @@ -970,6 +1048,9 @@ bool llvm::EmitAnyX86InstComments(const MCInst *MI, raw_ostream &OS, if (printPTERNLOGComments(MI, OS, MCII)) return true; + if (printFPCLASSComments(MI, OS, MCII)) + return true; + switch (MI->getOpcode()) { default: // Not an instruction for which we can decode comments. diff --git a/llvm/lib/Target/X86/MCTargetDesc/X86IntelInstPrinter.cpp b/llvm/lib/Target/X86/MCTargetDesc/X86IntelInstPrinter.cpp index cd8b9aa6257300..8e7dae229275bb 100644 --- a/llvm/lib/Target/X86/MCTargetDesc/X86IntelInstPrinter.cpp +++ b/llvm/lib/Target/X86/MCTargetDesc/X86IntelInstPrinter.cpp @@ -33,7 +33,7 @@ using namespace llvm; #define PRINT_ALIAS_INSTR #include "X86GenAsmWriter1.inc" -void X86IntelInstPrinter::printRegName(raw_ostream &OS, MCRegister Reg) const { +void X86IntelInstPrinter::printRegName(raw_ostream &OS, MCRegister Reg) { markup(OS, Markup::Register) << getRegisterName(Reg); } diff --git a/llvm/lib/Target/X86/MCTargetDesc/X86IntelInstPrinter.h b/llvm/lib/Target/X86/MCTargetDesc/X86IntelInstPrinter.h index a34c06782f4042..988ab9626c3fd7 100644 --- a/llvm/lib/Target/X86/MCTargetDesc/X86IntelInstPrinter.h +++ b/llvm/lib/Target/X86/MCTargetDesc/X86IntelInstPrinter.h @@ -24,7 +24,7 @@ class X86IntelInstPrinter final : public X86InstPrinterCommon { const MCRegisterInfo &MRI) : X86InstPrinterCommon(MAI, MII, MRI) {} - void printRegName(raw_ostream &OS, MCRegister Reg) const override; + void printRegName(raw_ostream &OS, MCRegister Reg) override; void printInst(const MCInst *MI, uint64_t Address, StringRef Annot, const MCSubtargetInfo &STI, raw_ostream &OS) override; bool printVecCompareInstr(const MCInst *MI, raw_ostream &OS); diff --git a/llvm/lib/Target/X86/X86ISelLowering.cpp b/llvm/lib/Target/X86/X86ISelLowering.cpp index 1c790f3813b7a4..34bc5d76c15cea 100644 --- a/llvm/lib/Target/X86/X86ISelLowering.cpp +++ b/llvm/lib/Target/X86/X86ISelLowering.cpp @@ -2440,6 +2440,10 @@ X86TargetLowering::X86TargetLowering(const X86TargetMachine &TM, setOperationAction(ISD::FMA, MVT::v32bf16, Legal); setOperationAction(ISD::SETCC, MVT::v32bf16, Custom); } + for (auto VT : {MVT::f16, MVT::f32, MVT::f64}) { + setCondCodeAction(ISD::SETOEQ, VT, Custom); + setCondCodeAction(ISD::SETUNE, VT, Custom); + } } if (!Subtarget.useSoftFloat() && Subtarget.hasVLX()) { @@ -24072,6 +24076,13 @@ SDValue X86TargetLowering::LowerSETCC(SDValue Op, SelectionDAG &DAG) const { return IsStrict ? DAG.getMergeValues({Res, Chain}, dl) : Res; } + if (Subtarget.hasAVX10_2()) { + if (CC == ISD::SETOEQ || CC == ISD::SETUNE) { + auto NewCC = (CC == ISD::SETOEQ) ? X86::COND_E : (X86::COND_NE); + return getSETCC(NewCC, DAG.getNode(X86ISD::UCOMX, dl, MVT::i32, Op0, Op1), + dl, DAG); + } + } // Handle floating point. X86::CondCode CondCode = TranslateX86CC(CC, dl, /*IsFP*/ true, Op0, Op1, DAG); if (CondCode == X86::COND_INVALID) diff --git a/llvm/lib/Target/X86/X86InstrAVX10.td b/llvm/lib/Target/X86/X86InstrAVX10.td index 4d64eb776e09ce..0301c07dfb540b 100644 --- a/llvm/lib/Target/X86/X86InstrAVX10.td +++ b/llvm/lib/Target/X86/X86InstrAVX10.td @@ -1541,6 +1541,24 @@ defm VFNMSUB132NEPBF16 : avx10_fma3p_132_bf16<0x9E, "vfnmsub132nepbf16", X86any_ //------------------------------------------------- // AVX10 COMEF instructions //------------------------------------------------- +multiclass avx10_com_ef Opc, RegisterClass RC, ValueType VT, + SDPatternOperator OpNode, string OpcodeStr, + X86MemOperand x86memop, PatFrag ld_frag, + Domain d, X86FoldableSchedWrite sched = WriteFComX>{ + let ExeDomain = d, mayRaiseFPException = 1, isCodeGenOnly = 1 in { + def rr : AVX512, + EVEX, EVEX_V128, Sched<[sched]>, SIMD_EXC; + let mayLoad = 1 in { + def rm : AVX512, + EVEX, EVEX_V128, Sched<[sched.Folded, sched.ReadAfterFold]>, SIMD_EXC; + } + } +} + multiclass avx10_com_ef_int Opc, X86VectorVTInfo _, SDNode OpNode, string OpcodeStr, Domain d, @@ -1564,6 +1582,15 @@ multiclass avx10_com_ef_int Opc, X86VectorVTInfo _, SDNode OpNode, } let Defs = [EFLAGS], Uses = [MXCSR], Predicates = [HasAVX10_2] in { + defm VUCOMXSDZ : avx10_com_ef<0x2e, FR64X, f64, X86ucomi512, + "vucomxsd", f64mem, loadf64, SSEPackedDouble>, + TB, XS, VEX_LIG, REX_W, EVEX_CD8<64, CD8VT1>; + defm VUCOMXSHZ : avx10_com_ef<0x2e, FR16X, f16, X86ucomi512, + "vucomxsh", f16mem, loadf16, SSEPackedSingle>, + T_MAP5, XD, EVEX_CD8<16, CD8VT1>; + defm VUCOMXSSZ : avx10_com_ef<0x2e, FR32X, f32, X86ucomi512, + "vucomxss", f32mem, loadf32, SSEPackedSingle>, + TB, XD, VEX_LIG, EVEX_CD8<32, CD8VT1>; defm VCOMXSDZ : avx10_com_ef_int<0x2f, v2f64x_info, X86comi512, "vcomxsd", SSEPackedDouble>, TB, XS, VEX_LIG, REX_W, EVEX_CD8<64, CD8VT1>; diff --git a/llvm/lib/Target/X86/X86TargetTransformInfo.cpp b/llvm/lib/Target/X86/X86TargetTransformInfo.cpp index bae223243b3dc9..520284d1d7a488 100644 --- a/llvm/lib/Target/X86/X86TargetTransformInfo.cpp +++ b/llvm/lib/Target/X86/X86TargetTransformInfo.cpp @@ -3068,6 +3068,13 @@ InstructionCost X86TTIImpl::getCastInstrCost(unsigned Opcode, Type *Dst, if (auto KindCost = Entry->Cost[CostKind]) return *KindCost; } + + if ((ISD == ISD::FP_ROUND && SimpleDstTy == MVT::f16) || + (ISD == ISD::FP_EXTEND && SimpleSrcTy == MVT::f16)) { + // fp16 conversions not covered by any table entries require a libcall. + // Return a large (arbitrary) number to model this. + return InstructionCost(64); + } } // Fall back to legalized types. @@ -3174,11 +3181,6 @@ InstructionCost X86TTIImpl::getCastInstrCost(unsigned Opcode, Type *Dst, TTI::CastContextHint::None, CostKind); } - if (ISD == ISD::FP_ROUND && LTDest.second.getScalarType() == MVT::f16) { - // Conversion requires a libcall. - return InstructionCost::getInvalid(); - } - // TODO: Allow non-throughput costs that aren't binary. auto AdjustCost = [&CostKind](InstructionCost Cost, InstructionCost N = 1) -> InstructionCost { diff --git a/llvm/lib/Target/XCore/MCTargetDesc/XCoreInstPrinter.cpp b/llvm/lib/Target/XCore/MCTargetDesc/XCoreInstPrinter.cpp index eda90d3101ab48..707c4a79087280 100644 --- a/llvm/lib/Target/XCore/MCTargetDesc/XCoreInstPrinter.cpp +++ b/llvm/lib/Target/XCore/MCTargetDesc/XCoreInstPrinter.cpp @@ -27,7 +27,7 @@ using namespace llvm; #include "XCoreGenAsmWriter.inc" -void XCoreInstPrinter::printRegName(raw_ostream &OS, MCRegister Reg) const { +void XCoreInstPrinter::printRegName(raw_ostream &OS, MCRegister Reg) { OS << StringRef(getRegisterName(Reg)).lower(); } diff --git a/llvm/lib/Target/XCore/MCTargetDesc/XCoreInstPrinter.h b/llvm/lib/Target/XCore/MCTargetDesc/XCoreInstPrinter.h index 916ca99968fbb0..2b47de457322ee 100644 --- a/llvm/lib/Target/XCore/MCTargetDesc/XCoreInstPrinter.h +++ b/llvm/lib/Target/XCore/MCTargetDesc/XCoreInstPrinter.h @@ -31,7 +31,7 @@ class XCoreInstPrinter : public MCInstPrinter { void printInstruction(const MCInst *MI, uint64_t Address, raw_ostream &O); static const char *getRegisterName(MCRegister Reg); - void printRegName(raw_ostream &OS, MCRegister Reg) const override; + void printRegName(raw_ostream &OS, MCRegister Reg) override; void printInst(const MCInst *MI, uint64_t Address, StringRef Annot, const MCSubtargetInfo &STI, raw_ostream &O) override; diff --git a/llvm/lib/Target/Xtensa/MCTargetDesc/XtensaInstPrinter.cpp b/llvm/lib/Target/Xtensa/MCTargetDesc/XtensaInstPrinter.cpp index fe1dc0e2e483e7..e04d7bd211216f 100644 --- a/llvm/lib/Target/Xtensa/MCTargetDesc/XtensaInstPrinter.cpp +++ b/llvm/lib/Target/Xtensa/MCTargetDesc/XtensaInstPrinter.cpp @@ -74,7 +74,7 @@ void XtensaInstPrinter::printInst(const MCInst *MI, uint64_t Address, printAnnotation(O, Annot); } -void XtensaInstPrinter::printRegName(raw_ostream &O, MCRegister Reg) const { +void XtensaInstPrinter::printRegName(raw_ostream &O, MCRegister Reg) { O << getRegisterName(Reg); } diff --git a/llvm/lib/Target/Xtensa/MCTargetDesc/XtensaInstPrinter.h b/llvm/lib/Target/Xtensa/MCTargetDesc/XtensaInstPrinter.h index 46a35ae6f4e3fa..4122b1ff2310b7 100644 --- a/llvm/lib/Target/Xtensa/MCTargetDesc/XtensaInstPrinter.h +++ b/llvm/lib/Target/Xtensa/MCTargetDesc/XtensaInstPrinter.h @@ -36,7 +36,7 @@ class XtensaInstPrinter : public MCInstPrinter { static void printOperand(const MCOperand &MO, raw_ostream &O); // Override MCInstPrinter. - void printRegName(raw_ostream &O, MCRegister Reg) const override; + void printRegName(raw_ostream &O, MCRegister Reg) override; void printInst(const MCInst *MI, uint64_t Address, StringRef Annot, const MCSubtargetInfo &STI, raw_ostream &O) override; diff --git a/llvm/lib/TargetParser/RISCVISAInfo.cpp b/llvm/lib/TargetParser/RISCVISAInfo.cpp index caa5a97747ee57..de5b5c39c9ed27 100644 --- a/llvm/lib/TargetParser/RISCVISAInfo.cpp +++ b/llvm/lib/TargetParser/RISCVISAInfo.cpp @@ -751,17 +751,6 @@ Error RISCVISAInfo::checkDependency() { if (HasZvl && !HasVector) return getExtensionRequiresError("zvl*b", "v' or 'zve*"); - if (!HasVector) - for (auto Ext : - {"zvbb", "zvbc32e", "zvkb", "zvkg", "zvkgs", "zvkned", "zvknha", "zvksed", "zvksh"}) - if (Exts.count(Ext)) - return getExtensionRequiresError(Ext, "v' or 'zve*"); - - if (!Exts.count("zve64x")) - for (auto Ext : {"zvknhb", "zvbc"}) - if (Exts.count(Ext)) - return getExtensionRequiresError(Ext, "v' or 'zve64*"); - if ((HasZcmt || Exts.count("zcmp")) && HasD && (HasC || Exts.count("zcd"))) return getError(Twine("'") + (HasZcmt ? "zcmt" : "zcmp") + "' extension is incompatible with '" + diff --git a/llvm/lib/Transforms/IPO/FunctionSpecialization.cpp b/llvm/lib/Transforms/IPO/FunctionSpecialization.cpp index 8e6993d35d4991..919d3143a13f7e 100644 --- a/llvm/lib/Transforms/IPO/FunctionSpecialization.cpp +++ b/llvm/lib/Transforms/IPO/FunctionSpecialization.cpp @@ -643,6 +643,18 @@ FunctionSpecializer::~FunctionSpecializer() { cleanUpSSA(); } +/// Get the unsigned Value of given Cost object. Assumes the Cost is always +/// non-negative, which is true for both TCK_CodeSize and TCK_Latency, and +/// always Valid. +static unsigned getCostValue(const Cost &C) { + int64_t Value = *C.getValue(); + + assert(Value >= 0 && "CodeSize and Latency cannot be negative"); + // It is safe to down cast since we know the arguments cannot be negative and + // Cost is of type int64_t. + return static_cast(Value); +} + /// Attempt to specialize functions in the module to enable constant /// propagation across function boundaries. /// @@ -757,6 +769,11 @@ bool FunctionSpecializer::run() { SmallVector Clones; for (unsigned I = 0; I < NSpecs; ++I) { Spec &S = AllSpecs[BestSpecs[I]]; + + // Accumulate the codesize growth for the function, now we are creating the + // specialization. + FunctionGrowth[S.F] += S.CodeSize; + S.Clone = createSpecialization(S.F, S.Sig); // Update the known call sites to call the clone. @@ -835,18 +852,6 @@ static Function *cloneCandidateFunction(Function *F, unsigned NSpecs) { return Clone; } -/// Get the unsigned Value of given Cost object. Assumes the Cost is always -/// non-negative, which is true for both TCK_CodeSize and TCK_Latency, and -/// always Valid. -static unsigned getCostValue(const Cost &C) { - int64_t Value = *C.getValue(); - - assert(Value >= 0 && "CodeSize and Latency cannot be negative"); - // It is safe to down cast since we know the arguments cannot be negative and - // Cost is of type int64_t. - return static_cast(Value); -} - bool FunctionSpecializer::findSpecializations(Function *F, unsigned FuncSize, SmallVectorImpl &AllSpecs, SpecMap &SM) { @@ -922,16 +927,14 @@ bool FunctionSpecializer::findSpecializations(Function *F, unsigned FuncSize, } CodeSize += Visitor.getCodeSizeSavingsFromPendingPHIs(); + unsigned CodeSizeSavings = getCostValue(CodeSize); + unsigned SpecSize = FuncSize - CodeSizeSavings; + auto IsProfitable = [&]() -> bool { // No check required. if (ForceSpecialization) return true; - unsigned CodeSizeSavings = getCostValue(CodeSize); - // TODO: We should only accumulate codesize increase of specializations - // that are actually created. - FunctionGrowth[F] += FuncSize - CodeSizeSavings; - LLVM_DEBUG( dbgs() << "FnSpecialization: Specialization bonus {Inlining = " << Score << " (" << (Score * 100 / FuncSize) << "%)}\n"); @@ -962,7 +965,7 @@ bool FunctionSpecializer::findSpecializations(Function *F, unsigned FuncSize, if (LatencySavings < MinLatencySavings * FuncSize / 100) return false; // Maximum codesize growth. - if (FunctionGrowth[F] / FuncSize > MaxCodeSizeGrowth) + if ((FunctionGrowth[F] + SpecSize) / FuncSize > MaxCodeSizeGrowth) return false; Score += std::max(CodeSizeSavings, LatencySavings); @@ -974,7 +977,7 @@ bool FunctionSpecializer::findSpecializations(Function *F, unsigned FuncSize, continue; // Create a new specialisation entry. - auto &Spec = AllSpecs.emplace_back(F, S, Score); + auto &Spec = AllSpecs.emplace_back(F, S, Score, SpecSize); if (CS.getFunction() != F) Spec.CallSites.push_back(&CS); const unsigned Index = AllSpecs.size() - 1; diff --git a/llvm/lib/Transforms/Utils/InlineFunction.cpp b/llvm/lib/Transforms/Utils/InlineFunction.cpp index 4ad426285ce2f0..a27cb4dd219c30 100644 --- a/llvm/lib/Transforms/Utils/InlineFunction.cpp +++ b/llvm/lib/Transforms/Utils/InlineFunction.cpp @@ -181,9 +181,21 @@ namespace { } } }; - } // end anonymous namespace +static IntrinsicInst *getConvergenceEntry(BasicBlock &BB) { + auto *I = BB.getFirstNonPHI(); + while (I) { + if (auto *IntrinsicCall = dyn_cast(I)) { + if (IntrinsicCall->isEntry()) { + return IntrinsicCall; + } + } + I = I->getNextNode(); + } + return nullptr; +} + /// Get or create a target for the branch from ResumeInsts. BasicBlock *LandingPadInliningInfo::getInnerResumeDest() { if (InnerResumeDest) return InnerResumeDest; @@ -2496,15 +2508,10 @@ llvm::InlineResult llvm::InlineFunction(CallBase &CB, InlineFunctionInfo &IFI, // fully implements convergence control tokens, there is no mixing of // controlled and uncontrolled convergent operations in the whole program. if (CB.isConvergent()) { - auto *I = CalledFunc->getEntryBlock().getFirstNonPHI(); - if (auto *IntrinsicCall = dyn_cast(I)) { - if (IntrinsicCall->getIntrinsicID() == - Intrinsic::experimental_convergence_entry) { - if (!ConvergenceControlToken) { - return InlineResult::failure( - "convergent call needs convergencectrl operand"); - } - } + if (!ConvergenceControlToken && + getConvergenceEntry(CalledFunc->getEntryBlock())) { + return InlineResult::failure( + "convergent call needs convergencectrl operand"); } } @@ -2795,13 +2802,10 @@ llvm::InlineResult llvm::InlineFunction(CallBase &CB, InlineFunctionInfo &IFI, } if (ConvergenceControlToken) { - auto *I = FirstNewBlock->getFirstNonPHI(); - if (auto *IntrinsicCall = dyn_cast(I)) { - if (IntrinsicCall->getIntrinsicID() == - Intrinsic::experimental_convergence_entry) { - IntrinsicCall->replaceAllUsesWith(ConvergenceControlToken); - IntrinsicCall->eraseFromParent(); - } + IntrinsicInst *IntrinsicCall = getConvergenceEntry(*FirstNewBlock); + if (IntrinsicCall) { + IntrinsicCall->replaceAllUsesWith(ConvergenceControlToken); + IntrinsicCall->eraseFromParent(); } } diff --git a/llvm/lib/Transforms/Vectorize/LoopVectorize.cpp b/llvm/lib/Transforms/Vectorize/LoopVectorize.cpp index 778d928252e051..150fc4a42b4847 100644 --- a/llvm/lib/Transforms/Vectorize/LoopVectorize.cpp +++ b/llvm/lib/Transforms/Vectorize/LoopVectorize.cpp @@ -581,8 +581,8 @@ class InnerLoopVectorizer { /// Allow subclasses to override and print debug traces before/after vplan /// execution, when trace information is requested. - virtual void printDebugTracesAtStart(){}; - virtual void printDebugTracesAtEnd(){}; + virtual void printDebugTracesAtStart() {} + virtual void printDebugTracesAtEnd() {} /// The original loop. Loop *OrigLoop; @@ -1310,7 +1310,7 @@ class LoopVectorizationCostModel { return false; case cl::BOU_FALSE: return true; - }; + } llvm_unreachable("impossible case value"); } @@ -9065,7 +9065,7 @@ LoopVectorizationPlanner::tryToBuildVPlanWithVPRecipes(VFRange &Range) { if (!getDecisionAndClampRange(ApplyIG, Range)) continue; InterleaveGroups.insert(IG); - }; + } // --------------------------------------------------------------------------- // Construct recipes for the instructions in the loop diff --git a/llvm/lib/Transforms/Vectorize/SandboxVectorizer/Legality.cpp b/llvm/lib/Transforms/Vectorize/SandboxVectorizer/Legality.cpp index 346d8a90589f55..1cc6356300e492 100644 --- a/llvm/lib/Transforms/Vectorize/SandboxVectorizer/Legality.cpp +++ b/llvm/lib/Transforms/Vectorize/SandboxVectorizer/Legality.cpp @@ -55,6 +55,21 @@ LegalityAnalysis::notVectorizableBasedOnOpcodesAndTypes( return ResultReason::DiffMathFlags; } + // TODO: Allow vectorization by using common flags. + // For now Pack if they don't have the same wrap flags. + bool CanHaveWrapFlags = + isa(I0) || isa(I0); + if (CanHaveWrapFlags) { + bool NUW0 = I0->hasNoUnsignedWrap(); + bool NSW0 = I0->hasNoSignedWrap(); + if (any_of(drop_begin(Bndl), [NUW0, NSW0](auto *V) { + return cast(V)->hasNoUnsignedWrap() != NUW0 || + cast(V)->hasNoSignedWrap() != NSW0; + })) { + return ResultReason::DiffWrapFlags; + } + } + // TODO: Missing checks return std::nullopt; diff --git a/llvm/lib/Transforms/Vectorize/VPlan.h b/llvm/lib/Transforms/Vectorize/VPlan.h index a34e34a0d71f1e..0e0c64f6df9cba 100644 --- a/llvm/lib/Transforms/Vectorize/VPlan.h +++ b/llvm/lib/Transforms/Vectorize/VPlan.h @@ -1688,13 +1688,18 @@ class VPWidenIntrinsicRecipe : public VPRecipeWithIRFlags { VPWidenIntrinsicRecipe(Intrinsic::ID VectorIntrinsicID, ArrayRef CallArguments, Type *Ty, - bool MayReadFromMemory, bool MayWriteToMemory, - bool MayHaveSideEffects, DebugLoc DL = {}) + DebugLoc DL = {}) : VPRecipeWithIRFlags(VPDef::VPWidenIntrinsicSC, CallArguments), - VectorIntrinsicID(VectorIntrinsicID), ResultTy(Ty), - MayReadFromMemory(MayReadFromMemory), - MayWriteToMemory(MayWriteToMemory), - MayHaveSideEffects(MayHaveSideEffects) {} + VectorIntrinsicID(VectorIntrinsicID), ResultTy(Ty) { + LLVMContext &Ctx = Ty->getContext(); + AttributeList Attrs = Intrinsic::getAttributes(Ctx, VectorIntrinsicID); + MemoryEffects ME = Attrs.getMemoryEffects(); + MayReadFromMemory = ME.onlyWritesMemory(); + MayWriteToMemory = ME.onlyReadsMemory(); + MayHaveSideEffects = MayWriteToMemory || + !Attrs.hasFnAttr(Attribute::NoUnwind) || + !Attrs.hasFnAttr(Attribute::WillReturn); + } ~VPWidenIntrinsicRecipe() override = default; @@ -2050,6 +2055,10 @@ class VPHeaderPHIRecipe : public VPSingleDefRecipe { /// Generate the phi nodes. void execute(VPTransformState &State) override = 0; + /// Return the cost of this header phi recipe. + InstructionCost computeCost(ElementCount VF, + VPCostContext &Ctx) const override; + #if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP) /// Print the recipe. void print(raw_ostream &O, const Twine &Indent, @@ -2295,6 +2304,10 @@ struct VPFirstOrderRecurrencePHIRecipe : public VPHeaderPHIRecipe { void execute(VPTransformState &State) override; + /// Return the cost of this first-order recurrence phi recipe. + InstructionCost computeCost(ElementCount VF, + VPCostContext &Ctx) const override; + #if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP) /// Print the recipe. void print(raw_ostream &O, const Twine &Indent, @@ -3134,6 +3147,13 @@ class VPCanonicalIVPHIRecipe : public VPHeaderPHIRecipe { /// canonical, i.e. has the same start and step (of 1) as the canonical IV. bool isCanonical(InductionDescriptor::InductionKind Kind, VPValue *Start, VPValue *Step) const; + + /// Return the cost of this VPCanonicalIVPHIRecipe. + InstructionCost computeCost(ElementCount VF, + VPCostContext &Ctx) const override { + // For now, match the behavior of the legacy cost model. + return 0; + } }; /// A recipe for generating the active lane mask for the vector loop that is @@ -3196,6 +3216,13 @@ class VPEVLBasedIVPHIRecipe : public VPHeaderPHIRecipe { /// TODO: investigate if it can share the code with VPCanonicalIVPHIRecipe. void execute(VPTransformState &State) override; + /// Return the cost of this VPEVLBasedIVPHIRecipe. + InstructionCost computeCost(ElementCount VF, + VPCostContext &Ctx) const override { + // For now, match the behavior of the legacy cost model. + return 0; + } + /// Returns true if the recipe only uses the first lane of operand \p Op. bool onlyFirstLaneUsed(const VPValue *Op) const override { assert(is_contained(operands(), Op) && diff --git a/llvm/lib/Transforms/Vectorize/VPlanRecipes.cpp b/llvm/lib/Transforms/Vectorize/VPlanRecipes.cpp index b1e6086398c4df..de7023167df899 100644 --- a/llvm/lib/Transforms/Vectorize/VPlanRecipes.cpp +++ b/llvm/lib/Transforms/Vectorize/VPlanRecipes.cpp @@ -1589,6 +1589,11 @@ void VPWidenCastRecipe::print(raw_ostream &O, const Twine &Indent, } #endif +InstructionCost VPHeaderPHIRecipe::computeCost(ElementCount VF, + VPCostContext &Ctx) const { + return Ctx.TTI.getCFInstrCost(Instruction::PHI, TTI::TCK_RecipThroughput); +} + /// This function adds /// (StartIdx * Step, (StartIdx + 1) * Step, (StartIdx + 2) * Step, ...) /// to each vector element of Val. The sequence starts at StartIndex. @@ -3334,6 +3339,23 @@ void VPFirstOrderRecurrencePHIRecipe::execute(VPTransformState &State) { State.set(this, Phi); } +InstructionCost +VPFirstOrderRecurrencePHIRecipe::computeCost(ElementCount VF, + VPCostContext &Ctx) const { + if (VF.isScalable() && VF.getKnownMinValue() == 1) + return InstructionCost::getInvalid(); + + SmallVector Mask(VF.getKnownMinValue()); + std::iota(Mask.begin(), Mask.end(), VF.getKnownMinValue() - 1); + Type *VectorTy = + ToVectorTy(Ctx.Types.inferScalarType(this->getVPSingleValue()), VF); + + TTI::TargetCostKind CostKind = TTI::TCK_RecipThroughput; + return Ctx.TTI.getShuffleCost(TargetTransformInfo::SK_Splice, + cast(VectorTy), Mask, CostKind, + VF.getKnownMinValue() - 1); +} + #if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP) void VPFirstOrderRecurrencePHIRecipe::print(raw_ostream &O, const Twine &Indent, VPSlotTracker &SlotTracker) const { diff --git a/llvm/lib/Transforms/Vectorize/VPlanTransforms.cpp b/llvm/lib/Transforms/Vectorize/VPlanTransforms.cpp index 03c4110761ac6a..355781f955052e 100644 --- a/llvm/lib/Transforms/Vectorize/VPlanTransforms.cpp +++ b/llvm/lib/Transforms/Vectorize/VPlanTransforms.cpp @@ -1489,7 +1489,7 @@ static void transformRecipestoEVLRecipes(VPlan &Plan, VPValue &EVL) { Ops.push_back(&EVL); return new VPWidenIntrinsicRecipe(Intrinsic::vp_select, Ops, TypeInfo.inferScalarType(Sel), - false, false, false); + Sel->getDebugLoc()); }) .Default([&](VPRecipeBase *R) { return nullptr; }); diff --git a/llvm/test/Analysis/CostModel/RISCV/fround.ll b/llvm/test/Analysis/CostModel/RISCV/fround.ll index c6826760a45bee..b0964983550814 100644 --- a/llvm/test/Analysis/CostModel/RISCV/fround.ll +++ b/llvm/test/Analysis/CostModel/RISCV/fround.ll @@ -425,15 +425,15 @@ define void @rint_fp16() { define void @lrint() { ; CHECK-LABEL: 'lrint' ; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %1 = call i64 @llvm.lrint.i64.bf16(bfloat undef) -; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %2 = call <2 x i64> @llvm.lrint.v2i64.v2bf16(<2 x bfloat> undef) -; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %3 = call <4 x i64> @llvm.lrint.v4i64.v4bf16(<4 x bfloat> undef) -; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %4 = call <8 x i64> @llvm.lrint.v8i64.v8bf16(<8 x bfloat> undef) -; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %5 = call <16 x i64> @llvm.lrint.v16i64.v16bf16(<16 x bfloat> undef) -; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %6 = call @llvm.lrint.nxv1i64.nxv1bf16( undef) -; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %7 = call @llvm.lrint.nxv2i64.nxv2bf16( undef) -; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %8 = call @llvm.lrint.nxv4i64.nxv4bf16( undef) -; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %9 = call @llvm.lrint.nxv8i64.nxv8bf16( undef) -; CHECK-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %10 = call @llvm.lrint.nxv16i64.nxv16bf16( undef) +; CHECK-NEXT: Cost Model: Invalid cost for instruction: %2 = call <2 x i64> @llvm.lrint.v2i64.v2bf16(<2 x bfloat> undef) +; CHECK-NEXT: Cost Model: Invalid cost for instruction: %3 = call <4 x i64> @llvm.lrint.v4i64.v4bf16(<4 x bfloat> undef) +; CHECK-NEXT: Cost Model: Invalid cost for instruction: %4 = call <8 x i64> @llvm.lrint.v8i64.v8bf16(<8 x bfloat> undef) +; CHECK-NEXT: Cost Model: Invalid cost for instruction: %5 = call <16 x i64> @llvm.lrint.v16i64.v16bf16(<16 x bfloat> undef) +; CHECK-NEXT: Cost Model: Invalid cost for instruction: %6 = call @llvm.lrint.nxv1i64.nxv1bf16( undef) +; CHECK-NEXT: Cost Model: Invalid cost for instruction: %7 = call @llvm.lrint.nxv2i64.nxv2bf16( undef) +; CHECK-NEXT: Cost Model: Invalid cost for instruction: %8 = call @llvm.lrint.nxv4i64.nxv4bf16( undef) +; CHECK-NEXT: Cost Model: Invalid cost for instruction: %9 = call @llvm.lrint.nxv8i64.nxv8bf16( undef) +; CHECK-NEXT: Cost Model: Invalid cost for instruction: %10 = call @llvm.lrint.nxv16i64.nxv16bf16( undef) ; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %11 = call i64 @llvm.lrint.i64.f32(float undef) ; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %12 = call <2 x i64> @llvm.lrint.v2i64.v2f32(<2 x float> undef) ; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %13 = call <4 x i64> @llvm.lrint.v4i64.v4f32(<4 x float> undef) @@ -490,15 +490,15 @@ define void @lrint() { define void @lrint_fp16() { ; CHECK-LABEL: 'lrint_fp16' ; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %1 = call i64 @llvm.lrint.i64.f16(half undef) -; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %2 = call <2 x i64> @llvm.lrint.v2i64.v2f16(<2 x half> undef) -; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %3 = call <4 x i64> @llvm.lrint.v4i64.v4f16(<4 x half> undef) -; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %4 = call <8 x i64> @llvm.lrint.v8i64.v8f16(<8 x half> undef) -; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %5 = call <16 x i64> @llvm.lrint.v16i64.v16f16(<16 x half> undef) -; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %6 = call @llvm.lrint.nxv1i64.nxv1f16( undef) -; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %7 = call @llvm.lrint.nxv2i64.nxv2f16( undef) -; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %8 = call @llvm.lrint.nxv4i64.nxv4f16( undef) -; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %9 = call @llvm.lrint.nxv8i64.nxv8f16( undef) -; CHECK-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %10 = call @llvm.lrint.nxv16i64.nxv16f16( undef) +; CHECK-NEXT: Cost Model: Invalid cost for instruction: %2 = call <2 x i64> @llvm.lrint.v2i64.v2f16(<2 x half> undef) +; CHECK-NEXT: Cost Model: Invalid cost for instruction: %3 = call <4 x i64> @llvm.lrint.v4i64.v4f16(<4 x half> undef) +; CHECK-NEXT: Cost Model: Invalid cost for instruction: %4 = call <8 x i64> @llvm.lrint.v8i64.v8f16(<8 x half> undef) +; CHECK-NEXT: Cost Model: Invalid cost for instruction: %5 = call <16 x i64> @llvm.lrint.v16i64.v16f16(<16 x half> undef) +; CHECK-NEXT: Cost Model: Invalid cost for instruction: %6 = call @llvm.lrint.nxv1i64.nxv1f16( undef) +; CHECK-NEXT: Cost Model: Invalid cost for instruction: %7 = call @llvm.lrint.nxv2i64.nxv2f16( undef) +; CHECK-NEXT: Cost Model: Invalid cost for instruction: %8 = call @llvm.lrint.nxv4i64.nxv4f16( undef) +; CHECK-NEXT: Cost Model: Invalid cost for instruction: %9 = call @llvm.lrint.nxv8i64.nxv8f16( undef) +; CHECK-NEXT: Cost Model: Invalid cost for instruction: %10 = call @llvm.lrint.nxv16i64.nxv16f16( undef) ; CHECK-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret void ; call i64 @llvm.lrint.f16(half undef) @@ -517,15 +517,15 @@ define void @lrint_fp16() { define void @llrint() { ; CHECK-LABEL: 'llrint' ; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %1 = call i64 @llvm.llrint.i64.bf16(bfloat undef) -; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %2 = call <2 x i64> @llvm.llrint.v2i64.v2bf16(<2 x bfloat> undef) -; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %3 = call <4 x i64> @llvm.llrint.v4i64.v4bf16(<4 x bfloat> undef) -; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %4 = call <8 x i64> @llvm.llrint.v8i64.v8bf16(<8 x bfloat> undef) -; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %5 = call <16 x i64> @llvm.llrint.v16i64.v16bf16(<16 x bfloat> undef) -; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %6 = call @llvm.llrint.nxv1i64.nxv1bf16( undef) -; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %7 = call @llvm.llrint.nxv2i64.nxv2bf16( undef) -; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %8 = call @llvm.llrint.nxv4i64.nxv4bf16( undef) -; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %9 = call @llvm.llrint.nxv8i64.nxv8bf16( undef) -; CHECK-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %10 = call @llvm.llrint.nxv16i64.nxv16bf16( undef) +; CHECK-NEXT: Cost Model: Invalid cost for instruction: %2 = call <2 x i64> @llvm.llrint.v2i64.v2bf16(<2 x bfloat> undef) +; CHECK-NEXT: Cost Model: Invalid cost for instruction: %3 = call <4 x i64> @llvm.llrint.v4i64.v4bf16(<4 x bfloat> undef) +; CHECK-NEXT: Cost Model: Invalid cost for instruction: %4 = call <8 x i64> @llvm.llrint.v8i64.v8bf16(<8 x bfloat> undef) +; CHECK-NEXT: Cost Model: Invalid cost for instruction: %5 = call <16 x i64> @llvm.llrint.v16i64.v16bf16(<16 x bfloat> undef) +; CHECK-NEXT: Cost Model: Invalid cost for instruction: %6 = call @llvm.llrint.nxv1i64.nxv1bf16( undef) +; CHECK-NEXT: Cost Model: Invalid cost for instruction: %7 = call @llvm.llrint.nxv2i64.nxv2bf16( undef) +; CHECK-NEXT: Cost Model: Invalid cost for instruction: %8 = call @llvm.llrint.nxv4i64.nxv4bf16( undef) +; CHECK-NEXT: Cost Model: Invalid cost for instruction: %9 = call @llvm.llrint.nxv8i64.nxv8bf16( undef) +; CHECK-NEXT: Cost Model: Invalid cost for instruction: %10 = call @llvm.llrint.nxv16i64.nxv16bf16( undef) ; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %11 = call i64 @llvm.llrint.i64.f32(float undef) ; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %12 = call <2 x i64> @llvm.llrint.v2i64.v2f32(<2 x float> undef) ; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %13 = call <4 x i64> @llvm.llrint.v4i64.v4f32(<4 x float> undef) @@ -582,15 +582,15 @@ define void @llrint() { define void @llrint_fp16() { ; CHECK-LABEL: 'llrint_fp16' ; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %1 = call i64 @llvm.llrint.i64.f16(half undef) -; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %2 = call <2 x i64> @llvm.llrint.v2i64.v2f16(<2 x half> undef) -; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %3 = call <4 x i64> @llvm.llrint.v4i64.v4f16(<4 x half> undef) -; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %4 = call <8 x i64> @llvm.llrint.v8i64.v8f16(<8 x half> undef) -; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %5 = call <16 x i64> @llvm.llrint.v16i64.v16f16(<16 x half> undef) -; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %6 = call @llvm.llrint.nxv1i64.nxv1f16( undef) -; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %7 = call @llvm.llrint.nxv2i64.nxv2f16( undef) -; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %8 = call @llvm.llrint.nxv4i64.nxv4f16( undef) -; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %9 = call @llvm.llrint.nxv8i64.nxv8f16( undef) -; CHECK-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %10 = call @llvm.llrint.nxv16i64.nxv16f16( undef) +; CHECK-NEXT: Cost Model: Invalid cost for instruction: %2 = call <2 x i64> @llvm.llrint.v2i64.v2f16(<2 x half> undef) +; CHECK-NEXT: Cost Model: Invalid cost for instruction: %3 = call <4 x i64> @llvm.llrint.v4i64.v4f16(<4 x half> undef) +; CHECK-NEXT: Cost Model: Invalid cost for instruction: %4 = call <8 x i64> @llvm.llrint.v8i64.v8f16(<8 x half> undef) +; CHECK-NEXT: Cost Model: Invalid cost for instruction: %5 = call <16 x i64> @llvm.llrint.v16i64.v16f16(<16 x half> undef) +; CHECK-NEXT: Cost Model: Invalid cost for instruction: %6 = call @llvm.llrint.nxv1i64.nxv1f16( undef) +; CHECK-NEXT: Cost Model: Invalid cost for instruction: %7 = call @llvm.llrint.nxv2i64.nxv2f16( undef) +; CHECK-NEXT: Cost Model: Invalid cost for instruction: %8 = call @llvm.llrint.nxv4i64.nxv4f16( undef) +; CHECK-NEXT: Cost Model: Invalid cost for instruction: %9 = call @llvm.llrint.nxv8i64.nxv8f16( undef) +; CHECK-NEXT: Cost Model: Invalid cost for instruction: %10 = call @llvm.llrint.nxv16i64.nxv16f16( undef) ; CHECK-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret void ; call i64 @llvm.llrint.f16(half undef) diff --git a/llvm/test/Analysis/CostModel/RISCV/reduce-fadd.ll b/llvm/test/Analysis/CostModel/RISCV/reduce-fadd.ll index 588d852d7f26e2..196e7376677a54 100644 --- a/llvm/test/Analysis/CostModel/RISCV/reduce-fadd.ll +++ b/llvm/test/Analysis/CostModel/RISCV/reduce-fadd.ll @@ -13,6 +13,12 @@ define void @reduce_fadd_bfloat() { ; FP-REDUCE-NEXT: Cost Model: Invalid cost for instruction: %v32 = call fast bfloat @llvm.vector.reduce.fadd.v32bf16(bfloat 0xR0000, <32 x bfloat> undef) ; FP-REDUCE-NEXT: Cost Model: Invalid cost for instruction: %V64 = call fast bfloat @llvm.vector.reduce.fadd.v64bf16(bfloat 0xR0000, <64 x bfloat> undef) ; FP-REDUCE-NEXT: Cost Model: Invalid cost for instruction: %V128 = call fast bfloat @llvm.vector.reduce.fadd.v128bf16(bfloat 0xR0000, <128 x bfloat> undef) +; FP-REDUCE-NEXT: Cost Model: Invalid cost for instruction: %NXV1 = call fast bfloat @llvm.vector.reduce.fadd.nxv1bf16(bfloat 0xR0000, undef) +; FP-REDUCE-NEXT: Cost Model: Invalid cost for instruction: %NXV2 = call fast bfloat @llvm.vector.reduce.fadd.nxv2bf16(bfloat 0xR0000, undef) +; FP-REDUCE-NEXT: Cost Model: Invalid cost for instruction: %NXV4 = call fast bfloat @llvm.vector.reduce.fadd.nxv4bf16(bfloat 0xR0000, undef) +; FP-REDUCE-NEXT: Cost Model: Invalid cost for instruction: %NXV8 = call fast bfloat @llvm.vector.reduce.fadd.nxv8bf16(bfloat 0xR0000, undef) +; FP-REDUCE-NEXT: Cost Model: Invalid cost for instruction: %NXV16 = call fast bfloat @llvm.vector.reduce.fadd.nxv16bf16(bfloat 0xR0000, undef) +; FP-REDUCE-NEXT: Cost Model: Invalid cost for instruction: %NXV32 = call fast bfloat @llvm.vector.reduce.fadd.nxv32bf16(bfloat 0xR0000, undef) ; FP-REDUCE-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret void ; ; SIZE-LABEL: 'reduce_fadd_bfloat' @@ -24,6 +30,12 @@ define void @reduce_fadd_bfloat() { ; SIZE-NEXT: Cost Model: Invalid cost for instruction: %v32 = call fast bfloat @llvm.vector.reduce.fadd.v32bf16(bfloat 0xR0000, <32 x bfloat> undef) ; SIZE-NEXT: Cost Model: Invalid cost for instruction: %V64 = call fast bfloat @llvm.vector.reduce.fadd.v64bf16(bfloat 0xR0000, <64 x bfloat> undef) ; SIZE-NEXT: Cost Model: Invalid cost for instruction: %V128 = call fast bfloat @llvm.vector.reduce.fadd.v128bf16(bfloat 0xR0000, <128 x bfloat> undef) +; SIZE-NEXT: Cost Model: Invalid cost for instruction: %NXV1 = call fast bfloat @llvm.vector.reduce.fadd.nxv1bf16(bfloat 0xR0000, undef) +; SIZE-NEXT: Cost Model: Invalid cost for instruction: %NXV2 = call fast bfloat @llvm.vector.reduce.fadd.nxv2bf16(bfloat 0xR0000, undef) +; SIZE-NEXT: Cost Model: Invalid cost for instruction: %NXV4 = call fast bfloat @llvm.vector.reduce.fadd.nxv4bf16(bfloat 0xR0000, undef) +; SIZE-NEXT: Cost Model: Invalid cost for instruction: %NXV8 = call fast bfloat @llvm.vector.reduce.fadd.nxv8bf16(bfloat 0xR0000, undef) +; SIZE-NEXT: Cost Model: Invalid cost for instruction: %NXV16 = call fast bfloat @llvm.vector.reduce.fadd.nxv16bf16(bfloat 0xR0000, undef) +; SIZE-NEXT: Cost Model: Invalid cost for instruction: %NXV32 = call fast bfloat @llvm.vector.reduce.fadd.nxv32bf16(bfloat 0xR0000, undef) ; SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret void ; %V1 = call fast bfloat @llvm.vector.reduce.fadd.v1bf16(bfloat 0.0, <1 x bfloat> undef) @@ -34,6 +46,12 @@ define void @reduce_fadd_bfloat() { %v32 = call fast bfloat @llvm.vector.reduce.fadd.v32bf16(bfloat 0.0, <32 x bfloat> undef) %V64 = call fast bfloat @llvm.vector.reduce.fadd.v64bf16(bfloat 0.0, <64 x bfloat> undef) %V128 = call fast bfloat @llvm.vector.reduce.fadd.v128bf16(bfloat 0.0, <128 x bfloat> undef) + %NXV1 = call fast bfloat @llvm.vector.reduce.fadd.nxv1bf16(bfloat 0.0, undef) + %NXV2 = call fast bfloat @llvm.vector.reduce.fadd.nxv2bf16(bfloat 0.0, undef) + %NXV4 = call fast bfloat @llvm.vector.reduce.fadd.nxv4bf16(bfloat 0.0, undef) + %NXV8 = call fast bfloat @llvm.vector.reduce.fadd.nxv8bf16(bfloat 0.0, undef) + %NXV16 = call fast bfloat @llvm.vector.reduce.fadd.nxv16bf16(bfloat 0.0, undef) + %NXV32 = call fast bfloat @llvm.vector.reduce.fadd.nxv32bf16(bfloat 0.0, undef) ret void } @@ -47,6 +65,12 @@ define void @reduce_fadd_half() { ; FP-REDUCE-ZVFH-NEXT: Cost Model: Found an estimated cost of 7 for instruction: %v32 = call fast half @llvm.vector.reduce.fadd.v32f16(half 0xH0000, <32 x half> undef) ; FP-REDUCE-ZVFH-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %V64 = call fast half @llvm.vector.reduce.fadd.v64f16(half 0xH0000, <64 x half> undef) ; FP-REDUCE-ZVFH-NEXT: Cost Model: Found an estimated cost of 16 for instruction: %V128 = call fast half @llvm.vector.reduce.fadd.v128f16(half 0xH0000, <128 x half> undef) +; FP-REDUCE-ZVFH-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %NXV1 = call fast half @llvm.vector.reduce.fadd.nxv1f16(half 0xH0000, undef) +; FP-REDUCE-ZVFH-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %NXV2 = call fast half @llvm.vector.reduce.fadd.nxv2f16(half 0xH0000, undef) +; FP-REDUCE-ZVFH-NEXT: Cost Model: Found an estimated cost of 5 for instruction: %NXV4 = call fast half @llvm.vector.reduce.fadd.nxv4f16(half 0xH0000, undef) +; FP-REDUCE-ZVFH-NEXT: Cost Model: Found an estimated cost of 6 for instruction: %NXV8 = call fast half @llvm.vector.reduce.fadd.nxv8f16(half 0xH0000, undef) +; FP-REDUCE-ZVFH-NEXT: Cost Model: Found an estimated cost of 7 for instruction: %NXV16 = call fast half @llvm.vector.reduce.fadd.nxv16f16(half 0xH0000, undef) +; FP-REDUCE-ZVFH-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %NXV32 = call fast half @llvm.vector.reduce.fadd.nxv32f16(half 0xH0000, undef) ; FP-REDUCE-ZVFH-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret void ; ; FP-REDUCE-ZVFHMIN-LABEL: 'reduce_fadd_half' @@ -58,6 +82,12 @@ define void @reduce_fadd_half() { ; FP-REDUCE-ZVFHMIN-NEXT: Cost Model: Invalid cost for instruction: %v32 = call fast half @llvm.vector.reduce.fadd.v32f16(half 0xH0000, <32 x half> undef) ; FP-REDUCE-ZVFHMIN-NEXT: Cost Model: Invalid cost for instruction: %V64 = call fast half @llvm.vector.reduce.fadd.v64f16(half 0xH0000, <64 x half> undef) ; FP-REDUCE-ZVFHMIN-NEXT: Cost Model: Invalid cost for instruction: %V128 = call fast half @llvm.vector.reduce.fadd.v128f16(half 0xH0000, <128 x half> undef) +; FP-REDUCE-ZVFHMIN-NEXT: Cost Model: Invalid cost for instruction: %NXV1 = call fast half @llvm.vector.reduce.fadd.nxv1f16(half 0xH0000, undef) +; FP-REDUCE-ZVFHMIN-NEXT: Cost Model: Invalid cost for instruction: %NXV2 = call fast half @llvm.vector.reduce.fadd.nxv2f16(half 0xH0000, undef) +; FP-REDUCE-ZVFHMIN-NEXT: Cost Model: Invalid cost for instruction: %NXV4 = call fast half @llvm.vector.reduce.fadd.nxv4f16(half 0xH0000, undef) +; FP-REDUCE-ZVFHMIN-NEXT: Cost Model: Invalid cost for instruction: %NXV8 = call fast half @llvm.vector.reduce.fadd.nxv8f16(half 0xH0000, undef) +; FP-REDUCE-ZVFHMIN-NEXT: Cost Model: Invalid cost for instruction: %NXV16 = call fast half @llvm.vector.reduce.fadd.nxv16f16(half 0xH0000, undef) +; FP-REDUCE-ZVFHMIN-NEXT: Cost Model: Invalid cost for instruction: %NXV32 = call fast half @llvm.vector.reduce.fadd.nxv32f16(half 0xH0000, undef) ; FP-REDUCE-ZVFHMIN-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret void ; ; SIZE-LABEL: 'reduce_fadd_half' @@ -69,6 +99,12 @@ define void @reduce_fadd_half() { ; SIZE-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %v32 = call fast half @llvm.vector.reduce.fadd.v32f16(half 0xH0000, <32 x half> undef) ; SIZE-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %V64 = call fast half @llvm.vector.reduce.fadd.v64f16(half 0xH0000, <64 x half> undef) ; SIZE-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V128 = call fast half @llvm.vector.reduce.fadd.v128f16(half 0xH0000, <128 x half> undef) +; SIZE-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %NXV1 = call fast half @llvm.vector.reduce.fadd.nxv1f16(half 0xH0000, undef) +; SIZE-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %NXV2 = call fast half @llvm.vector.reduce.fadd.nxv2f16(half 0xH0000, undef) +; SIZE-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %NXV4 = call fast half @llvm.vector.reduce.fadd.nxv4f16(half 0xH0000, undef) +; SIZE-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %NXV8 = call fast half @llvm.vector.reduce.fadd.nxv8f16(half 0xH0000, undef) +; SIZE-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %NXV16 = call fast half @llvm.vector.reduce.fadd.nxv16f16(half 0xH0000, undef) +; SIZE-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %NXV32 = call fast half @llvm.vector.reduce.fadd.nxv32f16(half 0xH0000, undef) ; SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret void ; %V1 = call fast half @llvm.vector.reduce.fadd.v1f16(half 0.0, <1 x half> undef) @@ -79,6 +115,12 @@ define void @reduce_fadd_half() { %v32 = call fast half @llvm.vector.reduce.fadd.v32f16(half 0.0, <32 x half> undef) %V64 = call fast half @llvm.vector.reduce.fadd.v64f16(half 0.0, <64 x half> undef) %V128 = call fast half @llvm.vector.reduce.fadd.v128f16(half 0.0, <128 x half> undef) + %NXV1 = call fast half @llvm.vector.reduce.fadd.nxv1f16(half 0.0, undef) + %NXV2 = call fast half @llvm.vector.reduce.fadd.nxv2f16(half 0.0, undef) + %NXV4 = call fast half @llvm.vector.reduce.fadd.nxv4f16(half 0.0, undef) + %NXV8 = call fast half @llvm.vector.reduce.fadd.nxv8f16(half 0.0, undef) + %NXV16 = call fast half @llvm.vector.reduce.fadd.nxv16f16(half 0.0, undef) + %NXV32 = call fast half @llvm.vector.reduce.fadd.nxv32f16(half 0.0, undef) ret void } @@ -92,6 +134,11 @@ define void @reduce_fadd_float() { ; FP-REDUCE-NEXT: Cost Model: Found an estimated cost of 7 for instruction: %v32 = call fast float @llvm.vector.reduce.fadd.v32f32(float 0.000000e+00, <32 x float> undef) ; FP-REDUCE-NEXT: Cost Model: Found an estimated cost of 15 for instruction: %V64 = call fast float @llvm.vector.reduce.fadd.v64f32(float 0.000000e+00, <64 x float> undef) ; FP-REDUCE-NEXT: Cost Model: Found an estimated cost of 31 for instruction: %V128 = call fast float @llvm.vector.reduce.fadd.v128f32(float 0.000000e+00, <128 x float> undef) +; FP-REDUCE-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %NXV1 = call fast float @llvm.vector.reduce.fadd.nxv1f32(float 0.000000e+00, undef) +; FP-REDUCE-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %NXV2 = call fast float @llvm.vector.reduce.fadd.nxv2f32(float 0.000000e+00, undef) +; FP-REDUCE-NEXT: Cost Model: Found an estimated cost of 5 for instruction: %NXV4 = call fast float @llvm.vector.reduce.fadd.nxv4f32(float 0.000000e+00, undef) +; FP-REDUCE-NEXT: Cost Model: Found an estimated cost of 6 for instruction: %NXV8 = call fast float @llvm.vector.reduce.fadd.nxv8f32(float 0.000000e+00, undef) +; FP-REDUCE-NEXT: Cost Model: Found an estimated cost of 7 for instruction: %NXV16 = call fast float @llvm.vector.reduce.fadd.nxv16f32(float 0.000000e+00, undef) ; FP-REDUCE-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret void ; ; SIZE-LABEL: 'reduce_fadd_float' @@ -103,6 +150,11 @@ define void @reduce_fadd_float() { ; SIZE-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %v32 = call fast float @llvm.vector.reduce.fadd.v32f32(float 0.000000e+00, <32 x float> undef) ; SIZE-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V64 = call fast float @llvm.vector.reduce.fadd.v64f32(float 0.000000e+00, <64 x float> undef) ; SIZE-NEXT: Cost Model: Found an estimated cost of 6 for instruction: %V128 = call fast float @llvm.vector.reduce.fadd.v128f32(float 0.000000e+00, <128 x float> undef) +; SIZE-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %NXV1 = call fast float @llvm.vector.reduce.fadd.nxv1f32(float 0.000000e+00, undef) +; SIZE-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %NXV2 = call fast float @llvm.vector.reduce.fadd.nxv2f32(float 0.000000e+00, undef) +; SIZE-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %NXV4 = call fast float @llvm.vector.reduce.fadd.nxv4f32(float 0.000000e+00, undef) +; SIZE-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %NXV8 = call fast float @llvm.vector.reduce.fadd.nxv8f32(float 0.000000e+00, undef) +; SIZE-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %NXV16 = call fast float @llvm.vector.reduce.fadd.nxv16f32(float 0.000000e+00, undef) ; SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret void ; %V1 = call fast float @llvm.vector.reduce.fadd.v1f32(float 0.0, <1 x float> undef) @@ -113,6 +165,11 @@ define void @reduce_fadd_float() { %v32 = call fast float @llvm.vector.reduce.fadd.v32f32(float 0.0, <32 x float> undef) %V64 = call fast float @llvm.vector.reduce.fadd.v64f32(float 0.0, <64 x float> undef) %V128 = call fast float @llvm.vector.reduce.fadd.v128f32(float 0.0, <128 x float> undef) + %NXV1 = call fast float @llvm.vector.reduce.fadd.nxv1f32(float 0.0, undef) + %NXV2 = call fast float @llvm.vector.reduce.fadd.nxv2f32(float 0.0, undef) + %NXV4 = call fast float @llvm.vector.reduce.fadd.nxv4f32(float 0.0, undef) + %NXV8 = call fast float @llvm.vector.reduce.fadd.nxv8f32(float 0.0, undef) + %NXV16 = call fast float @llvm.vector.reduce.fadd.nxv16f32(float 0.0, undef) ret void } @@ -126,6 +183,10 @@ define void @reduce_fadd_double() { ; FP-REDUCE-NEXT: Cost Model: Found an estimated cost of 14 for instruction: %v32 = call fast double @llvm.vector.reduce.fadd.v32f64(double 0.000000e+00, <32 x double> undef) ; FP-REDUCE-NEXT: Cost Model: Found an estimated cost of 30 for instruction: %V64 = call fast double @llvm.vector.reduce.fadd.v64f64(double 0.000000e+00, <64 x double> undef) ; FP-REDUCE-NEXT: Cost Model: Found an estimated cost of 62 for instruction: %V128 = call fast double @llvm.vector.reduce.fadd.v128f64(double 0.000000e+00, <128 x double> undef) +; FP-REDUCE-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %NXV1 = call fast double @llvm.vector.reduce.fadd.nxv1f64(double 0.000000e+00, undef) +; FP-REDUCE-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %NXV2 = call fast double @llvm.vector.reduce.fadd.nxv2f64(double 0.000000e+00, undef) +; FP-REDUCE-NEXT: Cost Model: Found an estimated cost of 5 for instruction: %NXV4 = call fast double @llvm.vector.reduce.fadd.nxv4f64(double 0.000000e+00, undef) +; FP-REDUCE-NEXT: Cost Model: Found an estimated cost of 6 for instruction: %NXV8 = call fast double @llvm.vector.reduce.fadd.nxv8f64(double 0.000000e+00, undef) ; FP-REDUCE-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret void ; ; SIZE-LABEL: 'reduce_fadd_double' @@ -137,6 +198,10 @@ define void @reduce_fadd_double() { ; SIZE-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %v32 = call fast double @llvm.vector.reduce.fadd.v32f64(double 0.000000e+00, <32 x double> undef) ; SIZE-NEXT: Cost Model: Found an estimated cost of 6 for instruction: %V64 = call fast double @llvm.vector.reduce.fadd.v64f64(double 0.000000e+00, <64 x double> undef) ; SIZE-NEXT: Cost Model: Found an estimated cost of 10 for instruction: %V128 = call fast double @llvm.vector.reduce.fadd.v128f64(double 0.000000e+00, <128 x double> undef) +; SIZE-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %NXV1 = call fast double @llvm.vector.reduce.fadd.nxv1f64(double 0.000000e+00, undef) +; SIZE-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %NXV2 = call fast double @llvm.vector.reduce.fadd.nxv2f64(double 0.000000e+00, undef) +; SIZE-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %NXV4 = call fast double @llvm.vector.reduce.fadd.nxv4f64(double 0.000000e+00, undef) +; SIZE-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %NXV8 = call fast double @llvm.vector.reduce.fadd.nxv8f64(double 0.000000e+00, undef) ; SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret void ; %V1 = call fast double @llvm.vector.reduce.fadd.v1f64(double 0.0, <1 x double> undef) @@ -147,11 +212,15 @@ define void @reduce_fadd_double() { %v32 = call fast double @llvm.vector.reduce.fadd.v32f64(double 0.0, <32 x double> undef) %V64 = call fast double @llvm.vector.reduce.fadd.v64f64(double 0.0, <64 x double> undef) %V128 = call fast double @llvm.vector.reduce.fadd.v128f64(double 0.0, <128 x double> undef) + %NXV1 = call fast double @llvm.vector.reduce.fadd.nxv1f64(double 0.0, undef) + %NXV2 = call fast double @llvm.vector.reduce.fadd.nxv2f64(double 0.0, undef) + %NXV4 = call fast double @llvm.vector.reduce.fadd.nxv4f64(double 0.0, undef) + %NXV8 = call fast double @llvm.vector.reduce.fadd.nxv8f64(double 0.0, undef) ret void } -define void @reduce_oredered_fadd_bfloat() { -; FP-REDUCE-LABEL: 'reduce_oredered_fadd_bfloat' +define void @reduce_ordered_fadd_bfloat() { +; FP-REDUCE-LABEL: 'reduce_ordered_fadd_bfloat' ; FP-REDUCE-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %V1 = call bfloat @llvm.vector.reduce.fadd.v1bf16(bfloat 0xR0000, <1 x bfloat> undef) ; FP-REDUCE-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V2 = call bfloat @llvm.vector.reduce.fadd.v2bf16(bfloat 0xR0000, <2 x bfloat> undef) ; FP-REDUCE-NEXT: Cost Model: Found an estimated cost of 6 for instruction: %V4 = call bfloat @llvm.vector.reduce.fadd.v4bf16(bfloat 0xR0000, <4 x bfloat> undef) @@ -160,9 +229,15 @@ define void @reduce_oredered_fadd_bfloat() { ; FP-REDUCE-NEXT: Cost Model: Found an estimated cost of 34 for instruction: %v32 = call bfloat @llvm.vector.reduce.fadd.v32bf16(bfloat 0xR0000, <32 x bfloat> undef) ; FP-REDUCE-NEXT: Cost Model: Found an estimated cost of 66 for instruction: %V64 = call bfloat @llvm.vector.reduce.fadd.v64bf16(bfloat 0xR0000, <64 x bfloat> undef) ; FP-REDUCE-NEXT: Cost Model: Found an estimated cost of 130 for instruction: %V128 = call bfloat @llvm.vector.reduce.fadd.v128bf16(bfloat 0xR0000, <128 x bfloat> undef) +; FP-REDUCE-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %NXV1 = call bfloat @llvm.vector.reduce.fadd.nxv1bf16(bfloat 0xR0000, undef) +; FP-REDUCE-NEXT: Cost Model: Found an estimated cost of 6 for instruction: %NXV2 = call bfloat @llvm.vector.reduce.fadd.nxv2bf16(bfloat 0xR0000, undef) +; FP-REDUCE-NEXT: Cost Model: Found an estimated cost of 10 for instruction: %NXV4 = call bfloat @llvm.vector.reduce.fadd.nxv4bf16(bfloat 0xR0000, undef) +; FP-REDUCE-NEXT: Cost Model: Found an estimated cost of 18 for instruction: %NXV8 = call bfloat @llvm.vector.reduce.fadd.nxv8bf16(bfloat 0xR0000, undef) +; FP-REDUCE-NEXT: Cost Model: Found an estimated cost of 34 for instruction: %NXV16 = call bfloat @llvm.vector.reduce.fadd.nxv16bf16(bfloat 0xR0000, undef) +; FP-REDUCE-NEXT: Cost Model: Found an estimated cost of 66 for instruction: %NXV32 = call bfloat @llvm.vector.reduce.fadd.nxv32bf16(bfloat 0xR0000, undef) ; FP-REDUCE-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret void ; -; SIZE-LABEL: 'reduce_oredered_fadd_bfloat' +; SIZE-LABEL: 'reduce_ordered_fadd_bfloat' ; SIZE-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %V1 = call bfloat @llvm.vector.reduce.fadd.v1bf16(bfloat 0xR0000, <1 x bfloat> undef) ; SIZE-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %V2 = call bfloat @llvm.vector.reduce.fadd.v2bf16(bfloat 0xR0000, <2 x bfloat> undef) ; SIZE-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %V4 = call bfloat @llvm.vector.reduce.fadd.v4bf16(bfloat 0xR0000, <4 x bfloat> undef) @@ -171,6 +246,12 @@ define void @reduce_oredered_fadd_bfloat() { ; SIZE-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %v32 = call bfloat @llvm.vector.reduce.fadd.v32bf16(bfloat 0xR0000, <32 x bfloat> undef) ; SIZE-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %V64 = call bfloat @llvm.vector.reduce.fadd.v64bf16(bfloat 0xR0000, <64 x bfloat> undef) ; SIZE-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V128 = call bfloat @llvm.vector.reduce.fadd.v128bf16(bfloat 0xR0000, <128 x bfloat> undef) +; SIZE-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %NXV1 = call bfloat @llvm.vector.reduce.fadd.nxv1bf16(bfloat 0xR0000, undef) +; SIZE-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %NXV2 = call bfloat @llvm.vector.reduce.fadd.nxv2bf16(bfloat 0xR0000, undef) +; SIZE-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %NXV4 = call bfloat @llvm.vector.reduce.fadd.nxv4bf16(bfloat 0xR0000, undef) +; SIZE-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %NXV8 = call bfloat @llvm.vector.reduce.fadd.nxv8bf16(bfloat 0xR0000, undef) +; SIZE-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %NXV16 = call bfloat @llvm.vector.reduce.fadd.nxv16bf16(bfloat 0xR0000, undef) +; SIZE-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %NXV32 = call bfloat @llvm.vector.reduce.fadd.nxv32bf16(bfloat 0xR0000, undef) ; SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret void ; %V1 = call bfloat @llvm.vector.reduce.fadd.v1bf16(bfloat 0.0, <1 x bfloat> undef) @@ -181,11 +262,17 @@ define void @reduce_oredered_fadd_bfloat() { %v32 = call bfloat @llvm.vector.reduce.fadd.v32bf16(bfloat 0.0, <32 x bfloat> undef) %V64 = call bfloat @llvm.vector.reduce.fadd.v64bf16(bfloat 0.0, <64 x bfloat> undef) %V128 = call bfloat @llvm.vector.reduce.fadd.v128bf16(bfloat 0.0, <128 x bfloat> undef) + %NXV1 = call bfloat @llvm.vector.reduce.fadd.nxv1bf16(bfloat 0.0, undef) + %NXV2 = call bfloat @llvm.vector.reduce.fadd.nxv2bf16(bfloat 0.0, undef) + %NXV4 = call bfloat @llvm.vector.reduce.fadd.nxv4bf16(bfloat 0.0, undef) + %NXV8 = call bfloat @llvm.vector.reduce.fadd.nxv8bf16(bfloat 0.0, undef) + %NXV16 = call bfloat @llvm.vector.reduce.fadd.nxv16bf16(bfloat 0.0, undef) + %NXV32 = call bfloat @llvm.vector.reduce.fadd.nxv32bf16(bfloat 0.0, undef) ret void } -define void @reduce_oredered_fadd_half() { -; FP-REDUCE-LABEL: 'reduce_oredered_fadd_half' +define void @reduce_ordered_fadd_half() { +; FP-REDUCE-LABEL: 'reduce_ordered_fadd_half' ; FP-REDUCE-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %V1 = call half @llvm.vector.reduce.fadd.v1f16(half 0xH0000, <1 x half> undef) ; FP-REDUCE-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V2 = call half @llvm.vector.reduce.fadd.v2f16(half 0xH0000, <2 x half> undef) ; FP-REDUCE-NEXT: Cost Model: Found an estimated cost of 6 for instruction: %V4 = call half @llvm.vector.reduce.fadd.v4f16(half 0xH0000, <4 x half> undef) @@ -194,9 +281,15 @@ define void @reduce_oredered_fadd_half() { ; FP-REDUCE-NEXT: Cost Model: Found an estimated cost of 34 for instruction: %v32 = call half @llvm.vector.reduce.fadd.v32f16(half 0xH0000, <32 x half> undef) ; FP-REDUCE-NEXT: Cost Model: Found an estimated cost of 66 for instruction: %V64 = call half @llvm.vector.reduce.fadd.v64f16(half 0xH0000, <64 x half> undef) ; FP-REDUCE-NEXT: Cost Model: Found an estimated cost of 130 for instruction: %V128 = call half @llvm.vector.reduce.fadd.v128f16(half 0xH0000, <128 x half> undef) +; FP-REDUCE-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %NXV1 = call half @llvm.vector.reduce.fadd.nxv1f16(half 0xH0000, undef) +; FP-REDUCE-NEXT: Cost Model: Found an estimated cost of 6 for instruction: %NXV2 = call half @llvm.vector.reduce.fadd.nxv2f16(half 0xH0000, undef) +; FP-REDUCE-NEXT: Cost Model: Found an estimated cost of 10 for instruction: %NXV4 = call half @llvm.vector.reduce.fadd.nxv4f16(half 0xH0000, undef) +; FP-REDUCE-NEXT: Cost Model: Found an estimated cost of 18 for instruction: %NXV8 = call half @llvm.vector.reduce.fadd.nxv8f16(half 0xH0000, undef) +; FP-REDUCE-NEXT: Cost Model: Found an estimated cost of 34 for instruction: %NXV16 = call half @llvm.vector.reduce.fadd.nxv16f16(half 0xH0000, undef) +; FP-REDUCE-NEXT: Cost Model: Found an estimated cost of 66 for instruction: %NXV32 = call half @llvm.vector.reduce.fadd.nxv32f16(half 0xH0000, undef) ; FP-REDUCE-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret void ; -; SIZE-LABEL: 'reduce_oredered_fadd_half' +; SIZE-LABEL: 'reduce_ordered_fadd_half' ; SIZE-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %V1 = call half @llvm.vector.reduce.fadd.v1f16(half 0xH0000, <1 x half> undef) ; SIZE-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %V2 = call half @llvm.vector.reduce.fadd.v2f16(half 0xH0000, <2 x half> undef) ; SIZE-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %V4 = call half @llvm.vector.reduce.fadd.v4f16(half 0xH0000, <4 x half> undef) @@ -205,6 +298,12 @@ define void @reduce_oredered_fadd_half() { ; SIZE-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %v32 = call half @llvm.vector.reduce.fadd.v32f16(half 0xH0000, <32 x half> undef) ; SIZE-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %V64 = call half @llvm.vector.reduce.fadd.v64f16(half 0xH0000, <64 x half> undef) ; SIZE-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V128 = call half @llvm.vector.reduce.fadd.v128f16(half 0xH0000, <128 x half> undef) +; SIZE-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %NXV1 = call half @llvm.vector.reduce.fadd.nxv1f16(half 0xH0000, undef) +; SIZE-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %NXV2 = call half @llvm.vector.reduce.fadd.nxv2f16(half 0xH0000, undef) +; SIZE-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %NXV4 = call half @llvm.vector.reduce.fadd.nxv4f16(half 0xH0000, undef) +; SIZE-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %NXV8 = call half @llvm.vector.reduce.fadd.nxv8f16(half 0xH0000, undef) +; SIZE-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %NXV16 = call half @llvm.vector.reduce.fadd.nxv16f16(half 0xH0000, undef) +; SIZE-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %NXV32 = call half @llvm.vector.reduce.fadd.nxv32f16(half 0xH0000, undef) ; SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret void ; %V1 = call half @llvm.vector.reduce.fadd.v1f16(half 0.0, <1 x half> undef) @@ -215,11 +314,17 @@ define void @reduce_oredered_fadd_half() { %v32 = call half @llvm.vector.reduce.fadd.v32f16(half 0.0, <32 x half> undef) %V64 = call half @llvm.vector.reduce.fadd.v64f16(half 0.0, <64 x half> undef) %V128 = call half @llvm.vector.reduce.fadd.v128f16(half 0.0, <128 x half> undef) + %NXV1 = call half @llvm.vector.reduce.fadd.nxv1f16(half 0.0, undef) + %NXV2 = call half @llvm.vector.reduce.fadd.nxv2f16(half 0.0, undef) + %NXV4 = call half @llvm.vector.reduce.fadd.nxv4f16(half 0.0, undef) + %NXV8 = call half @llvm.vector.reduce.fadd.nxv8f16(half 0.0, undef) + %NXV16 = call half @llvm.vector.reduce.fadd.nxv16f16(half 0.0, undef) + %NXV32 = call half @llvm.vector.reduce.fadd.nxv32f16(half 0.0, undef) ret void } -define void @reduce_oredered_fadd_float() { -; FP-REDUCE-LABEL: 'reduce_oredered_fadd_float' +define void @reduce_ordered_fadd_float() { +; FP-REDUCE-LABEL: 'reduce_ordered_fadd_float' ; FP-REDUCE-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %V1 = call float @llvm.vector.reduce.fadd.v1f32(float 0.000000e+00, <1 x float> undef) ; FP-REDUCE-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V2 = call float @llvm.vector.reduce.fadd.v2f32(float 0.000000e+00, <2 x float> undef) ; FP-REDUCE-NEXT: Cost Model: Found an estimated cost of 6 for instruction: %V4 = call float @llvm.vector.reduce.fadd.v4f32(float 0.000000e+00, <4 x float> undef) @@ -228,9 +333,14 @@ define void @reduce_oredered_fadd_float() { ; FP-REDUCE-NEXT: Cost Model: Found an estimated cost of 34 for instruction: %v32 = call float @llvm.vector.reduce.fadd.v32f32(float 0.000000e+00, <32 x float> undef) ; FP-REDUCE-NEXT: Cost Model: Found an estimated cost of 66 for instruction: %V64 = call float @llvm.vector.reduce.fadd.v64f32(float 0.000000e+00, <64 x float> undef) ; FP-REDUCE-NEXT: Cost Model: Found an estimated cost of 130 for instruction: %V128 = call float @llvm.vector.reduce.fadd.v128f32(float 0.000000e+00, <128 x float> undef) +; FP-REDUCE-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %NXV1 = call float @llvm.vector.reduce.fadd.nxv1f32(float 0.000000e+00, undef) +; FP-REDUCE-NEXT: Cost Model: Found an estimated cost of 6 for instruction: %NXV2 = call float @llvm.vector.reduce.fadd.nxv2f32(float 0.000000e+00, undef) +; FP-REDUCE-NEXT: Cost Model: Found an estimated cost of 10 for instruction: %NXV4 = call float @llvm.vector.reduce.fadd.nxv4f32(float 0.000000e+00, undef) +; FP-REDUCE-NEXT: Cost Model: Found an estimated cost of 18 for instruction: %NXV8 = call float @llvm.vector.reduce.fadd.nxv8f32(float 0.000000e+00, undef) +; FP-REDUCE-NEXT: Cost Model: Found an estimated cost of 34 for instruction: %NXV16 = call float @llvm.vector.reduce.fadd.nxv16f32(float 0.000000e+00, undef) ; FP-REDUCE-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret void ; -; SIZE-LABEL: 'reduce_oredered_fadd_float' +; SIZE-LABEL: 'reduce_ordered_fadd_float' ; SIZE-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %V1 = call float @llvm.vector.reduce.fadd.v1f32(float 0.000000e+00, <1 x float> undef) ; SIZE-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %V2 = call float @llvm.vector.reduce.fadd.v2f32(float 0.000000e+00, <2 x float> undef) ; SIZE-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %V4 = call float @llvm.vector.reduce.fadd.v4f32(float 0.000000e+00, <4 x float> undef) @@ -239,6 +349,11 @@ define void @reduce_oredered_fadd_float() { ; SIZE-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %v32 = call float @llvm.vector.reduce.fadd.v32f32(float 0.000000e+00, <32 x float> undef) ; SIZE-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V64 = call float @llvm.vector.reduce.fadd.v64f32(float 0.000000e+00, <64 x float> undef) ; SIZE-NEXT: Cost Model: Found an estimated cost of 6 for instruction: %V128 = call float @llvm.vector.reduce.fadd.v128f32(float 0.000000e+00, <128 x float> undef) +; SIZE-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %NXV1 = call float @llvm.vector.reduce.fadd.nxv1f32(float 0.000000e+00, undef) +; SIZE-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %NXV2 = call float @llvm.vector.reduce.fadd.nxv2f32(float 0.000000e+00, undef) +; SIZE-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %NXV4 = call float @llvm.vector.reduce.fadd.nxv4f32(float 0.000000e+00, undef) +; SIZE-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %NXV8 = call float @llvm.vector.reduce.fadd.nxv8f32(float 0.000000e+00, undef) +; SIZE-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %NXV16 = call float @llvm.vector.reduce.fadd.nxv16f32(float 0.000000e+00, undef) ; SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret void ; %V1 = call float @llvm.vector.reduce.fadd.v1f32(float 0.0, <1 x float> undef) @@ -249,11 +364,16 @@ define void @reduce_oredered_fadd_float() { %v32 = call float @llvm.vector.reduce.fadd.v32f32(float 0.0, <32 x float> undef) %V64 = call float @llvm.vector.reduce.fadd.v64f32(float 0.0, <64 x float> undef) %V128 = call float @llvm.vector.reduce.fadd.v128f32(float 0.0, <128 x float> undef) + %NXV1 = call float @llvm.vector.reduce.fadd.nxv1f32(float 0.0, undef) + %NXV2 = call float @llvm.vector.reduce.fadd.nxv2f32(float 0.0, undef) + %NXV4 = call float @llvm.vector.reduce.fadd.nxv4f32(float 0.0, undef) + %NXV8 = call float @llvm.vector.reduce.fadd.nxv8f32(float 0.0, undef) + %NXV16 = call float @llvm.vector.reduce.fadd.nxv16f32(float 0.0, undef) ret void } -define void @reduce_oredered_fadd_double() { -; FP-REDUCE-LABEL: 'reduce_oredered_fadd_double' +define void @reduce_ordered_fadd_double() { +; FP-REDUCE-LABEL: 'reduce_ordered_fadd_double' ; FP-REDUCE-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %V1 = call double @llvm.vector.reduce.fadd.v1f64(double 0.000000e+00, <1 x double> undef) ; FP-REDUCE-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V2 = call double @llvm.vector.reduce.fadd.v2f64(double 0.000000e+00, <2 x double> undef) ; FP-REDUCE-NEXT: Cost Model: Found an estimated cost of 6 for instruction: %V4 = call double @llvm.vector.reduce.fadd.v4f64(double 0.000000e+00, <4 x double> undef) @@ -262,9 +382,13 @@ define void @reduce_oredered_fadd_double() { ; FP-REDUCE-NEXT: Cost Model: Found an estimated cost of 34 for instruction: %v32 = call double @llvm.vector.reduce.fadd.v32f64(double 0.000000e+00, <32 x double> undef) ; FP-REDUCE-NEXT: Cost Model: Found an estimated cost of 66 for instruction: %V64 = call double @llvm.vector.reduce.fadd.v64f64(double 0.000000e+00, <64 x double> undef) ; FP-REDUCE-NEXT: Cost Model: Found an estimated cost of 130 for instruction: %V128 = call double @llvm.vector.reduce.fadd.v128f64(double 0.000000e+00, <128 x double> undef) +; FP-REDUCE-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %NXV1 = call double @llvm.vector.reduce.fadd.nxv1f64(double 0.000000e+00, undef) +; FP-REDUCE-NEXT: Cost Model: Found an estimated cost of 6 for instruction: %NXV2 = call double @llvm.vector.reduce.fadd.nxv2f64(double 0.000000e+00, undef) +; FP-REDUCE-NEXT: Cost Model: Found an estimated cost of 10 for instruction: %NXV4 = call double @llvm.vector.reduce.fadd.nxv4f64(double 0.000000e+00, undef) +; FP-REDUCE-NEXT: Cost Model: Found an estimated cost of 18 for instruction: %NXV8 = call double @llvm.vector.reduce.fadd.nxv8f64(double 0.000000e+00, undef) ; FP-REDUCE-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret void ; -; SIZE-LABEL: 'reduce_oredered_fadd_double' +; SIZE-LABEL: 'reduce_ordered_fadd_double' ; SIZE-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %V1 = call double @llvm.vector.reduce.fadd.v1f64(double 0.000000e+00, <1 x double> undef) ; SIZE-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %V2 = call double @llvm.vector.reduce.fadd.v2f64(double 0.000000e+00, <2 x double> undef) ; SIZE-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %V4 = call double @llvm.vector.reduce.fadd.v4f64(double 0.000000e+00, <4 x double> undef) @@ -273,6 +397,10 @@ define void @reduce_oredered_fadd_double() { ; SIZE-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %v32 = call double @llvm.vector.reduce.fadd.v32f64(double 0.000000e+00, <32 x double> undef) ; SIZE-NEXT: Cost Model: Found an estimated cost of 6 for instruction: %V64 = call double @llvm.vector.reduce.fadd.v64f64(double 0.000000e+00, <64 x double> undef) ; SIZE-NEXT: Cost Model: Found an estimated cost of 10 for instruction: %V128 = call double @llvm.vector.reduce.fadd.v128f64(double 0.000000e+00, <128 x double> undef) +; SIZE-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %NXV1 = call double @llvm.vector.reduce.fadd.nxv1f64(double 0.000000e+00, undef) +; SIZE-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %NXV2 = call double @llvm.vector.reduce.fadd.nxv2f64(double 0.000000e+00, undef) +; SIZE-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %NXV4 = call double @llvm.vector.reduce.fadd.nxv4f64(double 0.000000e+00, undef) +; SIZE-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %NXV8 = call double @llvm.vector.reduce.fadd.nxv8f64(double 0.000000e+00, undef) ; SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret void ; %V1 = call double @llvm.vector.reduce.fadd.v1f64(double 0.0, <1 x double> undef) @@ -283,30 +411,9 @@ define void @reduce_oredered_fadd_double() { %v32 = call double @llvm.vector.reduce.fadd.v32f64(double 0.0, <32 x double> undef) %V64 = call double @llvm.vector.reduce.fadd.v64f64(double 0.0, <64 x double> undef) %V128 = call double @llvm.vector.reduce.fadd.v128f64(double 0.0, <128 x double> undef) + %NXV1 = call double @llvm.vector.reduce.fadd.nxv1f64(double 0.0, undef) + %NXV2 = call double @llvm.vector.reduce.fadd.nxv2f64(double 0.0, undef) + %NXV4 = call double @llvm.vector.reduce.fadd.nxv4f64(double 0.0, undef) + %NXV8 = call double @llvm.vector.reduce.fadd.nxv8f64(double 0.0, undef) ret void } - -declare half @llvm.vector.reduce.fadd.v1f16(half, <1 x half>) -declare half @llvm.vector.reduce.fadd.v2f16(half, <2 x half>) -declare half @llvm.vector.reduce.fadd.v4f16(half, <4 x half>) -declare half @llvm.vector.reduce.fadd.v8f16(half, <8 x half>) -declare half @llvm.vector.reduce.fadd.v16f16(half, <16 x half>) -declare half @llvm.vector.reduce.fadd.v32f16(half, <32 x half>) -declare half @llvm.vector.reduce.fadd.v64f16(half, <64 x half>) -declare half @llvm.vector.reduce.fadd.v128f16(half, <128 x half>) -declare float @llvm.vector.reduce.fadd.v1f32(float, <1 x float>) -declare float @llvm.vector.reduce.fadd.v2f32(float, <2 x float>) -declare float @llvm.vector.reduce.fadd.v4f32(float, <4 x float>) -declare float @llvm.vector.reduce.fadd.v8f32(float, <8 x float>) -declare float @llvm.vector.reduce.fadd.v16f32(float, <16 x float>) -declare float @llvm.vector.reduce.fadd.v32f32(float, <32 x float>) -declare float @llvm.vector.reduce.fadd.v64f32(float, <64 x float>) -declare float @llvm.vector.reduce.fadd.v128f32(float, <128 x float>) -declare double @llvm.vector.reduce.fadd.v1f64(double, <1 x double>) -declare double @llvm.vector.reduce.fadd.v2f64(double, <2 x double>) -declare double @llvm.vector.reduce.fadd.v4f64(double, <4 x double>) -declare double @llvm.vector.reduce.fadd.v8f64(double, <8 x double>) -declare double @llvm.vector.reduce.fadd.v16f64(double, <16 x double>) -declare double @llvm.vector.reduce.fadd.v32f64(double, <32 x double>) -declare double @llvm.vector.reduce.fadd.v64f64(double, <64 x double>) -declare double @llvm.vector.reduce.fadd.v128f64(double, <128 x double>) diff --git a/llvm/test/Analysis/CostModel/RISCV/reduce-fmul.ll b/llvm/test/Analysis/CostModel/RISCV/reduce-fmul.ll index 162562c7b89310..211bcb1343eea4 100644 --- a/llvm/test/Analysis/CostModel/RISCV/reduce-fmul.ll +++ b/llvm/test/Analysis/CostModel/RISCV/reduce-fmul.ll @@ -13,6 +13,12 @@ define void @reduce_fmul_bfloat() { ; FP-REDUCE-NEXT: Cost Model: Found an estimated cost of 211 for instruction: %v32 = call fast bfloat @llvm.vector.reduce.fmul.v32bf16(bfloat 0xR0000, <32 x bfloat> undef) ; FP-REDUCE-NEXT: Cost Model: Found an estimated cost of 541 for instruction: %V64 = call fast bfloat @llvm.vector.reduce.fmul.v64bf16(bfloat 0xR0000, <64 x bfloat> undef) ; FP-REDUCE-NEXT: Cost Model: Found an estimated cost of 573 for instruction: %V128 = call fast bfloat @llvm.vector.reduce.fmul.v128bf16(bfloat 0xR0000, <128 x bfloat> undef) +; FP-REDUCE-NEXT: Cost Model: Invalid cost for instruction: %NXV1 = call fast bfloat @llvm.vector.reduce.fmul.nxv1bf16(bfloat 0xR0000, undef) +; FP-REDUCE-NEXT: Cost Model: Invalid cost for instruction: %NXV2 = call fast bfloat @llvm.vector.reduce.fmul.nxv2bf16(bfloat 0xR0000, undef) +; FP-REDUCE-NEXT: Cost Model: Invalid cost for instruction: %NXV4 = call fast bfloat @llvm.vector.reduce.fmul.nxv4bf16(bfloat 0xR0000, undef) +; FP-REDUCE-NEXT: Cost Model: Invalid cost for instruction: %NXV8 = call fast bfloat @llvm.vector.reduce.fmul.nxv8bf16(bfloat 0xR0000, undef) +; FP-REDUCE-NEXT: Cost Model: Invalid cost for instruction: %NXV16 = call fast bfloat @llvm.vector.reduce.fmul.nxv16bf16(bfloat 0xR0000, undef) +; FP-REDUCE-NEXT: Cost Model: Invalid cost for instruction: %NXV32 = call fast bfloat @llvm.vector.reduce.fmul.nxv32bf16(bfloat 0xR0000, undef) ; FP-REDUCE-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret void ; ; SIZE-LABEL: 'reduce_fmul_bfloat' @@ -24,6 +30,12 @@ define void @reduce_fmul_bfloat() { ; SIZE-NEXT: Cost Model: Found an estimated cost of 26 for instruction: %v32 = call fast bfloat @llvm.vector.reduce.fmul.v32bf16(bfloat 0xR0000, <32 x bfloat> undef) ; SIZE-NEXT: Cost Model: Found an estimated cost of 31 for instruction: %V64 = call fast bfloat @llvm.vector.reduce.fmul.v64bf16(bfloat 0xR0000, <64 x bfloat> undef) ; SIZE-NEXT: Cost Model: Found an estimated cost of 34 for instruction: %V128 = call fast bfloat @llvm.vector.reduce.fmul.v128bf16(bfloat 0xR0000, <128 x bfloat> undef) +; SIZE-NEXT: Cost Model: Invalid cost for instruction: %NXV1 = call fast bfloat @llvm.vector.reduce.fmul.nxv1bf16(bfloat 0xR0000, undef) +; SIZE-NEXT: Cost Model: Invalid cost for instruction: %NXV2 = call fast bfloat @llvm.vector.reduce.fmul.nxv2bf16(bfloat 0xR0000, undef) +; SIZE-NEXT: Cost Model: Invalid cost for instruction: %NXV4 = call fast bfloat @llvm.vector.reduce.fmul.nxv4bf16(bfloat 0xR0000, undef) +; SIZE-NEXT: Cost Model: Invalid cost for instruction: %NXV8 = call fast bfloat @llvm.vector.reduce.fmul.nxv8bf16(bfloat 0xR0000, undef) +; SIZE-NEXT: Cost Model: Invalid cost for instruction: %NXV16 = call fast bfloat @llvm.vector.reduce.fmul.nxv16bf16(bfloat 0xR0000, undef) +; SIZE-NEXT: Cost Model: Invalid cost for instruction: %NXV32 = call fast bfloat @llvm.vector.reduce.fmul.nxv32bf16(bfloat 0xR0000, undef) ; SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret void ; %V1 = call fast bfloat @llvm.vector.reduce.fmul.v1bf16(bfloat 0.0, <1 x bfloat> undef) @@ -34,6 +46,12 @@ define void @reduce_fmul_bfloat() { %v32 = call fast bfloat @llvm.vector.reduce.fmul.v32bf16(bfloat 0.0, <32 x bfloat> undef) %V64 = call fast bfloat @llvm.vector.reduce.fmul.v64bf16(bfloat 0.0, <64 x bfloat> undef) %V128 = call fast bfloat @llvm.vector.reduce.fmul.v128bf16(bfloat 0.0, <128 x bfloat> undef) + %NXV1 = call fast bfloat @llvm.vector.reduce.fmul.nxv1bf16(bfloat 0.0, undef) + %NXV2 = call fast bfloat @llvm.vector.reduce.fmul.nxv2bf16(bfloat 0.0, undef) + %NXV4 = call fast bfloat @llvm.vector.reduce.fmul.nxv4bf16(bfloat 0.0, undef) + %NXV8 = call fast bfloat @llvm.vector.reduce.fmul.nxv8bf16(bfloat 0.0, undef) + %NXV16 = call fast bfloat @llvm.vector.reduce.fmul.nxv16bf16(bfloat 0.0, undef) + %NXV32 = call fast bfloat @llvm.vector.reduce.fmul.nxv32bf16(bfloat 0.0, undef) ret void } @@ -47,6 +65,12 @@ define void @reduce_fmul_half() { ; FP-REDUCE-ZVFH-NEXT: Cost Model: Found an estimated cost of 151 for instruction: %v32 = call fast half @llvm.vector.reduce.fmul.v32f16(half 0xH0000, <32 x half> undef) ; FP-REDUCE-ZVFH-NEXT: Cost Model: Found an estimated cost of 541 for instruction: %V64 = call fast half @llvm.vector.reduce.fmul.v64f16(half 0xH0000, <64 x half> undef) ; FP-REDUCE-ZVFH-NEXT: Cost Model: Found an estimated cost of 573 for instruction: %V128 = call fast half @llvm.vector.reduce.fmul.v128f16(half 0xH0000, <128 x half> undef) +; FP-REDUCE-ZVFH-NEXT: Cost Model: Invalid cost for instruction: %NXV1 = call fast half @llvm.vector.reduce.fmul.nxv1f16(half 0xH0000, undef) +; FP-REDUCE-ZVFH-NEXT: Cost Model: Invalid cost for instruction: %NXV2 = call fast half @llvm.vector.reduce.fmul.nxv2f16(half 0xH0000, undef) +; FP-REDUCE-ZVFH-NEXT: Cost Model: Invalid cost for instruction: %NXV4 = call fast half @llvm.vector.reduce.fmul.nxv4f16(half 0xH0000, undef) +; FP-REDUCE-ZVFH-NEXT: Cost Model: Invalid cost for instruction: %NXV8 = call fast half @llvm.vector.reduce.fmul.nxv8f16(half 0xH0000, undef) +; FP-REDUCE-ZVFH-NEXT: Cost Model: Invalid cost for instruction: %NXV16 = call fast half @llvm.vector.reduce.fmul.nxv16f16(half 0xH0000, undef) +; FP-REDUCE-ZVFH-NEXT: Cost Model: Invalid cost for instruction: %NXV32 = call fast half @llvm.vector.reduce.fmul.nxv32f16(half 0xH0000, undef) ; FP-REDUCE-ZVFH-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret void ; ; FP-REDUCE-ZVFHMIN-LABEL: 'reduce_fmul_half' @@ -58,6 +82,12 @@ define void @reduce_fmul_half() { ; FP-REDUCE-ZVFHMIN-NEXT: Cost Model: Found an estimated cost of 211 for instruction: %v32 = call fast half @llvm.vector.reduce.fmul.v32f16(half 0xH0000, <32 x half> undef) ; FP-REDUCE-ZVFHMIN-NEXT: Cost Model: Found an estimated cost of 541 for instruction: %V64 = call fast half @llvm.vector.reduce.fmul.v64f16(half 0xH0000, <64 x half> undef) ; FP-REDUCE-ZVFHMIN-NEXT: Cost Model: Found an estimated cost of 573 for instruction: %V128 = call fast half @llvm.vector.reduce.fmul.v128f16(half 0xH0000, <128 x half> undef) +; FP-REDUCE-ZVFHMIN-NEXT: Cost Model: Invalid cost for instruction: %NXV1 = call fast half @llvm.vector.reduce.fmul.nxv1f16(half 0xH0000, undef) +; FP-REDUCE-ZVFHMIN-NEXT: Cost Model: Invalid cost for instruction: %NXV2 = call fast half @llvm.vector.reduce.fmul.nxv2f16(half 0xH0000, undef) +; FP-REDUCE-ZVFHMIN-NEXT: Cost Model: Invalid cost for instruction: %NXV4 = call fast half @llvm.vector.reduce.fmul.nxv4f16(half 0xH0000, undef) +; FP-REDUCE-ZVFHMIN-NEXT: Cost Model: Invalid cost for instruction: %NXV8 = call fast half @llvm.vector.reduce.fmul.nxv8f16(half 0xH0000, undef) +; FP-REDUCE-ZVFHMIN-NEXT: Cost Model: Invalid cost for instruction: %NXV16 = call fast half @llvm.vector.reduce.fmul.nxv16f16(half 0xH0000, undef) +; FP-REDUCE-ZVFHMIN-NEXT: Cost Model: Invalid cost for instruction: %NXV32 = call fast half @llvm.vector.reduce.fmul.nxv32f16(half 0xH0000, undef) ; FP-REDUCE-ZVFHMIN-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret void ; ; SIZE-LABEL: 'reduce_fmul_half' @@ -69,6 +99,12 @@ define void @reduce_fmul_half() { ; SIZE-NEXT: Cost Model: Found an estimated cost of 26 for instruction: %v32 = call fast half @llvm.vector.reduce.fmul.v32f16(half 0xH0000, <32 x half> undef) ; SIZE-NEXT: Cost Model: Found an estimated cost of 31 for instruction: %V64 = call fast half @llvm.vector.reduce.fmul.v64f16(half 0xH0000, <64 x half> undef) ; SIZE-NEXT: Cost Model: Found an estimated cost of 34 for instruction: %V128 = call fast half @llvm.vector.reduce.fmul.v128f16(half 0xH0000, <128 x half> undef) +; SIZE-NEXT: Cost Model: Invalid cost for instruction: %NXV1 = call fast half @llvm.vector.reduce.fmul.nxv1f16(half 0xH0000, undef) +; SIZE-NEXT: Cost Model: Invalid cost for instruction: %NXV2 = call fast half @llvm.vector.reduce.fmul.nxv2f16(half 0xH0000, undef) +; SIZE-NEXT: Cost Model: Invalid cost for instruction: %NXV4 = call fast half @llvm.vector.reduce.fmul.nxv4f16(half 0xH0000, undef) +; SIZE-NEXT: Cost Model: Invalid cost for instruction: %NXV8 = call fast half @llvm.vector.reduce.fmul.nxv8f16(half 0xH0000, undef) +; SIZE-NEXT: Cost Model: Invalid cost for instruction: %NXV16 = call fast half @llvm.vector.reduce.fmul.nxv16f16(half 0xH0000, undef) +; SIZE-NEXT: Cost Model: Invalid cost for instruction: %NXV32 = call fast half @llvm.vector.reduce.fmul.nxv32f16(half 0xH0000, undef) ; SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret void ; %V1 = call fast half @llvm.vector.reduce.fmul.v1f16(half 0.0, <1 x half> undef) @@ -79,6 +115,12 @@ define void @reduce_fmul_half() { %v32 = call fast half @llvm.vector.reduce.fmul.v32f16(half 0.0, <32 x half> undef) %V64 = call fast half @llvm.vector.reduce.fmul.v64f16(half 0.0, <64 x half> undef) %V128 = call fast half @llvm.vector.reduce.fmul.v128f16(half 0.0, <128 x half> undef) + %NXV1 = call fast half @llvm.vector.reduce.fmul.nxv1f16(half 0.0, undef) + %NXV2 = call fast half @llvm.vector.reduce.fmul.nxv2f16(half 0.0, undef) + %NXV4 = call fast half @llvm.vector.reduce.fmul.nxv4f16(half 0.0, undef) + %NXV8 = call fast half @llvm.vector.reduce.fmul.nxv8f16(half 0.0, undef) + %NXV16 = call fast half @llvm.vector.reduce.fmul.nxv16f16(half 0.0, undef) + %NXV32 = call fast half @llvm.vector.reduce.fmul.nxv32f16(half 0.0, undef) ret void } @@ -92,6 +134,11 @@ define void @reduce_fmul_float() { ; FP-REDUCE-NEXT: Cost Model: Found an estimated cost of 451 for instruction: %v32 = call fast float @llvm.vector.reduce.fmul.v32f32(float 0.000000e+00, <32 x float> undef) ; FP-REDUCE-NEXT: Cost Model: Found an estimated cost of 483 for instruction: %V64 = call fast float @llvm.vector.reduce.fmul.v64f32(float 0.000000e+00, <64 x float> undef) ; FP-REDUCE-NEXT: Cost Model: Found an estimated cost of 547 for instruction: %V128 = call fast float @llvm.vector.reduce.fmul.v128f32(float 0.000000e+00, <128 x float> undef) +; FP-REDUCE-NEXT: Cost Model: Invalid cost for instruction: %NXV1 = call fast float @llvm.vector.reduce.fmul.nxv1f32(float 0.000000e+00, undef) +; FP-REDUCE-NEXT: Cost Model: Invalid cost for instruction: %NXV2 = call fast float @llvm.vector.reduce.fmul.nxv2f32(float 0.000000e+00, undef) +; FP-REDUCE-NEXT: Cost Model: Invalid cost for instruction: %NXV4 = call fast float @llvm.vector.reduce.fmul.nxv4f32(float 0.000000e+00, undef) +; FP-REDUCE-NEXT: Cost Model: Invalid cost for instruction: %NXV8 = call fast float @llvm.vector.reduce.fmul.nxv8f32(float 0.000000e+00, undef) +; FP-REDUCE-NEXT: Cost Model: Invalid cost for instruction: %NXV16 = call fast float @llvm.vector.reduce.fmul.nxv16f32(float 0.000000e+00, undef) ; FP-REDUCE-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret void ; ; SIZE-LABEL: 'reduce_fmul_float' @@ -103,6 +150,11 @@ define void @reduce_fmul_float() { ; SIZE-NEXT: Cost Model: Found an estimated cost of 26 for instruction: %v32 = call fast float @llvm.vector.reduce.fmul.v32f32(float 0.000000e+00, <32 x float> undef) ; SIZE-NEXT: Cost Model: Found an estimated cost of 29 for instruction: %V64 = call fast float @llvm.vector.reduce.fmul.v64f32(float 0.000000e+00, <64 x float> undef) ; SIZE-NEXT: Cost Model: Found an estimated cost of 34 for instruction: %V128 = call fast float @llvm.vector.reduce.fmul.v128f32(float 0.000000e+00, <128 x float> undef) +; SIZE-NEXT: Cost Model: Invalid cost for instruction: %NXV1 = call fast float @llvm.vector.reduce.fmul.nxv1f32(float 0.000000e+00, undef) +; SIZE-NEXT: Cost Model: Invalid cost for instruction: %NXV2 = call fast float @llvm.vector.reduce.fmul.nxv2f32(float 0.000000e+00, undef) +; SIZE-NEXT: Cost Model: Invalid cost for instruction: %NXV4 = call fast float @llvm.vector.reduce.fmul.nxv4f32(float 0.000000e+00, undef) +; SIZE-NEXT: Cost Model: Invalid cost for instruction: %NXV8 = call fast float @llvm.vector.reduce.fmul.nxv8f32(float 0.000000e+00, undef) +; SIZE-NEXT: Cost Model: Invalid cost for instruction: %NXV16 = call fast float @llvm.vector.reduce.fmul.nxv16f32(float 0.000000e+00, undef) ; SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret void ; %V1 = call fast float @llvm.vector.reduce.fmul.v1f32(float 0.0, <1 x float> undef) @@ -113,6 +165,11 @@ define void @reduce_fmul_float() { %v32 = call fast float @llvm.vector.reduce.fmul.v32f32(float 0.0, <32 x float> undef) %V64 = call fast float @llvm.vector.reduce.fmul.v64f32(float 0.0, <64 x float> undef) %V128 = call fast float @llvm.vector.reduce.fmul.v128f32(float 0.0, <128 x float> undef) + %NXV1 = call fast float @llvm.vector.reduce.fmul.nxv1f32(float 0.0, undef) + %NXV2 = call fast float @llvm.vector.reduce.fmul.nxv2f32(float 0.0, undef) + %NXV4 = call fast float @llvm.vector.reduce.fmul.nxv4f32(float 0.0, undef) + %NXV8 = call fast float @llvm.vector.reduce.fmul.nxv8f32(float 0.0, undef) + %NXV16 = call fast float @llvm.vector.reduce.fmul.nxv16f32(float 0.0, undef) ret void } @@ -126,6 +183,10 @@ define void @reduce_fmul_double() { ; FP-REDUCE-NEXT: Cost Model: Found an estimated cost of 393 for instruction: %v32 = call fast double @llvm.vector.reduce.fmul.v32f64(double 0.000000e+00, <32 x double> undef) ; FP-REDUCE-NEXT: Cost Model: Found an estimated cost of 457 for instruction: %V64 = call fast double @llvm.vector.reduce.fmul.v64f64(double 0.000000e+00, <64 x double> undef) ; FP-REDUCE-NEXT: Cost Model: Found an estimated cost of 585 for instruction: %V128 = call fast double @llvm.vector.reduce.fmul.v128f64(double 0.000000e+00, <128 x double> undef) +; FP-REDUCE-NEXT: Cost Model: Invalid cost for instruction: %NXV1 = call fast double @llvm.vector.reduce.fmul.nxv1f64(double 0.000000e+00, undef) +; FP-REDUCE-NEXT: Cost Model: Invalid cost for instruction: %NXV2 = call fast double @llvm.vector.reduce.fmul.nxv2f64(double 0.000000e+00, undef) +; FP-REDUCE-NEXT: Cost Model: Invalid cost for instruction: %NXV4 = call fast double @llvm.vector.reduce.fmul.nxv4f64(double 0.000000e+00, undef) +; FP-REDUCE-NEXT: Cost Model: Invalid cost for instruction: %NXV8 = call fast double @llvm.vector.reduce.fmul.nxv8f64(double 0.000000e+00, undef) ; FP-REDUCE-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret void ; ; SIZE-LABEL: 'reduce_fmul_double' @@ -137,6 +198,10 @@ define void @reduce_fmul_double() { ; SIZE-NEXT: Cost Model: Found an estimated cost of 24 for instruction: %v32 = call fast double @llvm.vector.reduce.fmul.v32f64(double 0.000000e+00, <32 x double> undef) ; SIZE-NEXT: Cost Model: Found an estimated cost of 29 for instruction: %V64 = call fast double @llvm.vector.reduce.fmul.v64f64(double 0.000000e+00, <64 x double> undef) ; SIZE-NEXT: Cost Model: Found an estimated cost of 38 for instruction: %V128 = call fast double @llvm.vector.reduce.fmul.v128f64(double 0.000000e+00, <128 x double> undef) +; SIZE-NEXT: Cost Model: Invalid cost for instruction: %NXV1 = call fast double @llvm.vector.reduce.fmul.nxv1f64(double 0.000000e+00, undef) +; SIZE-NEXT: Cost Model: Invalid cost for instruction: %NXV2 = call fast double @llvm.vector.reduce.fmul.nxv2f64(double 0.000000e+00, undef) +; SIZE-NEXT: Cost Model: Invalid cost for instruction: %NXV4 = call fast double @llvm.vector.reduce.fmul.nxv4f64(double 0.000000e+00, undef) +; SIZE-NEXT: Cost Model: Invalid cost for instruction: %NXV8 = call fast double @llvm.vector.reduce.fmul.nxv8f64(double 0.000000e+00, undef) ; SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret void ; %V1 = call fast double @llvm.vector.reduce.fmul.v1f64(double 0.0, <1 x double> undef) @@ -147,6 +212,10 @@ define void @reduce_fmul_double() { %v32 = call fast double @llvm.vector.reduce.fmul.v32f64(double 0.0, <32 x double> undef) %V64 = call fast double @llvm.vector.reduce.fmul.v64f64(double 0.0, <64 x double> undef) %V128 = call fast double @llvm.vector.reduce.fmul.v128f64(double 0.0, <128 x double> undef) + %NXV1 = call fast double @llvm.vector.reduce.fmul.nxv1f64(double 0.0, undef) + %NXV2 = call fast double @llvm.vector.reduce.fmul.nxv2f64(double 0.0, undef) + %NXV4 = call fast double @llvm.vector.reduce.fmul.nxv4f64(double 0.0, undef) + %NXV8 = call fast double @llvm.vector.reduce.fmul.nxv8f64(double 0.0, undef) ret void } @@ -160,6 +229,12 @@ define void @reduce_ordered_fmul_bfloat() { ; FP-REDUCE-NEXT: Cost Model: Found an estimated cost of 127 for instruction: %v32 = call bfloat @llvm.vector.reduce.fmul.v32bf16(bfloat 0xR0000, <32 x bfloat> undef) ; FP-REDUCE-NEXT: Cost Model: Found an estimated cost of 255 for instruction: %V64 = call bfloat @llvm.vector.reduce.fmul.v64bf16(bfloat 0xR0000, <64 x bfloat> undef) ; FP-REDUCE-NEXT: Cost Model: Found an estimated cost of 510 for instruction: %V128 = call bfloat @llvm.vector.reduce.fmul.v128bf16(bfloat 0xR0000, <128 x bfloat> undef) +; FP-REDUCE-NEXT: Cost Model: Invalid cost for instruction: %NXV1 = call bfloat @llvm.vector.reduce.fmul.nxv1bf16(bfloat 0xR0000, undef) +; FP-REDUCE-NEXT: Cost Model: Invalid cost for instruction: %NXV2 = call bfloat @llvm.vector.reduce.fmul.nxv2bf16(bfloat 0xR0000, undef) +; FP-REDUCE-NEXT: Cost Model: Invalid cost for instruction: %NXV4 = call bfloat @llvm.vector.reduce.fmul.nxv4bf16(bfloat 0xR0000, undef) +; FP-REDUCE-NEXT: Cost Model: Invalid cost for instruction: %NXV8 = call bfloat @llvm.vector.reduce.fmul.nxv8bf16(bfloat 0xR0000, undef) +; FP-REDUCE-NEXT: Cost Model: Invalid cost for instruction: %NXV16 = call bfloat @llvm.vector.reduce.fmul.nxv16bf16(bfloat 0xR0000, undef) +; FP-REDUCE-NEXT: Cost Model: Invalid cost for instruction: %NXV32 = call bfloat @llvm.vector.reduce.fmul.nxv32bf16(bfloat 0xR0000, undef) ; FP-REDUCE-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret void ; ; SIZE-LABEL: 'reduce_ordered_fmul_bfloat' @@ -171,6 +246,12 @@ define void @reduce_ordered_fmul_bfloat() { ; SIZE-NEXT: Cost Model: Found an estimated cost of 95 for instruction: %v32 = call bfloat @llvm.vector.reduce.fmul.v32bf16(bfloat 0xR0000, <32 x bfloat> undef) ; SIZE-NEXT: Cost Model: Found an estimated cost of 191 for instruction: %V64 = call bfloat @llvm.vector.reduce.fmul.v64bf16(bfloat 0xR0000, <64 x bfloat> undef) ; SIZE-NEXT: Cost Model: Found an estimated cost of 382 for instruction: %V128 = call bfloat @llvm.vector.reduce.fmul.v128bf16(bfloat 0xR0000, <128 x bfloat> undef) +; SIZE-NEXT: Cost Model: Invalid cost for instruction: %NXV1 = call bfloat @llvm.vector.reduce.fmul.nxv1bf16(bfloat 0xR0000, undef) +; SIZE-NEXT: Cost Model: Invalid cost for instruction: %NXV2 = call bfloat @llvm.vector.reduce.fmul.nxv2bf16(bfloat 0xR0000, undef) +; SIZE-NEXT: Cost Model: Invalid cost for instruction: %NXV4 = call bfloat @llvm.vector.reduce.fmul.nxv4bf16(bfloat 0xR0000, undef) +; SIZE-NEXT: Cost Model: Invalid cost for instruction: %NXV8 = call bfloat @llvm.vector.reduce.fmul.nxv8bf16(bfloat 0xR0000, undef) +; SIZE-NEXT: Cost Model: Invalid cost for instruction: %NXV16 = call bfloat @llvm.vector.reduce.fmul.nxv16bf16(bfloat 0xR0000, undef) +; SIZE-NEXT: Cost Model: Invalid cost for instruction: %NXV32 = call bfloat @llvm.vector.reduce.fmul.nxv32bf16(bfloat 0xR0000, undef) ; SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret void ; %V1 = call bfloat @llvm.vector.reduce.fmul.v1bf16(bfloat 0.0, <1 x bfloat> undef) @@ -181,6 +262,12 @@ define void @reduce_ordered_fmul_bfloat() { %v32 = call bfloat @llvm.vector.reduce.fmul.v32bf16(bfloat 0.0, <32 x bfloat> undef) %V64 = call bfloat @llvm.vector.reduce.fmul.v64bf16(bfloat 0.0, <64 x bfloat> undef) %V128 = call bfloat @llvm.vector.reduce.fmul.v128bf16(bfloat 0.0, <128 x bfloat> undef) + %NXV1 = call bfloat @llvm.vector.reduce.fmul.nxv1bf16(bfloat 0.0, undef) + %NXV2 = call bfloat @llvm.vector.reduce.fmul.nxv2bf16(bfloat 0.0, undef) + %NXV4 = call bfloat @llvm.vector.reduce.fmul.nxv4bf16(bfloat 0.0, undef) + %NXV8 = call bfloat @llvm.vector.reduce.fmul.nxv8bf16(bfloat 0.0, undef) + %NXV16 = call bfloat @llvm.vector.reduce.fmul.nxv16bf16(bfloat 0.0, undef) + %NXV32 = call bfloat @llvm.vector.reduce.fmul.nxv32bf16(bfloat 0.0, undef) ret void } @@ -194,6 +281,12 @@ define void @reduce_ordered_fmul_half() { ; FP-REDUCE-NEXT: Cost Model: Found an estimated cost of 127 for instruction: %v32 = call half @llvm.vector.reduce.fmul.v32f16(half 0xH0000, <32 x half> undef) ; FP-REDUCE-NEXT: Cost Model: Found an estimated cost of 255 for instruction: %V64 = call half @llvm.vector.reduce.fmul.v64f16(half 0xH0000, <64 x half> undef) ; FP-REDUCE-NEXT: Cost Model: Found an estimated cost of 510 for instruction: %V128 = call half @llvm.vector.reduce.fmul.v128f16(half 0xH0000, <128 x half> undef) +; FP-REDUCE-NEXT: Cost Model: Invalid cost for instruction: %NXV1 = call half @llvm.vector.reduce.fmul.nxv1f16(half 0xH0000, undef) +; FP-REDUCE-NEXT: Cost Model: Invalid cost for instruction: %NXV2 = call half @llvm.vector.reduce.fmul.nxv2f16(half 0xH0000, undef) +; FP-REDUCE-NEXT: Cost Model: Invalid cost for instruction: %NXV4 = call half @llvm.vector.reduce.fmul.nxv4f16(half 0xH0000, undef) +; FP-REDUCE-NEXT: Cost Model: Invalid cost for instruction: %NXV8 = call half @llvm.vector.reduce.fmul.nxv8f16(half 0xH0000, undef) +; FP-REDUCE-NEXT: Cost Model: Invalid cost for instruction: %NXV16 = call half @llvm.vector.reduce.fmul.nxv16f16(half 0xH0000, undef) +; FP-REDUCE-NEXT: Cost Model: Invalid cost for instruction: %NXV32 = call half @llvm.vector.reduce.fmul.nxv32f16(half 0xH0000, undef) ; FP-REDUCE-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret void ; ; SIZE-LABEL: 'reduce_ordered_fmul_half' @@ -205,6 +298,12 @@ define void @reduce_ordered_fmul_half() { ; SIZE-NEXT: Cost Model: Found an estimated cost of 95 for instruction: %v32 = call half @llvm.vector.reduce.fmul.v32f16(half 0xH0000, <32 x half> undef) ; SIZE-NEXT: Cost Model: Found an estimated cost of 191 for instruction: %V64 = call half @llvm.vector.reduce.fmul.v64f16(half 0xH0000, <64 x half> undef) ; SIZE-NEXT: Cost Model: Found an estimated cost of 382 for instruction: %V128 = call half @llvm.vector.reduce.fmul.v128f16(half 0xH0000, <128 x half> undef) +; SIZE-NEXT: Cost Model: Invalid cost for instruction: %NXV1 = call half @llvm.vector.reduce.fmul.nxv1f16(half 0xH0000, undef) +; SIZE-NEXT: Cost Model: Invalid cost for instruction: %NXV2 = call half @llvm.vector.reduce.fmul.nxv2f16(half 0xH0000, undef) +; SIZE-NEXT: Cost Model: Invalid cost for instruction: %NXV4 = call half @llvm.vector.reduce.fmul.nxv4f16(half 0xH0000, undef) +; SIZE-NEXT: Cost Model: Invalid cost for instruction: %NXV8 = call half @llvm.vector.reduce.fmul.nxv8f16(half 0xH0000, undef) +; SIZE-NEXT: Cost Model: Invalid cost for instruction: %NXV16 = call half @llvm.vector.reduce.fmul.nxv16f16(half 0xH0000, undef) +; SIZE-NEXT: Cost Model: Invalid cost for instruction: %NXV32 = call half @llvm.vector.reduce.fmul.nxv32f16(half 0xH0000, undef) ; SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret void ; %V1 = call half @llvm.vector.reduce.fmul.v1f16(half 0.0, <1 x half> undef) @@ -215,6 +314,12 @@ define void @reduce_ordered_fmul_half() { %v32 = call half @llvm.vector.reduce.fmul.v32f16(half 0.0, <32 x half> undef) %V64 = call half @llvm.vector.reduce.fmul.v64f16(half 0.0, <64 x half> undef) %V128 = call half @llvm.vector.reduce.fmul.v128f16(half 0.0, <128 x half> undef) + %NXV1 = call half @llvm.vector.reduce.fmul.nxv1f16(half 0.0, undef) + %NXV2 = call half @llvm.vector.reduce.fmul.nxv2f16(half 0.0, undef) + %NXV4 = call half @llvm.vector.reduce.fmul.nxv4f16(half 0.0, undef) + %NXV8 = call half @llvm.vector.reduce.fmul.nxv8f16(half 0.0, undef) + %NXV16 = call half @llvm.vector.reduce.fmul.nxv16f16(half 0.0, undef) + %NXV32 = call half @llvm.vector.reduce.fmul.nxv32f16(half 0.0, undef) ret void } @@ -228,6 +333,11 @@ define void @reduce_ordered_fmul_float() { ; FP-REDUCE-NEXT: Cost Model: Found an estimated cost of 127 for instruction: %v32 = call float @llvm.vector.reduce.fmul.v32f32(float 0.000000e+00, <32 x float> undef) ; FP-REDUCE-NEXT: Cost Model: Found an estimated cost of 254 for instruction: %V64 = call float @llvm.vector.reduce.fmul.v64f32(float 0.000000e+00, <64 x float> undef) ; FP-REDUCE-NEXT: Cost Model: Found an estimated cost of 508 for instruction: %V128 = call float @llvm.vector.reduce.fmul.v128f32(float 0.000000e+00, <128 x float> undef) +; FP-REDUCE-NEXT: Cost Model: Invalid cost for instruction: %NXV1 = call float @llvm.vector.reduce.fmul.nxv1f32(float 0.000000e+00, undef) +; FP-REDUCE-NEXT: Cost Model: Invalid cost for instruction: %NXV2 = call float @llvm.vector.reduce.fmul.nxv2f32(float 0.000000e+00, undef) +; FP-REDUCE-NEXT: Cost Model: Invalid cost for instruction: %NXV4 = call float @llvm.vector.reduce.fmul.nxv4f32(float 0.000000e+00, undef) +; FP-REDUCE-NEXT: Cost Model: Invalid cost for instruction: %NXV8 = call float @llvm.vector.reduce.fmul.nxv8f32(float 0.000000e+00, undef) +; FP-REDUCE-NEXT: Cost Model: Invalid cost for instruction: %NXV16 = call float @llvm.vector.reduce.fmul.nxv16f32(float 0.000000e+00, undef) ; FP-REDUCE-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret void ; ; SIZE-LABEL: 'reduce_ordered_fmul_float' @@ -239,6 +349,11 @@ define void @reduce_ordered_fmul_float() { ; SIZE-NEXT: Cost Model: Found an estimated cost of 95 for instruction: %v32 = call float @llvm.vector.reduce.fmul.v32f32(float 0.000000e+00, <32 x float> undef) ; SIZE-NEXT: Cost Model: Found an estimated cost of 190 for instruction: %V64 = call float @llvm.vector.reduce.fmul.v64f32(float 0.000000e+00, <64 x float> undef) ; SIZE-NEXT: Cost Model: Found an estimated cost of 380 for instruction: %V128 = call float @llvm.vector.reduce.fmul.v128f32(float 0.000000e+00, <128 x float> undef) +; SIZE-NEXT: Cost Model: Invalid cost for instruction: %NXV1 = call float @llvm.vector.reduce.fmul.nxv1f32(float 0.000000e+00, undef) +; SIZE-NEXT: Cost Model: Invalid cost for instruction: %NXV2 = call float @llvm.vector.reduce.fmul.nxv2f32(float 0.000000e+00, undef) +; SIZE-NEXT: Cost Model: Invalid cost for instruction: %NXV4 = call float @llvm.vector.reduce.fmul.nxv4f32(float 0.000000e+00, undef) +; SIZE-NEXT: Cost Model: Invalid cost for instruction: %NXV8 = call float @llvm.vector.reduce.fmul.nxv8f32(float 0.000000e+00, undef) +; SIZE-NEXT: Cost Model: Invalid cost for instruction: %NXV16 = call float @llvm.vector.reduce.fmul.nxv16f32(float 0.000000e+00, undef) ; SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret void ; %V1 = call float @llvm.vector.reduce.fmul.v1f32(float 0.0, <1 x float> undef) @@ -249,6 +364,11 @@ define void @reduce_ordered_fmul_float() { %v32 = call float @llvm.vector.reduce.fmul.v32f32(float 0.0, <32 x float> undef) %V64 = call float @llvm.vector.reduce.fmul.v64f32(float 0.0, <64 x float> undef) %V128 = call float @llvm.vector.reduce.fmul.v128f32(float 0.0, <128 x float> undef) + %NXV1 = call float @llvm.vector.reduce.fmul.nxv1f32(float 0.0, undef) + %NXV2 = call float @llvm.vector.reduce.fmul.nxv2f32(float 0.0, undef) + %NXV4 = call float @llvm.vector.reduce.fmul.nxv4f32(float 0.0, undef) + %NXV8 = call float @llvm.vector.reduce.fmul.nxv8f32(float 0.0, undef) + %NXV16 = call float @llvm.vector.reduce.fmul.nxv16f32(float 0.0, undef) ret void } @@ -262,6 +382,10 @@ define void @reduce_ordered_fmul_double() { ; FP-REDUCE-NEXT: Cost Model: Found an estimated cost of 126 for instruction: %v32 = call double @llvm.vector.reduce.fmul.v32f64(double 0.000000e+00, <32 x double> undef) ; FP-REDUCE-NEXT: Cost Model: Found an estimated cost of 252 for instruction: %V64 = call double @llvm.vector.reduce.fmul.v64f64(double 0.000000e+00, <64 x double> undef) ; FP-REDUCE-NEXT: Cost Model: Found an estimated cost of 504 for instruction: %V128 = call double @llvm.vector.reduce.fmul.v128f64(double 0.000000e+00, <128 x double> undef) +; FP-REDUCE-NEXT: Cost Model: Invalid cost for instruction: %NXV1 = call double @llvm.vector.reduce.fmul.nxv1f64(double 0.000000e+00, undef) +; FP-REDUCE-NEXT: Cost Model: Invalid cost for instruction: %NXV2 = call double @llvm.vector.reduce.fmul.nxv2f64(double 0.000000e+00, undef) +; FP-REDUCE-NEXT: Cost Model: Invalid cost for instruction: %NXV4 = call double @llvm.vector.reduce.fmul.nxv4f64(double 0.000000e+00, undef) +; FP-REDUCE-NEXT: Cost Model: Invalid cost for instruction: %NXV8 = call double @llvm.vector.reduce.fmul.nxv8f64(double 0.000000e+00, undef) ; FP-REDUCE-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret void ; ; SIZE-LABEL: 'reduce_ordered_fmul_double' @@ -273,6 +397,10 @@ define void @reduce_ordered_fmul_double() { ; SIZE-NEXT: Cost Model: Found an estimated cost of 94 for instruction: %v32 = call double @llvm.vector.reduce.fmul.v32f64(double 0.000000e+00, <32 x double> undef) ; SIZE-NEXT: Cost Model: Found an estimated cost of 188 for instruction: %V64 = call double @llvm.vector.reduce.fmul.v64f64(double 0.000000e+00, <64 x double> undef) ; SIZE-NEXT: Cost Model: Found an estimated cost of 376 for instruction: %V128 = call double @llvm.vector.reduce.fmul.v128f64(double 0.000000e+00, <128 x double> undef) +; SIZE-NEXT: Cost Model: Invalid cost for instruction: %NXV1 = call double @llvm.vector.reduce.fmul.nxv1f64(double 0.000000e+00, undef) +; SIZE-NEXT: Cost Model: Invalid cost for instruction: %NXV2 = call double @llvm.vector.reduce.fmul.nxv2f64(double 0.000000e+00, undef) +; SIZE-NEXT: Cost Model: Invalid cost for instruction: %NXV4 = call double @llvm.vector.reduce.fmul.nxv4f64(double 0.000000e+00, undef) +; SIZE-NEXT: Cost Model: Invalid cost for instruction: %NXV8 = call double @llvm.vector.reduce.fmul.nxv8f64(double 0.000000e+00, undef) ; SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret void ; %V1 = call double @llvm.vector.reduce.fmul.v1f64(double 0.0, <1 x double> undef) @@ -283,5 +411,9 @@ define void @reduce_ordered_fmul_double() { %v32 = call double @llvm.vector.reduce.fmul.v32f64(double 0.0, <32 x double> undef) %V64 = call double @llvm.vector.reduce.fmul.v64f64(double 0.0, <64 x double> undef) %V128 = call double @llvm.vector.reduce.fmul.v128f64(double 0.0, <128 x double> undef) + %NXV1 = call double @llvm.vector.reduce.fmul.nxv1f64(double 0.0, undef) + %NXV2 = call double @llvm.vector.reduce.fmul.nxv2f64(double 0.0, undef) + %NXV4 = call double @llvm.vector.reduce.fmul.nxv4f64(double 0.0, undef) + %NXV8 = call double @llvm.vector.reduce.fmul.nxv8f64(double 0.0, undef) ret void } diff --git a/llvm/test/Analysis/StackSafetyAnalysis/local.ll b/llvm/test/Analysis/StackSafetyAnalysis/local.ll index 4a833611c78916..02d46c8449bae5 100644 --- a/llvm/test/Analysis/StackSafetyAnalysis/local.ll +++ b/llvm/test/Analysis/StackSafetyAnalysis/local.ll @@ -1120,5 +1120,21 @@ define void @NonPointer(ptr %p) { ret void } +@ifunc = dso_local ifunc i64 (ptr), ptr @ifunc_resolver + +define dso_local void @CallIfunc(ptr noundef %uaddr) local_unnamed_addr { +; CHECK-LABEL: @CallIfunc +; CHECK-NEXT: args uses: +; CHECK-NEXT: uaddr[]: full-set +entry: + tail call i64 @ifunc(ptr noundef %uaddr) + ret void +} + +define dso_local ptr @ifunc_resolver() { +entry: + ret ptr null +} + declare void @llvm.lifetime.start.p0(i64, ptr nocapture) declare void @llvm.lifetime.end.p0(i64, ptr nocapture) diff --git a/llvm/test/Assembler/invalid-inttype.ll b/llvm/test/Assembler/invalid-inttype.ll index c8aa7c66b79e4d..9e3c31148af2d6 100644 --- a/llvm/test/Assembler/invalid-inttype.ll +++ b/llvm/test/Assembler/invalid-inttype.ll @@ -1,5 +1,5 @@ ; RUN: not llvm-as --disable-output %s 2>&1 | FileCheck -DFILE=%s %s ; i8388609 is the smallest integer type that can't be represented in LLVM IR -; CHECK: [[FILE]]:[[@LINE+1]]:21: error: bitwidth for integer type out of range! +; CHECK: [[FILE]]:[[@LINE+1]]:21: error: bitwidth for integer type out of range @i2 = common global i8388609 0, align 4 diff --git a/llvm/test/Assembler/invalid-name.ll b/llvm/test/Assembler/invalid-name.ll index 74133e60df54d5..52e2bda3adbabd 100644 Binary files a/llvm/test/Assembler/invalid-name.ll and b/llvm/test/Assembler/invalid-name.ll differ diff --git a/llvm/test/Assembler/invalid-name2.ll b/llvm/test/Assembler/invalid-name2.ll index 8a848798a54caf..78da4dc3d1b8d0 100644 Binary files a/llvm/test/Assembler/invalid-name2.ll and b/llvm/test/Assembler/invalid-name2.ll differ diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-samesign.ll b/llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-samesign.ll new file mode 100644 index 00000000000000..0173f92c982203 --- /dev/null +++ b/llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-samesign.ll @@ -0,0 +1,69 @@ +; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 4 +; RUN: llc -global-isel -mtriple=aarch64-linux-gnu -O0 -stop-after=irtranslator < %s | FileCheck %s + + +define <2 x i1> @call_icmp_samesign_vector(<2 x i32> %a, <2 x i32> %b) { + ; CHECK-LABEL: name: call_icmp_samesign_vector + ; CHECK: bb.1.entry: + ; CHECK-NEXT: liveins: $d0, $d1 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<2 x s32>) = COPY $d0 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<2 x s32>) = COPY $d1 + ; CHECK-NEXT: %2:_(<2 x s1>) = samesign G_ICMP intpred(ult), [[COPY]](<2 x s32>), [[COPY1]] + ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(<2 x s32>) = G_ANYEXT %2(<2 x s1>) + ; CHECK-NEXT: $d0 = COPY [[ANYEXT]](<2 x s32>) + ; CHECK-NEXT: RET_ReallyLR implicit $d0 +entry: + %result = icmp samesign ult <2 x i32> %a, %b + ret <2 x i1> %result +} + +define <2 x i1> @call_icmp_vector(<2 x i32> %a, <2 x i32> %b) { + ; CHECK-LABEL: name: call_icmp_vector + ; CHECK: bb.1.entry: + ; CHECK-NEXT: liveins: $d0, $d1 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<2 x s32>) = COPY $d0 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<2 x s32>) = COPY $d1 + ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(<2 x s1>) = G_ICMP intpred(ult), [[COPY]](<2 x s32>), [[COPY1]] + ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(<2 x s32>) = G_ANYEXT [[ICMP]](<2 x s1>) + ; CHECK-NEXT: $d0 = COPY [[ANYEXT]](<2 x s32>) + ; CHECK-NEXT: RET_ReallyLR implicit $d0 +entry: + %result = icmp ult <2 x i32> %a, %b + ret <2 x i1> %result +} + +define i1 @call_icmp(i32 %a) { + ; CHECK-LABEL: name: call_icmp + ; CHECK: bb.1.entry: + ; CHECK-NEXT: liveins: $w0 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $w0 + ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 3 + ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(ult), [[COPY]](s32), [[C]] + ; CHECK-NEXT: [[ZEXT:%[0-9]+]]:_(s8) = G_ZEXT [[ICMP]](s1) + ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[ZEXT]](s8) + ; CHECK-NEXT: $w0 = COPY [[ANYEXT]](s32) + ; CHECK-NEXT: RET_ReallyLR implicit $w0 +entry: + %result = icmp ult i32 %a, 3 + ret i1 %result +} + +define i1 @call_icmp_samesign(i32 %a) { + ; CHECK-LABEL: name: call_icmp_samesign + ; CHECK: bb.1.entry: + ; CHECK-NEXT: liveins: $w0 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $w0 + ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 3 + ; CHECK-NEXT: %2:_(s1) = samesign G_ICMP intpred(ult), [[COPY]](s32), [[C]] + ; CHECK-NEXT: [[ZEXT:%[0-9]+]]:_(s8) = G_ZEXT %2(s1) + ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[ZEXT]](s8) + ; CHECK-NEXT: $w0 = COPY [[ANYEXT]](s32) + ; CHECK-NEXT: RET_ReallyLR implicit $w0 +entry: + %result = icmp samesign ult i32 %a, 3 + ret i1 %result +} diff --git a/llvm/test/CodeGen/AArch64/arm64-vshift.ll b/llvm/test/CodeGen/AArch64/arm64-vshift.ll index 1dfd977186b0e7..7af7c235f9ac16 100644 --- a/llvm/test/CodeGen/AArch64/arm64-vshift.ll +++ b/llvm/test/CodeGen/AArch64/arm64-vshift.ll @@ -3560,4 +3560,16 @@ entry: ret <4 x i16> %vrshrn_n1 } +define <8 x i16> @signbits_vashr(<8 x i16> %a) { +; CHECK-LABEL: signbits_vashr: +; CHECK: // %bb.0: +; CHECK-NEXT: sshr.8h v0, v0, #8 +; CHECK-NEXT: sshr.8h v0, v0, #9 +; CHECK-NEXT: ret + %b = call <8 x i16> @llvm.aarch64.neon.sshl.v8i16(<8 x i16> %a, <8 x i16> ) + %c = call <8 x i16> @llvm.aarch64.neon.sshl.v8i16(<8 x i16> %b, <8 x i16> ) + %d = ashr <8 x i16> %c, + ret <8 x i16> %d +} + declare <2 x i64> @llvm.aarch64.neon.addp.v2i64(<2 x i64>, <2 x i64>) diff --git a/llvm/test/CodeGen/AArch64/jump-table-duplicate.mir b/llvm/test/CodeGen/AArch64/jump-table-duplicate.mir index 0963ecbb123115..a2532a854923f5 100644 --- a/llvm/test/CodeGen/AArch64/jump-table-duplicate.mir +++ b/llvm/test/CodeGen/AArch64/jump-table-duplicate.mir @@ -1,4 +1,5 @@ # RUN: llc -run-pass=tailduplication -tail-dup-size=4 %s -o - | FileCheck %s +# RUN: llc -passes=tailduplication -tail-dup-size=4 %s -o - | FileCheck %s # JumpTableDest32 uses an `adr` to a temporary label (itself). If duplicated we # cannot guarantee reachability for any uses after the first. diff --git a/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-concat.ll b/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-concat.ll index c1810c678ea522..6e2ecfca9e963e 100644 --- a/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-concat.ll +++ b/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-concat.ll @@ -1,6 +1,6 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mattr=+sve -force-streaming-compatible < %s | FileCheck %s -; RUN: llc -mattr=+sme -force-streaming < %s | FileCheck %s +; RUN: llc -mattr=+sve2 -force-streaming-compatible < %s | FileCheck %s --check-prefixes=CHECK,SVE2 +; RUN: llc -mattr=+sme -force-streaming < %s | FileCheck %s --check-prefixes=CHECK,SME ; RUN: llc -force-streaming-compatible < %s | FileCheck %s --check-prefix=NONEON-NOSVE target triple = "aarch64-unknown-linux-gnu" @@ -61,10 +61,10 @@ define <8 x i8> @concat_v8i8(<4 x i8> %op1, <4 x i8> %op2) { define <16 x i8> @concat_v16i8(<8 x i8> %op1, <8 x i8> %op2) { ; CHECK-LABEL: concat_v16i8: ; CHECK: // %bb.0: +; CHECK-NEXT: // kill: def $d1 killed $d1 killed $z0_z1 def $z0_z1 ; CHECK-NEXT: ptrue p0.b, vl8 -; CHECK-NEXT: // kill: def $d0 killed $d0 def $z0 -; CHECK-NEXT: // kill: def $d1 killed $d1 def $z1 -; CHECK-NEXT: splice z0.b, p0, z0.b, z1.b +; CHECK-NEXT: // kill: def $d0 killed $d0 killed $z0_z1 def $z0_z1 +; CHECK-NEXT: splice z0.b, p0, { z0.b, z1.b } ; CHECK-NEXT: // kill: def $q0 killed $q0 killed $z0 ; CHECK-NEXT: ret ; @@ -172,10 +172,10 @@ define <4 x i16> @concat_v4i16(<2 x i16> %op1, <2 x i16> %op2) { define <8 x i16> @concat_v8i16(<4 x i16> %op1, <4 x i16> %op2) { ; CHECK-LABEL: concat_v8i16: ; CHECK: // %bb.0: +; CHECK-NEXT: // kill: def $d1 killed $d1 killed $z0_z1 def $z0_z1 ; CHECK-NEXT: ptrue p0.h, vl4 -; CHECK-NEXT: // kill: def $d0 killed $d0 def $z0 -; CHECK-NEXT: // kill: def $d1 killed $d1 def $z1 -; CHECK-NEXT: splice z0.h, p0, z0.h, z1.h +; CHECK-NEXT: // kill: def $d0 killed $d0 killed $z0_z1 def $z0_z1 +; CHECK-NEXT: splice z0.h, p0, { z0.h, z1.h } ; CHECK-NEXT: // kill: def $q0 killed $q0 killed $z0 ; CHECK-NEXT: ret ; @@ -270,10 +270,10 @@ define <2 x i32> @concat_v2i32(<1 x i32> %op1, <1 x i32> %op2) { define <4 x i32> @concat_v4i32(<2 x i32> %op1, <2 x i32> %op2) { ; CHECK-LABEL: concat_v4i32: ; CHECK: // %bb.0: +; CHECK-NEXT: // kill: def $d1 killed $d1 killed $z0_z1 def $z0_z1 ; CHECK-NEXT: ptrue p0.s, vl2 -; CHECK-NEXT: // kill: def $d0 killed $d0 def $z0 -; CHECK-NEXT: // kill: def $d1 killed $d1 def $z1 -; CHECK-NEXT: splice z0.s, p0, z0.s, z1.s +; CHECK-NEXT: // kill: def $d0 killed $d0 killed $z0_z1 def $z0_z1 +; CHECK-NEXT: splice z0.s, p0, { z0.s, z1.s } ; CHECK-NEXT: // kill: def $q0 killed $q0 killed $z0 ; CHECK-NEXT: ret ; @@ -340,10 +340,10 @@ define void @concat_v16i32(ptr %a, ptr %b, ptr %c) { define <2 x i64> @concat_v2i64(<1 x i64> %op1, <1 x i64> %op2) { ; CHECK-LABEL: concat_v2i64: ; CHECK: // %bb.0: +; CHECK-NEXT: // kill: def $d1 killed $d1 killed $z0_z1 def $z0_z1 ; CHECK-NEXT: ptrue p0.d, vl1 -; CHECK-NEXT: // kill: def $d0 killed $d0 def $z0 -; CHECK-NEXT: // kill: def $d1 killed $d1 def $z1 -; CHECK-NEXT: splice z0.d, p0, z0.d, z1.d +; CHECK-NEXT: // kill: def $d0 killed $d0 killed $z0_z1 def $z0_z1 +; CHECK-NEXT: splice z0.d, p0, { z0.d, z1.d } ; CHECK-NEXT: // kill: def $q0 killed $q0 killed $z0 ; CHECK-NEXT: ret ; @@ -406,17 +406,33 @@ define void @concat_v8i64(ptr %a, ptr %b, ptr %c) { ; define <4 x half> @concat_v4f16(<2 x half> %op1, <2 x half> %op2) { -; CHECK-LABEL: concat_v4f16: -; CHECK: // %bb.0: -; CHECK-NEXT: // kill: def $d1 killed $d1 def $z1 -; CHECK-NEXT: // kill: def $d0 killed $d0 def $z0 -; CHECK-NEXT: mov z2.h, z1.h[1] -; CHECK-NEXT: mov z3.h, z0.h[1] -; CHECK-NEXT: zip1 z1.h, z1.h, z2.h -; CHECK-NEXT: zip1 z0.h, z0.h, z3.h -; CHECK-NEXT: zip1 z0.s, z0.s, z1.s -; CHECK-NEXT: // kill: def $d0 killed $d0 killed $z0 -; CHECK-NEXT: ret +; SVE2-LABEL: concat_v4f16: +; SVE2: // %bb.0: +; SVE2-NEXT: cnth x8 +; SVE2-NEXT: adrp x9, .LCPI15_0 +; SVE2-NEXT: adrp x10, .LCPI15_1 +; SVE2-NEXT: mov z2.h, w8 +; SVE2-NEXT: ldr q3, [x9, :lo12:.LCPI15_0] +; SVE2-NEXT: ldr q4, [x10, :lo12:.LCPI15_1] +; SVE2-NEXT: ptrue p0.h, vl8 +; SVE2-NEXT: // kill: def $d1 killed $d1 killed $z0_z1 def $z0_z1 +; SVE2-NEXT: // kill: def $d0 killed $d0 killed $z0_z1 def $z0_z1 +; SVE2-NEXT: mad z2.h, p0/m, z3.h, z4.h +; SVE2-NEXT: tbl z0.h, { z0.h, z1.h }, z2.h +; SVE2-NEXT: // kill: def $d0 killed $d0 killed $z0 +; SVE2-NEXT: ret +; +; SME-LABEL: concat_v4f16: +; SME: // %bb.0: +; SME-NEXT: // kill: def $d1 killed $d1 def $z1 +; SME-NEXT: // kill: def $d0 killed $d0 def $z0 +; SME-NEXT: mov z2.h, z1.h[1] +; SME-NEXT: mov z3.h, z0.h[1] +; SME-NEXT: zip1 z1.h, z1.h, z2.h +; SME-NEXT: zip1 z0.h, z0.h, z3.h +; SME-NEXT: zip1 z0.s, z0.s, z1.s +; SME-NEXT: // kill: def $d0 killed $d0 killed $z0 +; SME-NEXT: ret ; ; NONEON-NOSVE-LABEL: concat_v4f16: ; NONEON-NOSVE: // %bb.0: @@ -436,10 +452,10 @@ define <4 x half> @concat_v4f16(<2 x half> %op1, <2 x half> %op2) { define <8 x half> @concat_v8f16(<4 x half> %op1, <4 x half> %op2) { ; CHECK-LABEL: concat_v8f16: ; CHECK: // %bb.0: +; CHECK-NEXT: // kill: def $d1 killed $d1 killed $z0_z1 def $z0_z1 ; CHECK-NEXT: ptrue p0.h, vl4 -; CHECK-NEXT: // kill: def $d0 killed $d0 def $z0 -; CHECK-NEXT: // kill: def $d1 killed $d1 def $z1 -; CHECK-NEXT: splice z0.h, p0, z0.h, z1.h +; CHECK-NEXT: // kill: def $d0 killed $d0 killed $z0_z1 def $z0_z1 +; CHECK-NEXT: splice z0.h, p0, { z0.h, z1.h } ; CHECK-NEXT: // kill: def $q0 killed $q0 killed $z0 ; CHECK-NEXT: ret ; @@ -534,10 +550,10 @@ define <2 x float> @concat_v2f32(<1 x float> %op1, <1 x float> %op2) { define <4 x float> @concat_v4f32(<2 x float> %op1, <2 x float> %op2) { ; CHECK-LABEL: concat_v4f32: ; CHECK: // %bb.0: +; CHECK-NEXT: // kill: def $d1 killed $d1 killed $z0_z1 def $z0_z1 ; CHECK-NEXT: ptrue p0.s, vl2 -; CHECK-NEXT: // kill: def $d0 killed $d0 def $z0 -; CHECK-NEXT: // kill: def $d1 killed $d1 def $z1 -; CHECK-NEXT: splice z0.s, p0, z0.s, z1.s +; CHECK-NEXT: // kill: def $d0 killed $d0 killed $z0_z1 def $z0_z1 +; CHECK-NEXT: splice z0.s, p0, { z0.s, z1.s } ; CHECK-NEXT: // kill: def $q0 killed $q0 killed $z0 ; CHECK-NEXT: ret ; @@ -604,10 +620,10 @@ define void @concat_v16f32(ptr %a, ptr %b, ptr %c) { define <2 x double> @concat_v2f64(<1 x double> %op1, <1 x double> %op2) { ; CHECK-LABEL: concat_v2f64: ; CHECK: // %bb.0: +; CHECK-NEXT: // kill: def $d1 killed $d1 killed $z0_z1 def $z0_z1 ; CHECK-NEXT: ptrue p0.d, vl1 -; CHECK-NEXT: // kill: def $d0 killed $d0 def $z0 -; CHECK-NEXT: // kill: def $d1 killed $d1 def $z1 -; CHECK-NEXT: splice z0.d, p0, z0.d, z1.d +; CHECK-NEXT: // kill: def $d0 killed $d0 killed $z0_z1 def $z0_z1 +; CHECK-NEXT: splice z0.d, p0, { z0.d, z1.d } ; CHECK-NEXT: // kill: def $q0 killed $q0 killed $z0 ; CHECK-NEXT: ret ; diff --git a/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-fcopysign.ll b/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-fcopysign.ll index f1771a753826cc..2282e74af5d006 100644 --- a/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-fcopysign.ll +++ b/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-fcopysign.ll @@ -1,7 +1,7 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mattr=+sve -force-streaming-compatible < %s | FileCheck %s --check-prefixes=CHECK,SVE -; RUN: llc -mattr=+sve2 -force-streaming-compatible < %s | FileCheck %s --check-prefixes=CHECK,SVE2 -; RUN: llc -mattr=+sme -force-streaming < %s | FileCheck %s --check-prefixes=CHECK,SVE2 +; RUN: llc -mattr=+sve -force-streaming-compatible < %s | FileCheck %s --check-prefixes=SVE +; RUN: llc -mattr=+sve2 -force-streaming-compatible < %s | FileCheck %s --check-prefixes=SVE2 +; RUN: llc -mattr=+sme -force-streaming < %s | FileCheck %s --check-prefixes=SVE2 ; RUN: llc -force-streaming-compatible < %s | FileCheck %s --check-prefix=NONEON-NOSVE target datalayout = "e-m:o-i64:64-i128:128-n32:64-S128" @@ -842,16 +842,16 @@ define void @test_copysign_v4f32_v4f64(ptr %ap, ptr %bp) { ; ; SVE2-LABEL: test_copysign_v4f32_v4f64: ; SVE2: // %bb.0: -; SVE2-NEXT: ldp q0, q1, [x1] +; SVE2-NEXT: ldp q1, q0, [x1] ; SVE2-NEXT: ptrue p0.d -; SVE2-NEXT: ldr q2, [x0] -; SVE2-NEXT: fcvt z1.s, p0/m, z1.d ; SVE2-NEXT: fcvt z0.s, p0/m, z0.d +; SVE2-NEXT: fcvt z1.s, p0/m, z1.d ; SVE2-NEXT: ptrue p0.s, vl2 -; SVE2-NEXT: uzp1 z1.s, z1.s, z1.s -; SVE2-NEXT: uzp1 z0.s, z0.s, z0.s -; SVE2-NEXT: splice z0.s, p0, z0.s, z1.s +; SVE2-NEXT: uzp1 z3.s, z0.s, z0.s +; SVE2-NEXT: uzp1 z2.s, z1.s, z1.s ; SVE2-NEXT: mov z1.s, #0x7fffffff +; SVE2-NEXT: splice z0.s, p0, { z2.s, z3.s } +; SVE2-NEXT: ldr q2, [x0] ; SVE2-NEXT: bsl z2.d, z2.d, z0.d, z1.d ; SVE2-NEXT: str q2, [x0] ; SVE2-NEXT: ret @@ -1237,16 +1237,16 @@ define void @test_copysign_v8f16_v8f32(ptr %ap, ptr %bp) { ; ; SVE2-LABEL: test_copysign_v8f16_v8f32: ; SVE2: // %bb.0: -; SVE2-NEXT: ldp q0, q1, [x1] +; SVE2-NEXT: ldp q1, q0, [x1] ; SVE2-NEXT: ptrue p0.s -; SVE2-NEXT: ldr q2, [x0] -; SVE2-NEXT: fcvt z1.h, p0/m, z1.s ; SVE2-NEXT: fcvt z0.h, p0/m, z0.s +; SVE2-NEXT: fcvt z1.h, p0/m, z1.s ; SVE2-NEXT: ptrue p0.h, vl4 -; SVE2-NEXT: uzp1 z1.h, z1.h, z1.h -; SVE2-NEXT: uzp1 z0.h, z0.h, z0.h -; SVE2-NEXT: splice z0.h, p0, z0.h, z1.h +; SVE2-NEXT: uzp1 z3.h, z0.h, z0.h +; SVE2-NEXT: uzp1 z2.h, z1.h, z1.h ; SVE2-NEXT: mov z1.h, #32767 // =0x7fff +; SVE2-NEXT: splice z0.h, p0, { z2.h, z3.h } +; SVE2-NEXT: ldr q2, [x0] ; SVE2-NEXT: bsl z2.d, z2.d, z0.d, z1.d ; SVE2-NEXT: str q2, [x0] ; SVE2-NEXT: ret @@ -1349,5 +1349,3 @@ declare <8 x float> @llvm.copysign.v8f32(<8 x float> %a, <8 x float> %b) #0 declare <2 x double> @llvm.copysign.v2f64(<2 x double> %a, <2 x double> %b) #0 declare <4 x double> @llvm.copysign.v4f64(<4 x double> %a, <4 x double> %b) #0 -;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line: -; CHECK: {{.*}} diff --git a/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-int-div.ll b/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-int-div.ll index 516772b8ca6640..1fdcd4f8268708 100644 --- a/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-int-div.ll +++ b/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-int-div.ll @@ -1,7 +1,6 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mattr=+sve -force-streaming-compatible < %s | FileCheck %s --check-prefixes=CHECK,SVE -; RUN: llc -mattr=+sve2 -force-streaming-compatible < %s | FileCheck %s --check-prefixes=CHECK,SVE2 -; RUN: llc -mattr=+sme -force-streaming < %s | FileCheck %s --check-prefixes=CHECK,SVE2 +; RUN: llc -mattr=+sve2 -force-streaming-compatible < %s | FileCheck %s --check-prefixes=CHECK +; RUN: llc -mattr=+sme -force-streaming < %s | FileCheck %s --check-prefixes=CHECK ; RUN: llc -force-streaming-compatible < %s | FileCheck %s --check-prefix=NONEON-NOSVE target triple = "aarch64-unknown-linux-gnu" @@ -26,19 +25,6 @@ define <4 x i8> @sdiv_v4i8(<4 x i8> %op1, <4 x i8> %op2) { ; CHECK-NEXT: // kill: def $d0 killed $d0 killed $z0 ; CHECK-NEXT: ret ; -; NEON-NOSVE-LABEL: sdiv_v4i8: -; NEON-NOSVE: // %bb.0: -; NEON-NOSVE-NEXT: shl v0.4h, v0.4h, #8 -; NEON-NOSVE-NEXT: shl v1.4h, v1.4h, #8 -; NEON-NOSVE-NEXT: ptrue p0.s, vl4 -; NEON-NOSVE-NEXT: sshr v0.4h, v0.4h, #8 -; NEON-NOSVE-NEXT: sshr v1.4h, v1.4h, #8 -; NEON-NOSVE-NEXT: sshll v1.4s, v1.4h, #0 -; NEON-NOSVE-NEXT: sshll v0.4s, v0.4h, #0 -; NEON-NOSVE-NEXT: sdiv z0.s, p0/m, z0.s, z1.s -; NEON-NOSVE-NEXT: xtn v0.4h, v0.4s -; NEON-NOSVE-NEXT: ret -; ; NONEON-NOSVE-LABEL: sdiv_v4i8: ; NONEON-NOSVE: // %bb.0: ; NONEON-NOSVE-NEXT: sub sp, sp, #32 @@ -85,27 +71,12 @@ define <8 x i8> @sdiv_v8i8(<8 x i8> %op1, <8 x i8> %op2) { ; CHECK-NEXT: sdiv z0.s, p0/m, z0.s, z1.s ; CHECK-NEXT: ptrue p0.h, vl4 ; CHECK-NEXT: uzp1 z1.h, z2.h, z2.h -; CHECK-NEXT: uzp1 z0.h, z0.h, z0.h -; CHECK-NEXT: splice z1.h, p0, z1.h, z0.h -; CHECK-NEXT: uzp1 z0.b, z1.b, z1.b +; CHECK-NEXT: uzp1 z2.h, z0.h, z0.h +; CHECK-NEXT: splice z0.h, p0, { z1.h, z2.h } +; CHECK-NEXT: uzp1 z0.b, z0.b, z0.b ; CHECK-NEXT: // kill: def $d0 killed $d0 killed $z0 ; CHECK-NEXT: ret ; -; NEON-NOSVE-LABEL: sdiv_v8i8: -; NEON-NOSVE: // %bb.0: -; NEON-NOSVE-NEXT: sshll v1.8h, v1.8b, #0 -; NEON-NOSVE-NEXT: sshll v0.8h, v0.8b, #0 -; NEON-NOSVE-NEXT: ptrue p0.s, vl4 -; NEON-NOSVE-NEXT: sshll2 v2.4s, v1.8h, #0 -; NEON-NOSVE-NEXT: sshll2 v3.4s, v0.8h, #0 -; NEON-NOSVE-NEXT: sshll v1.4s, v1.4h, #0 -; NEON-NOSVE-NEXT: sshll v0.4s, v0.4h, #0 -; NEON-NOSVE-NEXT: sdivr z2.s, p0/m, z2.s, z3.s -; NEON-NOSVE-NEXT: sdiv z0.s, p0/m, z0.s, z1.s -; NEON-NOSVE-NEXT: uzp1 v0.8h, v0.8h, v2.8h -; NEON-NOSVE-NEXT: xtn v0.8b, v0.8h -; NEON-NOSVE-NEXT: ret -; ; NONEON-NOSVE-LABEL: sdiv_v8i8: ; NONEON-NOSVE: // %bb.0: ; NONEON-NOSVE-NEXT: sub sp, sp, #32 @@ -177,45 +148,21 @@ define <16 x i8> @sdiv_v16i8(<16 x i8> %op1, <16 x i8> %op2) { ; CHECK-NEXT: ext z1.b, z1.b, z1.b, #8 ; CHECK-NEXT: sunpklo z1.s, z1.h ; CHECK-NEXT: sdivr z3.s, p0/m, z3.s, z5.s -; CHECK-NEXT: uzp1 z2.h, z2.h, z2.h +; CHECK-NEXT: uzp1 z4.h, z4.h, z4.h +; CHECK-NEXT: uzp1 z5.h, z2.h, z2.h ; CHECK-NEXT: sdiv z0.s, p0/m, z0.s, z1.s -; CHECK-NEXT: uzp1 z1.h, z4.h, z4.h ; CHECK-NEXT: ptrue p0.h, vl4 -; CHECK-NEXT: uzp1 z3.h, z3.h, z3.h -; CHECK-NEXT: splice z1.h, p0, z1.h, z2.h -; CHECK-NEXT: uzp1 z0.h, z0.h, z0.h -; CHECK-NEXT: splice z3.h, p0, z3.h, z0.h -; CHECK-NEXT: uzp1 z0.b, z1.b, z1.b +; CHECK-NEXT: uzp1 z1.h, z3.h, z3.h +; CHECK-NEXT: uzp1 z2.h, z0.h, z0.h +; CHECK-NEXT: splice z0.h, p0, { z4.h, z5.h } +; CHECK-NEXT: splice z1.h, p0, { z1.h, z2.h } ; CHECK-NEXT: ptrue p0.b, vl8 -; CHECK-NEXT: uzp1 z1.b, z3.b, z3.b -; CHECK-NEXT: splice z0.b, p0, z0.b, z1.b +; CHECK-NEXT: uzp1 z2.b, z0.b, z0.b +; CHECK-NEXT: uzp1 z3.b, z1.b, z1.b +; CHECK-NEXT: splice z0.b, p0, { z2.b, z3.b } ; CHECK-NEXT: // kill: def $q0 killed $q0 killed $z0 ; CHECK-NEXT: ret ; -; NEON-NOSVE-LABEL: sdiv_v16i8: -; NEON-NOSVE: // %bb.0: -; NEON-NOSVE-NEXT: sshll2 v2.8h, v1.16b, #0 -; NEON-NOSVE-NEXT: sshll2 v3.8h, v0.16b, #0 -; NEON-NOSVE-NEXT: sshll v1.8h, v1.8b, #0 -; NEON-NOSVE-NEXT: sshll v0.8h, v0.8b, #0 -; NEON-NOSVE-NEXT: ptrue p0.s, vl4 -; NEON-NOSVE-NEXT: sshll2 v4.4s, v2.8h, #0 -; NEON-NOSVE-NEXT: sshll2 v5.4s, v3.8h, #0 -; NEON-NOSVE-NEXT: sshll v2.4s, v2.4h, #0 -; NEON-NOSVE-NEXT: sshll v3.4s, v3.4h, #0 -; NEON-NOSVE-NEXT: sdivr z4.s, p0/m, z4.s, z5.s -; NEON-NOSVE-NEXT: sshll2 v5.4s, v0.8h, #0 -; NEON-NOSVE-NEXT: sshll v0.4s, v0.4h, #0 -; NEON-NOSVE-NEXT: sdivr z2.s, p0/m, z2.s, z3.s -; NEON-NOSVE-NEXT: sshll2 v3.4s, v1.8h, #0 -; NEON-NOSVE-NEXT: sshll v1.4s, v1.4h, #0 -; NEON-NOSVE-NEXT: sdivr z3.s, p0/m, z3.s, z5.s -; NEON-NOSVE-NEXT: sdiv z0.s, p0/m, z0.s, z1.s -; NEON-NOSVE-NEXT: uzp1 v1.8h, v2.8h, v4.8h -; NEON-NOSVE-NEXT: uzp1 v0.8h, v0.8h, v3.8h -; NEON-NOSVE-NEXT: uzp1 v0.16b, v0.16b, v1.16b -; NEON-NOSVE-NEXT: ret -; ; NONEON-NOSVE-LABEL: sdiv_v16i8: ; NONEON-NOSVE: // %bb.0: ; NONEON-NOSVE-NEXT: stp q0, q1, [sp, #-48]! @@ -319,7 +266,6 @@ define void @sdiv_v32i8(ptr %a, ptr %b) { ; CHECK-NEXT: sunpklo z4.h, z2.b ; CHECK-NEXT: sunpklo z2.s, z3.h ; CHECK-NEXT: ext z3.b, z3.b, z3.b, #8 -; CHECK-NEXT: uzp1 z0.h, z0.h, z0.h ; CHECK-NEXT: sunpklo z5.s, z4.h ; CHECK-NEXT: ext z4.b, z4.b, z4.b, #8 ; CHECK-NEXT: sunpklo z3.s, z3.h @@ -328,7 +274,6 @@ define void @sdiv_v32i8(ptr %a, ptr %b) { ; CHECK-NEXT: ldr q5, [x0] ; CHECK-NEXT: sunpklo z16.h, z5.b ; CHECK-NEXT: ext z5.b, z5.b, z5.b, #8 -; CHECK-NEXT: uzp1 z1.h, z1.h, z1.h ; CHECK-NEXT: sunpklo z5.h, z5.b ; CHECK-NEXT: sunpklo z18.s, z16.h ; CHECK-NEXT: ext z16.b, z16.b, z16.b, #8 @@ -337,81 +282,36 @@ define void @sdiv_v32i8(ptr %a, ptr %b) { ; CHECK-NEXT: sunpklo z18.s, z5.h ; CHECK-NEXT: ext z5.b, z5.b, z5.b, #8 ; CHECK-NEXT: sunpklo z5.s, z5.h -; CHECK-NEXT: uzp1 z2.h, z2.h, z2.h ; CHECK-NEXT: sdivr z7.s, p0/m, z7.s, z16.s ; CHECK-NEXT: sunpklo z16.s, z6.h ; CHECK-NEXT: ext z6.b, z6.b, z6.b, #8 ; CHECK-NEXT: sunpklo z6.s, z6.h +; CHECK-NEXT: uzp1 z20.h, z17.h, z17.h ; CHECK-NEXT: sdivr z16.s, p0/m, z16.s, z18.s +; CHECK-NEXT: uzp1 z18.h, z0.h, z0.h +; CHECK-NEXT: uzp1 z19.h, z1.h, z1.h +; CHECK-NEXT: uzp1 z21.h, z7.h, z7.h ; CHECK-NEXT: sdiv z5.s, p0/m, z5.s, z6.s -; CHECK-NEXT: uzp1 z6.h, z7.h, z7.h -; CHECK-NEXT: uzp1 z7.h, z16.h, z16.h +; CHECK-NEXT: uzp1 z0.h, z16.h, z16.h ; CHECK-NEXT: sdivr z3.s, p0/m, z3.s, z4.s -; CHECK-NEXT: uzp1 z4.h, z17.h, z17.h ; CHECK-NEXT: ptrue p0.h, vl4 -; CHECK-NEXT: splice z0.h, p0, z0.h, z1.h -; CHECK-NEXT: uzp1 z5.h, z5.h, z5.h -; CHECK-NEXT: splice z4.h, p0, z4.h, z6.h -; CHECK-NEXT: splice z7.h, p0, z7.h, z5.h -; CHECK-NEXT: uzp1 z0.b, z0.b, z0.b -; CHECK-NEXT: uzp1 z1.b, z4.b, z4.b -; CHECK-NEXT: uzp1 z3.h, z3.h, z3.h -; CHECK-NEXT: splice z2.h, p0, z2.h, z3.h -; CHECK-NEXT: uzp1 z3.b, z7.b, z7.b +; CHECK-NEXT: uzp1 z1.h, z5.h, z5.h +; CHECK-NEXT: uzp1 z4.h, z2.h, z2.h +; CHECK-NEXT: splice z2.h, p0, { z20.h, z21.h } +; CHECK-NEXT: splice z0.h, p0, { z0.h, z1.h } +; CHECK-NEXT: uzp1 z5.h, z3.h, z3.h +; CHECK-NEXT: splice z3.h, p0, { z18.h, z19.h } +; CHECK-NEXT: splice z1.h, p0, { z4.h, z5.h } +; CHECK-NEXT: uzp1 z4.b, z2.b, z2.b ; CHECK-NEXT: ptrue p0.b, vl8 -; CHECK-NEXT: splice z1.b, p0, z1.b, z3.b -; CHECK-NEXT: uzp1 z2.b, z2.b, z2.b -; CHECK-NEXT: splice z0.b, p0, z0.b, z2.b -; CHECK-NEXT: stp q1, q0, [x0] +; CHECK-NEXT: uzp1 z2.b, z3.b, z3.b +; CHECK-NEXT: uzp1 z5.b, z0.b, z0.b +; CHECK-NEXT: uzp1 z3.b, z1.b, z1.b +; CHECK-NEXT: splice z0.b, p0, { z4.b, z5.b } +; CHECK-NEXT: splice z1.b, p0, { z2.b, z3.b } +; CHECK-NEXT: stp q0, q1, [x0] ; CHECK-NEXT: ret ; -; NEON-NOSVE-LABEL: sdiv_v32i8: -; NEON-NOSVE: // %bb.0: -; NEON-NOSVE-NEXT: ldp q6, q3, [x1] -; NEON-NOSVE-NEXT: ptrue p0.s, vl4 -; NEON-NOSVE-NEXT: ldr q2, [x0, #16] -; NEON-NOSVE-NEXT: sshll2 v1.8h, v3.16b, #0 -; NEON-NOSVE-NEXT: sshll2 v4.8h, v2.16b, #0 -; NEON-NOSVE-NEXT: sshll v3.8h, v3.8b, #0 -; NEON-NOSVE-NEXT: sshll v2.8h, v2.8b, #0 -; NEON-NOSVE-NEXT: sshll2 v7.8h, v6.16b, #0 -; NEON-NOSVE-NEXT: sshll v6.8h, v6.8b, #0 -; NEON-NOSVE-NEXT: sshll2 v0.4s, v1.8h, #0 -; NEON-NOSVE-NEXT: sshll2 v5.4s, v4.8h, #0 -; NEON-NOSVE-NEXT: sshll v1.4s, v1.4h, #0 -; NEON-NOSVE-NEXT: sshll v4.4s, v4.4h, #0 -; NEON-NOSVE-NEXT: sshll2 v17.4s, v7.8h, #0 -; NEON-NOSVE-NEXT: sshll v7.4s, v7.4h, #0 -; NEON-NOSVE-NEXT: sdivr z0.s, p0/m, z0.s, z5.s -; NEON-NOSVE-NEXT: sshll2 v5.4s, v2.8h, #0 -; NEON-NOSVE-NEXT: sshll v2.4s, v2.4h, #0 -; NEON-NOSVE-NEXT: sdivr z1.s, p0/m, z1.s, z4.s -; NEON-NOSVE-NEXT: sshll2 v4.4s, v3.8h, #0 -; NEON-NOSVE-NEXT: sshll v3.4s, v3.4h, #0 -; NEON-NOSVE-NEXT: sdivr z4.s, p0/m, z4.s, z5.s -; NEON-NOSVE-NEXT: ldr q5, [x0] -; NEON-NOSVE-NEXT: sshll2 v16.8h, v5.16b, #0 -; NEON-NOSVE-NEXT: sshll v5.8h, v5.8b, #0 -; NEON-NOSVE-NEXT: uzp1 v0.8h, v1.8h, v0.8h -; NEON-NOSVE-NEXT: sshll2 v18.4s, v16.8h, #0 -; NEON-NOSVE-NEXT: sshll v16.4s, v16.4h, #0 -; NEON-NOSVE-NEXT: sdivr z17.s, p0/m, z17.s, z18.s -; NEON-NOSVE-NEXT: sshll2 v18.4s, v5.8h, #0 -; NEON-NOSVE-NEXT: sshll v5.4s, v5.4h, #0 -; NEON-NOSVE-NEXT: sdivr z7.s, p0/m, z7.s, z16.s -; NEON-NOSVE-NEXT: sshll2 v16.4s, v6.8h, #0 -; NEON-NOSVE-NEXT: sshll v6.4s, v6.4h, #0 -; NEON-NOSVE-NEXT: sdivr z16.s, p0/m, z16.s, z18.s -; NEON-NOSVE-NEXT: sdiv z5.s, p0/m, z5.s, z6.s -; NEON-NOSVE-NEXT: sdiv z2.s, p0/m, z2.s, z3.s -; NEON-NOSVE-NEXT: uzp1 v3.8h, v7.8h, v17.8h -; NEON-NOSVE-NEXT: uzp1 v5.8h, v5.8h, v16.8h -; NEON-NOSVE-NEXT: uzp1 v1.8h, v2.8h, v4.8h -; NEON-NOSVE-NEXT: uzp1 v2.16b, v5.16b, v3.16b -; NEON-NOSVE-NEXT: uzp1 v0.16b, v1.16b, v0.16b -; NEON-NOSVE-NEXT: stp q2, q0, [x0] -; NEON-NOSVE-NEXT: ret -; ; NONEON-NOSVE-LABEL: sdiv_v32i8: ; NONEON-NOSVE: // %bb.0: ; NONEON-NOSVE-NEXT: sub sp, sp, #96 @@ -571,17 +471,6 @@ define <2 x i16> @sdiv_v2i16(<2 x i16> %op1, <2 x i16> %op2) { ; CHECK-NEXT: // kill: def $d0 killed $d0 killed $z0 ; CHECK-NEXT: ret ; -; NEON-NOSVE-LABEL: sdiv_v2i16: -; NEON-NOSVE: // %bb.0: -; NEON-NOSVE-NEXT: shl v1.2s, v1.2s, #16 -; NEON-NOSVE-NEXT: shl v0.2s, v0.2s, #16 -; NEON-NOSVE-NEXT: ptrue p0.s, vl2 -; NEON-NOSVE-NEXT: sshr v1.2s, v1.2s, #16 -; NEON-NOSVE-NEXT: sshr v0.2s, v0.2s, #16 -; NEON-NOSVE-NEXT: sdiv z0.s, p0/m, z0.s, z1.s -; NEON-NOSVE-NEXT: // kill: def $d0 killed $d0 killed $z0 -; NEON-NOSVE-NEXT: ret -; ; NONEON-NOSVE-LABEL: sdiv_v2i16: ; NONEON-NOSVE: // %bb.0: ; NONEON-NOSVE-NEXT: sub sp, sp, #32 @@ -614,15 +503,6 @@ define <4 x i16> @sdiv_v4i16(<4 x i16> %op1, <4 x i16> %op2) { ; CHECK-NEXT: // kill: def $d0 killed $d0 killed $z0 ; CHECK-NEXT: ret ; -; NEON-NOSVE-LABEL: sdiv_v4i16: -; NEON-NOSVE: // %bb.0: -; NEON-NOSVE-NEXT: sshll v1.4s, v1.4h, #0 -; NEON-NOSVE-NEXT: sshll v0.4s, v0.4h, #0 -; NEON-NOSVE-NEXT: ptrue p0.s, vl4 -; NEON-NOSVE-NEXT: sdiv z0.s, p0/m, z0.s, z1.s -; NEON-NOSVE-NEXT: xtn v0.4h, v0.4s -; NEON-NOSVE-NEXT: ret -; ; NONEON-NOSVE-LABEL: sdiv_v4i16: ; NONEON-NOSVE: // %bb.0: ; NONEON-NOSVE-NEXT: sub sp, sp, #32 @@ -664,26 +544,14 @@ define <8 x i16> @sdiv_v8i16(<8 x i16> %op1, <8 x i16> %op2) { ; CHECK-NEXT: sunpklo z1.s, z1.h ; CHECK-NEXT: sunpklo z0.s, z0.h ; CHECK-NEXT: sdivr z2.s, p0/m, z2.s, z3.s -; CHECK-NEXT: sdivr z1.s, p0/m, z1.s, z0.s +; CHECK-NEXT: sdiv z0.s, p0/m, z0.s, z1.s ; CHECK-NEXT: ptrue p0.h, vl4 -; CHECK-NEXT: uzp1 z0.h, z2.h, z2.h -; CHECK-NEXT: uzp1 z1.h, z1.h, z1.h -; CHECK-NEXT: splice z0.h, p0, z0.h, z1.h +; CHECK-NEXT: uzp1 z1.h, z2.h, z2.h +; CHECK-NEXT: uzp1 z2.h, z0.h, z0.h +; CHECK-NEXT: splice z0.h, p0, { z1.h, z2.h } ; CHECK-NEXT: // kill: def $q0 killed $q0 killed $z0 ; CHECK-NEXT: ret ; -; NEON-NOSVE-LABEL: sdiv_v8i16: -; NEON-NOSVE: // %bb.0: -; NEON-NOSVE-NEXT: sshll2 v2.4s, v1.8h, #0 -; NEON-NOSVE-NEXT: sshll2 v3.4s, v0.8h, #0 -; NEON-NOSVE-NEXT: sshll v1.4s, v1.4h, #0 -; NEON-NOSVE-NEXT: sshll v0.4s, v0.4h, #0 -; NEON-NOSVE-NEXT: ptrue p0.s, vl4 -; NEON-NOSVE-NEXT: sdivr z2.s, p0/m, z2.s, z3.s -; NEON-NOSVE-NEXT: sdiv z0.s, p0/m, z0.s, z1.s -; NEON-NOSVE-NEXT: uzp1 v0.8h, v0.8h, v2.8h -; NEON-NOSVE-NEXT: ret -; ; NONEON-NOSVE-LABEL: sdiv_v8i16: ; NONEON-NOSVE: // %bb.0: ; NONEON-NOSVE-NEXT: stp q0, q1, [sp, #-48]! @@ -748,41 +616,18 @@ define void @sdiv_v16i16(ptr %a, ptr %b) { ; CHECK-NEXT: ext z3.b, z3.b, z3.b, #8 ; CHECK-NEXT: sunpklo z3.s, z3.h ; CHECK-NEXT: sdivr z5.s, p0/m, z5.s, z6.s -; CHECK-NEXT: uzp1 z2.h, z2.h, z2.h ; CHECK-NEXT: sdiv z3.s, p0/m, z3.s, z4.s +; CHECK-NEXT: uzp1 z4.h, z5.h, z5.h ; CHECK-NEXT: sdiv z0.s, p0/m, z0.s, z1.s -; CHECK-NEXT: uzp1 z1.h, z5.h, z5.h +; CHECK-NEXT: uzp1 z1.h, z2.h, z2.h ; CHECK-NEXT: ptrue p0.h, vl4 -; CHECK-NEXT: uzp1 z3.h, z3.h, z3.h -; CHECK-NEXT: splice z1.h, p0, z1.h, z3.h -; CHECK-NEXT: uzp1 z0.h, z0.h, z0.h -; CHECK-NEXT: splice z2.h, p0, z2.h, z0.h -; CHECK-NEXT: stp q1, q2, [x0] +; CHECK-NEXT: uzp1 z5.h, z3.h, z3.h +; CHECK-NEXT: uzp1 z2.h, z0.h, z0.h +; CHECK-NEXT: splice z0.h, p0, { z4.h, z5.h } +; CHECK-NEXT: splice z1.h, p0, { z1.h, z2.h } +; CHECK-NEXT: stp q0, q1, [x0] ; CHECK-NEXT: ret ; -; NEON-NOSVE-LABEL: sdiv_v16i16: -; NEON-NOSVE: // %bb.0: -; NEON-NOSVE-NEXT: ldp q4, q1, [x1] -; NEON-NOSVE-NEXT: ptrue p0.s, vl4 -; NEON-NOSVE-NEXT: ldr q0, [x0, #16] -; NEON-NOSVE-NEXT: sshll2 v2.4s, v1.8h, #0 -; NEON-NOSVE-NEXT: sshll2 v3.4s, v0.8h, #0 -; NEON-NOSVE-NEXT: sshll2 v5.4s, v4.8h, #0 -; NEON-NOSVE-NEXT: sshll v4.4s, v4.4h, #0 -; NEON-NOSVE-NEXT: sshll v1.4s, v1.4h, #0 -; NEON-NOSVE-NEXT: sshll v0.4s, v0.4h, #0 -; NEON-NOSVE-NEXT: sdivr z2.s, p0/m, z2.s, z3.s -; NEON-NOSVE-NEXT: ldr q3, [x0] -; NEON-NOSVE-NEXT: sshll2 v6.4s, v3.8h, #0 -; NEON-NOSVE-NEXT: sshll v3.4s, v3.4h, #0 -; NEON-NOSVE-NEXT: sdivr z5.s, p0/m, z5.s, z6.s -; NEON-NOSVE-NEXT: sdiv z3.s, p0/m, z3.s, z4.s -; NEON-NOSVE-NEXT: sdiv z0.s, p0/m, z0.s, z1.s -; NEON-NOSVE-NEXT: uzp1 v1.8h, v3.8h, v5.8h -; NEON-NOSVE-NEXT: uzp1 v0.8h, v0.8h, v2.8h -; NEON-NOSVE-NEXT: stp q1, q0, [x0] -; NEON-NOSVE-NEXT: ret -; ; NONEON-NOSVE-LABEL: sdiv_v16i16: ; NONEON-NOSVE: // %bb.0: ; NONEON-NOSVE-NEXT: sub sp, sp, #96 @@ -876,15 +721,6 @@ define <2 x i32> @sdiv_v2i32(<2 x i32> %op1, <2 x i32> %op2) { ; CHECK-NEXT: // kill: def $d0 killed $d0 killed $z0 ; CHECK-NEXT: ret ; -; NEON-NOSVE-LABEL: sdiv_v2i32: -; NEON-NOSVE: // %bb.0: -; NEON-NOSVE-NEXT: ptrue p0.s, vl2 -; NEON-NOSVE-NEXT: // kill: def $d0 killed $d0 def $z0 -; NEON-NOSVE-NEXT: // kill: def $d1 killed $d1 def $z1 -; NEON-NOSVE-NEXT: sdiv z0.s, p0/m, z0.s, z1.s -; NEON-NOSVE-NEXT: // kill: def $d0 killed $d0 killed $z0 -; NEON-NOSVE-NEXT: ret -; ; NONEON-NOSVE-LABEL: sdiv_v2i32: ; NONEON-NOSVE: // %bb.0: ; NONEON-NOSVE-NEXT: sub sp, sp, #32 @@ -913,15 +749,6 @@ define <4 x i32> @sdiv_v4i32(<4 x i32> %op1, <4 x i32> %op2) { ; CHECK-NEXT: // kill: def $q0 killed $q0 killed $z0 ; CHECK-NEXT: ret ; -; NEON-NOSVE-LABEL: sdiv_v4i32: -; NEON-NOSVE: // %bb.0: -; NEON-NOSVE-NEXT: ptrue p0.s, vl4 -; NEON-NOSVE-NEXT: // kill: def $q0 killed $q0 def $z0 -; NEON-NOSVE-NEXT: // kill: def $q1 killed $q1 def $z1 -; NEON-NOSVE-NEXT: sdiv z0.s, p0/m, z0.s, z1.s -; NEON-NOSVE-NEXT: // kill: def $q0 killed $q0 killed $z0 -; NEON-NOSVE-NEXT: ret -; ; NONEON-NOSVE-LABEL: sdiv_v4i32: ; NONEON-NOSVE: // %bb.0: ; NONEON-NOSVE-NEXT: stp q0, q1, [sp, #-48]! @@ -957,17 +784,6 @@ define void @sdiv_v8i32(ptr %a, ptr %b) { ; CHECK-NEXT: stp q0, q1, [x0] ; CHECK-NEXT: ret ; -; NEON-NOSVE-LABEL: sdiv_v8i32: -; NEON-NOSVE: // %bb.0: -; NEON-NOSVE-NEXT: ldp q0, q3, [x1] -; NEON-NOSVE-NEXT: ptrue p0.s, vl4 -; NEON-NOSVE-NEXT: ldp q1, q2, [x0] -; NEON-NOSVE-NEXT: sdivr z0.s, p0/m, z0.s, z1.s -; NEON-NOSVE-NEXT: movprfx z1, z2 -; NEON-NOSVE-NEXT: sdiv z1.s, p0/m, z1.s, z3.s -; NEON-NOSVE-NEXT: stp q0, q1, [x0] -; NEON-NOSVE-NEXT: ret -; ; NONEON-NOSVE-LABEL: sdiv_v8i32: ; NONEON-NOSVE: // %bb.0: ; NONEON-NOSVE-NEXT: sub sp, sp, #96 @@ -1021,15 +837,6 @@ define <1 x i64> @sdiv_v1i64(<1 x i64> %op1, <1 x i64> %op2) { ; CHECK-NEXT: // kill: def $d0 killed $d0 killed $z0 ; CHECK-NEXT: ret ; -; NEON-NOSVE-LABEL: sdiv_v1i64: -; NEON-NOSVE: // %bb.0: -; NEON-NOSVE-NEXT: ptrue p0.d, vl1 -; NEON-NOSVE-NEXT: // kill: def $d0 killed $d0 def $z0 -; NEON-NOSVE-NEXT: // kill: def $d1 killed $d1 def $z1 -; NEON-NOSVE-NEXT: sdiv z0.d, p0/m, z0.d, z1.d -; NEON-NOSVE-NEXT: // kill: def $d0 killed $d0 killed $z0 -; NEON-NOSVE-NEXT: ret -; ; NONEON-NOSVE-LABEL: sdiv_v1i64: ; NONEON-NOSVE: // %bb.0: ; NONEON-NOSVE-NEXT: sub sp, sp, #16 @@ -1055,15 +862,6 @@ define <2 x i64> @sdiv_v2i64(<2 x i64> %op1, <2 x i64> %op2) { ; CHECK-NEXT: // kill: def $q0 killed $q0 killed $z0 ; CHECK-NEXT: ret ; -; NEON-NOSVE-LABEL: sdiv_v2i64: -; NEON-NOSVE: // %bb.0: -; NEON-NOSVE-NEXT: ptrue p0.d, vl2 -; NEON-NOSVE-NEXT: // kill: def $q0 killed $q0 def $z0 -; NEON-NOSVE-NEXT: // kill: def $q1 killed $q1 def $z1 -; NEON-NOSVE-NEXT: sdiv z0.d, p0/m, z0.d, z1.d -; NEON-NOSVE-NEXT: // kill: def $q0 killed $q0 killed $z0 -; NEON-NOSVE-NEXT: ret -; ; NONEON-NOSVE-LABEL: sdiv_v2i64: ; NONEON-NOSVE: // %bb.0: ; NONEON-NOSVE-NEXT: stp q0, q1, [sp, #-48]! @@ -1093,17 +891,6 @@ define void @sdiv_v4i64(ptr %a, ptr %b) { ; CHECK-NEXT: stp q0, q1, [x0] ; CHECK-NEXT: ret ; -; NEON-NOSVE-LABEL: sdiv_v4i64: -; NEON-NOSVE: // %bb.0: -; NEON-NOSVE-NEXT: ldp q0, q3, [x1] -; NEON-NOSVE-NEXT: ptrue p0.d, vl2 -; NEON-NOSVE-NEXT: ldp q1, q2, [x0] -; NEON-NOSVE-NEXT: sdivr z0.d, p0/m, z0.d, z1.d -; NEON-NOSVE-NEXT: movprfx z1, z2 -; NEON-NOSVE-NEXT: sdiv z1.d, p0/m, z1.d, z3.d -; NEON-NOSVE-NEXT: stp q0, q1, [x0] -; NEON-NOSVE-NEXT: ret -; ; NONEON-NOSVE-LABEL: sdiv_v4i64: ; NONEON-NOSVE: // %bb.0: ; NONEON-NOSVE-NEXT: sub sp, sp, #96 @@ -1135,9 +922,7 @@ define void @sdiv_v4i64(ptr %a, ptr %b) { ret void } -; ; UDIV -; define <4 x i8> @udiv_v4i8(<4 x i8> %op1, <4 x i8> %op2) { ; CHECK-LABEL: udiv_v4i8: @@ -1154,17 +939,6 @@ define <4 x i8> @udiv_v4i8(<4 x i8> %op1, <4 x i8> %op2) { ; CHECK-NEXT: // kill: def $d0 killed $d0 killed $z0 ; CHECK-NEXT: ret ; -; NEON-NOSVE-LABEL: udiv_v4i8: -; NEON-NOSVE: // %bb.0: -; NEON-NOSVE-NEXT: bic v0.4h, #255, lsl #8 -; NEON-NOSVE-NEXT: bic v1.4h, #255, lsl #8 -; NEON-NOSVE-NEXT: ptrue p0.s, vl4 -; NEON-NOSVE-NEXT: ushll v1.4s, v1.4h, #0 -; NEON-NOSVE-NEXT: ushll v0.4s, v0.4h, #0 -; NEON-NOSVE-NEXT: udiv z0.s, p0/m, z0.s, z1.s -; NEON-NOSVE-NEXT: xtn v0.4h, v0.4s -; NEON-NOSVE-NEXT: ret -; ; NONEON-NOSVE-LABEL: udiv_v4i8: ; NONEON-NOSVE: // %bb.0: ; NONEON-NOSVE-NEXT: sub sp, sp, #32 @@ -1211,27 +985,12 @@ define <8 x i8> @udiv_v8i8(<8 x i8> %op1, <8 x i8> %op2) { ; CHECK-NEXT: udiv z0.s, p0/m, z0.s, z1.s ; CHECK-NEXT: ptrue p0.h, vl4 ; CHECK-NEXT: uzp1 z1.h, z2.h, z2.h -; CHECK-NEXT: uzp1 z0.h, z0.h, z0.h -; CHECK-NEXT: splice z1.h, p0, z1.h, z0.h -; CHECK-NEXT: uzp1 z0.b, z1.b, z1.b +; CHECK-NEXT: uzp1 z2.h, z0.h, z0.h +; CHECK-NEXT: splice z0.h, p0, { z1.h, z2.h } +; CHECK-NEXT: uzp1 z0.b, z0.b, z0.b ; CHECK-NEXT: // kill: def $d0 killed $d0 killed $z0 ; CHECK-NEXT: ret ; -; NEON-NOSVE-LABEL: udiv_v8i8: -; NEON-NOSVE: // %bb.0: -; NEON-NOSVE-NEXT: ushll v1.8h, v1.8b, #0 -; NEON-NOSVE-NEXT: ushll v0.8h, v0.8b, #0 -; NEON-NOSVE-NEXT: ptrue p0.s, vl4 -; NEON-NOSVE-NEXT: ushll2 v2.4s, v1.8h, #0 -; NEON-NOSVE-NEXT: ushll2 v3.4s, v0.8h, #0 -; NEON-NOSVE-NEXT: ushll v1.4s, v1.4h, #0 -; NEON-NOSVE-NEXT: ushll v0.4s, v0.4h, #0 -; NEON-NOSVE-NEXT: udivr z2.s, p0/m, z2.s, z3.s -; NEON-NOSVE-NEXT: udiv z0.s, p0/m, z0.s, z1.s -; NEON-NOSVE-NEXT: uzp1 v0.8h, v0.8h, v2.8h -; NEON-NOSVE-NEXT: xtn v0.8b, v0.8h -; NEON-NOSVE-NEXT: ret -; ; NONEON-NOSVE-LABEL: udiv_v8i8: ; NONEON-NOSVE: // %bb.0: ; NONEON-NOSVE-NEXT: sub sp, sp, #32 @@ -1303,45 +1062,21 @@ define <16 x i8> @udiv_v16i8(<16 x i8> %op1, <16 x i8> %op2) { ; CHECK-NEXT: ext z1.b, z1.b, z1.b, #8 ; CHECK-NEXT: uunpklo z1.s, z1.h ; CHECK-NEXT: udivr z3.s, p0/m, z3.s, z5.s -; CHECK-NEXT: uzp1 z2.h, z2.h, z2.h +; CHECK-NEXT: uzp1 z4.h, z4.h, z4.h +; CHECK-NEXT: uzp1 z5.h, z2.h, z2.h ; CHECK-NEXT: udiv z0.s, p0/m, z0.s, z1.s -; CHECK-NEXT: uzp1 z1.h, z4.h, z4.h ; CHECK-NEXT: ptrue p0.h, vl4 -; CHECK-NEXT: uzp1 z3.h, z3.h, z3.h -; CHECK-NEXT: splice z1.h, p0, z1.h, z2.h -; CHECK-NEXT: uzp1 z0.h, z0.h, z0.h -; CHECK-NEXT: splice z3.h, p0, z3.h, z0.h -; CHECK-NEXT: uzp1 z0.b, z1.b, z1.b +; CHECK-NEXT: uzp1 z1.h, z3.h, z3.h +; CHECK-NEXT: uzp1 z2.h, z0.h, z0.h +; CHECK-NEXT: splice z0.h, p0, { z4.h, z5.h } +; CHECK-NEXT: splice z1.h, p0, { z1.h, z2.h } ; CHECK-NEXT: ptrue p0.b, vl8 -; CHECK-NEXT: uzp1 z1.b, z3.b, z3.b -; CHECK-NEXT: splice z0.b, p0, z0.b, z1.b +; CHECK-NEXT: uzp1 z2.b, z0.b, z0.b +; CHECK-NEXT: uzp1 z3.b, z1.b, z1.b +; CHECK-NEXT: splice z0.b, p0, { z2.b, z3.b } ; CHECK-NEXT: // kill: def $q0 killed $q0 killed $z0 ; CHECK-NEXT: ret ; -; NEON-NOSVE-LABEL: udiv_v16i8: -; NEON-NOSVE: // %bb.0: -; NEON-NOSVE-NEXT: ushll2 v2.8h, v1.16b, #0 -; NEON-NOSVE-NEXT: ushll2 v3.8h, v0.16b, #0 -; NEON-NOSVE-NEXT: ushll v1.8h, v1.8b, #0 -; NEON-NOSVE-NEXT: ushll v0.8h, v0.8b, #0 -; NEON-NOSVE-NEXT: ptrue p0.s, vl4 -; NEON-NOSVE-NEXT: ushll2 v4.4s, v2.8h, #0 -; NEON-NOSVE-NEXT: ushll2 v5.4s, v3.8h, #0 -; NEON-NOSVE-NEXT: ushll v2.4s, v2.4h, #0 -; NEON-NOSVE-NEXT: ushll v3.4s, v3.4h, #0 -; NEON-NOSVE-NEXT: udivr z4.s, p0/m, z4.s, z5.s -; NEON-NOSVE-NEXT: ushll2 v5.4s, v0.8h, #0 -; NEON-NOSVE-NEXT: ushll v0.4s, v0.4h, #0 -; NEON-NOSVE-NEXT: udivr z2.s, p0/m, z2.s, z3.s -; NEON-NOSVE-NEXT: ushll2 v3.4s, v1.8h, #0 -; NEON-NOSVE-NEXT: ushll v1.4s, v1.4h, #0 -; NEON-NOSVE-NEXT: udivr z3.s, p0/m, z3.s, z5.s -; NEON-NOSVE-NEXT: udiv z0.s, p0/m, z0.s, z1.s -; NEON-NOSVE-NEXT: uzp1 v1.8h, v2.8h, v4.8h -; NEON-NOSVE-NEXT: uzp1 v0.8h, v0.8h, v3.8h -; NEON-NOSVE-NEXT: uzp1 v0.16b, v0.16b, v1.16b -; NEON-NOSVE-NEXT: ret -; ; NONEON-NOSVE-LABEL: udiv_v16i8: ; NONEON-NOSVE: // %bb.0: ; NONEON-NOSVE-NEXT: stp q0, q1, [sp, #-48]! @@ -1445,7 +1180,6 @@ define void @udiv_v32i8(ptr %a, ptr %b) { ; CHECK-NEXT: uunpklo z4.h, z2.b ; CHECK-NEXT: uunpklo z2.s, z3.h ; CHECK-NEXT: ext z3.b, z3.b, z3.b, #8 -; CHECK-NEXT: uzp1 z0.h, z0.h, z0.h ; CHECK-NEXT: uunpklo z5.s, z4.h ; CHECK-NEXT: ext z4.b, z4.b, z4.b, #8 ; CHECK-NEXT: uunpklo z3.s, z3.h @@ -1454,7 +1188,6 @@ define void @udiv_v32i8(ptr %a, ptr %b) { ; CHECK-NEXT: ldr q5, [x0] ; CHECK-NEXT: uunpklo z16.h, z5.b ; CHECK-NEXT: ext z5.b, z5.b, z5.b, #8 -; CHECK-NEXT: uzp1 z1.h, z1.h, z1.h ; CHECK-NEXT: uunpklo z5.h, z5.b ; CHECK-NEXT: uunpklo z18.s, z16.h ; CHECK-NEXT: ext z16.b, z16.b, z16.b, #8 @@ -1463,81 +1196,36 @@ define void @udiv_v32i8(ptr %a, ptr %b) { ; CHECK-NEXT: uunpklo z18.s, z5.h ; CHECK-NEXT: ext z5.b, z5.b, z5.b, #8 ; CHECK-NEXT: uunpklo z5.s, z5.h -; CHECK-NEXT: uzp1 z2.h, z2.h, z2.h ; CHECK-NEXT: udivr z7.s, p0/m, z7.s, z16.s ; CHECK-NEXT: uunpklo z16.s, z6.h ; CHECK-NEXT: ext z6.b, z6.b, z6.b, #8 ; CHECK-NEXT: uunpklo z6.s, z6.h +; CHECK-NEXT: uzp1 z20.h, z17.h, z17.h ; CHECK-NEXT: udivr z16.s, p0/m, z16.s, z18.s +; CHECK-NEXT: uzp1 z18.h, z0.h, z0.h +; CHECK-NEXT: uzp1 z19.h, z1.h, z1.h +; CHECK-NEXT: uzp1 z21.h, z7.h, z7.h ; CHECK-NEXT: udiv z5.s, p0/m, z5.s, z6.s -; CHECK-NEXT: uzp1 z6.h, z7.h, z7.h -; CHECK-NEXT: uzp1 z7.h, z16.h, z16.h +; CHECK-NEXT: uzp1 z0.h, z16.h, z16.h ; CHECK-NEXT: udivr z3.s, p0/m, z3.s, z4.s -; CHECK-NEXT: uzp1 z4.h, z17.h, z17.h ; CHECK-NEXT: ptrue p0.h, vl4 -; CHECK-NEXT: splice z0.h, p0, z0.h, z1.h -; CHECK-NEXT: uzp1 z5.h, z5.h, z5.h -; CHECK-NEXT: splice z4.h, p0, z4.h, z6.h -; CHECK-NEXT: splice z7.h, p0, z7.h, z5.h -; CHECK-NEXT: uzp1 z0.b, z0.b, z0.b -; CHECK-NEXT: uzp1 z1.b, z4.b, z4.b -; CHECK-NEXT: uzp1 z3.h, z3.h, z3.h -; CHECK-NEXT: splice z2.h, p0, z2.h, z3.h -; CHECK-NEXT: uzp1 z3.b, z7.b, z7.b +; CHECK-NEXT: uzp1 z1.h, z5.h, z5.h +; CHECK-NEXT: uzp1 z4.h, z2.h, z2.h +; CHECK-NEXT: splice z2.h, p0, { z20.h, z21.h } +; CHECK-NEXT: splice z0.h, p0, { z0.h, z1.h } +; CHECK-NEXT: uzp1 z5.h, z3.h, z3.h +; CHECK-NEXT: splice z3.h, p0, { z18.h, z19.h } +; CHECK-NEXT: splice z1.h, p0, { z4.h, z5.h } +; CHECK-NEXT: uzp1 z4.b, z2.b, z2.b ; CHECK-NEXT: ptrue p0.b, vl8 -; CHECK-NEXT: splice z1.b, p0, z1.b, z3.b -; CHECK-NEXT: uzp1 z2.b, z2.b, z2.b -; CHECK-NEXT: splice z0.b, p0, z0.b, z2.b -; CHECK-NEXT: stp q1, q0, [x0] +; CHECK-NEXT: uzp1 z2.b, z3.b, z3.b +; CHECK-NEXT: uzp1 z5.b, z0.b, z0.b +; CHECK-NEXT: uzp1 z3.b, z1.b, z1.b +; CHECK-NEXT: splice z0.b, p0, { z4.b, z5.b } +; CHECK-NEXT: splice z1.b, p0, { z2.b, z3.b } +; CHECK-NEXT: stp q0, q1, [x0] ; CHECK-NEXT: ret ; -; NEON-NOSVE-LABEL: udiv_v32i8: -; NEON-NOSVE: // %bb.0: -; NEON-NOSVE-NEXT: ldp q6, q3, [x1] -; NEON-NOSVE-NEXT: ptrue p0.s, vl4 -; NEON-NOSVE-NEXT: ldr q2, [x0, #16] -; NEON-NOSVE-NEXT: ushll2 v1.8h, v3.16b, #0 -; NEON-NOSVE-NEXT: ushll2 v4.8h, v2.16b, #0 -; NEON-NOSVE-NEXT: ushll v3.8h, v3.8b, #0 -; NEON-NOSVE-NEXT: ushll v2.8h, v2.8b, #0 -; NEON-NOSVE-NEXT: ushll2 v7.8h, v6.16b, #0 -; NEON-NOSVE-NEXT: ushll v6.8h, v6.8b, #0 -; NEON-NOSVE-NEXT: ushll2 v0.4s, v1.8h, #0 -; NEON-NOSVE-NEXT: ushll2 v5.4s, v4.8h, #0 -; NEON-NOSVE-NEXT: ushll v1.4s, v1.4h, #0 -; NEON-NOSVE-NEXT: ushll v4.4s, v4.4h, #0 -; NEON-NOSVE-NEXT: ushll2 v17.4s, v7.8h, #0 -; NEON-NOSVE-NEXT: ushll v7.4s, v7.4h, #0 -; NEON-NOSVE-NEXT: udivr z0.s, p0/m, z0.s, z5.s -; NEON-NOSVE-NEXT: ushll2 v5.4s, v2.8h, #0 -; NEON-NOSVE-NEXT: ushll v2.4s, v2.4h, #0 -; NEON-NOSVE-NEXT: udivr z1.s, p0/m, z1.s, z4.s -; NEON-NOSVE-NEXT: ushll2 v4.4s, v3.8h, #0 -; NEON-NOSVE-NEXT: ushll v3.4s, v3.4h, #0 -; NEON-NOSVE-NEXT: udivr z4.s, p0/m, z4.s, z5.s -; NEON-NOSVE-NEXT: ldr q5, [x0] -; NEON-NOSVE-NEXT: ushll2 v16.8h, v5.16b, #0 -; NEON-NOSVE-NEXT: ushll v5.8h, v5.8b, #0 -; NEON-NOSVE-NEXT: uzp1 v0.8h, v1.8h, v0.8h -; NEON-NOSVE-NEXT: ushll2 v18.4s, v16.8h, #0 -; NEON-NOSVE-NEXT: ushll v16.4s, v16.4h, #0 -; NEON-NOSVE-NEXT: udivr z17.s, p0/m, z17.s, z18.s -; NEON-NOSVE-NEXT: ushll2 v18.4s, v5.8h, #0 -; NEON-NOSVE-NEXT: ushll v5.4s, v5.4h, #0 -; NEON-NOSVE-NEXT: udivr z7.s, p0/m, z7.s, z16.s -; NEON-NOSVE-NEXT: ushll2 v16.4s, v6.8h, #0 -; NEON-NOSVE-NEXT: ushll v6.4s, v6.4h, #0 -; NEON-NOSVE-NEXT: udivr z16.s, p0/m, z16.s, z18.s -; NEON-NOSVE-NEXT: udiv z5.s, p0/m, z5.s, z6.s -; NEON-NOSVE-NEXT: udiv z2.s, p0/m, z2.s, z3.s -; NEON-NOSVE-NEXT: uzp1 v3.8h, v7.8h, v17.8h -; NEON-NOSVE-NEXT: uzp1 v5.8h, v5.8h, v16.8h -; NEON-NOSVE-NEXT: uzp1 v1.8h, v2.8h, v4.8h -; NEON-NOSVE-NEXT: uzp1 v2.16b, v5.16b, v3.16b -; NEON-NOSVE-NEXT: uzp1 v0.16b, v1.16b, v0.16b -; NEON-NOSVE-NEXT: stp q2, q0, [x0] -; NEON-NOSVE-NEXT: ret -; ; NONEON-NOSVE-LABEL: udiv_v32i8: ; NONEON-NOSVE: // %bb.0: ; NONEON-NOSVE-NEXT: sub sp, sp, #96 @@ -1697,16 +1385,6 @@ define <2 x i16> @udiv_v2i16(<2 x i16> %op1, <2 x i16> %op2) { ; CHECK-NEXT: // kill: def $d0 killed $d0 killed $z0 ; CHECK-NEXT: ret ; -; NEON-NOSVE-LABEL: udiv_v2i16: -; NEON-NOSVE: // %bb.0: -; NEON-NOSVE-NEXT: movi d2, #0x00ffff0000ffff -; NEON-NOSVE-NEXT: ptrue p0.s, vl2 -; NEON-NOSVE-NEXT: and v1.8b, v1.8b, v2.8b -; NEON-NOSVE-NEXT: and v0.8b, v0.8b, v2.8b -; NEON-NOSVE-NEXT: udiv z0.s, p0/m, z0.s, z1.s -; NEON-NOSVE-NEXT: // kill: def $d0 killed $d0 killed $z0 -; NEON-NOSVE-NEXT: ret -; ; NONEON-NOSVE-LABEL: udiv_v2i16: ; NONEON-NOSVE: // %bb.0: ; NONEON-NOSVE-NEXT: sub sp, sp, #32 @@ -1739,15 +1417,6 @@ define <4 x i16> @udiv_v4i16(<4 x i16> %op1, <4 x i16> %op2) { ; CHECK-NEXT: // kill: def $d0 killed $d0 killed $z0 ; CHECK-NEXT: ret ; -; NEON-NOSVE-LABEL: udiv_v4i16: -; NEON-NOSVE: // %bb.0: -; NEON-NOSVE-NEXT: ushll v1.4s, v1.4h, #0 -; NEON-NOSVE-NEXT: ushll v0.4s, v0.4h, #0 -; NEON-NOSVE-NEXT: ptrue p0.s, vl4 -; NEON-NOSVE-NEXT: udiv z0.s, p0/m, z0.s, z1.s -; NEON-NOSVE-NEXT: xtn v0.4h, v0.4s -; NEON-NOSVE-NEXT: ret -; ; NONEON-NOSVE-LABEL: udiv_v4i16: ; NONEON-NOSVE: // %bb.0: ; NONEON-NOSVE-NEXT: sub sp, sp, #32 @@ -1789,26 +1458,14 @@ define <8 x i16> @udiv_v8i16(<8 x i16> %op1, <8 x i16> %op2) { ; CHECK-NEXT: uunpklo z1.s, z1.h ; CHECK-NEXT: uunpklo z0.s, z0.h ; CHECK-NEXT: udivr z2.s, p0/m, z2.s, z3.s -; CHECK-NEXT: udivr z1.s, p0/m, z1.s, z0.s +; CHECK-NEXT: udiv z0.s, p0/m, z0.s, z1.s ; CHECK-NEXT: ptrue p0.h, vl4 -; CHECK-NEXT: uzp1 z0.h, z2.h, z2.h -; CHECK-NEXT: uzp1 z1.h, z1.h, z1.h -; CHECK-NEXT: splice z0.h, p0, z0.h, z1.h +; CHECK-NEXT: uzp1 z1.h, z2.h, z2.h +; CHECK-NEXT: uzp1 z2.h, z0.h, z0.h +; CHECK-NEXT: splice z0.h, p0, { z1.h, z2.h } ; CHECK-NEXT: // kill: def $q0 killed $q0 killed $z0 ; CHECK-NEXT: ret ; -; NEON-NOSVE-LABEL: udiv_v8i16: -; NEON-NOSVE: // %bb.0: -; NEON-NOSVE-NEXT: ushll2 v2.4s, v1.8h, #0 -; NEON-NOSVE-NEXT: ushll2 v3.4s, v0.8h, #0 -; NEON-NOSVE-NEXT: ushll v1.4s, v1.4h, #0 -; NEON-NOSVE-NEXT: ushll v0.4s, v0.4h, #0 -; NEON-NOSVE-NEXT: ptrue p0.s, vl4 -; NEON-NOSVE-NEXT: udivr z2.s, p0/m, z2.s, z3.s -; NEON-NOSVE-NEXT: udiv z0.s, p0/m, z0.s, z1.s -; NEON-NOSVE-NEXT: uzp1 v0.8h, v0.8h, v2.8h -; NEON-NOSVE-NEXT: ret -; ; NONEON-NOSVE-LABEL: udiv_v8i16: ; NONEON-NOSVE: // %bb.0: ; NONEON-NOSVE-NEXT: stp q0, q1, [sp, #-48]! @@ -1873,41 +1530,18 @@ define void @udiv_v16i16(ptr %a, ptr %b) { ; CHECK-NEXT: ext z3.b, z3.b, z3.b, #8 ; CHECK-NEXT: uunpklo z3.s, z3.h ; CHECK-NEXT: udivr z5.s, p0/m, z5.s, z6.s -; CHECK-NEXT: uzp1 z2.h, z2.h, z2.h ; CHECK-NEXT: udiv z3.s, p0/m, z3.s, z4.s +; CHECK-NEXT: uzp1 z4.h, z5.h, z5.h ; CHECK-NEXT: udiv z0.s, p0/m, z0.s, z1.s -; CHECK-NEXT: uzp1 z1.h, z5.h, z5.h +; CHECK-NEXT: uzp1 z1.h, z2.h, z2.h ; CHECK-NEXT: ptrue p0.h, vl4 -; CHECK-NEXT: uzp1 z3.h, z3.h, z3.h -; CHECK-NEXT: splice z1.h, p0, z1.h, z3.h -; CHECK-NEXT: uzp1 z0.h, z0.h, z0.h -; CHECK-NEXT: splice z2.h, p0, z2.h, z0.h -; CHECK-NEXT: stp q1, q2, [x0] +; CHECK-NEXT: uzp1 z5.h, z3.h, z3.h +; CHECK-NEXT: uzp1 z2.h, z0.h, z0.h +; CHECK-NEXT: splice z0.h, p0, { z4.h, z5.h } +; CHECK-NEXT: splice z1.h, p0, { z1.h, z2.h } +; CHECK-NEXT: stp q0, q1, [x0] ; CHECK-NEXT: ret ; -; NEON-NOSVE-LABEL: udiv_v16i16: -; NEON-NOSVE: // %bb.0: -; NEON-NOSVE-NEXT: ldp q4, q1, [x1] -; NEON-NOSVE-NEXT: ptrue p0.s, vl4 -; NEON-NOSVE-NEXT: ldr q0, [x0, #16] -; NEON-NOSVE-NEXT: ushll2 v2.4s, v1.8h, #0 -; NEON-NOSVE-NEXT: ushll2 v3.4s, v0.8h, #0 -; NEON-NOSVE-NEXT: ushll2 v5.4s, v4.8h, #0 -; NEON-NOSVE-NEXT: ushll v4.4s, v4.4h, #0 -; NEON-NOSVE-NEXT: ushll v1.4s, v1.4h, #0 -; NEON-NOSVE-NEXT: ushll v0.4s, v0.4h, #0 -; NEON-NOSVE-NEXT: udivr z2.s, p0/m, z2.s, z3.s -; NEON-NOSVE-NEXT: ldr q3, [x0] -; NEON-NOSVE-NEXT: ushll2 v6.4s, v3.8h, #0 -; NEON-NOSVE-NEXT: ushll v3.4s, v3.4h, #0 -; NEON-NOSVE-NEXT: udivr z5.s, p0/m, z5.s, z6.s -; NEON-NOSVE-NEXT: udiv z3.s, p0/m, z3.s, z4.s -; NEON-NOSVE-NEXT: udiv z0.s, p0/m, z0.s, z1.s -; NEON-NOSVE-NEXT: uzp1 v1.8h, v3.8h, v5.8h -; NEON-NOSVE-NEXT: uzp1 v0.8h, v0.8h, v2.8h -; NEON-NOSVE-NEXT: stp q1, q0, [x0] -; NEON-NOSVE-NEXT: ret -; ; NONEON-NOSVE-LABEL: udiv_v16i16: ; NONEON-NOSVE: // %bb.0: ; NONEON-NOSVE-NEXT: sub sp, sp, #96 @@ -2001,15 +1635,6 @@ define <2 x i32> @udiv_v2i32(<2 x i32> %op1, <2 x i32> %op2) { ; CHECK-NEXT: // kill: def $d0 killed $d0 killed $z0 ; CHECK-NEXT: ret ; -; NEON-NOSVE-LABEL: udiv_v2i32: -; NEON-NOSVE: // %bb.0: -; NEON-NOSVE-NEXT: ptrue p0.s, vl2 -; NEON-NOSVE-NEXT: // kill: def $d0 killed $d0 def $z0 -; NEON-NOSVE-NEXT: // kill: def $d1 killed $d1 def $z1 -; NEON-NOSVE-NEXT: udiv z0.s, p0/m, z0.s, z1.s -; NEON-NOSVE-NEXT: // kill: def $d0 killed $d0 killed $z0 -; NEON-NOSVE-NEXT: ret -; ; NONEON-NOSVE-LABEL: udiv_v2i32: ; NONEON-NOSVE: // %bb.0: ; NONEON-NOSVE-NEXT: sub sp, sp, #32 @@ -2038,15 +1663,6 @@ define <4 x i32> @udiv_v4i32(<4 x i32> %op1, <4 x i32> %op2) { ; CHECK-NEXT: // kill: def $q0 killed $q0 killed $z0 ; CHECK-NEXT: ret ; -; NEON-NOSVE-LABEL: udiv_v4i32: -; NEON-NOSVE: // %bb.0: -; NEON-NOSVE-NEXT: ptrue p0.s, vl4 -; NEON-NOSVE-NEXT: // kill: def $q0 killed $q0 def $z0 -; NEON-NOSVE-NEXT: // kill: def $q1 killed $q1 def $z1 -; NEON-NOSVE-NEXT: udiv z0.s, p0/m, z0.s, z1.s -; NEON-NOSVE-NEXT: // kill: def $q0 killed $q0 killed $z0 -; NEON-NOSVE-NEXT: ret -; ; NONEON-NOSVE-LABEL: udiv_v4i32: ; NONEON-NOSVE: // %bb.0: ; NONEON-NOSVE-NEXT: stp q0, q1, [sp, #-48]! @@ -2082,17 +1698,6 @@ define void @udiv_v8i32(ptr %a, ptr %b) { ; CHECK-NEXT: stp q0, q1, [x0] ; CHECK-NEXT: ret ; -; NEON-NOSVE-LABEL: udiv_v8i32: -; NEON-NOSVE: // %bb.0: -; NEON-NOSVE-NEXT: ldp q0, q3, [x1] -; NEON-NOSVE-NEXT: ptrue p0.s, vl4 -; NEON-NOSVE-NEXT: ldp q1, q2, [x0] -; NEON-NOSVE-NEXT: udivr z0.s, p0/m, z0.s, z1.s -; NEON-NOSVE-NEXT: movprfx z1, z2 -; NEON-NOSVE-NEXT: udiv z1.s, p0/m, z1.s, z3.s -; NEON-NOSVE-NEXT: stp q0, q1, [x0] -; NEON-NOSVE-NEXT: ret -; ; NONEON-NOSVE-LABEL: udiv_v8i32: ; NONEON-NOSVE: // %bb.0: ; NONEON-NOSVE-NEXT: sub sp, sp, #96 @@ -2146,15 +1751,6 @@ define <1 x i64> @udiv_v1i64(<1 x i64> %op1, <1 x i64> %op2) { ; CHECK-NEXT: // kill: def $d0 killed $d0 killed $z0 ; CHECK-NEXT: ret ; -; NEON-NOSVE-LABEL: udiv_v1i64: -; NEON-NOSVE: // %bb.0: -; NEON-NOSVE-NEXT: ptrue p0.d, vl1 -; NEON-NOSVE-NEXT: // kill: def $d0 killed $d0 def $z0 -; NEON-NOSVE-NEXT: // kill: def $d1 killed $d1 def $z1 -; NEON-NOSVE-NEXT: udiv z0.d, p0/m, z0.d, z1.d -; NEON-NOSVE-NEXT: // kill: def $d0 killed $d0 killed $z0 -; NEON-NOSVE-NEXT: ret -; ; NONEON-NOSVE-LABEL: udiv_v1i64: ; NONEON-NOSVE: // %bb.0: ; NONEON-NOSVE-NEXT: sub sp, sp, #16 @@ -2180,15 +1776,6 @@ define <2 x i64> @udiv_v2i64(<2 x i64> %op1, <2 x i64> %op2) { ; CHECK-NEXT: // kill: def $q0 killed $q0 killed $z0 ; CHECK-NEXT: ret ; -; NEON-NOSVE-LABEL: udiv_v2i64: -; NEON-NOSVE: // %bb.0: -; NEON-NOSVE-NEXT: ptrue p0.d, vl2 -; NEON-NOSVE-NEXT: // kill: def $q0 killed $q0 def $z0 -; NEON-NOSVE-NEXT: // kill: def $q1 killed $q1 def $z1 -; NEON-NOSVE-NEXT: udiv z0.d, p0/m, z0.d, z1.d -; NEON-NOSVE-NEXT: // kill: def $q0 killed $q0 killed $z0 -; NEON-NOSVE-NEXT: ret -; ; NONEON-NOSVE-LABEL: udiv_v2i64: ; NONEON-NOSVE: // %bb.0: ; NONEON-NOSVE-NEXT: stp q0, q1, [sp, #-48]! @@ -2218,17 +1805,6 @@ define void @udiv_v4i64(ptr %a, ptr %b) { ; CHECK-NEXT: stp q0, q1, [x0] ; CHECK-NEXT: ret ; -; NEON-NOSVE-LABEL: udiv_v4i64: -; NEON-NOSVE: // %bb.0: -; NEON-NOSVE-NEXT: ldp q0, q3, [x1] -; NEON-NOSVE-NEXT: ptrue p0.d, vl2 -; NEON-NOSVE-NEXT: ldp q1, q2, [x0] -; NEON-NOSVE-NEXT: udivr z0.d, p0/m, z0.d, z1.d -; NEON-NOSVE-NEXT: movprfx z1, z2 -; NEON-NOSVE-NEXT: udiv z1.d, p0/m, z1.d, z3.d -; NEON-NOSVE-NEXT: stp q0, q1, [x0] -; NEON-NOSVE-NEXT: ret -; ; NONEON-NOSVE-LABEL: udiv_v4i64: ; NONEON-NOSVE: // %bb.0: ; NONEON-NOSVE-NEXT: sub sp, sp, #96 @@ -2261,64 +1837,22 @@ define void @udiv_v4i64(ptr %a, ptr %b) { } define void @udiv_constantsplat_v8i32(ptr %a) { -; SVE-LABEL: udiv_constantsplat_v8i32: -; SVE: // %bb.0: -; SVE-NEXT: mov w8, #8969 // =0x2309 -; SVE-NEXT: ldp q1, q2, [x0] -; SVE-NEXT: movk w8, #22765, lsl #16 -; SVE-NEXT: ptrue p0.s, vl4 -; SVE-NEXT: mov z0.s, w8 -; SVE-NEXT: movprfx z3, z1 -; SVE-NEXT: umulh z3.s, p0/m, z3.s, z0.s -; SVE-NEXT: umulh z0.s, p0/m, z0.s, z2.s -; SVE-NEXT: sub z1.s, z1.s, z3.s -; SVE-NEXT: sub z2.s, z2.s, z0.s -; SVE-NEXT: lsr z1.s, z1.s, #1 -; SVE-NEXT: lsr z2.s, z2.s, #1 -; SVE-NEXT: add z1.s, z1.s, z3.s -; SVE-NEXT: add z0.s, z2.s, z0.s -; SVE-NEXT: lsr z1.s, z1.s, #6 -; SVE-NEXT: lsr z0.s, z0.s, #6 -; SVE-NEXT: stp q1, q0, [x0] -; SVE-NEXT: ret -; -; SVE2-LABEL: udiv_constantsplat_v8i32: -; SVE2: // %bb.0: -; SVE2-NEXT: mov w8, #8969 // =0x2309 -; SVE2-NEXT: ldp q1, q2, [x0] -; SVE2-NEXT: movk w8, #22765, lsl #16 -; SVE2-NEXT: mov z0.s, w8 -; SVE2-NEXT: umulh z3.s, z1.s, z0.s -; SVE2-NEXT: umulh z0.s, z2.s, z0.s -; SVE2-NEXT: sub z1.s, z1.s, z3.s -; SVE2-NEXT: sub z2.s, z2.s, z0.s -; SVE2-NEXT: usra z3.s, z1.s, #1 -; SVE2-NEXT: usra z0.s, z2.s, #1 -; SVE2-NEXT: lsr z1.s, z3.s, #6 -; SVE2-NEXT: lsr z0.s, z0.s, #6 -; SVE2-NEXT: stp q1, q0, [x0] -; SVE2-NEXT: ret -; -; NEON-NOSVE-LABEL: udiv_constantsplat_v8i32: -; NEON-NOSVE: // %bb.0: -; NEON-NOSVE-NEXT: mov w8, #8969 // =0x2309 -; NEON-NOSVE-NEXT: ldp q1, q2, [x0] -; NEON-NOSVE-NEXT: movk w8, #22765, lsl #16 -; NEON-NOSVE-NEXT: dup v0.4s, w8 -; NEON-NOSVE-NEXT: umull2 v3.2d, v1.4s, v0.4s -; NEON-NOSVE-NEXT: umull v4.2d, v1.2s, v0.2s -; NEON-NOSVE-NEXT: umull2 v5.2d, v2.4s, v0.4s -; NEON-NOSVE-NEXT: umull v0.2d, v2.2s, v0.2s -; NEON-NOSVE-NEXT: uzp2 v3.4s, v4.4s, v3.4s -; NEON-NOSVE-NEXT: uzp2 v0.4s, v0.4s, v5.4s -; NEON-NOSVE-NEXT: sub v1.4s, v1.4s, v3.4s -; NEON-NOSVE-NEXT: sub v2.4s, v2.4s, v0.4s -; NEON-NOSVE-NEXT: usra v3.4s, v1.4s, #1 -; NEON-NOSVE-NEXT: usra v0.4s, v2.4s, #1 -; NEON-NOSVE-NEXT: ushr v1.4s, v3.4s, #6 -; NEON-NOSVE-NEXT: ushr v0.4s, v0.4s, #6 -; NEON-NOSVE-NEXT: stp q1, q0, [x0] -; NEON-NOSVE-NEXT: ret +; CHECK-LABEL: udiv_constantsplat_v8i32: +; CHECK: // %bb.0: +; CHECK-NEXT: mov w8, #8969 // =0x2309 +; CHECK-NEXT: ldp q1, q2, [x0] +; CHECK-NEXT: movk w8, #22765, lsl #16 +; CHECK-NEXT: mov z0.s, w8 +; CHECK-NEXT: umulh z3.s, z1.s, z0.s +; CHECK-NEXT: umulh z0.s, z2.s, z0.s +; CHECK-NEXT: sub z1.s, z1.s, z3.s +; CHECK-NEXT: sub z2.s, z2.s, z0.s +; CHECK-NEXT: usra z3.s, z1.s, #1 +; CHECK-NEXT: usra z0.s, z2.s, #1 +; CHECK-NEXT: lsr z1.s, z3.s, #6 +; CHECK-NEXT: lsr z0.s, z0.s, #6 +; CHECK-NEXT: stp q1, q0, [x0] +; CHECK-NEXT: ret ; ; NONEON-NOSVE-LABEL: udiv_constantsplat_v8i32: ; NONEON-NOSVE: // %bb.0: diff --git a/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-int-rem.ll b/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-int-rem.ll index b4641172f8b06d..9497ec88e57b4d 100644 --- a/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-int-rem.ll +++ b/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-int-rem.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mattr=+sve -force-streaming-compatible < %s | FileCheck %s +; RUN: llc -mattr=+sve2 -force-streaming-compatible < %s | FileCheck %s ; RUN: llc -mattr=+sme -force-streaming < %s | FileCheck %s ; RUN: llc -force-streaming-compatible < %s | FileCheck %s --check-prefix=NONEON-NOSVE @@ -76,10 +76,10 @@ define <8 x i8> @srem_v8i8(<8 x i8> %op1, <8 x i8> %op2) { ; CHECK-NEXT: sdivr z2.s, p0/m, z2.s, z3.s ; CHECK-NEXT: ptrue p0.h, vl4 ; CHECK-NEXT: uzp1 z3.h, z4.h, z4.h -; CHECK-NEXT: uzp1 z2.h, z2.h, z2.h -; CHECK-NEXT: splice z3.h, p0, z3.h, z2.h +; CHECK-NEXT: uzp1 z4.h, z2.h, z2.h +; CHECK-NEXT: splice z2.h, p0, { z3.h, z4.h } ; CHECK-NEXT: ptrue p0.b, vl8 -; CHECK-NEXT: uzp1 z2.b, z3.b, z3.b +; CHECK-NEXT: uzp1 z2.b, z2.b, z2.b ; CHECK-NEXT: mls z0.b, p0/m, z2.b, z1.b ; CHECK-NEXT: // kill: def $d0 killed $d0 killed $z0 ; CHECK-NEXT: ret @@ -160,23 +160,23 @@ define <16 x i8> @srem_v16i8(<16 x i8> %op1, <16 x i8> %op2) { ; CHECK-NEXT: mov z3.d, z1.d ; CHECK-NEXT: sunpklo z5.s, z5.h ; CHECK-NEXT: ext z3.b, z3.b, z1.b, #8 -; CHECK-NEXT: uzp1 z4.h, z4.h, z4.h ; CHECK-NEXT: sunpklo z3.h, z3.b ; CHECK-NEXT: sunpklo z6.s, z3.h ; CHECK-NEXT: ext z3.b, z3.b, z3.b, #8 ; CHECK-NEXT: sunpklo z3.s, z3.h ; CHECK-NEXT: sdivr z6.s, p0/m, z6.s, z7.s -; CHECK-NEXT: uzp1 z2.h, z2.h, z2.h ; CHECK-NEXT: sdivr z3.s, p0/m, z3.s, z5.s +; CHECK-NEXT: uzp1 z4.h, z4.h, z4.h ; CHECK-NEXT: ptrue p0.h, vl4 -; CHECK-NEXT: splice z4.h, p0, z4.h, z2.h -; CHECK-NEXT: uzp1 z5.h, z6.h, z6.h -; CHECK-NEXT: uzp1 z2.b, z4.b, z4.b -; CHECK-NEXT: uzp1 z3.h, z3.h, z3.h -; CHECK-NEXT: splice z5.h, p0, z5.h, z3.h +; CHECK-NEXT: uzp1 z5.h, z2.h, z2.h +; CHECK-NEXT: uzp1 z6.h, z6.h, z6.h +; CHECK-NEXT: splice z2.h, p0, { z4.h, z5.h } +; CHECK-NEXT: uzp1 z4.b, z2.b, z2.b +; CHECK-NEXT: uzp1 z7.h, z3.h, z3.h +; CHECK-NEXT: splice z3.h, p0, { z6.h, z7.h } ; CHECK-NEXT: ptrue p0.b, vl8 -; CHECK-NEXT: uzp1 z3.b, z5.b, z5.b -; CHECK-NEXT: splice z2.b, p0, z2.b, z3.b +; CHECK-NEXT: uzp1 z5.b, z3.b, z3.b +; CHECK-NEXT: splice z2.b, p0, { z4.b, z5.b } ; CHECK-NEXT: ptrue p0.b, vl16 ; CHECK-NEXT: mls z0.b, p0/m, z2.b, z1.b ; CHECK-NEXT: // kill: def $q0 killed $q0 killed $z0 @@ -300,14 +300,12 @@ define void @srem_v32i8(ptr %a, ptr %b) { ; CHECK-NEXT: sunpklo z4.s, z16.h ; CHECK-NEXT: ext z7.b, z7.b, z7.b, #8 ; CHECK-NEXT: ext z16.b, z16.b, z16.b, #8 -; CHECK-NEXT: uzp1 z2.h, z2.h, z2.h ; CHECK-NEXT: sunpklo z7.s, z7.h ; CHECK-NEXT: movprfx z6, z4 ; CHECK-NEXT: sdiv z6.s, p0/m, z6.s, z3.s ; CHECK-NEXT: ldr q3, [x0] ; CHECK-NEXT: ldr q4, [x1] ; CHECK-NEXT: sunpklo z16.s, z16.h -; CHECK-NEXT: uzp1 z5.h, z5.h, z5.h ; CHECK-NEXT: sunpklo z17.h, z4.b ; CHECK-NEXT: sunpklo z18.h, z3.b ; CHECK-NEXT: sdivr z7.s, p0/m, z7.s, z16.s @@ -317,11 +315,9 @@ define void @srem_v32i8(ptr %a, ptr %b) { ; CHECK-NEXT: ext z18.b, z18.b, z18.b, #8 ; CHECK-NEXT: sunpklo z17.s, z17.h ; CHECK-NEXT: sunpklo z18.s, z18.h -; CHECK-NEXT: uzp1 z6.h, z6.h, z6.h ; CHECK-NEXT: sdivr z19.s, p0/m, z19.s, z20.s ; CHECK-NEXT: mov z20.d, z3.d ; CHECK-NEXT: ext z20.b, z20.b, z3.b, #8 -; CHECK-NEXT: uzp1 z7.h, z7.h, z7.h ; CHECK-NEXT: sunpklo z20.h, z20.b ; CHECK-NEXT: sunpklo z22.s, z20.h ; CHECK-NEXT: ext z20.b, z20.b, z20.b, #8 @@ -329,32 +325,36 @@ define void @srem_v32i8(ptr %a, ptr %b) { ; CHECK-NEXT: mov z18.d, z4.d ; CHECK-NEXT: sunpklo z20.s, z20.h ; CHECK-NEXT: ext z18.b, z18.b, z4.b, #8 -; CHECK-NEXT: uzp1 z16.h, z19.h, z19.h ; CHECK-NEXT: sunpklo z18.h, z18.b ; CHECK-NEXT: sunpklo z21.s, z18.h ; CHECK-NEXT: ext z18.b, z18.b, z18.b, #8 ; CHECK-NEXT: sunpklo z18.s, z18.h ; CHECK-NEXT: sdivr z21.s, p0/m, z21.s, z22.s -; CHECK-NEXT: uzp1 z17.h, z17.h, z17.h +; CHECK-NEXT: uzp1 z22.h, z2.h, z2.h +; CHECK-NEXT: uzp1 z23.h, z5.h, z5.h +; CHECK-NEXT: uzp1 z5.h, z6.h, z6.h +; CHECK-NEXT: uzp1 z6.h, z7.h, z7.h ; CHECK-NEXT: sdivr z18.s, p0/m, z18.s, z20.s +; CHECK-NEXT: uzp1 z19.h, z19.h, z19.h ; CHECK-NEXT: ptrue p0.h, vl4 -; CHECK-NEXT: splice z16.h, p0, z16.h, z17.h -; CHECK-NEXT: splice z2.h, p0, z2.h, z5.h -; CHECK-NEXT: splice z6.h, p0, z6.h, z7.h -; CHECK-NEXT: uzp1 z19.h, z21.h, z21.h -; CHECK-NEXT: uzp1 z5.b, z16.b, z16.b -; CHECK-NEXT: uzp1 z2.b, z2.b, z2.b -; CHECK-NEXT: uzp1 z6.b, z6.b, z6.b -; CHECK-NEXT: uzp1 z18.h, z18.h, z18.h -; CHECK-NEXT: splice z19.h, p0, z19.h, z18.h +; CHECK-NEXT: uzp1 z20.h, z17.h, z17.h +; CHECK-NEXT: splice z7.h, p0, { z22.h, z23.h } +; CHECK-NEXT: splice z5.h, p0, { z5.h, z6.h } +; CHECK-NEXT: uzp1 z16.h, z21.h, z21.h +; CHECK-NEXT: splice z2.h, p0, { z19.h, z20.h } +; CHECK-NEXT: uzp1 z6.b, z7.b, z7.b +; CHECK-NEXT: uzp1 z7.b, z5.b, z5.b +; CHECK-NEXT: uzp1 z17.h, z18.h, z18.h +; CHECK-NEXT: splice z16.h, p0, { z16.h, z17.h } +; CHECK-NEXT: uzp1 z17.b, z2.b, z2.b ; CHECK-NEXT: ptrue p0.b, vl8 -; CHECK-NEXT: splice z2.b, p0, z2.b, z6.b -; CHECK-NEXT: uzp1 z7.b, z19.b, z19.b -; CHECK-NEXT: splice z5.b, p0, z5.b, z7.b +; CHECK-NEXT: splice z5.b, p0, { z6.b, z7.b } +; CHECK-NEXT: uzp1 z18.b, z16.b, z16.b +; CHECK-NEXT: splice z2.b, p0, { z17.b, z18.b } ; CHECK-NEXT: ptrue p0.b, vl16 -; CHECK-NEXT: mls z0.b, p0/m, z2.b, z1.b -; CHECK-NEXT: mls z3.b, p0/m, z5.b, z4.b -; CHECK-NEXT: stp q3, q0, [x0] +; CHECK-NEXT: mls z0.b, p0/m, z5.b, z1.b +; CHECK-NEXT: msb z2.b, p0/m, z4.b, z3.b +; CHECK-NEXT: stp q2, q0, [x0] ; CHECK-NEXT: ret ; ; NONEON-NOSVE-LABEL: srem_v32i8: @@ -600,9 +600,9 @@ define <8 x i16> @srem_v8i16(<8 x i16> %op1, <8 x i16> %op2) { ; CHECK-NEXT: sunpklo z3.s, z3.h ; CHECK-NEXT: sdivr z3.s, p0/m, z3.s, z4.s ; CHECK-NEXT: ptrue p0.h, vl4 -; CHECK-NEXT: uzp1 z2.h, z2.h, z2.h -; CHECK-NEXT: uzp1 z3.h, z3.h, z3.h -; CHECK-NEXT: splice z2.h, p0, z2.h, z3.h +; CHECK-NEXT: uzp1 z4.h, z2.h, z2.h +; CHECK-NEXT: uzp1 z5.h, z3.h, z3.h +; CHECK-NEXT: splice z2.h, p0, { z4.h, z5.h } ; CHECK-NEXT: ptrue p0.h, vl8 ; CHECK-NEXT: mls z0.h, p0/m, z2.h, z1.h ; CHECK-NEXT: // kill: def $q0 killed $q0 killed $z0 @@ -680,23 +680,23 @@ define void @srem_v16i16(ptr %a, ptr %b) { ; CHECK-NEXT: sdivr z5.s, p0/m, z5.s, z6.s ; CHECK-NEXT: mov z6.d, z4.d ; CHECK-NEXT: ext z6.b, z6.b, z4.b, #8 -; CHECK-NEXT: uzp1 z2.h, z2.h, z2.h ; CHECK-NEXT: sunpklo z6.s, z6.h ; CHECK-NEXT: sdivr z6.s, p0/m, z6.s, z7.s ; CHECK-NEXT: mov z7.d, z1.d ; CHECK-NEXT: ext z7.b, z7.b, z1.b, #8 -; CHECK-NEXT: uzp1 z5.h, z5.h, z5.h ; CHECK-NEXT: sunpklo z7.s, z7.h ; CHECK-NEXT: sdivr z7.s, p0/m, z7.s, z16.s +; CHECK-NEXT: uzp1 z16.h, z5.h, z5.h ; CHECK-NEXT: ptrue p0.h, vl4 -; CHECK-NEXT: uzp1 z6.h, z6.h, z6.h -; CHECK-NEXT: splice z5.h, p0, z5.h, z6.h -; CHECK-NEXT: uzp1 z7.h, z7.h, z7.h -; CHECK-NEXT: splice z2.h, p0, z2.h, z7.h +; CHECK-NEXT: uzp1 z17.h, z6.h, z6.h +; CHECK-NEXT: uzp1 z5.h, z2.h, z2.h +; CHECK-NEXT: splice z2.h, p0, { z16.h, z17.h } +; CHECK-NEXT: uzp1 z6.h, z7.h, z7.h +; CHECK-NEXT: splice z5.h, p0, { z5.h, z6.h } ; CHECK-NEXT: ptrue p0.h, vl8 -; CHECK-NEXT: mls z3.h, p0/m, z5.h, z4.h -; CHECK-NEXT: mls z0.h, p0/m, z2.h, z1.h -; CHECK-NEXT: stp q3, q0, [x0] +; CHECK-NEXT: msb z2.h, p0/m, z4.h, z3.h +; CHECK-NEXT: mls z0.h, p0/m, z5.h, z1.h +; CHECK-NEXT: stp q2, q0, [x0] ; CHECK-NEXT: ret ; ; NONEON-NOSVE-LABEL: srem_v16i16: @@ -1126,10 +1126,10 @@ define <8 x i8> @urem_v8i8(<8 x i8> %op1, <8 x i8> %op2) { ; CHECK-NEXT: udivr z2.s, p0/m, z2.s, z3.s ; CHECK-NEXT: ptrue p0.h, vl4 ; CHECK-NEXT: uzp1 z3.h, z4.h, z4.h -; CHECK-NEXT: uzp1 z2.h, z2.h, z2.h -; CHECK-NEXT: splice z3.h, p0, z3.h, z2.h +; CHECK-NEXT: uzp1 z4.h, z2.h, z2.h +; CHECK-NEXT: splice z2.h, p0, { z3.h, z4.h } ; CHECK-NEXT: ptrue p0.b, vl8 -; CHECK-NEXT: uzp1 z2.b, z3.b, z3.b +; CHECK-NEXT: uzp1 z2.b, z2.b, z2.b ; CHECK-NEXT: mls z0.b, p0/m, z2.b, z1.b ; CHECK-NEXT: // kill: def $d0 killed $d0 killed $z0 ; CHECK-NEXT: ret @@ -1210,23 +1210,23 @@ define <16 x i8> @urem_v16i8(<16 x i8> %op1, <16 x i8> %op2) { ; CHECK-NEXT: mov z3.d, z1.d ; CHECK-NEXT: uunpklo z5.s, z5.h ; CHECK-NEXT: ext z3.b, z3.b, z1.b, #8 -; CHECK-NEXT: uzp1 z4.h, z4.h, z4.h ; CHECK-NEXT: uunpklo z3.h, z3.b ; CHECK-NEXT: uunpklo z6.s, z3.h ; CHECK-NEXT: ext z3.b, z3.b, z3.b, #8 ; CHECK-NEXT: uunpklo z3.s, z3.h ; CHECK-NEXT: udivr z6.s, p0/m, z6.s, z7.s -; CHECK-NEXT: uzp1 z2.h, z2.h, z2.h ; CHECK-NEXT: udivr z3.s, p0/m, z3.s, z5.s +; CHECK-NEXT: uzp1 z4.h, z4.h, z4.h ; CHECK-NEXT: ptrue p0.h, vl4 -; CHECK-NEXT: splice z4.h, p0, z4.h, z2.h -; CHECK-NEXT: uzp1 z5.h, z6.h, z6.h -; CHECK-NEXT: uzp1 z2.b, z4.b, z4.b -; CHECK-NEXT: uzp1 z3.h, z3.h, z3.h -; CHECK-NEXT: splice z5.h, p0, z5.h, z3.h +; CHECK-NEXT: uzp1 z5.h, z2.h, z2.h +; CHECK-NEXT: uzp1 z6.h, z6.h, z6.h +; CHECK-NEXT: splice z2.h, p0, { z4.h, z5.h } +; CHECK-NEXT: uzp1 z4.b, z2.b, z2.b +; CHECK-NEXT: uzp1 z7.h, z3.h, z3.h +; CHECK-NEXT: splice z3.h, p0, { z6.h, z7.h } ; CHECK-NEXT: ptrue p0.b, vl8 -; CHECK-NEXT: uzp1 z3.b, z5.b, z5.b -; CHECK-NEXT: splice z2.b, p0, z2.b, z3.b +; CHECK-NEXT: uzp1 z5.b, z3.b, z3.b +; CHECK-NEXT: splice z2.b, p0, { z4.b, z5.b } ; CHECK-NEXT: ptrue p0.b, vl16 ; CHECK-NEXT: mls z0.b, p0/m, z2.b, z1.b ; CHECK-NEXT: // kill: def $q0 killed $q0 killed $z0 @@ -1350,14 +1350,12 @@ define void @urem_v32i8(ptr %a, ptr %b) { ; CHECK-NEXT: uunpklo z4.s, z16.h ; CHECK-NEXT: ext z7.b, z7.b, z7.b, #8 ; CHECK-NEXT: ext z16.b, z16.b, z16.b, #8 -; CHECK-NEXT: uzp1 z2.h, z2.h, z2.h ; CHECK-NEXT: uunpklo z7.s, z7.h ; CHECK-NEXT: movprfx z6, z4 ; CHECK-NEXT: udiv z6.s, p0/m, z6.s, z3.s ; CHECK-NEXT: ldr q3, [x0] ; CHECK-NEXT: ldr q4, [x1] ; CHECK-NEXT: uunpklo z16.s, z16.h -; CHECK-NEXT: uzp1 z5.h, z5.h, z5.h ; CHECK-NEXT: uunpklo z17.h, z4.b ; CHECK-NEXT: uunpklo z18.h, z3.b ; CHECK-NEXT: udivr z7.s, p0/m, z7.s, z16.s @@ -1367,11 +1365,9 @@ define void @urem_v32i8(ptr %a, ptr %b) { ; CHECK-NEXT: ext z18.b, z18.b, z18.b, #8 ; CHECK-NEXT: uunpklo z17.s, z17.h ; CHECK-NEXT: uunpklo z18.s, z18.h -; CHECK-NEXT: uzp1 z6.h, z6.h, z6.h ; CHECK-NEXT: udivr z19.s, p0/m, z19.s, z20.s ; CHECK-NEXT: mov z20.d, z3.d ; CHECK-NEXT: ext z20.b, z20.b, z3.b, #8 -; CHECK-NEXT: uzp1 z7.h, z7.h, z7.h ; CHECK-NEXT: uunpklo z20.h, z20.b ; CHECK-NEXT: uunpklo z22.s, z20.h ; CHECK-NEXT: ext z20.b, z20.b, z20.b, #8 @@ -1379,32 +1375,36 @@ define void @urem_v32i8(ptr %a, ptr %b) { ; CHECK-NEXT: mov z18.d, z4.d ; CHECK-NEXT: uunpklo z20.s, z20.h ; CHECK-NEXT: ext z18.b, z18.b, z4.b, #8 -; CHECK-NEXT: uzp1 z16.h, z19.h, z19.h ; CHECK-NEXT: uunpklo z18.h, z18.b ; CHECK-NEXT: uunpklo z21.s, z18.h ; CHECK-NEXT: ext z18.b, z18.b, z18.b, #8 ; CHECK-NEXT: uunpklo z18.s, z18.h ; CHECK-NEXT: udivr z21.s, p0/m, z21.s, z22.s -; CHECK-NEXT: uzp1 z17.h, z17.h, z17.h +; CHECK-NEXT: uzp1 z22.h, z2.h, z2.h +; CHECK-NEXT: uzp1 z23.h, z5.h, z5.h +; CHECK-NEXT: uzp1 z5.h, z6.h, z6.h +; CHECK-NEXT: uzp1 z6.h, z7.h, z7.h ; CHECK-NEXT: udivr z18.s, p0/m, z18.s, z20.s +; CHECK-NEXT: uzp1 z19.h, z19.h, z19.h ; CHECK-NEXT: ptrue p0.h, vl4 -; CHECK-NEXT: splice z16.h, p0, z16.h, z17.h -; CHECK-NEXT: splice z2.h, p0, z2.h, z5.h -; CHECK-NEXT: splice z6.h, p0, z6.h, z7.h -; CHECK-NEXT: uzp1 z19.h, z21.h, z21.h -; CHECK-NEXT: uzp1 z5.b, z16.b, z16.b -; CHECK-NEXT: uzp1 z2.b, z2.b, z2.b -; CHECK-NEXT: uzp1 z6.b, z6.b, z6.b -; CHECK-NEXT: uzp1 z18.h, z18.h, z18.h -; CHECK-NEXT: splice z19.h, p0, z19.h, z18.h +; CHECK-NEXT: uzp1 z20.h, z17.h, z17.h +; CHECK-NEXT: splice z7.h, p0, { z22.h, z23.h } +; CHECK-NEXT: splice z5.h, p0, { z5.h, z6.h } +; CHECK-NEXT: uzp1 z16.h, z21.h, z21.h +; CHECK-NEXT: splice z2.h, p0, { z19.h, z20.h } +; CHECK-NEXT: uzp1 z6.b, z7.b, z7.b +; CHECK-NEXT: uzp1 z7.b, z5.b, z5.b +; CHECK-NEXT: uzp1 z17.h, z18.h, z18.h +; CHECK-NEXT: splice z16.h, p0, { z16.h, z17.h } +; CHECK-NEXT: uzp1 z17.b, z2.b, z2.b ; CHECK-NEXT: ptrue p0.b, vl8 -; CHECK-NEXT: splice z2.b, p0, z2.b, z6.b -; CHECK-NEXT: uzp1 z7.b, z19.b, z19.b -; CHECK-NEXT: splice z5.b, p0, z5.b, z7.b +; CHECK-NEXT: splice z5.b, p0, { z6.b, z7.b } +; CHECK-NEXT: uzp1 z18.b, z16.b, z16.b +; CHECK-NEXT: splice z2.b, p0, { z17.b, z18.b } ; CHECK-NEXT: ptrue p0.b, vl16 -; CHECK-NEXT: mls z0.b, p0/m, z2.b, z1.b -; CHECK-NEXT: mls z3.b, p0/m, z5.b, z4.b -; CHECK-NEXT: stp q3, q0, [x0] +; CHECK-NEXT: mls z0.b, p0/m, z5.b, z1.b +; CHECK-NEXT: msb z2.b, p0/m, z4.b, z3.b +; CHECK-NEXT: stp q2, q0, [x0] ; CHECK-NEXT: ret ; ; NONEON-NOSVE-LABEL: urem_v32i8: @@ -1650,9 +1650,9 @@ define <8 x i16> @urem_v8i16(<8 x i16> %op1, <8 x i16> %op2) { ; CHECK-NEXT: uunpklo z3.s, z3.h ; CHECK-NEXT: udivr z3.s, p0/m, z3.s, z4.s ; CHECK-NEXT: ptrue p0.h, vl4 -; CHECK-NEXT: uzp1 z2.h, z2.h, z2.h -; CHECK-NEXT: uzp1 z3.h, z3.h, z3.h -; CHECK-NEXT: splice z2.h, p0, z2.h, z3.h +; CHECK-NEXT: uzp1 z4.h, z2.h, z2.h +; CHECK-NEXT: uzp1 z5.h, z3.h, z3.h +; CHECK-NEXT: splice z2.h, p0, { z4.h, z5.h } ; CHECK-NEXT: ptrue p0.h, vl8 ; CHECK-NEXT: mls z0.h, p0/m, z2.h, z1.h ; CHECK-NEXT: // kill: def $q0 killed $q0 killed $z0 @@ -1730,23 +1730,23 @@ define void @urem_v16i16(ptr %a, ptr %b) { ; CHECK-NEXT: udivr z5.s, p0/m, z5.s, z6.s ; CHECK-NEXT: mov z6.d, z4.d ; CHECK-NEXT: ext z6.b, z6.b, z4.b, #8 -; CHECK-NEXT: uzp1 z2.h, z2.h, z2.h ; CHECK-NEXT: uunpklo z6.s, z6.h ; CHECK-NEXT: udivr z6.s, p0/m, z6.s, z7.s ; CHECK-NEXT: mov z7.d, z1.d ; CHECK-NEXT: ext z7.b, z7.b, z1.b, #8 -; CHECK-NEXT: uzp1 z5.h, z5.h, z5.h ; CHECK-NEXT: uunpklo z7.s, z7.h ; CHECK-NEXT: udivr z7.s, p0/m, z7.s, z16.s +; CHECK-NEXT: uzp1 z16.h, z5.h, z5.h ; CHECK-NEXT: ptrue p0.h, vl4 -; CHECK-NEXT: uzp1 z6.h, z6.h, z6.h -; CHECK-NEXT: splice z5.h, p0, z5.h, z6.h -; CHECK-NEXT: uzp1 z7.h, z7.h, z7.h -; CHECK-NEXT: splice z2.h, p0, z2.h, z7.h +; CHECK-NEXT: uzp1 z17.h, z6.h, z6.h +; CHECK-NEXT: uzp1 z5.h, z2.h, z2.h +; CHECK-NEXT: splice z2.h, p0, { z16.h, z17.h } +; CHECK-NEXT: uzp1 z6.h, z7.h, z7.h +; CHECK-NEXT: splice z5.h, p0, { z5.h, z6.h } ; CHECK-NEXT: ptrue p0.h, vl8 -; CHECK-NEXT: mls z3.h, p0/m, z5.h, z4.h -; CHECK-NEXT: mls z0.h, p0/m, z2.h, z1.h -; CHECK-NEXT: stp q3, q0, [x0] +; CHECK-NEXT: msb z2.h, p0/m, z4.h, z3.h +; CHECK-NEXT: mls z0.h, p0/m, z5.h, z1.h +; CHECK-NEXT: stp q2, q0, [x0] ; CHECK-NEXT: ret ; ; NONEON-NOSVE-LABEL: urem_v16i16: diff --git a/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-ptest.ll b/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-ptest.ll index 5235423c00d9a1..e07036f2a1acfc 100644 --- a/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-ptest.ll +++ b/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-ptest.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mattr=+sve -force-streaming-compatible < %s | FileCheck %s +; RUN: llc -mattr=+sve2 -force-streaming-compatible < %s | FileCheck %s ; RUN: llc -mattr=+sme -force-streaming < %s | FileCheck %s ; RUN: llc -force-streaming-compatible < %s | FileCheck %s --check-prefix=NONEON-NOSVE @@ -11,28 +11,28 @@ define i1 @ptest_v16i1(ptr %a, ptr %b) { ; CHECK: // %bb.0: ; CHECK-NEXT: ldp q1, q0, [x0, #32] ; CHECK-NEXT: ptrue p0.s, vl4 -; CHECK-NEXT: ldp q2, q3, [x0] +; CHECK-NEXT: ldp q3, q2, [x0] ; CHECK-NEXT: fcmne p1.s, p0/z, z0.s, #0.0 ; CHECK-NEXT: fcmne p2.s, p0/z, z1.s, #0.0 -; CHECK-NEXT: fcmne p3.s, p0/z, z3.s, #0.0 -; CHECK-NEXT: fcmne p0.s, p0/z, z2.s, #0.0 +; CHECK-NEXT: fcmne p3.s, p0/z, z2.s, #0.0 +; CHECK-NEXT: fcmne p0.s, p0/z, z3.s, #0.0 ; CHECK-NEXT: mov z0.s, p1/z, #-1 // =0xffffffffffffffff ; CHECK-NEXT: mov z1.s, p2/z, #-1 // =0xffffffffffffffff ; CHECK-NEXT: mov z2.s, p3/z, #-1 // =0xffffffffffffffff ; CHECK-NEXT: mov z3.s, p0/z, #-1 // =0xffffffffffffffff ; CHECK-NEXT: ptrue p0.h, vl4 -; CHECK-NEXT: uzp1 z0.h, z0.h, z0.h -; CHECK-NEXT: uzp1 z1.h, z1.h, z1.h -; CHECK-NEXT: uzp1 z2.h, z2.h, z2.h -; CHECK-NEXT: uzp1 z3.h, z3.h, z3.h -; CHECK-NEXT: splice z1.h, p0, z1.h, z0.h -; CHECK-NEXT: splice z3.h, p0, z3.h, z2.h +; CHECK-NEXT: uzp1 z5.h, z0.h, z0.h +; CHECK-NEXT: uzp1 z4.h, z1.h, z1.h +; CHECK-NEXT: uzp1 z1.h, z2.h, z2.h +; CHECK-NEXT: uzp1 z0.h, z3.h, z3.h +; CHECK-NEXT: splice z2.h, p0, { z4.h, z5.h } +; CHECK-NEXT: splice z0.h, p0, { z0.h, z1.h } ; CHECK-NEXT: ptrue p0.b, vl8 -; CHECK-NEXT: uzp1 z0.b, z1.b, z1.b -; CHECK-NEXT: uzp1 z1.b, z3.b, z3.b -; CHECK-NEXT: splice z1.b, p0, z1.b, z0.b +; CHECK-NEXT: uzp1 z2.b, z2.b, z2.b +; CHECK-NEXT: uzp1 z1.b, z0.b, z0.b +; CHECK-NEXT: splice z0.b, p0, { z1.b, z2.b } ; CHECK-NEXT: ptrue p0.b, vl16 -; CHECK-NEXT: umaxv b0, p0, z1.b +; CHECK-NEXT: umaxv b0, p0, z0.b ; CHECK-NEXT: fmov w8, s0 ; CHECK-NEXT: and w0, w8, #0x1 ; CHECK-NEXT: ret @@ -120,49 +120,49 @@ define i1 @ptest_v16i1(ptr %a, ptr %b) { define i1 @ptest_or_v16i1(ptr %a, ptr %b) { ; CHECK-LABEL: ptest_or_v16i1: ; CHECK: // %bb.0: -; CHECK-NEXT: ldp q1, q0, [x0, #32] +; CHECK-NEXT: ldp q0, q1, [x0, #32] ; CHECK-NEXT: ptrue p0.s, vl4 -; CHECK-NEXT: ldp q2, q3, [x0] -; CHECK-NEXT: ldp q4, q5, [x1, #32] -; CHECK-NEXT: fcmne p1.s, p0/z, z0.s, #0.0 -; CHECK-NEXT: fcmne p2.s, p0/z, z1.s, #0.0 -; CHECK-NEXT: ldp q0, q1, [x1] +; CHECK-NEXT: ldp q2, q3, [x1, #32] +; CHECK-NEXT: ldp q4, q5, [x0] +; CHECK-NEXT: fcmne p1.s, p0/z, z1.s, #0.0 +; CHECK-NEXT: ldp q1, q6, [x1] ; CHECK-NEXT: fcmne p3.s, p0/z, z3.s, #0.0 -; CHECK-NEXT: fcmne p4.s, p0/z, z2.s, #0.0 -; CHECK-NEXT: fcmne p5.s, p0/z, z5.s, #0.0 -; CHECK-NEXT: fcmne p6.s, p0/z, z4.s, #0.0 -; CHECK-NEXT: fcmne p7.s, p0/z, z1.s, #0.0 -; CHECK-NEXT: fcmne p0.s, p0/z, z0.s, #0.0 +; CHECK-NEXT: fcmne p2.s, p0/z, z0.s, #0.0 +; CHECK-NEXT: fcmne p5.s, p0/z, z2.s, #0.0 +; CHECK-NEXT: fcmne p4.s, p0/z, z5.s, #0.0 +; CHECK-NEXT: fcmne p7.s, p0/z, z4.s, #0.0 +; CHECK-NEXT: fcmne p6.s, p0/z, z6.s, #0.0 +; CHECK-NEXT: fcmne p0.s, p0/z, z1.s, #0.0 ; CHECK-NEXT: mov z0.s, p1/z, #-1 // =0xffffffffffffffff -; CHECK-NEXT: mov z1.s, p2/z, #-1 // =0xffffffffffffffff ; CHECK-NEXT: mov z2.s, p3/z, #-1 // =0xffffffffffffffff -; CHECK-NEXT: mov z3.s, p4/z, #-1 // =0xffffffffffffffff +; CHECK-NEXT: mov z1.s, p2/z, #-1 // =0xffffffffffffffff ; CHECK-NEXT: mov z4.s, p5/z, #-1 // =0xffffffffffffffff -; CHECK-NEXT: mov z5.s, p6/z, #-1 // =0xffffffffffffffff -; CHECK-NEXT: uzp1 z0.h, z0.h, z0.h +; CHECK-NEXT: mov z3.s, p4/z, #-1 // =0xffffffffffffffff ; CHECK-NEXT: mov z6.s, p7/z, #-1 // =0xffffffffffffffff +; CHECK-NEXT: mov z5.s, p6/z, #-1 // =0xffffffffffffffff ; CHECK-NEXT: mov z7.s, p0/z, #-1 // =0xffffffffffffffff -; CHECK-NEXT: uzp1 z1.h, z1.h, z1.h -; CHECK-NEXT: uzp1 z2.h, z2.h, z2.h -; CHECK-NEXT: uzp1 z3.h, z3.h, z3.h -; CHECK-NEXT: uzp1 z4.h, z4.h, z4.h -; CHECK-NEXT: uzp1 z5.h, z5.h, z5.h +; CHECK-NEXT: uzp1 z17.h, z0.h, z0.h +; CHECK-NEXT: uzp1 z19.h, z2.h, z2.h +; CHECK-NEXT: uzp1 z16.h, z1.h, z1.h ; CHECK-NEXT: ptrue p0.h, vl4 -; CHECK-NEXT: uzp1 z6.h, z6.h, z6.h -; CHECK-NEXT: uzp1 z7.h, z7.h, z7.h -; CHECK-NEXT: splice z1.h, p0, z1.h, z0.h -; CHECK-NEXT: splice z3.h, p0, z3.h, z2.h -; CHECK-NEXT: splice z5.h, p0, z5.h, z4.h -; CHECK-NEXT: splice z7.h, p0, z7.h, z6.h +; CHECK-NEXT: uzp1 z1.h, z3.h, z3.h +; CHECK-NEXT: uzp1 z18.h, z4.h, z4.h +; CHECK-NEXT: uzp1 z3.h, z5.h, z5.h +; CHECK-NEXT: uzp1 z0.h, z6.h, z6.h +; CHECK-NEXT: uzp1 z2.h, z7.h, z7.h +; CHECK-NEXT: splice z4.h, p0, { z16.h, z17.h } +; CHECK-NEXT: splice z5.h, p0, { z18.h, z19.h } +; CHECK-NEXT: splice z0.h, p0, { z0.h, z1.h } +; CHECK-NEXT: splice z1.h, p0, { z2.h, z3.h } ; CHECK-NEXT: ptrue p0.b, vl8 -; CHECK-NEXT: uzp1 z0.b, z1.b, z1.b -; CHECK-NEXT: uzp1 z1.b, z3.b, z3.b -; CHECK-NEXT: uzp1 z2.b, z5.b, z5.b -; CHECK-NEXT: uzp1 z3.b, z7.b, z7.b -; CHECK-NEXT: splice z1.b, p0, z1.b, z0.b -; CHECK-NEXT: splice z3.b, p0, z3.b, z2.b +; CHECK-NEXT: uzp1 z3.b, z4.b, z4.b +; CHECK-NEXT: uzp1 z5.b, z5.b, z5.b +; CHECK-NEXT: uzp1 z2.b, z0.b, z0.b +; CHECK-NEXT: uzp1 z4.b, z1.b, z1.b +; CHECK-NEXT: splice z0.b, p0, { z2.b, z3.b } +; CHECK-NEXT: splice z1.b, p0, { z4.b, z5.b } ; CHECK-NEXT: ptrue p0.b, vl16 -; CHECK-NEXT: orr z0.d, z1.d, z3.d +; CHECK-NEXT: orr z0.d, z0.d, z1.d ; CHECK-NEXT: umaxv b0, p0, z0.b ; CHECK-NEXT: fmov w8, s0 ; CHECK-NEXT: and w0, w8, #0x1 @@ -329,49 +329,49 @@ declare i1 @llvm.vector.reduce.or.i1.v16i1(<16 x i1>) define i1 @ptest_and_v16i1(ptr %a, ptr %b) { ; CHECK-LABEL: ptest_and_v16i1: ; CHECK: // %bb.0: -; CHECK-NEXT: ldp q1, q0, [x0, #32] +; CHECK-NEXT: ldp q0, q1, [x0, #32] ; CHECK-NEXT: ptrue p0.s, vl4 -; CHECK-NEXT: ldp q2, q3, [x0] -; CHECK-NEXT: ldp q4, q5, [x1, #32] -; CHECK-NEXT: fcmne p1.s, p0/z, z0.s, #0.0 -; CHECK-NEXT: fcmne p2.s, p0/z, z1.s, #0.0 -; CHECK-NEXT: ldp q0, q1, [x1] +; CHECK-NEXT: ldp q2, q3, [x1, #32] +; CHECK-NEXT: ldp q4, q5, [x0] +; CHECK-NEXT: fcmne p1.s, p0/z, z1.s, #0.0 +; CHECK-NEXT: ldp q1, q6, [x1] ; CHECK-NEXT: fcmne p3.s, p0/z, z3.s, #0.0 -; CHECK-NEXT: fcmne p4.s, p0/z, z2.s, #0.0 -; CHECK-NEXT: fcmne p5.s, p0/z, z5.s, #0.0 -; CHECK-NEXT: fcmne p6.s, p0/z, z4.s, #0.0 -; CHECK-NEXT: fcmne p7.s, p0/z, z1.s, #0.0 -; CHECK-NEXT: fcmne p0.s, p0/z, z0.s, #0.0 +; CHECK-NEXT: fcmne p2.s, p0/z, z0.s, #0.0 +; CHECK-NEXT: fcmne p5.s, p0/z, z2.s, #0.0 +; CHECK-NEXT: fcmne p4.s, p0/z, z5.s, #0.0 +; CHECK-NEXT: fcmne p7.s, p0/z, z4.s, #0.0 +; CHECK-NEXT: fcmne p6.s, p0/z, z6.s, #0.0 +; CHECK-NEXT: fcmne p0.s, p0/z, z1.s, #0.0 ; CHECK-NEXT: mov z0.s, p1/z, #-1 // =0xffffffffffffffff -; CHECK-NEXT: mov z1.s, p2/z, #-1 // =0xffffffffffffffff ; CHECK-NEXT: mov z2.s, p3/z, #-1 // =0xffffffffffffffff -; CHECK-NEXT: mov z3.s, p4/z, #-1 // =0xffffffffffffffff +; CHECK-NEXT: mov z1.s, p2/z, #-1 // =0xffffffffffffffff ; CHECK-NEXT: mov z4.s, p5/z, #-1 // =0xffffffffffffffff -; CHECK-NEXT: mov z5.s, p6/z, #-1 // =0xffffffffffffffff -; CHECK-NEXT: uzp1 z0.h, z0.h, z0.h +; CHECK-NEXT: mov z3.s, p4/z, #-1 // =0xffffffffffffffff ; CHECK-NEXT: mov z6.s, p7/z, #-1 // =0xffffffffffffffff +; CHECK-NEXT: mov z5.s, p6/z, #-1 // =0xffffffffffffffff ; CHECK-NEXT: mov z7.s, p0/z, #-1 // =0xffffffffffffffff -; CHECK-NEXT: uzp1 z1.h, z1.h, z1.h -; CHECK-NEXT: uzp1 z2.h, z2.h, z2.h -; CHECK-NEXT: uzp1 z3.h, z3.h, z3.h -; CHECK-NEXT: uzp1 z4.h, z4.h, z4.h -; CHECK-NEXT: uzp1 z5.h, z5.h, z5.h +; CHECK-NEXT: uzp1 z17.h, z0.h, z0.h +; CHECK-NEXT: uzp1 z19.h, z2.h, z2.h +; CHECK-NEXT: uzp1 z16.h, z1.h, z1.h ; CHECK-NEXT: ptrue p0.h, vl4 -; CHECK-NEXT: uzp1 z6.h, z6.h, z6.h -; CHECK-NEXT: uzp1 z7.h, z7.h, z7.h -; CHECK-NEXT: splice z1.h, p0, z1.h, z0.h -; CHECK-NEXT: splice z3.h, p0, z3.h, z2.h -; CHECK-NEXT: splice z5.h, p0, z5.h, z4.h -; CHECK-NEXT: splice z7.h, p0, z7.h, z6.h +; CHECK-NEXT: uzp1 z1.h, z3.h, z3.h +; CHECK-NEXT: uzp1 z18.h, z4.h, z4.h +; CHECK-NEXT: uzp1 z3.h, z5.h, z5.h +; CHECK-NEXT: uzp1 z0.h, z6.h, z6.h +; CHECK-NEXT: uzp1 z2.h, z7.h, z7.h +; CHECK-NEXT: splice z4.h, p0, { z16.h, z17.h } +; CHECK-NEXT: splice z5.h, p0, { z18.h, z19.h } +; CHECK-NEXT: splice z0.h, p0, { z0.h, z1.h } +; CHECK-NEXT: splice z1.h, p0, { z2.h, z3.h } ; CHECK-NEXT: ptrue p0.b, vl8 -; CHECK-NEXT: uzp1 z0.b, z1.b, z1.b -; CHECK-NEXT: uzp1 z1.b, z3.b, z3.b -; CHECK-NEXT: uzp1 z2.b, z5.b, z5.b -; CHECK-NEXT: uzp1 z3.b, z7.b, z7.b -; CHECK-NEXT: splice z1.b, p0, z1.b, z0.b -; CHECK-NEXT: splice z3.b, p0, z3.b, z2.b +; CHECK-NEXT: uzp1 z3.b, z4.b, z4.b +; CHECK-NEXT: uzp1 z5.b, z5.b, z5.b +; CHECK-NEXT: uzp1 z2.b, z0.b, z0.b +; CHECK-NEXT: uzp1 z4.b, z1.b, z1.b +; CHECK-NEXT: splice z0.b, p0, { z2.b, z3.b } +; CHECK-NEXT: splice z1.b, p0, { z4.b, z5.b } ; CHECK-NEXT: ptrue p0.b, vl16 -; CHECK-NEXT: and z0.d, z1.d, z3.d +; CHECK-NEXT: and z0.d, z0.d, z1.d ; CHECK-NEXT: uminv b0, p0, z0.b ; CHECK-NEXT: fmov w8, s0 ; CHECK-NEXT: and w0, w8, #0x1 diff --git a/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-trunc-stores.ll b/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-trunc-stores.ll index c0aa162b19b77d..13fcd94ea8a260 100644 --- a/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-trunc-stores.ll +++ b/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-trunc-stores.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mattr=+sve -force-streaming-compatible < %s | FileCheck %s +; RUN: llc -mattr=+sve2 -force-streaming-compatible < %s | FileCheck %s ; RUN: llc -mattr=+sme -force-streaming < %s | FileCheck %s ; RUN: llc -force-streaming-compatible < %s | FileCheck %s --check-prefix=NONEON-NOSVE @@ -129,11 +129,11 @@ define void @store_trunc_v2i64i8(ptr %ap, ptr %dest) { define void @store_trunc_v2i256i64(ptr %ap, ptr %dest) { ; CHECK-LABEL: store_trunc_v2i256i64: ; CHECK: // %bb.0: +; CHECK-NEXT: ldr d1, [x0, #32] ; CHECK-NEXT: ptrue p0.d, vl1 -; CHECK-NEXT: ldr d0, [x0, #32] -; CHECK-NEXT: ldr d1, [x0] -; CHECK-NEXT: splice z1.d, p0, z1.d, z0.d -; CHECK-NEXT: str q1, [x1] +; CHECK-NEXT: ldr d0, [x0] +; CHECK-NEXT: splice z0.d, p0, { z0.d, z1.d } +; CHECK-NEXT: str q0, [x1] ; CHECK-NEXT: ret ; ; NONEON-NOSVE-LABEL: store_trunc_v2i256i64: diff --git a/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-trunc.ll b/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-trunc.ll index 77aaeeadcfc2f0..9d241f6f927e11 100644 --- a/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-trunc.ll +++ b/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-trunc.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mattr=+sve -force-streaming-compatible < %s | FileCheck %s +; RUN: llc -mattr=+sve2 -force-streaming-compatible < %s | FileCheck %s ; RUN: llc -mattr=+sme -force-streaming < %s | FileCheck %s ; RUN: llc -force-streaming-compatible < %s | FileCheck %s --check-prefix=NONEON-NOSVE @@ -13,11 +13,11 @@ target triple = "aarch64-unknown-linux-gnu" define <16 x i8> @trunc_v16i16_v16i8(ptr %in) nounwind { ; CHECK-LABEL: trunc_v16i16_v16i8: ; CHECK: // %bb.0: -; CHECK-NEXT: ldp q0, q1, [x0] +; CHECK-NEXT: ldp q1, q0, [x0] ; CHECK-NEXT: ptrue p0.b, vl8 -; CHECK-NEXT: uzp1 z1.b, z1.b, z1.b -; CHECK-NEXT: uzp1 z0.b, z0.b, z0.b -; CHECK-NEXT: splice z0.b, p0, z0.b, z1.b +; CHECK-NEXT: uzp1 z3.b, z0.b, z0.b +; CHECK-NEXT: uzp1 z2.b, z1.b, z1.b +; CHECK-NEXT: splice z0.b, p0, { z2.b, z3.b } ; CHECK-NEXT: // kill: def $q0 killed $q0 killed $z0 ; CHECK-NEXT: ret ; @@ -69,18 +69,18 @@ define <16 x i8> @trunc_v16i16_v16i8(ptr %in) nounwind { define void @trunc_v32i16_v32i8(ptr %in, ptr %out) nounwind { ; CHECK-LABEL: trunc_v32i16_v32i8: ; CHECK: // %bb.0: -; CHECK-NEXT: ldp q0, q1, [x0, #32] +; CHECK-NEXT: ldp q1, q0, [x0, #32] ; CHECK-NEXT: ptrue p0.b, vl8 -; CHECK-NEXT: ldp q2, q3, [x0] -; CHECK-NEXT: uzp1 z1.b, z1.b, z1.b -; CHECK-NEXT: uzp1 z0.b, z0.b, z0.b -; CHECK-NEXT: uzp1 z3.b, z3.b, z3.b -; CHECK-NEXT: uzp1 z2.b, z2.b, z2.b -; CHECK-NEXT: splice z0.b, p0, z0.b, z1.b -; CHECK-NEXT: splice z2.b, p0, z2.b, z3.b -; CHECK-NEXT: add z0.b, z0.b, z0.b +; CHECK-NEXT: ldp q3, q2, [x0] +; CHECK-NEXT: uzp1 z5.b, z0.b, z0.b +; CHECK-NEXT: uzp1 z4.b, z1.b, z1.b +; CHECK-NEXT: uzp1 z1.b, z2.b, z2.b +; CHECK-NEXT: uzp1 z0.b, z3.b, z3.b +; CHECK-NEXT: splice z2.b, p0, { z4.b, z5.b } +; CHECK-NEXT: splice z0.b, p0, { z0.b, z1.b } ; CHECK-NEXT: add z1.b, z2.b, z2.b -; CHECK-NEXT: stp q1, q0, [x1] +; CHECK-NEXT: add z0.b, z0.b, z0.b +; CHECK-NEXT: stp q0, q1, [x1] ; CHECK-NEXT: ret ; ; NONEON-NOSVE-LABEL: trunc_v32i16_v32i8: @@ -216,27 +216,27 @@ define void @trunc_v32i16_v32i8(ptr %in, ptr %out) nounwind { define void @trunc_v64i16_v64i8(ptr %in, ptr %out) nounwind { ; CHECK-LABEL: trunc_v64i16_v64i8: ; CHECK: // %bb.0: -; CHECK-NEXT: ldp q0, q1, [x0, #64] +; CHECK-NEXT: ldp q1, q0, [x0, #64] ; CHECK-NEXT: ptrue p0.b, vl8 -; CHECK-NEXT: ldp q2, q3, [x0] -; CHECK-NEXT: ldp q4, q5, [x0, #96] -; CHECK-NEXT: ldp q6, q7, [x0, #32] -; CHECK-NEXT: uzp1 z1.b, z1.b, z1.b -; CHECK-NEXT: uzp1 z0.b, z0.b, z0.b -; CHECK-NEXT: uzp1 z3.b, z3.b, z3.b -; CHECK-NEXT: uzp1 z2.b, z2.b, z2.b -; CHECK-NEXT: uzp1 z5.b, z5.b, z5.b -; CHECK-NEXT: uzp1 z4.b, z4.b, z4.b -; CHECK-NEXT: uzp1 z7.b, z7.b, z7.b -; CHECK-NEXT: uzp1 z6.b, z6.b, z6.b -; CHECK-NEXT: splice z0.b, p0, z0.b, z1.b -; CHECK-NEXT: splice z2.b, p0, z2.b, z3.b -; CHECK-NEXT: splice z4.b, p0, z4.b, z5.b -; CHECK-NEXT: splice z6.b, p0, z6.b, z7.b +; CHECK-NEXT: ldp q2, q3, [x0, #96] +; CHECK-NEXT: ldp q4, q5, [x0] +; CHECK-NEXT: uzp1 z7.b, z0.b, z0.b +; CHECK-NEXT: uzp1 z6.b, z1.b, z1.b +; CHECK-NEXT: ldp q1, q0, [x0, #32] +; CHECK-NEXT: uzp1 z17.b, z3.b, z3.b +; CHECK-NEXT: uzp1 z16.b, z2.b, z2.b +; CHECK-NEXT: uzp1 z3.b, z5.b, z5.b +; CHECK-NEXT: uzp1 z2.b, z4.b, z4.b +; CHECK-NEXT: uzp1 z5.b, z0.b, z0.b +; CHECK-NEXT: splice z0.b, p0, { z6.b, z7.b } +; CHECK-NEXT: uzp1 z4.b, z1.b, z1.b +; CHECK-NEXT: splice z1.b, p0, { z16.b, z17.b } +; CHECK-NEXT: splice z2.b, p0, { z2.b, z3.b } +; CHECK-NEXT: splice z3.b, p0, { z4.b, z5.b } ; CHECK-NEXT: add z0.b, z0.b, z0.b +; CHECK-NEXT: add z1.b, z1.b, z1.b ; CHECK-NEXT: add z2.b, z2.b, z2.b -; CHECK-NEXT: add z1.b, z4.b, z4.b -; CHECK-NEXT: add z3.b, z6.b, z6.b +; CHECK-NEXT: add z3.b, z3.b, z3.b ; CHECK-NEXT: stp q0, q1, [x1, #32] ; CHECK-NEXT: stp q2, q3, [x1] ; CHECK-NEXT: ret @@ -527,49 +527,49 @@ define void @trunc_v128i16_v128i8(ptr %in, ptr %out) nounwind { ; CHECK: // %bb.0: ; CHECK-NEXT: ldp q2, q3, [x0, #192] ; CHECK-NEXT: ptrue p0.b, vl8 +; CHECK-NEXT: ldp q4, q5, [x0] ; CHECK-NEXT: ldp q6, q7, [x0, #64] -; CHECK-NEXT: ldp q16, q17, [x0, #224] -; CHECK-NEXT: uzp1 z3.b, z3.b, z3.b -; CHECK-NEXT: uzp1 z2.b, z2.b, z2.b -; CHECK-NEXT: ldp q20, q21, [x0, #160] -; CHECK-NEXT: uzp1 z7.b, z7.b, z7.b +; CHECK-NEXT: uzp1 z17.b, z3.b, z3.b +; CHECK-NEXT: ldp q3, q18, [x0, #224] +; CHECK-NEXT: uzp1 z16.b, z2.b, z2.b +; CHECK-NEXT: ldp q2, q19, [x0, #128] ; CHECK-NEXT: ldp q0, q1, [x0, #32] -; CHECK-NEXT: uzp1 z17.b, z17.b, z17.b -; CHECK-NEXT: ldp q4, q5, [x0, #96] -; CHECK-NEXT: uzp1 z16.b, z16.b, z16.b -; CHECK-NEXT: ldp q18, q19, [x0, #128] -; CHECK-NEXT: splice z2.b, p0, z2.b, z3.b -; CHECK-NEXT: uzp1 z3.b, z21.b, z21.b -; CHECK-NEXT: uzp1 z20.b, z20.b, z20.b -; CHECK-NEXT: uzp1 z6.b, z6.b, z6.b -; CHECK-NEXT: ldp q21, q22, [x0] -; CHECK-NEXT: splice z16.b, p0, z16.b, z17.b +; CHECK-NEXT: uzp1 z21.b, z18.b, z18.b +; CHECK-NEXT: ldp q18, q22, [x0, #160] +; CHECK-NEXT: uzp1 z20.b, z3.b, z3.b +; CHECK-NEXT: uzp1 z24.b, z19.b, z19.b +; CHECK-NEXT: ldp q3, q19, [x0, #96] +; CHECK-NEXT: uzp1 z23.b, z2.b, z2.b +; CHECK-NEXT: uzp1 z26.b, z22.b, z22.b +; CHECK-NEXT: splice z2.b, p0, { z16.b, z17.b } +; CHECK-NEXT: uzp1 z17.b, z7.b, z7.b +; CHECK-NEXT: uzp1 z25.b, z18.b, z18.b +; CHECK-NEXT: splice z7.b, p0, { z20.b, z21.b } +; CHECK-NEXT: uzp1 z21.b, z5.b, z5.b ; CHECK-NEXT: uzp1 z19.b, z19.b, z19.b -; CHECK-NEXT: uzp1 z18.b, z18.b, z18.b -; CHECK-NEXT: uzp1 z4.b, z4.b, z4.b -; CHECK-NEXT: splice z20.b, p0, z20.b, z3.b -; CHECK-NEXT: uzp1 z3.b, z5.b, z5.b -; CHECK-NEXT: splice z6.b, p0, z6.b, z7.b -; CHECK-NEXT: uzp1 z5.b, z22.b, z22.b -; CHECK-NEXT: uzp1 z7.b, z21.b, z21.b -; CHECK-NEXT: uzp1 z1.b, z1.b, z1.b -; CHECK-NEXT: uzp1 z0.b, z0.b, z0.b -; CHECK-NEXT: splice z18.b, p0, z18.b, z19.b -; CHECK-NEXT: add z2.b, z2.b, z2.b -; CHECK-NEXT: splice z4.b, p0, z4.b, z3.b -; CHECK-NEXT: add z3.b, z16.b, z16.b -; CHECK-NEXT: splice z7.b, p0, z7.b, z5.b -; CHECK-NEXT: splice z0.b, p0, z0.b, z1.b -; CHECK-NEXT: add z1.b, z20.b, z20.b -; CHECK-NEXT: add z5.b, z18.b, z18.b -; CHECK-NEXT: stp q2, q3, [x1, #96] -; CHECK-NEXT: add z2.b, z6.b, z6.b +; CHECK-NEXT: uzp1 z20.b, z4.b, z4.b +; CHECK-NEXT: uzp1 z5.b, z1.b, z1.b +; CHECK-NEXT: uzp1 z16.b, z6.b, z6.b +; CHECK-NEXT: splice z6.b, p0, { z23.b, z24.b } +; CHECK-NEXT: uzp1 z18.b, z3.b, z3.b +; CHECK-NEXT: splice z3.b, p0, { z25.b, z26.b } +; CHECK-NEXT: uzp1 z4.b, z0.b, z0.b +; CHECK-NEXT: add z0.b, z2.b, z2.b +; CHECK-NEXT: add z7.b, z7.b, z7.b +; CHECK-NEXT: splice z1.b, p0, { z16.b, z17.b } +; CHECK-NEXT: splice z2.b, p0, { z18.b, z19.b } +; CHECK-NEXT: splice z16.b, p0, { z20.b, z21.b } +; CHECK-NEXT: splice z4.b, p0, { z4.b, z5.b } +; CHECK-NEXT: add z6.b, z6.b, z6.b +; CHECK-NEXT: add z3.b, z3.b, z3.b +; CHECK-NEXT: stp q0, q7, [x1, #96] +; CHECK-NEXT: add z0.b, z1.b, z1.b +; CHECK-NEXT: add z1.b, z2.b, z2.b +; CHECK-NEXT: add z2.b, z16.b, z16.b +; CHECK-NEXT: stp q6, q3, [x1, #64] ; CHECK-NEXT: add z3.b, z4.b, z4.b -; CHECK-NEXT: add z4.b, z7.b, z7.b -; CHECK-NEXT: add z0.b, z0.b, z0.b -; CHECK-NEXT: stp q5, q1, [x1, #64] -; CHECK-NEXT: stp q2, q3, [x1, #32] -; CHECK-NEXT: stp q4, q0, [x1] +; CHECK-NEXT: stp q0, q1, [x1, #32] +; CHECK-NEXT: stp q2, q3, [x1] ; CHECK-NEXT: ret ; ; NONEON-NOSVE-LABEL: trunc_v128i16_v128i8: @@ -1181,11 +1181,11 @@ define void @trunc_v128i16_v128i8(ptr %in, ptr %out) nounwind { define <8 x i8> @trunc_v8i32_v8i8(ptr %in) nounwind { ; CHECK-LABEL: trunc_v8i32_v8i8: ; CHECK: // %bb.0: -; CHECK-NEXT: ldp q0, q1, [x0] +; CHECK-NEXT: ldp q1, q0, [x0] ; CHECK-NEXT: ptrue p0.h, vl4 -; CHECK-NEXT: uzp1 z1.h, z1.h, z1.h -; CHECK-NEXT: uzp1 z0.h, z0.h, z0.h -; CHECK-NEXT: splice z0.h, p0, z0.h, z1.h +; CHECK-NEXT: uzp1 z3.h, z0.h, z0.h +; CHECK-NEXT: uzp1 z2.h, z1.h, z1.h +; CHECK-NEXT: splice z0.h, p0, { z2.h, z3.h } ; CHECK-NEXT: uzp1 z0.b, z0.b, z0.b ; CHECK-NEXT: // kill: def $d0 killed $d0 killed $z0 ; CHECK-NEXT: ret @@ -1219,17 +1219,17 @@ define <16 x i8> @trunc_v16i32_v16i8(ptr %in) nounwind { ; CHECK: // %bb.0: ; CHECK-NEXT: ldp q1, q0, [x0, #32] ; CHECK-NEXT: ptrue p0.h, vl4 -; CHECK-NEXT: ldp q2, q3, [x0] -; CHECK-NEXT: uzp1 z0.h, z0.h, z0.h -; CHECK-NEXT: uzp1 z1.h, z1.h, z1.h -; CHECK-NEXT: uzp1 z3.h, z3.h, z3.h -; CHECK-NEXT: uzp1 z2.h, z2.h, z2.h -; CHECK-NEXT: splice z1.h, p0, z1.h, z0.h -; CHECK-NEXT: splice z2.h, p0, z2.h, z3.h +; CHECK-NEXT: ldp q3, q2, [x0] +; CHECK-NEXT: uzp1 z5.h, z0.h, z0.h +; CHECK-NEXT: uzp1 z4.h, z1.h, z1.h +; CHECK-NEXT: uzp1 z1.h, z2.h, z2.h +; CHECK-NEXT: uzp1 z0.h, z3.h, z3.h +; CHECK-NEXT: splice z2.h, p0, { z4.h, z5.h } +; CHECK-NEXT: splice z0.h, p0, { z0.h, z1.h } ; CHECK-NEXT: ptrue p0.b, vl8 -; CHECK-NEXT: uzp1 z1.b, z1.b, z1.b -; CHECK-NEXT: uzp1 z0.b, z2.b, z2.b -; CHECK-NEXT: splice z0.b, p0, z0.b, z1.b +; CHECK-NEXT: uzp1 z2.b, z2.b, z2.b +; CHECK-NEXT: uzp1 z1.b, z0.b, z0.b +; CHECK-NEXT: splice z0.b, p0, { z1.b, z2.b } ; CHECK-NEXT: // kill: def $q0 killed $q0 killed $z0 ; CHECK-NEXT: ret ; @@ -1277,32 +1277,32 @@ define <16 x i8> @trunc_v16i32_v16i8(ptr %in) nounwind { define void @trunc_v32i32_v32i8(ptr %in, ptr %out) nounwind { ; CHECK-LABEL: trunc_v32i32_v32i8: ; CHECK: // %bb.0: -; CHECK-NEXT: ldp q0, q1, [x0, #32] +; CHECK-NEXT: ldp q0, q1, [x0, #96] ; CHECK-NEXT: ptrue p0.h, vl4 -; CHECK-NEXT: ldp q2, q3, [x0, #96] +; CHECK-NEXT: ldp q2, q3, [x0, #32] ; CHECK-NEXT: ldp q4, q5, [x0, #64] ; CHECK-NEXT: ldp q6, q7, [x0] -; CHECK-NEXT: uzp1 z1.h, z1.h, z1.h -; CHECK-NEXT: uzp1 z3.h, z3.h, z3.h -; CHECK-NEXT: uzp1 z2.h, z2.h, z2.h -; CHECK-NEXT: uzp1 z0.h, z0.h, z0.h -; CHECK-NEXT: uzp1 z5.h, z5.h, z5.h -; CHECK-NEXT: uzp1 z4.h, z4.h, z4.h -; CHECK-NEXT: uzp1 z7.h, z7.h, z7.h -; CHECK-NEXT: uzp1 z6.h, z6.h, z6.h -; CHECK-NEXT: splice z2.h, p0, z2.h, z3.h -; CHECK-NEXT: splice z0.h, p0, z0.h, z1.h -; CHECK-NEXT: splice z4.h, p0, z4.h, z5.h -; CHECK-NEXT: splice z6.h, p0, z6.h, z7.h +; CHECK-NEXT: uzp1 z17.h, z1.h, z1.h +; CHECK-NEXT: uzp1 z16.h, z0.h, z0.h +; CHECK-NEXT: uzp1 z1.h, z3.h, z3.h +; CHECK-NEXT: uzp1 z19.h, z5.h, z5.h +; CHECK-NEXT: uzp1 z0.h, z2.h, z2.h +; CHECK-NEXT: uzp1 z3.h, z7.h, z7.h +; CHECK-NEXT: uzp1 z18.h, z4.h, z4.h +; CHECK-NEXT: uzp1 z2.h, z6.h, z6.h +; CHECK-NEXT: splice z4.h, p0, { z16.h, z17.h } +; CHECK-NEXT: splice z0.h, p0, { z0.h, z1.h } +; CHECK-NEXT: splice z5.h, p0, { z18.h, z19.h } +; CHECK-NEXT: splice z1.h, p0, { z2.h, z3.h } ; CHECK-NEXT: ptrue p0.b, vl8 -; CHECK-NEXT: uzp1 z1.b, z2.b, z2.b -; CHECK-NEXT: uzp1 z0.b, z0.b, z0.b -; CHECK-NEXT: uzp1 z2.b, z4.b, z4.b -; CHECK-NEXT: uzp1 z3.b, z6.b, z6.b -; CHECK-NEXT: splice z2.b, p0, z2.b, z1.b -; CHECK-NEXT: splice z3.b, p0, z3.b, z0.b -; CHECK-NEXT: add z0.b, z2.b, z2.b -; CHECK-NEXT: add z1.b, z3.b, z3.b +; CHECK-NEXT: uzp1 z3.b, z4.b, z4.b +; CHECK-NEXT: uzp1 z7.b, z0.b, z0.b +; CHECK-NEXT: uzp1 z2.b, z5.b, z5.b +; CHECK-NEXT: uzp1 z6.b, z1.b, z1.b +; CHECK-NEXT: splice z0.b, p0, { z2.b, z3.b } +; CHECK-NEXT: splice z1.b, p0, { z6.b, z7.b } +; CHECK-NEXT: add z0.b, z0.b, z0.b +; CHECK-NEXT: add z1.b, z1.b, z1.b ; CHECK-NEXT: stp q1, q0, [x1] ; CHECK-NEXT: ret ; @@ -1429,56 +1429,56 @@ define void @trunc_v64i32_v64i8(ptr %in, ptr %out) nounwind { ; CHECK: // %bb.0: ; CHECK-NEXT: ldp q2, q3, [x0, #160] ; CHECK-NEXT: ptrue p0.h, vl4 -; CHECK-NEXT: ldp q4, q5, [x0, #128] +; CHECK-NEXT: ldp q4, q5, [x0, #96] +; CHECK-NEXT: ldp q6, q7, [x0] +; CHECK-NEXT: uzp1 z17.h, z3.h, z3.h +; CHECK-NEXT: ldp q3, q18, [x0, #128] +; CHECK-NEXT: uzp1 z16.h, z2.h, z2.h +; CHECK-NEXT: ldp q2, q19, [x0, #192] ; CHECK-NEXT: ldp q0, q1, [x0, #64] -; CHECK-NEXT: ldp q6, q7, [x0, #96] -; CHECK-NEXT: uzp1 z3.h, z3.h, z3.h -; CHECK-NEXT: uzp1 z2.h, z2.h, z2.h -; CHECK-NEXT: uzp1 z5.h, z5.h, z5.h -; CHECK-NEXT: uzp1 z4.h, z4.h, z4.h -; CHECK-NEXT: ldp q16, q17, [x0] -; CHECK-NEXT: uzp1 z1.h, z1.h, z1.h -; CHECK-NEXT: ldp q18, q19, [x0, #192] -; CHECK-NEXT: uzp1 z7.h, z7.h, z7.h -; CHECK-NEXT: ldp q20, q21, [x0, #224] -; CHECK-NEXT: splice z2.h, p0, z2.h, z3.h -; CHECK-NEXT: ldp q22, q23, [x0, #32] -; CHECK-NEXT: splice z4.h, p0, z4.h, z5.h -; CHECK-NEXT: uzp1 z19.h, z19.h, z19.h -; CHECK-NEXT: uzp1 z18.h, z18.h, z18.h -; CHECK-NEXT: uzp1 z17.h, z17.h, z17.h -; CHECK-NEXT: uzp1 z3.h, z21.h, z21.h -; CHECK-NEXT: uzp1 z5.h, z20.h, z20.h -; CHECK-NEXT: uzp1 z16.h, z16.h, z16.h -; CHECK-NEXT: uzp1 z20.h, z23.h, z23.h -; CHECK-NEXT: uzp1 z21.h, z22.h, z22.h -; CHECK-NEXT: uzp1 z6.h, z6.h, z6.h -; CHECK-NEXT: uzp1 z0.h, z0.h, z0.h -; CHECK-NEXT: splice z18.h, p0, z18.h, z19.h -; CHECK-NEXT: splice z5.h, p0, z5.h, z3.h -; CHECK-NEXT: splice z16.h, p0, z16.h, z17.h -; CHECK-NEXT: splice z21.h, p0, z21.h, z20.h -; CHECK-NEXT: splice z6.h, p0, z6.h, z7.h -; CHECK-NEXT: splice z0.h, p0, z0.h, z1.h -; CHECK-NEXT: uzp1 z1.b, z2.b, z2.b -; CHECK-NEXT: uzp1 z2.b, z4.b, z4.b +; CHECK-NEXT: uzp1 z21.h, z18.h, z18.h +; CHECK-NEXT: ldp q18, q22, [x0, #224] +; CHECK-NEXT: uzp1 z20.h, z3.h, z3.h +; CHECK-NEXT: ldp q3, q23, [x0, #32] +; CHECK-NEXT: splice z16.h, p0, { z16.h, z17.h } +; CHECK-NEXT: uzp1 z27.h, z19.h, z19.h +; CHECK-NEXT: uzp1 z25.h, z22.h, z22.h +; CHECK-NEXT: uzp1 z26.h, z2.h, z2.h +; CHECK-NEXT: uzp1 z24.h, z18.h, z18.h +; CHECK-NEXT: uzp1 z18.h, z23.h, z23.h +; CHECK-NEXT: uzp1 z23.h, z5.h, z5.h +; CHECK-NEXT: uzp1 z17.h, z3.h, z3.h +; CHECK-NEXT: uzp1 z3.h, z7.h, z7.h +; CHECK-NEXT: uzp1 z22.h, z4.h, z4.h +; CHECK-NEXT: uzp1 z2.h, z6.h, z6.h +; CHECK-NEXT: uzp1 z5.h, z1.h, z1.h +; CHECK-NEXT: splice z1.h, p0, { z20.h, z21.h } +; CHECK-NEXT: splice z6.h, p0, { z24.h, z25.h } +; CHECK-NEXT: uzp1 z4.h, z0.h, z0.h +; CHECK-NEXT: splice z0.h, p0, { z26.h, z27.h } +; CHECK-NEXT: splice z7.h, p0, { z17.h, z18.h } +; CHECK-NEXT: uzp1 z17.b, z16.b, z16.b +; CHECK-NEXT: splice z2.h, p0, { z2.h, z3.h } +; CHECK-NEXT: splice z3.h, p0, { z22.h, z23.h } +; CHECK-NEXT: splice z4.h, p0, { z4.h, z5.h } +; CHECK-NEXT: uzp1 z16.b, z1.b, z1.b ; CHECK-NEXT: ptrue p0.b, vl8 -; CHECK-NEXT: uzp1 z4.b, z18.b, z18.b -; CHECK-NEXT: uzp1 z3.b, z5.b, z5.b -; CHECK-NEXT: uzp1 z7.b, z16.b, z16.b -; CHECK-NEXT: uzp1 z5.b, z21.b, z21.b -; CHECK-NEXT: splice z2.b, p0, z2.b, z1.b -; CHECK-NEXT: uzp1 z1.b, z6.b, z6.b -; CHECK-NEXT: uzp1 z0.b, z0.b, z0.b -; CHECK-NEXT: splice z4.b, p0, z4.b, z3.b -; CHECK-NEXT: splice z7.b, p0, z7.b, z5.b -; CHECK-NEXT: splice z0.b, p0, z0.b, z1.b -; CHECK-NEXT: add z1.b, z2.b, z2.b -; CHECK-NEXT: add z2.b, z4.b, z4.b -; CHECK-NEXT: add z3.b, z7.b, z7.b +; CHECK-NEXT: uzp1 z6.b, z6.b, z6.b +; CHECK-NEXT: uzp1 z5.b, z0.b, z0.b +; CHECK-NEXT: uzp1 z1.b, z7.b, z7.b +; CHECK-NEXT: uzp1 z0.b, z2.b, z2.b +; CHECK-NEXT: uzp1 z3.b, z3.b, z3.b +; CHECK-NEXT: splice z7.b, p0, { z16.b, z17.b } +; CHECK-NEXT: uzp1 z2.b, z4.b, z4.b +; CHECK-NEXT: splice z4.b, p0, { z5.b, z6.b } +; CHECK-NEXT: splice z0.b, p0, { z0.b, z1.b } +; CHECK-NEXT: splice z1.b, p0, { z2.b, z3.b } +; CHECK-NEXT: add z2.b, z7.b, z7.b +; CHECK-NEXT: add z3.b, z4.b, z4.b ; CHECK-NEXT: add z0.b, z0.b, z0.b -; CHECK-NEXT: stp q1, q2, [x1, #32] -; CHECK-NEXT: stp q3, q0, [x1] +; CHECK-NEXT: add z1.b, z1.b, z1.b +; CHECK-NEXT: stp q2, q3, [x1, #32] +; CHECK-NEXT: stp q0, q1, [x1] ; CHECK-NEXT: ret ; ; NONEON-NOSVE-LABEL: trunc_v64i32_v64i8: @@ -1765,11 +1765,11 @@ define void @trunc_v64i32_v64i8(ptr %in, ptr %out) nounwind { define <8 x i16> @trunc_v8i32_v8i16(ptr %in) nounwind { ; CHECK-LABEL: trunc_v8i32_v8i16: ; CHECK: // %bb.0: -; CHECK-NEXT: ldp q0, q1, [x0] +; CHECK-NEXT: ldp q1, q0, [x0] ; CHECK-NEXT: ptrue p0.h, vl4 -; CHECK-NEXT: uzp1 z1.h, z1.h, z1.h -; CHECK-NEXT: uzp1 z0.h, z0.h, z0.h -; CHECK-NEXT: splice z0.h, p0, z0.h, z1.h +; CHECK-NEXT: uzp1 z3.h, z0.h, z0.h +; CHECK-NEXT: uzp1 z2.h, z1.h, z1.h +; CHECK-NEXT: splice z0.h, p0, { z2.h, z3.h } ; CHECK-NEXT: // kill: def $q0 killed $q0 killed $z0 ; CHECK-NEXT: ret ; @@ -1801,18 +1801,18 @@ define <8 x i16> @trunc_v8i32_v8i16(ptr %in) nounwind { define void @trunc_v16i32_v16i16(ptr %in, ptr %out) nounwind { ; CHECK-LABEL: trunc_v16i32_v16i16: ; CHECK: // %bb.0: -; CHECK-NEXT: ldp q0, q1, [x0, #32] +; CHECK-NEXT: ldp q1, q0, [x0, #32] ; CHECK-NEXT: ptrue p0.h, vl4 -; CHECK-NEXT: ldp q2, q3, [x0] -; CHECK-NEXT: uzp1 z1.h, z1.h, z1.h -; CHECK-NEXT: uzp1 z0.h, z0.h, z0.h -; CHECK-NEXT: uzp1 z3.h, z3.h, z3.h -; CHECK-NEXT: uzp1 z2.h, z2.h, z2.h -; CHECK-NEXT: splice z0.h, p0, z0.h, z1.h -; CHECK-NEXT: splice z2.h, p0, z2.h, z3.h -; CHECK-NEXT: add z0.h, z0.h, z0.h +; CHECK-NEXT: ldp q3, q2, [x0] +; CHECK-NEXT: uzp1 z5.h, z0.h, z0.h +; CHECK-NEXT: uzp1 z4.h, z1.h, z1.h +; CHECK-NEXT: uzp1 z1.h, z2.h, z2.h +; CHECK-NEXT: uzp1 z0.h, z3.h, z3.h +; CHECK-NEXT: splice z2.h, p0, { z4.h, z5.h } +; CHECK-NEXT: splice z0.h, p0, { z0.h, z1.h } ; CHECK-NEXT: add z1.h, z2.h, z2.h -; CHECK-NEXT: stp q1, q0, [x1] +; CHECK-NEXT: add z0.h, z0.h, z0.h +; CHECK-NEXT: stp q0, q1, [x1] ; CHECK-NEXT: ret ; ; NONEON-NOSVE-LABEL: trunc_v16i32_v16i16: @@ -1877,27 +1877,27 @@ define void @trunc_v16i32_v16i16(ptr %in, ptr %out) nounwind { define void @trunc_v32i32_v32i16(ptr %in, ptr %out) nounwind { ; CHECK-LABEL: trunc_v32i32_v32i16: ; CHECK: // %bb.0: -; CHECK-NEXT: ldp q0, q1, [x0, #64] +; CHECK-NEXT: ldp q1, q0, [x0, #64] ; CHECK-NEXT: ptrue p0.h, vl4 -; CHECK-NEXT: ldp q2, q3, [x0] -; CHECK-NEXT: ldp q4, q5, [x0, #96] -; CHECK-NEXT: ldp q6, q7, [x0, #32] -; CHECK-NEXT: uzp1 z1.h, z1.h, z1.h -; CHECK-NEXT: uzp1 z0.h, z0.h, z0.h -; CHECK-NEXT: uzp1 z3.h, z3.h, z3.h -; CHECK-NEXT: uzp1 z2.h, z2.h, z2.h -; CHECK-NEXT: uzp1 z5.h, z5.h, z5.h -; CHECK-NEXT: uzp1 z4.h, z4.h, z4.h -; CHECK-NEXT: uzp1 z7.h, z7.h, z7.h -; CHECK-NEXT: uzp1 z6.h, z6.h, z6.h -; CHECK-NEXT: splice z0.h, p0, z0.h, z1.h -; CHECK-NEXT: splice z2.h, p0, z2.h, z3.h -; CHECK-NEXT: splice z4.h, p0, z4.h, z5.h -; CHECK-NEXT: splice z6.h, p0, z6.h, z7.h +; CHECK-NEXT: ldp q2, q3, [x0, #96] +; CHECK-NEXT: ldp q4, q5, [x0] +; CHECK-NEXT: uzp1 z7.h, z0.h, z0.h +; CHECK-NEXT: uzp1 z6.h, z1.h, z1.h +; CHECK-NEXT: ldp q1, q0, [x0, #32] +; CHECK-NEXT: uzp1 z17.h, z3.h, z3.h +; CHECK-NEXT: uzp1 z16.h, z2.h, z2.h +; CHECK-NEXT: uzp1 z3.h, z5.h, z5.h +; CHECK-NEXT: uzp1 z2.h, z4.h, z4.h +; CHECK-NEXT: uzp1 z5.h, z0.h, z0.h +; CHECK-NEXT: splice z0.h, p0, { z6.h, z7.h } +; CHECK-NEXT: uzp1 z4.h, z1.h, z1.h +; CHECK-NEXT: splice z1.h, p0, { z16.h, z17.h } +; CHECK-NEXT: splice z2.h, p0, { z2.h, z3.h } +; CHECK-NEXT: splice z3.h, p0, { z4.h, z5.h } ; CHECK-NEXT: add z0.h, z0.h, z0.h +; CHECK-NEXT: add z1.h, z1.h, z1.h ; CHECK-NEXT: add z2.h, z2.h, z2.h -; CHECK-NEXT: add z1.h, z4.h, z4.h -; CHECK-NEXT: add z3.h, z6.h, z6.h +; CHECK-NEXT: add z3.h, z3.h, z3.h ; CHECK-NEXT: stp q0, q1, [x1, #32] ; CHECK-NEXT: stp q2, q3, [x1] ; CHECK-NEXT: ret @@ -2027,49 +2027,49 @@ define void @trunc_v64i32_v64i16(ptr %in, ptr %out) nounwind { ; CHECK: // %bb.0: ; CHECK-NEXT: ldp q2, q3, [x0, #192] ; CHECK-NEXT: ptrue p0.h, vl4 +; CHECK-NEXT: ldp q4, q5, [x0] ; CHECK-NEXT: ldp q6, q7, [x0, #64] -; CHECK-NEXT: ldp q16, q17, [x0, #224] -; CHECK-NEXT: uzp1 z3.h, z3.h, z3.h -; CHECK-NEXT: uzp1 z2.h, z2.h, z2.h -; CHECK-NEXT: ldp q20, q21, [x0, #160] -; CHECK-NEXT: uzp1 z7.h, z7.h, z7.h +; CHECK-NEXT: uzp1 z17.h, z3.h, z3.h +; CHECK-NEXT: ldp q3, q18, [x0, #224] +; CHECK-NEXT: uzp1 z16.h, z2.h, z2.h +; CHECK-NEXT: ldp q2, q19, [x0, #128] ; CHECK-NEXT: ldp q0, q1, [x0, #32] -; CHECK-NEXT: uzp1 z17.h, z17.h, z17.h -; CHECK-NEXT: ldp q4, q5, [x0, #96] -; CHECK-NEXT: uzp1 z16.h, z16.h, z16.h -; CHECK-NEXT: ldp q18, q19, [x0, #128] -; CHECK-NEXT: splice z2.h, p0, z2.h, z3.h -; CHECK-NEXT: uzp1 z3.h, z21.h, z21.h -; CHECK-NEXT: uzp1 z20.h, z20.h, z20.h -; CHECK-NEXT: uzp1 z6.h, z6.h, z6.h -; CHECK-NEXT: ldp q21, q22, [x0] -; CHECK-NEXT: splice z16.h, p0, z16.h, z17.h +; CHECK-NEXT: uzp1 z21.h, z18.h, z18.h +; CHECK-NEXT: ldp q18, q22, [x0, #160] +; CHECK-NEXT: uzp1 z20.h, z3.h, z3.h +; CHECK-NEXT: uzp1 z24.h, z19.h, z19.h +; CHECK-NEXT: ldp q3, q19, [x0, #96] +; CHECK-NEXT: uzp1 z23.h, z2.h, z2.h +; CHECK-NEXT: uzp1 z26.h, z22.h, z22.h +; CHECK-NEXT: splice z2.h, p0, { z16.h, z17.h } +; CHECK-NEXT: uzp1 z17.h, z7.h, z7.h +; CHECK-NEXT: uzp1 z25.h, z18.h, z18.h +; CHECK-NEXT: splice z7.h, p0, { z20.h, z21.h } +; CHECK-NEXT: uzp1 z21.h, z5.h, z5.h ; CHECK-NEXT: uzp1 z19.h, z19.h, z19.h -; CHECK-NEXT: uzp1 z18.h, z18.h, z18.h -; CHECK-NEXT: uzp1 z4.h, z4.h, z4.h -; CHECK-NEXT: splice z20.h, p0, z20.h, z3.h -; CHECK-NEXT: uzp1 z3.h, z5.h, z5.h -; CHECK-NEXT: splice z6.h, p0, z6.h, z7.h -; CHECK-NEXT: uzp1 z5.h, z22.h, z22.h -; CHECK-NEXT: uzp1 z7.h, z21.h, z21.h -; CHECK-NEXT: uzp1 z1.h, z1.h, z1.h -; CHECK-NEXT: uzp1 z0.h, z0.h, z0.h -; CHECK-NEXT: splice z18.h, p0, z18.h, z19.h -; CHECK-NEXT: add z2.h, z2.h, z2.h -; CHECK-NEXT: splice z4.h, p0, z4.h, z3.h -; CHECK-NEXT: add z3.h, z16.h, z16.h -; CHECK-NEXT: splice z7.h, p0, z7.h, z5.h -; CHECK-NEXT: splice z0.h, p0, z0.h, z1.h -; CHECK-NEXT: add z1.h, z20.h, z20.h -; CHECK-NEXT: add z5.h, z18.h, z18.h -; CHECK-NEXT: stp q2, q3, [x1, #96] -; CHECK-NEXT: add z2.h, z6.h, z6.h +; CHECK-NEXT: uzp1 z20.h, z4.h, z4.h +; CHECK-NEXT: uzp1 z5.h, z1.h, z1.h +; CHECK-NEXT: uzp1 z16.h, z6.h, z6.h +; CHECK-NEXT: splice z6.h, p0, { z23.h, z24.h } +; CHECK-NEXT: uzp1 z18.h, z3.h, z3.h +; CHECK-NEXT: splice z3.h, p0, { z25.h, z26.h } +; CHECK-NEXT: uzp1 z4.h, z0.h, z0.h +; CHECK-NEXT: add z0.h, z2.h, z2.h +; CHECK-NEXT: add z7.h, z7.h, z7.h +; CHECK-NEXT: splice z1.h, p0, { z16.h, z17.h } +; CHECK-NEXT: splice z2.h, p0, { z18.h, z19.h } +; CHECK-NEXT: splice z16.h, p0, { z20.h, z21.h } +; CHECK-NEXT: splice z4.h, p0, { z4.h, z5.h } +; CHECK-NEXT: add z6.h, z6.h, z6.h +; CHECK-NEXT: add z3.h, z3.h, z3.h +; CHECK-NEXT: stp q0, q7, [x1, #96] +; CHECK-NEXT: add z0.h, z1.h, z1.h +; CHECK-NEXT: add z1.h, z2.h, z2.h +; CHECK-NEXT: add z2.h, z16.h, z16.h +; CHECK-NEXT: stp q6, q3, [x1, #64] ; CHECK-NEXT: add z3.h, z4.h, z4.h -; CHECK-NEXT: add z4.h, z7.h, z7.h -; CHECK-NEXT: add z0.h, z0.h, z0.h -; CHECK-NEXT: stp q5, q1, [x1, #64] -; CHECK-NEXT: stp q2, q3, [x1, #32] -; CHECK-NEXT: stp q4, q0, [x1] +; CHECK-NEXT: stp q0, q1, [x1, #32] +; CHECK-NEXT: stp q2, q3, [x1] ; CHECK-NEXT: ret ; ; NONEON-NOSVE-LABEL: trunc_v64i32_v64i16: @@ -2360,11 +2360,11 @@ define void @trunc_v64i32_v64i16(ptr %in, ptr %out) nounwind { define <4 x i8> @trunc_v4i64_v4i8(ptr %in) nounwind { ; CHECK-LABEL: trunc_v4i64_v4i8: ; CHECK: // %bb.0: -; CHECK-NEXT: ldp q0, q1, [x0] +; CHECK-NEXT: ldp q1, q0, [x0] ; CHECK-NEXT: ptrue p0.s, vl2 -; CHECK-NEXT: uzp1 z1.s, z1.s, z1.s -; CHECK-NEXT: uzp1 z0.s, z0.s, z0.s -; CHECK-NEXT: splice z0.s, p0, z0.s, z1.s +; CHECK-NEXT: uzp1 z3.s, z0.s, z0.s +; CHECK-NEXT: uzp1 z2.s, z1.s, z1.s +; CHECK-NEXT: splice z0.s, p0, { z2.s, z3.s } ; CHECK-NEXT: uzp1 z0.h, z0.h, z0.h ; CHECK-NEXT: // kill: def $d0 killed $d0 killed $z0 ; CHECK-NEXT: ret @@ -2392,18 +2392,18 @@ define <8 x i8> @trunc_v8i64_v8i8(ptr %in) nounwind { ; CHECK: // %bb.0: ; CHECK-NEXT: ldp q1, q0, [x0, #32] ; CHECK-NEXT: ptrue p0.s, vl2 -; CHECK-NEXT: ldp q2, q3, [x0] -; CHECK-NEXT: uzp1 z0.s, z0.s, z0.s -; CHECK-NEXT: uzp1 z1.s, z1.s, z1.s -; CHECK-NEXT: uzp1 z3.s, z3.s, z3.s -; CHECK-NEXT: uzp1 z2.s, z2.s, z2.s -; CHECK-NEXT: splice z1.s, p0, z1.s, z0.s -; CHECK-NEXT: splice z2.s, p0, z2.s, z3.s +; CHECK-NEXT: ldp q3, q2, [x0] +; CHECK-NEXT: uzp1 z5.s, z0.s, z0.s +; CHECK-NEXT: uzp1 z4.s, z1.s, z1.s +; CHECK-NEXT: uzp1 z1.s, z2.s, z2.s +; CHECK-NEXT: uzp1 z0.s, z3.s, z3.s +; CHECK-NEXT: splice z2.s, p0, { z4.s, z5.s } +; CHECK-NEXT: splice z0.s, p0, { z0.s, z1.s } ; CHECK-NEXT: ptrue p0.h, vl4 -; CHECK-NEXT: uzp1 z0.h, z1.h, z1.h -; CHECK-NEXT: uzp1 z1.h, z2.h, z2.h -; CHECK-NEXT: splice z1.h, p0, z1.h, z0.h -; CHECK-NEXT: uzp1 z0.b, z1.b, z1.b +; CHECK-NEXT: uzp1 z2.h, z2.h, z2.h +; CHECK-NEXT: uzp1 z1.h, z0.h, z0.h +; CHECK-NEXT: splice z0.h, p0, { z1.h, z2.h } +; CHECK-NEXT: uzp1 z0.b, z0.b, z0.b ; CHECK-NEXT: // kill: def $d0 killed $d0 killed $z0 ; CHECK-NEXT: ret ; @@ -2439,34 +2439,34 @@ define <8 x i8> @trunc_v8i64_v8i8(ptr %in) nounwind { define <16 x i8> @trunc_v16i64_v16i8(ptr %in) nounwind { ; CHECK-LABEL: trunc_v16i64_v16i8: ; CHECK: // %bb.0: -; CHECK-NEXT: ldp q0, q1, [x0, #32] +; CHECK-NEXT: ldp q0, q1, [x0, #96] ; CHECK-NEXT: ptrue p0.s, vl2 -; CHECK-NEXT: ldp q2, q3, [x0, #96] +; CHECK-NEXT: ldp q2, q3, [x0, #32] ; CHECK-NEXT: ldp q4, q5, [x0, #64] ; CHECK-NEXT: ldp q6, q7, [x0] -; CHECK-NEXT: uzp1 z1.s, z1.s, z1.s -; CHECK-NEXT: uzp1 z3.s, z3.s, z3.s -; CHECK-NEXT: uzp1 z2.s, z2.s, z2.s -; CHECK-NEXT: uzp1 z0.s, z0.s, z0.s -; CHECK-NEXT: uzp1 z5.s, z5.s, z5.s -; CHECK-NEXT: uzp1 z4.s, z4.s, z4.s -; CHECK-NEXT: uzp1 z7.s, z7.s, z7.s -; CHECK-NEXT: uzp1 z6.s, z6.s, z6.s -; CHECK-NEXT: splice z2.s, p0, z2.s, z3.s -; CHECK-NEXT: splice z0.s, p0, z0.s, z1.s -; CHECK-NEXT: splice z4.s, p0, z4.s, z5.s -; CHECK-NEXT: splice z6.s, p0, z6.s, z7.s +; CHECK-NEXT: uzp1 z17.s, z1.s, z1.s +; CHECK-NEXT: uzp1 z16.s, z0.s, z0.s +; CHECK-NEXT: uzp1 z19.s, z3.s, z3.s +; CHECK-NEXT: uzp1 z1.s, z5.s, z5.s +; CHECK-NEXT: uzp1 z18.s, z2.s, z2.s +; CHECK-NEXT: uzp1 z0.s, z4.s, z4.s +; CHECK-NEXT: uzp1 z3.s, z7.s, z7.s +; CHECK-NEXT: uzp1 z2.s, z6.s, z6.s +; CHECK-NEXT: splice z4.s, p0, { z16.s, z17.s } +; CHECK-NEXT: splice z0.s, p0, { z0.s, z1.s } +; CHECK-NEXT: splice z1.s, p0, { z18.s, z19.s } +; CHECK-NEXT: splice z2.s, p0, { z2.s, z3.s } ; CHECK-NEXT: ptrue p0.h, vl4 -; CHECK-NEXT: uzp1 z1.h, z2.h, z2.h -; CHECK-NEXT: uzp1 z0.h, z0.h, z0.h -; CHECK-NEXT: uzp1 z2.h, z4.h, z4.h -; CHECK-NEXT: uzp1 z3.h, z6.h, z6.h -; CHECK-NEXT: splice z2.h, p0, z2.h, z1.h -; CHECK-NEXT: splice z3.h, p0, z3.h, z0.h +; CHECK-NEXT: uzp1 z4.h, z4.h, z4.h +; CHECK-NEXT: uzp1 z3.h, z0.h, z0.h +; CHECK-NEXT: uzp1 z1.h, z1.h, z1.h +; CHECK-NEXT: uzp1 z0.h, z2.h, z2.h +; CHECK-NEXT: splice z2.h, p0, { z3.h, z4.h } +; CHECK-NEXT: splice z0.h, p0, { z0.h, z1.h } ; CHECK-NEXT: ptrue p0.b, vl8 -; CHECK-NEXT: uzp1 z1.b, z2.b, z2.b -; CHECK-NEXT: uzp1 z0.b, z3.b, z3.b -; CHECK-NEXT: splice z0.b, p0, z0.b, z1.b +; CHECK-NEXT: uzp1 z2.b, z2.b, z2.b +; CHECK-NEXT: uzp1 z1.b, z0.b, z0.b +; CHECK-NEXT: splice z0.b, p0, { z1.b, z2.b } ; CHECK-NEXT: // kill: def $q0 killed $q0 killed $z0 ; CHECK-NEXT: ret ; @@ -2523,62 +2523,62 @@ define <16 x i8> @trunc_v16i64_v16i8(ptr %in) nounwind { define void @trunc_v32i64_v32i8(ptr %in, ptr %out) nounwind { ; CHECK-LABEL: trunc_v32i64_v32i8: ; CHECK: // %bb.0: -; CHECK-NEXT: ldp q0, q1, [x0] +; CHECK-NEXT: ldp q5, q6, [x0, #224] ; CHECK-NEXT: ptrue p0.s, vl2 -; CHECK-NEXT: ldp q2, q3, [x0, #224] -; CHECK-NEXT: ldp q4, q5, [x0, #32] -; CHECK-NEXT: ldp q6, q7, [x0, #64] -; CHECK-NEXT: uzp1 z1.s, z1.s, z1.s -; CHECK-NEXT: ldp q16, q17, [x0, #192] -; CHECK-NEXT: uzp1 z3.s, z3.s, z3.s -; CHECK-NEXT: ldp q18, q19, [x0, #128] -; CHECK-NEXT: uzp1 z2.s, z2.s, z2.s -; CHECK-NEXT: ldp q20, q21, [x0, #160] -; CHECK-NEXT: uzp1 z7.s, z7.s, z7.s -; CHECK-NEXT: ldp q22, q23, [x0, #96] -; CHECK-NEXT: uzp1 z17.s, z17.s, z17.s -; CHECK-NEXT: uzp1 z16.s, z16.s, z16.s -; CHECK-NEXT: uzp1 z19.s, z19.s, z19.s -; CHECK-NEXT: uzp1 z18.s, z18.s, z18.s -; CHECK-NEXT: uzp1 z21.s, z21.s, z21.s -; CHECK-NEXT: uzp1 z20.s, z20.s, z20.s -; CHECK-NEXT: uzp1 z6.s, z6.s, z6.s -; CHECK-NEXT: uzp1 z23.s, z23.s, z23.s -; CHECK-NEXT: uzp1 z22.s, z22.s, z22.s -; CHECK-NEXT: uzp1 z5.s, z5.s, z5.s -; CHECK-NEXT: uzp1 z4.s, z4.s, z4.s -; CHECK-NEXT: uzp1 z0.s, z0.s, z0.s -; CHECK-NEXT: splice z2.s, p0, z2.s, z3.s -; CHECK-NEXT: splice z16.s, p0, z16.s, z17.s -; CHECK-NEXT: splice z20.s, p0, z20.s, z21.s -; CHECK-NEXT: splice z18.s, p0, z18.s, z19.s -; CHECK-NEXT: splice z22.s, p0, z22.s, z23.s -; CHECK-NEXT: splice z6.s, p0, z6.s, z7.s -; CHECK-NEXT: splice z4.s, p0, z4.s, z5.s -; CHECK-NEXT: splice z0.s, p0, z0.s, z1.s +; CHECK-NEXT: ldp q2, q3, [x0, #32] +; CHECK-NEXT: ldp q4, q7, [x0, #64] +; CHECK-NEXT: uzp1 z17.s, z6.s, z6.s +; CHECK-NEXT: ldp q6, q18, [x0, #192] +; CHECK-NEXT: uzp1 z16.s, z5.s, z5.s +; CHECK-NEXT: ldp q5, q19, [x0, #128] +; CHECK-NEXT: ldp q0, q1, [x0] +; CHECK-NEXT: uzp1 z21.s, z18.s, z18.s +; CHECK-NEXT: ldp q18, q22, [x0, #160] +; CHECK-NEXT: uzp1 z20.s, z6.s, z6.s +; CHECK-NEXT: ldp q6, q23, [x0, #96] +; CHECK-NEXT: splice z16.s, p0, { z16.s, z17.s } +; CHECK-NEXT: uzp1 z27.s, z19.s, z19.s +; CHECK-NEXT: uzp1 z25.s, z22.s, z22.s +; CHECK-NEXT: uzp1 z26.s, z5.s, z5.s +; CHECK-NEXT: uzp1 z24.s, z18.s, z18.s +; CHECK-NEXT: uzp1 z18.s, z23.s, z23.s +; CHECK-NEXT: uzp1 z23.s, z3.s, z3.s +; CHECK-NEXT: uzp1 z17.s, z6.s, z6.s +; CHECK-NEXT: uzp1 z6.s, z7.s, z7.s +; CHECK-NEXT: uzp1 z22.s, z2.s, z2.s +; CHECK-NEXT: uzp1 z5.s, z4.s, z4.s +; CHECK-NEXT: uzp1 z2.s, z1.s, z1.s +; CHECK-NEXT: splice z3.s, p0, { z20.s, z21.s } +; CHECK-NEXT: uzp1 z1.s, z0.s, z0.s +; CHECK-NEXT: splice z0.s, p0, { z24.s, z25.s } +; CHECK-NEXT: splice z7.s, p0, { z26.s, z27.s } +; CHECK-NEXT: splice z4.s, p0, { z17.s, z18.s } +; CHECK-NEXT: uzp1 z17.h, z16.h, z16.h +; CHECK-NEXT: splice z5.s, p0, { z5.s, z6.s } +; CHECK-NEXT: splice z6.s, p0, { z22.s, z23.s } +; CHECK-NEXT: splice z1.s, p0, { z1.s, z2.s } +; CHECK-NEXT: uzp1 z16.h, z3.h, z3.h ; CHECK-NEXT: ptrue p0.h, vl4 -; CHECK-NEXT: uzp1 z1.h, z2.h, z2.h -; CHECK-NEXT: uzp1 z2.h, z16.h, z16.h -; CHECK-NEXT: uzp1 z3.h, z20.h, z20.h -; CHECK-NEXT: uzp1 z5.h, z18.h, z18.h -; CHECK-NEXT: uzp1 z7.h, z22.h, z22.h -; CHECK-NEXT: uzp1 z6.h, z6.h, z6.h -; CHECK-NEXT: uzp1 z4.h, z4.h, z4.h -; CHECK-NEXT: uzp1 z0.h, z0.h, z0.h -; CHECK-NEXT: splice z2.h, p0, z2.h, z1.h -; CHECK-NEXT: splice z5.h, p0, z5.h, z3.h -; CHECK-NEXT: splice z6.h, p0, z6.h, z7.h -; CHECK-NEXT: splice z0.h, p0, z0.h, z4.h +; CHECK-NEXT: uzp1 z3.h, z0.h, z0.h +; CHECK-NEXT: uzp1 z19.h, z4.h, z4.h +; CHECK-NEXT: uzp1 z2.h, z7.h, z7.h +; CHECK-NEXT: uzp1 z18.h, z5.h, z5.h +; CHECK-NEXT: uzp1 z5.h, z6.h, z6.h +; CHECK-NEXT: splice z0.h, p0, { z16.h, z17.h } +; CHECK-NEXT: uzp1 z4.h, z1.h, z1.h +; CHECK-NEXT: splice z1.h, p0, { z2.h, z3.h } +; CHECK-NEXT: splice z2.h, p0, { z18.h, z19.h } +; CHECK-NEXT: splice z3.h, p0, { z4.h, z5.h } +; CHECK-NEXT: uzp1 z5.b, z0.b, z0.b ; CHECK-NEXT: ptrue p0.b, vl8 -; CHECK-NEXT: uzp1 z1.b, z2.b, z2.b -; CHECK-NEXT: uzp1 z2.b, z5.b, z5.b -; CHECK-NEXT: uzp1 z3.b, z6.b, z6.b -; CHECK-NEXT: uzp1 z0.b, z0.b, z0.b -; CHECK-NEXT: splice z2.b, p0, z2.b, z1.b -; CHECK-NEXT: splice z0.b, p0, z0.b, z3.b -; CHECK-NEXT: add z1.b, z2.b, z2.b +; CHECK-NEXT: uzp1 z4.b, z1.b, z1.b +; CHECK-NEXT: uzp1 z7.b, z2.b, z2.b +; CHECK-NEXT: uzp1 z6.b, z3.b, z3.b +; CHECK-NEXT: splice z0.b, p0, { z4.b, z5.b } +; CHECK-NEXT: splice z1.b, p0, { z6.b, z7.b } ; CHECK-NEXT: add z0.b, z0.b, z0.b -; CHECK-NEXT: stp q0, q1, [x1] +; CHECK-NEXT: add z1.b, z1.b, z1.b +; CHECK-NEXT: stp q1, q0, [x1] ; CHECK-NEXT: ret ; ; NONEON-NOSVE-LABEL: trunc_v32i64_v32i8: @@ -2731,11 +2731,11 @@ define void @trunc_v32i64_v32i8(ptr %in, ptr %out) nounwind { define <4 x i16> @trunc_v4i64_v4i16(ptr %in) nounwind { ; CHECK-LABEL: trunc_v4i64_v4i16: ; CHECK: // %bb.0: -; CHECK-NEXT: ldp q0, q1, [x0] +; CHECK-NEXT: ldp q1, q0, [x0] ; CHECK-NEXT: ptrue p0.s, vl2 -; CHECK-NEXT: uzp1 z1.s, z1.s, z1.s -; CHECK-NEXT: uzp1 z0.s, z0.s, z0.s -; CHECK-NEXT: splice z0.s, p0, z0.s, z1.s +; CHECK-NEXT: uzp1 z3.s, z0.s, z0.s +; CHECK-NEXT: uzp1 z2.s, z1.s, z1.s +; CHECK-NEXT: splice z0.s, p0, { z2.s, z3.s } ; CHECK-NEXT: uzp1 z0.h, z0.h, z0.h ; CHECK-NEXT: // kill: def $d0 killed $d0 killed $z0 ; CHECK-NEXT: ret @@ -2763,17 +2763,17 @@ define <8 x i16> @trunc_v8i64_v8i16(ptr %in) nounwind { ; CHECK: // %bb.0: ; CHECK-NEXT: ldp q1, q0, [x0, #32] ; CHECK-NEXT: ptrue p0.s, vl2 -; CHECK-NEXT: ldp q2, q3, [x0] -; CHECK-NEXT: uzp1 z0.s, z0.s, z0.s -; CHECK-NEXT: uzp1 z1.s, z1.s, z1.s -; CHECK-NEXT: uzp1 z3.s, z3.s, z3.s -; CHECK-NEXT: uzp1 z2.s, z2.s, z2.s -; CHECK-NEXT: splice z1.s, p0, z1.s, z0.s -; CHECK-NEXT: splice z2.s, p0, z2.s, z3.s +; CHECK-NEXT: ldp q3, q2, [x0] +; CHECK-NEXT: uzp1 z5.s, z0.s, z0.s +; CHECK-NEXT: uzp1 z4.s, z1.s, z1.s +; CHECK-NEXT: uzp1 z1.s, z2.s, z2.s +; CHECK-NEXT: uzp1 z0.s, z3.s, z3.s +; CHECK-NEXT: splice z2.s, p0, { z4.s, z5.s } +; CHECK-NEXT: splice z0.s, p0, { z0.s, z1.s } ; CHECK-NEXT: ptrue p0.h, vl4 -; CHECK-NEXT: uzp1 z1.h, z1.h, z1.h -; CHECK-NEXT: uzp1 z0.h, z2.h, z2.h -; CHECK-NEXT: splice z0.h, p0, z0.h, z1.h +; CHECK-NEXT: uzp1 z2.h, z2.h, z2.h +; CHECK-NEXT: uzp1 z1.h, z0.h, z0.h +; CHECK-NEXT: splice z0.h, p0, { z1.h, z2.h } ; CHECK-NEXT: // kill: def $q0 killed $q0 killed $z0 ; CHECK-NEXT: ret ; @@ -2810,32 +2810,32 @@ define <8 x i16> @trunc_v8i64_v8i16(ptr %in) nounwind { define void @trunc_v16i64_v16i16(ptr %in, ptr %out) nounwind { ; CHECK-LABEL: trunc_v16i64_v16i16: ; CHECK: // %bb.0: -; CHECK-NEXT: ldp q0, q1, [x0, #32] +; CHECK-NEXT: ldp q0, q1, [x0, #96] ; CHECK-NEXT: ptrue p0.s, vl2 -; CHECK-NEXT: ldp q2, q3, [x0, #96] +; CHECK-NEXT: ldp q2, q3, [x0, #32] ; CHECK-NEXT: ldp q4, q5, [x0, #64] ; CHECK-NEXT: ldp q6, q7, [x0] -; CHECK-NEXT: uzp1 z1.s, z1.s, z1.s -; CHECK-NEXT: uzp1 z3.s, z3.s, z3.s -; CHECK-NEXT: uzp1 z2.s, z2.s, z2.s -; CHECK-NEXT: uzp1 z0.s, z0.s, z0.s -; CHECK-NEXT: uzp1 z5.s, z5.s, z5.s -; CHECK-NEXT: uzp1 z4.s, z4.s, z4.s -; CHECK-NEXT: uzp1 z7.s, z7.s, z7.s -; CHECK-NEXT: uzp1 z6.s, z6.s, z6.s -; CHECK-NEXT: splice z2.s, p0, z2.s, z3.s -; CHECK-NEXT: splice z0.s, p0, z0.s, z1.s -; CHECK-NEXT: splice z4.s, p0, z4.s, z5.s -; CHECK-NEXT: splice z6.s, p0, z6.s, z7.s +; CHECK-NEXT: uzp1 z17.s, z1.s, z1.s +; CHECK-NEXT: uzp1 z16.s, z0.s, z0.s +; CHECK-NEXT: uzp1 z1.s, z3.s, z3.s +; CHECK-NEXT: uzp1 z19.s, z5.s, z5.s +; CHECK-NEXT: uzp1 z0.s, z2.s, z2.s +; CHECK-NEXT: uzp1 z3.s, z7.s, z7.s +; CHECK-NEXT: uzp1 z18.s, z4.s, z4.s +; CHECK-NEXT: uzp1 z2.s, z6.s, z6.s +; CHECK-NEXT: splice z4.s, p0, { z16.s, z17.s } +; CHECK-NEXT: splice z0.s, p0, { z0.s, z1.s } +; CHECK-NEXT: splice z5.s, p0, { z18.s, z19.s } +; CHECK-NEXT: splice z1.s, p0, { z2.s, z3.s } ; CHECK-NEXT: ptrue p0.h, vl4 -; CHECK-NEXT: uzp1 z1.h, z2.h, z2.h -; CHECK-NEXT: uzp1 z0.h, z0.h, z0.h -; CHECK-NEXT: uzp1 z2.h, z4.h, z4.h -; CHECK-NEXT: uzp1 z3.h, z6.h, z6.h -; CHECK-NEXT: splice z2.h, p0, z2.h, z1.h -; CHECK-NEXT: splice z3.h, p0, z3.h, z0.h -; CHECK-NEXT: add z0.h, z2.h, z2.h -; CHECK-NEXT: add z1.h, z3.h, z3.h +; CHECK-NEXT: uzp1 z3.h, z4.h, z4.h +; CHECK-NEXT: uzp1 z7.h, z0.h, z0.h +; CHECK-NEXT: uzp1 z2.h, z5.h, z5.h +; CHECK-NEXT: uzp1 z6.h, z1.h, z1.h +; CHECK-NEXT: splice z0.h, p0, { z2.h, z3.h } +; CHECK-NEXT: splice z1.h, p0, { z6.h, z7.h } +; CHECK-NEXT: add z0.h, z0.h, z0.h +; CHECK-NEXT: add z1.h, z1.h, z1.h ; CHECK-NEXT: stp q1, q0, [x1] ; CHECK-NEXT: ret ; @@ -2915,56 +2915,56 @@ define void @trunc_v32i64_v32i16(ptr %in, ptr %out) nounwind { ; CHECK: // %bb.0: ; CHECK-NEXT: ldp q2, q3, [x0, #160] ; CHECK-NEXT: ptrue p0.s, vl2 -; CHECK-NEXT: ldp q4, q5, [x0, #128] +; CHECK-NEXT: ldp q4, q5, [x0, #96] +; CHECK-NEXT: ldp q6, q7, [x0] +; CHECK-NEXT: uzp1 z17.s, z3.s, z3.s +; CHECK-NEXT: ldp q3, q18, [x0, #128] +; CHECK-NEXT: uzp1 z16.s, z2.s, z2.s +; CHECK-NEXT: ldp q2, q19, [x0, #192] ; CHECK-NEXT: ldp q0, q1, [x0, #64] -; CHECK-NEXT: ldp q6, q7, [x0, #96] -; CHECK-NEXT: uzp1 z3.s, z3.s, z3.s -; CHECK-NEXT: uzp1 z2.s, z2.s, z2.s -; CHECK-NEXT: uzp1 z5.s, z5.s, z5.s -; CHECK-NEXT: uzp1 z4.s, z4.s, z4.s -; CHECK-NEXT: ldp q16, q17, [x0] -; CHECK-NEXT: uzp1 z1.s, z1.s, z1.s -; CHECK-NEXT: ldp q18, q19, [x0, #192] -; CHECK-NEXT: uzp1 z7.s, z7.s, z7.s -; CHECK-NEXT: ldp q20, q21, [x0, #224] -; CHECK-NEXT: splice z2.s, p0, z2.s, z3.s -; CHECK-NEXT: ldp q22, q23, [x0, #32] -; CHECK-NEXT: splice z4.s, p0, z4.s, z5.s -; CHECK-NEXT: uzp1 z19.s, z19.s, z19.s -; CHECK-NEXT: uzp1 z18.s, z18.s, z18.s -; CHECK-NEXT: uzp1 z17.s, z17.s, z17.s -; CHECK-NEXT: uzp1 z3.s, z21.s, z21.s -; CHECK-NEXT: uzp1 z5.s, z20.s, z20.s -; CHECK-NEXT: uzp1 z16.s, z16.s, z16.s -; CHECK-NEXT: uzp1 z20.s, z23.s, z23.s -; CHECK-NEXT: uzp1 z21.s, z22.s, z22.s -; CHECK-NEXT: uzp1 z6.s, z6.s, z6.s -; CHECK-NEXT: uzp1 z0.s, z0.s, z0.s -; CHECK-NEXT: splice z18.s, p0, z18.s, z19.s -; CHECK-NEXT: splice z5.s, p0, z5.s, z3.s -; CHECK-NEXT: splice z16.s, p0, z16.s, z17.s -; CHECK-NEXT: splice z21.s, p0, z21.s, z20.s -; CHECK-NEXT: splice z6.s, p0, z6.s, z7.s -; CHECK-NEXT: splice z0.s, p0, z0.s, z1.s -; CHECK-NEXT: uzp1 z1.h, z2.h, z2.h -; CHECK-NEXT: uzp1 z2.h, z4.h, z4.h +; CHECK-NEXT: uzp1 z21.s, z18.s, z18.s +; CHECK-NEXT: ldp q18, q22, [x0, #224] +; CHECK-NEXT: uzp1 z20.s, z3.s, z3.s +; CHECK-NEXT: ldp q3, q23, [x0, #32] +; CHECK-NEXT: splice z16.s, p0, { z16.s, z17.s } +; CHECK-NEXT: uzp1 z27.s, z19.s, z19.s +; CHECK-NEXT: uzp1 z25.s, z22.s, z22.s +; CHECK-NEXT: uzp1 z26.s, z2.s, z2.s +; CHECK-NEXT: uzp1 z24.s, z18.s, z18.s +; CHECK-NEXT: uzp1 z18.s, z23.s, z23.s +; CHECK-NEXT: uzp1 z23.s, z5.s, z5.s +; CHECK-NEXT: uzp1 z17.s, z3.s, z3.s +; CHECK-NEXT: uzp1 z3.s, z7.s, z7.s +; CHECK-NEXT: uzp1 z22.s, z4.s, z4.s +; CHECK-NEXT: uzp1 z2.s, z6.s, z6.s +; CHECK-NEXT: uzp1 z5.s, z1.s, z1.s +; CHECK-NEXT: splice z1.s, p0, { z20.s, z21.s } +; CHECK-NEXT: splice z6.s, p0, { z24.s, z25.s } +; CHECK-NEXT: uzp1 z4.s, z0.s, z0.s +; CHECK-NEXT: splice z0.s, p0, { z26.s, z27.s } +; CHECK-NEXT: splice z7.s, p0, { z17.s, z18.s } +; CHECK-NEXT: uzp1 z17.h, z16.h, z16.h +; CHECK-NEXT: splice z2.s, p0, { z2.s, z3.s } +; CHECK-NEXT: splice z3.s, p0, { z22.s, z23.s } +; CHECK-NEXT: splice z4.s, p0, { z4.s, z5.s } +; CHECK-NEXT: uzp1 z16.h, z1.h, z1.h ; CHECK-NEXT: ptrue p0.h, vl4 -; CHECK-NEXT: uzp1 z4.h, z18.h, z18.h -; CHECK-NEXT: uzp1 z3.h, z5.h, z5.h -; CHECK-NEXT: uzp1 z7.h, z16.h, z16.h -; CHECK-NEXT: uzp1 z5.h, z21.h, z21.h -; CHECK-NEXT: splice z2.h, p0, z2.h, z1.h -; CHECK-NEXT: uzp1 z1.h, z6.h, z6.h -; CHECK-NEXT: uzp1 z0.h, z0.h, z0.h -; CHECK-NEXT: splice z4.h, p0, z4.h, z3.h -; CHECK-NEXT: splice z7.h, p0, z7.h, z5.h -; CHECK-NEXT: splice z0.h, p0, z0.h, z1.h -; CHECK-NEXT: add z1.h, z2.h, z2.h -; CHECK-NEXT: add z2.h, z4.h, z4.h -; CHECK-NEXT: add z3.h, z7.h, z7.h +; CHECK-NEXT: uzp1 z6.h, z6.h, z6.h +; CHECK-NEXT: uzp1 z5.h, z0.h, z0.h +; CHECK-NEXT: uzp1 z1.h, z7.h, z7.h +; CHECK-NEXT: uzp1 z0.h, z2.h, z2.h +; CHECK-NEXT: uzp1 z3.h, z3.h, z3.h +; CHECK-NEXT: splice z7.h, p0, { z16.h, z17.h } +; CHECK-NEXT: uzp1 z2.h, z4.h, z4.h +; CHECK-NEXT: splice z4.h, p0, { z5.h, z6.h } +; CHECK-NEXT: splice z0.h, p0, { z0.h, z1.h } +; CHECK-NEXT: splice z1.h, p0, { z2.h, z3.h } +; CHECK-NEXT: add z2.h, z7.h, z7.h +; CHECK-NEXT: add z3.h, z4.h, z4.h ; CHECK-NEXT: add z0.h, z0.h, z0.h -; CHECK-NEXT: stp q1, q2, [x1, #32] -; CHECK-NEXT: stp q3, q0, [x1] +; CHECK-NEXT: add z1.h, z1.h, z1.h +; CHECK-NEXT: stp q2, q3, [x1, #32] +; CHECK-NEXT: stp q0, q1, [x1] ; CHECK-NEXT: ret ; ; NONEON-NOSVE-LABEL: trunc_v32i64_v32i16: @@ -3118,11 +3118,11 @@ define void @trunc_v32i64_v32i16(ptr %in, ptr %out) nounwind { define <4 x i32> @trunc_v4i64_v4i32(ptr %in) nounwind { ; CHECK-LABEL: trunc_v4i64_v4i32: ; CHECK: // %bb.0: -; CHECK-NEXT: ldp q0, q1, [x0] +; CHECK-NEXT: ldp q1, q0, [x0] ; CHECK-NEXT: ptrue p0.s, vl2 -; CHECK-NEXT: uzp1 z1.s, z1.s, z1.s -; CHECK-NEXT: uzp1 z0.s, z0.s, z0.s -; CHECK-NEXT: splice z0.s, p0, z0.s, z1.s +; CHECK-NEXT: uzp1 z3.s, z0.s, z0.s +; CHECK-NEXT: uzp1 z2.s, z1.s, z1.s +; CHECK-NEXT: splice z0.s, p0, { z2.s, z3.s } ; CHECK-NEXT: // kill: def $q0 killed $q0 killed $z0 ; CHECK-NEXT: ret ; @@ -3146,18 +3146,18 @@ define <4 x i32> @trunc_v4i64_v4i32(ptr %in) nounwind { define void @trunc_v8i64_v8i32(ptr %in, ptr %out) nounwind { ; CHECK-LABEL: trunc_v8i64_v8i32: ; CHECK: // %bb.0: -; CHECK-NEXT: ldp q0, q1, [x0, #32] +; CHECK-NEXT: ldp q1, q0, [x0, #32] ; CHECK-NEXT: ptrue p0.s, vl2 -; CHECK-NEXT: ldp q2, q3, [x0] -; CHECK-NEXT: uzp1 z1.s, z1.s, z1.s -; CHECK-NEXT: uzp1 z0.s, z0.s, z0.s -; CHECK-NEXT: uzp1 z3.s, z3.s, z3.s -; CHECK-NEXT: uzp1 z2.s, z2.s, z2.s -; CHECK-NEXT: splice z0.s, p0, z0.s, z1.s -; CHECK-NEXT: splice z2.s, p0, z2.s, z3.s -; CHECK-NEXT: add z0.s, z0.s, z0.s +; CHECK-NEXT: ldp q3, q2, [x0] +; CHECK-NEXT: uzp1 z5.s, z0.s, z0.s +; CHECK-NEXT: uzp1 z4.s, z1.s, z1.s +; CHECK-NEXT: uzp1 z1.s, z2.s, z2.s +; CHECK-NEXT: uzp1 z0.s, z3.s, z3.s +; CHECK-NEXT: splice z2.s, p0, { z4.s, z5.s } +; CHECK-NEXT: splice z0.s, p0, { z0.s, z1.s } ; CHECK-NEXT: add z1.s, z2.s, z2.s -; CHECK-NEXT: stp q1, q0, [x1] +; CHECK-NEXT: add z0.s, z0.s, z0.s +; CHECK-NEXT: stp q0, q1, [x1] ; CHECK-NEXT: ret ; ; NONEON-NOSVE-LABEL: trunc_v8i64_v8i32: @@ -3202,27 +3202,27 @@ define void @trunc_v8i64_v8i32(ptr %in, ptr %out) nounwind { define void @trunc_v16i64_v16i32(ptr %in, ptr %out) nounwind { ; CHECK-LABEL: trunc_v16i64_v16i32: ; CHECK: // %bb.0: -; CHECK-NEXT: ldp q0, q1, [x0, #64] +; CHECK-NEXT: ldp q1, q0, [x0, #64] ; CHECK-NEXT: ptrue p0.s, vl2 -; CHECK-NEXT: ldp q2, q3, [x0] -; CHECK-NEXT: ldp q4, q5, [x0, #96] -; CHECK-NEXT: ldp q6, q7, [x0, #32] -; CHECK-NEXT: uzp1 z1.s, z1.s, z1.s -; CHECK-NEXT: uzp1 z0.s, z0.s, z0.s -; CHECK-NEXT: uzp1 z3.s, z3.s, z3.s -; CHECK-NEXT: uzp1 z2.s, z2.s, z2.s -; CHECK-NEXT: uzp1 z5.s, z5.s, z5.s -; CHECK-NEXT: uzp1 z4.s, z4.s, z4.s -; CHECK-NEXT: uzp1 z7.s, z7.s, z7.s -; CHECK-NEXT: uzp1 z6.s, z6.s, z6.s -; CHECK-NEXT: splice z0.s, p0, z0.s, z1.s -; CHECK-NEXT: splice z2.s, p0, z2.s, z3.s -; CHECK-NEXT: splice z4.s, p0, z4.s, z5.s -; CHECK-NEXT: splice z6.s, p0, z6.s, z7.s +; CHECK-NEXT: ldp q2, q3, [x0, #96] +; CHECK-NEXT: ldp q4, q5, [x0] +; CHECK-NEXT: uzp1 z7.s, z0.s, z0.s +; CHECK-NEXT: uzp1 z6.s, z1.s, z1.s +; CHECK-NEXT: ldp q1, q0, [x0, #32] +; CHECK-NEXT: uzp1 z17.s, z3.s, z3.s +; CHECK-NEXT: uzp1 z16.s, z2.s, z2.s +; CHECK-NEXT: uzp1 z3.s, z5.s, z5.s +; CHECK-NEXT: uzp1 z2.s, z4.s, z4.s +; CHECK-NEXT: uzp1 z5.s, z0.s, z0.s +; CHECK-NEXT: splice z0.s, p0, { z6.s, z7.s } +; CHECK-NEXT: uzp1 z4.s, z1.s, z1.s +; CHECK-NEXT: splice z1.s, p0, { z16.s, z17.s } +; CHECK-NEXT: splice z2.s, p0, { z2.s, z3.s } +; CHECK-NEXT: splice z3.s, p0, { z4.s, z5.s } ; CHECK-NEXT: add z0.s, z0.s, z0.s +; CHECK-NEXT: add z1.s, z1.s, z1.s ; CHECK-NEXT: add z2.s, z2.s, z2.s -; CHECK-NEXT: add z1.s, z4.s, z4.s -; CHECK-NEXT: add z3.s, z6.s, z6.s +; CHECK-NEXT: add z3.s, z3.s, z3.s ; CHECK-NEXT: stp q0, q1, [x1, #32] ; CHECK-NEXT: stp q2, q3, [x1] ; CHECK-NEXT: ret @@ -3297,49 +3297,49 @@ define void @trunc_v32i64_v32i32(ptr %in, ptr %out) nounwind { ; CHECK: // %bb.0: ; CHECK-NEXT: ldp q2, q3, [x0, #192] ; CHECK-NEXT: ptrue p0.s, vl2 +; CHECK-NEXT: ldp q4, q5, [x0] ; CHECK-NEXT: ldp q6, q7, [x0, #64] -; CHECK-NEXT: ldp q16, q17, [x0, #224] -; CHECK-NEXT: uzp1 z3.s, z3.s, z3.s -; CHECK-NEXT: uzp1 z2.s, z2.s, z2.s -; CHECK-NEXT: ldp q20, q21, [x0, #160] -; CHECK-NEXT: uzp1 z7.s, z7.s, z7.s +; CHECK-NEXT: uzp1 z17.s, z3.s, z3.s +; CHECK-NEXT: ldp q3, q18, [x0, #224] +; CHECK-NEXT: uzp1 z16.s, z2.s, z2.s +; CHECK-NEXT: ldp q2, q19, [x0, #128] ; CHECK-NEXT: ldp q0, q1, [x0, #32] -; CHECK-NEXT: uzp1 z17.s, z17.s, z17.s -; CHECK-NEXT: ldp q4, q5, [x0, #96] -; CHECK-NEXT: uzp1 z16.s, z16.s, z16.s -; CHECK-NEXT: ldp q18, q19, [x0, #128] -; CHECK-NEXT: splice z2.s, p0, z2.s, z3.s -; CHECK-NEXT: uzp1 z3.s, z21.s, z21.s -; CHECK-NEXT: uzp1 z20.s, z20.s, z20.s -; CHECK-NEXT: uzp1 z6.s, z6.s, z6.s -; CHECK-NEXT: ldp q21, q22, [x0] -; CHECK-NEXT: splice z16.s, p0, z16.s, z17.s +; CHECK-NEXT: uzp1 z21.s, z18.s, z18.s +; CHECK-NEXT: ldp q18, q22, [x0, #160] +; CHECK-NEXT: uzp1 z20.s, z3.s, z3.s +; CHECK-NEXT: uzp1 z24.s, z19.s, z19.s +; CHECK-NEXT: ldp q3, q19, [x0, #96] +; CHECK-NEXT: uzp1 z23.s, z2.s, z2.s +; CHECK-NEXT: uzp1 z26.s, z22.s, z22.s +; CHECK-NEXT: splice z2.s, p0, { z16.s, z17.s } +; CHECK-NEXT: uzp1 z17.s, z7.s, z7.s +; CHECK-NEXT: uzp1 z25.s, z18.s, z18.s +; CHECK-NEXT: splice z7.s, p0, { z20.s, z21.s } +; CHECK-NEXT: uzp1 z21.s, z5.s, z5.s ; CHECK-NEXT: uzp1 z19.s, z19.s, z19.s -; CHECK-NEXT: uzp1 z18.s, z18.s, z18.s -; CHECK-NEXT: uzp1 z4.s, z4.s, z4.s -; CHECK-NEXT: splice z20.s, p0, z20.s, z3.s -; CHECK-NEXT: uzp1 z3.s, z5.s, z5.s -; CHECK-NEXT: splice z6.s, p0, z6.s, z7.s -; CHECK-NEXT: uzp1 z5.s, z22.s, z22.s -; CHECK-NEXT: uzp1 z7.s, z21.s, z21.s -; CHECK-NEXT: uzp1 z1.s, z1.s, z1.s -; CHECK-NEXT: uzp1 z0.s, z0.s, z0.s -; CHECK-NEXT: splice z18.s, p0, z18.s, z19.s -; CHECK-NEXT: add z2.s, z2.s, z2.s -; CHECK-NEXT: splice z4.s, p0, z4.s, z3.s -; CHECK-NEXT: add z3.s, z16.s, z16.s -; CHECK-NEXT: splice z7.s, p0, z7.s, z5.s -; CHECK-NEXT: splice z0.s, p0, z0.s, z1.s -; CHECK-NEXT: add z1.s, z20.s, z20.s -; CHECK-NEXT: add z5.s, z18.s, z18.s -; CHECK-NEXT: stp q2, q3, [x1, #96] -; CHECK-NEXT: add z2.s, z6.s, z6.s +; CHECK-NEXT: uzp1 z20.s, z4.s, z4.s +; CHECK-NEXT: uzp1 z5.s, z1.s, z1.s +; CHECK-NEXT: uzp1 z16.s, z6.s, z6.s +; CHECK-NEXT: splice z6.s, p0, { z23.s, z24.s } +; CHECK-NEXT: uzp1 z18.s, z3.s, z3.s +; CHECK-NEXT: splice z3.s, p0, { z25.s, z26.s } +; CHECK-NEXT: uzp1 z4.s, z0.s, z0.s +; CHECK-NEXT: add z0.s, z2.s, z2.s +; CHECK-NEXT: add z7.s, z7.s, z7.s +; CHECK-NEXT: splice z1.s, p0, { z16.s, z17.s } +; CHECK-NEXT: splice z2.s, p0, { z18.s, z19.s } +; CHECK-NEXT: splice z16.s, p0, { z20.s, z21.s } +; CHECK-NEXT: splice z4.s, p0, { z4.s, z5.s } +; CHECK-NEXT: add z6.s, z6.s, z6.s +; CHECK-NEXT: add z3.s, z3.s, z3.s +; CHECK-NEXT: stp q0, q7, [x1, #96] +; CHECK-NEXT: add z0.s, z1.s, z1.s +; CHECK-NEXT: add z1.s, z2.s, z2.s +; CHECK-NEXT: add z2.s, z16.s, z16.s +; CHECK-NEXT: stp q6, q3, [x1, #64] ; CHECK-NEXT: add z3.s, z4.s, z4.s -; CHECK-NEXT: add z4.s, z7.s, z7.s -; CHECK-NEXT: add z0.s, z0.s, z0.s -; CHECK-NEXT: stp q5, q1, [x1, #64] -; CHECK-NEXT: stp q2, q3, [x1, #32] -; CHECK-NEXT: stp q4, q0, [x1] +; CHECK-NEXT: stp q0, q1, [x1, #32] +; CHECK-NEXT: stp q2, q3, [x1] ; CHECK-NEXT: ret ; ; NONEON-NOSVE-LABEL: trunc_v32i64_v32i32: diff --git a/llvm/test/CodeGen/AMDGPU/addrspacecast.ll b/llvm/test/CodeGen/AMDGPU/addrspacecast.ll index 7336543b41cbc8..236956c1829e77 100644 --- a/llvm/test/CodeGen/AMDGPU/addrspacecast.ll +++ b/llvm/test/CodeGen/AMDGPU/addrspacecast.ll @@ -409,6 +409,1183 @@ define amdgpu_kernel void @use_constant32bit_to_flat_addrspacecast_1(ptr addrspa ret void } +define <2 x ptr addrspace(5)> @addrspacecast_v2p0_to_v2p5(<2 x ptr> %ptr) { +; HSA-LABEL: addrspacecast_v2p0_to_v2p5: +; HSA: ; %bb.0: +; HSA-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; HSA-NEXT: v_cmp_ne_u64_e32 vcc, 0, v[0:1] +; HSA-NEXT: v_cndmask_b32_e32 v0, -1, v0, vcc +; HSA-NEXT: v_cmp_ne_u64_e32 vcc, 0, v[2:3] +; HSA-NEXT: v_cndmask_b32_e32 v1, -1, v2, vcc +; HSA-NEXT: s_setpc_b64 s[30:31] + %cast = addrspacecast <2 x ptr> %ptr to <2 x ptr addrspace(5)> + ret <2 x ptr addrspace(5)> %cast +} + +define <3 x ptr addrspace(5)> @addrspacecast_v3p0_to_v3p5(<3 x ptr> %ptr) { +; HSA-LABEL: addrspacecast_v3p0_to_v3p5: +; HSA: ; %bb.0: +; HSA-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; HSA-NEXT: v_cmp_ne_u64_e32 vcc, 0, v[0:1] +; HSA-NEXT: v_cndmask_b32_e32 v0, -1, v0, vcc +; HSA-NEXT: v_cmp_ne_u64_e32 vcc, 0, v[2:3] +; HSA-NEXT: v_cndmask_b32_e32 v1, -1, v2, vcc +; HSA-NEXT: v_cmp_ne_u64_e32 vcc, 0, v[4:5] +; HSA-NEXT: v_cndmask_b32_e32 v2, -1, v4, vcc +; HSA-NEXT: s_setpc_b64 s[30:31] + %cast = addrspacecast <3 x ptr> %ptr to <3 x ptr addrspace(5)> + ret <3 x ptr addrspace(5)> %cast +} + +define <4 x ptr addrspace(5)> @addrspacecast_v4p0_to_v4p5(<4 x ptr> %ptr) { +; HSA-LABEL: addrspacecast_v4p0_to_v4p5: +; HSA: ; %bb.0: +; HSA-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; HSA-NEXT: v_cmp_ne_u64_e32 vcc, 0, v[0:1] +; HSA-NEXT: v_cndmask_b32_e32 v0, -1, v0, vcc +; HSA-NEXT: v_cmp_ne_u64_e32 vcc, 0, v[2:3] +; HSA-NEXT: v_cndmask_b32_e32 v1, -1, v2, vcc +; HSA-NEXT: v_cmp_ne_u64_e32 vcc, 0, v[4:5] +; HSA-NEXT: v_cndmask_b32_e32 v2, -1, v4, vcc +; HSA-NEXT: v_cmp_ne_u64_e32 vcc, 0, v[6:7] +; HSA-NEXT: v_cndmask_b32_e32 v3, -1, v6, vcc +; HSA-NEXT: s_setpc_b64 s[30:31] + %cast = addrspacecast <4 x ptr> %ptr to <4 x ptr addrspace(5)> + ret <4 x ptr addrspace(5)> %cast +} + +define <8 x ptr addrspace(5)> @addrspacecast_v8p0_to_v8p5(<8 x ptr> %ptr) { +; HSA-LABEL: addrspacecast_v8p0_to_v8p5: +; HSA: ; %bb.0: +; HSA-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; HSA-NEXT: v_cmp_ne_u64_e32 vcc, 0, v[0:1] +; HSA-NEXT: v_cndmask_b32_e32 v0, -1, v0, vcc +; HSA-NEXT: v_cmp_ne_u64_e32 vcc, 0, v[2:3] +; HSA-NEXT: v_cndmask_b32_e32 v1, -1, v2, vcc +; HSA-NEXT: v_cmp_ne_u64_e32 vcc, 0, v[4:5] +; HSA-NEXT: v_cndmask_b32_e32 v2, -1, v4, vcc +; HSA-NEXT: v_cmp_ne_u64_e32 vcc, 0, v[6:7] +; HSA-NEXT: v_cndmask_b32_e32 v3, -1, v6, vcc +; HSA-NEXT: v_cmp_ne_u64_e32 vcc, 0, v[8:9] +; HSA-NEXT: v_cndmask_b32_e32 v4, -1, v8, vcc +; HSA-NEXT: v_cmp_ne_u64_e32 vcc, 0, v[10:11] +; HSA-NEXT: v_cndmask_b32_e32 v5, -1, v10, vcc +; HSA-NEXT: v_cmp_ne_u64_e32 vcc, 0, v[12:13] +; HSA-NEXT: v_cndmask_b32_e32 v6, -1, v12, vcc +; HSA-NEXT: v_cmp_ne_u64_e32 vcc, 0, v[14:15] +; HSA-NEXT: v_cndmask_b32_e32 v7, -1, v14, vcc +; HSA-NEXT: s_setpc_b64 s[30:31] + %cast = addrspacecast <8 x ptr> %ptr to <8 x ptr addrspace(5)> + ret <8 x ptr addrspace(5)> %cast +} + +define <16 x ptr addrspace(5)> @addrspacecast_v16p0_to_v16p5(<16 x ptr> %ptr) { +; HSA-LABEL: addrspacecast_v16p0_to_v16p5: +; HSA: ; %bb.0: +; HSA-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; HSA-NEXT: buffer_load_dword v31, off, s[0:3], s32 +; HSA-NEXT: v_cmp_ne_u64_e32 vcc, 0, v[0:1] +; HSA-NEXT: v_cmp_ne_u64_e64 s[4:5], 0, v[24:25] +; HSA-NEXT: v_cndmask_b32_e32 v0, -1, v0, vcc +; HSA-NEXT: v_cmp_ne_u64_e32 vcc, 0, v[2:3] +; HSA-NEXT: v_cmp_ne_u64_e64 s[6:7], 0, v[26:27] +; HSA-NEXT: v_cndmask_b32_e32 v1, -1, v2, vcc +; HSA-NEXT: v_cmp_ne_u64_e32 vcc, 0, v[4:5] +; HSA-NEXT: v_cmp_ne_u64_e64 s[8:9], 0, v[28:29] +; HSA-NEXT: v_cndmask_b32_e32 v2, -1, v4, vcc +; HSA-NEXT: v_cmp_ne_u64_e32 vcc, 0, v[6:7] +; HSA-NEXT: v_cndmask_b32_e32 v3, -1, v6, vcc +; HSA-NEXT: v_cmp_ne_u64_e32 vcc, 0, v[8:9] +; HSA-NEXT: v_cndmask_b32_e32 v4, -1, v8, vcc +; HSA-NEXT: v_cmp_ne_u64_e32 vcc, 0, v[10:11] +; HSA-NEXT: v_cndmask_b32_e32 v5, -1, v10, vcc +; HSA-NEXT: v_cmp_ne_u64_e32 vcc, 0, v[12:13] +; HSA-NEXT: v_cndmask_b32_e64 v13, -1, v26, s[6:7] +; HSA-NEXT: v_cndmask_b32_e32 v6, -1, v12, vcc +; HSA-NEXT: v_cmp_ne_u64_e32 vcc, 0, v[14:15] +; HSA-NEXT: v_cndmask_b32_e64 v12, -1, v24, s[4:5] +; HSA-NEXT: v_cndmask_b32_e32 v7, -1, v14, vcc +; HSA-NEXT: v_cmp_ne_u64_e32 vcc, 0, v[16:17] +; HSA-NEXT: v_cndmask_b32_e64 v14, -1, v28, s[8:9] +; HSA-NEXT: v_cndmask_b32_e32 v8, -1, v16, vcc +; HSA-NEXT: v_cmp_ne_u64_e32 vcc, 0, v[18:19] +; HSA-NEXT: v_cndmask_b32_e32 v9, -1, v18, vcc +; HSA-NEXT: v_cmp_ne_u64_e32 vcc, 0, v[20:21] +; HSA-NEXT: v_cndmask_b32_e32 v10, -1, v20, vcc +; HSA-NEXT: v_cmp_ne_u64_e32 vcc, 0, v[22:23] +; HSA-NEXT: v_cndmask_b32_e32 v11, -1, v22, vcc +; HSA-NEXT: s_waitcnt vmcnt(0) +; HSA-NEXT: v_cmp_ne_u64_e32 vcc, 0, v[30:31] +; HSA-NEXT: v_cndmask_b32_e32 v15, -1, v30, vcc +; HSA-NEXT: s_setpc_b64 s[30:31] + %cast = addrspacecast <16 x ptr> %ptr to <16 x ptr addrspace(5)> + ret <16 x ptr addrspace(5)> %cast +} + +define <2 x ptr> @addrspacecast_v2p5_to_v2p0(<2 x ptr addrspace(5)> %ptr) { +; CI-LABEL: addrspacecast_v2p5_to_v2p0: +; CI: ; %bb.0: +; CI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; CI-NEXT: s_load_dword s4, s[6:7], 0x11 +; CI-NEXT: v_cmp_ne_u32_e32 vcc, -1, v0 +; CI-NEXT: v_cndmask_b32_e32 v0, 0, v0, vcc +; CI-NEXT: s_waitcnt lgkmcnt(0) +; CI-NEXT: v_mov_b32_e32 v3, s4 +; CI-NEXT: v_cndmask_b32_e32 v4, 0, v3, vcc +; CI-NEXT: v_cmp_ne_u32_e32 vcc, -1, v1 +; CI-NEXT: v_cndmask_b32_e32 v2, 0, v1, vcc +; CI-NEXT: v_cndmask_b32_e32 v3, 0, v3, vcc +; CI-NEXT: v_mov_b32_e32 v1, v4 +; CI-NEXT: s_setpc_b64 s[30:31] +; +; GFX9-LABEL: addrspacecast_v2p5_to_v2p0: +; GFX9: ; %bb.0: +; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX9-NEXT: s_mov_b64 s[4:5], src_private_base +; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, -1, v0 +; GFX9-NEXT: v_mov_b32_e32 v3, s5 +; GFX9-NEXT: v_cndmask_b32_e32 v0, 0, v0, vcc +; GFX9-NEXT: v_cndmask_b32_e32 v4, 0, v3, vcc +; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, -1, v1 +; GFX9-NEXT: v_cndmask_b32_e32 v2, 0, v1, vcc +; GFX9-NEXT: v_cndmask_b32_e32 v3, 0, v3, vcc +; GFX9-NEXT: v_mov_b32_e32 v1, v4 +; GFX9-NEXT: s_setpc_b64 s[30:31] + %cast = addrspacecast <2 x ptr addrspace(5)> %ptr to <2 x ptr> + ret <2 x ptr> %cast +} + +define <3 x ptr> @addrspacecast_v3p5_to_v3p0(<3 x ptr addrspace(5)> %ptr) { +; CI-LABEL: addrspacecast_v3p5_to_v3p0: +; CI: ; %bb.0: +; CI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; CI-NEXT: s_load_dword s4, s[6:7], 0x11 +; CI-NEXT: v_cmp_ne_u32_e32 vcc, -1, v0 +; CI-NEXT: v_cndmask_b32_e32 v0, 0, v0, vcc +; CI-NEXT: s_waitcnt lgkmcnt(0) +; CI-NEXT: v_mov_b32_e32 v5, s4 +; CI-NEXT: v_cndmask_b32_e32 v7, 0, v5, vcc +; CI-NEXT: v_cmp_ne_u32_e32 vcc, -1, v1 +; CI-NEXT: v_cndmask_b32_e32 v6, 0, v1, vcc +; CI-NEXT: v_cndmask_b32_e32 v3, 0, v5, vcc +; CI-NEXT: v_cmp_ne_u32_e32 vcc, -1, v2 +; CI-NEXT: v_cndmask_b32_e32 v4, 0, v2, vcc +; CI-NEXT: v_cndmask_b32_e32 v5, 0, v5, vcc +; CI-NEXT: v_mov_b32_e32 v1, v7 +; CI-NEXT: v_mov_b32_e32 v2, v6 +; CI-NEXT: s_setpc_b64 s[30:31] +; +; GFX9-LABEL: addrspacecast_v3p5_to_v3p0: +; GFX9: ; %bb.0: +; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX9-NEXT: s_mov_b64 s[4:5], src_private_base +; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, -1, v0 +; GFX9-NEXT: v_mov_b32_e32 v5, s5 +; GFX9-NEXT: v_cndmask_b32_e32 v0, 0, v0, vcc +; GFX9-NEXT: v_cndmask_b32_e32 v7, 0, v5, vcc +; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, -1, v1 +; GFX9-NEXT: v_cndmask_b32_e32 v6, 0, v1, vcc +; GFX9-NEXT: v_cndmask_b32_e32 v3, 0, v5, vcc +; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, -1, v2 +; GFX9-NEXT: v_cndmask_b32_e32 v4, 0, v2, vcc +; GFX9-NEXT: v_cndmask_b32_e32 v5, 0, v5, vcc +; GFX9-NEXT: v_mov_b32_e32 v1, v7 +; GFX9-NEXT: v_mov_b32_e32 v2, v6 +; GFX9-NEXT: s_setpc_b64 s[30:31] + %cast = addrspacecast <3 x ptr addrspace(5)> %ptr to <3 x ptr> + ret <3 x ptr> %cast +} + +define <4 x ptr> @addrspacecast_v4p5_to_v4p0(<4 x ptr addrspace(5)> %ptr) { +; CI-LABEL: addrspacecast_v4p5_to_v4p0: +; CI: ; %bb.0: +; CI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; CI-NEXT: s_load_dword s4, s[6:7], 0x11 +; CI-NEXT: v_cmp_ne_u32_e32 vcc, -1, v0 +; CI-NEXT: v_cndmask_b32_e32 v0, 0, v0, vcc +; CI-NEXT: s_waitcnt lgkmcnt(0) +; CI-NEXT: v_mov_b32_e32 v7, s4 +; CI-NEXT: v_cndmask_b32_e32 v10, 0, v7, vcc +; CI-NEXT: v_cmp_ne_u32_e32 vcc, -1, v1 +; CI-NEXT: v_cndmask_b32_e32 v8, 0, v1, vcc +; CI-NEXT: v_cndmask_b32_e32 v9, 0, v7, vcc +; CI-NEXT: v_cmp_ne_u32_e32 vcc, -1, v2 +; CI-NEXT: v_cndmask_b32_e32 v4, 0, v2, vcc +; CI-NEXT: v_cndmask_b32_e32 v5, 0, v7, vcc +; CI-NEXT: v_cmp_ne_u32_e32 vcc, -1, v3 +; CI-NEXT: v_cndmask_b32_e32 v6, 0, v3, vcc +; CI-NEXT: v_cndmask_b32_e32 v7, 0, v7, vcc +; CI-NEXT: v_mov_b32_e32 v1, v10 +; CI-NEXT: v_mov_b32_e32 v2, v8 +; CI-NEXT: v_mov_b32_e32 v3, v9 +; CI-NEXT: s_setpc_b64 s[30:31] +; +; GFX9-LABEL: addrspacecast_v4p5_to_v4p0: +; GFX9: ; %bb.0: +; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX9-NEXT: s_mov_b64 s[4:5], src_private_base +; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, -1, v0 +; GFX9-NEXT: v_mov_b32_e32 v7, s5 +; GFX9-NEXT: v_cndmask_b32_e32 v0, 0, v0, vcc +; GFX9-NEXT: v_cndmask_b32_e32 v10, 0, v7, vcc +; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, -1, v1 +; GFX9-NEXT: v_cndmask_b32_e32 v8, 0, v1, vcc +; GFX9-NEXT: v_cndmask_b32_e32 v9, 0, v7, vcc +; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, -1, v2 +; GFX9-NEXT: v_cndmask_b32_e32 v4, 0, v2, vcc +; GFX9-NEXT: v_cndmask_b32_e32 v5, 0, v7, vcc +; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, -1, v3 +; GFX9-NEXT: v_cndmask_b32_e32 v6, 0, v3, vcc +; GFX9-NEXT: v_cndmask_b32_e32 v7, 0, v7, vcc +; GFX9-NEXT: v_mov_b32_e32 v1, v10 +; GFX9-NEXT: v_mov_b32_e32 v2, v8 +; GFX9-NEXT: v_mov_b32_e32 v3, v9 +; GFX9-NEXT: s_setpc_b64 s[30:31] + %cast = addrspacecast <4 x ptr addrspace(5)> %ptr to <4 x ptr> + ret <4 x ptr> %cast +} + +define <8 x ptr> @addrspacecast_v8p5_to_v8p0(<8 x ptr addrspace(5)> %ptr) { +; CI-LABEL: addrspacecast_v8p5_to_v8p0: +; CI: ; %bb.0: +; CI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; CI-NEXT: s_load_dword s4, s[6:7], 0x11 +; CI-NEXT: v_cmp_ne_u32_e32 vcc, -1, v0 +; CI-NEXT: v_cndmask_b32_e32 v0, 0, v0, vcc +; CI-NEXT: s_waitcnt lgkmcnt(0) +; CI-NEXT: v_mov_b32_e32 v15, s4 +; CI-NEXT: v_cndmask_b32_e32 v22, 0, v15, vcc +; CI-NEXT: v_cmp_ne_u32_e32 vcc, -1, v1 +; CI-NEXT: v_cndmask_b32_e32 v16, 0, v1, vcc +; CI-NEXT: v_cndmask_b32_e32 v17, 0, v15, vcc +; CI-NEXT: v_cmp_ne_u32_e32 vcc, -1, v2 +; CI-NEXT: v_cndmask_b32_e32 v18, 0, v2, vcc +; CI-NEXT: v_cndmask_b32_e32 v19, 0, v15, vcc +; CI-NEXT: v_cmp_ne_u32_e32 vcc, -1, v3 +; CI-NEXT: v_cndmask_b32_e32 v20, 0, v3, vcc +; CI-NEXT: v_cndmask_b32_e32 v21, 0, v15, vcc +; CI-NEXT: v_cmp_ne_u32_e32 vcc, -1, v4 +; CI-NEXT: v_cndmask_b32_e32 v8, 0, v4, vcc +; CI-NEXT: v_cndmask_b32_e32 v9, 0, v15, vcc +; CI-NEXT: v_cmp_ne_u32_e32 vcc, -1, v5 +; CI-NEXT: v_cndmask_b32_e32 v10, 0, v5, vcc +; CI-NEXT: v_cndmask_b32_e32 v11, 0, v15, vcc +; CI-NEXT: v_cmp_ne_u32_e32 vcc, -1, v6 +; CI-NEXT: v_cndmask_b32_e32 v12, 0, v6, vcc +; CI-NEXT: v_cndmask_b32_e32 v13, 0, v15, vcc +; CI-NEXT: v_cmp_ne_u32_e32 vcc, -1, v7 +; CI-NEXT: v_cndmask_b32_e32 v14, 0, v7, vcc +; CI-NEXT: v_cndmask_b32_e32 v15, 0, v15, vcc +; CI-NEXT: v_mov_b32_e32 v1, v22 +; CI-NEXT: v_mov_b32_e32 v2, v16 +; CI-NEXT: v_mov_b32_e32 v3, v17 +; CI-NEXT: v_mov_b32_e32 v4, v18 +; CI-NEXT: v_mov_b32_e32 v5, v19 +; CI-NEXT: v_mov_b32_e32 v6, v20 +; CI-NEXT: v_mov_b32_e32 v7, v21 +; CI-NEXT: s_setpc_b64 s[30:31] +; +; GFX9-LABEL: addrspacecast_v8p5_to_v8p0: +; GFX9: ; %bb.0: +; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX9-NEXT: s_mov_b64 s[4:5], src_private_base +; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, -1, v0 +; GFX9-NEXT: v_mov_b32_e32 v15, s5 +; GFX9-NEXT: v_cndmask_b32_e32 v0, 0, v0, vcc +; GFX9-NEXT: v_cndmask_b32_e32 v22, 0, v15, vcc +; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, -1, v1 +; GFX9-NEXT: v_cndmask_b32_e32 v16, 0, v1, vcc +; GFX9-NEXT: v_cndmask_b32_e32 v17, 0, v15, vcc +; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, -1, v2 +; GFX9-NEXT: v_cndmask_b32_e32 v18, 0, v2, vcc +; GFX9-NEXT: v_cndmask_b32_e32 v19, 0, v15, vcc +; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, -1, v3 +; GFX9-NEXT: v_cndmask_b32_e32 v20, 0, v3, vcc +; GFX9-NEXT: v_cndmask_b32_e32 v21, 0, v15, vcc +; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, -1, v4 +; GFX9-NEXT: v_cndmask_b32_e32 v8, 0, v4, vcc +; GFX9-NEXT: v_cndmask_b32_e32 v9, 0, v15, vcc +; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, -1, v5 +; GFX9-NEXT: v_cndmask_b32_e32 v10, 0, v5, vcc +; GFX9-NEXT: v_cndmask_b32_e32 v11, 0, v15, vcc +; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, -1, v6 +; GFX9-NEXT: v_cndmask_b32_e32 v12, 0, v6, vcc +; GFX9-NEXT: v_cndmask_b32_e32 v13, 0, v15, vcc +; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, -1, v7 +; GFX9-NEXT: v_cndmask_b32_e32 v14, 0, v7, vcc +; GFX9-NEXT: v_cndmask_b32_e32 v15, 0, v15, vcc +; GFX9-NEXT: v_mov_b32_e32 v1, v22 +; GFX9-NEXT: v_mov_b32_e32 v2, v16 +; GFX9-NEXT: v_mov_b32_e32 v3, v17 +; GFX9-NEXT: v_mov_b32_e32 v4, v18 +; GFX9-NEXT: v_mov_b32_e32 v5, v19 +; GFX9-NEXT: v_mov_b32_e32 v6, v20 +; GFX9-NEXT: v_mov_b32_e32 v7, v21 +; GFX9-NEXT: s_setpc_b64 s[30:31] + %cast = addrspacecast <8 x ptr addrspace(5)> %ptr to <8 x ptr> + ret <8 x ptr> %cast +} + +define <16 x ptr> @addrspacecast_v16p5_to_v16p0(<16 x ptr addrspace(5)> %ptr) { +; CI-LABEL: addrspacecast_v16p5_to_v16p0: +; CI: ; %bb.0: +; CI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; CI-NEXT: s_load_dword s4, s[6:7], 0x11 +; CI-NEXT: v_cmp_ne_u32_e32 vcc, -1, v0 +; CI-NEXT: v_cndmask_b32_e32 v0, 0, v0, vcc +; CI-NEXT: v_cmp_ne_u32_e64 s[6:7], -1, v6 +; CI-NEXT: v_cmp_ne_u32_e64 s[8:9], -1, v7 +; CI-NEXT: s_waitcnt lgkmcnt(0) +; CI-NEXT: v_mov_b32_e32 v31, s4 +; CI-NEXT: v_cndmask_b32_e32 v48, 0, v31, vcc +; CI-NEXT: v_cmp_ne_u32_e32 vcc, -1, v1 +; CI-NEXT: v_cndmask_b32_e32 v35, 0, v1, vcc +; CI-NEXT: v_cndmask_b32_e32 v33, 0, v31, vcc +; CI-NEXT: v_cmp_ne_u32_e32 vcc, -1, v2 +; CI-NEXT: v_cndmask_b32_e32 v36, 0, v2, vcc +; CI-NEXT: v_cndmask_b32_e32 v49, 0, v31, vcc +; CI-NEXT: v_cmp_ne_u32_e32 vcc, -1, v3 +; CI-NEXT: v_cndmask_b32_e32 v37, 0, v3, vcc +; CI-NEXT: v_cndmask_b32_e32 v34, 0, v31, vcc +; CI-NEXT: v_cmp_ne_u32_e32 vcc, -1, v4 +; CI-NEXT: v_cmp_ne_u32_e64 s[4:5], -1, v5 +; CI-NEXT: v_cndmask_b32_e32 v38, 0, v4, vcc +; CI-NEXT: v_cndmask_b32_e64 v50, 0, v5, s[4:5] +; CI-NEXT: v_cndmask_b32_e64 v39, 0, v6, s[6:7] +; CI-NEXT: v_cndmask_b32_e64 v32, 0, v7, s[8:9] +; CI-NEXT: v_cmp_ne_u32_e64 s[10:11], -1, v8 +; CI-NEXT: v_cmp_ne_u32_e64 s[12:13], -1, v9 +; CI-NEXT: v_cmp_ne_u32_e64 s[14:15], -1, v10 +; CI-NEXT: v_cmp_ne_u32_e64 s[16:17], -1, v11 +; CI-NEXT: v_cmp_ne_u32_e64 s[18:19], -1, v12 +; CI-NEXT: v_cmp_ne_u32_e64 s[20:21], -1, v13 +; CI-NEXT: v_cmp_ne_u32_e64 s[22:23], -1, v14 +; CI-NEXT: v_cmp_ne_u32_e64 s[24:25], -1, v15 +; CI-NEXT: v_cndmask_b32_e64 v16, 0, v8, s[10:11] +; CI-NEXT: v_cndmask_b32_e64 v18, 0, v9, s[12:13] +; CI-NEXT: v_cndmask_b32_e64 v20, 0, v10, s[14:15] +; CI-NEXT: v_cndmask_b32_e64 v22, 0, v11, s[16:17] +; CI-NEXT: v_cndmask_b32_e64 v24, 0, v12, s[18:19] +; CI-NEXT: v_cndmask_b32_e64 v26, 0, v13, s[20:21] +; CI-NEXT: v_cndmask_b32_e64 v28, 0, v14, s[22:23] +; CI-NEXT: v_cndmask_b32_e64 v30, 0, v15, s[24:25] +; CI-NEXT: v_cndmask_b32_e32 v9, 0, v31, vcc +; CI-NEXT: v_cndmask_b32_e64 v11, 0, v31, s[4:5] +; CI-NEXT: v_cndmask_b32_e64 v13, 0, v31, s[6:7] +; CI-NEXT: v_cndmask_b32_e64 v15, 0, v31, s[8:9] +; CI-NEXT: v_cndmask_b32_e64 v17, 0, v31, s[10:11] +; CI-NEXT: v_cndmask_b32_e64 v19, 0, v31, s[12:13] +; CI-NEXT: v_cndmask_b32_e64 v21, 0, v31, s[14:15] +; CI-NEXT: v_cndmask_b32_e64 v23, 0, v31, s[16:17] +; CI-NEXT: v_cndmask_b32_e64 v25, 0, v31, s[18:19] +; CI-NEXT: v_cndmask_b32_e64 v27, 0, v31, s[20:21] +; CI-NEXT: v_cndmask_b32_e64 v29, 0, v31, s[22:23] +; CI-NEXT: v_cndmask_b32_e64 v31, 0, v31, s[24:25] +; CI-NEXT: v_mov_b32_e32 v1, v48 +; CI-NEXT: v_mov_b32_e32 v2, v35 +; CI-NEXT: v_mov_b32_e32 v3, v33 +; CI-NEXT: v_mov_b32_e32 v4, v36 +; CI-NEXT: v_mov_b32_e32 v5, v49 +; CI-NEXT: v_mov_b32_e32 v6, v37 +; CI-NEXT: v_mov_b32_e32 v7, v34 +; CI-NEXT: v_mov_b32_e32 v8, v38 +; CI-NEXT: v_mov_b32_e32 v10, v50 +; CI-NEXT: v_mov_b32_e32 v12, v39 +; CI-NEXT: v_mov_b32_e32 v14, v32 +; CI-NEXT: s_setpc_b64 s[30:31] +; +; GFX9-LABEL: addrspacecast_v16p5_to_v16p0: +; GFX9: ; %bb.0: +; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX9-NEXT: s_mov_b64 s[4:5], src_private_base +; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, -1, v0 +; GFX9-NEXT: v_mov_b32_e32 v31, s5 +; GFX9-NEXT: v_cndmask_b32_e32 v0, 0, v0, vcc +; GFX9-NEXT: v_cndmask_b32_e32 v48, 0, v31, vcc +; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, -1, v1 +; GFX9-NEXT: v_cndmask_b32_e32 v35, 0, v1, vcc +; GFX9-NEXT: v_cndmask_b32_e32 v33, 0, v31, vcc +; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, -1, v2 +; GFX9-NEXT: v_cndmask_b32_e32 v36, 0, v2, vcc +; GFX9-NEXT: v_cndmask_b32_e32 v49, 0, v31, vcc +; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, -1, v3 +; GFX9-NEXT: v_cndmask_b32_e32 v37, 0, v3, vcc +; GFX9-NEXT: v_cndmask_b32_e32 v34, 0, v31, vcc +; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, -1, v4 +; GFX9-NEXT: v_cmp_ne_u32_e64 s[4:5], -1, v5 +; GFX9-NEXT: v_cmp_ne_u32_e64 s[6:7], -1, v6 +; GFX9-NEXT: v_cmp_ne_u32_e64 s[8:9], -1, v7 +; GFX9-NEXT: v_cndmask_b32_e32 v38, 0, v4, vcc +; GFX9-NEXT: v_cndmask_b32_e64 v50, 0, v5, s[4:5] +; GFX9-NEXT: v_cndmask_b32_e64 v39, 0, v6, s[6:7] +; GFX9-NEXT: v_cndmask_b32_e64 v32, 0, v7, s[8:9] +; GFX9-NEXT: v_cmp_ne_u32_e64 s[10:11], -1, v8 +; GFX9-NEXT: v_cmp_ne_u32_e64 s[12:13], -1, v9 +; GFX9-NEXT: v_cmp_ne_u32_e64 s[14:15], -1, v10 +; GFX9-NEXT: v_cmp_ne_u32_e64 s[16:17], -1, v11 +; GFX9-NEXT: v_cmp_ne_u32_e64 s[18:19], -1, v12 +; GFX9-NEXT: v_cmp_ne_u32_e64 s[20:21], -1, v13 +; GFX9-NEXT: v_cmp_ne_u32_e64 s[22:23], -1, v14 +; GFX9-NEXT: v_cmp_ne_u32_e64 s[24:25], -1, v15 +; GFX9-NEXT: v_cndmask_b32_e64 v16, 0, v8, s[10:11] +; GFX9-NEXT: v_cndmask_b32_e64 v18, 0, v9, s[12:13] +; GFX9-NEXT: v_cndmask_b32_e64 v20, 0, v10, s[14:15] +; GFX9-NEXT: v_cndmask_b32_e64 v22, 0, v11, s[16:17] +; GFX9-NEXT: v_cndmask_b32_e64 v24, 0, v12, s[18:19] +; GFX9-NEXT: v_cndmask_b32_e64 v26, 0, v13, s[20:21] +; GFX9-NEXT: v_cndmask_b32_e64 v28, 0, v14, s[22:23] +; GFX9-NEXT: v_cndmask_b32_e64 v30, 0, v15, s[24:25] +; GFX9-NEXT: v_cndmask_b32_e32 v9, 0, v31, vcc +; GFX9-NEXT: v_cndmask_b32_e64 v11, 0, v31, s[4:5] +; GFX9-NEXT: v_cndmask_b32_e64 v13, 0, v31, s[6:7] +; GFX9-NEXT: v_cndmask_b32_e64 v15, 0, v31, s[8:9] +; GFX9-NEXT: v_cndmask_b32_e64 v17, 0, v31, s[10:11] +; GFX9-NEXT: v_cndmask_b32_e64 v19, 0, v31, s[12:13] +; GFX9-NEXT: v_cndmask_b32_e64 v21, 0, v31, s[14:15] +; GFX9-NEXT: v_cndmask_b32_e64 v23, 0, v31, s[16:17] +; GFX9-NEXT: v_cndmask_b32_e64 v25, 0, v31, s[18:19] +; GFX9-NEXT: v_cndmask_b32_e64 v27, 0, v31, s[20:21] +; GFX9-NEXT: v_cndmask_b32_e64 v29, 0, v31, s[22:23] +; GFX9-NEXT: v_cndmask_b32_e64 v31, 0, v31, s[24:25] +; GFX9-NEXT: v_mov_b32_e32 v1, v48 +; GFX9-NEXT: v_mov_b32_e32 v2, v35 +; GFX9-NEXT: v_mov_b32_e32 v3, v33 +; GFX9-NEXT: v_mov_b32_e32 v4, v36 +; GFX9-NEXT: v_mov_b32_e32 v5, v49 +; GFX9-NEXT: v_mov_b32_e32 v6, v37 +; GFX9-NEXT: v_mov_b32_e32 v7, v34 +; GFX9-NEXT: v_mov_b32_e32 v8, v38 +; GFX9-NEXT: v_mov_b32_e32 v10, v50 +; GFX9-NEXT: v_mov_b32_e32 v12, v39 +; GFX9-NEXT: v_mov_b32_e32 v14, v32 +; GFX9-NEXT: s_setpc_b64 s[30:31] + %cast = addrspacecast <16 x ptr addrspace(5)> %ptr to <16 x ptr> + ret <16 x ptr> %cast +} + +define <2 x ptr addrspace(3)> @addrspacecast_v2p0_to_v2p3(<2 x ptr> %ptr) { +; HSA-LABEL: addrspacecast_v2p0_to_v2p3: +; HSA: ; %bb.0: +; HSA-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; HSA-NEXT: v_cmp_ne_u64_e32 vcc, 0, v[0:1] +; HSA-NEXT: v_cndmask_b32_e32 v0, -1, v0, vcc +; HSA-NEXT: v_cmp_ne_u64_e32 vcc, 0, v[2:3] +; HSA-NEXT: v_cndmask_b32_e32 v1, -1, v2, vcc +; HSA-NEXT: s_setpc_b64 s[30:31] + %cast = addrspacecast <2 x ptr> %ptr to <2 x ptr addrspace(3)> + ret <2 x ptr addrspace(3)> %cast +} + +define <3 x ptr addrspace(3)> @addrspacecast_v3p0_to_v3p3(<3 x ptr> %ptr) { +; HSA-LABEL: addrspacecast_v3p0_to_v3p3: +; HSA: ; %bb.0: +; HSA-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; HSA-NEXT: v_cmp_ne_u64_e32 vcc, 0, v[0:1] +; HSA-NEXT: v_cndmask_b32_e32 v0, -1, v0, vcc +; HSA-NEXT: v_cmp_ne_u64_e32 vcc, 0, v[2:3] +; HSA-NEXT: v_cndmask_b32_e32 v1, -1, v2, vcc +; HSA-NEXT: v_cmp_ne_u64_e32 vcc, 0, v[4:5] +; HSA-NEXT: v_cndmask_b32_e32 v2, -1, v4, vcc +; HSA-NEXT: s_setpc_b64 s[30:31] + %cast = addrspacecast <3 x ptr> %ptr to <3 x ptr addrspace(3)> + ret <3 x ptr addrspace(3)> %cast +} + +define <4 x ptr addrspace(3)> @addrspacecast_v4p0_to_v4p3(<4 x ptr> %ptr) { +; HSA-LABEL: addrspacecast_v4p0_to_v4p3: +; HSA: ; %bb.0: +; HSA-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; HSA-NEXT: v_cmp_ne_u64_e32 vcc, 0, v[0:1] +; HSA-NEXT: v_cndmask_b32_e32 v0, -1, v0, vcc +; HSA-NEXT: v_cmp_ne_u64_e32 vcc, 0, v[2:3] +; HSA-NEXT: v_cndmask_b32_e32 v1, -1, v2, vcc +; HSA-NEXT: v_cmp_ne_u64_e32 vcc, 0, v[4:5] +; HSA-NEXT: v_cndmask_b32_e32 v2, -1, v4, vcc +; HSA-NEXT: v_cmp_ne_u64_e32 vcc, 0, v[6:7] +; HSA-NEXT: v_cndmask_b32_e32 v3, -1, v6, vcc +; HSA-NEXT: s_setpc_b64 s[30:31] + %cast = addrspacecast <4 x ptr> %ptr to <4 x ptr addrspace(3)> + ret <4 x ptr addrspace(3)> %cast +} + +define <8 x ptr addrspace(3)> @addrspacecast_v8p0_to_v8p3(<8 x ptr> %ptr) { +; HSA-LABEL: addrspacecast_v8p0_to_v8p3: +; HSA: ; %bb.0: +; HSA-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; HSA-NEXT: v_cmp_ne_u64_e32 vcc, 0, v[0:1] +; HSA-NEXT: v_cndmask_b32_e32 v0, -1, v0, vcc +; HSA-NEXT: v_cmp_ne_u64_e32 vcc, 0, v[2:3] +; HSA-NEXT: v_cndmask_b32_e32 v1, -1, v2, vcc +; HSA-NEXT: v_cmp_ne_u64_e32 vcc, 0, v[4:5] +; HSA-NEXT: v_cndmask_b32_e32 v2, -1, v4, vcc +; HSA-NEXT: v_cmp_ne_u64_e32 vcc, 0, v[6:7] +; HSA-NEXT: v_cndmask_b32_e32 v3, -1, v6, vcc +; HSA-NEXT: v_cmp_ne_u64_e32 vcc, 0, v[8:9] +; HSA-NEXT: v_cndmask_b32_e32 v4, -1, v8, vcc +; HSA-NEXT: v_cmp_ne_u64_e32 vcc, 0, v[10:11] +; HSA-NEXT: v_cndmask_b32_e32 v5, -1, v10, vcc +; HSA-NEXT: v_cmp_ne_u64_e32 vcc, 0, v[12:13] +; HSA-NEXT: v_cndmask_b32_e32 v6, -1, v12, vcc +; HSA-NEXT: v_cmp_ne_u64_e32 vcc, 0, v[14:15] +; HSA-NEXT: v_cndmask_b32_e32 v7, -1, v14, vcc +; HSA-NEXT: s_setpc_b64 s[30:31] + %cast = addrspacecast <8 x ptr> %ptr to <8 x ptr addrspace(3)> + ret <8 x ptr addrspace(3)> %cast +} + +define <16 x ptr addrspace(3)> @addrspacecast_v16p0_to_v16p3(<16 x ptr> %ptr) { +; HSA-LABEL: addrspacecast_v16p0_to_v16p3: +; HSA: ; %bb.0: +; HSA-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; HSA-NEXT: buffer_load_dword v31, off, s[0:3], s32 +; HSA-NEXT: v_cmp_ne_u64_e32 vcc, 0, v[0:1] +; HSA-NEXT: v_cmp_ne_u64_e64 s[4:5], 0, v[24:25] +; HSA-NEXT: v_cndmask_b32_e32 v0, -1, v0, vcc +; HSA-NEXT: v_cmp_ne_u64_e32 vcc, 0, v[2:3] +; HSA-NEXT: v_cmp_ne_u64_e64 s[6:7], 0, v[26:27] +; HSA-NEXT: v_cndmask_b32_e32 v1, -1, v2, vcc +; HSA-NEXT: v_cmp_ne_u64_e32 vcc, 0, v[4:5] +; HSA-NEXT: v_cmp_ne_u64_e64 s[8:9], 0, v[28:29] +; HSA-NEXT: v_cndmask_b32_e32 v2, -1, v4, vcc +; HSA-NEXT: v_cmp_ne_u64_e32 vcc, 0, v[6:7] +; HSA-NEXT: v_cndmask_b32_e32 v3, -1, v6, vcc +; HSA-NEXT: v_cmp_ne_u64_e32 vcc, 0, v[8:9] +; HSA-NEXT: v_cndmask_b32_e32 v4, -1, v8, vcc +; HSA-NEXT: v_cmp_ne_u64_e32 vcc, 0, v[10:11] +; HSA-NEXT: v_cndmask_b32_e32 v5, -1, v10, vcc +; HSA-NEXT: v_cmp_ne_u64_e32 vcc, 0, v[12:13] +; HSA-NEXT: v_cndmask_b32_e64 v13, -1, v26, s[6:7] +; HSA-NEXT: v_cndmask_b32_e32 v6, -1, v12, vcc +; HSA-NEXT: v_cmp_ne_u64_e32 vcc, 0, v[14:15] +; HSA-NEXT: v_cndmask_b32_e64 v12, -1, v24, s[4:5] +; HSA-NEXT: v_cndmask_b32_e32 v7, -1, v14, vcc +; HSA-NEXT: v_cmp_ne_u64_e32 vcc, 0, v[16:17] +; HSA-NEXT: v_cndmask_b32_e64 v14, -1, v28, s[8:9] +; HSA-NEXT: v_cndmask_b32_e32 v8, -1, v16, vcc +; HSA-NEXT: v_cmp_ne_u64_e32 vcc, 0, v[18:19] +; HSA-NEXT: v_cndmask_b32_e32 v9, -1, v18, vcc +; HSA-NEXT: v_cmp_ne_u64_e32 vcc, 0, v[20:21] +; HSA-NEXT: v_cndmask_b32_e32 v10, -1, v20, vcc +; HSA-NEXT: v_cmp_ne_u64_e32 vcc, 0, v[22:23] +; HSA-NEXT: v_cndmask_b32_e32 v11, -1, v22, vcc +; HSA-NEXT: s_waitcnt vmcnt(0) +; HSA-NEXT: v_cmp_ne_u64_e32 vcc, 0, v[30:31] +; HSA-NEXT: v_cndmask_b32_e32 v15, -1, v30, vcc +; HSA-NEXT: s_setpc_b64 s[30:31] + %cast = addrspacecast <16 x ptr> %ptr to <16 x ptr addrspace(3)> + ret <16 x ptr addrspace(3)> %cast +} + +define <2 x ptr> @addrspacecast_v2p3_to_v2p0(<2 x ptr addrspace(3)> %ptr) { +; CI-LABEL: addrspacecast_v2p3_to_v2p0: +; CI: ; %bb.0: +; CI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; CI-NEXT: s_load_dword s4, s[6:7], 0x10 +; CI-NEXT: v_cmp_ne_u32_e32 vcc, -1, v0 +; CI-NEXT: v_cndmask_b32_e32 v0, 0, v0, vcc +; CI-NEXT: s_waitcnt lgkmcnt(0) +; CI-NEXT: v_mov_b32_e32 v3, s4 +; CI-NEXT: v_cndmask_b32_e32 v4, 0, v3, vcc +; CI-NEXT: v_cmp_ne_u32_e32 vcc, -1, v1 +; CI-NEXT: v_cndmask_b32_e32 v2, 0, v1, vcc +; CI-NEXT: v_cndmask_b32_e32 v3, 0, v3, vcc +; CI-NEXT: v_mov_b32_e32 v1, v4 +; CI-NEXT: s_setpc_b64 s[30:31] +; +; GFX9-LABEL: addrspacecast_v2p3_to_v2p0: +; GFX9: ; %bb.0: +; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX9-NEXT: s_mov_b64 s[4:5], src_shared_base +; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, -1, v0 +; GFX9-NEXT: v_mov_b32_e32 v3, s5 +; GFX9-NEXT: v_cndmask_b32_e32 v0, 0, v0, vcc +; GFX9-NEXT: v_cndmask_b32_e32 v4, 0, v3, vcc +; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, -1, v1 +; GFX9-NEXT: v_cndmask_b32_e32 v2, 0, v1, vcc +; GFX9-NEXT: v_cndmask_b32_e32 v3, 0, v3, vcc +; GFX9-NEXT: v_mov_b32_e32 v1, v4 +; GFX9-NEXT: s_setpc_b64 s[30:31] + %cast = addrspacecast <2 x ptr addrspace(3)> %ptr to <2 x ptr> + ret <2 x ptr> %cast +} + +define <3 x ptr> @addrspacecast_v3p3_to_v3p0(<3 x ptr addrspace(3)> %ptr) { +; CI-LABEL: addrspacecast_v3p3_to_v3p0: +; CI: ; %bb.0: +; CI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; CI-NEXT: s_load_dword s4, s[6:7], 0x10 +; CI-NEXT: v_cmp_ne_u32_e32 vcc, -1, v0 +; CI-NEXT: v_cndmask_b32_e32 v0, 0, v0, vcc +; CI-NEXT: s_waitcnt lgkmcnt(0) +; CI-NEXT: v_mov_b32_e32 v5, s4 +; CI-NEXT: v_cndmask_b32_e32 v7, 0, v5, vcc +; CI-NEXT: v_cmp_ne_u32_e32 vcc, -1, v1 +; CI-NEXT: v_cndmask_b32_e32 v6, 0, v1, vcc +; CI-NEXT: v_cndmask_b32_e32 v3, 0, v5, vcc +; CI-NEXT: v_cmp_ne_u32_e32 vcc, -1, v2 +; CI-NEXT: v_cndmask_b32_e32 v4, 0, v2, vcc +; CI-NEXT: v_cndmask_b32_e32 v5, 0, v5, vcc +; CI-NEXT: v_mov_b32_e32 v1, v7 +; CI-NEXT: v_mov_b32_e32 v2, v6 +; CI-NEXT: s_setpc_b64 s[30:31] +; +; GFX9-LABEL: addrspacecast_v3p3_to_v3p0: +; GFX9: ; %bb.0: +; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX9-NEXT: s_mov_b64 s[4:5], src_shared_base +; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, -1, v0 +; GFX9-NEXT: v_mov_b32_e32 v5, s5 +; GFX9-NEXT: v_cndmask_b32_e32 v0, 0, v0, vcc +; GFX9-NEXT: v_cndmask_b32_e32 v7, 0, v5, vcc +; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, -1, v1 +; GFX9-NEXT: v_cndmask_b32_e32 v6, 0, v1, vcc +; GFX9-NEXT: v_cndmask_b32_e32 v3, 0, v5, vcc +; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, -1, v2 +; GFX9-NEXT: v_cndmask_b32_e32 v4, 0, v2, vcc +; GFX9-NEXT: v_cndmask_b32_e32 v5, 0, v5, vcc +; GFX9-NEXT: v_mov_b32_e32 v1, v7 +; GFX9-NEXT: v_mov_b32_e32 v2, v6 +; GFX9-NEXT: s_setpc_b64 s[30:31] + %cast = addrspacecast <3 x ptr addrspace(3)> %ptr to <3 x ptr> + ret <3 x ptr> %cast +} + +define <4 x ptr> @addrspacecast_v4p3_to_v4p0(<4 x ptr addrspace(3)> %ptr) { +; CI-LABEL: addrspacecast_v4p3_to_v4p0: +; CI: ; %bb.0: +; CI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; CI-NEXT: s_load_dword s4, s[6:7], 0x10 +; CI-NEXT: v_cmp_ne_u32_e32 vcc, -1, v0 +; CI-NEXT: v_cndmask_b32_e32 v0, 0, v0, vcc +; CI-NEXT: s_waitcnt lgkmcnt(0) +; CI-NEXT: v_mov_b32_e32 v7, s4 +; CI-NEXT: v_cndmask_b32_e32 v10, 0, v7, vcc +; CI-NEXT: v_cmp_ne_u32_e32 vcc, -1, v1 +; CI-NEXT: v_cndmask_b32_e32 v8, 0, v1, vcc +; CI-NEXT: v_cndmask_b32_e32 v9, 0, v7, vcc +; CI-NEXT: v_cmp_ne_u32_e32 vcc, -1, v2 +; CI-NEXT: v_cndmask_b32_e32 v4, 0, v2, vcc +; CI-NEXT: v_cndmask_b32_e32 v5, 0, v7, vcc +; CI-NEXT: v_cmp_ne_u32_e32 vcc, -1, v3 +; CI-NEXT: v_cndmask_b32_e32 v6, 0, v3, vcc +; CI-NEXT: v_cndmask_b32_e32 v7, 0, v7, vcc +; CI-NEXT: v_mov_b32_e32 v1, v10 +; CI-NEXT: v_mov_b32_e32 v2, v8 +; CI-NEXT: v_mov_b32_e32 v3, v9 +; CI-NEXT: s_setpc_b64 s[30:31] +; +; GFX9-LABEL: addrspacecast_v4p3_to_v4p0: +; GFX9: ; %bb.0: +; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX9-NEXT: s_mov_b64 s[4:5], src_shared_base +; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, -1, v0 +; GFX9-NEXT: v_mov_b32_e32 v7, s5 +; GFX9-NEXT: v_cndmask_b32_e32 v0, 0, v0, vcc +; GFX9-NEXT: v_cndmask_b32_e32 v10, 0, v7, vcc +; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, -1, v1 +; GFX9-NEXT: v_cndmask_b32_e32 v8, 0, v1, vcc +; GFX9-NEXT: v_cndmask_b32_e32 v9, 0, v7, vcc +; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, -1, v2 +; GFX9-NEXT: v_cndmask_b32_e32 v4, 0, v2, vcc +; GFX9-NEXT: v_cndmask_b32_e32 v5, 0, v7, vcc +; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, -1, v3 +; GFX9-NEXT: v_cndmask_b32_e32 v6, 0, v3, vcc +; GFX9-NEXT: v_cndmask_b32_e32 v7, 0, v7, vcc +; GFX9-NEXT: v_mov_b32_e32 v1, v10 +; GFX9-NEXT: v_mov_b32_e32 v2, v8 +; GFX9-NEXT: v_mov_b32_e32 v3, v9 +; GFX9-NEXT: s_setpc_b64 s[30:31] + %cast = addrspacecast <4 x ptr addrspace(3)> %ptr to <4 x ptr> + ret <4 x ptr> %cast +} + +define <8 x ptr> @addrspacecast_v8p3_to_v8p0(<8 x ptr addrspace(3)> %ptr) { +; CI-LABEL: addrspacecast_v8p3_to_v8p0: +; CI: ; %bb.0: +; CI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; CI-NEXT: s_load_dword s4, s[6:7], 0x10 +; CI-NEXT: v_cmp_ne_u32_e32 vcc, -1, v0 +; CI-NEXT: v_cndmask_b32_e32 v0, 0, v0, vcc +; CI-NEXT: s_waitcnt lgkmcnt(0) +; CI-NEXT: v_mov_b32_e32 v15, s4 +; CI-NEXT: v_cndmask_b32_e32 v22, 0, v15, vcc +; CI-NEXT: v_cmp_ne_u32_e32 vcc, -1, v1 +; CI-NEXT: v_cndmask_b32_e32 v16, 0, v1, vcc +; CI-NEXT: v_cndmask_b32_e32 v17, 0, v15, vcc +; CI-NEXT: v_cmp_ne_u32_e32 vcc, -1, v2 +; CI-NEXT: v_cndmask_b32_e32 v18, 0, v2, vcc +; CI-NEXT: v_cndmask_b32_e32 v19, 0, v15, vcc +; CI-NEXT: v_cmp_ne_u32_e32 vcc, -1, v3 +; CI-NEXT: v_cndmask_b32_e32 v20, 0, v3, vcc +; CI-NEXT: v_cndmask_b32_e32 v21, 0, v15, vcc +; CI-NEXT: v_cmp_ne_u32_e32 vcc, -1, v4 +; CI-NEXT: v_cndmask_b32_e32 v8, 0, v4, vcc +; CI-NEXT: v_cndmask_b32_e32 v9, 0, v15, vcc +; CI-NEXT: v_cmp_ne_u32_e32 vcc, -1, v5 +; CI-NEXT: v_cndmask_b32_e32 v10, 0, v5, vcc +; CI-NEXT: v_cndmask_b32_e32 v11, 0, v15, vcc +; CI-NEXT: v_cmp_ne_u32_e32 vcc, -1, v6 +; CI-NEXT: v_cndmask_b32_e32 v12, 0, v6, vcc +; CI-NEXT: v_cndmask_b32_e32 v13, 0, v15, vcc +; CI-NEXT: v_cmp_ne_u32_e32 vcc, -1, v7 +; CI-NEXT: v_cndmask_b32_e32 v14, 0, v7, vcc +; CI-NEXT: v_cndmask_b32_e32 v15, 0, v15, vcc +; CI-NEXT: v_mov_b32_e32 v1, v22 +; CI-NEXT: v_mov_b32_e32 v2, v16 +; CI-NEXT: v_mov_b32_e32 v3, v17 +; CI-NEXT: v_mov_b32_e32 v4, v18 +; CI-NEXT: v_mov_b32_e32 v5, v19 +; CI-NEXT: v_mov_b32_e32 v6, v20 +; CI-NEXT: v_mov_b32_e32 v7, v21 +; CI-NEXT: s_setpc_b64 s[30:31] +; +; GFX9-LABEL: addrspacecast_v8p3_to_v8p0: +; GFX9: ; %bb.0: +; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX9-NEXT: s_mov_b64 s[4:5], src_shared_base +; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, -1, v0 +; GFX9-NEXT: v_mov_b32_e32 v15, s5 +; GFX9-NEXT: v_cndmask_b32_e32 v0, 0, v0, vcc +; GFX9-NEXT: v_cndmask_b32_e32 v22, 0, v15, vcc +; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, -1, v1 +; GFX9-NEXT: v_cndmask_b32_e32 v16, 0, v1, vcc +; GFX9-NEXT: v_cndmask_b32_e32 v17, 0, v15, vcc +; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, -1, v2 +; GFX9-NEXT: v_cndmask_b32_e32 v18, 0, v2, vcc +; GFX9-NEXT: v_cndmask_b32_e32 v19, 0, v15, vcc +; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, -1, v3 +; GFX9-NEXT: v_cndmask_b32_e32 v20, 0, v3, vcc +; GFX9-NEXT: v_cndmask_b32_e32 v21, 0, v15, vcc +; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, -1, v4 +; GFX9-NEXT: v_cndmask_b32_e32 v8, 0, v4, vcc +; GFX9-NEXT: v_cndmask_b32_e32 v9, 0, v15, vcc +; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, -1, v5 +; GFX9-NEXT: v_cndmask_b32_e32 v10, 0, v5, vcc +; GFX9-NEXT: v_cndmask_b32_e32 v11, 0, v15, vcc +; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, -1, v6 +; GFX9-NEXT: v_cndmask_b32_e32 v12, 0, v6, vcc +; GFX9-NEXT: v_cndmask_b32_e32 v13, 0, v15, vcc +; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, -1, v7 +; GFX9-NEXT: v_cndmask_b32_e32 v14, 0, v7, vcc +; GFX9-NEXT: v_cndmask_b32_e32 v15, 0, v15, vcc +; GFX9-NEXT: v_mov_b32_e32 v1, v22 +; GFX9-NEXT: v_mov_b32_e32 v2, v16 +; GFX9-NEXT: v_mov_b32_e32 v3, v17 +; GFX9-NEXT: v_mov_b32_e32 v4, v18 +; GFX9-NEXT: v_mov_b32_e32 v5, v19 +; GFX9-NEXT: v_mov_b32_e32 v6, v20 +; GFX9-NEXT: v_mov_b32_e32 v7, v21 +; GFX9-NEXT: s_setpc_b64 s[30:31] + %cast = addrspacecast <8 x ptr addrspace(3)> %ptr to <8 x ptr> + ret <8 x ptr> %cast +} + +define <16 x ptr> @addrspacecast_v16p3_to_v16p0(<16 x ptr addrspace(3)> %ptr) { +; CI-LABEL: addrspacecast_v16p3_to_v16p0: +; CI: ; %bb.0: +; CI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; CI-NEXT: s_load_dword s4, s[6:7], 0x10 +; CI-NEXT: v_cmp_ne_u32_e32 vcc, -1, v0 +; CI-NEXT: v_cndmask_b32_e32 v0, 0, v0, vcc +; CI-NEXT: v_cmp_ne_u32_e64 s[6:7], -1, v6 +; CI-NEXT: v_cmp_ne_u32_e64 s[8:9], -1, v7 +; CI-NEXT: s_waitcnt lgkmcnt(0) +; CI-NEXT: v_mov_b32_e32 v31, s4 +; CI-NEXT: v_cndmask_b32_e32 v48, 0, v31, vcc +; CI-NEXT: v_cmp_ne_u32_e32 vcc, -1, v1 +; CI-NEXT: v_cndmask_b32_e32 v35, 0, v1, vcc +; CI-NEXT: v_cndmask_b32_e32 v33, 0, v31, vcc +; CI-NEXT: v_cmp_ne_u32_e32 vcc, -1, v2 +; CI-NEXT: v_cndmask_b32_e32 v36, 0, v2, vcc +; CI-NEXT: v_cndmask_b32_e32 v49, 0, v31, vcc +; CI-NEXT: v_cmp_ne_u32_e32 vcc, -1, v3 +; CI-NEXT: v_cndmask_b32_e32 v37, 0, v3, vcc +; CI-NEXT: v_cndmask_b32_e32 v34, 0, v31, vcc +; CI-NEXT: v_cmp_ne_u32_e32 vcc, -1, v4 +; CI-NEXT: v_cmp_ne_u32_e64 s[4:5], -1, v5 +; CI-NEXT: v_cndmask_b32_e32 v38, 0, v4, vcc +; CI-NEXT: v_cndmask_b32_e64 v50, 0, v5, s[4:5] +; CI-NEXT: v_cndmask_b32_e64 v39, 0, v6, s[6:7] +; CI-NEXT: v_cndmask_b32_e64 v32, 0, v7, s[8:9] +; CI-NEXT: v_cmp_ne_u32_e64 s[10:11], -1, v8 +; CI-NEXT: v_cmp_ne_u32_e64 s[12:13], -1, v9 +; CI-NEXT: v_cmp_ne_u32_e64 s[14:15], -1, v10 +; CI-NEXT: v_cmp_ne_u32_e64 s[16:17], -1, v11 +; CI-NEXT: v_cmp_ne_u32_e64 s[18:19], -1, v12 +; CI-NEXT: v_cmp_ne_u32_e64 s[20:21], -1, v13 +; CI-NEXT: v_cmp_ne_u32_e64 s[22:23], -1, v14 +; CI-NEXT: v_cmp_ne_u32_e64 s[24:25], -1, v15 +; CI-NEXT: v_cndmask_b32_e64 v16, 0, v8, s[10:11] +; CI-NEXT: v_cndmask_b32_e64 v18, 0, v9, s[12:13] +; CI-NEXT: v_cndmask_b32_e64 v20, 0, v10, s[14:15] +; CI-NEXT: v_cndmask_b32_e64 v22, 0, v11, s[16:17] +; CI-NEXT: v_cndmask_b32_e64 v24, 0, v12, s[18:19] +; CI-NEXT: v_cndmask_b32_e64 v26, 0, v13, s[20:21] +; CI-NEXT: v_cndmask_b32_e64 v28, 0, v14, s[22:23] +; CI-NEXT: v_cndmask_b32_e64 v30, 0, v15, s[24:25] +; CI-NEXT: v_cndmask_b32_e32 v9, 0, v31, vcc +; CI-NEXT: v_cndmask_b32_e64 v11, 0, v31, s[4:5] +; CI-NEXT: v_cndmask_b32_e64 v13, 0, v31, s[6:7] +; CI-NEXT: v_cndmask_b32_e64 v15, 0, v31, s[8:9] +; CI-NEXT: v_cndmask_b32_e64 v17, 0, v31, s[10:11] +; CI-NEXT: v_cndmask_b32_e64 v19, 0, v31, s[12:13] +; CI-NEXT: v_cndmask_b32_e64 v21, 0, v31, s[14:15] +; CI-NEXT: v_cndmask_b32_e64 v23, 0, v31, s[16:17] +; CI-NEXT: v_cndmask_b32_e64 v25, 0, v31, s[18:19] +; CI-NEXT: v_cndmask_b32_e64 v27, 0, v31, s[20:21] +; CI-NEXT: v_cndmask_b32_e64 v29, 0, v31, s[22:23] +; CI-NEXT: v_cndmask_b32_e64 v31, 0, v31, s[24:25] +; CI-NEXT: v_mov_b32_e32 v1, v48 +; CI-NEXT: v_mov_b32_e32 v2, v35 +; CI-NEXT: v_mov_b32_e32 v3, v33 +; CI-NEXT: v_mov_b32_e32 v4, v36 +; CI-NEXT: v_mov_b32_e32 v5, v49 +; CI-NEXT: v_mov_b32_e32 v6, v37 +; CI-NEXT: v_mov_b32_e32 v7, v34 +; CI-NEXT: v_mov_b32_e32 v8, v38 +; CI-NEXT: v_mov_b32_e32 v10, v50 +; CI-NEXT: v_mov_b32_e32 v12, v39 +; CI-NEXT: v_mov_b32_e32 v14, v32 +; CI-NEXT: s_setpc_b64 s[30:31] +; +; GFX9-LABEL: addrspacecast_v16p3_to_v16p0: +; GFX9: ; %bb.0: +; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX9-NEXT: s_mov_b64 s[4:5], src_shared_base +; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, -1, v0 +; GFX9-NEXT: v_mov_b32_e32 v31, s5 +; GFX9-NEXT: v_cndmask_b32_e32 v0, 0, v0, vcc +; GFX9-NEXT: v_cndmask_b32_e32 v48, 0, v31, vcc +; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, -1, v1 +; GFX9-NEXT: v_cndmask_b32_e32 v35, 0, v1, vcc +; GFX9-NEXT: v_cndmask_b32_e32 v33, 0, v31, vcc +; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, -1, v2 +; GFX9-NEXT: v_cndmask_b32_e32 v36, 0, v2, vcc +; GFX9-NEXT: v_cndmask_b32_e32 v49, 0, v31, vcc +; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, -1, v3 +; GFX9-NEXT: v_cndmask_b32_e32 v37, 0, v3, vcc +; GFX9-NEXT: v_cndmask_b32_e32 v34, 0, v31, vcc +; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, -1, v4 +; GFX9-NEXT: v_cmp_ne_u32_e64 s[4:5], -1, v5 +; GFX9-NEXT: v_cmp_ne_u32_e64 s[6:7], -1, v6 +; GFX9-NEXT: v_cmp_ne_u32_e64 s[8:9], -1, v7 +; GFX9-NEXT: v_cndmask_b32_e32 v38, 0, v4, vcc +; GFX9-NEXT: v_cndmask_b32_e64 v50, 0, v5, s[4:5] +; GFX9-NEXT: v_cndmask_b32_e64 v39, 0, v6, s[6:7] +; GFX9-NEXT: v_cndmask_b32_e64 v32, 0, v7, s[8:9] +; GFX9-NEXT: v_cmp_ne_u32_e64 s[10:11], -1, v8 +; GFX9-NEXT: v_cmp_ne_u32_e64 s[12:13], -1, v9 +; GFX9-NEXT: v_cmp_ne_u32_e64 s[14:15], -1, v10 +; GFX9-NEXT: v_cmp_ne_u32_e64 s[16:17], -1, v11 +; GFX9-NEXT: v_cmp_ne_u32_e64 s[18:19], -1, v12 +; GFX9-NEXT: v_cmp_ne_u32_e64 s[20:21], -1, v13 +; GFX9-NEXT: v_cmp_ne_u32_e64 s[22:23], -1, v14 +; GFX9-NEXT: v_cmp_ne_u32_e64 s[24:25], -1, v15 +; GFX9-NEXT: v_cndmask_b32_e64 v16, 0, v8, s[10:11] +; GFX9-NEXT: v_cndmask_b32_e64 v18, 0, v9, s[12:13] +; GFX9-NEXT: v_cndmask_b32_e64 v20, 0, v10, s[14:15] +; GFX9-NEXT: v_cndmask_b32_e64 v22, 0, v11, s[16:17] +; GFX9-NEXT: v_cndmask_b32_e64 v24, 0, v12, s[18:19] +; GFX9-NEXT: v_cndmask_b32_e64 v26, 0, v13, s[20:21] +; GFX9-NEXT: v_cndmask_b32_e64 v28, 0, v14, s[22:23] +; GFX9-NEXT: v_cndmask_b32_e64 v30, 0, v15, s[24:25] +; GFX9-NEXT: v_cndmask_b32_e32 v9, 0, v31, vcc +; GFX9-NEXT: v_cndmask_b32_e64 v11, 0, v31, s[4:5] +; GFX9-NEXT: v_cndmask_b32_e64 v13, 0, v31, s[6:7] +; GFX9-NEXT: v_cndmask_b32_e64 v15, 0, v31, s[8:9] +; GFX9-NEXT: v_cndmask_b32_e64 v17, 0, v31, s[10:11] +; GFX9-NEXT: v_cndmask_b32_e64 v19, 0, v31, s[12:13] +; GFX9-NEXT: v_cndmask_b32_e64 v21, 0, v31, s[14:15] +; GFX9-NEXT: v_cndmask_b32_e64 v23, 0, v31, s[16:17] +; GFX9-NEXT: v_cndmask_b32_e64 v25, 0, v31, s[18:19] +; GFX9-NEXT: v_cndmask_b32_e64 v27, 0, v31, s[20:21] +; GFX9-NEXT: v_cndmask_b32_e64 v29, 0, v31, s[22:23] +; GFX9-NEXT: v_cndmask_b32_e64 v31, 0, v31, s[24:25] +; GFX9-NEXT: v_mov_b32_e32 v1, v48 +; GFX9-NEXT: v_mov_b32_e32 v2, v35 +; GFX9-NEXT: v_mov_b32_e32 v3, v33 +; GFX9-NEXT: v_mov_b32_e32 v4, v36 +; GFX9-NEXT: v_mov_b32_e32 v5, v49 +; GFX9-NEXT: v_mov_b32_e32 v6, v37 +; GFX9-NEXT: v_mov_b32_e32 v7, v34 +; GFX9-NEXT: v_mov_b32_e32 v8, v38 +; GFX9-NEXT: v_mov_b32_e32 v10, v50 +; GFX9-NEXT: v_mov_b32_e32 v12, v39 +; GFX9-NEXT: v_mov_b32_e32 v14, v32 +; GFX9-NEXT: s_setpc_b64 s[30:31] + %cast = addrspacecast <16 x ptr addrspace(3)> %ptr to <16 x ptr> + ret <16 x ptr> %cast +} + +define <2 x ptr addrspace(1)> @addrspacecast_v2p0_to_v2p1(<2 x ptr> %ptr) { +; HSA-LABEL: addrspacecast_v2p0_to_v2p1: +; HSA: ; %bb.0: +; HSA-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; HSA-NEXT: s_setpc_b64 s[30:31] + %cast = addrspacecast <2 x ptr> %ptr to <2 x ptr addrspace(1)> + ret <2 x ptr addrspace(1)> %cast +} + +define <3 x ptr addrspace(1)> @addrspacecast_v3p0_to_v3p1(<3 x ptr> %ptr) { +; HSA-LABEL: addrspacecast_v3p0_to_v3p1: +; HSA: ; %bb.0: +; HSA-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; HSA-NEXT: s_setpc_b64 s[30:31] + %cast = addrspacecast <3 x ptr> %ptr to <3 x ptr addrspace(1)> + ret <3 x ptr addrspace(1)> %cast +} + +define <4 x ptr addrspace(1)> @addrspacecast_v4p0_to_v4p1(<4 x ptr> %ptr) { +; HSA-LABEL: addrspacecast_v4p0_to_v4p1: +; HSA: ; %bb.0: +; HSA-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; HSA-NEXT: s_setpc_b64 s[30:31] + %cast = addrspacecast <4 x ptr> %ptr to <4 x ptr addrspace(1)> + ret <4 x ptr addrspace(1)> %cast +} + +define <8 x ptr addrspace(1)> @addrspacecast_v8p0_to_v8p1(<8 x ptr> %ptr) { +; HSA-LABEL: addrspacecast_v8p0_to_v8p1: +; HSA: ; %bb.0: +; HSA-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; HSA-NEXT: s_setpc_b64 s[30:31] + %cast = addrspacecast <8 x ptr> %ptr to <8 x ptr addrspace(1)> + ret <8 x ptr addrspace(1)> %cast +} + +define <16 x ptr addrspace(1)> @addrspacecast_v16p0_to_v16p1(<16 x ptr> %ptr) { +; HSA-LABEL: addrspacecast_v16p0_to_v16p1: +; HSA: ; %bb.0: +; HSA-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; HSA-NEXT: buffer_load_dword v31, off, s[0:3], s32 +; HSA-NEXT: s_waitcnt vmcnt(0) +; HSA-NEXT: s_setpc_b64 s[30:31] + %cast = addrspacecast <16 x ptr> %ptr to <16 x ptr addrspace(1)> + ret <16 x ptr addrspace(1)> %cast +} + +define <2 x ptr> @addrspacecast_v2p1_to_v2p0(<2 x ptr addrspace(1)> %ptr) { +; HSA-LABEL: addrspacecast_v2p1_to_v2p0: +; HSA: ; %bb.0: +; HSA-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; HSA-NEXT: s_setpc_b64 s[30:31] + %cast = addrspacecast <2 x ptr addrspace(1)> %ptr to <2 x ptr> + ret <2 x ptr> %cast +} + +define <1 x ptr> @addrspacecast_v1p1_to_v1p0(<1 x ptr addrspace(1)> %ptr) { +; HSA-LABEL: addrspacecast_v1p1_to_v1p0: +; HSA: ; %bb.0: +; HSA-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; HSA-NEXT: s_setpc_b64 s[30:31] + %cast = addrspacecast <1 x ptr addrspace(1)> %ptr to <1 x ptr> + ret <1 x ptr> %cast +} + +define <4 x ptr> @addrspacecast_v4p1_to_v4p0(<4 x ptr addrspace(1)> %ptr) { +; HSA-LABEL: addrspacecast_v4p1_to_v4p0: +; HSA: ; %bb.0: +; HSA-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; HSA-NEXT: s_setpc_b64 s[30:31] + %cast = addrspacecast <4 x ptr addrspace(1)> %ptr to <4 x ptr> + ret <4 x ptr> %cast +} + +define <8 x ptr> @addrspacecast_v8p1_to_v8p0(<8 x ptr addrspace(1)> %ptr) { +; HSA-LABEL: addrspacecast_v8p1_to_v8p0: +; HSA: ; %bb.0: +; HSA-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; HSA-NEXT: s_setpc_b64 s[30:31] + %cast = addrspacecast <8 x ptr addrspace(1)> %ptr to <8 x ptr> + ret <8 x ptr> %cast +} + +define <16 x ptr> @addrspacecast_v16p1_to_v16p0(<16 x ptr addrspace(1)> %ptr) { +; HSA-LABEL: addrspacecast_v16p1_to_v16p0: +; HSA: ; %bb.0: +; HSA-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; HSA-NEXT: buffer_load_dword v31, off, s[0:3], s32 +; HSA-NEXT: s_waitcnt vmcnt(0) +; HSA-NEXT: s_setpc_b64 s[30:31] + %cast = addrspacecast <16 x ptr addrspace(1)> %ptr to <16 x ptr> + ret <16 x ptr> %cast +} + +define <2 x ptr addrspace(6)> @addrspacecast_v2p0_to_v2p6(<2 x ptr> %ptr) { +; HSA-LABEL: addrspacecast_v2p0_to_v2p6: +; HSA: ; %bb.0: +; HSA-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; HSA-NEXT: v_mov_b32_e32 v1, v2 +; HSA-NEXT: s_setpc_b64 s[30:31] + %cast = addrspacecast <2 x ptr> %ptr to <2 x ptr addrspace(6)> + ret <2 x ptr addrspace(6)> %cast +} + +define <3 x ptr addrspace(6)> @addrspacecast_v3p0_to_v3p6(<3 x ptr> %ptr) { +; HSA-LABEL: addrspacecast_v3p0_to_v3p6: +; HSA: ; %bb.0: +; HSA-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; HSA-NEXT: v_mov_b32_e32 v1, v2 +; HSA-NEXT: v_mov_b32_e32 v2, v4 +; HSA-NEXT: s_setpc_b64 s[30:31] + %cast = addrspacecast <3 x ptr> %ptr to <3 x ptr addrspace(6)> + ret <3 x ptr addrspace(6)> %cast +} + +define <4 x ptr addrspace(6)> @addrspacecast_v4p0_to_v4p6(<4 x ptr> %ptr) { +; HSA-LABEL: addrspacecast_v4p0_to_v4p6: +; HSA: ; %bb.0: +; HSA-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; HSA-NEXT: v_mov_b32_e32 v3, v6 +; HSA-NEXT: v_mov_b32_e32 v1, v2 +; HSA-NEXT: v_mov_b32_e32 v2, v4 +; HSA-NEXT: s_setpc_b64 s[30:31] + %cast = addrspacecast <4 x ptr> %ptr to <4 x ptr addrspace(6)> + ret <4 x ptr addrspace(6)> %cast +} + +define <8 x ptr addrspace(6)> @addrspacecast_v8p0_to_v8p6(<8 x ptr> %ptr) { +; HSA-LABEL: addrspacecast_v8p0_to_v8p6: +; HSA: ; %bb.0: +; HSA-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; HSA-NEXT: v_mov_b32_e32 v7, v14 +; HSA-NEXT: v_mov_b32_e32 v5, v10 +; HSA-NEXT: v_mov_b32_e32 v3, v6 +; HSA-NEXT: v_mov_b32_e32 v1, v2 +; HSA-NEXT: v_mov_b32_e32 v2, v4 +; HSA-NEXT: v_mov_b32_e32 v4, v8 +; HSA-NEXT: v_mov_b32_e32 v6, v12 +; HSA-NEXT: s_setpc_b64 s[30:31] + %cast = addrspacecast <8 x ptr> %ptr to <8 x ptr addrspace(6)> + ret <8 x ptr addrspace(6)> %cast +} + +define <16 x ptr addrspace(6)> @addrspacecast_v16p0_to_v16p6(<16 x ptr> %ptr) { +; HSA-LABEL: addrspacecast_v16p0_to_v16p6: +; HSA: ; %bb.0: +; HSA-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; HSA-NEXT: v_mov_b32_e32 v15, v30 +; HSA-NEXT: v_mov_b32_e32 v13, v26 +; HSA-NEXT: v_mov_b32_e32 v11, v22 +; HSA-NEXT: v_mov_b32_e32 v9, v18 +; HSA-NEXT: v_mov_b32_e32 v7, v14 +; HSA-NEXT: v_mov_b32_e32 v5, v10 +; HSA-NEXT: v_mov_b32_e32 v3, v6 +; HSA-NEXT: v_mov_b32_e32 v1, v2 +; HSA-NEXT: v_mov_b32_e32 v2, v4 +; HSA-NEXT: v_mov_b32_e32 v4, v8 +; HSA-NEXT: v_mov_b32_e32 v6, v12 +; HSA-NEXT: v_mov_b32_e32 v8, v16 +; HSA-NEXT: v_mov_b32_e32 v10, v20 +; HSA-NEXT: v_mov_b32_e32 v12, v24 +; HSA-NEXT: v_mov_b32_e32 v14, v28 +; HSA-NEXT: s_setpc_b64 s[30:31] + %cast = addrspacecast <16 x ptr> %ptr to <16 x ptr addrspace(6)> + ret <16 x ptr addrspace(6)> %cast +} + +define <2 x ptr> @addrspacecast_v2p6_to_v2p0(<2 x ptr addrspace(6)> %ptr) { +; HSA-LABEL: addrspacecast_v2p6_to_v2p0: +; HSA: ; %bb.0: +; HSA-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; HSA-NEXT: v_mov_b32_e32 v2, v1 +; HSA-NEXT: v_mov_b32_e32 v1, 0 +; HSA-NEXT: v_mov_b32_e32 v3, 0 +; HSA-NEXT: s_setpc_b64 s[30:31] + %cast = addrspacecast <2 x ptr addrspace(6)> %ptr to <2 x ptr> + ret <2 x ptr> %cast +} + +define <1 x ptr> @addrspacecast_v1p6_to_v1p0(<1 x ptr addrspace(6)> %ptr) { +; HSA-LABEL: addrspacecast_v1p6_to_v1p0: +; HSA: ; %bb.0: +; HSA-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; HSA-NEXT: v_mov_b32_e32 v1, 0 +; HSA-NEXT: s_setpc_b64 s[30:31] + %cast = addrspacecast <1 x ptr addrspace(6)> %ptr to <1 x ptr> + ret <1 x ptr> %cast +} + +define <4 x ptr> @addrspacecast_v4p6_to_v4p0(<4 x ptr addrspace(6)> %ptr) { +; HSA-LABEL: addrspacecast_v4p6_to_v4p0: +; HSA: ; %bb.0: +; HSA-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; HSA-NEXT: v_mov_b32_e32 v6, v3 +; HSA-NEXT: v_mov_b32_e32 v4, v2 +; HSA-NEXT: v_mov_b32_e32 v2, v1 +; HSA-NEXT: v_mov_b32_e32 v1, 0 +; HSA-NEXT: v_mov_b32_e32 v3, 0 +; HSA-NEXT: v_mov_b32_e32 v5, 0 +; HSA-NEXT: v_mov_b32_e32 v7, 0 +; HSA-NEXT: s_setpc_b64 s[30:31] + %cast = addrspacecast <4 x ptr addrspace(6)> %ptr to <4 x ptr> + ret <4 x ptr> %cast +} + +define <8 x ptr> @addrspacecast_v8p6_to_v8p0(<8 x ptr addrspace(6)> %ptr) { +; HSA-LABEL: addrspacecast_v8p6_to_v8p0: +; HSA: ; %bb.0: +; HSA-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; HSA-NEXT: v_mov_b32_e32 v14, v7 +; HSA-NEXT: v_mov_b32_e32 v12, v6 +; HSA-NEXT: v_mov_b32_e32 v10, v5 +; HSA-NEXT: v_mov_b32_e32 v8, v4 +; HSA-NEXT: v_mov_b32_e32 v6, v3 +; HSA-NEXT: v_mov_b32_e32 v4, v2 +; HSA-NEXT: v_mov_b32_e32 v2, v1 +; HSA-NEXT: v_mov_b32_e32 v1, 0 +; HSA-NEXT: v_mov_b32_e32 v3, 0 +; HSA-NEXT: v_mov_b32_e32 v5, 0 +; HSA-NEXT: v_mov_b32_e32 v7, 0 +; HSA-NEXT: v_mov_b32_e32 v9, 0 +; HSA-NEXT: v_mov_b32_e32 v11, 0 +; HSA-NEXT: v_mov_b32_e32 v13, 0 +; HSA-NEXT: v_mov_b32_e32 v15, 0 +; HSA-NEXT: s_setpc_b64 s[30:31] + %cast = addrspacecast <8 x ptr addrspace(6)> %ptr to <8 x ptr> + ret <8 x ptr> %cast +} + +define <16 x ptr> @addrspacecast_v16p6_to_v16p0(<16 x ptr addrspace(6)> %ptr) { +; HSA-LABEL: addrspacecast_v16p6_to_v16p0: +; HSA: ; %bb.0: +; HSA-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; HSA-NEXT: v_mov_b32_e32 v30, v15 +; HSA-NEXT: v_mov_b32_e32 v28, v14 +; HSA-NEXT: v_mov_b32_e32 v26, v13 +; HSA-NEXT: v_mov_b32_e32 v24, v12 +; HSA-NEXT: v_mov_b32_e32 v22, v11 +; HSA-NEXT: v_mov_b32_e32 v20, v10 +; HSA-NEXT: v_mov_b32_e32 v18, v9 +; HSA-NEXT: v_mov_b32_e32 v16, v8 +; HSA-NEXT: v_mov_b32_e32 v14, v7 +; HSA-NEXT: v_mov_b32_e32 v12, v6 +; HSA-NEXT: v_mov_b32_e32 v10, v5 +; HSA-NEXT: v_mov_b32_e32 v8, v4 +; HSA-NEXT: v_mov_b32_e32 v6, v3 +; HSA-NEXT: v_mov_b32_e32 v4, v2 +; HSA-NEXT: v_mov_b32_e32 v2, v1 +; HSA-NEXT: v_mov_b32_e32 v1, 0 +; HSA-NEXT: v_mov_b32_e32 v3, 0 +; HSA-NEXT: v_mov_b32_e32 v5, 0 +; HSA-NEXT: v_mov_b32_e32 v7, 0 +; HSA-NEXT: v_mov_b32_e32 v9, 0 +; HSA-NEXT: v_mov_b32_e32 v11, 0 +; HSA-NEXT: v_mov_b32_e32 v13, 0 +; HSA-NEXT: v_mov_b32_e32 v15, 0 +; HSA-NEXT: v_mov_b32_e32 v17, 0 +; HSA-NEXT: v_mov_b32_e32 v19, 0 +; HSA-NEXT: v_mov_b32_e32 v21, 0 +; HSA-NEXT: v_mov_b32_e32 v23, 0 +; HSA-NEXT: v_mov_b32_e32 v25, 0 +; HSA-NEXT: v_mov_b32_e32 v27, 0 +; HSA-NEXT: v_mov_b32_e32 v29, 0 +; HSA-NEXT: v_mov_b32_e32 v31, 0 +; HSA-NEXT: s_setpc_b64 s[30:31] + %cast = addrspacecast <16 x ptr addrspace(6)> %ptr to <16 x ptr> + ret <16 x ptr> %cast +} + declare void @llvm.amdgcn.s.barrier() #1 declare i32 @llvm.amdgcn.workitem.id.x() #2 diff --git a/llvm/test/CodeGen/AMDGPU/early-tailduplicator-nophis.mir b/llvm/test/CodeGen/AMDGPU/early-tailduplicator-nophis.mir index 2cb84c7ef4637d..072cc3a60a60ca 100644 --- a/llvm/test/CodeGen/AMDGPU/early-tailduplicator-nophis.mir +++ b/llvm/test/CodeGen/AMDGPU/early-tailduplicator-nophis.mir @@ -1,5 +1,6 @@ # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py # RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 -run-pass=early-tailduplication -verify-machineinstrs -o - %s | FileCheck %s +# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 -passes=early-tailduplication -o - %s | FileCheck %s # There are no phis in this testcase. Early tail duplication introduces them, # so the NoPHIs property needs to be cleared to avoid verifier errors diff --git a/llvm/test/CodeGen/AMDGPU/early-tailduplicator-terminator.mir b/llvm/test/CodeGen/AMDGPU/early-tailduplicator-terminator.mir index 41c6906b3c85ad..8132fa4df89eee 100644 --- a/llvm/test/CodeGen/AMDGPU/early-tailduplicator-terminator.mir +++ b/llvm/test/CodeGen/AMDGPU/early-tailduplicator-terminator.mir @@ -1,5 +1,6 @@ # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py # RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 -run-pass=early-tailduplication -verify-machineinstrs -o - %s | FileCheck %s +# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 -passes=early-tailduplication -o - %s | FileCheck %s # Early tail duplication should not merge bb.6 into bb.5, adding a # non-terminator (S_SLEEP) after the terminator S_MOV_B32_term. diff --git a/llvm/test/CodeGen/AMDGPU/fold-omod-crash.mir b/llvm/test/CodeGen/AMDGPU/fold-omod-crash.mir new file mode 100644 index 00000000000000..8065e2cfc00432 --- /dev/null +++ b/llvm/test/CodeGen/AMDGPU/fold-omod-crash.mir @@ -0,0 +1,50 @@ +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 5 +# RUN: llc -mtriple=amdgcn -mcpu=gfx900 -run-pass=si-fold-operands %s -verify-machineinstrs -o - | FileCheck %s -check-prefix=GFX9 + +# When V_ADD_F32 is replaced with an output modifier on V_RSQ_F32, check that +# the kill flag is cleared on the use of %4 in V_MUL_F32. +--- +name: main +tracksRegLiveness: true +machineFunctionInfo: + mode: + ieee: false + fp32-input-denormals: false + fp32-output-denormals: false +body: | + ; GFX9-LABEL: name: main + ; GFX9: bb.0: + ; GFX9-NEXT: successors: %bb.1(0x80000000) + ; GFX9-NEXT: liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5, $vgpr6, $vgpr7, $vgpr8, $vgpr9 + ; GFX9-NEXT: {{ $}} + ; GFX9-NEXT: [[DEF:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF + ; GFX9-NEXT: [[DEF1:%[0-9]+]]:sreg_64 = IMPLICIT_DEF + ; GFX9-NEXT: [[V_RSQ_F32_e64_:%[0-9]+]]:vgpr_32 = nofpexcept V_RSQ_F32_e64 0, undef [[DEF]], 0, 1, implicit $mode, implicit $exec + ; GFX9-NEXT: {{ $}} + ; GFX9-NEXT: bb.1: + ; GFX9-NEXT: successors: %bb.1(0x40000000), %bb.2(0x40000000) + ; GFX9-NEXT: {{ $}} + ; GFX9-NEXT: [[DEF2:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF + ; GFX9-NEXT: [[V_MUL_F32_e64_:%[0-9]+]]:vgpr_32 = V_MUL_F32_e64 0, killed undef [[DEF2]], 0, [[V_RSQ_F32_e64_]], 0, 0, implicit $mode, implicit $exec + ; GFX9-NEXT: SI_LOOP undef [[DEF1]], %bb.1, implicit-def dead $exec, implicit-def dead $scc, implicit $exec + ; GFX9-NEXT: S_BRANCH %bb.2 + ; GFX9-NEXT: {{ $}} + ; GFX9-NEXT: bb.2: + ; GFX9-NEXT: S_ENDPGM 0 + bb.0: + liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5, $vgpr6, $vgpr7, $vgpr8, $vgpr9 + + %0:vgpr_32 = IMPLICIT_DEF + %1:sreg_64 = IMPLICIT_DEF + %2:vgpr_32 = nofpexcept V_RSQ_F32_e64 0, undef %0, 0, 0, implicit $mode, implicit $exec + + bb.1: + %3:vgpr_32 = IMPLICIT_DEF + %4:vgpr_32 = nsz reassoc nofpexcept V_ADD_F32_e64 0, undef %2, 0, undef %2, 0, 0, implicit $mode, implicit $exec + %5:vgpr_32 = V_MUL_F32_e64 0, killed undef %3, 0, killed %4, 0, 0, implicit $mode, implicit $exec + SI_LOOP undef %1, %bb.1, implicit-def dead $exec, implicit-def dead $scc, implicit $exec + S_BRANCH %bb.2 + + bb.2: + S_ENDPGM 0 +... diff --git a/llvm/test/CodeGen/AMDGPU/promote-alloca-invalid-vector-gep.ll b/llvm/test/CodeGen/AMDGPU/promote-alloca-invalid-vector-gep.ll new file mode 100644 index 00000000000000..b0d578e421e280 --- /dev/null +++ b/llvm/test/CodeGen/AMDGPU/promote-alloca-invalid-vector-gep.ll @@ -0,0 +1,44 @@ +; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 5 +; RUN: opt -S -mtriple=amdgcn-amd-amdhsa -passes=amdgpu-promote-alloca < %s | FileCheck %s + +; Check that invalid IR is not produced on a vector typed +; getelementptr with a scalar alloca pointer base. + +define amdgpu_kernel void @scalar_alloca_ptr_with_vector_gep_offset() { +; CHECK-LABEL: define amdgpu_kernel void @scalar_alloca_ptr_with_vector_gep_offset() { +; CHECK-NEXT: [[BB:.*:]] +; CHECK-NEXT: [[ALLOCA:%.*]] = alloca i32, align 4, addrspace(5) +; CHECK-NEXT: [[GETELEMENTPTR:%.*]] = getelementptr inbounds i8, ptr addrspace(5) [[ALLOCA]], <4 x i64> +; CHECK-NEXT: [[EXTRACTELEMENT:%.*]] = extractelement <4 x ptr addrspace(5)> [[GETELEMENTPTR]], i64 0 +; CHECK-NEXT: store i32 0, ptr addrspace(5) [[EXTRACTELEMENT]], align 4 +; CHECK-NEXT: ret void +; +bb: + %alloca = alloca i32, align 4, addrspace(5) + %getelementptr = getelementptr inbounds i8, ptr addrspace(5) %alloca, <4 x i64> + %extractelement = extractelement <4 x ptr addrspace(5)> %getelementptr, i64 0 + store i32 0, ptr addrspace(5) %extractelement + ret void +} + +define amdgpu_kernel void @scalar_alloca_ptr_with_vector_gep_offset_select(i1 %cond) { +; CHECK-LABEL: define amdgpu_kernel void @scalar_alloca_ptr_with_vector_gep_offset_select( +; CHECK-SAME: i1 [[COND:%.*]]) { +; CHECK-NEXT: [[BB:.*:]] +; CHECK-NEXT: [[ALLOCA:%.*]] = alloca i32, align 4, addrspace(5) +; CHECK-NEXT: [[GETELEMENTPTR0:%.*]] = getelementptr inbounds i8, ptr addrspace(5) [[ALLOCA]], <4 x i64> +; CHECK-NEXT: [[GETELEMENTPTR1:%.*]] = getelementptr inbounds i8, ptr addrspace(5) [[ALLOCA]], <4 x i64> +; CHECK-NEXT: [[SELECT:%.*]] = select i1 [[COND]], <4 x ptr addrspace(5)> [[GETELEMENTPTR0]], <4 x ptr addrspace(5)> [[GETELEMENTPTR1]] +; CHECK-NEXT: [[EXTRACTELEMENT:%.*]] = extractelement <4 x ptr addrspace(5)> [[SELECT]], i64 1 +; CHECK-NEXT: store i32 0, ptr addrspace(5) [[EXTRACTELEMENT]], align 4 +; CHECK-NEXT: ret void +; +bb: + %alloca = alloca i32, align 4, addrspace(5) + %getelementptr0 = getelementptr inbounds i8, ptr addrspace(5) %alloca, <4 x i64> + %getelementptr1 = getelementptr inbounds i8, ptr addrspace(5) %alloca, <4 x i64> + %select = select i1 %cond, <4 x ptr addrspace(5)> %getelementptr0, <4 x ptr addrspace(5)> %getelementptr1 + %extractelement = extractelement <4 x ptr addrspace(5)> %select, i64 1 + store i32 0, ptr addrspace(5) %extractelement + ret void +} diff --git a/llvm/test/CodeGen/AMDGPU/stop-tail-duplicate-cfg-intrinsic.mir b/llvm/test/CodeGen/AMDGPU/stop-tail-duplicate-cfg-intrinsic.mir index c23c8900096fba..be1a8aceb8c903 100644 --- a/llvm/test/CodeGen/AMDGPU/stop-tail-duplicate-cfg-intrinsic.mir +++ b/llvm/test/CodeGen/AMDGPU/stop-tail-duplicate-cfg-intrinsic.mir @@ -1,5 +1,6 @@ # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py # RUN: llc -mtriple=amdgcn-amd-amdhsa -run-pass=early-tailduplication -verify-machineinstrs -o - %s | FileCheck %s +# RUN: llc -mtriple=amdgcn-amd-amdhsa -passes=early-tailduplication -o - %s | FileCheck %s --- name: stop_duplicate_cfg_intrinsic diff --git a/llvm/test/CodeGen/DirectX/countbits.ll b/llvm/test/CodeGen/DirectX/countbits.ll index c6bc2b6790948e..f03ab9c5e79c35 100644 --- a/llvm/test/CodeGen/DirectX/countbits.ll +++ b/llvm/test/CodeGen/DirectX/countbits.ll @@ -4,35 +4,67 @@ define noundef i16 @test_countbits_short(i16 noundef %a) { entry: -; CHECK: call i16 @dx.op.unary.i16(i32 31, i16 %{{.*}}) +; CHECK: [[A:%.*]] = call i32 @dx.op.unaryBits.i16(i32 31, i16 %{{.*}}) +; CHECK-NEXT: [[B:%.*]] = trunc i32 [[A]] to i16 +; CHECK-NEXT ret i16 [[B]] %elt.ctpop = call i16 @llvm.ctpop.i16(i16 %a) ret i16 %elt.ctpop } +define noundef i32 @test_countbits_short2(i16 noundef %a) { +entry: +; CHECK: [[A:%.*]] = call i32 @dx.op.unaryBits.i16(i32 31, i16 %{{.*}}) +; CHECK-NEXT: ret i32 [[A]] + %elt.ctpop = call i16 @llvm.ctpop.i16(i16 %a) + %elt.zext = zext i16 %elt.ctpop to i32 + ret i32 %elt.zext +} + +define noundef i32 @test_countbits_short3(i16 noundef %a) { +entry: +; CHECK: [[A:%.*]] = call i32 @dx.op.unaryBits.i16(i32 31, i16 %{{.*}}) +; CHECK-NEXT: ret i32 [[A]] + %elt.ctpop = call i16 @llvm.ctpop.i16(i16 %a) + %elt.sext = sext i16 %elt.ctpop to i32 + ret i32 %elt.sext +} + define noundef i32 @test_countbits_int(i32 noundef %a) { entry: -; CHECK: call i32 @dx.op.unary.i32(i32 31, i32 %{{.*}}) +; CHECK: [[A:%.*]] = call i32 @dx.op.unaryBits.i32(i32 31, i32 %{{.*}}) +; CHECK-NEXT: ret i32 [[A]] %elt.ctpop = call i32 @llvm.ctpop.i32(i32 %a) ret i32 %elt.ctpop } define noundef i64 @test_countbits_long(i64 noundef %a) { entry: -; CHECK: call i64 @dx.op.unary.i64(i32 31, i64 %{{.*}}) +; CHECK: [[A:%.*]] = call i32 @dx.op.unaryBits.i64(i32 31, i64 %{{.*}}) +; CHECK-NEXT: [[B:%.*]] = zext i32 [[A]] to i64 +; CHECK-NEXT ret i64 [[B]] %elt.ctpop = call i64 @llvm.ctpop.i64(i64 %a) ret i64 %elt.ctpop } +define noundef i32 @test_countbits_long2(i64 noundef %a) { +entry: +; CHECK: [[A:%.*]] = call i32 @dx.op.unaryBits.i64(i32 31, i64 %{{.*}}) +; CHECK-NEXT: ret i32 [[A]] + %elt.ctpop = call i64 @llvm.ctpop.i64(i64 %a) + %elt.trunc = trunc i64 %elt.ctpop to i32 + ret i32 %elt.trunc +} + define noundef <4 x i32> @countbits_vec4_i32(<4 x i32> noundef %a) { entry: ; CHECK: [[ee0:%.*]] = extractelement <4 x i32> %a, i64 0 - ; CHECK: [[ie0:%.*]] = call i32 @dx.op.unary.i32(i32 31, i32 [[ee0]]) + ; CHECK: [[ie0:%.*]] = call i32 @dx.op.unaryBits.i32(i32 31, i32 [[ee0]]) ; CHECK: [[ee1:%.*]] = extractelement <4 x i32> %a, i64 1 - ; CHECK: [[ie1:%.*]] = call i32 @dx.op.unary.i32(i32 31, i32 [[ee1]]) + ; CHECK: [[ie1:%.*]] = call i32 @dx.op.unaryBits.i32(i32 31, i32 [[ee1]]) ; CHECK: [[ee2:%.*]] = extractelement <4 x i32> %a, i64 2 - ; CHECK: [[ie2:%.*]] = call i32 @dx.op.unary.i32(i32 31, i32 [[ee2]]) + ; CHECK: [[ie2:%.*]] = call i32 @dx.op.unaryBits.i32(i32 31, i32 [[ee2]]) ; CHECK: [[ee3:%.*]] = extractelement <4 x i32> %a, i64 3 - ; CHECK: [[ie3:%.*]] = call i32 @dx.op.unary.i32(i32 31, i32 [[ee3]]) + ; CHECK: [[ie3:%.*]] = call i32 @dx.op.unaryBits.i32(i32 31, i32 [[ee3]]) ; CHECK: insertelement <4 x i32> poison, i32 [[ie0]], i64 0 ; CHECK: insertelement <4 x i32> %{{.*}}, i32 [[ie1]], i64 1 ; CHECK: insertelement <4 x i32> %{{.*}}, i32 [[ie2]], i64 2 diff --git a/llvm/test/CodeGen/DirectX/group_memory_barrier_with_group_sync.ll b/llvm/test/CodeGen/DirectX/group_memory_barrier_with_group_sync.ll new file mode 100644 index 00000000000000..baf93d4e177f0f --- /dev/null +++ b/llvm/test/CodeGen/DirectX/group_memory_barrier_with_group_sync.ll @@ -0,0 +1,8 @@ +; RUN: opt -S -dxil-op-lower -mtriple=dxil-pc-shadermodel6.3-library < %s | FileCheck %s + +define void @test_group_memory_barrier_with_group_sync() { +entry: + ; CHECK: call void @dx.op.barrier(i32 80, i32 9) + call void @llvm.dx.group.memory.barrier.with.group.sync() + ret void +} \ No newline at end of file diff --git a/llvm/test/CodeGen/Generic/MIRStripDebug/bundles.mir b/llvm/test/CodeGen/Generic/MIRStripDebug/bundles.mir new file mode 100644 index 00000000000000..111c886f585cf6 --- /dev/null +++ b/llvm/test/CodeGen/Generic/MIRStripDebug/bundles.mir @@ -0,0 +1,63 @@ +# RUN: llc -run-pass=mir-strip-debug -o - %s | FileCheck %s +# RUN: llc -run-pass=mir-strip-debug,mir-debugify,mir-strip-debug -o - %s | FileCheck %s + +--- | + source_filename = "loc-only.ll" + + define i32 @test(i32 %a, i32 %b) !dbg !6 { + %add = add i32 %a, 2, !dbg !12 + call void @llvm.dbg.value(metadata i32 %add, metadata !9, metadata !DIExpression()), !dbg !12 + %sub = sub i32 %add, %b, !dbg !13 + call void @llvm.dbg.value(metadata i32 %sub, metadata !11, metadata !DIExpression()), !dbg !13 + ret i32 %sub, !dbg !14 + } + + declare void @llvm.dbg.value(metadata, metadata, metadata) + + !llvm.dbg.cu = !{!0} + ; CHECK-NOT: !llvm.dbg.cu + !llvm.debugify = !{!3, !4} + ; CHECK-NOT: !llvm.debugify + !llvm.module.flags = !{!5} + ; CHECK-NOT: !llvm.module.flags + + ; CHECK-NOT: !DI + !0 = distinct !DICompileUnit(language: DW_LANG_C, file: !1, producer: "debugify", isOptimized: true, runtimeVersion: 0, emissionKind: FullDebug, enums: !2) + !1 = !DIFile(filename: "", directory: "/") + !2 = !{} + !3 = !{i32 3} + !4 = !{i32 2} + !5 = !{i32 2, !"Debug Info Version", i32 3} + !6 = distinct !DISubprogram(name: "test", linkageName: "test", scope: null, file: !1, line: 1, type: !7, scopeLine: 1, spFlags: DISPFlagDefinition | DISPFlagOptimized, unit: !0, retainedNodes: !8) + !7 = !DISubroutineType(types: !2) + !8 = !{!9, !11} + !9 = !DILocalVariable(name: "1", scope: !6, file: !1, line: 1, type: !10) + !10 = !DIBasicType(name: "ty32", size: 32, encoding: DW_ATE_unsigned) + !11 = !DILocalVariable(name: "2", scope: !6, file: !1, line: 2, type: !10) + !12 = !DILocation(line: 1, column: 1, scope: !6) + !13 = !DILocation(line: 2, column: 1, scope: !6) + !14 = !DILocation(line: 3, column: 1, scope: !6) + +... +--- +name: test +body: | + bb.1 (%ir-block.0): + %0:_(s32) = G_IMPLICIT_DEF + %1:_(s32) = G_IMPLICIT_DEF + BUNDLE { + %2:_(s32) = G_CONSTANT i32 2, debug-location !DILocation(line: 0, scope: !6) + %3:_(s32) = G_ADD %0, %1, debug-location !12 + } + + ; CHECK-LABEL: body: + ; CHECK-NOT: debug-location + ; CHECK-NOT: !DI + ; CHECK-NEXT: bb + ; CHECK-NEXT: %0:_(s32) = G_IMPLICIT_DEF{{$}} + ; CHECK-NEXT: %1:_(s32) = G_IMPLICIT_DEF{{$}} + ; CHECK-NEXT: BUNDLE { + ; CHECK-NEXT: %2:_(s32) = G_CONSTANT i32 2{{$}} + ; CHECK-NEXT: %3:_(s32) = G_ADD %0, %1{{$}} + ; CHECK-NEXT: } +... diff --git a/llvm/test/CodeGen/MIR/icmp-flags.mir b/llvm/test/CodeGen/MIR/icmp-flags.mir new file mode 100644 index 00000000000000..3c03a7aaa9bcdc --- /dev/null +++ b/llvm/test/CodeGen/MIR/icmp-flags.mir @@ -0,0 +1,50 @@ +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py +# RUN: llc -mtriple aarch64 -run-pass=none -verify-machineinstrs %s -o - | FileCheck %s + + +--- +name: icmp_samesign +body: | + bb.0: + liveins: $w0, $w1 + + ; CHECK-LABEL: name: icmp_samesign + ; CHECK: liveins: $w0, $w1 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: %x:_(s32) = COPY $w0 + ; CHECK-NEXT: %y:_(s32) = COPY $w1 + ; CHECK-NEXT: %cmp:_(s1) = samesign G_ICMP intpred(eq), %y(s32), %y + ; CHECK-NEXT: %zext:_(s32) = G_ZEXT %cmp(s1) + ; CHECK-NEXT: $w0 = COPY %zext(s32) + ; CHECK-NEXT: RET_ReallyLR implicit $w0 + %x:_(s32) = COPY $w0 + %y:_(s32) = COPY $w1 + %cmp:_(s1) = samesign G_ICMP intpred(eq), %y:_(s32), %y:_ + %zext:_(s32) = G_ZEXT %cmp:_(s1) + $w0 = COPY %zext + RET_ReallyLR implicit $w0 + + +... +--- +name: icmp_differentsign +body: | + bb.0: + liveins: $w0, $w1 + + ; CHECK-LABEL: name: icmp_differentsign + ; CHECK: liveins: $w0, $w1 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: %x:_(s32) = COPY $w0 + ; CHECK-NEXT: %y:_(s32) = COPY $w1 + ; CHECK-NEXT: %cmp:_(s1) = G_ICMP intpred(eq), %y(s32), %y + ; CHECK-NEXT: %zext:_(s32) = G_ZEXT %cmp(s1) + ; CHECK-NEXT: $w0 = COPY %zext(s32) + ; CHECK-NEXT: RET_ReallyLR implicit $w0 + %x:_(s32) = COPY $w0 + %y:_(s32) = COPY $w1 + %cmp:_(s1) = G_ICMP intpred(eq), %y:_(s32), %y:_ + %zext:_(s32) = G_ZEXT %cmp:_(s1) + $w0 = COPY %zext + RET_ReallyLR implicit $w0 +--- diff --git a/llvm/test/CodeGen/PowerPC/saddo-ssubo.ll b/llvm/test/CodeGen/PowerPC/saddo-ssubo.ll index fd5f26ba35742f..7147257d27c4b8 100644 --- a/llvm/test/CodeGen/PowerPC/saddo-ssubo.ll +++ b/llvm/test/CodeGen/PowerPC/saddo-ssubo.ll @@ -129,12 +129,11 @@ entry: define i1 @test_ssubo_i32(i32 %a, i32 %b) nounwind { ; CHECK-LABEL: test_ssubo_i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: sub 5, 3, 4 -; CHECK-NEXT: cmpwi 1, 4, 0 -; CHECK-NEXT: cmpw 5, 3 -; CHECK-NEXT: li 3, 1 -; CHECK-NEXT: creqv 20, 5, 0 -; CHECK-NEXT: isel 3, 0, 3, 20 +; CHECK-NEXT: sub 3, 3, 4 +; CHECK-NEXT: extsw 4, 3 +; CHECK-NEXT: xor 3, 4, 3 +; CHECK-NEXT: addic 4, 3, -1 +; CHECK-NEXT: subfe 3, 4, 3 ; CHECK-NEXT: blr entry: %res = call { i32, i1 } @llvm.ssub.with.overflow.i32(i32 %a, i32 %b) nounwind diff --git a/llvm/test/CodeGen/RISCV/rvv/allocate-lmul-2-4-8.ll b/llvm/test/CodeGen/RISCV/rvv/allocate-lmul-2-4-8.ll index 35e269b9119025..43be8feece23c1 100644 --- a/llvm/test/CodeGen/RISCV/rvv/allocate-lmul-2-4-8.ll +++ b/llvm/test/CodeGen/RISCV/rvv/allocate-lmul-2-4-8.ll @@ -756,3 +756,104 @@ define void @lmul_8_x9() nounwind { %v9 = alloca ret void } + +define void @lmul_16_align() nounwind { +; NOZBA-LABEL: lmul_16_align: +; NOZBA: # %bb.0: +; NOZBA-NEXT: addi sp, sp, -144 +; NOZBA-NEXT: sd ra, 136(sp) # 8-byte Folded Spill +; NOZBA-NEXT: sd s0, 128(sp) # 8-byte Folded Spill +; NOZBA-NEXT: addi s0, sp, 144 +; NOZBA-NEXT: csrr a0, vlenb +; NOZBA-NEXT: li a1, 24 +; NOZBA-NEXT: mul a0, a0, a1 +; NOZBA-NEXT: sub sp, sp, a0 +; NOZBA-NEXT: andi sp, sp, -128 +; NOZBA-NEXT: vsetvli a0, zero, e64, m8, ta, ma +; NOZBA-NEXT: vmv.v.i v8, 0 +; NOZBA-NEXT: csrr a0, vlenb +; NOZBA-NEXT: add a0, sp, a0 +; NOZBA-NEXT: addi a0, a0, 128 +; NOZBA-NEXT: vs8r.v v8, (a0) +; NOZBA-NEXT: csrr a1, vlenb +; NOZBA-NEXT: slli a1, a1, 3 +; NOZBA-NEXT: add a0, a0, a1 +; NOZBA-NEXT: vs8r.v v8, (a0) +; NOZBA-NEXT: vsetvli a0, zero, e64, m1, ta, ma +; NOZBA-NEXT: vmv.v.i v8, 0 +; NOZBA-NEXT: addi a0, sp, 128 +; NOZBA-NEXT: vs1r.v v8, (a0) +; NOZBA-NEXT: addi sp, s0, -144 +; NOZBA-NEXT: ld ra, 136(sp) # 8-byte Folded Reload +; NOZBA-NEXT: ld s0, 128(sp) # 8-byte Folded Reload +; NOZBA-NEXT: addi sp, sp, 144 +; NOZBA-NEXT: ret +; +; ZBA-LABEL: lmul_16_align: +; ZBA: # %bb.0: +; ZBA-NEXT: addi sp, sp, -144 +; ZBA-NEXT: sd ra, 136(sp) # 8-byte Folded Spill +; ZBA-NEXT: sd s0, 128(sp) # 8-byte Folded Spill +; ZBA-NEXT: addi s0, sp, 144 +; ZBA-NEXT: csrr a0, vlenb +; ZBA-NEXT: slli a0, a0, 3 +; ZBA-NEXT: sh1add a0, a0, a0 +; ZBA-NEXT: sub sp, sp, a0 +; ZBA-NEXT: andi sp, sp, -128 +; ZBA-NEXT: vsetvli a0, zero, e64, m8, ta, ma +; ZBA-NEXT: vmv.v.i v8, 0 +; ZBA-NEXT: csrr a0, vlenb +; ZBA-NEXT: add a0, sp, a0 +; ZBA-NEXT: addi a0, a0, 128 +; ZBA-NEXT: vs8r.v v8, (a0) +; ZBA-NEXT: csrr a1, vlenb +; ZBA-NEXT: sh3add a0, a1, a0 +; ZBA-NEXT: vs8r.v v8, (a0) +; ZBA-NEXT: vsetvli a0, zero, e64, m1, ta, ma +; ZBA-NEXT: vmv.v.i v8, 0 +; ZBA-NEXT: addi a0, sp, 128 +; ZBA-NEXT: vs1r.v v8, (a0) +; ZBA-NEXT: addi sp, s0, -144 +; ZBA-NEXT: ld ra, 136(sp) # 8-byte Folded Reload +; ZBA-NEXT: ld s0, 128(sp) # 8-byte Folded Reload +; ZBA-NEXT: addi sp, sp, 144 +; ZBA-NEXT: ret +; +; NOMUL-LABEL: lmul_16_align: +; NOMUL: # %bb.0: +; NOMUL-NEXT: addi sp, sp, -144 +; NOMUL-NEXT: sd ra, 136(sp) # 8-byte Folded Spill +; NOMUL-NEXT: sd s0, 128(sp) # 8-byte Folded Spill +; NOMUL-NEXT: addi s0, sp, 144 +; NOMUL-NEXT: csrr a0, vlenb +; NOMUL-NEXT: slli a0, a0, 3 +; NOMUL-NEXT: mv a1, a0 +; NOMUL-NEXT: slli a0, a0, 1 +; NOMUL-NEXT: add a0, a0, a1 +; NOMUL-NEXT: sub sp, sp, a0 +; NOMUL-NEXT: andi sp, sp, -128 +; NOMUL-NEXT: vsetvli a0, zero, e64, m8, ta, ma +; NOMUL-NEXT: vmv.v.i v8, 0 +; NOMUL-NEXT: csrr a0, vlenb +; NOMUL-NEXT: add a0, sp, a0 +; NOMUL-NEXT: addi a0, a0, 128 +; NOMUL-NEXT: vs8r.v v8, (a0) +; NOMUL-NEXT: csrr a1, vlenb +; NOMUL-NEXT: slli a1, a1, 3 +; NOMUL-NEXT: add a0, a0, a1 +; NOMUL-NEXT: vs8r.v v8, (a0) +; NOMUL-NEXT: vsetvli a0, zero, e64, m1, ta, ma +; NOMUL-NEXT: vmv.v.i v8, 0 +; NOMUL-NEXT: addi a0, sp, 128 +; NOMUL-NEXT: vs1r.v v8, (a0) +; NOMUL-NEXT: addi sp, s0, -144 +; NOMUL-NEXT: ld ra, 136(sp) # 8-byte Folded Reload +; NOMUL-NEXT: ld s0, 128(sp) # 8-byte Folded Reload +; NOMUL-NEXT: addi sp, sp, 144 +; NOMUL-NEXT: ret + %v1 = alloca + %v2 = alloca + store zeroinitializer, ptr %v1 + store zeroinitializer, ptr %v2 + ret void +} diff --git a/llvm/test/CodeGen/SPIRV/HlslBufferLoad.ll b/llvm/test/CodeGen/SPIRV/HlslBufferLoad.ll index fe960f0d6f2f9a..66d5f0f4b05fe6 100644 --- a/llvm/test/CodeGen/SPIRV/HlslBufferLoad.ll +++ b/llvm/test/CodeGen/SPIRV/HlslBufferLoad.ll @@ -1,4 +1,5 @@ -; RUN: llc -verify-machineinstrs -O0 -mtriple=spirv-vulkan-library %s -o - | FileCheck %s +; TODO(pull/110270): verifier, fix G_BITCAST error "bitcast must change type" +; RUN: llc -O0 -mtriple=spirv-vulkan-library %s -o - | FileCheck %s ; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv-vulkan-library %s -o - -filetype=obj | spirv-val %} ; CHECK-DAG: OpDecorate [[IntBufferVar:%[0-9]+]] DescriptorSet 16 @@ -18,13 +19,13 @@ ; CHECK: {{%[0-9]+}} = OpFunction {{%[0-9]+}} DontInline {{%[0-9]+}} ; CHECK-NEXT: OpLabel define void @RWBufferLoad() #0 { -; CHECK-NEXT: [[buffer:%[0-9]+]] = OpLoad [[RWBufferTypeInt]] [[IntBufferVar]] +; CHECK: [[buffer:%[0-9]+]] = OpLoad [[RWBufferTypeInt]] [[IntBufferVar]] %buffer0 = call target("spirv.Image", i32, 5, 2, 0, 0, 2, 24) @llvm.spv.handle.fromBinding.tspirv.Image_f32_5_2_0_0_2_24( i32 16, i32 7, i32 1, i32 0, i1 false) ; Make sure we use the same variable with multiple loads. -; CHECK-NEXT: [[buffer:%[0-9]+]] = OpLoad [[RWBufferTypeInt]] [[IntBufferVar]] +; CHECK: [[buffer:%[0-9]+]] = OpLoad [[RWBufferTypeInt]] [[IntBufferVar]] %buffer1 = call target("spirv.Image", i32, 5, 2, 0, 0, 2, 24) @llvm.spv.handle.fromBinding.tspirv.Image_f32_5_2_0_0_2_24( i32 16, i32 7, i32 1, i32 0, i1 false) @@ -36,7 +37,7 @@ define void @RWBufferLoad() #0 { define void @UseDifferentGlobalVar() #0 { ; Make sure we use a different variable from the first function. They have ; different types. -; CHECK-NEXT: [[buffer:%[0-9]+]] = OpLoad [[RWBufferTypeFloat]] [[FloatBufferVar]] +; CHECK: [[buffer:%[0-9]+]] = OpLoad [[RWBufferTypeFloat]] [[FloatBufferVar]] %buffer0 = call target("spirv.Image", float, 5, 2, 0, 0, 2, 3) @llvm.spv.handle.fromBinding.tspirv.Image_f32_5_2_0_0_2_3( i32 16, i32 7, i32 1, i32 0, i1 false) @@ -48,7 +49,7 @@ define void @UseDifferentGlobalVar() #0 { define void @ReuseGlobalVarFromFirstFunction() #0 { ; Make sure we use the same variable as the first function. They should be the ; same in case one function calls the other. -; CHECK-NEXT: [[buffer:%[0-9]+]] = OpLoad [[RWBufferTypeInt]] [[IntBufferVar]] +; CHECK: [[buffer:%[0-9]+]] = OpLoad [[RWBufferTypeInt]] [[IntBufferVar]] %buffer1 = call target("spirv.Image", i32, 5, 2, 0, 0, 2, 24) @llvm.spv.handle.fromBinding.tspirv.Image_f32_5_2_0_0_2_24( i32 16, i32 7, i32 1, i32 0, i1 false) diff --git a/llvm/test/CodeGen/SPIRV/OpVariable_order.ll b/llvm/test/CodeGen/SPIRV/OpVariable_order.ll index 6057bf38d4c4c4..c68250697c4a7b 100644 --- a/llvm/test/CodeGen/SPIRV/OpVariable_order.ll +++ b/llvm/test/CodeGen/SPIRV/OpVariable_order.ll @@ -1,7 +1,7 @@ ; All OpVariable instructions in a function must be the first instructions in the first block -; RUN: llc -O0 -mtriple=spirv-unknown-linux %s -o - | FileCheck %s --check-prefix=CHECK-SPIRV -; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv-unknown-linux %s -o - -filetype=obj | spirv-val %} +; RUN: llc -O0 -mtriple=spirv32-unknown-linux %s -o - | FileCheck %s --check-prefix=CHECK-SPIRV +; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv32-unknown-linux %s -o - -filetype=obj | spirv-val %} ; CHECK-SPIRV: OpFunction ; CHECK-SPIRV-NEXT: OpLabel diff --git a/llvm/test/CodeGen/SPIRV/ShaderBufferImage.ll b/llvm/test/CodeGen/SPIRV/ShaderBufferImage.ll index 3c002e1849b8dd..1f203043e6a164 100644 --- a/llvm/test/CodeGen/SPIRV/ShaderBufferImage.ll +++ b/llvm/test/CodeGen/SPIRV/ShaderBufferImage.ll @@ -1,4 +1,5 @@ -; RUN: llc -verify-machineinstrs -O0 -mtriple=spirv-vulkan-library %s -o - | FileCheck %s +; TODO(pull/110270): verifier, fix G_BITCAST error "bitcast must change type" +; RUN: llc -O0 -mtriple=spirv-vulkan-library %s -o - | FileCheck %s ; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv-vulkan-library %s -o - -filetype=obj | spirv-val %} ; CHECK-NOT: OpCapability ImageBasic diff --git a/llvm/test/CodeGen/SPIRV/ShaderImage.ll b/llvm/test/CodeGen/SPIRV/ShaderImage.ll index 6ac58ce42f950f..9cd5fb33808056 100644 --- a/llvm/test/CodeGen/SPIRV/ShaderImage.ll +++ b/llvm/test/CodeGen/SPIRV/ShaderImage.ll @@ -1,4 +1,5 @@ -; RUN: llc -verify-machineinstrs -O0 -mtriple=spirv-vulkan-library %s -o - | FileCheck %s +; TODO(pull/110270): verifier, fix G_BITCAST error "bitcast must change type" +; RUN: llc -O0 -mtriple=spirv-vulkan-library %s -o - | FileCheck %s ; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv-vulkan-library %s -o - -filetype=obj | spirv-val %} ; CHECK-DAG: [[Float:%[0-9]+]] = OpTypeFloat 32 diff --git a/llvm/test/CodeGen/SPIRV/basic_float_types.ll b/llvm/test/CodeGen/SPIRV/basic_float_types.ll index 1c7a8a851f59c6..dfee1ace2205dd 100644 --- a/llvm/test/CodeGen/SPIRV/basic_float_types.ll +++ b/llvm/test/CodeGen/SPIRV/basic_float_types.ll @@ -1,4 +1,3 @@ -; RUN: llc -O0 -mtriple=spirv-unknown-unknown %s -o - | FileCheck %s ; RUN: llc -O0 -mtriple=spirv32-unknown-unknown %s -o - | FileCheck %s ; RUN: llc -O0 -mtriple=spirv64-unknown-unknown %s -o - | FileCheck %s ; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv-unknown-unknown %s -o - -filetype=obj | spirv-val %} diff --git a/llvm/test/CodeGen/SPIRV/basic_int_types.ll b/llvm/test/CodeGen/SPIRV/basic_int_types.ll index bb664568ed842f..e85e0919d17934 100644 --- a/llvm/test/CodeGen/SPIRV/basic_int_types.ll +++ b/llvm/test/CodeGen/SPIRV/basic_int_types.ll @@ -1,6 +1,4 @@ -; RUN: llc -verify-machineinstrs -O0 -mtriple=spirv-unknown-unknown %s -o - | FileCheck %s -; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv-unknown-unknown %s -o - -filetype=obj | spirv-val %} - +; TODO(pull/110270): verifier, fix G_BITCAST error "bitcast must change type" ; RUN: llc -verify-machineinstrs -O0 -mtriple=spirv32-unknown-unknown %s -o - | FileCheck %s ; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv32-unknown-unknown %s -o - -filetype=obj | spirv-val %} diff --git a/llvm/test/CodeGen/SPIRV/basic_int_types_spirvdis.ll b/llvm/test/CodeGen/SPIRV/basic_int_types_spirvdis.ll index 3778d897929188..0d7b2b99f64eac 100644 --- a/llvm/test/CodeGen/SPIRV/basic_int_types_spirvdis.ll +++ b/llvm/test/CodeGen/SPIRV/basic_int_types_spirvdis.ll @@ -1,5 +1,5 @@ +; TODO(pull/110270): verifier, fix G_BITCAST error "bitcast must change type" ; REQUIRES: spirv-tools -; RUN: llc -O0 -mtriple=spirv-unknown-unknown %s -o - --filetype=obj | spirv-dis | FileCheck %s ; RUN: llc -O0 -mtriple=spirv32-unknown-unknown %s -o - --filetype=obj | spirv-dis | FileCheck %s ; RUN: llc -O0 -mtriple=spirv64-unknown-unknown %s -o - --filetype=obj | spirv-dis | FileCheck %s diff --git a/llvm/test/CodeGen/SPIRV/hlsl-intrinsics/SV_DispatchThreadID.ll b/llvm/test/CodeGen/SPIRV/hlsl-intrinsics/SV_DispatchThreadID.ll index c84b1c4b06c199..2d8692adf12a2a 100644 --- a/llvm/test/CodeGen/SPIRV/hlsl-intrinsics/SV_DispatchThreadID.ll +++ b/llvm/test/CodeGen/SPIRV/hlsl-intrinsics/SV_DispatchThreadID.ll @@ -1,4 +1,5 @@ -; RUN: llc -verify-machineinstrs -O0 -mtriple=spirv-vulkan-unknown %s -o - | FileCheck %s +; TODO(pull/110270): verifier, fix G_BITCAST error "bitcast must change type" +; RUN: llc -O0 -mtriple=spirv-vulkan-unknown %s -o - | FileCheck %s ; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv-vulkan-unknown %s -o - -filetype=obj | spirv-val %} ; This file generated from the following command: diff --git a/llvm/test/CodeGen/SPIRV/hlsl-intrinsics/WaveGetLaneIndex.ll b/llvm/test/CodeGen/SPIRV/hlsl-intrinsics/WaveGetLaneIndex.ll index 89a8575fa15991..d0a56854c32f8a 100644 --- a/llvm/test/CodeGen/SPIRV/hlsl-intrinsics/WaveGetLaneIndex.ll +++ b/llvm/test/CodeGen/SPIRV/hlsl-intrinsics/WaveGetLaneIndex.ll @@ -1,4 +1,5 @@ -; RUN: llc -verify-machineinstrs -O0 -mtriple=spirv-vulkan-unknown %s -o - | FileCheck %s +; TODO(pull/110270): verifier, fix G_BITCAST error "bitcast must change type" +; RUN: llc -O0 -mtriple=spirv-vulkan-unknown %s -o - | FileCheck %s ; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv-vulkan-unknown %s -o - -filetype=obj | spirv-val %} ; This file generated from the following command: diff --git a/llvm/test/CodeGen/SPIRV/hlsl-intrinsics/abs.ll b/llvm/test/CodeGen/SPIRV/hlsl-intrinsics/abs.ll index 8f1092c2206ed8..c3e894afd710b6 100644 --- a/llvm/test/CodeGen/SPIRV/hlsl-intrinsics/abs.ll +++ b/llvm/test/CodeGen/SPIRV/hlsl-intrinsics/abs.ll @@ -1,4 +1,5 @@ -; RUN: llc -verify-machineinstrs -O0 -mtriple=spirv-unknown-unknown %s -o - | FileCheck %s +; TODO(pull/110270): verifier, fix G_BITCAST error "bitcast must change type" +; RUN: llc -O0 -mtriple=spirv-unknown-unknown %s -o - | FileCheck %s ; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv-unknown-unknown %s -o - -filetype=obj | spirv-val %} ; CHECK: OpExtInstImport "GLSL.std.450" diff --git a/llvm/test/CodeGen/SPIRV/hlsl-intrinsics/acos.ll b/llvm/test/CodeGen/SPIRV/hlsl-intrinsics/acos.ll index 7c9450267cbe89..1936f6d2720737 100644 --- a/llvm/test/CodeGen/SPIRV/hlsl-intrinsics/acos.ll +++ b/llvm/test/CodeGen/SPIRV/hlsl-intrinsics/acos.ll @@ -1,4 +1,5 @@ -; RUN: llc -verify-machineinstrs -O0 -mtriple=spirv-unknown-unknown %s -o - | FileCheck %s +; TODO(pull/110270): verifier, fix G_BITCAST error "bitcast must change type" +; RUN: llc -O0 -mtriple=spirv-unknown-unknown %s -o - | FileCheck %s ; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv-unknown-unknown %s -o - -filetype=obj | spirv-val %} ; CHECK-DAG: %[[#op_ext_glsl:]] = OpExtInstImport "GLSL.std.450" diff --git a/llvm/test/CodeGen/SPIRV/hlsl-intrinsics/all.ll b/llvm/test/CodeGen/SPIRV/hlsl-intrinsics/all.ll index 7c40eed8465a1d..1edd69e2b0d5b0 100644 --- a/llvm/test/CodeGen/SPIRV/hlsl-intrinsics/all.ll +++ b/llvm/test/CodeGen/SPIRV/hlsl-intrinsics/all.ll @@ -1,5 +1,6 @@ -; RUN: llc -verify-machineinstrs -O0 -mtriple=spirv-unknown-unknown %s -o - | FileCheck %s --check-prefixes=CHECK,CHECK-HLSL -; RUN: llc -verify-machineinstrs -O0 -mtriple=spirv32-unknown-unknown %s -o - | FileCheck %s --check-prefixes=CHECK,CHECK-OCL +; TODO(pull/110270): verifier, fix G_BITCAST error "bitcast must change type" +; RUN: llc -O0 -mtriple=spirv-unknown-unknown %s -o - | FileCheck %s --check-prefixes=CHECK,CHECK-HLSL +; RUN: llc -O0 -mtriple=spirv32-unknown-unknown %s -o - | FileCheck %s --check-prefixes=CHECK,CHECK-OCL ; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv-unknown-unknown %s -o - -filetype=obj | spirv-val %} ; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv32-unknown-unknown %s -o - -filetype=obj | spirv-val %} ; Make sure spirv operation function calls for all are generated. diff --git a/llvm/test/CodeGen/SPIRV/hlsl-intrinsics/any.ll b/llvm/test/CodeGen/SPIRV/hlsl-intrinsics/any.ll index 54f5b7774b579e..dc6e9dc2033055 100644 --- a/llvm/test/CodeGen/SPIRV/hlsl-intrinsics/any.ll +++ b/llvm/test/CodeGen/SPIRV/hlsl-intrinsics/any.ll @@ -1,5 +1,6 @@ -; RUN: llc -verify-machineinstrs -O0 -mtriple=spirv-unknown-unknown %s -o - | FileCheck %s --check-prefixes=CHECK,CHECK-HLSL -; RUN: llc -verify-machineinstrs -O0 -mtriple=spirv32-unknown-unknown %s -o - | FileCheck %s --check-prefixes=CHECK,CHECK-OCL +; TODO(pull/110270): verifier, fix G_BITCAST error "bitcast must change type" +; RUN: llc -O0 -mtriple=spirv-unknown-unknown %s -o - | FileCheck %s --check-prefixes=CHECK,CHECK-HLSL +; RUN: llc -O0 -mtriple=spirv32-unknown-unknown %s -o - | FileCheck %s --check-prefixes=CHECK,CHECK-OCL ; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv-unknown-unknown %s -o - -filetype=obj | spirv-val %} ; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv32-unknown-unknown %s -o - -filetype=obj | spirv-val %} ; Make sure spirv operation function calls for any are generated. diff --git a/llvm/test/CodeGen/SPIRV/hlsl-intrinsics/asin.ll b/llvm/test/CodeGen/SPIRV/hlsl-intrinsics/asin.ll index 4d57c6fce77f70..be338f22bf1255 100644 --- a/llvm/test/CodeGen/SPIRV/hlsl-intrinsics/asin.ll +++ b/llvm/test/CodeGen/SPIRV/hlsl-intrinsics/asin.ll @@ -1,4 +1,5 @@ -; RUN: llc -verify-machineinstrs -O0 -mtriple=spirv-unknown-unknown %s -o - | FileCheck %s +; TODO(pull/110270): verifier, fix G_BITCAST error "bitcast must change type" +; RUN: llc -O0 -mtriple=spirv-unknown-unknown %s -o - | FileCheck %s ; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv-unknown-unknown %s -o - -filetype=obj | spirv-val %} ; CHECK-DAG: %[[#op_ext_glsl:]] = OpExtInstImport "GLSL.std.450" diff --git a/llvm/test/CodeGen/SPIRV/hlsl-intrinsics/atan.ll b/llvm/test/CodeGen/SPIRV/hlsl-intrinsics/atan.ll index 65e198d0e71a35..5d352eb80af2d3 100644 --- a/llvm/test/CodeGen/SPIRV/hlsl-intrinsics/atan.ll +++ b/llvm/test/CodeGen/SPIRV/hlsl-intrinsics/atan.ll @@ -1,4 +1,5 @@ -; RUN: llc -verify-machineinstrs -O0 -mtriple=spirv-unknown-unknown %s -o - | FileCheck %s +; TODO(pull/110270): verifier, fix G_BITCAST error "bitcast must change type" +; RUN: llc -O0 -mtriple=spirv-unknown-unknown %s -o - | FileCheck %s ; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv-unknown-unknown %s -o - -filetype=obj | spirv-val %} ; CHECK-DAG: %[[#op_ext_glsl:]] = OpExtInstImport "GLSL.std.450" diff --git a/llvm/test/CodeGen/SPIRV/hlsl-intrinsics/atan2.ll b/llvm/test/CodeGen/SPIRV/hlsl-intrinsics/atan2.ll index bdbfc133efa29b..aba6f7583b6833 100644 --- a/llvm/test/CodeGen/SPIRV/hlsl-intrinsics/atan2.ll +++ b/llvm/test/CodeGen/SPIRV/hlsl-intrinsics/atan2.ll @@ -1,4 +1,5 @@ -; RUN: llc -verify-machineinstrs -O0 -mtriple=spirv-unknown-unknown %s -o - | FileCheck %s +; TODO(pull/110270): verifier, fix G_BITCAST error "bitcast must change type" +; RUN: llc -O0 -mtriple=spirv-unknown-unknown %s -o - | FileCheck %s ; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv-unknown-unknown %s -o - -filetype=obj | spirv-val %} ; CHECK-DAG: %[[#op_ext_glsl:]] = OpExtInstImport "GLSL.std.450" diff --git a/llvm/test/CodeGen/SPIRV/hlsl-intrinsics/ceil.ll b/llvm/test/CodeGen/SPIRV/hlsl-intrinsics/ceil.ll index 93677aadffa5e9..2c36459bdac95d 100644 --- a/llvm/test/CodeGen/SPIRV/hlsl-intrinsics/ceil.ll +++ b/llvm/test/CodeGen/SPIRV/hlsl-intrinsics/ceil.ll @@ -1,4 +1,5 @@ -; RUN: llc -verify-machineinstrs -O0 -mtriple=spirv-unknown-unknown %s -o - | FileCheck %s +; TODO(pull/110270): verifier, fix G_BITCAST error "bitcast must change type" +; RUN: llc -O0 -mtriple=spirv-unknown-unknown %s -o - | FileCheck %s ; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv-unknown-unknown %s -o - -filetype=obj | spirv-val %} ; CHECK: OpExtInstImport "GLSL.std.450" diff --git a/llvm/test/CodeGen/SPIRV/hlsl-intrinsics/cos.ll b/llvm/test/CodeGen/SPIRV/hlsl-intrinsics/cos.ll index e9e9642354f5a5..937a545cc563cb 100644 --- a/llvm/test/CodeGen/SPIRV/hlsl-intrinsics/cos.ll +++ b/llvm/test/CodeGen/SPIRV/hlsl-intrinsics/cos.ll @@ -1,4 +1,5 @@ -; RUN: llc -verify-machineinstrs -O0 -mtriple=spirv-unknown-unknown %s -o - | FileCheck %s +; TODO(pull/110270): verifier, fix G_BITCAST error "bitcast must change type" +; RUN: llc -O0 -mtriple=spirv-unknown-unknown %s -o - | FileCheck %s ; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv-unknown-unknown %s -o - -filetype=obj | spirv-val %} ; CHECK: OpExtInstImport "GLSL.std.450" diff --git a/llvm/test/CodeGen/SPIRV/hlsl-intrinsics/cosh.ll b/llvm/test/CodeGen/SPIRV/hlsl-intrinsics/cosh.ll index 1560f9b9bd7605..2d7a4caada7d54 100644 --- a/llvm/test/CodeGen/SPIRV/hlsl-intrinsics/cosh.ll +++ b/llvm/test/CodeGen/SPIRV/hlsl-intrinsics/cosh.ll @@ -1,4 +1,5 @@ -; RUN: llc -verify-machineinstrs -O0 -mtriple=spirv-unknown-unknown %s -o - | FileCheck %s +; TODO(pull/110270): verifier, fix G_BITCAST error "bitcast must change type" +; RUN: llc -O0 -mtriple=spirv-unknown-unknown %s -o - | FileCheck %s ; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv-unknown-unknown %s -o - -filetype=obj | spirv-val %} ; CHECK-DAG: %[[#op_ext_glsl:]] = OpExtInstImport "GLSL.std.450" diff --git a/llvm/test/CodeGen/SPIRV/hlsl-intrinsics/countbits.ll b/llvm/test/CodeGen/SPIRV/hlsl-intrinsics/countbits.ll index 57ec0bda2e1890..d47ec3ec27aa1b 100644 --- a/llvm/test/CodeGen/SPIRV/hlsl-intrinsics/countbits.ll +++ b/llvm/test/CodeGen/SPIRV/hlsl-intrinsics/countbits.ll @@ -1,4 +1,5 @@ -; RUN: llc -verify-machineinstrs -O0 -mtriple=spirv-unknown-unknown %s -o - | FileCheck %s +; TODO(pull/110270): verifier, fix G_BITCAST error "bitcast must change type" +; RUN: llc -O0 -mtriple=spirv-unknown-unknown %s -o - | FileCheck %s ; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv-unknown-unknown %s -o - -filetype=obj | spirv-val %} ; CHECK: OpMemoryModel Logical GLSL450 diff --git a/llvm/test/CodeGen/SPIRV/hlsl-intrinsics/degrees.ll b/llvm/test/CodeGen/SPIRV/hlsl-intrinsics/degrees.ll index 533bcca6f62169..6915362001288b 100644 --- a/llvm/test/CodeGen/SPIRV/hlsl-intrinsics/degrees.ll +++ b/llvm/test/CodeGen/SPIRV/hlsl-intrinsics/degrees.ll @@ -1,4 +1,5 @@ -; RUN: llc -verify-machineinstrs -O0 -mtriple=spirv-unknown-unknown %s -o - | FileCheck %s +; TODO(pull/110270): verifier, fix G_BITCAST error "bitcast must change type" +; RUN: llc -O0 -mtriple=spirv-unknown-unknown %s -o - | FileCheck %s ; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv-unknown-unknown %s -o - -filetype=obj | spirv-val %} ; CHECK-DAG: %[[#op_ext_glsl:]] = OpExtInstImport "GLSL.std.450" diff --git a/llvm/test/CodeGen/SPIRV/hlsl-intrinsics/exp.ll b/llvm/test/CodeGen/SPIRV/hlsl-intrinsics/exp.ll index c1734a264ea042..43bb8e217a6705 100644 --- a/llvm/test/CodeGen/SPIRV/hlsl-intrinsics/exp.ll +++ b/llvm/test/CodeGen/SPIRV/hlsl-intrinsics/exp.ll @@ -1,4 +1,5 @@ -; RUN: llc -verify-machineinstrs -O0 -mtriple=spirv-unknown-unknown %s -o - | FileCheck %s +; TODO(pull/110270): verifier, fix G_BITCAST error "bitcast must change type" +; RUN: llc -O0 -mtriple=spirv-unknown-unknown %s -o - | FileCheck %s ; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv-unknown-unknown %s -o - -filetype=obj | spirv-val %} ; CHECK: OpExtInstImport "GLSL.std.450" diff --git a/llvm/test/CodeGen/SPIRV/hlsl-intrinsics/exp2.ll b/llvm/test/CodeGen/SPIRV/hlsl-intrinsics/exp2.ll index 4753b7bd9fe5bd..ae6c33cb0c7ef2 100644 --- a/llvm/test/CodeGen/SPIRV/hlsl-intrinsics/exp2.ll +++ b/llvm/test/CodeGen/SPIRV/hlsl-intrinsics/exp2.ll @@ -1,4 +1,5 @@ -; RUN: llc -verify-machineinstrs -O0 -mtriple=spirv-unknown-unknown %s -o - | FileCheck %s +; TODO(pull/110270): verifier, fix G_BITCAST error "bitcast must change type" +; RUN: llc -O0 -mtriple=spirv-unknown-unknown %s -o - | FileCheck %s ; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv-unknown-unknown %s -o - -filetype=obj | spirv-val %} ; CHECK: OpExtInstImport "GLSL.std.450" diff --git a/llvm/test/CodeGen/SPIRV/hlsl-intrinsics/floor.ll b/llvm/test/CodeGen/SPIRV/hlsl-intrinsics/floor.ll index ea19fa94ea3265..1ecaafc22e6fad 100644 --- a/llvm/test/CodeGen/SPIRV/hlsl-intrinsics/floor.ll +++ b/llvm/test/CodeGen/SPIRV/hlsl-intrinsics/floor.ll @@ -1,4 +1,5 @@ -; RUN: llc -verify-machineinstrs -O0 -mtriple=spirv-unknown-unknown %s -o - | FileCheck %s +; TODO(pull/110270): verifier, fix G_BITCAST error "bitcast must change type" +; RUN: llc -O0 -mtriple=spirv-unknown-unknown %s -o - | FileCheck %s ; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv-unknown-unknown %s -o - -filetype=obj | spirv-val %} ; CHECK: OpExtInstImport "GLSL.std.450" diff --git a/llvm/test/CodeGen/SPIRV/hlsl-intrinsics/fmad.ll b/llvm/test/CodeGen/SPIRV/hlsl-intrinsics/fmad.ll index b1ca34dc504c03..add94601bd1687 100644 --- a/llvm/test/CodeGen/SPIRV/hlsl-intrinsics/fmad.ll +++ b/llvm/test/CodeGen/SPIRV/hlsl-intrinsics/fmad.ll @@ -1,4 +1,5 @@ -; RUN: llc -verify-machineinstrs -O0 -mtriple=spirv-unknown-unknown %s -o - | FileCheck %s +; TODO(pull/110270): verifier, fix G_BITCAST error "bitcast must change type" +; RUN: llc -O0 -mtriple=spirv-unknown-unknown %s -o - | FileCheck %s ; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv-unknown-unknown %s -o - -filetype=obj | spirv-val %} ; CHECK: OpExtInstImport "GLSL.std.450" diff --git a/llvm/test/CodeGen/SPIRV/hlsl-intrinsics/fmax.ll b/llvm/test/CodeGen/SPIRV/hlsl-intrinsics/fmax.ll index ca0fcfe8d646b6..b202025f5dc83d 100644 --- a/llvm/test/CodeGen/SPIRV/hlsl-intrinsics/fmax.ll +++ b/llvm/test/CodeGen/SPIRV/hlsl-intrinsics/fmax.ll @@ -1,4 +1,5 @@ -; RUN: llc -verify-machineinstrs -O0 -mtriple=spirv-unknown-unknown %s -o - | FileCheck %s +; TODO(pull/110270): verifier, fix G_BITCAST error "bitcast must change type" +; RUN: llc -O0 -mtriple=spirv-unknown-unknown %s -o - | FileCheck %s ; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv-unknown-unknown %s -o - -filetype=obj | spirv-val %} ; CHECK: OpExtInstImport "GLSL.std.450" diff --git a/llvm/test/CodeGen/SPIRV/hlsl-intrinsics/fmin.ll b/llvm/test/CodeGen/SPIRV/hlsl-intrinsics/fmin.ll index adc563bcea5c6c..77e2ed1748e6ee 100644 --- a/llvm/test/CodeGen/SPIRV/hlsl-intrinsics/fmin.ll +++ b/llvm/test/CodeGen/SPIRV/hlsl-intrinsics/fmin.ll @@ -1,4 +1,5 @@ -; RUN: llc -verify-machineinstrs -O0 -mtriple=spirv-unknown-unknown %s -o - | FileCheck %s +; TODO(pull/110270): verifier, fix G_BITCAST error "bitcast must change type" +; RUN: llc -O0 -mtriple=spirv-unknown-unknown %s -o - | FileCheck %s ; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv-unknown-unknown %s -o - -filetype=obj | spirv-val %} ; CHECK: OpExtInstImport "GLSL.std.450" diff --git a/llvm/test/CodeGen/SPIRV/hlsl-intrinsics/frac.ll b/llvm/test/CodeGen/SPIRV/hlsl-intrinsics/frac.ll index 4c088b6b38103c..41c18b693574f7 100644 --- a/llvm/test/CodeGen/SPIRV/hlsl-intrinsics/frac.ll +++ b/llvm/test/CodeGen/SPIRV/hlsl-intrinsics/frac.ll @@ -1,4 +1,5 @@ -; RUN: llc -verify-machineinstrs -O0 -mtriple=spirv-unknown-unknown %s -o - | FileCheck %s +; TODO(pull/110270): verifier, fix G_BITCAST error "bitcast must change type" +; RUN: llc -O0 -mtriple=spirv-unknown-unknown %s -o - | FileCheck %s ; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv-unknown-unknown %s -o - -filetype=obj | spirv-val %} ; CHECK-DAG: %[[#op_ext_glsl:]] = OpExtInstImport "GLSL.std.450" diff --git a/llvm/test/CodeGen/SPIRV/hlsl-intrinsics/group_memory_barrier_with_group_sync.ll b/llvm/test/CodeGen/SPIRV/hlsl-intrinsics/group_memory_barrier_with_group_sync.ll new file mode 100644 index 00000000000000..e314361fe41812 --- /dev/null +++ b/llvm/test/CodeGen/SPIRV/hlsl-intrinsics/group_memory_barrier_with_group_sync.ll @@ -0,0 +1,15 @@ +; TODO(pull/110270): verifier, fix G_BITCAST error "bitcast must change type" +; RUN: llc -O0 -mtriple=spirv-unknown-unknown %s -o - | FileCheck %s +; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv-unknown-unknown %s -o - -filetype=obj | spirv-val %} + +; CHECK: OpMemoryModel Logical GLSL450 + +define void @test_group_memory_barrier_with_group_sync() { +entry: + ; CHECK: %[[#TY:]] = OpTypeInt 32 0 + ; CHECK-DAG: %[[#MEM_SEM:]] = OpConstant %[[#TY]] 16 + ; CHECK-DAG: %[[#EXEC_AND_MEM_SCOPE:]] = OpConstant %[[#TY]] 2 + ; CHECK: OpControlBarrier %[[#EXEC_AND_MEM_SCOPE]] %[[#EXEC_AND_MEM_SCOPE]] %[[#MEM_SEM]] + call void @llvm.spv.group.memory.barrier.with.group.sync() + ret void +} diff --git a/llvm/test/CodeGen/SPIRV/hlsl-intrinsics/imad.ll b/llvm/test/CodeGen/SPIRV/hlsl-intrinsics/imad.ll index 1be8eb7e651661..a161147c8b9647 100644 --- a/llvm/test/CodeGen/SPIRV/hlsl-intrinsics/imad.ll +++ b/llvm/test/CodeGen/SPIRV/hlsl-intrinsics/imad.ll @@ -1,4 +1,5 @@ -; RUN: llc -verify-machineinstrs -O0 -mtriple=spirv-unknown-unknown %s -o - | FileCheck %s +; TODO(pull/110270): verifier, fix G_BITCAST error "bitcast must change type" +; RUN: llc -O0 -mtriple=spirv-unknown-unknown %s -o - | FileCheck %s ; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv-unknown-unknown %s -o - -filetype=obj | spirv-val %} ; CHECK-DAG: %[[#int_16:]] = OpTypeInt 16 0 diff --git a/llvm/test/CodeGen/SPIRV/hlsl-intrinsics/lerp.ll b/llvm/test/CodeGen/SPIRV/hlsl-intrinsics/lerp.ll index aa7ad8c74d336c..94272a84bd6392 100644 --- a/llvm/test/CodeGen/SPIRV/hlsl-intrinsics/lerp.ll +++ b/llvm/test/CodeGen/SPIRV/hlsl-intrinsics/lerp.ll @@ -1,4 +1,5 @@ -; RUN: llc -verify-machineinstrs -O0 -mtriple=spirv-unknown-unknown %s -o - | FileCheck %s +; TODO(pull/110270): verifier, fix G_BITCAST error "bitcast must change type" +; RUN: llc -O0 -mtriple=spirv-unknown-unknown %s -o - | FileCheck %s ; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv-unknown-unknown %s -o - -filetype=obj | spirv-val %} ; Make sure SPIRV operation function calls for lerp are generated as FMix diff --git a/llvm/test/CodeGen/SPIRV/hlsl-intrinsics/log.ll b/llvm/test/CodeGen/SPIRV/hlsl-intrinsics/log.ll index f85b20324da515..d5dd92042537a1 100644 --- a/llvm/test/CodeGen/SPIRV/hlsl-intrinsics/log.ll +++ b/llvm/test/CodeGen/SPIRV/hlsl-intrinsics/log.ll @@ -1,4 +1,5 @@ -; RUN: llc -verify-machineinstrs -O0 -mtriple=spirv-unknown-unknown %s -o - | FileCheck %s +; TODO(pull/110270): verifier, fix G_BITCAST error "bitcast must change type" +; RUN: llc -O0 -mtriple=spirv-unknown-unknown %s -o - | FileCheck %s ; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv-unknown-unknown %s -o - -filetype=obj | spirv-val %} ; CHECK: OpExtInstImport "GLSL.std.450" diff --git a/llvm/test/CodeGen/SPIRV/hlsl-intrinsics/log10.ll b/llvm/test/CodeGen/SPIRV/hlsl-intrinsics/log10.ll index 32d63a0c0f1d21..a829422d84ebfa 100644 --- a/llvm/test/CodeGen/SPIRV/hlsl-intrinsics/log10.ll +++ b/llvm/test/CodeGen/SPIRV/hlsl-intrinsics/log10.ll @@ -1,4 +1,5 @@ -; RUN: llc -verify-machineinstrs -O0 -mtriple=spirv-unknown-unknown %s -o - | FileCheck %s +; TODO(pull/110270): verifier, fix G_BITCAST error "bitcast must change type" +; RUN: llc -O0 -mtriple=spirv-unknown-unknown %s -o - | FileCheck %s ; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv-unknown-unknown %s -o - -filetype=obj | spirv-val %} ; CHECK: %[[#extinst:]] = OpExtInstImport "GLSL.std.450" @@ -6,35 +7,22 @@ ; CHECK: %[[#float:]] = OpTypeFloat 32 ; CHECK: %[[#v4float:]] = OpTypeVector %[[#float]] 4 ; CHECK: %[[#float_0_30103001:]] = OpConstant %[[#float]] 0.30103000998497009 -; CHECK: %[[#_ptr_Function_v4float:]] = OpTypePointer Function %[[#v4float]] -; CHECK: %[[#_ptr_Function_float:]] = OpTypePointer Function %[[#float]] -define void @main() { +define void @main(float %f, <4 x float> %f4) { entry: -; CHECK: %[[#f:]] = OpVariable %[[#_ptr_Function_float]] Function -; CHECK: %[[#logf:]] = OpVariable %[[#_ptr_Function_float]] Function -; CHECK: %[[#f4:]] = OpVariable %[[#_ptr_Function_v4float]] Function -; CHECK: %[[#logf4:]] = OpVariable %[[#_ptr_Function_v4float]] Function - %f = alloca float, align 4 +; CHECK-DAG: %[[#f:]] = OpFunctionParameter %[[#float]] +; CHECK-DAG: %[[#f4:]] = OpFunctionParameter %[[#v4float]] %logf = alloca float, align 4 - %f4 = alloca <4 x float>, align 16 %logf4 = alloca <4 x float>, align 16 -; CHECK: %[[#load:]] = OpLoad %[[#float]] %[[#f]] Aligned 4 -; CHECK: %[[#log2:]] = OpExtInst %[[#float]] %[[#extinst]] Log2 %[[#load]] + +; CHECK: %[[#log2:]] = OpExtInst %[[#float]] %[[#extinst]] Log2 %[[#f]] ; CHECK: %[[#res:]] = OpFMul %[[#float]] %[[#log2]] %[[#float_0_30103001]] -; CHECK: OpStore %[[#logf]] %[[#res]] Aligned 4 - %0 = load float, ptr %f, align 4 - %elt.log10 = call float @llvm.log10.f32(float %0) - store float %elt.log10, ptr %logf, align 4 + %elt.log10 = call float @llvm.log10.f32(float %f) -; CHECK: %[[#load:]] = OpLoad %[[#v4float]] %[[#f4]] Aligned 16 -; CHECK: %[[#log2:]] = OpExtInst %[[#v4float]] %[[#extinst]] Log2 %[[#load]] +; CHECK: %[[#log2:]] = OpExtInst %[[#v4float]] %[[#extinst]] Log2 %[[#f4]] ; CHECK: %[[#res:]] = OpVectorTimesScalar %[[#v4float]] %[[#log2]] %[[#float_0_30103001]] -; CHECK: OpStore %[[#logf4]] %[[#res]] Aligned 16 - %1 = load <4 x float>, ptr %f4, align 16 - %elt.log101 = call <4 x float> @llvm.log10.v4f32(<4 x float> %1) - store <4 x float> %elt.log101, ptr %logf4, align 16 + %elt.log101 = call <4 x float> @llvm.log10.v4f32(<4 x float> %f4) ret void } diff --git a/llvm/test/CodeGen/SPIRV/hlsl-intrinsics/log2.ll b/llvm/test/CodeGen/SPIRV/hlsl-intrinsics/log2.ll index add7f77897f790..c71ca125c172a7 100644 --- a/llvm/test/CodeGen/SPIRV/hlsl-intrinsics/log2.ll +++ b/llvm/test/CodeGen/SPIRV/hlsl-intrinsics/log2.ll @@ -1,4 +1,5 @@ -; RUN: llc -verify-machineinstrs -O0 -mtriple=spirv-unknown-unknown %s -o - | FileCheck %s +; TODO(pull/110270): verifier, fix G_BITCAST error "bitcast must change type" +; RUN: llc -O0 -mtriple=spirv-unknown-unknown %s -o - | FileCheck %s ; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv-unknown-unknown %s -o - -filetype=obj | spirv-val %} ; CHECK: OpExtInstImport "GLSL.std.450" diff --git a/llvm/test/CodeGen/SPIRV/hlsl-intrinsics/normalize.ll b/llvm/test/CodeGen/SPIRV/hlsl-intrinsics/normalize.ll index fa73b9c2a4d3ab..ddf89221be2ae4 100644 --- a/llvm/test/CodeGen/SPIRV/hlsl-intrinsics/normalize.ll +++ b/llvm/test/CodeGen/SPIRV/hlsl-intrinsics/normalize.ll @@ -1,3 +1,4 @@ +; TODO(pull/110270): verifier, fix G_BITCAST error "bitcast must change type" ; RUN: llc -O0 -mtriple=spirv-unknown-unknown %s -o - | FileCheck %s ; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv-unknown-unknown %s -o - -filetype=obj | spirv-val %} diff --git a/llvm/test/CodeGen/SPIRV/hlsl-intrinsics/pow.ll b/llvm/test/CodeGen/SPIRV/hlsl-intrinsics/pow.ll index 3ac98853b92fbc..38c51ca47d86c9 100644 --- a/llvm/test/CodeGen/SPIRV/hlsl-intrinsics/pow.ll +++ b/llvm/test/CodeGen/SPIRV/hlsl-intrinsics/pow.ll @@ -1,4 +1,5 @@ -; RUN: llc -verify-machineinstrs -O0 -mtriple=spirv-unknown-unknown %s -o - | FileCheck %s +; TODO(pull/110270): verifier, fix G_BITCAST error "bitcast must change type" +; RUN: llc -O0 -mtriple=spirv-unknown-unknown %s -o - | FileCheck %s ; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv-unknown-unknown %s -o - -filetype=obj | spirv-val %} ; CHECK: OpExtInstImport "GLSL.std.450" diff --git a/llvm/test/CodeGen/SPIRV/hlsl-intrinsics/radians.ll b/llvm/test/CodeGen/SPIRV/hlsl-intrinsics/radians.ll index 1fe8ab30ed9538..7aad4df76e3185 100644 --- a/llvm/test/CodeGen/SPIRV/hlsl-intrinsics/radians.ll +++ b/llvm/test/CodeGen/SPIRV/hlsl-intrinsics/radians.ll @@ -1,4 +1,5 @@ -; RUN: llc -verify-machineinstrs -O0 -mtriple=spirv-unknown-unknown %s -o - | FileCheck %s +; TODO(pull/110270): verifier, fix G_BITCAST error "bitcast must change type" +; RUN: llc -O0 -mtriple=spirv-unknown-unknown %s -o - | FileCheck %s ; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv-unknown-unknown %s -o - -filetype=obj | spirv-val %} ; CHECK-DAG: %[[#op_ext_glsl:]] = OpExtInstImport "GLSL.std.450" diff --git a/llvm/test/CodeGen/SPIRV/hlsl-intrinsics/rcp.ll b/llvm/test/CodeGen/SPIRV/hlsl-intrinsics/rcp.ll index 6f91162a378c8a..9c8c14c2a7220a 100644 --- a/llvm/test/CodeGen/SPIRV/hlsl-intrinsics/rcp.ll +++ b/llvm/test/CodeGen/SPIRV/hlsl-intrinsics/rcp.ll @@ -1,4 +1,5 @@ - ; RUN: llc -verify-machineinstrs -O0 -mtriple=spirv-unknown-unknown %s -o - | FileCheck %s +; TODO(pull/110270): verifier, fix G_BITCAST error "bitcast must change type" + ; RUN: llc -O0 -mtriple=spirv-unknown-unknown %s -o - | FileCheck %s ; CHECK-DAG: %[[#float_64:]] = OpTypeFloat 64 ; CHECK-DAG: %[[#float_32:]] = OpTypeFloat 32 diff --git a/llvm/test/CodeGen/SPIRV/hlsl-intrinsics/reversebits.ll b/llvm/test/CodeGen/SPIRV/hlsl-intrinsics/reversebits.ll index a23b15ab075d60..ce8175fdceb202 100644 --- a/llvm/test/CodeGen/SPIRV/hlsl-intrinsics/reversebits.ll +++ b/llvm/test/CodeGen/SPIRV/hlsl-intrinsics/reversebits.ll @@ -1,4 +1,5 @@ -; RUN: llc -verify-machineinstrs -O0 -mtriple=spirv-unknown-unknown %s -o - | FileCheck %s +; TODO(pull/110270): verifier, fix G_BITCAST error "bitcast must change type" +; RUN: llc -O0 -mtriple=spirv-unknown-unknown %s -o - | FileCheck %s ; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv-unknown-unknown %s -o - -filetype=obj | spirv-val %} ; CHECK: OpMemoryModel Logical GLSL450 diff --git a/llvm/test/CodeGen/SPIRV/hlsl-intrinsics/round.ll b/llvm/test/CodeGen/SPIRV/hlsl-intrinsics/round.ll index 1c7e78261ffefd..0c88c55cbd395f 100644 --- a/llvm/test/CodeGen/SPIRV/hlsl-intrinsics/round.ll +++ b/llvm/test/CodeGen/SPIRV/hlsl-intrinsics/round.ll @@ -1,4 +1,5 @@ -; RUN: llc -verify-machineinstrs -O0 -mtriple=spirv-unknown-unknown %s -o - | FileCheck %s +; TODO(pull/110270): verifier, fix G_BITCAST error "bitcast must change type" +; RUN: llc -O0 -mtriple=spirv-unknown-unknown %s -o - | FileCheck %s ; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv-unknown-unknown %s -o - -filetype=obj | spirv-val %} ; CHECK: OpExtInstImport "GLSL.std.450" diff --git a/llvm/test/CodeGen/SPIRV/hlsl-intrinsics/rsqrt.ll b/llvm/test/CodeGen/SPIRV/hlsl-intrinsics/rsqrt.ll index 91023a1e401e16..33d3edc080fd78 100644 --- a/llvm/test/CodeGen/SPIRV/hlsl-intrinsics/rsqrt.ll +++ b/llvm/test/CodeGen/SPIRV/hlsl-intrinsics/rsqrt.ll @@ -1,4 +1,5 @@ -; RUN: llc -verify-machineinstrs -O0 -mtriple=spirv-unknown-unknown %s -o - | FileCheck %s +; TODO(pull/110270): verifier, fix G_BITCAST error "bitcast must change type" +; RUN: llc -O0 -mtriple=spirv-unknown-unknown %s -o - | FileCheck %s ; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv-unknown-unknown %s -o - -filetype=obj | spirv-val %} ; CHECK-DAG: %[[#op_ext_glsl:]] = OpExtInstImport "GLSL.std.450" diff --git a/llvm/test/CodeGen/SPIRV/hlsl-intrinsics/sin.ll b/llvm/test/CodeGen/SPIRV/hlsl-intrinsics/sin.ll index a6ae70a48e5db4..7474b759945138 100644 --- a/llvm/test/CodeGen/SPIRV/hlsl-intrinsics/sin.ll +++ b/llvm/test/CodeGen/SPIRV/hlsl-intrinsics/sin.ll @@ -1,4 +1,5 @@ -; RUN: llc -verify-machineinstrs -O0 -mtriple=spirv-unknown-unknown %s -o - | FileCheck %s +; TODO(pull/110270): verifier, fix G_BITCAST error "bitcast must change type" +; RUN: llc -O0 -mtriple=spirv-unknown-unknown %s -o - | FileCheck %s ; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv-unknown-unknown %s -o - -filetype=obj | spirv-val %} ; CHECK: OpExtInstImport "GLSL.std.450" diff --git a/llvm/test/CodeGen/SPIRV/hlsl-intrinsics/sinh.ll b/llvm/test/CodeGen/SPIRV/hlsl-intrinsics/sinh.ll index 3b8bdbed0041bb..6a31b702187733 100644 --- a/llvm/test/CodeGen/SPIRV/hlsl-intrinsics/sinh.ll +++ b/llvm/test/CodeGen/SPIRV/hlsl-intrinsics/sinh.ll @@ -1,4 +1,5 @@ -; RUN: llc -verify-machineinstrs -O0 -mtriple=spirv-unknown-unknown %s -o - | FileCheck %s +; TODO(pull/110270): verifier, fix G_BITCAST error "bitcast must change type" +; RUN: llc -O0 -mtriple=spirv-unknown-unknown %s -o - | FileCheck %s ; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv-unknown-unknown %s -o - -filetype=obj | spirv-val %} ; CHECK-DAG: %[[#op_ext_glsl:]] = OpExtInstImport "GLSL.std.450" diff --git a/llvm/test/CodeGen/SPIRV/hlsl-intrinsics/smax.ll b/llvm/test/CodeGen/SPIRV/hlsl-intrinsics/smax.ll index 901e4764e15f67..cbf0b243ab2b3f 100644 --- a/llvm/test/CodeGen/SPIRV/hlsl-intrinsics/smax.ll +++ b/llvm/test/CodeGen/SPIRV/hlsl-intrinsics/smax.ll @@ -1,4 +1,5 @@ -; RUN: llc -verify-machineinstrs -O0 -mtriple=spirv-unknown-unknown %s -o - | FileCheck %s +; TODO(pull/110270): verifier, fix G_BITCAST error "bitcast must change type" +; RUN: llc -O0 -mtriple=spirv-unknown-unknown %s -o - | FileCheck %s ; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv-unknown-unknown %s -o - -filetype=obj | spirv-val %} ; CHECK: OpExtInstImport "GLSL.std.450" diff --git a/llvm/test/CodeGen/SPIRV/hlsl-intrinsics/smin.ll b/llvm/test/CodeGen/SPIRV/hlsl-intrinsics/smin.ll index c39c39f0455fad..960de853f3afdf 100644 --- a/llvm/test/CodeGen/SPIRV/hlsl-intrinsics/smin.ll +++ b/llvm/test/CodeGen/SPIRV/hlsl-intrinsics/smin.ll @@ -1,4 +1,5 @@ -; RUN: llc -verify-machineinstrs -O0 -mtriple=spirv-unknown-unknown %s -o - | FileCheck %s +; TODO(pull/110270): verifier, fix G_BITCAST error "bitcast must change type" +; RUN: llc -O0 -mtriple=spirv-unknown-unknown %s -o - | FileCheck %s ; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv-unknown-unknown %s -o - -filetype=obj | spirv-val %} ; CHECK: OpExtInstImport "GLSL.std.450" diff --git a/llvm/test/CodeGen/SPIRV/hlsl-intrinsics/splitdouble.ll b/llvm/test/CodeGen/SPIRV/hlsl-intrinsics/splitdouble.ll index d18b16b843c37b..a05a31c18a754f 100644 --- a/llvm/test/CodeGen/SPIRV/hlsl-intrinsics/splitdouble.ll +++ b/llvm/test/CodeGen/SPIRV/hlsl-intrinsics/splitdouble.ll @@ -1,4 +1,5 @@ -; RUN: llc -verify-machineinstrs -O0 -mtriple=spirv-unknown-unknown %s -o - | FileCheck %s +; TODO(pull/110270): verifier, fix G_BITCAST error "bitcast must change type" +; RUN: llc -O0 -mtriple=spirv-unknown-unknown %s -o - | FileCheck %s ; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv-unknown-unknown %s -o - -filetype=obj | spirv-val %} ; Make sure lowering is correctly generating spirv code. diff --git a/llvm/test/CodeGen/SPIRV/hlsl-intrinsics/sqrt.ll b/llvm/test/CodeGen/SPIRV/hlsl-intrinsics/sqrt.ll index bb1f0346047e22..55d8a286a0e7fd 100644 --- a/llvm/test/CodeGen/SPIRV/hlsl-intrinsics/sqrt.ll +++ b/llvm/test/CodeGen/SPIRV/hlsl-intrinsics/sqrt.ll @@ -1,4 +1,5 @@ -; RUN: llc -verify-machineinstrs -O0 -mtriple=spirv-unknown-unknown %s -o - | FileCheck %s +; TODO(pull/110270): verifier, fix G_BITCAST error "bitcast must change type" +; RUN: llc -O0 -mtriple=spirv-unknown-unknown %s -o - | FileCheck %s ; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv-unknown-unknown %s -o - -filetype=obj | spirv-val %} ; CHECK: OpExtInstImport "GLSL.std.450" diff --git a/llvm/test/CodeGen/SPIRV/hlsl-intrinsics/step.ll b/llvm/test/CodeGen/SPIRV/hlsl-intrinsics/step.ll index bb50d8c790f8ad..eac0b858955545 100644 --- a/llvm/test/CodeGen/SPIRV/hlsl-intrinsics/step.ll +++ b/llvm/test/CodeGen/SPIRV/hlsl-intrinsics/step.ll @@ -1,3 +1,4 @@ +; TODO(pull/110270): verifier, fix G_BITCAST error "bitcast must change type" ; RUN: llc -O0 -mtriple=spirv-unknown-unknown %s -o - | FileCheck %s ; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv-unknown-unknown %s -o - -filetype=obj | spirv-val %} diff --git a/llvm/test/CodeGen/SPIRV/hlsl-intrinsics/tan.ll b/llvm/test/CodeGen/SPIRV/hlsl-intrinsics/tan.ll index b4a6e1574f732b..6e2f0698b7b6d5 100644 --- a/llvm/test/CodeGen/SPIRV/hlsl-intrinsics/tan.ll +++ b/llvm/test/CodeGen/SPIRV/hlsl-intrinsics/tan.ll @@ -1,4 +1,5 @@ -; RUN: llc -verify-machineinstrs -O0 -mtriple=spirv-unknown-unknown %s -o - | FileCheck %s +; TODO(pull/110270): verifier, fix G_BITCAST error "bitcast must change type" +; RUN: llc -O0 -mtriple=spirv-unknown-unknown %s -o - | FileCheck %s ; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv-unknown-unknown %s -o - -filetype=obj | spirv-val %} ; CHECK-DAG: %[[#op_ext_glsl:]] = OpExtInstImport "GLSL.std.450" diff --git a/llvm/test/CodeGen/SPIRV/hlsl-intrinsics/tanh.ll b/llvm/test/CodeGen/SPIRV/hlsl-intrinsics/tanh.ll index 94fc3f0ec7abf5..1dfdf83fee31e7 100644 --- a/llvm/test/CodeGen/SPIRV/hlsl-intrinsics/tanh.ll +++ b/llvm/test/CodeGen/SPIRV/hlsl-intrinsics/tanh.ll @@ -1,4 +1,5 @@ -; RUN: llc -verify-machineinstrs -O0 -mtriple=spirv-unknown-unknown %s -o - | FileCheck %s +; TODO(pull/110270): verifier, fix G_BITCAST error "bitcast must change type" +; RUN: llc -O0 -mtriple=spirv-unknown-unknown %s -o - | FileCheck %s ; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv-unknown-unknown %s -o - -filetype=obj | spirv-val %} ; CHECK-DAG: %[[#op_ext_glsl:]] = OpExtInstImport "GLSL.std.450" diff --git a/llvm/test/CodeGen/SPIRV/hlsl-intrinsics/trunc.ll b/llvm/test/CodeGen/SPIRV/hlsl-intrinsics/trunc.ll index 2a308028a9b482..bae614ee59676c 100644 --- a/llvm/test/CodeGen/SPIRV/hlsl-intrinsics/trunc.ll +++ b/llvm/test/CodeGen/SPIRV/hlsl-intrinsics/trunc.ll @@ -1,4 +1,5 @@ -; RUN: llc -verify-machineinstrs -O0 -mtriple=spirv-unknown-unknown %s -o - | FileCheck %s +; TODO(pull/110270): verifier, fix G_BITCAST error "bitcast must change type" +; RUN: llc -O0 -mtriple=spirv-unknown-unknown %s -o - | FileCheck %s ; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv-unknown-unknown %s -o - -filetype=obj | spirv-val %} ; CHECK: OpExtInstImport "GLSL.std.450" diff --git a/llvm/test/CodeGen/SPIRV/hlsl-intrinsics/umax.ll b/llvm/test/CodeGen/SPIRV/hlsl-intrinsics/umax.ll index 01606a38732772..e2b14b089bc139 100644 --- a/llvm/test/CodeGen/SPIRV/hlsl-intrinsics/umax.ll +++ b/llvm/test/CodeGen/SPIRV/hlsl-intrinsics/umax.ll @@ -1,4 +1,5 @@ -; RUN: llc -verify-machineinstrs -O0 -mtriple=spirv-unknown-unknown %s -o - | FileCheck %s +; TODO(pull/110270): verifier, fix G_BITCAST error "bitcast must change type" +; RUN: llc -O0 -mtriple=spirv-unknown-unknown %s -o - | FileCheck %s ; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv-unknown-unknown %s -o - -filetype=obj | spirv-val %} ; CHECK: OpExtInstImport "GLSL.std.450" diff --git a/llvm/test/CodeGen/SPIRV/hlsl-intrinsics/umin.ll b/llvm/test/CodeGen/SPIRV/hlsl-intrinsics/umin.ll index 34185ad7143e32..708b76a93e6613 100644 --- a/llvm/test/CodeGen/SPIRV/hlsl-intrinsics/umin.ll +++ b/llvm/test/CodeGen/SPIRV/hlsl-intrinsics/umin.ll @@ -1,4 +1,5 @@ -; RUN: llc -verify-machineinstrs -O0 -mtriple=spirv-unknown-unknown %s -o - | FileCheck %s +; TODO(pull/110270): verifier, fix G_BITCAST error "bitcast must change type" +; RUN: llc -O0 -mtriple=spirv-unknown-unknown %s -o - | FileCheck %s ; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv-unknown-unknown %s -o - -filetype=obj | spirv-val %} ; CHECK: OpExtInstImport "GLSL.std.450" diff --git a/llvm/test/CodeGen/SPIRV/literals.ll b/llvm/test/CodeGen/SPIRV/literals.ll index 4109bb6de56110..86a366976a6e26 100644 --- a/llvm/test/CodeGen/SPIRV/literals.ll +++ b/llvm/test/CodeGen/SPIRV/literals.ll @@ -1,12 +1,10 @@ +; TODO(pull/110270): verifier, fix G_BITCAST error "bitcast must change type" ; RUN: llc -verify-machineinstrs -O0 -mtriple=spirv32-unknown-unknown %s -o - | FileCheck %s ; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv32-unknown-unknown %s -o - -filetype=obj | spirv-val %} ; RUN: llc -verify-machineinstrs -O0 -mtriple=spirv64-unknown-unknown %s -o - | FileCheck %s ; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv64-unknown-unknown %s -o - -filetype=obj | spirv-val %} -; RUN: llc -verify-machineinstrs -O0 -mtriple=spirv-unknown-unknown %s -o - | FileCheck %s -; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv-unknown-unknown %s -o - -filetype=obj | spirv-val %} - ; CHECK: %[[#F32:]] = OpTypeFloat 32 ; CHECK: %[[#F64:]] = OpTypeFloat 64 diff --git a/llvm/test/CodeGen/SPIRV/structurizer/basic-if.ll b/llvm/test/CodeGen/SPIRV/structurizer/basic-if.ll new file mode 100644 index 00000000000000..5585e4a07590a3 --- /dev/null +++ b/llvm/test/CodeGen/SPIRV/structurizer/basic-if.ll @@ -0,0 +1,52 @@ +; RUN: llc -mtriple=spirv-unknown-vulkan-compute -O0 %s -o - | FileCheck %s +; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv-unknown-vulkan-compute %s -o - -filetype=obj | spirv-val %} + +target triple = "spirv-unknown-vulkan1.3-compute" + +; Function Attrs: convergent noinline norecurse nounwind optnone +define spir_func noundef i32 @_Z7processv() #0 { + +; CHECK: %[[#entry:]] = OpLabel +; CHECK: OpSelectionMerge %[[#merge:]] None +; CHECK: OpBranchConditional %[[#]] %[[#left:]] %[[#right:]] +entry: + %0 = call token @llvm.experimental.convergence.entry() + %1 = alloca i32, align 4 + br i1 true, label %left, label %right + +; CHECK: %[[#left]] = OpLabel +; CHECK: OpBranch %[[#merge]] +left: + store i32 0, ptr %1 + br label %end + +; CHECK: %[[#right]] = OpLabel +; CHECK: OpBranch %[[#merge]] +right: + store i32 0, ptr %1 + br label %end + +; CHECK: %[[#merge]] = OpLabel +; CHECK: OpReturnValue %[[#]] +end: + ret i32 0 +} + +; Function Attrs: convergent nocallback nofree nosync nounwind willreturn memory(none) +declare token @llvm.experimental.convergence.entry() #1 + +; Function Attrs: convergent nocallback nofree nosync nounwind willreturn memory(none) +declare token @llvm.experimental.convergence.loop() #1 + + +attributes #0 = { convergent noinline norecurse nounwind optnone "frame-pointer"="all" "no-trapping-math"="true" "stack-protector-buffer-size"="8" } +attributes #1 = { convergent nocallback nofree nosync nounwind willreturn memory(none) } +attributes #2 = { convergent norecurse "frame-pointer"="all" "hlsl.numthreads"="1,1,1" "hlsl.shader"="compute" "no-trapping-math"="true" "stack-protector-buffer-size"="8" } +attributes #3 = { convergent } + +!llvm.module.flags = !{!0, !1, !2} + + +!0 = !{i32 1, !"wchar_size", i32 4} +!1 = !{i32 4, !"dx.disable_optimizations", i32 1} +!2 = !{i32 7, !"frame-pointer", i32 2} diff --git a/llvm/test/CodeGen/SPIRV/structurizer/basic-imbalanced-if.ll b/llvm/test/CodeGen/SPIRV/structurizer/basic-imbalanced-if.ll new file mode 100644 index 00000000000000..810b5785e4b1a4 --- /dev/null +++ b/llvm/test/CodeGen/SPIRV/structurizer/basic-imbalanced-if.ll @@ -0,0 +1,47 @@ +; RUN: llc -mtriple=spirv-unknown-vulkan-compute -O0 %s -o - | FileCheck %s +; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv-unknown-vulkan-compute %s -o - -filetype=obj | spirv-val %} + +target datalayout = "e-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128-v192:256-v256:256-v512:512-v1024:1024-G1" +target triple = "spirv-unknown-vulkan1.3-compute" + +; Function Attrs: convergent noinline norecurse nounwind optnone +define spir_func noundef i32 @_Z7processv() #0 { + +; CHECK: %[[#entry:]] = OpLabel +; CHECK: OpSelectionMerge %[[#merge:]] None +; CHECK: OpBranchConditional %[[#]] %[[#left:]] %[[#merge]] +entry: + %0 = call token @llvm.experimental.convergence.entry() + %1 = alloca i32, align 4 + br i1 true, label %left, label %end + +; CHECK: %[[#left]] = OpLabel +; CHECK: OpBranch %[[#merge]] +left: + store i32 0, ptr %1 + br label %end + +; CHECK: %[[#merge]] = OpLabel +; CHECK: OpReturnValue %[[#]] +end: + ret i32 0 +} + +; Function Attrs: convergent nocallback nofree nosync nounwind willreturn memory(none) +declare token @llvm.experimental.convergence.entry() #1 + +; Function Attrs: convergent nocallback nofree nosync nounwind willreturn memory(none) +declare token @llvm.experimental.convergence.loop() #1 + + +attributes #0 = { convergent noinline norecurse nounwind optnone "frame-pointer"="all" "no-trapping-math"="true" "stack-protector-buffer-size"="8" } +attributes #1 = { convergent nocallback nofree nosync nounwind willreturn memory(none) } +attributes #2 = { convergent norecurse "frame-pointer"="all" "hlsl.numthreads"="1,1,1" "hlsl.shader"="compute" "no-trapping-math"="true" "stack-protector-buffer-size"="8" } +attributes #3 = { convergent } + +!llvm.module.flags = !{!0, !1, !2} + + +!0 = !{i32 1, !"wchar_size", i32 4} +!1 = !{i32 4, !"dx.disable_optimizations", i32 1} +!2 = !{i32 7, !"frame-pointer", i32 2} diff --git a/llvm/test/CodeGen/SPIRV/structurizer/basic-loop.ll b/llvm/test/CodeGen/SPIRV/structurizer/basic-loop.ll new file mode 100644 index 00000000000000..ded9c335c5a25f --- /dev/null +++ b/llvm/test/CodeGen/SPIRV/structurizer/basic-loop.ll @@ -0,0 +1,59 @@ +; RUN: llc -mtriple=spirv-unknown-vulkan-compute -O0 %s -o - | FileCheck %s +; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv-unknown-vulkan-compute %s -o - -filetype=obj | spirv-val %} + +target datalayout = "e-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128-v192:256-v256:256-v512:512-v1024:1024-G1" +target triple = "spirv-unknown-vulkan1.3-compute" + +; Function Attrs: convergent noinline norecurse nounwind optnone +define spir_func noundef i32 @_Z7processv() #0 { + +; CHECK: %[[#entry:]] = OpLabel +; CHECK: OpBranch %[[#header:]] +entry: + %0 = call token @llvm.experimental.convergence.entry() + %1 = alloca i32, align 4 + br label %header + +; CHECK: %[[#header]] = OpLabel +; CHECK: OpLoopMerge %[[#merge:]] %[[#continue:]] None +; CHECK: OpBranchConditional %[[#]] %[[#body:]] %[[#merge]] +header: + %2 = call token @llvm.experimental.convergence.loop() [ "convergencectrl"(token %0) ] + br i1 true, label %body, label %merge + +; CHECK: %[[#body]] = OpLabel +; CHECK: OpBranch %[[#continue]] +body: + store i32 0, ptr %1 + br label %continue + +continue: + br label %header +; CHECK: %[[#continue]] = OpLabel +; CHECK: OpBranch %[[#header]] + +; CHECK: %[[#merge]] = OpLabel +; CHECK: OpReturnValue %[[#]] +merge: + ret i32 0 +} + +; Function Attrs: convergent nocallback nofree nosync nounwind willreturn memory(none) +declare token @llvm.experimental.convergence.entry() #1 + +; Function Attrs: convergent nocallback nofree nosync nounwind willreturn memory(none) +declare token @llvm.experimental.convergence.loop() #1 + + +attributes #0 = { convergent noinline norecurse nounwind optnone "frame-pointer"="all" "no-trapping-math"="true" "stack-protector-buffer-size"="8" } +attributes #1 = { convergent nocallback nofree nosync nounwind willreturn memory(none) } +attributes #2 = { convergent norecurse "frame-pointer"="all" "hlsl.numthreads"="1,1,1" "hlsl.shader"="compute" "no-trapping-math"="true" "stack-protector-buffer-size"="8" } +attributes #3 = { convergent } + +!llvm.module.flags = !{!0, !1, !2} + + +!0 = !{i32 1, !"wchar_size", i32 4} +!1 = !{i32 4, !"dx.disable_optimizations", i32 1} +!2 = !{i32 7, !"frame-pointer", i32 2} + diff --git a/llvm/test/CodeGen/SPIRV/structurizer/basic-phi.ll b/llvm/test/CodeGen/SPIRV/structurizer/basic-phi.ll new file mode 100644 index 00000000000000..a43d25e9b06d5d --- /dev/null +++ b/llvm/test/CodeGen/SPIRV/structurizer/basic-phi.ll @@ -0,0 +1,58 @@ +; RUN: llc -mtriple=spirv-unknown-vulkan-compute -O0 %s -o - | FileCheck %s +; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv-unknown-vulkan-compute %s -o - -filetype=obj | spirv-val %} + +target datalayout = "e-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128-v192:256-v256:256-v512:512-v1024:1024-G1" +target triple = "spirv-unknown-vulkan1.3-compute" + +; Function Attrs: convergent noinline norecurse nounwind optnone +define spir_func noundef i32 @_Z7processv() #0 { + +; CHECK-DAG: %[[#int_0:]] = OpConstant %[[#]] 0 +; CHECK-DAG: %[[#int_1:]] = OpConstant %[[#]] 1 + +; CHECK: %[[#entry:]] = OpLabel +; CHECK: %[[#var:]] = OpVariable %[[#]] Function +; CHECK: OpSelectionMerge %[[#merge:]] None +; CHECK: OpBranchConditional %[[#]] %[[#left:]] %[[#right:]] +entry: + %0 = call token @llvm.experimental.convergence.entry() + br i1 true, label %left, label %right + +; CHECK: %[[#left]] = OpLabel +; CHECK-NEXT: OpStore %[[#var]] %[[#int_0]] +; CHECK-NEXT: OpBranch %[[#merge]] +left: + br label %end + +; CHECK: %[[#right]] = OpLabel +; CHECK-NEXT: OpStore %[[#var]] %[[#int_1]] +; CHECK-NEXT: OpBranch %[[#merge]] +right: + br label %end + +; CHECK: %[[#merge]] = OpLabel +; CHECK: %[[#tmp:]] = OpLoad %[[#]] %[[#var]] +; CHECK: OpReturnValue %[[#tmp]] +end: + %1 = phi i32 [ 0, %left ], [ 1, %right ] + ret i32 %1 +} + +; Function Attrs: convergent nocallback nofree nosync nounwind willreturn memory(none) +declare token @llvm.experimental.convergence.entry() #1 + +; Function Attrs: convergent nocallback nofree nosync nounwind willreturn memory(none) +declare token @llvm.experimental.convergence.loop() #1 + + +attributes #0 = { convergent noinline norecurse nounwind optnone "frame-pointer"="all" "no-trapping-math"="true" "stack-protector-buffer-size"="8" } +attributes #1 = { convergent nocallback nofree nosync nounwind willreturn memory(none) } +attributes #2 = { convergent norecurse "frame-pointer"="all" "hlsl.numthreads"="1,1,1" "hlsl.shader"="compute" "no-trapping-math"="true" "stack-protector-buffer-size"="8" } +attributes #3 = { convergent } + +!llvm.module.flags = !{!0, !1, !2} + + +!0 = !{i32 1, !"wchar_size", i32 4} +!1 = !{i32 4, !"dx.disable_optimizations", i32 1} +!2 = !{i32 7, !"frame-pointer", i32 2} diff --git a/llvm/test/CodeGen/SPIRV/structurizer/cf.cond-op.ll b/llvm/test/CodeGen/SPIRV/structurizer/cf.cond-op.ll index 4934b17c8c002e..86033608deb6e2 100644 --- a/llvm/test/CodeGen/SPIRV/structurizer/cf.cond-op.ll +++ b/llvm/test/CodeGen/SPIRV/structurizer/cf.cond-op.ll @@ -8,16 +8,17 @@ target triple = "spirv-unknown-vulkan1.3-compute" ; CHECK-DAG: OpName %[[#fn:]] "_Z2fnv" ; CHECK-DAG: OpName %[[#fn1:]] "_Z3fn1v" ; CHECK-DAG: OpName %[[#fn2:]] "_Z3fn2v" -; CHECK-DAG: OpName %[[#val:]] "val" -; CHECK-DAG: OpName %[[#a:]] "a" -; CHECK-DAG: OpName %[[#b:]] "b" -; CHECK-DAG: OpName %[[#c:]] "c" + +; CHECK-DAG: OpName %[[#r2m_a:]] ".reg2mem3" +; CHECK-DAG: OpName %[[#r2m_b:]] ".reg2mem1" +; CHECK-DAG: OpName %[[#r2m_c:]] ".reg2mem" ; CHECK-DAG: %[[#int_ty:]] = OpTypeInt 32 0 -; CHECK-DAG: %[[#bool_ty:]] = OpTypeBool -; CHECK-DAG: %[[#int_pfty:]] = OpTypePointer Function %[[#int_ty]] -; CHECK-DAG: %[[#int_0:]] = OpConstant %[[#int_ty]] 0 +; CHECK-DAG: %[[#int_0:]] = OpConstant %[[#]] 0 +; CHECK-DAG: %[[#int_1:]] = OpConstant %[[#]] 1 +; CHECK-DAG: %[[#true:]] = OpConstantTrue +; CHECK-DAG: %[[#false:]] = OpConstantFalse declare token @llvm.experimental.convergence.entry() #1 @@ -44,100 +45,86 @@ entry: ; CHECK: %[[#process]] = OpFunction %[[#int_ty]] define spir_func noundef i32 @_Z7processv() #0 { + +; CHECK: %[[#entry:]] = OpLabel +; CHECK-DAG: %[[#r2m_a]] = OpVariable %[[#]] Function +; CHECK: OpSelectionMerge %[[#a_merge:]] +; CHECK: OpBranchConditional %[[#]] %[[#a_true:]] %[[#a_false:]] entry: - ; CHECK: %[[#entry:]] = OpLabel %0 = call token @llvm.experimental.convergence.entry() - %a = alloca i32, align 4 - %b = alloca i32, align 4 - %c = alloca i32, align 4 - %val = alloca i32, align 4 - store i32 0, ptr %a, align 4 - store i32 1, ptr %b, align 4 - store i32 2, ptr %c, align 4 - store i32 0, ptr %val, align 4 - ; CHECK-DAG: %[[#a]] = OpVariable %[[#int_pfty]] Function - ; CHECK-DAG: %[[#b]] = OpVariable %[[#int_pfty]] Function - ; CHECK-DAG: %[[#c]] = OpVariable %[[#int_pfty]] Function - ; CHECK-DAG: %[[#val]] = OpVariable %[[#int_pfty]] Function - %1 = load i32, ptr %a, align 4 - %tobool = icmp ne i32 %1, 0 - br i1 %tobool, label %cond.true, label %cond.false - ; CHECK: %[[#tmp:]] = OpLoad %[[#int_ty]] %[[#a]] - ; CHECK: %[[#cond:]] = OpINotEqual %[[#bool_ty]] %[[#tmp]] %[[#int_0]] - ; CHECK: OpSelectionMerge %[[#cond_end:]] - ; CHECK: OpBranchConditional %[[#cond]] %[[#cond_true:]] %[[#cond_false:]] - -cond.true: ; preds = %entry - %2 = load i32, ptr %b, align 4 - br label %cond.end - ; CHECK: %[[#cond_true]] = OpLabel - ; CHECK: OpBranch %[[#cond_end]] - -cond.false: ; preds = %entry - %3 = load i32, ptr %c, align 4 - br label %cond.end - ; CHECK: %[[#cond_false]] = OpLabel - ; CHECK: %[[#load_c:]] = OpLoad %[[#]] %[[#c]] - ; CHECK: OpBranch %[[#cond_end]] - -cond.end: ; preds = %cond.false, %cond.true - %cond = phi i32 [ %2, %cond.true ], [ %3, %cond.false ] - %tobool1 = icmp ne i32 %cond, 0 - br i1 %tobool1, label %if.then, label %if.end - ; CHECK: %[[#cond_end]] = OpLabel - ; CHECK: %[[#tmp:]] = OpPhi %[[#int_ty]] %[[#load_b:]] %[[#cond_true]] %[[#load_c]] %[[#cond_false]] - ; CHECK: OpSelectionMerge %[[#if_end:]] - ; CHECK: OpBranchConditional %[[#]] %[[#if_then:]] %[[#if_end]] - -if.then: ; preds = %cond.end - %4 = load i32, ptr %val, align 4 - %inc = add nsw i32 %4, 1 - store i32 %inc, ptr %val, align 4 - br label %if.end - ; CHECK: %[[#if_then]] = OpLabel - ; CHECK: OpBranch %[[#if_end]] - -if.end: ; preds = %if.then, %cond.end - %call2 = call spir_func noundef i32 @_Z2fnv() #4 [ "convergencectrl"(token %0) ] - %tobool3 = icmp ne i32 %call2, 0 - br i1 %tobool3, label %cond.true4, label %cond.false6 - ; CHECK: %[[#if_end]] = OpLabel - ; CHECK: OpSelectionMerge %[[#cond_end8:]] - ; CHECK: OpBranchConditional %[[#]] %[[#cond_true4:]] %[[#cond_false6:]] - -cond.true4: ; preds = %if.end - %call5 = call spir_func noundef i32 @_Z3fn1v() #4 [ "convergencectrl"(token %0) ] - br label %cond.end8 - ; CHECK: %[[#cond_true4]] = OpLabel - ; CHECK: OpBranch %[[#cond_end8]] - -cond.false6: ; preds = %if.end - %call7 = call spir_func noundef i32 @_Z3fn2v() #4 [ "convergencectrl"(token %0) ] - br label %cond.end8 - ; CHECK: %[[#cond_false6]] = OpLabel - ; CHECK: OpBranch %[[#cond_end8]] - -cond.end8: ; preds = %cond.false6, %cond.true4 - %cond9 = phi i32 [ %call5, %cond.true4 ], [ %call7, %cond.false6 ] - %tobool10 = icmp ne i32 %cond9, 0 - br i1 %tobool10, label %if.then11, label %if.end13 - ; CHECK: %[[#cond_end8]] = OpLabel - ; CHECK: OpSelectionMerge %[[#if_end13:]] - ; CHECK: OpBranchConditional %[[#]] %[[#if_then11:]] %[[#if_end13]] - -if.then11: ; preds = %cond.end8 - %5 = load i32, ptr %val, align 4 - %inc12 = add nsw i32 %5, 1 - store i32 %inc12, ptr %val, align 4 - br label %if.end13 - ; CHECK: %[[#if_then11]] = OpLabel - ; CHECK: OpBranch %[[#if_end13]] - -if.end13: ; preds = %if.then11, %cond.end8 - %6 = load i32, ptr %val, align 4 - ret i32 %6 - ; CHECK: %[[#if_end13]] = OpLabel - ; CHECK: OpReturnValue + %var = alloca i32 + br i1 true, label %a_true, label %a_false + +; CHECK: %[[#a_true]] = OpLabel +; CHECK: OpStore %[[#r2m_a]] %[[#true]] +; CHECK: OpBranch %[[#a_merge]] +a_true: + br label %a_merge + +; CHECK: %[[#a_false]] = OpLabel +; CHECK: OpStore %[[#r2m_a]] %[[#false]] +; CHECK: OpBranch %[[#a_merge]] +a_false: + br label %a_merge + +; CHECK: %[[#a_merge]] = OpLabel +; CHECK: %[[#tmp:]] = OpLoad %[[#]] %[[#r2m_a]] +; CHECK: OpSelectionMerge %[[#b_merge:]] +; CHECK: OpBranchConditional %[[#]] %[[#b_true:]] %[[#b_merge]] +a_merge: + %1 = phi i1 [ true, %a_true ], [ false, %a_false ] + br i1 %1, label %b_true, label %b_merge + +; CHECK: %[[#b_true]] = OpLabel +; CHECK: OpBranch %[[#b_merge]] +b_true: + store i32 0, ptr %var ; Prevents whole branch optimization. + br label %b_merge + +; CHECK: %[[#b_merge]] = OpLabel +; CHECK: OpFunctionCall +; CHECK: OpSelectionMerge %[[#c_merge:]] +; CHECK: OpBranchConditional %[[#]] %[[#c_true:]] %[[#c_false:]] +b_merge: + %f1 = call spir_func noundef i32 @_Z2fnv() #4 [ "convergencectrl"(token %0) ] + br i1 true, label %c_true, label %c_false + +; CHECK: %[[#c_true]] = OpLabel +; CHECK: %[[#]] = OpFunctionCall +; CHECK: OpStore %[[#r2m_b]] %[[#]] +; CHECK: OpBranch %[[#c_merge]] +c_true: + %f2 = call spir_func noundef i32 @_Z3fn1v() #4 [ "convergencectrl"(token %0) ] + br label %c_merge + +; CHECK: %[[#c_false]] = OpLabel +; CHECK: %[[#]] = OpFunctionCall +; CHECK: OpStore %[[#r2m_b]] %[[#]] +; CHECK: OpBranch %[[#c_merge]] +c_false: + %f3 = call spir_func noundef i32 @_Z3fn2v() #4 [ "convergencectrl"(token %0) ] + br label %c_merge + +; CHECK: %[[#c_merge]] = OpLabel +; CHECK: %[[#tmp:]] = OpLoad %[[#]] %[[#r2m_b]] +; CHECK: OpStore %[[#r2m_c]] %[[#tmp:]] +; CHECK: OpSelectionMerge %[[#d_merge:]] +; CHECK: OpBranchConditional %[[#]] %[[#d_true:]] %[[#d_merge]] +c_merge: + %5 = phi i32 [ %f2, %c_true ], [ %f3, %c_false ] + br i1 true, label %d_true, label %d_merge + +; CHECK: %[[#d_true]] = OpLabel +; CHECK: OpBranch %[[#d_merge]] +d_true: + store i32 0, ptr %var ; Prevents whole branch optimization. + br label %d_merge + +; CHECK: %[[#d_merge]] = OpLabel +; CHECK: %[[#tmp:]] = OpLoad %[[#]] %[[#r2m_c]] +; CHECK: OpReturnValue %[[#tmp]] +d_merge: + ret i32 %5 } ; Function Attrs: convergent noinline norecurse nounwind optnone diff --git a/llvm/test/CodeGen/SPIRV/structurizer/cf.do.break.ll b/llvm/test/CodeGen/SPIRV/structurizer/cf.do.break.ll index 3fc440dc445e14..8e05bf1ebdaa7c 100644 --- a/llvm/test/CodeGen/SPIRV/structurizer/cf.do.break.ll +++ b/llvm/test/CodeGen/SPIRV/structurizer/cf.do.break.ll @@ -1,5 +1,4 @@ ; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv-unknown-vulkan-compute %s -o - -filetype=obj | spirv-val %} -; RUN: llc -mtriple=spirv-unknown-vulkan-compute -O0 %s -o - | spirv-sim --function=_Z7processv --wave=1 --expects=2 ; int foo() { return true; } ; diff --git a/llvm/test/CodeGen/SPIRV/structurizer/cf.do.continue.ll b/llvm/test/CodeGen/SPIRV/structurizer/cf.do.continue.ll index 051f0685a40426..36b61745fa55af 100644 --- a/llvm/test/CodeGen/SPIRV/structurizer/cf.do.continue.ll +++ b/llvm/test/CodeGen/SPIRV/structurizer/cf.do.continue.ll @@ -1,4 +1,3 @@ -; RUN: llc -mtriple=spirv-unknown-vulkan-compute -O0 %s -o - | spirv-sim --function=_Z7processv --wave=1 --expects=10 ; RUN: %if spirv-tools %{ llc -mtriple=spirv-unknown-vulkan-compute -O0 %s -o - | spirv-as --preserve-numeric-ids - -o - | spirv-val %} ; ; Source HLSL: diff --git a/llvm/test/CodeGen/SPIRV/structurizer/cf.do.nested.ll b/llvm/test/CodeGen/SPIRV/structurizer/cf.do.nested.ll index a28e1c7b942de0..d8e17c2291a7c6 100644 --- a/llvm/test/CodeGen/SPIRV/structurizer/cf.do.nested.ll +++ b/llvm/test/CodeGen/SPIRV/structurizer/cf.do.nested.ll @@ -1,5 +1,4 @@ ; RUN: %if spirv-tools %{ llc -mtriple=spirv-unknown-vulkan-compute -O0 %s -o - | spirv-as --preserve-numeric-ids - -o - | spirv-val %} -; RUN: llc -mtriple=spirv-unknown-vulkan-compute -O0 %s -o - | spirv-sim --function=_Z7processv --wave=1 --expects=142 ; ; Source HLSL: ; diff --git a/llvm/test/CodeGen/SPIRV/structurizer/cf.for.break.ll b/llvm/test/CodeGen/SPIRV/structurizer/cf.for.break.ll index f2e60f916c795b..9d8cab44c0cbb5 100644 --- a/llvm/test/CodeGen/SPIRV/structurizer/cf.for.break.ll +++ b/llvm/test/CodeGen/SPIRV/structurizer/cf.for.break.ll @@ -1,5 +1,4 @@ ; RUN: %if spirv-tools %{ llc -mtriple=spirv-unknown-vulkan-compute -O0 %s -o - | spirv-as --preserve-numeric-ids - -o - | spirv-val %} -; RUN: llc -mtriple=spirv-unknown-vulkan-compute -O0 %s -o - | spirv-sim --function=_Z7processv --wave=1 --expects=4 ; ; Source HLSL: ; diff --git a/llvm/test/CodeGen/SPIRV/structurizer/cf.for.continue.ll b/llvm/test/CodeGen/SPIRV/structurizer/cf.for.continue.ll index 31a3433cae4c07..12e6473c15c757 100644 --- a/llvm/test/CodeGen/SPIRV/structurizer/cf.for.continue.ll +++ b/llvm/test/CodeGen/SPIRV/structurizer/cf.for.continue.ll @@ -1,6 +1,5 @@ ; RUN: llc -mtriple=spirv-unknown-vulkan-compute -O0 %s -o - | FileCheck %s ; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv-unknown-vulkan-compute %s -o - -filetype=obj | spirv-val %} -; RUN: llc -mtriple=spirv-unknown-vulkan-compute -O0 %s -o - | spirv-sim --function=_Z7processv --wave=1 --expects=19 ; ; int process() { diff --git a/llvm/test/CodeGen/SPIRV/structurizer/cf.for.nested.ll b/llvm/test/CodeGen/SPIRV/structurizer/cf.for.nested.ll index 1619a519273b37..ddd4c5222301a3 100644 --- a/llvm/test/CodeGen/SPIRV/structurizer/cf.for.nested.ll +++ b/llvm/test/CodeGen/SPIRV/structurizer/cf.for.nested.ll @@ -1,6 +1,5 @@ ; RUN: llc -mtriple=spirv-unknown-vulkan-compute -O0 %s -o - | FileCheck %s ; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv-unknown-vulkan-compute %s -o - -filetype=obj | spirv-val %} -; RUN: llc -mtriple=spirv-unknown-vulkan-compute -O0 %s -o - | spirv-sim --function=_Z7processv --wave=1 --expects=2563170 ; ; int process() { diff --git a/llvm/test/CodeGen/SPIRV/structurizer/cf.for.short-circuited-cond.ll b/llvm/test/CodeGen/SPIRV/structurizer/cf.for.short-circuited-cond.ll index 1b5e868317fba5..07c20ebadd159e 100644 --- a/llvm/test/CodeGen/SPIRV/structurizer/cf.for.short-circuited-cond.ll +++ b/llvm/test/CodeGen/SPIRV/structurizer/cf.for.short-circuited-cond.ll @@ -1,6 +1,5 @@ ; RUN: llc -mtriple=spirv-unknown-vulkan-compute -O0 %s -o - | FileCheck %s ; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv-unknown-vulkan-compute %s -o - -filetype=obj | spirv-val %} -; RUN: llc -mtriple=spirv-unknown-vulkan-compute -O0 %s -o - | spirv-sim --function=_Z7processv --wave=1 --expects=9 ; ; int process() { @@ -139,10 +138,10 @@ ; CHECK: OpBranchConditional %[[#]] %[[#bb130:]] %[[#bb125:]] ; CHECK: %[[#bb130:]] = OpLabel ; CHECK: OpBranch %[[#bb126:]] -; CHECK: %[[#bb125:]] = OpLabel -; CHECK: OpReturnValue %[[#]] ; CHECK: %[[#bb126:]] = OpLabel ; CHECK: OpBranch %[[#bb124:]] +; CHECK: %[[#bb125:]] = OpLabel +; CHECK: OpReturnValue %[[#]] ; CHECK: OpFunctionEnd ; CHECK: %[[#func_83:]] = OpFunction %[[#void:]] DontInline %[[#]] ; CHECK: %[[#bb131:]] = OpLabel diff --git a/llvm/test/CodeGen/SPIRV/structurizer/cf.if.const-cond.ll b/llvm/test/CodeGen/SPIRV/structurizer/cf.if.const-cond.ll index f3a9109b06ee2e..df406917fdff97 100644 --- a/llvm/test/CodeGen/SPIRV/structurizer/cf.if.const-cond.ll +++ b/llvm/test/CodeGen/SPIRV/structurizer/cf.if.const-cond.ll @@ -1,6 +1,5 @@ ; RUN: llc -mtriple=spirv-unknown-vulkan-compute -O0 %s -o - | FileCheck %s ; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv-unknown-vulkan-compute %s -o - -filetype=obj | spirv-val %} -; RUN: llc -mtriple=spirv-unknown-vulkan-compute -O0 %s -o - | spirv-sim --function=_Z7processv --wave=1 --expects=3 ; ; int process() { diff --git a/llvm/test/CodeGen/SPIRV/structurizer/cf.if.for.ll b/llvm/test/CodeGen/SPIRV/structurizer/cf.if.for.ll index 42c885070453ac..93effc141fc812 100644 --- a/llvm/test/CodeGen/SPIRV/structurizer/cf.if.for.ll +++ b/llvm/test/CodeGen/SPIRV/structurizer/cf.if.for.ll @@ -1,6 +1,5 @@ ; RUN: llc -mtriple=spirv-unknown-vulkan-compute -O0 %s -o - | FileCheck %s ; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv-unknown-vulkan-compute %s -o - -filetype=obj | spirv-val %} -; RUN: llc -mtriple=spirv-unknown-vulkan-compute -O0 %s -o - | spirv-sim --function=_Z7processv --wave=1 --expects=6 ; ; int process() { diff --git a/llvm/test/CodeGen/SPIRV/structurizer/cf.if.nested.ll b/llvm/test/CodeGen/SPIRV/structurizer/cf.if.nested.ll index 1fea1ebd888f5c..a69475a59db6f4 100644 --- a/llvm/test/CodeGen/SPIRV/structurizer/cf.if.nested.ll +++ b/llvm/test/CodeGen/SPIRV/structurizer/cf.if.nested.ll @@ -1,6 +1,5 @@ ; RUN: llc -mtriple=spirv-unknown-vulkan-compute -O0 %s -o - | FileCheck %s ; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv-unknown-vulkan-compute %s -o - -filetype=obj | spirv-val %} -; RUN: llc -mtriple=spirv-unknown-vulkan-compute -O0 %s -o - | spirv-sim --function=_Z7processv --wave=1 --expects=3 ; diff --git a/llvm/test/CodeGen/SPIRV/structurizer/cf.if.plain.ll b/llvm/test/CodeGen/SPIRV/structurizer/cf.if.plain.ll index c3b0caa4e26947..8fa8c2c14878bf 100644 --- a/llvm/test/CodeGen/SPIRV/structurizer/cf.if.plain.ll +++ b/llvm/test/CodeGen/SPIRV/structurizer/cf.if.plain.ll @@ -1,6 +1,5 @@ ; RUN: llc -mtriple=spirv-unknown-vulkan-compute -O0 %s -o - | FileCheck %s ; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv-unknown-vulkan-compute %s -o - -filetype=obj | spirv-val %} -; RUN: llc -mtriple=spirv-unknown-vulkan-compute -O0 %s -o - | spirv-sim --function=_Z7processv --wave=1 --expects=2 ; ; int process() { diff --git a/llvm/test/CodeGen/SPIRV/structurizer/cf.logical-and.ll b/llvm/test/CodeGen/SPIRV/structurizer/cf.logical-and.ll index a5f00071ca2712..9d35fb3c82b077 100644 --- a/llvm/test/CodeGen/SPIRV/structurizer/cf.logical-and.ll +++ b/llvm/test/CodeGen/SPIRV/structurizer/cf.logical-and.ll @@ -1,6 +1,5 @@ ; RUN: llc -mtriple=spirv-unknown-vulkan-compute -O0 %s -o - | FileCheck %s ; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv-unknown-vulkan-compute %s -o - -filetype=obj | spirv-val %} -; RUN: llc -mtriple=spirv-unknown-vulkan-compute -O0 %s -o - | spirv-sim --function=_Z7processv --wave=1 --expects=1 ; ; int fn() { return true; } diff --git a/llvm/test/CodeGen/SPIRV/structurizer/cf.logical-or.ll b/llvm/test/CodeGen/SPIRV/structurizer/cf.logical-or.ll index 73db1c897711fa..0a986661e50d5b 100644 --- a/llvm/test/CodeGen/SPIRV/structurizer/cf.logical-or.ll +++ b/llvm/test/CodeGen/SPIRV/structurizer/cf.logical-or.ll @@ -1,6 +1,5 @@ ; RUN: llc -mtriple=spirv-unknown-vulkan-compute -O0 %s -o - | FileCheck %s ; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv-unknown-vulkan-compute %s -o - -filetype=obj | spirv-val %} -; RUN: llc -mtriple=spirv-unknown-vulkan-compute -O0 %s -o - | spirv-sim --function=_Z7processv --wave=1 --expects=3 ; ; int fn() { return true; } diff --git a/llvm/test/CodeGen/SPIRV/structurizer/cf.return.early.ll b/llvm/test/CodeGen/SPIRV/structurizer/cf.return.early.ll index 62d18cdf538c37..dfaca85be2280c 100644 --- a/llvm/test/CodeGen/SPIRV/structurizer/cf.return.early.ll +++ b/llvm/test/CodeGen/SPIRV/structurizer/cf.return.early.ll @@ -1,6 +1,5 @@ ; RUN: llc -mtriple=spirv-unknown-vulkan-compute -O0 %s -o - | FileCheck %s ; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv-unknown-vulkan-compute %s -o - -filetype=obj | spirv-val %} -; RUN: llc -mtriple=spirv-unknown-vulkan-compute -O0 %s -o - | spirv-sim --function=_Z7processv --wave=1 --expects=0 ; ; int process() { diff --git a/llvm/test/CodeGen/SPIRV/structurizer/cf.switch.ifstmt.ll b/llvm/test/CodeGen/SPIRV/structurizer/cf.switch.ifstmt.ll index d2447fe4562435..8e2a0506d286d6 100644 --- a/llvm/test/CodeGen/SPIRV/structurizer/cf.switch.ifstmt.ll +++ b/llvm/test/CodeGen/SPIRV/structurizer/cf.switch.ifstmt.ll @@ -1,6 +1,5 @@ ; RUN: llc -mtriple=spirv-unknown-vulkan-compute -O0 %s -o - | FileCheck %s ; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv-unknown-vulkan-compute %s -o - -filetype=obj | spirv-val %} -; RUN: llc -mtriple=spirv-unknown-vulkan-compute -O0 %s -o - | spirv-sim --function=_Z7processv --wave=1 --expects=308 ; ; int foo() { return 200; } diff --git a/llvm/test/CodeGen/SPIRV/structurizer/cf.switch.ifstmt.simple.ll b/llvm/test/CodeGen/SPIRV/structurizer/cf.switch.ifstmt.simple.ll index 74c5a2edf7c2fb..125e3f751315eb 100644 --- a/llvm/test/CodeGen/SPIRV/structurizer/cf.switch.ifstmt.simple.ll +++ b/llvm/test/CodeGen/SPIRV/structurizer/cf.switch.ifstmt.simple.ll @@ -1,6 +1,5 @@ ; RUN: llc -mtriple=spirv-unknown-vulkan-compute -O0 %s -o - | FileCheck %s ; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv-unknown-vulkan-compute %s -o - -filetype=obj | spirv-val %} -; RUN: llc -mtriple=spirv-unknown-vulkan-compute -O0 %s -o - | spirv-sim --function=_Z7processv --wave=1 --expects=5 ; ; int process() { diff --git a/llvm/test/CodeGen/SPIRV/structurizer/cf.switch.ifstmt.simple2.ll b/llvm/test/CodeGen/SPIRV/structurizer/cf.switch.ifstmt.simple2.ll index bfe3b45779afb6..cf50b982b23dc8 100644 --- a/llvm/test/CodeGen/SPIRV/structurizer/cf.switch.ifstmt.simple2.ll +++ b/llvm/test/CodeGen/SPIRV/structurizer/cf.switch.ifstmt.simple2.ll @@ -1,6 +1,5 @@ ; RUN: llc -mtriple=spirv-unknown-vulkan-compute -O0 %s -o - | FileCheck %s ; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv-unknown-vulkan-compute %s -o - -filetype=obj | spirv-val %} -; RUN: llc -mtriple=spirv-unknown-vulkan-compute -O0 %s -o - | spirv-sim --function=_Z7processv --wave=1 --expects=5 ; ; int foo() { return 200; } diff --git a/llvm/test/CodeGen/SPIRV/structurizer/cf.while.break.ll b/llvm/test/CodeGen/SPIRV/structurizer/cf.while.break.ll index 8f3981a2449682..769be32c9fc41e 100644 --- a/llvm/test/CodeGen/SPIRV/structurizer/cf.while.break.ll +++ b/llvm/test/CodeGen/SPIRV/structurizer/cf.while.break.ll @@ -41,47 +41,45 @@ ; } ; CHECK: %[[#func_16:]] = OpFunction %[[#uint:]] DontInline %[[#]] -; CHECK: %[[#bb37:]] = OpLabel +; CHECK: %[[#bb44:]] = OpLabel ; CHECK: OpReturnValue %[[#]] ; CHECK: OpFunctionEnd -; CHECK: %[[#func_17:]] = OpFunction %[[#void:]] DontInline %[[#]] -; CHECK: %[[#bb38:]] = OpLabel -; CHECK: OpBranch %[[#bb39:]] -; CHECK: %[[#bb39:]] = OpLabel -; CHECK: OpLoopMerge %[[#bb40:]] %[[#bb41:]] None -; CHECK: OpBranchConditional %[[#]] %[[#bb42:]] %[[#bb40:]] -; CHECK: %[[#bb42:]] = OpLabel -; CHECK: OpBranchConditional %[[#]] %[[#bb40:]] %[[#bb43:]] -; CHECK: %[[#bb43:]] = OpLabel -; CHECK: OpBranchConditional %[[#]] %[[#bb40:]] %[[#bb41:]] -; CHECK: %[[#bb40:]] = OpLabel -; CHECK: OpSelectionMerge %[[#bb44:]] None -; CHECK: OpSwitch %[[#]] %[[#bb44:]] 1 %[[#bb44:]] 2 %[[#bb44:]] -; CHECK: %[[#bb41:]] = OpLabel -; CHECK: OpBranch %[[#bb39:]] -; CHECK: %[[#bb44:]] = OpLabel -; CHECK: OpBranch %[[#bb45:]] +; CHECK: %[[#func_19:]] = OpFunction %[[#void:]] DontInline %[[#]] ; CHECK: %[[#bb45:]] = OpLabel ; CHECK: OpBranch %[[#bb46:]] ; CHECK: %[[#bb46:]] = OpLabel -; CHECK: OpBranch %[[#bb47:]] -; CHECK: %[[#bb47:]] = OpLabel -; CHECK: OpSelectionMerge %[[#bb48:]] None -; CHECK: OpBranchConditional %[[#]] %[[#bb49:]] %[[#bb48:]] +; CHECK: OpLoopMerge %[[#bb47:]] %[[#bb48:]] None +; CHECK: OpBranchConditional %[[#]] %[[#bb49:]] %[[#bb47:]] ; CHECK: %[[#bb49:]] = OpLabel -; CHECK: OpBranch %[[#bb48:]] -; CHECK: %[[#bb48:]] = OpLabel -; CHECK: OpBranch %[[#bb50:]] +; CHECK: OpBranchConditional %[[#]] %[[#bb47:]] %[[#bb50:]] ; CHECK: %[[#bb50:]] = OpLabel +; CHECK: OpBranchConditional %[[#]] %[[#bb47:]] %[[#bb48:]] +; CHECK: %[[#bb48:]] = OpLabel +; CHECK: OpBranch %[[#bb46:]] +; CHECK: %[[#bb47:]] = OpLabel +; CHECK: OpSelectionMerge %[[#bb51:]] None +; CHECK: OpSwitch %[[#]] %[[#bb51:]] 1 %[[#bb51:]] 2 %[[#bb51:]] +; CHECK: %[[#bb51:]] = OpLabel +; CHECK: OpBranch %[[#bb52:]] +; CHECK: %[[#bb52:]] = OpLabel +; CHECK: OpBranch %[[#bb53:]] +; CHECK: %[[#bb53:]] = OpLabel +; CHECK: OpBranch %[[#bb54:]] +; CHECK: %[[#bb54:]] = OpLabel +; CHECK: OpSelectionMerge %[[#bb55:]] None +; CHECK: OpBranchConditional %[[#]] %[[#bb56:]] %[[#bb55:]] +; CHECK: %[[#bb56:]] = OpLabel +; CHECK: OpBranch %[[#bb55:]] +; CHECK: %[[#bb55:]] = OpLabel +; CHECK: OpBranch %[[#bb57:]] +; CHECK: %[[#bb57:]] = OpLabel ; CHECK: OpReturn ; CHECK: OpFunctionEnd -; CHECK: %[[#func_35:]] = OpFunction %[[#void:]] None %[[#]] -; CHECK: %[[#bb51:]] = OpLabel +; CHECK: %[[#func_40:]] = OpFunction %[[#void:]] None %[[#]] +; CHECK: %[[#bb58:]] = OpLabel ; CHECK: OpReturn ; CHECK: OpFunctionEnd - - target datalayout = "e-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128-v192:256-v256:256-v512:512-v1024:1024-G1" target triple = "spirv-unknown-vulkan1.3-compute" diff --git a/llvm/test/CodeGen/SPIRV/structurizer/condition-linear.ll b/llvm/test/CodeGen/SPIRV/structurizer/condition-linear.ll index faab2553ae6f51..71f3ce9263da56 100644 --- a/llvm/test/CodeGen/SPIRV/structurizer/condition-linear.ll +++ b/llvm/test/CodeGen/SPIRV/structurizer/condition-linear.ll @@ -1,5 +1,5 @@ +; RUN: llc -mtriple=spirv-unknown-vulkan-compute -O0 %s -o - | FileCheck %s ; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv-unknown-vulkan-compute %s -o - -filetype=obj | spirv-val %} -; RUN: llc -mtriple=spirv-unknown-vulkan-compute -O0 %s -o - | FileCheck %s --match-full-lines target datalayout = "e-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128-v192:256-v256:256-v512:512-v1024:1024-G1" target triple = "spirv-unknown-vulkan-compute" @@ -25,90 +25,92 @@ entry: ret i32 1 } + +; CHECK-DAG: OpName %[[#reg_0:]] "cond.reg2mem" +; CHECK-DAG: OpName %[[#reg_1:]] "cond9.reg2mem" + define internal spir_func void @main() #0 { -; CHECK: %[[#cond:]] = OpINotEqual %[[#bool_ty:]] %[[#a:]] %[[#b:]] -; CHECK: OpSelectionMerge %[[#cond_end:]] None -; CHECK: OpBranchConditional %[[#cond]] %[[#cond_true:]] %[[#cond_false:]] +; CHECK: OpSelectionMerge %[[#cond1_merge:]] None +; CHECK: OpBranchConditional %[[#]] %[[#cond1_true:]] %[[#cond1_false:]] entry: %0 = call token @llvm.experimental.convergence.entry() %a = alloca i32, align 4 %b = alloca i32, align 4 - %c = alloca i32, align 4 - %val = alloca i32, align 4 - store i32 0, ptr %val, align 4 - %1 = load i32, ptr %a, align 4 - %tobool = icmp ne i32 %1, 0 - br i1 %tobool, label %cond.true, label %cond.false - -; CHECK: %[[#cond_true]] = OpLabel -; CHECK: OpBranch %[[#cond_end]] -cond.true: - %2 = load i32, ptr %b, align 4 - br label %cond.end - -; CHECK: %[[#cond_false]] = OpLabel -; CHECK: OpBranch %[[#cond_end]] -cond.false: - %3 = load i32, ptr %c, align 4 - br label %cond.end - -; CHECK: %[[#cond_end]] = OpLabel -; CHECK: %[[#tmp:]] = OpPhi %[[#int_ty:]] %[[#load_cond_true:]] %[[#cond_true]] %[[#load_cond_false:]] %[[#cond_false:]] -; CHECK: %[[#cond:]] = OpINotEqual %[[#bool_ty]] %[[#tmp]] %[[#int_0:]] -; CHECK: OpSelectionMerge %[[#if_end:]] None -; CHECK: OpBranchConditional %[[#cond]] %[[#if_then:]] %[[#if_end]] -cond.end: - %cond = phi i32 [ %2, %cond.true ], [ %3, %cond.false ] + br i1 true, label %cond1_true, label %cond1_false + +; CHECK: %[[#cond1_true]] = OpLabel +; CHECK: OpStore %[[#reg_0]] %[[#]] +; CHECK: OpBranch %[[#cond1_merge]] +cond1_true: + %2 = load i32, ptr %a, align 4 + br label %cond1_merge + +; CHECK: %[[#cond1_false]] = OpLabel +; CHECK: OpStore %[[#reg_0]] %[[#]] +; CHECK: OpBranch %[[#cond1_merge]] +cond1_false: + %3 = load i32, ptr %b, align 4 + br label %cond1_merge + +; CHECK: %[[#cond1_merge]] = OpLabel +; CHECK: %[[#tmp:]] = OpLoad %[[#]] %[[#reg_0]] +; CHECK: %[[#cond:]] = OpINotEqual %[[#]] %[[#tmp]] %[[#]] +; CHECK: OpSelectionMerge %[[#cond2_merge:]] None +; CHECK: OpBranchConditional %[[#cond]] %[[#cond2_true:]] %[[#cond2_merge]] +cond1_merge: + %cond = phi i32 [ %2, %cond1_true ], [ %3, %cond1_false ] %tobool1 = icmp ne i32 %cond, 0 - br i1 %tobool1, label %if.then, label %if.end - -; CHECK: %[[#if_then]] = OpLabel -; CHECK: OpBranch %[[#if_end]] -if.then: - %4 = load i32, ptr %val, align 4 - %inc = add nsw i32 %4, 1 - store i32 %inc, ptr %val, align 4 - br label %if.end - -; CHECK: %[[#if_end]] = OpLabel -; CHECK: OpSelectionMerge %[[#cond_end8:]] None -; CHECK: OpBranchConditional %[[#tmp:]] %[[#cond4_true:]] %[[#cond_false6:]] -if.end: + br i1 %tobool1, label %cond2_true, label %cond2_merge + +; CHECK: %[[#cond2_true]] = OpLabel +; CHECK: OpBranch %[[#cond2_merge]] +cond2_true: + store i32 0, ptr %a + br label %cond2_merge + +; CHECK: %[[#cond2_merge]] = OpLabel +; CHECK: OpFunctionCall +; CHECK: OpSelectionMerge %[[#cond3_merge:]] None +; CHECK: OpBranchConditional %[[#]] %[[#cond3_true:]] %[[#cond3_false:]] +cond2_merge: %call2 = call spir_func noundef i32 @fn() #4 [ "convergencectrl"(token %0) ] - %tobool3 = icmp ne i32 %call2, 0 - br i1 %tobool3, label %cond.true4, label %cond.false6 + br i1 true, label %cond3_true, label %cond3_false -; CHECK: %[[#cond4_true]] = OpLabel -; CHECK: OpBranch %[[#cond_end8]] -cond.true4: +; CHECK: %[[#cond3_true]] = OpLabel +; CHECK: OpFunctionCall +; CHECK: OpStore %[[#reg_1]] %[[#]] +; CHECK: OpBranch %[[#cond3_merge]] +cond3_true: %call5 = call spir_func noundef i32 @fn1() #4 [ "convergencectrl"(token %0) ] - br label %cond.end8 + br label %cond3_merge -; CHECK: %[[#cond_false6]] = OpLabel -; CHECK: OpBranch %[[#cond_end8]] -cond.false6: +; CHECK: %[[#cond3_false]] = OpLabel +; CHECK: OpFunctionCall +; CHECK: OpStore %[[#reg_1]] %[[#]] +; CHECK: OpBranch %[[#cond3_merge]] +cond3_false: %call7 = call spir_func noundef i32 @fn2() #4 [ "convergencectrl"(token %0) ] - br label %cond.end8 - -; CHECK: %[[#cond_end8]] = OpLabel -; CHECK: OpSelectionMerge %[[#if_end13:]] None -; CHECK: OpBranchConditional %[[#tmp:]] %[[#if_then11:]] %[[#if_end13]] -cond.end8: - %cond9 = phi i32 [ %call5, %cond.true4 ], [ %call7, %cond.false6 ] + br label %cond3_merge + +; CHECK: %[[#cond3_merge]] = OpLabel +; CHECK: %[[#tmp:]] = OpLoad %[[#]] %[[#reg_1]] +; CHECK: %[[#cond:]] = OpINotEqual %[[#]] %[[#tmp]] %[[#]] +; CHECK: OpSelectionMerge %[[#cond4_merge:]] None +; CHECK: OpBranchConditional %[[#cond]] %[[#cond4_true:]] %[[#cond4_merge]] +cond3_merge: + %cond9 = phi i32 [ %call5, %cond3_true ], [ %call7, %cond3_false ] %tobool10 = icmp ne i32 %cond9, 0 - br i1 %tobool10, label %if.then11, label %if.end13 + br i1 %tobool10, label %cond4_true, label %cond4_merge -; CHECK: %[[#if_then11]] = OpLabel -; CHECK: OpBranch %[[#if_end13]] -if.then11: - %5 = load i32, ptr %val, align 4 - %inc12 = add nsw i32 %5, 1 - store i32 %inc12, ptr %val, align 4 - br label %if.end13 +; CHECK: %[[#cond4_true]] = OpLabel +; CHECK: OpBranch %[[#cond4_merge]] +cond4_true: + store i32 0, ptr %a + br label %cond4_merge -; CHECK: %[[#if_end13]] = OpLabel +; CHECK: %[[#cond4_merge]] = OpLabel ; CHECK: OpReturn -if.end13: +cond4_merge: ret void } diff --git a/llvm/test/CodeGen/SPIRV/structurizer/do-continue.ll b/llvm/test/CodeGen/SPIRV/structurizer/do-continue.ll index d547ad8eded976..05071d03164d5f 100644 --- a/llvm/test/CodeGen/SPIRV/structurizer/do-continue.ll +++ b/llvm/test/CodeGen/SPIRV/structurizer/do-continue.ll @@ -1,5 +1,5 @@ -; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv-unknown-vulkan-compute %s -o - -filetype=obj | spirv-val %} ; RUN: llc -mtriple=spirv-unknown-vulkan-compute -O0 %s -o - | FileCheck %s --match-full-lines +; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv-unknown-vulkan-compute %s -o - -filetype=obj | spirv-val %} target datalayout = "e-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128-v192:256-v256:256-v512:512-v1024:1024-G1" target triple = "spirv-unknown-vulkan1.3-compute" @@ -12,100 +12,98 @@ entry: define internal spir_func void @main() #2 { ; CHECK: %[[#entry:]] = OpLabel -; CHECK: OpBranch %[[#do_body:]] +; CHECK: OpBranch %[[#do_header:]] entry: %0 = call token @llvm.experimental.convergence.entry() - %val = alloca i32, align 4 - %i = alloca i32, align 4 - store i32 0, ptr %val, align 4 - store i32 0, ptr %i, align 4 - br label %do.body + %var = alloca i32, align 4 + br label %do_header +; Here a the loop header had to be split in two: +; - 1 header for the loop +; - 1 header for the condition. +; In SPIR-V, a loop header cannot directly ; CHECK: %[[#do_header:]] = OpLabel -; CHECK: OpLoopMerge %[[#do_end:]] %[[#do_cond:]] None -; CHECK: OpBranch %[[#do_body:]] +; CHECK: OpLoopMerge %[[#do_merge:]] %[[#do_latch:]] None +; CHECK: OpBranch %[[#new_header:]] -; CHECK: %[[#do_body]] = OpLabel -; CHECK: OpSelectionMerge %[[#if_then:]] None -; CHECK: OpBranchConditional %[[#cond:]] %[[#if_then]] %[[#if_end:]] -do.body: +; CHECK: %[[#new_header]] = OpLabel +; CHECK: OpSelectionMerge %[[#if_merge:]] None +; CHECK: OpBranchConditional %[[#]] %[[#if_then:]] %[[#if_end:]] +do_header: %1 = call token @llvm.experimental.convergence.loop() [ "convergencectrl"(token %0) ] - %2 = load i32, ptr %i, align 4 - %inc = add nsw i32 %2, 1 - store i32 %inc, ptr %i, align 4 - %3 = load i32, ptr %i, align 4 - %cmp = icmp sgt i32 %3, 5 - br i1 %cmp, label %if.then, label %if.end + store i32 0, ptr %var + br i1 true, label %if.then, label %if.end + +; CHECK: %[[#if_then]] = OpLabel +; CHECK: OpBranch %[[#if_merge]] +if.then: + store i32 0, ptr %var + br label %do_latch ; CHECK: %[[#if_end]] = OpLabel -; CHECK: OpBranch %[[#if_then]] +; CHECK: OpBranch %[[#if_merge]] if.end: - %4 = load i32, ptr %i, align 4 - store i32 %4, ptr %val, align 4 - br label %do.cond + store i32 0, ptr %var + br label %do_latch -; CHECK: %[[#if_then]] = OpLabel -; CHECK: OpBranch %[[#do_cond]] -if.then: - br label %do.cond +; CHECK: %[[#if_merge]] = OpLabel +; CHECK: OpBranchConditional %[[#]] %[[#do_latch]] %[[#do_merge]] -; CHECK: %[[#do_cond]] = OpLabel -; CHECK: OpBranchConditional %[[#cond:]] %[[#do_header]] %[[#do_end]] -do.cond: - %5 = load i32, ptr %i, align 4 - %cmp1 = icmp slt i32 %5, 10 - br i1 %cmp1, label %do.body, label %do.end +; CHECK: %[[#do_latch]] = OpLabel +; CHECK: OpBranch %[[#do_header]] +do_latch: + store i32 0, ptr %var + br i1 true, label %do_header, label %do.end -; CHECK: %[[#do_end]] = OpLabel -; CHECK: OpBranch %[[#do_body2:]] +; CHECK: %[[#do_merge]] = OpLabel +; CHECK: OpBranch %[[#do2_header:]] do.end: - br label %do.body2 + store i32 0, ptr %var + br label %do2_header -; CHECK: %[[#do_body2]] = OpLabel -; CHECK: OpLoopMerge %[[#do_end11:]] %[[#do_cond9:]] None -; CHECK: OpBranch %[[#do_body4:]] -do.body2: +; CHECK: %[[#do2_header]] = OpLabel +; CHECK: OpLoopMerge %[[#do2_merge:]] %[[#do2_continue:]] None +; CHECK: OpBranch %[[#do3_header:]] +do2_header: %6 = call token @llvm.experimental.convergence.loop() [ "convergencectrl"(token %0) ] - %7 = load i32, ptr %i, align 4 - %inc3 = add nsw i32 %7, 1 - store i32 %inc3, ptr %i, align 4 - br label %do.body4 - -; CHECK: %[[#do_body4]] = OpLabel -; CHECK: OpLoopMerge %[[#do_end8:]] %[[#do_cond6:]] None -; CHECK: OpBranch %[[#do_cond6]] -do.body4: + store i32 0, ptr %var + br label %do3_header + +; CHECK: %[[#do3_header]] = OpLabel +; CHECK: OpLoopMerge %[[#do3_merge:]] %[[#do3_continue:]] None +; CHECK: OpBranch %[[#do3_body:]] +do3_header: %8 = call token @llvm.experimental.convergence.loop() [ "convergencectrl"(token %6) ] - %9 = load i32, ptr %val, align 4 - %inc5 = add nsw i32 %9, 1 - store i32 %inc5, ptr %val, align 4 - br label %do.cond6 - -; CHECK: %[[#do_cond6]] = OpLabel -; CHECK: OpBranchConditional %[[#cond:]] %[[#do_body4]] %[[#do_end8]] -do.cond6: - %10 = load i32, ptr %i, align 4 - %cmp7 = icmp slt i32 %10, 10 - br i1 %cmp7, label %do.body4, label %do.end8 - -; CHECK: %[[#do_end8]] = OpLabel -; CHECK: OpBranch %[[#do_cond9]] -do.end8: - %11 = load i32, ptr %i, align 4 - %dec = add nsw i32 %11, -1 - store i32 %dec, ptr %i, align 4 - br label %do.cond9 - -; CHECK: %[[#do_cond9]] = OpLabel -; CHECK: OpBranchConditional %[[#cond:]] %[[#do_body2]] %[[#do_end11]] -do.cond9: - %12 = load i32, ptr %val, align 4 - %cmp10 = icmp slt i32 %12, 10 - br i1 %cmp10, label %do.body2, label %do.end11 - -; CHECK: %[[#do_end11]] = OpLabel -; CHECK: OpReturn -do.end11: + store i32 0, ptr %var + br label %do3_continue + +; CHECK: %[[#do3_body]] = OpLabel +; CHECK: OpBranchConditional %[[#]] %[[#do3_continue]] %[[#do3_merge]] + +; CHECK: %[[#do3_continue]] = OpLabel +; CHECK: OpBranch %[[#do3_header]] +do3_continue: + store i32 0, ptr %var + br i1 true, label %do3_header, label %do3_merge + +; CHECK: %[[#do3_merge]] = OpLabel +; CHECK: OpBranch %[[#do2_new_latch:]] +do3_merge: + store i32 0, ptr %var + br label %do2_continue + +; CHECK: %[[#do2_new_latch]] = OpLabel +; CHECK: OpBranchConditional %[[#]] %[[#do2_continue]] %[[#do2_merge]] + +; CHECK: %[[#do2_continue]] = OpLabel +; CHECK: OpBranch %[[#do2_header]] +do2_continue: + store i32 0, ptr %var + br i1 true, label %do2_header, label %do2_merge + +; CHECK: %[[#do2_merge]] = OpLabel +; CHECK: OpReturn +do2_merge: ret void } diff --git a/llvm/test/CodeGen/SPIRV/structurizer/do-nested.ll b/llvm/test/CodeGen/SPIRV/structurizer/do-nested.ll index a16eed5cdfb4ce..bef95f5f63bf7b 100644 --- a/llvm/test/CodeGen/SPIRV/structurizer/do-nested.ll +++ b/llvm/test/CodeGen/SPIRV/structurizer/do-nested.ll @@ -1,5 +1,5 @@ -; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv-unknown-vulkan-compute %s -o - -filetype=obj | spirv-val %} ; RUN: llc -mtriple=spirv-unknown-vulkan-compute -O0 %s -o - | FileCheck %s --match-full-lines +; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv-unknown-vulkan-compute %s -o - -filetype=obj | spirv-val %} target datalayout = "e-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128-v192:256-v256:256-v512:512-v1024:1024-G1" target triple = "spirv-unknown-vulkan1.3-compute" @@ -8,84 +8,72 @@ define internal spir_func void @main() #0 { ; CHECK: %[[#entry:]] = OpLabel entry: %0 = call token @llvm.experimental.convergence.entry() - %val = alloca i32, align 4 - %i = alloca i32, align 4 - %j = alloca i32, align 4 - %k = alloca i32, align 4 - store i32 0, ptr %val, align 4 - store i32 0, ptr %i, align 4 - store i32 0, ptr %j, align 4 - store i32 0, ptr %k, align 4 - br label %do.body + %var = alloca i32, align 4 + br label %do1_header -; CHECK: %[[#do_1_header:]] = OpLabel -; CHECK: OpLoopMerge %[[#end:]] %[[#do_1_latch:]] None -; CHECK: OpBranch %[[#do_2_header:]] -do.body: +; CHECK: %[[#do1_header:]] = OpLabel +; CHECK: OpLoopMerge %[[#do1_merge:]] %[[#do1_continue:]] None +; CHECK: OpBranch %[[#do2_header:]] +do1_header: %1 = call token @llvm.experimental.convergence.loop() [ "convergencectrl"(token %0) ] - %2 = load i32, ptr %val, align 4 - %3 = load i32, ptr %i, align 4 - %add = add nsw i32 %2, %3 - store i32 %add, ptr %val, align 4 - br label %do.body1 + store i32 0, ptr %var + br label %do2_header -; CHECK: %[[#do_2_header]] = OpLabel -; CHECK: OpLoopMerge %[[#do_2_end:]] %[[#do_2_latch:]] None -; CHECK: OpBranch %[[#do_2_body:]] -do.body1: +; CHECK: %[[#do2_header:]] = OpLabel +; CHECK: OpLoopMerge %[[#do2_merge:]] %[[#do2_continue:]] None +; CHECK: OpBranch %[[#do3_header:]] +do2_header: %4 = call token @llvm.experimental.convergence.loop() [ "convergencectrl"(token %1) ] - br label %do.body2 + store i32 0, ptr %var + br label %do3_header -; CHECK: %[[#do_2_body]] = OpLabel -; CHECK: OpLoopMerge %[[#do_3_end:]] %[[#do_3_header:]] None -; CHECK: OpBranch %[[#do_3_header]] -do.body2: +; CHECK: %[[#do3_header:]] = OpLabel +; CHECK: OpLoopMerge %[[#do3_merge:]] %[[#do3_continue:]] None +; CHECK: OpBranch %[[#do3_cond:]] +do3_header: %5 = call token @llvm.experimental.convergence.loop() [ "convergencectrl"(token %4) ] - %6 = load i32, ptr %k, align 4 - %inc = add nsw i32 %6, 1 - store i32 %inc, ptr %k, align 4 - br label %do.cond + store i32 0, ptr %var + br label %do3_continue -; CHECK: %[[#do_3_header]] = OpLabel -; CHECK: OpBranchConditional %[[#cond:]] %[[#do_2_body]] %[[#do_3_end]] -do.cond: - %7 = load i32, ptr %k, align 4 - %cmp = icmp slt i32 %7, 30 - br i1 %cmp, label %do.body2, label %do.end +; CHECK: %[[#do3_cond]] = OpLabel +; CHECK: OpBranchConditional %[[#]] %[[#do3_continue]] %[[#do3_merge]] +; CHECK: %[[#do3_continue]] = OpLabel +; CHECK: OpBranch %[[#do3_header]] +do3_continue: + store i32 0, ptr %var + br i1 true, label %do3_header, label %do3_merge -; CHECK: %[[#do_3_end]] = OpLabel -; CHECK: OpBranch %[[#do_2_latch]] -do.end: - %8 = load i32, ptr %j, align 4 - %inc3 = add nsw i32 %8, 1 - store i32 %inc3, ptr %j, align 4 - br label %do.cond4 +; CHECK: %[[#do3_merge]] = OpLabel +; CHECK: OpBranch %[[#do2_cond:]] +do3_merge: + store i32 0, ptr %var + br label %do2_continue -; CHECK: %[[#do_2_latch]] = OpLabel -; CHECK: OpBranchConditional %[[#cond:]] %[[#do_2_header]] %[[#do_2_end]] -do.cond4: - %9 = load i32, ptr %j, align 4 - %cmp5 = icmp slt i32 %9, 20 - br i1 %cmp5, label %do.body1, label %do.end6 +; CHECK: %[[#do2_cond]] = OpLabel +; CHECK: OpBranchConditional %[[#]] %[[#do2_continue]] %[[#do2_merge]] +; CHECK: %[[#do2_continue]] = OpLabel +; CHECK: OpBranch %[[#do2_header]] +do2_continue: + store i32 0, ptr %var + br i1 true, label %do2_header, label %do2_merge -; CHECK: %[[#do_2_end]] = OpLabel -; CHECK: OpBranch %[[#do_1_latch]] -do.end6: - %10 = load i32, ptr %i, align 4 - %inc7 = add nsw i32 %10, 1 - store i32 %inc7, ptr %i, align 4 - br label %do.cond8 +; CHECK: %[[#do2_merge]] = OpLabel +; CHECK: OpBranch %[[#do1_cond:]] +do2_merge: + store i32 0, ptr %var + br label %do1_continue -; CHECK: %[[#do_1_latch]] = OpLabel -; CHECK: OpBranchConditional %[[#cond:]] %[[#do_1_header]] %[[#end]] -do.cond8: - %11 = load i32, ptr %i, align 4 - %cmp9 = icmp slt i32 %11, 10 - br i1 %cmp9, label %do.body, label %do.end10 +; CHECK: %[[#do1_cond]] = OpLabel +; CHECK: OpBranchConditional %[[#]] %[[#do1_continue]] %[[#do1_merge]] +; CHECK: %[[#do1_continue]] = OpLabel +; CHECK: OpBranch %[[#do1_header]] +do1_continue: + store i32 0, ptr %var + br i1 true, label %do1_header, label %do1_merge -; CHECK: %[[#end]] = OpLabel -; CHECK: OpReturn -do.end10: +; CHECK: %[[#do1_merge]] = OpLabel +; CHECK: OpReturn +do1_merge: ret void } diff --git a/llvm/test/CodeGen/SPIRV/structurizer/do-plain.ll b/llvm/test/CodeGen/SPIRV/structurizer/do-plain.ll index 6d4a0e591cf512..9f84fc317021f0 100644 --- a/llvm/test/CodeGen/SPIRV/structurizer/do-plain.ll +++ b/llvm/test/CodeGen/SPIRV/structurizer/do-plain.ll @@ -15,71 +15,75 @@ entry: define internal spir_func void @main() #2 { ; CHECK: %[[#entry:]] = OpLabel -; CHECK: OpBranch %[[#do_body:]] +; CHECK: OpBranch %[[#do1_header:]] entry: %0 = call token @llvm.experimental.convergence.entry() - %val = alloca i32, align 4 - %i = alloca i32, align 4 - store i32 0, ptr %val, align 4 - store i32 0, ptr %i, align 4 - br label %do.body - -; CHECK: %[[#do_body]] = OpLabel -; CHECK: OpLoopMerge %[[#do_end:]] %[[#do_cond:]] None -; CHECK: OpBranch %[[#do_cond]] -do.body: + %var = alloca i32, align 4 + br label %do1_header + +; CHECK: %[[#do1_header]] = OpLabel +; CHECK: OpLoopMerge %[[#do1_merge:]] %[[#do1_continue:]] None +; CHECK: OpBranch %[[#do1_cond:]] +do1_header: %1 = call token @llvm.experimental.convergence.loop() [ "convergencectrl"(token %0) ] - %2 = load i32, ptr %i, align 4 - store i32 %2, ptr %val, align 4 - br label %do.cond - -; CHECK: %[[#do_cond]] = OpLabel -; CHECK: OpBranchConditional %[[#cond:]] %[[#do_body]] %[[#do_end]] -do.cond: - %3 = load i32, ptr %i, align 4 - %cmp = icmp slt i32 %3, 10 - br i1 %cmp, label %do.body, label %do.end - -; CHECK: %[[#do_end]] = OpLabel -; CHECK: OpBranch %[[#do_body1:]] -do.end: - br label %do.body1 - -; CHECK: %[[#do_body1]] = OpLabel -; CHECK: OpLoopMerge %[[#do_end3:]] %[[#do_cond2:]] None -; CHECK: OpBranch %[[#do_cond2]] -do.body1: + store i32 0, ptr %var + br label %do1_continue + +; CHECK: %[[#do1_cond]] = OpLabel +; CHECK: OpBranchConditional %[[#]] %[[#do1_continue]] %[[#do1_merge]] +; CHECK: %[[#do1_continue]] = OpLabel +; CHECK: OpBranch %[[#do1_header]] +do1_continue: + store i32 0, ptr %var + br i1 true, label %do1_header, label %do1_merge + +; CHECK: %[[#do1_merge]] = OpLabel +; CHECK: OpBranch %[[#do2_header:]] +do1_merge: + store i32 0, ptr %var + br label %do2_header + +; CHECK: %[[#do2_header]] = OpLabel +; CHECK: OpLoopMerge %[[#do2_merge:]] %[[#do2_continue:]] None +; CHECK: OpBranch %[[#do2_cond:]] +do2_header: %4 = call token @llvm.experimental.convergence.loop() [ "convergencectrl"(token %0) ] - store i32 0, ptr %val, align 4 - br label %do.cond2 - -; CHECK: %[[#do_cond2]] = OpLabel -; CHECK: OpBranchConditional %[[#cond:]] %[[#do_body1]] %[[#do_end3]] -do.cond2: - br i1 true, label %do.body1, label %do.end3 - -; CHECK: %[[#do_end3]] = OpLabel -; CHECK: OpBranch %[[#do_body4:]] -do.end3: - br label %do.body4 - -; CHECK: %[[#do_body4]] = OpLabel -; CHECK: OpLoopMerge %[[#do_end7:]] %[[#do_cond5:]] None -; CHECK: OpBranch %[[#do_cond5]] -do.body4: + store i32 0, ptr %var + br label %do2_continue + +; CHECK: %[[#do2_cond]] = OpLabel +; CHECK: OpBranchConditional %[[#]] %[[#do2_continue]] %[[#do2_merge]] +; CHECK: %[[#do2_continue]] = OpLabel +; CHECK: OpBranch %[[#do2_header]] +do2_continue: + store i32 0, ptr %var + br i1 true, label %do2_header, label %do2_merge + +; CHECK: %[[#do2_merge]] = OpLabel +; CHECK: OpBranch %[[#do3_header:]] +do2_merge: + store i32 0, ptr %var + br label %do3_header + +; CHECK: %[[#do3_header]] = OpLabel +; CHECK: OpLoopMerge %[[#do3_merge:]] %[[#do3_continue:]] None +; CHECK: OpBranch %[[#do3_cond:]] +do3_header: %5 = call token @llvm.experimental.convergence.loop() [ "convergencectrl"(token %0) ] - br label %do.cond5 - -; CHECK: %[[#do_cond5]] = OpLabel -; CHECK: OpBranchConditional %[[#cond:]] %[[#do_body4]] %[[#do_end7]] -do.cond5: - %6 = load i32, ptr %val, align 4 - %cmp6 = icmp slt i32 %6, 20 - br i1 %cmp6, label %do.body4, label %do.end7 - -; CHECK: %[[#do_end7]] = OpLabel -; CHECK: OpReturn -do.end7: + store i32 0, ptr %var + br label %do3_continue + +; CHECK: %[[#do3_cond]] = OpLabel +; CHECK: OpBranchConditional %[[#]] %[[#do3_continue]] %[[#do3_merge]] +; CHECK: %[[#do3_continue]] = OpLabel +; CHECK: OpBranch %[[#do3_header]] +do3_continue: + store i32 0, ptr %var + br i1 true, label %do3_header, label %do3_merge + +; CHECK: %[[#do3_merge]] = OpLabel +; CHECK: OpReturn +do3_merge: ret void } diff --git a/llvm/test/CodeGen/SPIRV/structurizer/logical-or.ll b/llvm/test/CodeGen/SPIRV/structurizer/logical-or.ll index 26b12a1e14f0e2..235f15b0644704 100644 --- a/llvm/test/CodeGen/SPIRV/structurizer/logical-or.ll +++ b/llvm/test/CodeGen/SPIRV/structurizer/logical-or.ll @@ -1,84 +1,77 @@ +; RUN: llc -mtriple=spirv-unknown-vulkan-compute -O0 %s -o - --asm-verbose=0 | FileCheck %s ; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv-unknown-vulkan-compute %s -o - -filetype=obj | spirv-val %} -; RUN: llc -mtriple=spirv-unknown-vulkan-compute -O0 %s -o - --asm-verbose=0 | FileCheck %s --match-full-lines target datalayout = "e-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128-v192:256-v256:256-v512:512-v1024:1024-G1" target triple = "spirv-unknown-vulkan1.3-compute" -; CHECK-DAG: OpName %[[#fn:]] "fn" -; CHECK-DAG: OpName %[[#main:]] "main" -; CHECK-DAG: OpName %[[#var_a:]] "a" -; CHECK-DAG: OpName %[[#var_b:]] "b" +define internal spir_func void @main() #3 { +; CHECK-DAG: OpName %[[#switch_0:]] "reg1" +; CHECK-DAG: OpName %[[#switch_1:]] "reg" -; CHECK-DAG: %[[#bool:]] = OpTypeBool -; CHECK-DAG: %[[#true:]] = OpConstantTrue %[[#bool]] +; CHECK-DAG: %[[#int_0:]] = OpConstant %[[#]] 0 +; CHECK-DAG: %[[#int_1:]] = OpConstant %[[#]] 1 -; CHECK: %[[#fn]] = OpFunction %[[#param:]] DontInline %[[#ftype:]] -define spir_func noundef i32 @fn() #0 { -entry: - %0 = call token @llvm.experimental.convergence.entry() - ret i32 1 -} +; CHECK: %[[#entry:]] = OpLabel +; CHECK-DAG: %[[#switch_0]] = OpVariable %[[#]] Function +; CHECK-DAG: %[[#switch_1]] = OpVariable %[[#]] Function +; CHECK: OpSelectionMerge %[[#merge:]] None +; CHECK: OpBranchConditional %[[#]] %[[#new_header:]] %[[#unreachable:]] -; CHECK: %[[#main]] = OpFunction %[[#param:]] DontInline %[[#ftype:]] +; CHECK: %[[#new_header]] = OpLabel +; CHECK: OpSelectionMerge %[[#new_merge:]] None +; CHECK: OpBranchConditional %[[#]] %[[#taint_true_merge:]] %[[#br_false:]] -define internal spir_func void @main() #3 { +; CHECK: %[[#unreachable]] = OpLabel +; CHECK-NEXT: OpUnreachable -; CHECK: %[[#entry:]] = OpLabel -; CHECK-DAG: %[[#var_a]] = OpVariable %[[#type:]] Function -; CHECK-DAG: %[[#var_b]] = OpVariable %[[#type:]] Function -; CHECK: %[[#tmp:]] = OpLoad %[[#type:]] %[[#var_a]] Aligned 4 -; CHECK: %[[#cond:]] = OpINotEqual %[[#bool]] %[[#tmp]] %[[#const:]] -; CHECK: OpSelectionMerge %[[#if_end:]] None -; CHECK: OpBranchConditional %[[#true]] %[[#cond1:]] %[[#dead:]] +; CHECK: %[[#taint_true_merge]] = OpLabel +; CHECK: OpStore %[[#switch_0]] %[[#int_1]] +; CHECK: OpBranch %[[#new_merge]] -; CHECK: %[[#cond1]] = OpLabel -; CHECK: OpSelectionMerge %[[#new_exit:]] None -; CHECK: OpBranchConditional %[[#cond]] %[[#new_exit]] %[[#lor_lhs_false:]] +; CHECK: %[[#br_false]] = OpLabel +; CHECK-DAG: OpStore %[[#switch_1]] %[[#int_0]] +; CHECK: OpSelectionMerge %[[#taint_merge:]] None +; CHECK: OpBranchConditional %[[#]] %[[#taint_merge]] %[[#taint_false:]] -; CHECK: %[[#dead]] = OpLabel -; CHECK-NEXT: OpUnreachable +; CHECK: %[[#taint_false]] = OpLabel +; CHECK: OpStore %[[#switch_1]] %[[#int_1]] +; CHECK: OpBranch %[[#taint_merge]] -; CHECK: %[[#lor_lhs_false]] = OpLabel -; CHECK: %[[#tmp:]] = OpLoad %[[#type:]] %[[#var_b]] Aligned 4 -; CHECK: %[[#cond:]] = OpINotEqual %[[#bool]] %[[#tmp]] %[[#value:]] -; CHECK: OpBranchConditional %[[#cond]] %[[#new_exit]] %[[#alias_exit:]] +; CHECK: %[[#taint_merge]] = OpLabel +; CHECK: OpStore %[[#switch_0]] %[[#int_0]] +; CHECK: %[[#tmp:]] = OpLoad %[[#]] %[[#switch_1]] +; CHECK: %[[#cond:]] = OpIEqual %[[#]] %[[#int_0]] %[[#tmp]] +; CHECK: OpBranchConditional %[[#cond]] %[[#taint_false_true:]] %[[#new_merge]] -; CHECK: %[[#alias_exit]] = OpLabel -; CHECK: OpBranch %[[#new_exit]] +; CHECK: %[[#taint_false_true]] = OpLabel +; CHECK: OpStore %[[#switch_0]] %[[#int_1]] +; CHECK: OpBranch %[[#new_merge]] -; CHECK: %[[#new_exit]] = OpLabel -; CHECK: %[[#tmp:]] = OpPhi %[[#type:]] %[[#A:]] %[[#cond1]] %[[#A:]] %[[#lor_lhs_false]] %[[#B:]] %[[#alias_exit]] -; CHECK: %[[#cond:]] = OpIEqual %[[#bool]] %[[#A]] %[[#tmp]] -; CHECK: OpBranchConditional %[[#cond]] %[[#if_then:]] %[[#if_end]] +; CHECK: %[[#new_merge]] = OpLabel +; CHECK: %[[#tmp:]] = OpLoad %[[#]] %[[#switch_0]] +; CHECK: %[[#cond:]] = OpIEqual %[[#]] %[[#int_0]] %[[#tmp]] +; CHECK: OpBranchConditional %[[#cond]] %[[#merge]] %[[#br_true:]] -; CHECK: %[[#if_then]] = OpLabel -; CHECK: OpBranch %[[#if_end]] +; CHECK: %[[#br_true]] = OpLabel +; CHECK: OpBranch %[[#merge]] -; CHECK: %[[#if_end]] = OpLabel -; CHECK: OpReturn +; CHECK: %[[#merge]] = OpLabel +; CHECK: OpReturn entry: %0 = call token @llvm.experimental.convergence.entry() - %a = alloca i32, align 4 - %b = alloca i32, align 4 - %val = alloca i32, align 4 - store i32 0, ptr %val, align 4 - %1 = load i32, ptr %a, align 4 - %tobool = icmp ne i32 %1, 0 - br i1 %tobool, label %if.then, label %lor.lhs.false - -lor.lhs.false: - %2 = load i32, ptr %b, align 4 - %tobool1 = icmp ne i32 %2, 0 - br i1 %tobool1, label %if.then, label %if.end - -if.then: - %8 = load i32, ptr %val, align 4 - %inc = add nsw i32 %8, 1 - store i32 %inc, ptr %val, align 4 - br label %if.end - -if.end: + %var = alloca i32, align 4 + br i1 true, label %br_true, label %br_false + +br_false: + store i32 0, ptr %var, align 4 + br i1 true, label %br_true, label %merge + +br_true: + store i32 0, ptr %var, align 4 + br label %merge + +merge: ret void } diff --git a/llvm/test/CodeGen/SPIRV/structurizer/loop-continue-split.ll b/llvm/test/CodeGen/SPIRV/structurizer/loop-continue-split.ll new file mode 100644 index 00000000000000..5a5ea002e0942f --- /dev/null +++ b/llvm/test/CodeGen/SPIRV/structurizer/loop-continue-split.ll @@ -0,0 +1,104 @@ +; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv-unknown-vulkan-compute %s -o - -filetype=obj | spirv-val %} +; RUN: llc -mtriple=spirv-unknown-vulkan-compute -O0 %s -o - | FileCheck %s + +; The goal of this test is to voluntarily create 2 overlapping convergence +; structures: the loop, and the inner condition. +; Here, the condition header also branches to 2 internal nodes, which are not +; directly a merge/exits. +; This will require a proper header-split. +; In addition, splitting the header makes the continue the merge of the inner +; condition, so we need to properly split the continue block to create a +; valid inner merge, in the correct order. + +target datalayout = "e-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128-v192:256-v256:256-v512:512-v1024:1024-G1" +target triple = "spirv-unknown-vulkan1.3-compute" + +; CHECK-DAG: OpName %[[#switch_0:]] "reg1" +; CHECK-DAG: OpName %[[#variable:]] "var" + +; CHECK-DAG: %[[#int_0:]] = OpConstant %[[#]] 0 +; CHECK-DAG: %[[#int_1:]] = OpConstant %[[#]] 1 +; CHECK-DAG: %[[#int_2:]] = OpConstant %[[#]] 2 +; CHECK-DAG: %[[#int_3:]] = OpConstant %[[#]] 3 +; CHECK-DAG: %[[#int_4:]] = OpConstant %[[#]] 4 + +define internal spir_func void @main() #1 { +; CHECK: %[[#entry:]] = OpLabel +; CHECK: %[[#switch_0]] = OpVariable %[[#]] Function +; CHECK: %[[#variable]] = OpVariable %[[#]] Function +; CHECK: OpBranch %[[#header:]] +entry: + %0 = call token @llvm.experimental.convergence.entry() + %var = alloca i32, align 4 + br label %header + +; CHECK: %[[#header]] = OpLabel +; CHECK: OpLoopMerge %[[#merge:]] %[[#continue:]] None +; CHECK: OpBranch %[[#split_header:]] + +; CHECK: %[[#split_header]] = OpLabel +; CHECK: OpSelectionMerge %[[#inner_merge:]] None +; CHECK: OpBranchConditional %[[#]] %[[#left:]] %[[#right:]] +header: + %2 = call token @llvm.experimental.convergence.loop() [ "convergencectrl"(token %0) ] + br i1 true, label %left, label %right + +; CHECK: %[[#left]] = OpLabel +; CHECK-DAG: OpStore %[[#switch_0]] %[[#int_0]] +; CHECK-DAG: OpStore %[[#variable]] %[[#int_1]] +; CHECK: OpBranchConditional %[[#]] %[[#inner_merge]] %[[#left_next:]] +left: + store i32 1, ptr %var + br i1 true, label %merge, label %left_next + +; CHECK: %[[#right]] = OpLabel +; CHECK-DAG: OpStore %[[#switch_0]] %[[#int_0]] +; CHECK-DAG: OpStore %[[#variable]] %[[#int_2]] +; CHECK: OpBranchConditional %[[#]] %[[#inner_merge]] %[[#right_next:]] +right: + store i32 2, ptr %var + br i1 true, label %merge, label %right_next + +; CHECK: %[[#left_next]] = OpLabel +; CHECK-DAG: OpStore %[[#switch_0]] %[[#int_1]] +; CHECK-DAG: OpStore %[[#variable]] %[[#int_3]] +; CHECK: OpBranch %[[#inner_merge]] +left_next: + store i32 3, ptr %var + br label %continue + +; CHECK: %[[#right_next]] = OpLabel +; CHECK-DAG: OpStore %[[#switch_0]] %[[#int_1]] +; CHECK-DAG: OpStore %[[#variable]] %[[#int_4]] +; CHECK: OpBranch %[[#inner_merge]] +right_next: + store i32 4, ptr %var + br label %continue + +; CHECK: %[[#inner_merge]] = OpLabel +; CHECK: %[[#tmp:]] = OpLoad %[[#]] %[[#switch_0]] +; CHECK: %[[#cond:]] = OpIEqual %[[#]] %[[#int_0]] %[[#tmp]] +; CHECK: OpBranchConditional %[[#cond]] %[[#merge]] %[[#continue]] + +; CHECK: %[[#continue]] = OpLabel +; CHECK: OpBranch %[[#header]] +continue: + br label %header + +; CHECK: %[[#merge]] = OpLabel +; CHECK: OpReturn +merge: + ret void +} + + +declare token @llvm.experimental.convergence.entry() #0 +declare token @llvm.experimental.convergence.loop() #0 + +attributes #0 = { convergent nocallback nofree nosync nounwind willreturn memory(none) } +attributes #1 = { convergent noinline norecurse nounwind optnone "frame-pointer"="all" "no-trapping-math"="true" "stack-protector-buffer-size"="8" } + +!llvm.module.flags = !{!0, !1} + +!0 = !{i32 1, !"wchar_size", i32 4} +!1 = !{i32 4, !"dx.disable_optimizations", i32 1} diff --git a/llvm/test/CodeGen/SPIRV/structurizer/merge-exit-break.ll b/llvm/test/CodeGen/SPIRV/structurizer/merge-exit-break.ll index a9a0397718e1f5..b421ae7990c67a 100644 --- a/llvm/test/CodeGen/SPIRV/structurizer/merge-exit-break.ll +++ b/llvm/test/CodeGen/SPIRV/structurizer/merge-exit-break.ll @@ -1,23 +1,23 @@ -; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv-unknown-vulkan-compute %s -o - -filetype=obj | spirv-val %} ; RUN: llc -mtriple=spirv-unknown-vulkan-compute -O0 %s -o - | FileCheck %s --match-full-lines +; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv-unknown-vulkan-compute %s -o - -filetype=obj | spirv-val %} target datalayout = "e-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128-v192:256-v256:256-v512:512-v1024:1024-G1" target triple = "spirv-unknown-vulkan-compute" define internal spir_func void @main() #0 { -; CHECK: OpDecorate %[[#builtin:]] BuiltIn SubgroupLocalInvocationId -; CHECK-DAG: %[[#int_ty:]] = OpTypeInt 32 0 -; CHECK-DAG: %[[#int_fpty:]] = OpTypePointer Function %[[#int_ty]] +; CHECK-DAG: OpName %[[#idx:]] "idx" +; CHECK-DAG: OpDecorate %[[#builtin:]] BuiltIn SubgroupLocalInvocationId +; CHECK-DAG: %[[#int_ty:]] = OpTypeInt 32 0 ; CHECK-DAG: %[[#int_ipty:]] = OpTypePointer Input %[[#int_ty]] -; CHECK-DAG: %[[#bool_ty:]] = OpTypeBool -; CHECK-DAG: %[[#int_0:]] = OpConstant %[[#int_ty]] 0 -; CHECK-DAG: %[[#int_10:]] = OpConstant %[[#int_ty]] 10 -; CHECK-DAG: %[[#builtin]] = OpVariable %[[#int_ipty]] Input +; CHECK-DAG: %[[#bool_ty:]] = OpTypeBool +; CHECK-DAG: %[[#int_0:]] = OpConstant %[[#int_ty]] 0 +; CHECK-DAG: %[[#int_10:]] = OpConstant %[[#int_ty]] 10 +; CHECK-DAG: %[[#builtin]] = OpVariable %[[#int_ipty]] Input ; CHECK: %[[#entry:]] = OpLabel -; CHECK: %[[#idx:]] = OpVariable %[[#int_fpty]] Function -; CHECK: OpStore %[[#idx]] %[[#int_0]] Aligned 4 +; CHECK: %[[#idx]] = OpVariable %[[#]] Function +; ACHECK: OpStore %[[#idx]] %[[#int_0]] Aligned 4 ; CHECK: OpBranch %[[#while_cond:]] entry: %0 = call token @llvm.experimental.convergence.entry() @@ -37,12 +37,12 @@ while.cond: %cmp = icmp ne i32 %2, 10 br i1 %cmp, label %while.body, label %while.end -; CHECK: %[[#while_body]] = OpLabel -; CHECK-NEXT: %[[#tmp:]] = OpLoad %[[#int_ty]] %[[#builtin]] Aligned 1 -; CHECK-NEXT: OpStore %[[#idx]] %[[#tmp]] Aligned 4 -; CHECK-NEXT: %[[#tmp:]] = OpLoad %[[#int_ty]] %[[#idx]] Aligned 4 -; CHECK-NEXT: %[[#cmp1:]] = OpIEqual %[[#bool_ty]] %[[#tmp]] %[[#int_0]] -; CHECK: OpBranchConditional %[[#cmp1]] %[[#new_end]] %[[#if_end]] +; CHECK: %[[#while_body]] = OpLabel +; CHECK: %[[#tmp:]] = OpLoad %[[#]] %[[#builtin]] Aligned 1 +; CHECK: OpStore %[[#idx]] %[[#tmp]] Aligned 4 +; CHECK: %[[#tmp:]] = OpLoad %[[#int_ty]] %[[#idx]] Aligned 4 +; CHECK: %[[#cmp1:]] = OpIEqual %[[#bool_ty]] %[[#tmp]] %[[#int_0]] +; CHECK: OpBranchConditional %[[#cmp1]] %[[#new_end]] %[[#if_end]] while.body: %3 = call i32 @__hlsl_wave_get_lane_index() [ "convergencectrl"(token %1) ] store i32 %3, ptr %idx, align 4 @@ -50,14 +50,14 @@ while.body: %cmp1 = icmp eq i32 %4, 0 br i1 %cmp1, label %if.then, label %if.end +; CHECK: %[[#if_end]] = OpLabel +; CHECK: OpBranch %[[#while_cond]] + ; CHECK: %[[#new_end]] = OpLabel ; CHECK: OpBranch %[[#while_end:]] - if.then: br label %while.end -; CHECK: %[[#if_end]] = OpLabel -; CHECK: OpBranch %[[#while_cond]] if.end: br label %while.cond diff --git a/llvm/test/CodeGen/SPIRV/structurizer/merge-exit-convergence-in-break.ll b/llvm/test/CodeGen/SPIRV/structurizer/merge-exit-convergence-in-break.ll index 3db7545b81780c..ac330a96444b82 100644 --- a/llvm/test/CodeGen/SPIRV/structurizer/merge-exit-convergence-in-break.ll +++ b/llvm/test/CodeGen/SPIRV/structurizer/merge-exit-convergence-in-break.ll @@ -1,21 +1,20 @@ -; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv-unknown-vulkan-compute %s -o - -filetype=obj | spirv-val %} ; RUN: llc -mtriple=spirv-unknown-vulkan-compute -O0 %s -o - | FileCheck %s --match-full-lines +; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv-unknown-vulkan-compute %s -o - -filetype=obj | spirv-val %} target datalayout = "e-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128-v192:256-v256:256-v512:512-v1024:1024-G1" target triple = "spirv-unknown-vulkan-compute" define internal spir_func void @main() #0 { -; CHECK: OpDecorate %[[#builtin:]] BuiltIn SubgroupLocalInvocationId - +; CHECK-DAG: OpName %[[#idx:]] "idx" +; CHECK-DAG: OpDecorate %[[#builtin:]] BuiltIn SubgroupLocalInvocationId ; CHECK-DAG: %[[#int_ty:]] = OpTypeInt 32 0 -; CHECK-DAG: %[[#pint_ty:]] = OpTypePointer Function %[[#int_ty]] ; CHECK-DAG: %[[#bool_ty:]] = OpTypeBool ; CHECK-DAG: %[[#int_0:]] = OpConstant %[[#int_ty]] 0 ; CHECK-DAG: %[[#int_10:]] = OpConstant %[[#int_ty]] 10 ; CHECK: %[[#entry:]] = OpLabel -; CHECK: %[[#idx:]] = OpVariable %[[#pint_ty]] Function +; CHECK: %[[#idx]] = OpVariable %[[#]] Function ; CHECK: OpStore %[[#idx]] %[[#int_0]] Aligned 4 ; CHECK: OpBranch %[[#while_cond:]] entry: @@ -48,17 +47,18 @@ while.body: %cmp1 = icmp eq i32 %4, 0 br i1 %cmp1, label %if.then, label %if.end +; CHECK: %[[#if_end]] = OpLabel +; CHECK: OpBranch %[[#while_cond]] + ; CHECK: %[[#if_then]] = OpLabel -; CHECK-NEXT: %[[#tmp:]] = OpLoad %[[#int_ty]] %[[#builtin]] Aligned 1 -; CHECK-NEXT: OpStore %[[#idx]] %[[#tmp]] Aligned 4 +; CHECK: %[[#tmp:]] = OpLoad %[[#int_ty]] %[[#builtin]] Aligned 1 +; CHECK: OpStore %[[#idx]] %[[#tmp]] Aligned 4 ; CHECK: OpBranch %[[#new_end]] if.then: %5 = call i32 @__hlsl_wave_get_lane_index() [ "convergencectrl"(token %1) ] store i32 %5, ptr %idx, align 4 br label %while.end -; CHECK: %[[#if_end]] = OpLabel -; CHECK: OpBranch %[[#while_cond]] if.end: br label %while.cond diff --git a/llvm/test/CodeGen/SPIRV/structurizer/merge-exit-multiple-break.ll b/llvm/test/CodeGen/SPIRV/structurizer/merge-exit-multiple-break.ll index d25b30df45ae04..784bd38a6fbaed 100644 --- a/llvm/test/CodeGen/SPIRV/structurizer/merge-exit-multiple-break.ll +++ b/llvm/test/CodeGen/SPIRV/structurizer/merge-exit-multiple-break.ll @@ -1,14 +1,15 @@ -; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv-unknown-vulkan-compute %s -o - -filetype=obj | spirv-val %} ; RUN: llc -mtriple=spirv-unknown-vulkan-compute -O0 %s -o - | FileCheck %s --match-full-lines +; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv-unknown-vulkan-compute %s -o - -filetype=obj | spirv-val %} target datalayout = "e-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128-v192:256-v256:256-v512:512-v1024:1024-G1" target triple = "spirv-unknown-vulkan-compute" define internal spir_func void @main() #0 { -; CHECK: OpDecorate %[[#builtin:]] BuiltIn SubgroupLocalInvocationId +; CHECK-DAG: OpName %[[#idx:]] "idx" +; CHECK-DAG: OpName %[[#reg_0:]] "reg" +; CHECK-DAG: OpDecorate %[[#builtin:]] BuiltIn SubgroupLocalInvocationId ; CHECK-DAG: %[[#int_ty:]] = OpTypeInt 32 0 -; CHECK-DAG: %[[#pint_ty:]] = OpTypePointer Function %[[#int_ty]] ; CHECK-DAG: %[[#bool_ty:]] = OpTypeBool ; CHECK-DAG: %[[#int_0:]] = OpConstant %[[#int_ty]] 0 ; CHECK-DAG: %[[#int_1:]] = OpConstant %[[#int_ty]] 1 @@ -16,7 +17,7 @@ define internal spir_func void @main() #0 { ; CHECK-DAG: %[[#int_10:]] = OpConstant %[[#int_ty]] 10 ; CHECK: %[[#entry:]] = OpLabel -; CHECK: %[[#idx:]] = OpVariable %[[#pint_ty]] Function +; CHECK: %[[#idx]] = OpVariable %[[#]] Function ; CHECK: OpStore %[[#idx]] %[[#int_0]] Aligned 4 ; CHECK: OpBranch %[[#while_cond:]] entry: @@ -26,6 +27,7 @@ entry: br label %while.cond ; CHECK: %[[#while_cond]] = OpLabel +; CHECK: OpStore %[[#reg_0]] %[[#]] Aligned 4 ; CHECK: %[[#tmp:]] = OpLoad %[[#int_ty]] %[[#idx]] Aligned 4 ; CHECK: %[[#cmp:]] = OpINotEqual %[[#bool_ty]] %[[#tmp]] %[[#int_10]] ; CHECK: OpLoopMerge %[[#new_end:]] %[[#if_end2:]] None @@ -37,10 +39,11 @@ while.cond: br i1 %cmp, label %while.body, label %while.end ; CHECK: %[[#while_body]] = OpLabel -; CHECK-NEXT: %[[#tmp:]] = OpLoad %[[#int_ty]] %[[#builtin]] Aligned 1 -; CHECK-NEXT: OpStore %[[#idx]] %[[#tmp]] Aligned 4 -; CHECK-NEXT: %[[#tmp:]] = OpLoad %[[#int_ty]] %[[#idx]] Aligned 4 -; CHECK-NEXT: %[[#cmp1:]] = OpIEqual %[[#bool_ty]] %[[#tmp]] %[[#int_0]] +; CHECK: OpStore %[[#reg_0]] %[[#]] Aligned 4 +; CHECK: %[[#tmp:]] = OpLoad %[[#]] %[[#builtin]] Aligned 1 +; CHECK: OpStore %[[#idx]] %[[#tmp]] Aligned 4 +; CHECK: %[[#tmp:]] = OpLoad %[[#int_ty]] %[[#idx]] Aligned 4 +; CHECK: %[[#cmp1:]] = OpIEqual %[[#bool_ty]] %[[#tmp]] %[[#int_0]] ; CHECK: OpBranchConditional %[[#cmp1]] %[[#new_end]] %[[#if_end:]] while.body: %3 = call i32 @__hlsl_wave_get_lane_index() [ "convergencectrl"(token %1) ] @@ -50,10 +53,11 @@ while.body: br i1 %cmp1, label %if.then, label %if.end ; CHECK: %[[#if_end]] = OpLabel -; CHECK-NEXT: %[[#tmp:]] = OpLoad %[[#int_ty]] %[[#builtin]] Aligned 1 -; CHECK-NEXT: OpStore %[[#idx]] %[[#tmp]] Aligned 4 -; CHECK-NEXT: %[[#tmp:]] = OpLoad %[[#int_ty]] %[[#idx]] Aligned 4 -; CHECK-NEXT: %[[#cmp2:]] = OpIEqual %[[#bool_ty]] %[[#tmp]] %[[#int_0]] +; CHECK: OpStore %[[#reg_0]] %[[#]] Aligned 4 +; CHECK: %[[#tmp:]] = OpLoad %[[#int_ty]] %[[#builtin]] Aligned 1 +; CHECK: OpStore %[[#idx]] %[[#tmp]] Aligned 4 +; CHECK: %[[#tmp:]] = OpLoad %[[#int_ty]] %[[#idx]] Aligned 4 +; CHECK: %[[#cmp2:]] = OpIEqual %[[#bool_ty]] %[[#tmp]] %[[#int_0]] ; CHECK: OpBranchConditional %[[#cmp2]] %[[#new_end]] %[[#if_end2]] if.end: %5 = call i32 @__hlsl_wave_get_lane_index() [ "convergencectrl"(token %1) ] @@ -62,14 +66,15 @@ if.end: %cmp2 = icmp eq i32 %6, 0 br i1 %cmp2, label %if.then2, label %if.end2 +; CHECK: %[[#if_end2]] = OpLabel +; CHECK: OpBranch %[[#while_cond]] + ; TODO: this OpSwitch is useless. Improve the "remove useless branches" step of the structurizer to ; cleanup those. ; CHECK: %[[#new_end]] = OpLabel -; CHECK: %[[#route:]] = OpPhi %[[#int_ty]] %[[#int_0]] %[[#while_cond]] %[[#int_1]] %[[#while_body]] %[[#int_2]] %[[#if_end]] +; CHECK: %[[#route:]] = OpLoad %[[#]] %[[#reg_0]] Aligned 4 ; CHECK: OpSwitch %[[#route]] %[[#while_end:]] 1 %[[#while_end:]] 2 %[[#while_end:]] -; CHECK: %[[#if_end2]] = OpLabel -; CHECK: OpBranch %[[#while_cond]] if.end2: br label %while.cond diff --git a/llvm/test/CodeGen/SPIRV/structurizer/phi-exit.ll b/llvm/test/CodeGen/SPIRV/structurizer/phi-exit.ll new file mode 100644 index 00000000000000..541b23a6495c9a --- /dev/null +++ b/llvm/test/CodeGen/SPIRV/structurizer/phi-exit.ll @@ -0,0 +1,45 @@ +; RUN: llc -mtriple=spirv-unknown-vulkan-compute -O0 %s -o - | FileCheck %s --match-full-lines +; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv-unknown-vulkan-compute %s -o - -filetype=obj | spirv-val %} + +target datalayout = "e-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128-v192:256-v256:256-v512:512-v1024:1024-G1" +target triple = "spirv-unknown-vulkan1.3-compute" + +define internal spir_func void @main() #1 { +; CHECK: %[[#entry:]] = OpLabel +; CHECK: OpBranch %[[#do_body:]] +entry: + %0 = call token @llvm.experimental.convergence.entry() + %a = alloca i32, align 4 + br label %loop_body + +loop_body: + br i1 true, label %left, label %right + +left: + br i1 true, label %loop_exit, label %loop_continue + +right: + br i1 true, label %loop_exit, label %loop_continue + +loop_continue: + br label %loop_body + +loop_exit: + %r = phi i32 [ 0, %left ], [ 1, %right ] + store i32 %r, ptr %a, align 4 + ret void + +} + + +declare token @llvm.experimental.convergence.entry() #0 +declare token @llvm.experimental.convergence.loop() #0 + +attributes #0 = { convergent nocallback nofree nosync nounwind willreturn memory(none) } +attributes #1 = { convergent noinline norecurse nounwind optnone "frame-pointer"="all" "no-trapping-math"="true" "stack-protector-buffer-size"="8" } + +!llvm.module.flags = !{!0, !1} + +!0 = !{i32 1, !"wchar_size", i32 4} +!1 = !{i32 4, !"dx.disable_optimizations", i32 1} + diff --git a/llvm/test/CodeGen/SPIRV/structurizer/return-early.ll b/llvm/test/CodeGen/SPIRV/structurizer/return-early.ll index 6f60538153dfc9..e27aca8784286c 100644 --- a/llvm/test/CodeGen/SPIRV/structurizer/return-early.ll +++ b/llvm/test/CodeGen/SPIRV/structurizer/return-early.ll @@ -1,6 +1,9 @@ -; RUN: llc -mtriple=spirv-unknown-vulkan-compute -O0 %s -o - | FileCheck %s --match-full-lines +; RUN: llc -mtriple=spirv-unknown-vulkan-compute -O0 %s -o - | FileCheck %s ; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv-unknown-vulkan-compute %s -o - -filetype=obj | spirv-val %} +; CHECK-DAG: OpName %[[#reg_0:]] "reg2" +; CHECK-DAG: OpName %[[#reg_1:]] "reg1" + target datalayout = "e-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128-v192:256-v256:256-v512:512-v1024:1024-G1" target triple = "spirv-unknown-vulkan1.3-compute" @@ -37,36 +40,40 @@ while.body: ] ; CHECK: %[[#case_1]] = OpLabel +; CHECK: OpStore %[[#reg_0]] %[[#]] ; CHECK: OpBranch %[[#switch_end]] sw.bb: store i32 1, ptr %a, align 4 br label %while.end ; CHECK: %[[#case_2]] = OpLabel +; CHECK: OpStore %[[#reg_0]] %[[#]] ; CHECK: OpBranch %[[#switch_end]] sw.bb1: store i32 3, ptr %a, align 4 br label %while.end ; CHECK: %[[#case_5]] = OpLabel +; CHECK: OpStore %[[#reg_0]] %[[#]] ; CHECK: OpBranch %[[#switch_end]] sw.bb2: store i32 5, ptr %a, align 4 br label %while.end ; CHECK: %[[#switch_end]] = OpLabel -; CHECK: %[[#phi:]] = OpPhi %[[#type:]] %[[#A:]] %[[#while_body]] %[[#B:]] %[[#case_5]] %[[#B:]] %[[#case_2]] %[[#B:]] %[[#case_1]] -; CHECK: %[[#tmp:]] = OpIEqual %[[#type:]] %[[#A]] %[[#phi]] +; CHECK: %[[#val:]] = OpLoad %[[#]] %[[#reg_0]] +; CHECK: %[[#tmp:]] = OpIEqual %[[#type:]] %[[#]] %[[#val]] ; CHECK: OpBranchConditional %[[#tmp]] %[[#sw_default:]] %[[#while_end]] ; CHECK: %[[#sw_default]] = OpLabel -; CHECK: OpStore %[[#A:]] %[[#B:]] Aligned 4 +; CHECK: OpStore %[[#]] %[[#B:]] Aligned 4 ; CHECK: OpBranch %[[#for_cond:]] sw.default: store i32 0, ptr %i, align 4 br label %for.cond ; CHECK: %[[#for_cond]] = OpLabel +; CHECK: OpStore %[[#reg_1]] %[[#]] ; CHECK: OpSelectionMerge %[[#for_merge:]] None ; CHECK-NEXT: OpBranchConditional %[[#cond:]] %[[#for_merge]] %[[#for_end:]] for.cond: @@ -76,13 +83,14 @@ for.cond: br i1 %cmp, label %for.body, label %for.end ; CHECK: %[[#for_end]] = OpLabel +; CHECK: OpStore %[[#reg_1]] %[[#]] ; CHECK: OpBranch %[[#for_merge]] for.end: br label %while.end ; CHECK: %[[#for_merge]] = OpLabel -; CHECK: %[[#phi:]] = OpPhi %[[#type:]] %[[#A:]] %[[#for_cond]] %[[#B:]] %[[#for_end]] -; CHECK: %[[#tmp:]] = OpIEqual %[[#type:]] %[[#A]] %[[#phi]] +; CHECK: %[[#val:]] = OpLoad %[[#]] %[[#reg_1]] +; CHECK: %[[#tmp:]] = OpIEqual %[[#type:]] %[[#]] %[[#val]] ; CHECK: OpBranchConditional %[[#tmp]] %[[#for_body:]] %[[#while_end]] ; CHECK: %[[#for_body]] = OpLabel diff --git a/llvm/test/CodeGen/X86/andnot-patterns.ll b/llvm/test/CodeGen/X86/andnot-patterns.ll index 1df29f0b12d1b6..fc573fbd4fc99d 100644 --- a/llvm/test/CodeGen/X86/andnot-patterns.ll +++ b/llvm/test/CodeGen/X86/andnot-patterns.ll @@ -14,41 +14,73 @@ declare void @use_i32(i32) ; define i64 @andnot_rotl_i64(i64 %a0, i64 %a1, i64 %a2) nounwind { -; X86-LABEL: andnot_rotl_i64: -; X86: # %bb.0: -; X86-NEXT: pushl %esi -; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx -; X86-NEXT: movl {{[0-9]+}}(%esp), %edx -; X86-NEXT: movl {{[0-9]+}}(%esp), %esi -; X86-NEXT: notl %esi -; X86-NEXT: notl %edx -; X86-NEXT: testb $32, %cl -; X86-NEXT: jne .LBB0_1 -; X86-NEXT: # %bb.2: -; X86-NEXT: movl %edx, %eax -; X86-NEXT: jmp .LBB0_3 -; X86-NEXT: .LBB0_1: -; X86-NEXT: movl %esi, %eax -; X86-NEXT: movl %edx, %esi -; X86-NEXT: .LBB0_3: -; X86-NEXT: movl %esi, %edx -; X86-NEXT: shldl %cl, %eax, %edx -; X86-NEXT: # kill: def $cl killed $cl killed $ecx -; X86-NEXT: shldl %cl, %esi, %eax -; X86-NEXT: andl {{[0-9]+}}(%esp), %eax -; X86-NEXT: andl {{[0-9]+}}(%esp), %edx -; X86-NEXT: popl %esi -; X86-NEXT: retl +; X86-NOBMI-LABEL: andnot_rotl_i64: +; X86-NOBMI: # %bb.0: +; X86-NOBMI-NEXT: pushl %esi +; X86-NOBMI-NEXT: movl {{[0-9]+}}(%esp), %esi +; X86-NOBMI-NEXT: movl {{[0-9]+}}(%esp), %eax +; X86-NOBMI-NEXT: movl {{[0-9]+}}(%esp), %ecx +; X86-NOBMI-NEXT: testb $32, %cl +; X86-NOBMI-NEXT: jne .LBB0_1 +; X86-NOBMI-NEXT: # %bb.2: +; X86-NOBMI-NEXT: movl %eax, %edx +; X86-NOBMI-NEXT: jmp .LBB0_3 +; X86-NOBMI-NEXT: .LBB0_1: +; X86-NOBMI-NEXT: movl %esi, %edx +; X86-NOBMI-NEXT: movl %eax, %esi +; X86-NOBMI-NEXT: .LBB0_3: +; X86-NOBMI-NEXT: movl %esi, %eax +; X86-NOBMI-NEXT: shldl %cl, %edx, %eax +; X86-NOBMI-NEXT: notl %eax +; X86-NOBMI-NEXT: andl {{[0-9]+}}(%esp), %eax +; X86-NOBMI-NEXT: # kill: def $cl killed $cl killed $ecx +; X86-NOBMI-NEXT: shldl %cl, %esi, %edx +; X86-NOBMI-NEXT: notl %edx +; X86-NOBMI-NEXT: andl {{[0-9]+}}(%esp), %edx +; X86-NOBMI-NEXT: popl %esi +; X86-NOBMI-NEXT: retl ; -; X64-LABEL: andnot_rotl_i64: -; X64: # %bb.0: -; X64-NEXT: movq %rdx, %rcx -; X64-NEXT: movq %rsi, %rax -; X64-NEXT: notq %rax -; X64-NEXT: # kill: def $cl killed $cl killed $rcx -; X64-NEXT: rolq %cl, %rax -; X64-NEXT: andq %rdi, %rax -; X64-NEXT: retq +; X86-BMI-LABEL: andnot_rotl_i64: +; X86-BMI: # %bb.0: +; X86-BMI-NEXT: pushl %esi +; X86-BMI-NEXT: movl {{[0-9]+}}(%esp), %edx +; X86-BMI-NEXT: movl {{[0-9]+}}(%esp), %eax +; X86-BMI-NEXT: movl {{[0-9]+}}(%esp), %ecx +; X86-BMI-NEXT: testb $32, %cl +; X86-BMI-NEXT: jne .LBB0_1 +; X86-BMI-NEXT: # %bb.2: +; X86-BMI-NEXT: movl %eax, %esi +; X86-BMI-NEXT: jmp .LBB0_3 +; X86-BMI-NEXT: .LBB0_1: +; X86-BMI-NEXT: movl %edx, %esi +; X86-BMI-NEXT: movl %eax, %edx +; X86-BMI-NEXT: .LBB0_3: +; X86-BMI-NEXT: movl %edx, %eax +; X86-BMI-NEXT: shldl %cl, %esi, %eax +; X86-BMI-NEXT: andnl {{[0-9]+}}(%esp), %eax, %eax +; X86-BMI-NEXT: # kill: def $cl killed $cl killed $ecx +; X86-BMI-NEXT: shldl %cl, %edx, %esi +; X86-BMI-NEXT: andnl {{[0-9]+}}(%esp), %esi, %edx +; X86-BMI-NEXT: popl %esi +; X86-BMI-NEXT: retl +; +; X64-NOBMI-LABEL: andnot_rotl_i64: +; X64-NOBMI: # %bb.0: +; X64-NOBMI-NEXT: movq %rdx, %rcx +; X64-NOBMI-NEXT: movq %rsi, %rax +; X64-NOBMI-NEXT: # kill: def $cl killed $cl killed $rcx +; X64-NOBMI-NEXT: rolq %cl, %rax +; X64-NOBMI-NEXT: notq %rax +; X64-NOBMI-NEXT: andq %rdi, %rax +; X64-NOBMI-NEXT: retq +; +; X64-BMI-LABEL: andnot_rotl_i64: +; X64-BMI: # %bb.0: +; X64-BMI-NEXT: movq %rdx, %rcx +; X64-BMI-NEXT: # kill: def $cl killed $cl killed $rcx +; X64-BMI-NEXT: rolq %cl, %rsi +; X64-BMI-NEXT: andnq %rdi, %rsi, %rax +; X64-BMI-NEXT: retq %not = xor i64 %a1, -1 %rot = tail call i64 @llvm.fshl.i64(i64 %not, i64 %not, i64 %a2) %and = and i64 %rot, %a0 @@ -56,24 +88,40 @@ define i64 @andnot_rotl_i64(i64 %a0, i64 %a1, i64 %a2) nounwind { } define i32 @andnot_rotl_i32(i32 %a0, i32 %a1, i32 %a2) nounwind { -; X86-LABEL: andnot_rotl_i32: -; X86: # %bb.0: -; X86-NEXT: movzbl {{[0-9]+}}(%esp), %ecx -; X86-NEXT: movl {{[0-9]+}}(%esp), %eax -; X86-NEXT: notl %eax -; X86-NEXT: roll %cl, %eax -; X86-NEXT: andl {{[0-9]+}}(%esp), %eax -; X86-NEXT: retl +; X86-NOBMI-LABEL: andnot_rotl_i32: +; X86-NOBMI: # %bb.0: +; X86-NOBMI-NEXT: movzbl {{[0-9]+}}(%esp), %ecx +; X86-NOBMI-NEXT: movl {{[0-9]+}}(%esp), %eax +; X86-NOBMI-NEXT: roll %cl, %eax +; X86-NOBMI-NEXT: notl %eax +; X86-NOBMI-NEXT: andl {{[0-9]+}}(%esp), %eax +; X86-NOBMI-NEXT: retl ; -; X64-LABEL: andnot_rotl_i32: -; X64: # %bb.0: -; X64-NEXT: movl %edx, %ecx -; X64-NEXT: movl %esi, %eax -; X64-NEXT: notl %eax -; X64-NEXT: # kill: def $cl killed $cl killed $ecx -; X64-NEXT: roll %cl, %eax -; X64-NEXT: andl %edi, %eax -; X64-NEXT: retq +; X86-BMI-LABEL: andnot_rotl_i32: +; X86-BMI: # %bb.0: +; X86-BMI-NEXT: movzbl {{[0-9]+}}(%esp), %ecx +; X86-BMI-NEXT: movl {{[0-9]+}}(%esp), %eax +; X86-BMI-NEXT: roll %cl, %eax +; X86-BMI-NEXT: andnl {{[0-9]+}}(%esp), %eax, %eax +; X86-BMI-NEXT: retl +; +; X64-NOBMI-LABEL: andnot_rotl_i32: +; X64-NOBMI: # %bb.0: +; X64-NOBMI-NEXT: movl %edx, %ecx +; X64-NOBMI-NEXT: movl %esi, %eax +; X64-NOBMI-NEXT: # kill: def $cl killed $cl killed $ecx +; X64-NOBMI-NEXT: roll %cl, %eax +; X64-NOBMI-NEXT: notl %eax +; X64-NOBMI-NEXT: andl %edi, %eax +; X64-NOBMI-NEXT: retq +; +; X64-BMI-LABEL: andnot_rotl_i32: +; X64-BMI: # %bb.0: +; X64-BMI-NEXT: movl %edx, %ecx +; X64-BMI-NEXT: # kill: def $cl killed $cl killed $ecx +; X64-BMI-NEXT: roll %cl, %esi +; X64-BMI-NEXT: andnl %edi, %esi, %eax +; X64-BMI-NEXT: retq %not = xor i32 %a1, -1 %rot = tail call i32 @llvm.fshl.i32(i32 %not, i32 %not, i32 %a2) %and = and i32 %rot, %a0 @@ -84,23 +132,32 @@ define i16 @andnot_rotl_i16(i16 %a0, i16 %a1, i16 %a2) nounwind { ; X86-LABEL: andnot_rotl_i16: ; X86: # %bb.0: ; X86-NEXT: movzbl {{[0-9]+}}(%esp), %ecx -; X86-NEXT: movl {{[0-9]+}}(%esp), %eax -; X86-NEXT: notl %eax +; X86-NEXT: movzwl {{[0-9]+}}(%esp), %eax ; X86-NEXT: rolw %cl, %ax +; X86-NEXT: notl %eax ; X86-NEXT: andw {{[0-9]+}}(%esp), %ax ; X86-NEXT: # kill: def $ax killed $ax killed $eax ; X86-NEXT: retl ; -; X64-LABEL: andnot_rotl_i16: -; X64: # %bb.0: -; X64-NEXT: movl %edx, %ecx -; X64-NEXT: movl %esi, %eax -; X64-NEXT: notl %eax -; X64-NEXT: # kill: def $cl killed $cl killed $ecx -; X64-NEXT: rolw %cl, %ax -; X64-NEXT: andl %edi, %eax -; X64-NEXT: # kill: def $ax killed $ax killed $eax -; X64-NEXT: retq +; X64-NOBMI-LABEL: andnot_rotl_i16: +; X64-NOBMI: # %bb.0: +; X64-NOBMI-NEXT: movl %edx, %ecx +; X64-NOBMI-NEXT: movl %esi, %eax +; X64-NOBMI-NEXT: # kill: def $cl killed $cl killed $ecx +; X64-NOBMI-NEXT: rolw %cl, %ax +; X64-NOBMI-NEXT: notl %eax +; X64-NOBMI-NEXT: andl %edi, %eax +; X64-NOBMI-NEXT: # kill: def $ax killed $ax killed $eax +; X64-NOBMI-NEXT: retq +; +; X64-BMI-LABEL: andnot_rotl_i16: +; X64-BMI: # %bb.0: +; X64-BMI-NEXT: movl %edx, %ecx +; X64-BMI-NEXT: # kill: def $cl killed $cl killed $ecx +; X64-BMI-NEXT: rolw %cl, %si +; X64-BMI-NEXT: andnl %edi, %esi, %eax +; X64-BMI-NEXT: # kill: def $ax killed $ax killed $eax +; X64-BMI-NEXT: retq %not = xor i16 %a1, -1 %rot = tail call i16 @llvm.fshl.i16(i16 %not, i16 %not, i16 %a2) %and = and i16 %rot, %a0 @@ -112,8 +169,8 @@ define i8 @andnot_rotl_i8(i8 %a0, i8 %a1, i8 %a2) nounwind { ; X86: # %bb.0: ; X86-NEXT: movzbl {{[0-9]+}}(%esp), %ecx ; X86-NEXT: movzbl {{[0-9]+}}(%esp), %eax -; X86-NEXT: notb %al ; X86-NEXT: rolb %cl, %al +; X86-NEXT: notb %al ; X86-NEXT: andb {{[0-9]+}}(%esp), %al ; X86-NEXT: retl ; @@ -121,9 +178,9 @@ define i8 @andnot_rotl_i8(i8 %a0, i8 %a1, i8 %a2) nounwind { ; X64: # %bb.0: ; X64-NEXT: movl %edx, %ecx ; X64-NEXT: movl %esi, %eax -; X64-NEXT: notb %al ; X64-NEXT: # kill: def $cl killed $cl killed $ecx ; X64-NEXT: rolb %cl, %al +; X64-NEXT: notb %al ; X64-NEXT: andb %dil, %al ; X64-NEXT: # kill: def $al killed $al killed $eax ; X64-NEXT: retq @@ -198,41 +255,73 @@ define i64 @andnot_rotl_i64_multiuse_rot(i64 %a0, i64 %a1, i64 %a2) nounwind { ; define i64 @andnot_rotr_i64(i64 %a0, i64 %a1, i64 %a2) nounwind { -; X86-LABEL: andnot_rotr_i64: -; X86: # %bb.0: -; X86-NEXT: pushl %esi -; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx -; X86-NEXT: movl {{[0-9]+}}(%esp), %esi -; X86-NEXT: movl {{[0-9]+}}(%esp), %edx -; X86-NEXT: notl %esi -; X86-NEXT: notl %edx -; X86-NEXT: testb $32, %cl -; X86-NEXT: je .LBB5_1 -; X86-NEXT: # %bb.2: -; X86-NEXT: movl %edx, %eax -; X86-NEXT: jmp .LBB5_3 -; X86-NEXT: .LBB5_1: -; X86-NEXT: movl %esi, %eax -; X86-NEXT: movl %edx, %esi -; X86-NEXT: .LBB5_3: -; X86-NEXT: movl %esi, %edx -; X86-NEXT: shrdl %cl, %eax, %edx -; X86-NEXT: # kill: def $cl killed $cl killed $ecx -; X86-NEXT: shrdl %cl, %esi, %eax -; X86-NEXT: andl {{[0-9]+}}(%esp), %eax -; X86-NEXT: andl {{[0-9]+}}(%esp), %edx -; X86-NEXT: popl %esi -; X86-NEXT: retl +; X86-NOBMI-LABEL: andnot_rotr_i64: +; X86-NOBMI: # %bb.0: +; X86-NOBMI-NEXT: pushl %esi +; X86-NOBMI-NEXT: movl {{[0-9]+}}(%esp), %eax +; X86-NOBMI-NEXT: movl {{[0-9]+}}(%esp), %esi +; X86-NOBMI-NEXT: movl {{[0-9]+}}(%esp), %ecx +; X86-NOBMI-NEXT: testb $32, %cl +; X86-NOBMI-NEXT: je .LBB5_1 +; X86-NOBMI-NEXT: # %bb.2: +; X86-NOBMI-NEXT: movl %eax, %edx +; X86-NOBMI-NEXT: jmp .LBB5_3 +; X86-NOBMI-NEXT: .LBB5_1: +; X86-NOBMI-NEXT: movl %esi, %edx +; X86-NOBMI-NEXT: movl %eax, %esi +; X86-NOBMI-NEXT: .LBB5_3: +; X86-NOBMI-NEXT: movl %esi, %eax +; X86-NOBMI-NEXT: shrdl %cl, %edx, %eax +; X86-NOBMI-NEXT: notl %eax +; X86-NOBMI-NEXT: andl {{[0-9]+}}(%esp), %eax +; X86-NOBMI-NEXT: # kill: def $cl killed $cl killed $ecx +; X86-NOBMI-NEXT: shrdl %cl, %esi, %edx +; X86-NOBMI-NEXT: notl %edx +; X86-NOBMI-NEXT: andl {{[0-9]+}}(%esp), %edx +; X86-NOBMI-NEXT: popl %esi +; X86-NOBMI-NEXT: retl ; -; X64-LABEL: andnot_rotr_i64: -; X64: # %bb.0: -; X64-NEXT: movq %rdx, %rcx -; X64-NEXT: movq %rsi, %rax -; X64-NEXT: notq %rax -; X64-NEXT: # kill: def $cl killed $cl killed $rcx -; X64-NEXT: rorq %cl, %rax -; X64-NEXT: andq %rdi, %rax -; X64-NEXT: retq +; X86-BMI-LABEL: andnot_rotr_i64: +; X86-BMI: # %bb.0: +; X86-BMI-NEXT: pushl %esi +; X86-BMI-NEXT: movl {{[0-9]+}}(%esp), %eax +; X86-BMI-NEXT: movl {{[0-9]+}}(%esp), %edx +; X86-BMI-NEXT: movl {{[0-9]+}}(%esp), %ecx +; X86-BMI-NEXT: testb $32, %cl +; X86-BMI-NEXT: je .LBB5_1 +; X86-BMI-NEXT: # %bb.2: +; X86-BMI-NEXT: movl %eax, %esi +; X86-BMI-NEXT: jmp .LBB5_3 +; X86-BMI-NEXT: .LBB5_1: +; X86-BMI-NEXT: movl %edx, %esi +; X86-BMI-NEXT: movl %eax, %edx +; X86-BMI-NEXT: .LBB5_3: +; X86-BMI-NEXT: movl %edx, %eax +; X86-BMI-NEXT: shrdl %cl, %esi, %eax +; X86-BMI-NEXT: andnl {{[0-9]+}}(%esp), %eax, %eax +; X86-BMI-NEXT: # kill: def $cl killed $cl killed $ecx +; X86-BMI-NEXT: shrdl %cl, %edx, %esi +; X86-BMI-NEXT: andnl {{[0-9]+}}(%esp), %esi, %edx +; X86-BMI-NEXT: popl %esi +; X86-BMI-NEXT: retl +; +; X64-NOBMI-LABEL: andnot_rotr_i64: +; X64-NOBMI: # %bb.0: +; X64-NOBMI-NEXT: movq %rdx, %rcx +; X64-NOBMI-NEXT: movq %rsi, %rax +; X64-NOBMI-NEXT: # kill: def $cl killed $cl killed $rcx +; X64-NOBMI-NEXT: rorq %cl, %rax +; X64-NOBMI-NEXT: notq %rax +; X64-NOBMI-NEXT: andq %rdi, %rax +; X64-NOBMI-NEXT: retq +; +; X64-BMI-LABEL: andnot_rotr_i64: +; X64-BMI: # %bb.0: +; X64-BMI-NEXT: movq %rdx, %rcx +; X64-BMI-NEXT: # kill: def $cl killed $cl killed $rcx +; X64-BMI-NEXT: rorq %cl, %rsi +; X64-BMI-NEXT: andnq %rdi, %rsi, %rax +; X64-BMI-NEXT: retq %not = xor i64 %a1, -1 %rot = tail call i64 @llvm.fshr.i64(i64 %not, i64 %not, i64 %a2) %and = and i64 %rot, %a0 @@ -240,24 +329,40 @@ define i64 @andnot_rotr_i64(i64 %a0, i64 %a1, i64 %a2) nounwind { } define i32 @andnot_rotr_i32(i32 %a0, i32 %a1, i32 %a2) nounwind { -; X86-LABEL: andnot_rotr_i32: -; X86: # %bb.0: -; X86-NEXT: movzbl {{[0-9]+}}(%esp), %ecx -; X86-NEXT: movl {{[0-9]+}}(%esp), %eax -; X86-NEXT: notl %eax -; X86-NEXT: rorl %cl, %eax -; X86-NEXT: andl {{[0-9]+}}(%esp), %eax -; X86-NEXT: retl +; X86-NOBMI-LABEL: andnot_rotr_i32: +; X86-NOBMI: # %bb.0: +; X86-NOBMI-NEXT: movzbl {{[0-9]+}}(%esp), %ecx +; X86-NOBMI-NEXT: movl {{[0-9]+}}(%esp), %eax +; X86-NOBMI-NEXT: rorl %cl, %eax +; X86-NOBMI-NEXT: notl %eax +; X86-NOBMI-NEXT: andl {{[0-9]+}}(%esp), %eax +; X86-NOBMI-NEXT: retl ; -; X64-LABEL: andnot_rotr_i32: -; X64: # %bb.0: -; X64-NEXT: movl %edx, %ecx -; X64-NEXT: movl %esi, %eax -; X64-NEXT: notl %eax -; X64-NEXT: # kill: def $cl killed $cl killed $ecx -; X64-NEXT: rorl %cl, %eax -; X64-NEXT: andl %edi, %eax -; X64-NEXT: retq +; X86-BMI-LABEL: andnot_rotr_i32: +; X86-BMI: # %bb.0: +; X86-BMI-NEXT: movzbl {{[0-9]+}}(%esp), %ecx +; X86-BMI-NEXT: movl {{[0-9]+}}(%esp), %eax +; X86-BMI-NEXT: rorl %cl, %eax +; X86-BMI-NEXT: andnl {{[0-9]+}}(%esp), %eax, %eax +; X86-BMI-NEXT: retl +; +; X64-NOBMI-LABEL: andnot_rotr_i32: +; X64-NOBMI: # %bb.0: +; X64-NOBMI-NEXT: movl %edx, %ecx +; X64-NOBMI-NEXT: movl %esi, %eax +; X64-NOBMI-NEXT: # kill: def $cl killed $cl killed $ecx +; X64-NOBMI-NEXT: rorl %cl, %eax +; X64-NOBMI-NEXT: notl %eax +; X64-NOBMI-NEXT: andl %edi, %eax +; X64-NOBMI-NEXT: retq +; +; X64-BMI-LABEL: andnot_rotr_i32: +; X64-BMI: # %bb.0: +; X64-BMI-NEXT: movl %edx, %ecx +; X64-BMI-NEXT: # kill: def $cl killed $cl killed $ecx +; X64-BMI-NEXT: rorl %cl, %esi +; X64-BMI-NEXT: andnl %edi, %esi, %eax +; X64-BMI-NEXT: retq %not = xor i32 %a1, -1 %rot = tail call i32 @llvm.fshr.i32(i32 %not, i32 %not, i32 %a2) %and = and i32 %rot, %a0 @@ -268,23 +373,32 @@ define i16 @andnot_rotr_i16(i16 %a0, i16 %a1, i16 %a2) nounwind { ; X86-LABEL: andnot_rotr_i16: ; X86: # %bb.0: ; X86-NEXT: movzbl {{[0-9]+}}(%esp), %ecx -; X86-NEXT: movl {{[0-9]+}}(%esp), %eax -; X86-NEXT: notl %eax +; X86-NEXT: movzwl {{[0-9]+}}(%esp), %eax ; X86-NEXT: rorw %cl, %ax +; X86-NEXT: notl %eax ; X86-NEXT: andw {{[0-9]+}}(%esp), %ax ; X86-NEXT: # kill: def $ax killed $ax killed $eax ; X86-NEXT: retl ; -; X64-LABEL: andnot_rotr_i16: -; X64: # %bb.0: -; X64-NEXT: movl %edx, %ecx -; X64-NEXT: movl %esi, %eax -; X64-NEXT: notl %eax -; X64-NEXT: # kill: def $cl killed $cl killed $ecx -; X64-NEXT: rorw %cl, %ax -; X64-NEXT: andl %edi, %eax -; X64-NEXT: # kill: def $ax killed $ax killed $eax -; X64-NEXT: retq +; X64-NOBMI-LABEL: andnot_rotr_i16: +; X64-NOBMI: # %bb.0: +; X64-NOBMI-NEXT: movl %edx, %ecx +; X64-NOBMI-NEXT: movl %esi, %eax +; X64-NOBMI-NEXT: # kill: def $cl killed $cl killed $ecx +; X64-NOBMI-NEXT: rorw %cl, %ax +; X64-NOBMI-NEXT: notl %eax +; X64-NOBMI-NEXT: andl %edi, %eax +; X64-NOBMI-NEXT: # kill: def $ax killed $ax killed $eax +; X64-NOBMI-NEXT: retq +; +; X64-BMI-LABEL: andnot_rotr_i16: +; X64-BMI: # %bb.0: +; X64-BMI-NEXT: movl %edx, %ecx +; X64-BMI-NEXT: # kill: def $cl killed $cl killed $ecx +; X64-BMI-NEXT: rorw %cl, %si +; X64-BMI-NEXT: andnl %edi, %esi, %eax +; X64-BMI-NEXT: # kill: def $ax killed $ax killed $eax +; X64-BMI-NEXT: retq %not = xor i16 %a1, -1 %rot = tail call i16 @llvm.fshr.i16(i16 %not, i16 %not, i16 %a2) %and = and i16 %rot, %a0 @@ -296,8 +410,8 @@ define i8 @andnot_rotr_i8(i8 %a0, i8 %a1, i8 %a2) nounwind { ; X86: # %bb.0: ; X86-NEXT: movzbl {{[0-9]+}}(%esp), %ecx ; X86-NEXT: movzbl {{[0-9]+}}(%esp), %eax -; X86-NEXT: notb %al ; X86-NEXT: rorb %cl, %al +; X86-NEXT: notb %al ; X86-NEXT: andb {{[0-9]+}}(%esp), %al ; X86-NEXT: retl ; @@ -305,9 +419,9 @@ define i8 @andnot_rotr_i8(i8 %a0, i8 %a1, i8 %a2) nounwind { ; X64: # %bb.0: ; X64-NEXT: movl %edx, %ecx ; X64-NEXT: movl %esi, %eax -; X64-NEXT: notb %al ; X64-NEXT: # kill: def $cl killed $cl killed $ecx ; X64-NEXT: rorb %cl, %al +; X64-NEXT: notb %al ; X64-NEXT: andb %dil, %al ; X64-NEXT: # kill: def $al killed $al killed $eax ; X64-NEXT: retq @@ -318,36 +432,67 @@ define i8 @andnot_rotr_i8(i8 %a0, i8 %a1, i8 %a2) nounwind { } define i32 @andnot_rotr_i32_multiuse_not(i32 %a0, i32 %a1, i32 %a2) nounwind { -; X86-LABEL: andnot_rotr_i32_multiuse_not: -; X86: # %bb.0: -; X86-NEXT: pushl %esi -; X86-NEXT: movzbl {{[0-9]+}}(%esp), %ecx -; X86-NEXT: movl {{[0-9]+}}(%esp), %eax -; X86-NEXT: notl %eax -; X86-NEXT: movl %eax, %esi -; X86-NEXT: rorl %cl, %esi -; X86-NEXT: andl {{[0-9]+}}(%esp), %esi -; X86-NEXT: pushl %eax -; X86-NEXT: calll use_i32@PLT -; X86-NEXT: addl $4, %esp -; X86-NEXT: movl %esi, %eax -; X86-NEXT: popl %esi -; X86-NEXT: retl +; X86-NOBMI-LABEL: andnot_rotr_i32_multiuse_not: +; X86-NOBMI: # %bb.0: +; X86-NOBMI-NEXT: pushl %esi +; X86-NOBMI-NEXT: movzbl {{[0-9]+}}(%esp), %ecx +; X86-NOBMI-NEXT: movl {{[0-9]+}}(%esp), %eax +; X86-NOBMI-NEXT: notl %eax +; X86-NOBMI-NEXT: movl %eax, %esi +; X86-NOBMI-NEXT: rorl %cl, %esi +; X86-NOBMI-NEXT: andl {{[0-9]+}}(%esp), %esi +; X86-NOBMI-NEXT: pushl %eax +; X86-NOBMI-NEXT: calll use_i32@PLT +; X86-NOBMI-NEXT: addl $4, %esp +; X86-NOBMI-NEXT: movl %esi, %eax +; X86-NOBMI-NEXT: popl %esi +; X86-NOBMI-NEXT: retl ; -; X64-LABEL: andnot_rotr_i32_multiuse_not: -; X64: # %bb.0: -; X64-NEXT: pushq %rbx -; X64-NEXT: movl %edx, %ecx -; X64-NEXT: notl %esi -; X64-NEXT: movl %esi, %ebx -; X64-NEXT: # kill: def $cl killed $cl killed $ecx -; X64-NEXT: rorl %cl, %ebx -; X64-NEXT: andl %edi, %ebx -; X64-NEXT: movl %esi, %edi -; X64-NEXT: callq use_i32@PLT -; X64-NEXT: movl %ebx, %eax -; X64-NEXT: popq %rbx -; X64-NEXT: retq +; X86-BMI-LABEL: andnot_rotr_i32_multiuse_not: +; X86-BMI: # %bb.0: +; X86-BMI-NEXT: pushl %esi +; X86-BMI-NEXT: movzbl {{[0-9]+}}(%esp), %ecx +; X86-BMI-NEXT: movl {{[0-9]+}}(%esp), %eax +; X86-BMI-NEXT: movl %eax, %edx +; X86-BMI-NEXT: notl %edx +; X86-BMI-NEXT: rorl %cl, %eax +; X86-BMI-NEXT: andnl {{[0-9]+}}(%esp), %eax, %esi +; X86-BMI-NEXT: pushl %edx +; X86-BMI-NEXT: calll use_i32@PLT +; X86-BMI-NEXT: addl $4, %esp +; X86-BMI-NEXT: movl %esi, %eax +; X86-BMI-NEXT: popl %esi +; X86-BMI-NEXT: retl +; +; X64-NOBMI-LABEL: andnot_rotr_i32_multiuse_not: +; X64-NOBMI: # %bb.0: +; X64-NOBMI-NEXT: pushq %rbx +; X64-NOBMI-NEXT: movl %edx, %ecx +; X64-NOBMI-NEXT: notl %esi +; X64-NOBMI-NEXT: movl %esi, %ebx +; X64-NOBMI-NEXT: # kill: def $cl killed $cl killed $ecx +; X64-NOBMI-NEXT: rorl %cl, %ebx +; X64-NOBMI-NEXT: andl %edi, %ebx +; X64-NOBMI-NEXT: movl %esi, %edi +; X64-NOBMI-NEXT: callq use_i32@PLT +; X64-NOBMI-NEXT: movl %ebx, %eax +; X64-NOBMI-NEXT: popq %rbx +; X64-NOBMI-NEXT: retq +; +; X64-BMI-LABEL: andnot_rotr_i32_multiuse_not: +; X64-BMI: # %bb.0: +; X64-BMI-NEXT: pushq %rbx +; X64-BMI-NEXT: movl %edx, %ecx +; X64-BMI-NEXT: movl %esi, %eax +; X64-BMI-NEXT: notl %eax +; X64-BMI-NEXT: # kill: def $cl killed $cl killed $ecx +; X64-BMI-NEXT: rorl %cl, %esi +; X64-BMI-NEXT: andnl %edi, %esi, %ebx +; X64-BMI-NEXT: movl %eax, %edi +; X64-BMI-NEXT: callq use_i32@PLT +; X64-BMI-NEXT: movl %ebx, %eax +; X64-BMI-NEXT: popq %rbx +; X64-BMI-NEXT: retq %not = xor i32 %a1, -1 %rot = tail call i32 @llvm.fshr.i32(i32 %not, i32 %not, i32 %a2) %and = and i32 %rot, %a0 diff --git a/llvm/test/CodeGen/X86/avx10_2-cmp.ll b/llvm/test/CodeGen/X86/avx10_2-cmp.ll new file mode 100644 index 00000000000000..de0bec7ea2695a --- /dev/null +++ b/llvm/test/CodeGen/X86/avx10_2-cmp.ll @@ -0,0 +1,237 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5 +; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx10.2-256 | FileCheck %s --check-prefix=X64 +; RUN: llc < %s -mtriple=i386-unknown-unknown -mattr=+avx10.2-256 | FileCheck %s --check-prefix=X86 + +define i1 @hoeq(half %x, half %y) { +; X64-LABEL: hoeq: +; X64: # %bb.0: +; X64-NEXT: vucomxsh %xmm1, %xmm0 +; X64-NEXT: sete %al +; X64-NEXT: retq +; +; X86-LABEL: hoeq: +; X86: # %bb.0: +; X86-NEXT: vmovsh {{.*#+}} xmm0 = mem[0],zero,zero,zero,zero,zero,zero,zero +; X86-NEXT: vucomxsh {{[0-9]+}}(%esp), %xmm0 +; X86-NEXT: sete %al +; X86-NEXT: retl + %1 = fcmp oeq half %x, %y + ret i1 %1 +} + +define i1 @hune(half %x, half %y) { +; X64-LABEL: hune: +; X64: # %bb.0: +; X64-NEXT: vucomxsh %xmm1, %xmm0 +; X64-NEXT: setne %al +; X64-NEXT: retq +; +; X86-LABEL: hune: +; X86: # %bb.0: +; X86-NEXT: vmovsh {{.*#+}} xmm0 = mem[0],zero,zero,zero,zero,zero,zero,zero +; X86-NEXT: vucomxsh {{[0-9]+}}(%esp), %xmm0 +; X86-NEXT: setne %al +; X86-NEXT: retl + %1 = fcmp une half %x, %y + ret i1 %1 +} + +define i1 @hoeq_mem(ptr %xp, ptr %yp) { +; X64-LABEL: hoeq_mem: +; X64: # %bb.0: +; X64-NEXT: vmovsh {{.*#+}} xmm0 = mem[0],zero,zero,zero,zero,zero,zero,zero +; X64-NEXT: vucomxsh (%rsi), %xmm0 +; X64-NEXT: sete %al +; X64-NEXT: retq +; +; X86-LABEL: hoeq_mem: +; X86: # %bb.0: +; X86-NEXT: movl {{[0-9]+}}(%esp), %eax +; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx +; X86-NEXT: vmovsh {{.*#+}} xmm0 = mem[0],zero,zero,zero,zero,zero,zero,zero +; X86-NEXT: vucomxsh (%eax), %xmm0 +; X86-NEXT: sete %al +; X86-NEXT: retl + %x = load half, ptr %xp + %y = load half, ptr %yp + %1 = fcmp oeq half %x, %y + ret i1 %1 +} + +define i1 @hune_mem(ptr %xp, ptr %yp) { +; X64-LABEL: hune_mem: +; X64: # %bb.0: +; X64-NEXT: vmovsh {{.*#+}} xmm0 = mem[0],zero,zero,zero,zero,zero,zero,zero +; X64-NEXT: vucomxsh (%rsi), %xmm0 +; X64-NEXT: setne %al +; X64-NEXT: retq +; +; X86-LABEL: hune_mem: +; X86: # %bb.0: +; X86-NEXT: movl {{[0-9]+}}(%esp), %eax +; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx +; X86-NEXT: vmovsh {{.*#+}} xmm0 = mem[0],zero,zero,zero,zero,zero,zero,zero +; X86-NEXT: vucomxsh (%eax), %xmm0 +; X86-NEXT: setne %al +; X86-NEXT: retl + %x = load half, ptr %xp + %y = load half, ptr %yp + %1 = fcmp une half %x, %y + ret i1 %1 +} + +define i1 @foeq(float %x, float %y) { +; X64-LABEL: foeq: +; X64: # %bb.0: +; X64-NEXT: vucomxss %xmm1, %xmm0 +; X64-NEXT: sete %al +; X64-NEXT: retq +; +; X86-LABEL: foeq: +; X86: # %bb.0: +; X86-NEXT: vmovss {{.*#+}} xmm0 = mem[0],zero,zero,zero +; X86-NEXT: vucomxss {{[0-9]+}}(%esp), %xmm0 +; X86-NEXT: sete %al +; X86-NEXT: retl + %1 = fcmp oeq float %x, %y + ret i1 %1 +} + +define i1 @fune(float %x, float %y) { +; X64-LABEL: fune: +; X64: # %bb.0: +; X64-NEXT: vucomxss %xmm1, %xmm0 +; X64-NEXT: setne %al +; X64-NEXT: retq +; +; X86-LABEL: fune: +; X86: # %bb.0: +; X86-NEXT: vmovss {{.*#+}} xmm0 = mem[0],zero,zero,zero +; X86-NEXT: vucomxss {{[0-9]+}}(%esp), %xmm0 +; X86-NEXT: setne %al +; X86-NEXT: retl + %1 = fcmp une float %x, %y + ret i1 %1 +} + +define i1 @foeq_mem(ptr %xp, ptr %yp) { +; X64-LABEL: foeq_mem: +; X64: # %bb.0: +; X64-NEXT: vmovss {{.*#+}} xmm0 = mem[0],zero,zero,zero +; X64-NEXT: vucomxss (%rsi), %xmm0 +; X64-NEXT: sete %al +; X64-NEXT: retq +; +; X86-LABEL: foeq_mem: +; X86: # %bb.0: +; X86-NEXT: movl {{[0-9]+}}(%esp), %eax +; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx +; X86-NEXT: vmovss {{.*#+}} xmm0 = mem[0],zero,zero,zero +; X86-NEXT: vucomxss (%eax), %xmm0 +; X86-NEXT: sete %al +; X86-NEXT: retl + %x = load float, ptr %xp + %y = load float, ptr %yp + %1 = fcmp oeq float %x, %y + ret i1 %1 +} + +define i1 @fune_mem(ptr %xp, ptr %yp) { +; X64-LABEL: fune_mem: +; X64: # %bb.0: +; X64-NEXT: vmovss {{.*#+}} xmm0 = mem[0],zero,zero,zero +; X64-NEXT: vucomxss (%rsi), %xmm0 +; X64-NEXT: setne %al +; X64-NEXT: retq +; +; X86-LABEL: fune_mem: +; X86: # %bb.0: +; X86-NEXT: movl {{[0-9]+}}(%esp), %eax +; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx +; X86-NEXT: vmovss {{.*#+}} xmm0 = mem[0],zero,zero,zero +; X86-NEXT: vucomxss (%eax), %xmm0 +; X86-NEXT: setne %al +; X86-NEXT: retl + %x = load float, ptr %xp + %y = load float, ptr %yp + %1 = fcmp une float %x, %y + ret i1 %1 +} + +define i1 @doeq(double %x, double %y) { +; X64-LABEL: doeq: +; X64: # %bb.0: +; X64-NEXT: vucomxsd %xmm1, %xmm0 +; X64-NEXT: sete %al +; X64-NEXT: retq +; +; X86-LABEL: doeq: +; X86: # %bb.0: +; X86-NEXT: vmovsd {{.*#+}} xmm0 = mem[0],zero +; X86-NEXT: vucomxsd {{[0-9]+}}(%esp), %xmm0 +; X86-NEXT: sete %al +; X86-NEXT: retl + %1 = fcmp oeq double %x, %y + ret i1 %1 +} + +define i1 @dune(double %x, double %y) { +; X64-LABEL: dune: +; X64: # %bb.0: +; X64-NEXT: vucomxsd %xmm1, %xmm0 +; X64-NEXT: setne %al +; X64-NEXT: retq +; +; X86-LABEL: dune: +; X86: # %bb.0: +; X86-NEXT: vmovsd {{.*#+}} xmm0 = mem[0],zero +; X86-NEXT: vucomxsd {{[0-9]+}}(%esp), %xmm0 +; X86-NEXT: setne %al +; X86-NEXT: retl + %1 = fcmp une double %x, %y + ret i1 %1 +} + +define i1 @doeq_mem(ptr %xp, ptr %yp) { +; X64-LABEL: doeq_mem: +; X64: # %bb.0: +; X64-NEXT: vmovsd {{.*#+}} xmm0 = mem[0],zero +; X64-NEXT: vucomxsd (%rsi), %xmm0 +; X64-NEXT: sete %al +; X64-NEXT: retq +; +; X86-LABEL: doeq_mem: +; X86: # %bb.0: +; X86-NEXT: movl {{[0-9]+}}(%esp), %eax +; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx +; X86-NEXT: vmovsd {{.*#+}} xmm0 = mem[0],zero +; X86-NEXT: vucomxsd (%eax), %xmm0 +; X86-NEXT: sete %al +; X86-NEXT: retl + %x = load double, ptr %xp + %y = load double, ptr %yp + %1 = fcmp oeq double %x, %y + ret i1 %1 +} + +define i1 @dune_mem(ptr %xp, ptr %yp) { +; X64-LABEL: dune_mem: +; X64: # %bb.0: +; X64-NEXT: vmovsd {{.*#+}} xmm0 = mem[0],zero +; X64-NEXT: vucomxsd (%rsi), %xmm0 +; X64-NEXT: setne %al +; X64-NEXT: retq +; +; X86-LABEL: dune_mem: +; X86: # %bb.0: +; X86-NEXT: movl {{[0-9]+}}(%esp), %eax +; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx +; X86-NEXT: vmovsd {{.*#+}} xmm0 = mem[0],zero +; X86-NEXT: vucomxsd (%eax), %xmm0 +; X86-NEXT: setne %al +; X86-NEXT: retl + %x = load double, ptr %xp + %y = load double, ptr %yp + %1 = fcmp une double %x, %y + ret i1 %1 +} diff --git a/llvm/test/CodeGen/X86/avx10_2_512bf16-intrinsics.ll b/llvm/test/CodeGen/X86/avx10_2_512bf16-intrinsics.ll index 7b81d547db085c..5f2bcf0556b021 100644 --- a/llvm/test/CodeGen/X86/avx10_2_512bf16-intrinsics.ll +++ b/llvm/test/CodeGen/X86/avx10_2_512bf16-intrinsics.ll @@ -76,13 +76,15 @@ declare <32 x i1> @llvm.x86.avx10.fpclass.nepbf16.512(<32 x bfloat>, i32) define i32 @test_int_x86_avx512_fpclass_nepbf16_512(<32 x bfloat> %x0) { ; CHECK-LABEL: test_int_x86_avx512_fpclass_nepbf16_512: ; CHECK: # %bb.0: -; CHECK-NEXT: vfpclasspbf16 $2, %zmm0, %k1 # encoding: [0x62,0xf3,0x7f,0x48,0x66,0xc8,0x02] -; CHECK-NEXT: vfpclasspbf16 $4, %zmm0, %k0 {%k1} # encoding: [0x62,0xf3,0x7f,0x49,0x66,0xc0,0x04] +; CHECK-NEXT: vfpclasspbf16 $6, %zmm0, %k1 # encoding: [0x62,0xf3,0x7f,0x48,0x66,0xc8,0x06] +; CHECK-NEXT: # k1 = isPositiveZero(zmm0) | isNegativeZero(zmm0) +; CHECK-NEXT: vfpclasspbf16 $0, %zmm0, %k0 {%k1} # encoding: [0x62,0xf3,0x7f,0x49,0x66,0xc0,0x00] +; CHECK-NEXT: # k0 {%k1} = false ; CHECK-NEXT: kmovd %k0, %eax # encoding: [0xc5,0xfb,0x93,0xc0] ; CHECK-NEXT: vzeroupper # encoding: [0xc5,0xf8,0x77] ; CHECK-NEXT: ret{{[l|q]}} # encoding: [0xc3] - %res = call <32 x i1> @llvm.x86.avx10.fpclass.nepbf16.512(<32 x bfloat> %x0, i32 4) - %res1 = call <32 x i1> @llvm.x86.avx10.fpclass.nepbf16.512(<32 x bfloat> %x0, i32 2) + %res = call <32 x i1> @llvm.x86.avx10.fpclass.nepbf16.512(<32 x bfloat> %x0, i32 0) + %res1 = call <32 x i1> @llvm.x86.avx10.fpclass.nepbf16.512(<32 x bfloat> %x0, i32 6) %1 = and <32 x i1> %res1, %res %2 = bitcast <32 x i1> %1 to i32 ret i32 %2 diff --git a/llvm/test/CodeGen/X86/avx10_2bf16-intrinsics.ll b/llvm/test/CodeGen/X86/avx10_2bf16-intrinsics.ll index 559d866b55cc7b..59151d4dd96099 100644 --- a/llvm/test/CodeGen/X86/avx10_2bf16-intrinsics.ll +++ b/llvm/test/CodeGen/X86/avx10_2bf16-intrinsics.ll @@ -298,6 +298,7 @@ define i8 @test_int_x86_avx512_fpclass_nepbf16_128(<8 x bfloat> %x0) { ; CHECK-LABEL: test_int_x86_avx512_fpclass_nepbf16_128: ; CHECK: # %bb.0: ; CHECK-NEXT: vfpclasspbf16 $2, %xmm0, %k1 # encoding: [0x62,0xf3,0x7f,0x08,0x66,0xc8,0x02] +; CHECK-NEXT: # k1 = isPositiveZero(xmm0) ; CHECK-NEXT: vfpclasspbf16 $4, %xmm0, %k0 {%k1} # encoding: [0x62,0xf3,0x7f,0x09,0x66,0xc0,0x04] ; CHECK-NEXT: kmovd %k0, %eax # encoding: [0xc5,0xfb,0x93,0xc0] ; CHECK-NEXT: # kill: def $al killed $al killed $eax @@ -313,6 +314,7 @@ define i16 @test_int_x86_avx512_fpclass_nepbf16_256(<16 x bfloat> %x0) { ; CHECK-LABEL: test_int_x86_avx512_fpclass_nepbf16_256: ; CHECK: # %bb.0: ; CHECK-NEXT: vfpclasspbf16 $2, %ymm0, %k1 # encoding: [0x62,0xf3,0x7f,0x28,0x66,0xc8,0x02] +; CHECK-NEXT: # k1 = isPositiveZero(ymm0) ; CHECK-NEXT: vfpclasspbf16 $4, %ymm0, %k0 {%k1} # encoding: [0x62,0xf3,0x7f,0x29,0x66,0xc0,0x04] ; CHECK-NEXT: kmovd %k0, %eax # encoding: [0xc5,0xfb,0x93,0xc0] ; CHECK-NEXT: # kill: def $ax killed $ax killed $eax diff --git a/llvm/test/CodeGen/X86/avx512dq-intrinsics-fast-isel.ll b/llvm/test/CodeGen/X86/avx512dq-intrinsics-fast-isel.ll index 64063bdf8333eb..53193597d62f08 100644 --- a/llvm/test/CodeGen/X86/avx512dq-intrinsics-fast-isel.ll +++ b/llvm/test/CodeGen/X86/avx512dq-intrinsics-fast-isel.ll @@ -7,7 +7,7 @@ define zeroext i8 @test_mm512_mask_fpclass_pd_mask(i8 zeroext %__U, <8 x double> %__A) { ; X86-LABEL: test_mm512_mask_fpclass_pd_mask: ; X86: # %bb.0: # %entry -; X86-NEXT: vfpclasspd $4, %zmm0, %k0 +; X86-NEXT: vfpclasspd $4, %zmm0, %k0 # k0 = isNegativeZero(zmm0) ; X86-NEXT: kmovw %k0, %eax ; X86-NEXT: andb {{[0-9]+}}(%esp), %al ; X86-NEXT: # kill: def $al killed $al killed $eax @@ -16,7 +16,7 @@ define zeroext i8 @test_mm512_mask_fpclass_pd_mask(i8 zeroext %__U, <8 x double> ; ; X64-LABEL: test_mm512_mask_fpclass_pd_mask: ; X64: # %bb.0: # %entry -; X64-NEXT: vfpclasspd $4, %zmm0, %k0 +; X64-NEXT: vfpclasspd $4, %zmm0, %k0 # k0 = isNegativeZero(zmm0) ; X64-NEXT: kmovw %k0, %eax ; X64-NEXT: andb %dil, %al ; X64-NEXT: # kill: def $al killed $al killed $eax @@ -35,7 +35,7 @@ declare <8 x i1> @llvm.x86.avx512.fpclass.pd.512(<8 x double>, i32) define zeroext i8 @test_mm512_fpclass_pd_mask(<8 x double> %__A) { ; CHECK-LABEL: test_mm512_fpclass_pd_mask: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vfpclasspd $4, %zmm0, %k0 +; CHECK-NEXT: vfpclasspd $4, %zmm0, %k0 # k0 = isNegativeZero(zmm0) ; CHECK-NEXT: kmovw %k0, %eax ; CHECK-NEXT: # kill: def $al killed $al killed $eax ; CHECK-NEXT: vzeroupper @@ -49,7 +49,7 @@ entry: define zeroext i16 @test_mm512_mask_fpclass_ps_mask(i16 zeroext %__U, <16 x float> %__A) { ; X86-LABEL: test_mm512_mask_fpclass_ps_mask: ; X86: # %bb.0: # %entry -; X86-NEXT: vfpclassps $4, %zmm0, %k0 +; X86-NEXT: vfpclassps $4, %zmm0, %k0 # k0 = isNegativeZero(zmm0) ; X86-NEXT: kmovw %k0, %eax ; X86-NEXT: andw {{[0-9]+}}(%esp), %ax ; X86-NEXT: # kill: def $ax killed $ax killed $eax @@ -58,7 +58,7 @@ define zeroext i16 @test_mm512_mask_fpclass_ps_mask(i16 zeroext %__U, <16 x floa ; ; X64-LABEL: test_mm512_mask_fpclass_ps_mask: ; X64: # %bb.0: # %entry -; X64-NEXT: vfpclassps $4, %zmm0, %k0 +; X64-NEXT: vfpclassps $4, %zmm0, %k0 # k0 = isNegativeZero(zmm0) ; X64-NEXT: kmovw %k0, %eax ; X64-NEXT: andl %edi, %eax ; X64-NEXT: # kill: def $ax killed $ax killed $eax @@ -77,7 +77,7 @@ declare <16 x i1> @llvm.x86.avx512.fpclass.ps.512(<16 x float>, i32) define zeroext i16 @test_mm512_fpclass_ps_mask(<16 x float> %__A) { ; CHECK-LABEL: test_mm512_fpclass_ps_mask: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vfpclassps $4, %zmm0, %k0 +; CHECK-NEXT: vfpclassps $4, %zmm0, %k0 # k0 = isNegativeZero(zmm0) ; CHECK-NEXT: kmovw %k0, %eax ; CHECK-NEXT: # kill: def $ax killed $ax killed $eax ; CHECK-NEXT: vzeroupper @@ -91,7 +91,7 @@ entry: define zeroext i8 @test_mm_fpclass_sd_mask(<4 x float> %__A) { ; CHECK-LABEL: test_mm_fpclass_sd_mask: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vfpclasssd $2, %xmm0, %k0 +; CHECK-NEXT: vfpclasssd $2, %xmm0, %k0 # k0 = isPositiveZero(xmm0) ; CHECK-NEXT: kmovw %k0, %eax ; CHECK-NEXT: # kill: def $al killed $al killed $eax ; CHECK-NEXT: ret{{[l|q]}} @@ -107,7 +107,7 @@ define zeroext i8 @test_mm_mask_fpclass_sd_mask(i8 zeroext %__U, <4 x float> %__ ; X86-LABEL: test_mm_mask_fpclass_sd_mask: ; X86: # %bb.0: # %entry ; X86-NEXT: kmovb {{[0-9]+}}(%esp), %k1 -; X86-NEXT: vfpclasssd $2, %xmm0, %k0 {%k1} +; X86-NEXT: vfpclasssd $2, %xmm0, %k0 {%k1} # k0 {%k1} = isPositiveZero(xmm0) ; X86-NEXT: kmovw %k0, %eax ; X86-NEXT: # kill: def $al killed $al killed $eax ; X86-NEXT: retl @@ -115,7 +115,7 @@ define zeroext i8 @test_mm_mask_fpclass_sd_mask(i8 zeroext %__U, <4 x float> %__ ; X64-LABEL: test_mm_mask_fpclass_sd_mask: ; X64: # %bb.0: # %entry ; X64-NEXT: kmovw %edi, %k1 -; X64-NEXT: vfpclasssd $2, %xmm0, %k0 {%k1} +; X64-NEXT: vfpclasssd $2, %xmm0, %k0 {%k1} # k0 {%k1} = isPositiveZero(xmm0) ; X64-NEXT: kmovw %k0, %eax ; X64-NEXT: # kill: def $al killed $al killed $eax ; X64-NEXT: retq @@ -128,7 +128,7 @@ entry: define zeroext i8 @test_mm_fpclass_ss_mask(<4 x float> %__A) { ; CHECK-LABEL: test_mm_fpclass_ss_mask: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vfpclassss $2, %xmm0, %k0 +; CHECK-NEXT: vfpclassss $2, %xmm0, %k0 # k0 = isPositiveZero(xmm0) ; CHECK-NEXT: kmovw %k0, %eax ; CHECK-NEXT: # kill: def $al killed $al killed $eax ; CHECK-NEXT: ret{{[l|q]}} @@ -143,7 +143,7 @@ define zeroext i8 @test_mm_mask_fpclass_ss_mask(i8 zeroext %__U, <4 x float> %__ ; X86-LABEL: test_mm_mask_fpclass_ss_mask: ; X86: # %bb.0: # %entry ; X86-NEXT: kmovb {{[0-9]+}}(%esp), %k1 -; X86-NEXT: vfpclassss $2, %xmm0, %k0 {%k1} +; X86-NEXT: vfpclassss $2, %xmm0, %k0 {%k1} # k0 {%k1} = isPositiveZero(xmm0) ; X86-NEXT: kmovw %k0, %eax ; X86-NEXT: # kill: def $al killed $al killed $eax ; X86-NEXT: retl @@ -151,7 +151,7 @@ define zeroext i8 @test_mm_mask_fpclass_ss_mask(i8 zeroext %__U, <4 x float> %__ ; X64-LABEL: test_mm_mask_fpclass_ss_mask: ; X64: # %bb.0: # %entry ; X64-NEXT: kmovw %edi, %k1 -; X64-NEXT: vfpclassss $2, %xmm0, %k0 {%k1} +; X64-NEXT: vfpclassss $2, %xmm0, %k0 {%k1} # k0 {%k1} = isPositiveZero(xmm0) ; X64-NEXT: kmovw %k0, %eax ; X64-NEXT: # kill: def $al killed $al killed $eax ; X64-NEXT: retq diff --git a/llvm/test/CodeGen/X86/avx512dq-intrinsics-upgrade.ll b/llvm/test/CodeGen/X86/avx512dq-intrinsics-upgrade.ll index 23e929aa9d89b1..8a0428d022b6d7 100644 --- a/llvm/test/CodeGen/X86/avx512dq-intrinsics-upgrade.ll +++ b/llvm/test/CodeGen/X86/avx512dq-intrinsics-upgrade.ll @@ -654,7 +654,9 @@ define i8 @test_int_x86_avx512_mask_fpclass_pd_512(<8 x double> %x0) { ; CHECK-LABEL: test_int_x86_avx512_mask_fpclass_pd_512: ; CHECK: # %bb.0: ; CHECK-NEXT: vfpclasspd $2, %zmm0, %k1 # encoding: [0x62,0xf3,0xfd,0x48,0x66,0xc8,0x02] +; CHECK-NEXT: # k1 = isPositiveZero(zmm0) ; CHECK-NEXT: vfpclasspd $4, %zmm0, %k0 {%k1} # encoding: [0x62,0xf3,0xfd,0x49,0x66,0xc0,0x04] +; CHECK-NEXT: # k0 {%k1} = isNegativeZero(zmm0) ; CHECK-NEXT: kmovw %k0, %eax # encoding: [0xc5,0xf8,0x93,0xc0] ; CHECK-NEXT: # kill: def $al killed $al killed $eax ; CHECK-NEXT: vzeroupper # encoding: [0xc5,0xf8,0x77] @@ -669,7 +671,9 @@ define i16@test_int_x86_avx512_mask_fpclass_ps_512(<16 x float> %x0) { ; CHECK-LABEL: test_int_x86_avx512_mask_fpclass_ps_512: ; CHECK: # %bb.0: ; CHECK-NEXT: vfpclassps $2, %zmm0, %k1 # encoding: [0x62,0xf3,0x7d,0x48,0x66,0xc8,0x02] +; CHECK-NEXT: # k1 = isPositiveZero(zmm0) ; CHECK-NEXT: vfpclassps $4, %zmm0, %k0 {%k1} # encoding: [0x62,0xf3,0x7d,0x49,0x66,0xc0,0x04] +; CHECK-NEXT: # k0 {%k1} = isNegativeZero(zmm0) ; CHECK-NEXT: kmovw %k0, %eax # encoding: [0xc5,0xf8,0x93,0xc0] ; CHECK-NEXT: # kill: def $ax killed $ax killed $eax ; CHECK-NEXT: vzeroupper # encoding: [0xc5,0xf8,0x77] diff --git a/llvm/test/CodeGen/X86/avx512dq-intrinsics.ll b/llvm/test/CodeGen/X86/avx512dq-intrinsics.ll index 027bca9c8badf9..70f60c802a2d52 100644 --- a/llvm/test/CodeGen/X86/avx512dq-intrinsics.ll +++ b/llvm/test/CodeGen/X86/avx512dq-intrinsics.ll @@ -726,7 +726,9 @@ define i8 @test_int_x86_avx512_fpclass_pd_512(<8 x double> %x0) { ; CHECK-LABEL: test_int_x86_avx512_fpclass_pd_512: ; CHECK: # %bb.0: ; CHECK-NEXT: vfpclasspd $2, %zmm0, %k1 # encoding: [0x62,0xf3,0xfd,0x48,0x66,0xc8,0x02] +; CHECK-NEXT: # k1 = isPositiveZero(zmm0) ; CHECK-NEXT: vfpclasspd $4, %zmm0, %k0 {%k1} # encoding: [0x62,0xf3,0xfd,0x49,0x66,0xc0,0x04] +; CHECK-NEXT: # k0 {%k1} = isNegativeZero(zmm0) ; CHECK-NEXT: kmovw %k0, %eax # encoding: [0xc5,0xf8,0x93,0xc0] ; CHECK-NEXT: # kill: def $al killed $al killed $eax ; CHECK-NEXT: vzeroupper # encoding: [0xc5,0xf8,0x77] @@ -743,7 +745,9 @@ define i16@test_int_x86_avx512_fpclass_ps_512(<16 x float> %x0) { ; CHECK-LABEL: test_int_x86_avx512_fpclass_ps_512: ; CHECK: # %bb.0: ; CHECK-NEXT: vfpclassps $2, %zmm0, %k1 # encoding: [0x62,0xf3,0x7d,0x48,0x66,0xc8,0x02] +; CHECK-NEXT: # k1 = isPositiveZero(zmm0) ; CHECK-NEXT: vfpclassps $4, %zmm0, %k0 {%k1} # encoding: [0x62,0xf3,0x7d,0x49,0x66,0xc0,0x04] +; CHECK-NEXT: # k0 {%k1} = isNegativeZero(zmm0) ; CHECK-NEXT: kmovw %k0, %eax # encoding: [0xc5,0xf8,0x93,0xc0] ; CHECK-NEXT: # kill: def $ax killed $ax killed $eax ; CHECK-NEXT: vzeroupper # encoding: [0xc5,0xf8,0x77] @@ -761,7 +765,9 @@ define i8 @test_int_x86_avx512_mask_fpclass_sd(<2 x double> %x0) { ; CHECK-LABEL: test_int_x86_avx512_mask_fpclass_sd: ; CHECK: # %bb.0: ; CHECK-NEXT: vfpclasssd $4, %xmm0, %k1 # encoding: [0x62,0xf3,0xfd,0x08,0x67,0xc8,0x04] +; CHECK-NEXT: # k1 = isNegativeZero(xmm0) ; CHECK-NEXT: vfpclasssd $2, %xmm0, %k0 {%k1} # encoding: [0x62,0xf3,0xfd,0x09,0x67,0xc0,0x02] +; CHECK-NEXT: # k0 {%k1} = isPositiveZero(xmm0) ; CHECK-NEXT: kmovw %k0, %eax # encoding: [0xc5,0xf8,0x93,0xc0] ; CHECK-NEXT: # kill: def $al killed $al killed $eax ; CHECK-NEXT: ret{{[l|q]}} # encoding: [0xc3] @@ -775,6 +781,7 @@ define i8 @test_int_x86_avx512_mask_fpclass_sd_load(ptr %x0ptr) { ; X86: # %bb.0: ; X86-NEXT: movl {{[0-9]+}}(%esp), %eax # encoding: [0x8b,0x44,0x24,0x04] ; X86-NEXT: vfpclasssd $4, (%eax), %k0 # encoding: [0x62,0xf3,0xfd,0x08,0x67,0x00,0x04] +; X86-NEXT: # k0 = isNegativeZero(mem) ; X86-NEXT: kmovw %k0, %eax # encoding: [0xc5,0xf8,0x93,0xc0] ; X86-NEXT: # kill: def $al killed $al killed $eax ; X86-NEXT: retl # encoding: [0xc3] @@ -782,6 +789,7 @@ define i8 @test_int_x86_avx512_mask_fpclass_sd_load(ptr %x0ptr) { ; X64-LABEL: test_int_x86_avx512_mask_fpclass_sd_load: ; X64: # %bb.0: ; X64-NEXT: vfpclasssd $4, (%rdi), %k0 # encoding: [0x62,0xf3,0xfd,0x08,0x67,0x07,0x04] +; X64-NEXT: # k0 = isNegativeZero(mem) ; X64-NEXT: kmovw %k0, %eax # encoding: [0xc5,0xf8,0x93,0xc0] ; X64-NEXT: # kill: def $al killed $al killed $eax ; X64-NEXT: retq # encoding: [0xc3] @@ -796,7 +804,9 @@ define i8 @test_int_x86_avx512_mask_fpclass_ss(<4 x float> %x0) { ; CHECK-LABEL: test_int_x86_avx512_mask_fpclass_ss: ; CHECK: # %bb.0: ; CHECK-NEXT: vfpclassss $4, %xmm0, %k1 # encoding: [0x62,0xf3,0x7d,0x08,0x67,0xc8,0x04] +; CHECK-NEXT: # k1 = isNegativeZero(xmm0) ; CHECK-NEXT: vfpclassss $2, %xmm0, %k0 {%k1} # encoding: [0x62,0xf3,0x7d,0x09,0x67,0xc0,0x02] +; CHECK-NEXT: # k0 {%k1} = isPositiveZero(xmm0) ; CHECK-NEXT: kmovw %k0, %eax # encoding: [0xc5,0xf8,0x93,0xc0] ; CHECK-NEXT: # kill: def $al killed $al killed $eax ; CHECK-NEXT: ret{{[l|q]}} # encoding: [0xc3] @@ -810,6 +820,7 @@ define i8 @test_int_x86_avx512_mask_fpclass_ss_load(ptr %x0ptr, i8 %x1) { ; X86: # %bb.0: ; X86-NEXT: movl {{[0-9]+}}(%esp), %eax # encoding: [0x8b,0x44,0x24,0x04] ; X86-NEXT: vfpclassss $4, (%eax), %k0 # encoding: [0x62,0xf3,0x7d,0x08,0x67,0x00,0x04] +; X86-NEXT: # k0 = isNegativeZero(mem) ; X86-NEXT: kmovw %k0, %eax # encoding: [0xc5,0xf8,0x93,0xc0] ; X86-NEXT: # kill: def $al killed $al killed $eax ; X86-NEXT: retl # encoding: [0xc3] @@ -817,6 +828,7 @@ define i8 @test_int_x86_avx512_mask_fpclass_ss_load(ptr %x0ptr, i8 %x1) { ; X64-LABEL: test_int_x86_avx512_mask_fpclass_ss_load: ; X64: # %bb.0: ; X64-NEXT: vfpclassss $4, (%rdi), %k0 # encoding: [0x62,0xf3,0x7d,0x08,0x67,0x07,0x04] +; X64-NEXT: # k0 = isNegativeZero(mem) ; X64-NEXT: kmovw %k0, %eax # encoding: [0xc5,0xf8,0x93,0xc0] ; X64-NEXT: # kill: def $al killed $al killed $eax ; X64-NEXT: retq # encoding: [0xc3] diff --git a/llvm/test/CodeGen/X86/avx512dqvl-intrinsics-fast-isel.ll b/llvm/test/CodeGen/X86/avx512dqvl-intrinsics-fast-isel.ll index 703591acef5720..a8a38d9c481133 100644 --- a/llvm/test/CodeGen/X86/avx512dqvl-intrinsics-fast-isel.ll +++ b/llvm/test/CodeGen/X86/avx512dqvl-intrinsics-fast-isel.ll @@ -235,7 +235,7 @@ declare <2 x i1> @llvm.x86.avx512.fpclass.pd.128(<2 x double>, i32) define zeroext i8 @test_mm_fpclass_pd_mask(<2 x double> %__A) { ; CHECK-LABEL: test_mm_fpclass_pd_mask: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vfpclasspd $2, %xmm0, %k0 +; CHECK-NEXT: vfpclasspd $2, %xmm0, %k0 # k0 = isPositiveZero(xmm0) ; CHECK-NEXT: kmovw %k0, %eax ; CHECK-NEXT: # kill: def $al killed $al killed $eax ; CHECK-NEXT: ret{{[l|q]}} @@ -279,7 +279,7 @@ declare <4 x i1> @llvm.x86.avx512.fpclass.pd.256(<4 x double>, i32) define zeroext i8 @test_mm256_fpclass_pd_mask(<4 x double> %__A) { ; CHECK-LABEL: test_mm256_fpclass_pd_mask: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vfpclasspd $2, %ymm0, %k0 +; CHECK-NEXT: vfpclasspd $2, %ymm0, %k0 # k0 = isPositiveZero(ymm0) ; CHECK-NEXT: kmovw %k0, %eax ; CHECK-NEXT: # kill: def $al killed $al killed $eax ; CHECK-NEXT: vzeroupper @@ -322,7 +322,7 @@ declare <4 x i1> @llvm.x86.avx512.fpclass.ps.128(<4 x float>, i32) define zeroext i8 @test_mm_fpclass_ps_mask(<4 x float> %__A) { ; CHECK-LABEL: test_mm_fpclass_ps_mask: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vfpclassps $2, %xmm0, %k0 +; CHECK-NEXT: vfpclassps $2, %xmm0, %k0 # k0 = isPositiveZero(xmm0) ; CHECK-NEXT: kmovw %k0, %eax ; CHECK-NEXT: # kill: def $al killed $al killed $eax ; CHECK-NEXT: ret{{[l|q]}} @@ -336,7 +336,7 @@ entry: define zeroext i8 @test_mm256_mask_fpclass_ps_mask(i8 zeroext %__U, <8 x float> %__A) { ; X86-LABEL: test_mm256_mask_fpclass_ps_mask: ; X86: # %bb.0: # %entry -; X86-NEXT: vfpclassps $2, %ymm0, %k0 +; X86-NEXT: vfpclassps $2, %ymm0, %k0 # k0 = isPositiveZero(ymm0) ; X86-NEXT: kmovw %k0, %eax ; X86-NEXT: andb {{[0-9]+}}(%esp), %al ; X86-NEXT: # kill: def $al killed $al killed $eax @@ -345,7 +345,7 @@ define zeroext i8 @test_mm256_mask_fpclass_ps_mask(i8 zeroext %__U, <8 x float> ; ; X64-LABEL: test_mm256_mask_fpclass_ps_mask: ; X64: # %bb.0: # %entry -; X64-NEXT: vfpclassps $2, %ymm0, %k0 +; X64-NEXT: vfpclassps $2, %ymm0, %k0 # k0 = isPositiveZero(ymm0) ; X64-NEXT: kmovw %k0, %eax ; X64-NEXT: andb %dil, %al ; X64-NEXT: # kill: def $al killed $al killed $eax @@ -364,7 +364,7 @@ declare <8 x i1> @llvm.x86.avx512.fpclass.ps.256(<8 x float>, i32) define zeroext i8 @test_mm256_fpclass_ps_mask(<8 x float> %__A) { ; CHECK-LABEL: test_mm256_fpclass_ps_mask: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vfpclassps $2, %ymm0, %k0 +; CHECK-NEXT: vfpclassps $2, %ymm0, %k0 # k0 = isPositiveZero(ymm0) ; CHECK-NEXT: kmovw %k0, %eax ; CHECK-NEXT: # kill: def $al killed $al killed $eax ; CHECK-NEXT: vzeroupper diff --git a/llvm/test/CodeGen/X86/avx512dqvl-intrinsics-upgrade.ll b/llvm/test/CodeGen/X86/avx512dqvl-intrinsics-upgrade.ll index 8d609eb7fdd009..f31dafcd686269 100644 --- a/llvm/test/CodeGen/X86/avx512dqvl-intrinsics-upgrade.ll +++ b/llvm/test/CodeGen/X86/avx512dqvl-intrinsics-upgrade.ll @@ -2921,6 +2921,7 @@ define i8 @test_int_x86_avx512_mask_fpclass_ps_128(<4 x float> %x0) { ; CHECK-LABEL: test_int_x86_avx512_mask_fpclass_ps_128: ; CHECK: # %bb.0: ; CHECK-NEXT: vfpclassps $4, %xmm0, %k1 # encoding: [0x62,0xf3,0x7d,0x08,0x66,0xc8,0x04] +; CHECK-NEXT: # k1 = isNegativeZero(xmm0) ; CHECK-NEXT: vfpclassps $2, %xmm0, %k0 {%k1} # encoding: [0x62,0xf3,0x7d,0x09,0x66,0xc0,0x02] ; CHECK-NEXT: kmovw %k0, %eax # encoding: [0xc5,0xf8,0x93,0xc0] ; CHECK-NEXT: # kill: def $al killed $al killed $eax @@ -2936,6 +2937,7 @@ define i8 @test_int_x86_avx512_mask_fpclass_ps_256(<8 x float> %x0) { ; CHECK-LABEL: test_int_x86_avx512_mask_fpclass_ps_256: ; CHECK: # %bb.0: ; CHECK-NEXT: vfpclassps $4, %ymm0, %k1 # encoding: [0x62,0xf3,0x7d,0x28,0x66,0xc8,0x04] +; CHECK-NEXT: # k1 = isNegativeZero(ymm0) ; CHECK-NEXT: vfpclassps $2, %ymm0, %k0 {%k1} # encoding: [0x62,0xf3,0x7d,0x29,0x66,0xc0,0x02] ; CHECK-NEXT: kmovw %k0, %eax # encoding: [0xc5,0xf8,0x93,0xc0] ; CHECK-NEXT: # kill: def $al killed $al killed $eax @@ -2952,6 +2954,7 @@ define i8 @test_int_x86_avx512_mask_fpclass_pd_128(<2 x double> %x0) { ; CHECK-LABEL: test_int_x86_avx512_mask_fpclass_pd_128: ; CHECK: # %bb.0: ; CHECK-NEXT: vfpclasspd $2, %xmm0, %k1 # encoding: [0x62,0xf3,0xfd,0x08,0x66,0xc8,0x02] +; CHECK-NEXT: # k1 = isPositiveZero(xmm0) ; CHECK-NEXT: vfpclasspd $4, %xmm0, %k0 {%k1} # encoding: [0x62,0xf3,0xfd,0x09,0x66,0xc0,0x04] ; CHECK-NEXT: kmovw %k0, %eax # encoding: [0xc5,0xf8,0x93,0xc0] ; CHECK-NEXT: # kill: def $al killed $al killed $eax @@ -2967,6 +2970,7 @@ define i8 @test_int_x86_avx512_mask_fpclass_pd_256(<4 x double> %x0) { ; CHECK-LABEL: test_int_x86_avx512_mask_fpclass_pd_256: ; CHECK: # %bb.0: ; CHECK-NEXT: vfpclasspd $4, %ymm0, %k1 # encoding: [0x62,0xf3,0xfd,0x28,0x66,0xc8,0x04] +; CHECK-NEXT: # k1 = isNegativeZero(ymm0) ; CHECK-NEXT: vfpclasspd $2, %ymm0, %k0 {%k1} # encoding: [0x62,0xf3,0xfd,0x29,0x66,0xc0,0x02] ; CHECK-NEXT: kmovw %k0, %eax # encoding: [0xc5,0xf8,0x93,0xc0] ; CHECK-NEXT: # kill: def $al killed $al killed $eax diff --git a/llvm/test/CodeGen/X86/avx512dqvl-intrinsics.ll b/llvm/test/CodeGen/X86/avx512dqvl-intrinsics.ll index 3b9f96ef452c32..ec94b593148dfa 100644 --- a/llvm/test/CodeGen/X86/avx512dqvl-intrinsics.ll +++ b/llvm/test/CodeGen/X86/avx512dqvl-intrinsics.ll @@ -1500,6 +1500,7 @@ define i8 @test_int_x86_avx512_fpclass_ps_128(<4 x float> %x0) { ; CHECK-LABEL: test_int_x86_avx512_fpclass_ps_128: ; CHECK: # %bb.0: ; CHECK-NEXT: vfpclassps $4, %xmm0, %k1 # encoding: [0x62,0xf3,0x7d,0x08,0x66,0xc8,0x04] +; CHECK-NEXT: # k1 = isNegativeZero(xmm0) ; CHECK-NEXT: vfpclassps $2, %xmm0, %k0 {%k1} # encoding: [0x62,0xf3,0x7d,0x09,0x66,0xc0,0x02] ; CHECK-NEXT: kmovw %k0, %eax # encoding: [0xc5,0xf8,0x93,0xc0] ; CHECK-NEXT: # kill: def $al killed $al killed $eax @@ -1518,6 +1519,7 @@ define i8 @test_int_x86_avx512_fpclass_ps_256(<8 x float> %x0) { ; CHECK-LABEL: test_int_x86_avx512_fpclass_ps_256: ; CHECK: # %bb.0: ; CHECK-NEXT: vfpclassps $4, %ymm0, %k1 # encoding: [0x62,0xf3,0x7d,0x28,0x66,0xc8,0x04] +; CHECK-NEXT: # k1 = isNegativeZero(ymm0) ; CHECK-NEXT: vfpclassps $2, %ymm0, %k0 {%k1} # encoding: [0x62,0xf3,0x7d,0x29,0x66,0xc0,0x02] ; CHECK-NEXT: kmovw %k0, %eax # encoding: [0xc5,0xf8,0x93,0xc0] ; CHECK-NEXT: # kill: def $al killed $al killed $eax @@ -1536,6 +1538,7 @@ define i8 @test_int_x86_avx512_fpclass_pd_128(<2 x double> %x0) { ; CHECK-LABEL: test_int_x86_avx512_fpclass_pd_128: ; CHECK: # %bb.0: ; CHECK-NEXT: vfpclasspd $2, %xmm0, %k1 # encoding: [0x62,0xf3,0xfd,0x08,0x66,0xc8,0x02] +; CHECK-NEXT: # k1 = isPositiveZero(xmm0) ; CHECK-NEXT: vfpclasspd $4, %xmm0, %k0 {%k1} # encoding: [0x62,0xf3,0xfd,0x09,0x66,0xc0,0x04] ; CHECK-NEXT: kmovw %k0, %eax # encoding: [0xc5,0xf8,0x93,0xc0] ; CHECK-NEXT: # kill: def $al killed $al killed $eax @@ -1554,6 +1557,7 @@ define i8 @test_int_x86_avx512_fpclass_pd_256(<4 x double> %x0) { ; CHECK-LABEL: test_int_x86_avx512_fpclass_pd_256: ; CHECK: # %bb.0: ; CHECK-NEXT: vfpclasspd $4, %ymm0, %k1 # encoding: [0x62,0xf3,0xfd,0x28,0x66,0xc8,0x04] +; CHECK-NEXT: # k1 = isNegativeZero(ymm0) ; CHECK-NEXT: vfpclasspd $2, %ymm0, %k0 {%k1} # encoding: [0x62,0xf3,0xfd,0x29,0x66,0xc0,0x02] ; CHECK-NEXT: kmovw %k0, %eax # encoding: [0xc5,0xf8,0x93,0xc0] ; CHECK-NEXT: # kill: def $al killed $al killed $eax diff --git a/llvm/test/CodeGen/X86/stack-folding-fp-avx512fp16.ll b/llvm/test/CodeGen/X86/stack-folding-fp-avx512fp16.ll index ed7109c416e7fd..9382ba31ab649d 100644 --- a/llvm/test/CodeGen/X86/stack-folding-fp-avx512fp16.ll +++ b/llvm/test/CodeGen/X86/stack-folding-fp-avx512fp16.ll @@ -234,6 +234,7 @@ define i32 @stack_fold_fpclassph(<32 x half> %a0) { ; CHECK-NEXT: nop ; CHECK-NEXT: #NO_APP ; CHECK-NEXT: vfpclassphz $4, {{[-0-9]+}}(%r{{[sb]}}p), %k0 # 64-byte Folded Reload +; CHECK-NEXT: # k0 = isNegativeZero(mem) ; CHECK-NEXT: kmovd %k0, %eax ; CHECK-NEXT: vzeroupper ; CHECK-NEXT: retq @@ -253,6 +254,7 @@ define i32 @stack_fold_fpclassph_mask(<32 x half> %a0, ptr %p) { ; CHECK-NEXT: #NO_APP ; CHECK-NEXT: kmovd (%rdi), %k1 ; CHECK-NEXT: vfpclassphz $4, {{[-0-9]+}}(%r{{[sb]}}p), %k0 {%k1} # 64-byte Folded Reload +; CHECK-NEXT: # k0 {%k1} = isNegativeZero(mem) ; CHECK-NEXT: kmovd %k0, %eax ; CHECK-NEXT: vzeroupper ; CHECK-NEXT: retq @@ -272,6 +274,7 @@ define i8 @stack_fold_fpclasssh(<8 x half> %a0) { ; CHECK-NEXT: nop ; CHECK-NEXT: #NO_APP ; CHECK-NEXT: vfpclasssh $4, {{[-0-9]+}}(%r{{[sb]}}p), %k0 # 16-byte Folded Reload +; CHECK-NEXT: # k0 = isNegativeZero(mem) ; CHECK-NEXT: kmovd %k0, %eax ; CHECK-NEXT: # kill: def $al killed $al killed $eax ; CHECK-NEXT: retq @@ -290,6 +293,7 @@ define i8 @stack_fold_fpclasssh_mask(<8 x half> %a0, ptr %p) { ; CHECK-NEXT: #NO_APP ; CHECK-NEXT: kmovb (%rdi), %k1 ; CHECK-NEXT: vfpclasssh $4, {{[-0-9]+}}(%r{{[sb]}}p), %k0 {%k1} # 16-byte Folded Reload +; CHECK-NEXT: # k0 {%k1} = isNegativeZero(mem) ; CHECK-NEXT: kmovd %k0, %eax ; CHECK-NEXT: # kill: def $al killed $al killed $eax ; CHECK-NEXT: retq diff --git a/llvm/test/CodeGen/X86/stack-folding-fp-avx512fp16vl.ll b/llvm/test/CodeGen/X86/stack-folding-fp-avx512fp16vl.ll index e2ed997783f59b..3386f4a9b51981 100644 --- a/llvm/test/CodeGen/X86/stack-folding-fp-avx512fp16vl.ll +++ b/llvm/test/CodeGen/X86/stack-folding-fp-avx512fp16vl.ll @@ -110,6 +110,7 @@ define i8 @stack_fold_fpclassph(<8 x half> %a0) { ; CHECK-NEXT: nop ; CHECK-NEXT: #NO_APP ; CHECK-NEXT: vfpclassphx $4, {{[-0-9]+}}(%r{{[sb]}}p), %k0 # 16-byte Folded Reload +; CHECK-NEXT: # k0 = isNegativeZero(mem) ; CHECK-NEXT: kmovd %k0, %eax ; CHECK-NEXT: # kill: def $al killed $al killed $eax ; CHECK-NEXT: retq @@ -148,6 +149,7 @@ define i16 @stack_fold_fpclassph_ymm(<16 x half> %a0) { ; CHECK-NEXT: nop ; CHECK-NEXT: #NO_APP ; CHECK-NEXT: vfpclassphy $4, {{[-0-9]+}}(%r{{[sb]}}p), %k0 # 32-byte Folded Reload +; CHECK-NEXT: # k0 = isNegativeZero(mem) ; CHECK-NEXT: kmovd %k0, %eax ; CHECK-NEXT: # kill: def $ax killed $ax killed $eax ; CHECK-NEXT: vzeroupper diff --git a/llvm/test/MC/AArch64/SME2p2/bfmop4as-non-widening-diagnostics.s b/llvm/test/MC/AArch64/SME2p2/bfmop4as-non-widening-diagnostics.s new file mode 100644 index 00000000000000..231d4cd9967a49 --- /dev/null +++ b/llvm/test/MC/AArch64/SME2p2/bfmop4as-non-widening-diagnostics.s @@ -0,0 +1,220 @@ +// RUN: not llvm-mc -triple=aarch64 -mattr=+sme2p2,+sme-b16b16 < %s 2>&1 | FileCheck %s + +// BFMOP4A + +// Single vectors + +bfmop4a za0.d, z0.h, z16.h +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid matrix operand, expected za[0-3].s + +bfmop4a za4.h, z0.h, z16.h +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction + +bfmop4a za0.h, z0.s, z16.h +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid restricted vector register, expected even register in z0.h..z14.h + +bfmop4a za0.h, z15.h, z16.h +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid restricted vector register, expected even register in z0.h..z14.h + +bfmop4a za0.h, z16.h, z16.h +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid restricted vector register, expected even register in z0.h..z14.h + +bfmop4a za0.h, z0.h, z16.s +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid restricted vector register, expected even register in z16.h..z30.h + +bfmop4a za0.h, z12.h, z17.h +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid restricted vector register, expected even register in z16.h..z30.h + +bfmop4a za0.h, z12.h, z14.h +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid restricted vector register, expected even register in z16.h..z30.h + +bfmop4a za0.h, z12.h, z31.h +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid restricted vector register, expected even register in z16.h..z30.h + +// Single and multiple vectors + +bfmop4a za0.d, z0.h, {z16.h-z17.h} +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid matrix operand, expected za[0-3].s + +bfmop4a za4.h, z0.h, {z16.h-z17.h} +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction + +bfmop4a za0.h, z0.s, {z16.h-z17.h} +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid restricted vector register, expected even register in z0.h..z14.h + +bfmop4a za0.h, z1.h, {z16.h-z17.h} +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid restricted vector register, expected even register in z0.h..z14.h + +bfmop4a za0.h, z16.h, {z16.h-z17.h} +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid restricted vector register, expected even register in z0.h..z14.h + +bfmop4a za0.h, z0.h, {z16.s-z17.s} +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction + +bfmop4a za0.h, z0.h, {z17.h-z18.h} +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid vector list, expected list with 2 consecutive SVE vectors in the range z16-z30, where the first vector is a multiple of 2 and with matching element types + +bfmop4a za0.h, z0.h, {z12.h-z13.h} +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid vector list, expected list with 2 consecutive SVE vectors in the range z16-z30, where the first vector is a multiple of 2 and with matching element types + +// Multiple and single vectors + +bfmop4a za0.d, {z0.h-z1.h}, z16.h +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid matrix operand, expected za[0-3].s + +bfmop4a za4.h, {z0.h-z1.h}, z16.h +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction + +bfmop4a za0.h, {z0.s-z1.h}, z16.h +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: mismatched register size suffix + +bfmop4a za0.h, {z1.h-z2.h}, z16.h +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid vector list, expected list with 2 consecutive SVE vectors in the range z0-z14, where the first vector is a multiple of 2 and with matching element types + +bfmop4a za0.h, {z16.h-z17.h}, z16.h +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid vector list, expected list with 2 consecutive SVE vectors in the range z0-z14, where the first vector is a multiple of 2 and with matching element types + +bfmop4a za0.h, {z0.h-z1.h}, z16.d +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid restricted vector register, expected even register in z16.h..z30.h + +bfmop4a za0.h, {z0.h-z1.h}, z17.h +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid restricted vector register, expected even register in z16.h..z30.h + +bfmop4a za0.h, {z0.h-z1.h}, z12.h +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid restricted vector register, expected even register in z16.h..z30.h + +// Multiple vectors + +bfmop4a za0.d, {z0.h-z1.h}, {z16.h-z17.h} +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid matrix operand, expected za[0-3].s + +bfmop4a za4.h, {z0.h-z1.h}, {z16.h-z17.h} +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction + +bfmop4a za0.h, {z0.s-z1.s}, {z16.h-z17.h} +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction + +bfmop4a za0.h, {z1.h-z2.h}, {z16.h-z17.h} +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid vector list, expected list with 2 consecutive SVE vectors in the range z0-z14, where the first vector is a multiple of 2 and with matching element types + +bfmop4a za0.h, {z18.h-z19.h}, {z16.h-z17.h} +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid vector list, expected list with 2 consecutive SVE vectors in the range z0-z14, where the first vector is a multiple of 2 and with matching element types + +bfmop4a za0.h, {z0.h-z1.h}, {z16.s-z17.s} +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction + +bfmop4a za0.h, {z0.h-z1.h}, {z19.h-z20.h} +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid vector list, expected list with 2 consecutive SVE vectors in the range z16-z30, where the first vector is a multiple of 2 and with matching element types + +bfmop4a za0.h, {z0.h-z1.h}, {z10.h-z11.h} +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid vector list, expected list with 2 consecutive SVE vectors in the range z16-z30, where the first vector is a multiple of 2 and with matching element types + + +// BFMOP4S + +// Single vectors + +bfmop4s za0.d, z0.h, z16.h +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid matrix operand, expected za[0-3].s + +bfmop4s za4.h, z0.h, z16.h +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction + +bfmop4s za0.h, z0.s, z16.h +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid restricted vector register, expected even register in z0.h..z14.h + +bfmop4s za0.h, z15.h, z16.h +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid restricted vector register, expected even register in z0.h..z14.h + +bfmop4s za0.h, z16.h, z16.h +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid restricted vector register, expected even register in z0.h..z14.h + +bfmop4s za0.h, z0.h, z16.s +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid restricted vector register, expected even register in z16.h..z30.h + +bfmop4s za0.h, z12.h, z17.h +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid restricted vector register, expected even register in z16.h..z30.h + +bfmop4s za0.h, z12.h, z14.h +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid restricted vector register, expected even register in z16.h..z30.h + +bfmop4s za0.h, z12.h, z31.h +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid restricted vector register, expected even register in z16.h..z30.h + +// Single and multiple vectors + +bfmop4s za0.d, z0.h, {z16.h-z17.h} +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid matrix operand, expected za[0-3].s + +bfmop4s za4.h, z0.h, {z16.h-z17.h} +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction + +bfmop4s za0.h, z0.s, {z16.h-z17.h} +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid restricted vector register, expected even register in z0.h..z14.h + +bfmop4s za0.h, z1.h, {z16.h-z17.h} +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid restricted vector register, expected even register in z0.h..z14.h + +bfmop4s za0.h, z16.h, {z16.h-z17.h} +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid restricted vector register, expected even register in z0.h..z14.h + +bfmop4s za0.h, z0.h, {z16.s-z17.s} +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction + +bfmop4s za0.h, z0.h, {z17.h-z18.h} +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid vector list, expected list with 2 consecutive SVE vectors in the range z16-z30, where the first vector is a multiple of 2 and with matching element types + +bfmop4s za0.h, z0.h, {z12.h-z13.h} +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid vector list, expected list with 2 consecutive SVE vectors in the range z16-z30, where the first vector is a multiple of 2 and with matching element types + +// Multiple and single vectors + +bfmop4s za0.d, {z0.h-z1.h}, z16.h +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid matrix operand, expected za[0-3].s + +bfmop4s za4.h, {z0.h-z1.h}, z16.h +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction + +bfmop4s za0.h, {z0.s-z1.h}, z16.h +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: mismatched register size suffix + +bfmop4s za0.h, {z1.h-z2.h}, z16.h +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid vector list, expected list with 2 consecutive SVE vectors in the range z0-z14, where the first vector is a multiple of 2 and with matching element types + +bfmop4s za0.h, {z16.h-z17.h}, z16.h +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid vector list, expected list with 2 consecutive SVE vectors in the range z0-z14, where the first vector is a multiple of 2 and with matching element types + +bfmop4s za0.h, {z0.h-z1.h}, z16.d +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid restricted vector register, expected even register in z16.h..z30.h + +bfmop4s za0.h, {z0.h-z1.h}, z17.h +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid restricted vector register, expected even register in z16.h..z30.h + +bfmop4s za0.h, {z0.h-z1.h}, z12.h +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid restricted vector register, expected even register in z16.h..z30.h + +// Multiple vectors + +bfmop4s za0.d, {z0.h-z1.h}, {z16.h-z17.h} +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid matrix operand, expected za[0-3].s + +bfmop4s za4.h, {z0.h-z1.h}, {z16.h-z17.h} +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction + +bfmop4s za0.h, {z0.s-z1.s}, {z16.h-z17.h} +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction + +bfmop4s za0.h, {z1.h-z2.h}, {z16.h-z17.h} +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid vector list, expected list with 2 consecutive SVE vectors in the range z0-z14, where the first vector is a multiple of 2 and with matching element types + +bfmop4s za0.h, {z18.h-z19.h}, {z16.h-z17.h} +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid vector list, expected list with 2 consecutive SVE vectors in the range z0-z14, where the first vector is a multiple of 2 and with matching element types + +bfmop4s za0.h, {z0.h-z1.h}, {z16.s-z17.s} +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction + +bfmop4s za0.h, {z0.h-z1.h}, {z19.h-z20.h} +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid vector list, expected list with 2 consecutive SVE vectors in the range z16-z30, where the first vector is a multiple of 2 and with matching element types + +bfmop4s za0.h, {z0.h-z1.h}, {z10.h-z11.h} +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid vector list, expected list with 2 consecutive SVE vectors in the range z16-z30, where the first vector is a multiple of 2 and with matching element types diff --git a/llvm/test/MC/AArch64/SME2p2/bfmop4as-non-widening.s b/llvm/test/MC/AArch64/SME2p2/bfmop4as-non-widening.s new file mode 100644 index 00000000000000..b98bb99def0569 --- /dev/null +++ b/llvm/test/MC/AArch64/SME2p2/bfmop4as-non-widening.s @@ -0,0 +1,178 @@ +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2p2,+sme-b16b16 < %s \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \ +// RUN: | FileCheck %s --check-prefix=CHECK-ERROR +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme2p2,+sme-b16b16 < %s \ +// RUN: | llvm-objdump -d --mattr=+sme2p2,+sme-b16b16 - | FileCheck %s --check-prefix=CHECK-INST +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme2p2,+sme-b16b16 < %s \ +// RUN: | llvm-objdump -d --mattr=-sme2p2 - | FileCheck %s --check-prefix=CHECK-UNKNOWN +// Disassemble encoding and check the re-encoding (-show-encoding) matches. +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2p2,+sme-b16b16 < %s \ +// RUN: | sed '/.text/d' | sed 's/.*encoding: //g' \ +// RUN: | llvm-mc -triple=aarch64 -mattr=+sme2p2,+sme-b16b16 -disassemble -show-encoding \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST + +// BFMOP4A + +// Single vectors + +bfmop4a za0.h, z0.h, z16.h // 10000001-00100000-00000000-00001000 +// CHECK-INST: bfmop4a za0.h, z0.h, z16.h +// CHECK-ENCODING: [0x08,0x00,0x20,0x81] +// CHECK-ERROR: instruction requires: sme2p2 sme-b16b16 +// CHECK-UNKNOWN: 81200008 + +bfmop4a za1.h, z12.h, z24.h // 10000001-00101000-00000001-10001001 +// CHECK-INST: bfmop4a za1.h, z12.h, z24.h +// CHECK-ENCODING: [0x89,0x01,0x28,0x81] +// CHECK-ERROR: instruction requires: sme2p2 sme-b16b16 +// CHECK-UNKNOWN: 81280189 + +bfmop4a za1.h, z14.h, z30.h // 10000001-00101110-00000001-11001001 +// CHECK-INST: bfmop4a za1.h, z14.h, z30.h +// CHECK-ENCODING: [0xc9,0x01,0x2e,0x81] +// CHECK-ERROR: instruction requires: sme2p2 sme-b16b16 +// CHECK-UNKNOWN: 812e01c9 + +// Single and multiple vectors + +bfmop4a za0.h, z0.h, {z16.h-z17.h} // 10000001-00110000-00000000-00001000 +// CHECK-INST: bfmop4a za0.h, z0.h, { z16.h, z17.h } +// CHECK-ENCODING: [0x08,0x00,0x30,0x81] +// CHECK-ERROR: instruction requires: sme2p2 sme-b16b16 +// CHECK-UNKNOWN: 81300008 + +bfmop4a za1.h, z12.h, {z24.h-z25.h} // 10000001-00111000-00000001-10001001 +// CHECK-INST: bfmop4a za1.h, z12.h, { z24.h, z25.h } +// CHECK-ENCODING: [0x89,0x01,0x38,0x81] +// CHECK-ERROR: instruction requires: sme2p2 sme-b16b16 +// CHECK-UNKNOWN: 81380189 + +bfmop4a za1.h, z14.h, {z30.h-z31.h} // 10000001-00111110-00000001-11001001 +// CHECK-INST: bfmop4a za1.h, z14.h, { z30.h, z31.h } +// CHECK-ENCODING: [0xc9,0x01,0x3e,0x81] +// CHECK-ERROR: instruction requires: sme2p2 sme-b16b16 +// CHECK-UNKNOWN: 813e01c9 + +// Multiple and single vectors + +bfmop4a za0.h, {z0.h-z1.h}, z16.h // 10000001-00100000-00000010-00001000 +// CHECK-INST: bfmop4a za0.h, { z0.h, z1.h }, z16.h +// CHECK-ENCODING: [0x08,0x02,0x20,0x81] +// CHECK-ERROR: instruction requires: sme2p2 sme-b16b16 +// CHECK-UNKNOWN: 81200208 + +bfmop4a za1.h, {z12.h-z13.h}, z24.h // 10000001-00101000-00000011-10001001 +// CHECK-INST: bfmop4a za1.h, { z12.h, z13.h }, z24.h +// CHECK-ENCODING: [0x89,0x03,0x28,0x81] +// CHECK-ERROR: instruction requires: sme2p2 sme-b16b16 +// CHECK-UNKNOWN: 81280389 + +bfmop4a za1.h, {z14.h-z15.h}, z30.h // 10000001-00101110-00000011-11001001 +// CHECK-INST: bfmop4a za1.h, { z14.h, z15.h }, z30.h +// CHECK-ENCODING: [0xc9,0x03,0x2e,0x81] +// CHECK-ERROR: instruction requires: sme2p2 sme-b16b16 +// CHECK-UNKNOWN: 812e03c9 + +// Multiple vectors + +bfmop4a za0.h, {z0.h-z1.h}, {z16.h-z17.h} // 10000001-00110000-00000010-00001000 +// CHECK-INST: bfmop4a za0.h, { z0.h, z1.h }, { z16.h, z17.h } +// CHECK-ENCODING: [0x08,0x02,0x30,0x81] +// CHECK-ERROR: instruction requires: sme2p2 sme-b16b16 +// CHECK-UNKNOWN: 81300208 + +bfmop4a za1.h, {z12.h-z13.h}, {z24.h-z25.h} // 10000001-00111000-00000011-10001001 +// CHECK-INST: bfmop4a za1.h, { z12.h, z13.h }, { z24.h, z25.h } +// CHECK-ENCODING: [0x89,0x03,0x38,0x81] +// CHECK-ERROR: instruction requires: sme2p2 sme-b16b16 +// CHECK-UNKNOWN: 81380389 + +bfmop4a za1.h, {z14.h-z15.h}, {z30.h-z31.h} // 10000001-00111110-00000011-11001001 +// CHECK-INST: bfmop4a za1.h, { z14.h, z15.h }, { z30.h, z31.h } +// CHECK-ENCODING: [0xc9,0x03,0x3e,0x81] +// CHECK-ERROR: instruction requires: sme2p2 sme-b16b16 +// CHECK-UNKNOWN: 813e03c9 + + +// BFMOP4S + +// Single vectors + +bfmop4s za0.h, z0.h, z16.h // 10000001-00100000-00000000-00011000 +// CHECK-INST: bfmop4s za0.h, z0.h, z16.h +// CHECK-ENCODING: [0x18,0x00,0x20,0x81] +// CHECK-ERROR: instruction requires: sme2p2 sme-b16b16 +// CHECK-UNKNOWN: 81200018 + +bfmop4s za1.h, z12.h, z24.h // 10000001-00101000-00000001-10011001 +// CHECK-INST: bfmop4s za1.h, z12.h, z24.h +// CHECK-ENCODING: [0x99,0x01,0x28,0x81] +// CHECK-ERROR: instruction requires: sme2p2 sme-b16b16 +// CHECK-UNKNOWN: 81280199 + +bfmop4s za1.h, z14.h, z30.h // 10000001-00101110-00000001-11011001 +// CHECK-INST: bfmop4s za1.h, z14.h, z30.h +// CHECK-ENCODING: [0xd9,0x01,0x2e,0x81] +// CHECK-ERROR: instruction requires: sme2p2 sme-b16b16 +// CHECK-UNKNOWN: 812e01d9 + +// Single and multiple vectors + +bfmop4s za0.h, z0.h, {z16.h-z17.h} // 10000001-00110000-00000000-00011000 +// CHECK-INST: bfmop4s za0.h, z0.h, { z16.h, z17.h } +// CHECK-ENCODING: [0x18,0x00,0x30,0x81] +// CHECK-ERROR: instruction requires: sme2p2 sme-b16b16 +// CHECK-UNKNOWN: 81300018 + +bfmop4s za1.h, z12.h, {z24.h-z25.h} // 10000001-00111000-00000001-10011001 +// CHECK-INST: bfmop4s za1.h, z12.h, { z24.h, z25.h } +// CHECK-ENCODING: [0x99,0x01,0x38,0x81] +// CHECK-ERROR: instruction requires: sme2p2 sme-b16b16 +// CHECK-UNKNOWN: 81380199 + +bfmop4s za1.h, z14.h, {z30.h-z31.h} // 10000001-00111110-00000001-11011001 +// CHECK-INST: bfmop4s za1.h, z14.h, { z30.h, z31.h } +// CHECK-ENCODING: [0xd9,0x01,0x3e,0x81] +// CHECK-ERROR: instruction requires: sme2p2 sme-b16b16 +// CHECK-UNKNOWN: 813e01d9 + +// Multiple and single vectors + +bfmop4s za0.h, {z0.h-z1.h}, z16.h // 10000001-00100000-00000010-00011000 +// CHECK-INST: bfmop4s za0.h, { z0.h, z1.h }, z16.h +// CHECK-ENCODING: [0x18,0x02,0x20,0x81] +// CHECK-ERROR: instruction requires: sme2p2 sme-b16b16 +// CHECK-UNKNOWN: 81200218 + +bfmop4s za1.h, {z12.h-z13.h}, z24.h // 10000001-00101000-00000011-10011001 +// CHECK-INST: bfmop4s za1.h, { z12.h, z13.h }, z24.h +// CHECK-ENCODING: [0x99,0x03,0x28,0x81] +// CHECK-ERROR: instruction requires: sme2p2 sme-b16b16 +// CHECK-UNKNOWN: 81280399 + +bfmop4s za1.h, {z14.h-z15.h}, z30.h // 10000001-00101110-00000011-11011001 +// CHECK-INST: bfmop4s za1.h, { z14.h, z15.h }, z30.h +// CHECK-ENCODING: [0xd9,0x03,0x2e,0x81] +// CHECK-ERROR: instruction requires: sme2p2 sme-b16b16 +// CHECK-UNKNOWN: 812e03d9 + +// Multiple vectors + +bfmop4s za0.h, {z0.h-z1.h}, {z16.h-z17.h} // 10000001-00110000-00000010-00011000 +// CHECK-INST: bfmop4s za0.h, { z0.h, z1.h }, { z16.h, z17.h } +// CHECK-ENCODING: [0x18,0x02,0x30,0x81] +// CHECK-ERROR: instruction requires: sme2p2 sme-b16b16 +// CHECK-UNKNOWN: 81300218 + +bfmop4s za1.h, {z12.h-z13.h}, {z24.h-z25.h} // 10000001-00111000-00000011-10011001 +// CHECK-INST: bfmop4s za1.h, { z12.h, z13.h }, { z24.h, z25.h } +// CHECK-ENCODING: [0x99,0x03,0x38,0x81] +// CHECK-ERROR: instruction requires: sme2p2 sme-b16b16 +// CHECK-UNKNOWN: 81380399 + +bfmop4s za1.h, {z14.h-z15.h}, {z30.h-z31.h} // 10000001-00111110-00000011-11011001 +// CHECK-INST: bfmop4s za1.h, { z14.h, z15.h }, { z30.h, z31.h } +// CHECK-ENCODING: [0xd9,0x03,0x3e,0x81] +// CHECK-ERROR: instruction requires: sme2p2 sme-b16b16 +// CHECK-UNKNOWN: 813e03d9 diff --git a/llvm/test/MC/AArch64/SME2p2/fmop4a-fp8-fp32-widening-diagnostics.s b/llvm/test/MC/AArch64/SME2p2/fmop4a-fp8-fp32-widening-diagnostics.s new file mode 100644 index 00000000000000..9a06192c0b30af --- /dev/null +++ b/llvm/test/MC/AArch64/SME2p2/fmop4a-fp8-fp32-widening-diagnostics.s @@ -0,0 +1,120 @@ +// RUN: not llvm-mc -triple=aarch64 -mattr=+sme2p2,+sme-f8f32 < %s 2>&1 | FileCheck %s + +// Single vectors + +fmop4a za0.d, z0.b, z16.b +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid matrix operand + +fmop4a za4.s, z0.b, z16.b +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction + +fmop4a za0.s, z0.d, z16.b +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid restricted vector register, expected even register in z0.b..z14.b + +fmop4a za0.s, z15.b, z16.b +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid restricted vector register, expected even register in z0.b..z14.b + +fmop4a za0.s, z16.b, z16.b +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid restricted vector register, expected even register in z0.b..z14.b + +fmop4a za0.s, z0.b, z16.s +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid restricted vector register, expected even register in z16.b..z30.b + +fmop4a za0.s, z12.b, z17.b +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid restricted vector register, expected even register in z16.b..z30.b + +fmop4a za0.s, z12.b, z14.b +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid restricted vector register, expected even register in z16.b..z30.b + +fmop4a za0.s, z12.b, z31.b +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid restricted vector register, expected even register in z16.b..z30.b + +// Single and multiple vectors + +fmop4a za0.d, z0.b, {z16.b-z17.b} +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid matrix operand + +fmop4a za4.s, z0.b, {z16.b-z17.b} +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction + +fmop4a za0.s, z0.d, {z16.b-z17.b} +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid restricted vector register, expected even register in z0.b..z14.b + +fmop4a za0.s, z1.b, {z16.b-z17.b} +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid restricted vector register, expected even register in z0.b..z14.b + +fmop4a za0.s, z16.b, {z16.b-z17.b} +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid restricted vector register, expected even register in z0.b..z14.b + +fmop4a za0.s, z0.b, {z16.s-z17.s} +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction + +fmop4a za0.s, z0.b, {z17.b-z18.b} +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid vector list, expected list with 2 consecutive SVE vectors in the range z16-z30, where the first vector is a multiple of 2 and with matching element types + +fmop4a za0.s, z0.b, {z16.b-z18.b} +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction + +fmop4a za0.s, z0.b, {z12.b-z13.b} +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid vector list, expected list with 2 consecutive SVE vectors in the range z16-z30, where the first vector is a multiple of 2 and with matching element types + +// Multiple and single vectors + +fmop4a za0.d, {z0.b-z1.b}, z16.b +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid matrix operand + +fmop4a za4.s, {z0.b-z1.b}, z16.b +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction + +fmop4a za0.s, {z0.s-z1.b}, z16.b +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: mismatched register size suffix + +fmop4a za0.s, {z1.b-z2.b}, z16.b +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid vector list, expected list with 2 consecutive SVE vectors in the range z0-z14, where the first vector is a multiple of 2 and with matching element types + +fmop4a za0.s, {z0.b-z2.b}, z16.b +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction + +fmop4a za0.s, {z16.b-z17.b}, z16.b +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid vector list, expected list with 2 consecutive SVE vectors in the range z0-z14, where the first vector is a multiple of 2 and with matching element types + +fmop4a za0.s, {z0.b-z1.b}, z16.d +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid restricted vector register, expected even register in z16.b..z30.b + +fmop4a za0.s, {z0.b-z1.b}, z17.b +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid restricted vector register, expected even register in z16.b..z30.b + +fmop4a za0.s, {z0.b-z1.b}, z12.b +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid restricted vector register, expected even register in z16.b..z30.b + +// Multiple vectors + +fmop4a za0.d, {z0.b-z1.b}, {z16.b-z17.b} +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid matrix operand + +fmop4a za4.s, {z0.b-z1.b}, {z16.b-z17.b} +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction + +fmop4a za0.s, {z0.s-z1.s}, {z16.b-z17.b} +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction + +fmop4a za0.s, {z1.b-z2.b}, {z16.b-z17.b} +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid vector list, expected list with 2 consecutive SVE vectors in the range z0-z14, where the first vector is a multiple of 2 and with matching element types + +fmop4a za0.s, {z0.b-z2.b}, {z16.b-z17.b} +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction + +fmop4a za0.s, {z18.b-z19.b}, {z16.b-z17.b} +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid vector list, expected list with 2 consecutive SVE vectors in the range z0-z14, where the first vector is a multiple of 2 and with matching element types + +fmop4a za0.s, {z0.b-z1.b}, {z16.s-z17.s} +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction + +fmop4a za0.s, {z0.b-z1.b}, {z19.b-z20.b} +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid vector list, expected list with 2 consecutive SVE vectors in the range z16-z30, where the first vector is a multiple of 2 and with matching element types + +fmop4a za0.s, {z0.b-z1.b}, {z18.b-z20.b} +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction + +fmop4a za0.s, {z0.b-z1.b}, {z10.b-z11.b} +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid vector list, expected list with 2 consecutive SVE vectors in the range z16-z30, where the first vector is a multiple of 2 and with matching element types diff --git a/llvm/test/MC/AArch64/SME2p2/fmop4a-fp8-fp32-widening.s b/llvm/test/MC/AArch64/SME2p2/fmop4a-fp8-fp32-widening.s new file mode 100644 index 00000000000000..9e378bcf3d7533 --- /dev/null +++ b/llvm/test/MC/AArch64/SME2p2/fmop4a-fp8-fp32-widening.s @@ -0,0 +1,93 @@ +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2p2,+sme-f8f32 < %s \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \ +// RUN: | FileCheck %s --check-prefix=CHECK-ERROR +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme2p2,+sme-f8f32 < %s \ +// RUN: | llvm-objdump -d --mattr=+sme2p2,+sme-f8f32 - | FileCheck %s --check-prefix=CHECK-INST +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme2p2,+sme-f8f32 < %s \ +// RUN: | llvm-objdump -d --mattr=-sme2p2 - | FileCheck %s --check-prefix=CHECK-UNKNOWN +// Disassemble encoding and check the re-encoding (-show-encoding) matches. +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2p2,+sme-f8f32 < %s \ +// RUN: | sed '/.text/d' | sed 's/.*encoding: //g' \ +// RUN: | llvm-mc -triple=aarch64 -mattr=+sme2p2,+sme-f8f32 -disassemble -show-encoding \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST + +// Single vectors + +fmop4a za0.s, z0.b, z16.b // 10000000-00100000-00000000-00000000 +// CHECK-INST: fmop4a za0.s, z0.b, z16.b +// CHECK-ENCODING: [0x00,0x00,0x20,0x80] +// CHECK-ERROR: instruction requires: sme2p2 sme-f8f32 +// CHECK-UNKNOWN: 80200000 + +fmop4a za1.s, z10.b, z20.b // 10000000-00100100-00000001-01000001 +// CHECK-INST: fmop4a za1.s, z10.b, z20.b +// CHECK-ENCODING: [0x41,0x01,0x24,0x80] +// CHECK-ERROR: instruction requires: sme2p2 sme-f8f32 +// CHECK-UNKNOWN: 80240141 + +fmop4a za3.s, z14.b, z30.b // 10000000-00101110-00000001-11000011 +// CHECK-INST: fmop4a za3.s, z14.b, z30.b +// CHECK-ENCODING: [0xc3,0x01,0x2e,0x80] +// CHECK-ERROR: instruction requires: sme2p2 sme-f8f32 +// CHECK-UNKNOWN: 802e01c3 + +// Single and multiple vectors + +fmop4a za0.s, z0.b, {z16.b-z17.b} // 10000000-00110000-00000000-00000000 +// CHECK-INST: fmop4a za0.s, z0.b, { z16.b, z17.b } +// CHECK-ENCODING: [0x00,0x00,0x30,0x80] +// CHECK-ERROR: instruction requires: sme2p2 sme-f8f32 +// CHECK-UNKNOWN: 80300000 + +fmop4a za1.s, z10.b, {z20.b-z21.b} // 10000000-00110100-00000001-01000001 +// CHECK-INST: fmop4a za1.s, z10.b, { z20.b, z21.b } +// CHECK-ENCODING: [0x41,0x01,0x34,0x80] +// CHECK-ERROR: instruction requires: sme2p2 sme-f8f32 +// CHECK-UNKNOWN: 80340141 + +fmop4a za3.s, z14.b, {z30.b-z31.b} // 10000000-00111110-00000001-11000011 +// CHECK-INST: fmop4a za3.s, z14.b, { z30.b, z31.b } +// CHECK-ENCODING: [0xc3,0x01,0x3e,0x80] +// CHECK-ERROR: instruction requires: sme2p2 sme-f8f32 +// CHECK-UNKNOWN: 803e01c3 + +// Multiple and single vectors + +fmop4a za0.s, {z0.b-z1.b}, z16.b // 10000000-00100000-00000010-00000000 +// CHECK-INST: fmop4a za0.s, { z0.b, z1.b }, z16.b +// CHECK-ENCODING: [0x00,0x02,0x20,0x80] +// CHECK-ERROR: instruction requires: sme2p2 sme-f8f32 +// CHECK-UNKNOWN: 80200200 + +fmop4a za1.s, {z10.b-z11.b}, z20.b // 10000000-00100100-00000011-01000001 +// CHECK-INST: fmop4a za1.s, { z10.b, z11.b }, z20.b +// CHECK-ENCODING: [0x41,0x03,0x24,0x80] +// CHECK-ERROR: instruction requires: sme2p2 sme-f8f32 +// CHECK-UNKNOWN: 80240341 + +fmop4a za3.s, {z14.b-z15.b}, z30.b // 10000000-00101110-00000011-11000011 +// CHECK-INST: fmop4a za3.s, { z14.b, z15.b }, z30.b +// CHECK-ENCODING: [0xc3,0x03,0x2e,0x80] +// CHECK-ERROR: instruction requires: sme2p2 sme-f8f32 +// CHECK-UNKNOWN: 802e03c3 + +// Multiple vectors + +fmop4a za0.s, {z0.b-z1.b}, {z16.b-z17.b} // 10000000-00110000-00000010-00000000 +// CHECK-INST: fmop4a za0.s, { z0.b, z1.b }, { z16.b, z17.b } +// CHECK-ENCODING: [0x00,0x02,0x30,0x80] +// CHECK-ERROR: instruction requires: sme2p2 sme-f8f32 +// CHECK-UNKNOWN: 80300200 + +fmop4a za1.s, {z10.b-z11.b}, {z20.b-z21.b} // 10000000-00110100-00000011-01000001 +// CHECK-INST: fmop4a za1.s, { z10.b, z11.b }, { z20.b, z21.b } +// CHECK-ENCODING: [0x41,0x03,0x34,0x80] +// CHECK-ERROR: instruction requires: sme2p2 sme-f8f32 +// CHECK-UNKNOWN: 80340341 + +fmop4a za3.s, {z14.b-z15.b}, {z30.b-z31.b} // 10000000-00111110-00000011-11000011 +// CHECK-INST: fmop4a za3.s, { z14.b, z15.b }, { z30.b, z31.b } +// CHECK-ENCODING: [0xc3,0x03,0x3e,0x80] +// CHECK-ERROR: instruction requires: sme2p2 sme-f8f32 +// CHECK-UNKNOWN: 803e03c3 diff --git a/llvm/test/MC/AArch64/SME2p2/fmop4as-fp16-non-widening-diagnostics.s b/llvm/test/MC/AArch64/SME2p2/fmop4as-fp16-non-widening-diagnostics.s new file mode 100644 index 00000000000000..0272721e083621 --- /dev/null +++ b/llvm/test/MC/AArch64/SME2p2/fmop4as-fp16-non-widening-diagnostics.s @@ -0,0 +1,220 @@ +// RUN: not llvm-mc -triple=aarch64 -mattr=+sme2p2,+sme-f16f16 < %s 2>&1 | FileCheck %s + +// FMOP4A + +// Single vectors + +fmop4a za0.d, z0.h, z16.h +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid matrix operand + +fmop4a za2.h, z0.h, z16.h +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction + +fmop4a za0.h, z0.s, z16.h +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid restricted vector register, expected even register in z0.h..z14.h + +fmop4a za0.h, z15.h, z16.h +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid restricted vector register, expected even register in z0.h..z14.h + +fmop4a za0.h, z16.h, z16.h +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid restricted vector register, expected even register in z0.h..z14.h + +fmop4a za0.h, z0.h, z16.s +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid restricted vector register, expected even register in z16.h..z30.h + +fmop4a za0.h, z12.h, z17.h +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid restricted vector register, expected even register in z16.h..z30.h + +fmop4a za0.h, z12.h, z14.h +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid restricted vector register, expected even register in z16.h..z30.h + +fmop4a za0.h, z12.h, z31.h +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid restricted vector register, expected even register in z16.h..z30.h + +// Single and multiple vectors + +fmop4a za0.d, z0.h, {z16.h-z17.h} +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid matrix operand + +fmop4a za2.h, z0.h, {z16.h-z17.h} +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction + +fmop4a za0.h, z0.s, {z16.h-z17.h} +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid restricted vector register, expected even register in z0.h..z14.h + +fmop4a za0.h, z1.h, {z16.h-z17.h} +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid restricted vector register, expected even register in z0.h..z14.h + +fmop4a za0.h, z16.h, {z16.h-z17.h} +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid restricted vector register, expected even register in z0.h..z14.h + +fmop4a za0.h, z0.h, {z16.s-z17.s} +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction + +fmop4a za0.h, z0.h, {z17.h-z18.h} +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid vector list, expected list with 2 consecutive SVE vectors in the range z16-z30, where the first vector is a multiple of 2 and with matching element types + +fmop4a za0.h, z0.h, {z12.h-z13.h} +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid vector list, expected list with 2 consecutive SVE vectors in the range z16-z30, where the first vector is a multiple of 2 and with matching element types + +// Multiple and single vectors + +fmop4a za0.d, {z0.h-z1.h}, z16.h +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid matrix operand + +fmop4a za2.h, {z0.h-z1.h}, z16.h +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction + +fmop4a za0.h, {z0.s-z1.h}, z16.h +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: mismatched register size suffix + +fmop4a za0.h, {z1.h-z2.h}, z16.h +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid vector list, expected list with 2 consecutive SVE vectors in the range z0-z14, where the first vector is a multiple of 2 and with matching element types + +fmop4a za0.h, {z16.h-z17.h}, z16.h +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid vector list, expected list with 2 consecutive SVE vectors in the range z0-z14, where the first vector is a multiple of 2 and with matching element types + +fmop4a za0.h, {z0.h-z1.h}, z16.d +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid restricted vector register, expected even register in z16.h..z30.h + +fmop4a za0.h, {z0.h-z1.h}, z17.h +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid restricted vector register, expected even register in z16.h..z30.h + +fmop4a za0.h, {z0.h-z1.h}, z12.h +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid restricted vector register, expected even register in z16.h..z30.h + +// Multiple vectors + +fmop4a za0.d, {z0.h-z1.h}, {z16.h-z17.h} +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid matrix operand + +fmop4a za2.h, {z0.h-z1.h}, {z16.h-z17.h} +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction + +fmop4a za0.h, {z0.s-z1.s}, {z16.h-z17.h} +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction + +fmop4a za0.h, {z1.h-z2.h}, {z16.h-z17.h} +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid vector list, expected list with 2 consecutive SVE vectors in the range z0-z14, where the first vector is a multiple of 2 and with matching element types + +fmop4a za0.h, {z18.h-z19.h}, {z16.h-z17.h} +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid vector list, expected list with 2 consecutive SVE vectors in the range z0-z14, where the first vector is a multiple of 2 and with matching element types + +fmop4a za0.h, {z0.h-z1.h}, {z16.s-z17.s} +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction + +fmop4a za0.h, {z0.h-z1.h}, {z19.h-z20.h} +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid vector list, expected list with 2 consecutive SVE vectors in the range z16-z30, where the first vector is a multiple of 2 and with matching element types + +fmop4a za0.h, {z0.h-z1.h}, {z10.h-z11.h} +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid vector list, expected list with 2 consecutive SVE vectors in the range z16-z30, where the first vector is a multiple of 2 and with matching element types + + +// FMOP4S + +// Single vectors + +fmop4s za0.d, z0.h, z16.h +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid matrix operand + +fmop4s za2.h, z0.h, z16.h +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction + +fmop4s za0.h, z0.s, z16.h +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid restricted vector register, expected even register in z0.h..z14.h + +fmop4s za0.h, z15.h, z16.h +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid restricted vector register, expected even register in z0.h..z14.h + +fmop4s za0.h, z16.h, z16.h +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid restricted vector register, expected even register in z0.h..z14.h + +fmop4s za0.h, z0.h, z16.s +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid restricted vector register, expected even register in z16.h..z30.h + +fmop4s za0.h, z12.h, z17.h +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid restricted vector register, expected even register in z16.h..z30.h + +fmop4s za0.h, z12.h, z14.h +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid restricted vector register, expected even register in z16.h..z30.h + +fmop4s za0.h, z12.h, z31.h +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid restricted vector register, expected even register in z16.h..z30.h + +// Single and multiple vectors + +fmop4s za0.d, z0.h, {z16.h-z17.h} +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid matrix operand + +fmop4s za2.h, z0.h, {z16.h-z17.h} +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction + +fmop4s za0.h, z0.s, {z16.h-z17.h} +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid restricted vector register, expected even register in z0.h..z14.h + +fmop4s za0.h, z1.h, {z16.h-z17.h} +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid restricted vector register, expected even register in z0.h..z14.h + +fmop4s za0.h, z16.h, {z16.h-z17.h} +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid restricted vector register, expected even register in z0.h..z14.h + +fmop4s za0.h, z0.h, {z16.s-z17.s} +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction + +fmop4s za0.h, z0.h, {z17.h-z18.h} +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid vector list, expected list with 2 consecutive SVE vectors in the range z16-z30, where the first vector is a multiple of 2 and with matching element types + +fmop4s za0.h, z0.h, {z12.h-z13.h} +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid vector list, expected list with 2 consecutive SVE vectors in the range z16-z30, where the first vector is a multiple of 2 and with matching element types + +// Multiple and single vectors + +fmop4s za0.d, {z0.h-z1.h}, z16.h +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid matrix operand + +fmop4s za2.h, {z0.h-z1.h}, z16.h +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction + +fmop4s za0.h, {z0.s-z1.h}, z16.h +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: mismatched register size suffix + +fmop4s za0.h, {z1.h-z2.h}, z16.h +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid vector list, expected list with 2 consecutive SVE vectors in the range z0-z14, where the first vector is a multiple of 2 and with matching element types + +fmop4s za0.h, {z16.h-z17.h}, z16.h +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid vector list, expected list with 2 consecutive SVE vectors in the range z0-z14, where the first vector is a multiple of 2 and with matching element types + +fmop4s za0.h, {z0.h-z1.h}, z16.d +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid restricted vector register, expected even register in z16.h..z30.h + +fmop4s za0.h, {z0.h-z1.h}, z17.h +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid restricted vector register, expected even register in z16.h..z30.h + +fmop4s za0.h, {z0.h-z1.h}, z12.h +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid restricted vector register, expected even register in z16.h..z30.h + +// Multiple vectors + +fmop4s za0.d, {z0.h-z1.h}, {z16.h-z17.h} +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid matrix operand + +fmop4s za2.h, {z0.h-z1.h}, {z16.h-z17.h} +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction + +fmop4s za0.h, {z0.s-z1.s}, {z16.h-z17.h} +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction + +fmop4s za0.h, {z1.h-z2.h}, {z16.h-z17.h} +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid vector list, expected list with 2 consecutive SVE vectors in the range z0-z14, where the first vector is a multiple of 2 and with matching element types + +fmop4s za0.h, {z18.h-z19.h}, {z16.h-z17.h} +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid vector list, expected list with 2 consecutive SVE vectors in the range z0-z14, where the first vector is a multiple of 2 and with matching element types + +fmop4s za0.h, {z0.h-z1.h}, {z16.s-z17.s} +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction + +fmop4s za0.h, {z0.h-z1.h}, {z19.h-z20.h} +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid vector list, expected list with 2 consecutive SVE vectors in the range z16-z30, where the first vector is a multiple of 2 and with matching element types + +fmop4s za0.h, {z0.h-z1.h}, {z10.h-z11.h} +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid vector list, expected list with 2 consecutive SVE vectors in the range z16-z30, where the first vector is a multiple of 2 and with matching element types diff --git a/llvm/test/MC/AArch64/SME2p2/fmop4as-fp16-non-widening.s b/llvm/test/MC/AArch64/SME2p2/fmop4as-fp16-non-widening.s new file mode 100644 index 00000000000000..2a94acd35e95c3 --- /dev/null +++ b/llvm/test/MC/AArch64/SME2p2/fmop4as-fp16-non-widening.s @@ -0,0 +1,179 @@ + +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2p2,+sme-f16f16 < %s \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \ +// RUN: | FileCheck %s --check-prefix=CHECK-ERROR +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme2p2,+sme-f16f16 < %s \ +// RUN: | llvm-objdump -d --mattr=+sme2p2,+sme-f16f16 - | FileCheck %s --check-prefix=CHECK-INST +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme2p2,+sme-f16f16 < %s \ +// RUN: | llvm-objdump -d --mattr=-sme2p2 - | FileCheck %s --check-prefix=CHECK-UNKNOWN +// Disassemble encoding and check the re-encoding (-show-encoding) matches. +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2p2,+sme-f16f16 < %s \ +// RUN: | sed '/.text/d' | sed 's/.*encoding: //g' \ +// RUN: | llvm-mc -triple=aarch64 -mattr=+sme2p2,+sme-f16f16 -disassemble -show-encoding \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST + + +// FMOP4A + +// Single vectors + +fmop4a za0.h, z0.h, z16.h // 10000001-00000000-00000000-00001000 +// CHECK-INST: fmop4a za0.h, z0.h, z16.h +// CHECK-ENCODING: [0x08,0x00,0x00,0x81] +// CHECK-ERROR: instruction requires: sme2p2 sme-f16f16 +// CHECK-UNKNOWN: 81000008 + +fmop4a za1.h, z12.h, z24.h // 10000001-00001000-00000001-10001001 +// CHECK-INST: fmop4a za1.h, z12.h, z24.h +// CHECK-ENCODING: [0x89,0x01,0x08,0x81] +// CHECK-ERROR: instruction requires: sme2p2 sme-f16f16 +// CHECK-UNKNOWN: 81080189 + +fmop4a za1.h, z14.h, z30.h // 10000001-00001110-00000001-11001001 +// CHECK-INST: fmop4a za1.h, z14.h, z30.h +// CHECK-ENCODING: [0xc9,0x01,0x0e,0x81] +// CHECK-ERROR: instruction requires: sme2p2 sme-f16f16 +// CHECK-UNKNOWN: 810e01c9 + +// Single and multiple vectors + +fmop4a za0.h, z0.h, {z16.h-z17.h} // 10000001-00010000-00000000-00001000 +// CHECK-INST: fmop4a za0.h, z0.h, { z16.h, z17.h } +// CHECK-ENCODING: [0x08,0x00,0x10,0x81] +// CHECK-ERROR: instruction requires: sme2p2 sme-f16f16 +// CHECK-UNKNOWN: 81100008 + +fmop4a za1.h, z12.h, {z24.h-z25.h} // 10000001-00011000-00000001-10001001 +// CHECK-INST: fmop4a za1.h, z12.h, { z24.h, z25.h } +// CHECK-ENCODING: [0x89,0x01,0x18,0x81] +// CHECK-ERROR: instruction requires: sme2p2 sme-f16f16 +// CHECK-UNKNOWN: 81180189 + +fmop4a za1.h, z14.h, {z30.h-z31.h} // 10000001-00011110-00000001-11001001 +// CHECK-INST: fmop4a za1.h, z14.h, { z30.h, z31.h } +// CHECK-ENCODING: [0xc9,0x01,0x1e,0x81] +// CHECK-ERROR: instruction requires: sme2p2 sme-f16f16 +// CHECK-UNKNOWN: 811e01c9 + +// Multiple and single vectors + +fmop4a za0.h, {z0.h-z1.h}, z16.h // 10000001-00000000-00000010-00001000 +// CHECK-INST: fmop4a za0.h, { z0.h, z1.h }, z16.h +// CHECK-ENCODING: [0x08,0x02,0x00,0x81] +// CHECK-ERROR: instruction requires: sme2p2 sme-f16f16 +// CHECK-UNKNOWN: 81000208 + +fmop4a za1.h, {z12.h-z13.h}, z24.h // 10000001-00001000-00000011-10001001 +// CHECK-INST: fmop4a za1.h, { z12.h, z13.h }, z24.h +// CHECK-ENCODING: [0x89,0x03,0x08,0x81] +// CHECK-ERROR: instruction requires: sme2p2 sme-f16f16 +// CHECK-UNKNOWN: 81080389 + +fmop4a za1.h, {z14.h-z15.h}, z30.h // 10000001-00001110-00000011-11001001 +// CHECK-INST: fmop4a za1.h, { z14.h, z15.h }, z30.h +// CHECK-ENCODING: [0xc9,0x03,0x0e,0x81] +// CHECK-ERROR: instruction requires: sme2p2 sme-f16f16 +// CHECK-UNKNOWN: 810e03c9 + +// Multiple vectors + +fmop4a za0.h, {z0.h-z1.h}, {z16.h-z17.h} // 10000001-00010000-00000010-00001000 +// CHECK-INST: fmop4a za0.h, { z0.h, z1.h }, { z16.h, z17.h } +// CHECK-ENCODING: [0x08,0x02,0x10,0x81] +// CHECK-ERROR: instruction requires: sme2p2 sme-f16f16 +// CHECK-UNKNOWN: 81100208 + +fmop4a za1.h, {z12.h-z13.h}, {z24.h-z25.h} // 10000001-00011000-00000011-10001001 +// CHECK-INST: fmop4a za1.h, { z12.h, z13.h }, { z24.h, z25.h } +// CHECK-ENCODING: [0x89,0x03,0x18,0x81] +// CHECK-ERROR: instruction requires: sme2p2 sme-f16f16 +// CHECK-UNKNOWN: 81180389 + +fmop4a za1.h, {z14.h-z15.h}, {z30.h-z31.h} // 10000001-00011110-00000011-11001001 +// CHECK-INST: fmop4a za1.h, { z14.h, z15.h }, { z30.h, z31.h } +// CHECK-ENCODING: [0xc9,0x03,0x1e,0x81] +// CHECK-ERROR: instruction requires: sme2p2 sme-f16f16 +// CHECK-UNKNOWN: 811e03c9 + +// FMOP4S + +// Single vectors + +fmop4s za0.h, z0.h, z16.h // 10000001-00000000-00000000-00011000 +// CHECK-INST: fmop4s za0.h, z0.h, z16.h +// CHECK-ENCODING: [0x18,0x00,0x00,0x81] +// CHECK-ERROR: instruction requires: sme2p2 sme-f16f16 +// CHECK-UNKNOWN: 81000018 + +fmop4s za1.h, z12.h, z24.h // 10000001-00001000-00000001-10011001 +// CHECK-INST: fmop4s za1.h, z12.h, z24.h +// CHECK-ENCODING: [0x99,0x01,0x08,0x81] +// CHECK-ERROR: instruction requires: sme2p2 sme-f16f16 +// CHECK-UNKNOWN: 81080199 + +fmop4s za1.h, z14.h, z30.h // 10000001-00001110-00000001-11011001 +// CHECK-INST: fmop4s za1.h, z14.h, z30.h +// CHECK-ENCODING: [0xd9,0x01,0x0e,0x81] +// CHECK-ERROR: instruction requires: sme2p2 sme-f16f16 +// CHECK-UNKNOWN: 810e01d9 + +// Single and multiple vectors + +fmop4s za0.h, z0.h, {z16.h-z17.h} // 10000001-00010000-00000000-00011000 +// CHECK-INST: fmop4s za0.h, z0.h, { z16.h, z17.h } +// CHECK-ENCODING: [0x18,0x00,0x10,0x81] +// CHECK-ERROR: instruction requires: sme2p2 sme-f16f16 +// CHECK-UNKNOWN: 81100018 + +fmop4s za1.h, z12.h, {z24.h-z25.h} // 10000001-00011000-00000001-10011001 +// CHECK-INST: fmop4s za1.h, z12.h, { z24.h, z25.h } +// CHECK-ENCODING: [0x99,0x01,0x18,0x81] +// CHECK-ERROR: instruction requires: sme2p2 sme-f16f16 +// CHECK-UNKNOWN: 81180199 + +fmop4s za1.h, z14.h, {z30.h-z31.h} // 10000001-00011110-00000001-11011001 +// CHECK-INST: fmop4s za1.h, z14.h, { z30.h, z31.h } +// CHECK-ENCODING: [0xd9,0x01,0x1e,0x81] +// CHECK-ERROR: instruction requires: sme2p2 sme-f16f16 +// CHECK-UNKNOWN: 811e01d9 + +// Multiple and single vectors + +fmop4s za0.h, {z0.h-z1.h}, z16.h // 10000001-00000000-00000010-00011000 +// CHECK-INST: fmop4s za0.h, { z0.h, z1.h }, z16.h +// CHECK-ENCODING: [0x18,0x02,0x00,0x81] +// CHECK-ERROR: instruction requires: sme2p2 sme-f16f16 +// CHECK-UNKNOWN: 81000218 + +fmop4s za1.h, {z12.h-z13.h}, z24.h // 10000001-00001000-00000011-10011001 +// CHECK-INST: fmop4s za1.h, { z12.h, z13.h }, z24.h +// CHECK-ENCODING: [0x99,0x03,0x08,0x81] +// CHECK-ERROR: instruction requires: sme2p2 sme-f16f16 +// CHECK-UNKNOWN: 81080399 + +fmop4s za1.h, {z14.h-z15.h}, z30.h // 10000001-00001110-00000011-11011001 +// CHECK-INST: fmop4s za1.h, { z14.h, z15.h }, z30.h +// CHECK-ENCODING: [0xd9,0x03,0x0e,0x81] +// CHECK-ERROR: instruction requires: sme2p2 sme-f16f16 +// CHECK-UNKNOWN: 810e03d9 + +// Multiple vectors + +fmop4s za0.h, {z0.h-z1.h}, {z16.h-z17.h} // 10000001-00010000-00000010-00011000 +// CHECK-INST: fmop4s za0.h, { z0.h, z1.h }, { z16.h, z17.h } +// CHECK-ENCODING: [0x18,0x02,0x10,0x81] +// CHECK-ERROR: instruction requires: sme2p2 sme-f16f16 +// CHECK-UNKNOWN: 81100218 + +fmop4s za1.h, {z12.h-z13.h}, {z24.h-z25.h} // 10000001-00011000-00000011-10011001 +// CHECK-INST: fmop4s za1.h, { z12.h, z13.h }, { z24.h, z25.h } +// CHECK-ENCODING: [0x99,0x03,0x18,0x81] +// CHECK-ERROR: instruction requires: sme2p2 sme-f16f16 +// CHECK-UNKNOWN: 81180399 + +fmop4s za1.h, {z14.h-z15.h}, {z30.h-z31.h} // 10000001-00011110-00000011-11011001 +// CHECK-INST: fmop4s za1.h, { z14.h, z15.h }, { z30.h, z31.h } +// CHECK-ENCODING: [0xd9,0x03,0x1e,0x81] +// CHECK-ERROR: instruction requires: sme2p2 sme-f16f16 +// CHECK-UNKNOWN: 811e03d9 diff --git a/llvm/test/MC/AArch64/SVE/bfcvt-diagnostics.s b/llvm/test/MC/AArch64/SVE/bfcvt-diagnostics.s index 013f15f8b6e005..6c55ebe4088ff1 100644 --- a/llvm/test/MC/AArch64/SVE/bfcvt-diagnostics.s +++ b/llvm/test/MC/AArch64/SVE/bfcvt-diagnostics.s @@ -11,7 +11,7 @@ bfcvt z0.h, p0/m, z1.h // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: bfcvt z0.h, p0/z, z1.s -// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction requires: sme2p2 or sve2p2 // CHECK-NEXT: bfcvt z0.h, p0/z, z1.s // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: diff --git a/llvm/test/MC/AArch64/SVE/compact-diagnostics.s b/llvm/test/MC/AArch64/SVE/compact-diagnostics.s index a3d86267d917b5..b8ff8cc46201f2 100644 --- a/llvm/test/MC/AArch64/SVE/compact-diagnostics.s +++ b/llvm/test/MC/AArch64/SVE/compact-diagnostics.s @@ -28,12 +28,12 @@ compact z31.s, p7, z31.d // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: compact z31.b, p7, z31.b -// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction requires: sme2p2 or sve2p2 // CHECK-NEXT: compact z31.b, p7, z31.b // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: compact z31.h, p7, z31.h -// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction requires: sme2p2 or sve2p2 // CHECK-NEXT: compact z31.h, p7, z31.h // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: diff --git a/llvm/test/MC/AArch64/SVE/compact.s b/llvm/test/MC/AArch64/SVE/compact.s index ff815980781d79..a9b47dea246bee 100644 --- a/llvm/test/MC/AArch64/SVE/compact.s +++ b/llvm/test/MC/AArch64/SVE/compact.s @@ -12,11 +12,11 @@ compact z31.s, p7, z31.s // CHECK-INST: compact z31.s, p7, z31.s // CHECK-ENCODING: [0xff,0x9f,0xa1,0x05] -// CHECK-ERROR: instruction requires: sve +// CHECK-ERROR: instruction requires: sve or sme2p2 // CHECK-UNKNOWN: 05a19fff compact z31.d, p7, z31.d // CHECK-INST: compact z31.d, p7, z31.d // CHECK-ENCODING: [0xff,0x9f,0xe1,0x05] -// CHECK-ERROR: instruction requires: sve +// CHECK-ERROR: instruction requires: sve or sme2p2 // CHECK-UNKNOWN: 05e19fff diff --git a/llvm/test/MC/AArch64/SVE/matrix-multiply-fp-diagnostics.s b/llvm/test/MC/AArch64/SVE/matrix-multiply-fp-diagnostics.s index 8ae4d499284423..2fe43f7aa8444c 100644 --- a/llvm/test/MC/AArch64/SVE/matrix-multiply-fp-diagnostics.s +++ b/llvm/test/MC/AArch64/SVE/matrix-multiply-fp-diagnostics.s @@ -3,11 +3,6 @@ // --------------------------------------------------------------------------// // FMMLA (SVE) -// Invalid element size - -fmmla z0.h, z1.h, z2.h -// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width - // Mis-matched element size fmmla z0.d, z1.s, z2.s diff --git a/llvm/test/MC/AArch64/SVE2/directive-arch-negative.s b/llvm/test/MC/AArch64/SVE2/directive-arch-negative.s index 858aaf9d13ecc4..966bead071fe39 100644 --- a/llvm/test/MC/AArch64/SVE2/directive-arch-negative.s +++ b/llvm/test/MC/AArch64/SVE2/directive-arch-negative.s @@ -30,8 +30,26 @@ bgrp z21.s, z10.s, z21.s // CHECK: error: instruction requires: sve2-bitperm // CHECK-NEXT: bgrp z21.s, z10.s, z21.s +.arch armv9-a+f8f16mm +.arch armv9-a+nof8f16mm +fmmla z23.h, z13.b, z8.b +// CHECK: error: instruction requires: f8f16mm +// CHECK-NEXT: fmmla z23.h, z13.b, z8.b + +.arch armv9-a+f8f32mm +.arch armv9-a+nof8f32mm +fmmla z23.s, z13.b, z8.b +// CHECK: error: instruction requires: f8f32mm +// CHECK-NEXT: fmmla z23.s, z13.b, z8.b + +.arch armv9-a+sve-f16f32mm +.arch armv9-a+nosve-f16f32mm +fmmla z23.s, z13.h, z8.h +// CHECK: error: instruction requires: sve-f16f32mm +// CHECK-NEXT: fmmla z23.s, z13.h, z8.h + .arch armv9-a+sve-bfscale .arch armv9-a+nosve-bfscale bfscale z0.h, p0/m, z0.h, z0.h // CHECK: error: instruction requires: sve-bfscale -// CHECK-NEXT: bfscale z0.h, p0/m, z0.h, z0.h \ No newline at end of file +// CHECK-NEXT: bfscale z0.h, p0/m, z0.h, z0.h diff --git a/llvm/test/MC/AArch64/SVE2/directive-arch.s b/llvm/test/MC/AArch64/SVE2/directive-arch.s index b9710b67f8a1d0..99f6198a60abbc 100644 --- a/llvm/test/MC/AArch64/SVE2/directive-arch.s +++ b/llvm/test/MC/AArch64/SVE2/directive-arch.s @@ -20,6 +20,18 @@ rax1 z0.d, z0.d, z0.d bgrp z21.s, z10.s, z21.s // CHECK: bgrp z21.s, z10.s, z21.s +.arch armv9-a+f8f16mm +fmmla z23.h, z13.b, z8.b +// CHECK: fmmla z23.h, z13.b, z8.b + +.arch armv9-a+f8f32mm +fmmla z23.s, z13.b, z8.b +// CHECK: fmmla z23.s, z13.b, z8.b + +.arch armv9-a+sve-f16f32mm +fmmla z23.s, z13.h, z8.h +// CHECK: fmmla z23.s, z13.h, z8.h + .arch armv9-a+sve-bfscale bfscale z0.h, p0/m, z0.h, z0.h -// CHECK: bfscale z0.h, p0/m, z0.h, z0.h \ No newline at end of file +// CHECK: bfscale z0.h, p0/m, z0.h, z0.h diff --git a/llvm/test/MC/AArch64/SVE2/directive-arch_extension-negative.s b/llvm/test/MC/AArch64/SVE2/directive-arch_extension-negative.s index bd625d25262692..e967f5aa60bd73 100644 --- a/llvm/test/MC/AArch64/SVE2/directive-arch_extension-negative.s +++ b/llvm/test/MC/AArch64/SVE2/directive-arch_extension-negative.s @@ -30,8 +30,26 @@ bgrp z21.s, z10.s, z21.s // CHECK: error: instruction requires: sve2-bitperm // CHECK-NEXT: bgrp z21.s, z10.s, z21.s +.arch_extension f8f16mm +.arch_extension nof8f16mm +fmmla z23.h, z13.b, z8.b +// CHECK: error: instruction requires: f8f16mm +// CHECK-NEXT: fmmla z23.h, z13.b, z8.b + +.arch_extension f8f32mm +.arch_extension nof8f32mm +fmmla z23.s, z13.b, z8.b +// CHECK: error: instruction requires: f8f32mm +// CHECK-NEXT: fmmla z23.s, z13.b, z8.b + +.arch_extension sve-f16f32mm +.arch_extension nosve-f16f32mm +fmmla z23.s, z13.h, z8.h +// CHECK: error: instruction requires: sve-f16f32mm +// CHECK-NEXT: fmmla z23.s, z13.h, z8.h + .arch_extension sve-bfscale .arch_extension nosve-bfscale bfscale z0.h, p0/m, z0.h, z0.h // CHECK: error: instruction requires: sve-bfscale -// CHECK-NEXT: bfscale z0.h, p0/m, z0.h, z0.h \ No newline at end of file +// CHECK-NEXT: bfscale z0.h, p0/m, z0.h, z0.h diff --git a/llvm/test/MC/AArch64/SVE2/directive-arch_extension.s b/llvm/test/MC/AArch64/SVE2/directive-arch_extension.s index 28d803bf7cc88c..2fdbb525464d90 100644 --- a/llvm/test/MC/AArch64/SVE2/directive-arch_extension.s +++ b/llvm/test/MC/AArch64/SVE2/directive-arch_extension.s @@ -20,6 +20,18 @@ rax1 z0.d, z0.d, z0.d bgrp z21.s, z10.s, z21.s // CHECK: bgrp z21.s, z10.s, z21.s +.arch_extension f8f16mm +fmmla z23.h, z13.b, z8.b +// CHECK: fmmla z23.h, z13.b, z8.b + +.arch_extension f8f32mm +fmmla z23.s, z13.b, z8.b +// CHECK: fmmla z23.s, z13.b, z8.b + +.arch_extension sve-f16f32mm +fmmla z23.s, z13.h, z8.h +// CHECK: fmmla z23.s, z13.h, z8.h + .arch_extension sve-bfscale bfscale z0.h, p0/m, z0.h, z0.h -// CHECK: bfscale z0.h, p0/m, z0.h, z0.h \ No newline at end of file +// CHECK: bfscale z0.h, p0/m, z0.h, z0.h diff --git a/llvm/test/MC/AArch64/SVE2/directive-cpu-negative.s b/llvm/test/MC/AArch64/SVE2/directive-cpu-negative.s index 45a04a58eac3b4..9a8af638b70378 100644 --- a/llvm/test/MC/AArch64/SVE2/directive-cpu-negative.s +++ b/llvm/test/MC/AArch64/SVE2/directive-cpu-negative.s @@ -30,8 +30,26 @@ bgrp z21.s, z10.s, z21.s // CHECK: error: instruction requires: sve2-bitperm // CHECK-NEXT: bgrp z21.s, z10.s, z21.s +.cpu generic+sve2+f8f16mm +.cpu generic+sve2+nof8f16mm +fmmla z23.h, z13.b, z8.b +// CHECK: error: instruction requires: f8f16mm +// CHECK-NEXT: fmmla z23.h, z13.b, z8.b + +.cpu generic+sve2+f8f32mm +.cpu generic+sve2+nof8f32mm +fmmla z23.s, z13.b, z8.b +// CHECK: error: instruction requires: f8f32mm +// CHECK-NEXT: fmmla z23.s, z13.b, z8.b + +.cpu generic+sve-f16f32mm +.cpu generic+nosve-f16f32mm +fmmla z23.s, z13.h, z8.h +// CHECK: error: instruction requires: sve-f16f32mm +// CHECK-NEXT: fmmla z23.s, z13.h, z8.h + .cpu generic+sve-bfscale .cpu generic+nosve-bfscale bfscale z0.h, p0/m, z0.h, z0.h // CHECK: error: instruction requires: sve-bfscale -// CHECK-NEXT: bfscale z0.h, p0/m, z0.h, z0.h \ No newline at end of file +// CHECK-NEXT: bfscale z0.h, p0/m, z0.h, z0.h diff --git a/llvm/test/MC/AArch64/SVE2/directive-cpu.s b/llvm/test/MC/AArch64/SVE2/directive-cpu.s index 75d2321bf62077..daa5ec510b226a 100644 --- a/llvm/test/MC/AArch64/SVE2/directive-cpu.s +++ b/llvm/test/MC/AArch64/SVE2/directive-cpu.s @@ -20,6 +20,18 @@ rax1 z0.d, z0.d, z0.d bgrp z21.s, z10.s, z21.s // CHECK: bgrp z21.s, z10.s, z21.s +.cpu generic+sve2+f8f16mm +fmmla z23.h, z13.b, z8.b +// CHECK: fmmla z23.h, z13.b, z8.b + +.cpu generic+sve2+f8f32mm +fmmla z23.s, z13.b, z8.b +// CHECK: fmmla z23.s, z13.b, z8.b + +.cpu generic+sve-f16f32mm +fmmla z23.s, z13.h, z8.h +// CHECK: fmmla z23.s, z13.h, z8.h + .cpu generic+sve-bfscale bfscale z0.h, p0/m, z0.h, z0.h -// CHECK: bfscale z0.h, p0/m, z0.h, z0.h \ No newline at end of file +// CHECK: bfscale z0.h, p0/m, z0.h, z0.h diff --git a/llvm/test/MC/AArch64/SVE2/fcvtx-diagnostics.s b/llvm/test/MC/AArch64/SVE2/fcvtx-diagnostics.s index 5f365496033633..36c5d5fe9cbea6 100644 --- a/llvm/test/MC/AArch64/SVE2/fcvtx-diagnostics.s +++ b/llvm/test/MC/AArch64/SVE2/fcvtx-diagnostics.s @@ -29,7 +29,7 @@ fcvtx z0.d, p0/m, z0.d // Invalid predicate operation fcvtx z0.s, p0/z, z0.d -// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction requires: sme2p2 or sve2p2 // CHECK-NEXT: fcvtx z0.s, p0/z, z0.d // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: diff --git a/llvm/test/MC/AArch64/SVE2/fmmla-f16f32mm-diagnostics.s b/llvm/test/MC/AArch64/SVE2/fmmla-f16f32mm-diagnostics.s new file mode 100644 index 00000000000000..924c123f0ca5bc --- /dev/null +++ b/llvm/test/MC/AArch64/SVE2/fmmla-f16f32mm-diagnostics.s @@ -0,0 +1,18 @@ +// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve-f16f32mm 2>&1 < %s | FileCheck %s + +// --------------------------------------------------------------------------// +// FMMLA (SVE) + +// Invalid element size + +fmmla z0.s, z1.b, z2.b +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction requires: f8f32mm +fmmla z0.d, z1.h, z2.h +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width + +// Mis-matched element size + +fmmla z0.s, z1.h, z2.s +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +fmmla z0.s, z1.d, z2.h +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width \ No newline at end of file diff --git a/llvm/test/MC/AArch64/SVE2/fmmla-f16f32mm.s b/llvm/test/MC/AArch64/SVE2/fmmla-f16f32mm.s new file mode 100644 index 00000000000000..84efcfe8b12e48 --- /dev/null +++ b/llvm/test/MC/AArch64/SVE2/fmmla-f16f32mm.s @@ -0,0 +1,41 @@ + +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve,+sve-f16f32mm < %s \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \ +// RUN: | FileCheck %s --check-prefix=CHECK-ERROR +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve,+sve-f16f32mm < %s \ +// RUN: | llvm-objdump -d --mattr=+sve,+sve-f16f32mm - | FileCheck %s --check-prefix=CHECK-INST +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve,+sve-f16f32mm < %s \ +// RUN: | llvm-objdump -d --mattr=-sve - | FileCheck %s --check-prefix=CHECK-UNKNOWN +// Disassemble encoding and check the re-encoding (-show-encoding) matches. +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve,+sve-f16f32mm < %s \ +// RUN: | sed '/.text/d' | sed 's/.*encoding: //g' \ +// RUN: | llvm-mc -triple=aarch64 -mattr=+sve,+sve-f16f32mm -disassemble -show-encoding \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST + + +movprfx z23, z31 +fmmla z23.s, z13.h, z8.h // 01100100-00101000-11100101-10110111 +// CHECK-INST: movprfx z23, z31 +// CHECK-INST: fmmla z23.s, z13.h, z8.h +// CHECK-ENCODING: [0xb7,0xe5,0x28,0x64] +// CHECK-ERROR: instruction requires: sve-f16f32mm +// CHECK-UNKNOWN: 6428e5b7 + +fmmla z0.s, z0.h, z0.h // 01100100-00100000-11100100-00000000 +// CHECK-INST: fmmla z0.s, z0.h, z0.h +// CHECK-ENCODING: [0x00,0xe4,0x20,0x64] +// CHECK-ERROR: instruction requires: sve-f16f32mm +// CHECK-UNKNOWN: 6420e400 + +fmmla z23.s, z13.h, z8.h // 01100100-00101000-11100101-10110111 +// CHECK-INST: fmmla z23.s, z13.h, z8.h +// CHECK-ENCODING: [0xb7,0xe5,0x28,0x64] +// CHECK-ERROR: instruction requires: sve-f16f32mm +// CHECK-UNKNOWN: 6428e5b7 + +fmmla z31.s, z31.h, z31.h // 01100100-00111111-11100111-11111111 +// CHECK-INST: fmmla z31.s, z31.h, z31.h +// CHECK-ENCODING: [0xff,0xe7,0x3f,0x64] +// CHECK-ERROR: instruction requires: sve-f16f32mm +// CHECK-UNKNOWN: 643fe7ff \ No newline at end of file diff --git a/llvm/test/MC/AArch64/SVE2/fmmla-f8f16mm-diagnostics.s b/llvm/test/MC/AArch64/SVE2/fmmla-f8f16mm-diagnostics.s new file mode 100644 index 00000000000000..59818d2d24a481 --- /dev/null +++ b/llvm/test/MC/AArch64/SVE2/fmmla-f8f16mm-diagnostics.s @@ -0,0 +1,24 @@ +// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2,+f8f16mm 2>&1 < %s| FileCheck %s + +// ------------------------------------------------------------------------- // +// Invalid element width + +fmmla z21.b, z10.b, z21.b +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: fmmla z21.b, z10.b, z21.b +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +fmmla z21.d, z10.b, z21.b +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: fmmla z21.d, z10.b, z21.b +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +fmmla z21.s, z10.h, z21.h +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction requires: sve-f16f32mm +// CHECK-NEXT: fmmla z21.s, z10.h, z21.h +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +fmmla z21.s, z10.s, z21.s +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction requires: f32mm +// CHECK-NEXT: fmmla z21.s, z10.s, z21.s +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: \ No newline at end of file diff --git a/llvm/test/MC/AArch64/SVE2/fmmla-f8f16mm.s b/llvm/test/MC/AArch64/SVE2/fmmla-f8f16mm.s new file mode 100644 index 00000000000000..ff343548993cfe --- /dev/null +++ b/llvm/test/MC/AArch64/SVE2/fmmla-f8f16mm.s @@ -0,0 +1,39 @@ +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2,+f8f16mm < %s \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \ +// RUN: | FileCheck %s --check-prefix=CHECK-ERROR +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2,+f8f16mm < %s \ +// RUN: | llvm-objdump -d --mattr=+sve2,+f8f16mm - | FileCheck %s --check-prefix=CHECK-INST +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2,+f8f16mm < %s \ +// RUN: | llvm-objdump -d --mattr=-sve2 - | FileCheck %s --check-prefix=CHECK-UNKNOWN +// Disassemble encoding and check the re-encoding (-show-encoding) matches. +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2,+f8f16mm < %s \ +// RUN: | sed '/.text/d' | sed 's/.*encoding: //g' \ +// RUN: | llvm-mc -triple=aarch64 -mattr=+sve2,+f8f16mm -disassemble -show-encoding \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST + +movprfx z23, z31 +fmmla z23.h, z13.b, z8.b // 01100100-01101000-11100001-10110111 +// CHECK-INST: movprfx z23, z31 +// CHECK-INST: fmmla z23.h, z13.b, z8.b +// CHECK-ENCODING: [0xb7,0xe1,0x68,0x64] +// CHECK-ERROR: instruction requires: f8f16mm sve2 +// CHECK-UNKNOWN: 6468e1b7 + +fmmla z0.h, z0.b, z0.b // 01100100-01100000-11100000-00000000 +// CHECK-INST: fmmla z0.h, z0.b, z0.b +// CHECK-ENCODING: [0x00,0xe0,0x60,0x64] +// CHECK-ERROR: instruction requires: f8f16mm sve2 +// CHECK-UNKNOWN: 6460e000 + +fmmla z21.h, z10.b, z21.b // 01100100-01110101-11100001-01010101 +// CHECK-INST: fmmla z21.h, z10.b, z21.b +// CHECK-ENCODING: [0x55,0xe1,0x75,0x64] +// CHECK-ERROR: instruction requires: f8f16mm sve2 +// CHECK-UNKNOWN: 6475e155 + +fmmla z31.h, z31.b, z31.b // 01100100-01111111-11100011-11111111 +// CHECK-INST: fmmla z31.h, z31.b, z31.b +// CHECK-ENCODING: [0xff,0xe3,0x7f,0x64] +// CHECK-ERROR: instruction requires: f8f16mm sve2 +// CHECK-UNKNOWN: 647fe3ff \ No newline at end of file diff --git a/llvm/test/MC/AArch64/SVE2/fmmla-f8f32mm-diagnostics.s b/llvm/test/MC/AArch64/SVE2/fmmla-f8f32mm-diagnostics.s new file mode 100644 index 00000000000000..0b1eb1b24e2643 --- /dev/null +++ b/llvm/test/MC/AArch64/SVE2/fmmla-f8f32mm-diagnostics.s @@ -0,0 +1,30 @@ +// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2,+f8f32mm 2>&1 < %s| FileCheck %s + + +// ------------------------------------------------------------------------- // +// Invalid element width + +fmmla z21.b, z10.b, z21.b +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: fmmla z21.b, z10.b, z21.b +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +fmmla z21.h, z10.b, z21.b +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction requires: f8f16mm +// CHECK-NEXT: fmmla z21.h, z10.b, z21.b +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +fmmla z21.d, z10.b, z21.b +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: fmmla z21.d, z10.b, z21.b +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +fmmla z21.s, z10.h, z21.h +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction requires: sve-f16f32mm +// CHECK-NEXT: fmmla z21.s, z10.h, z21.h +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +fmmla z21.s, z10.s, z21.s +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction requires: f32mm +// CHECK-NEXT: fmmla z21.s, z10.s, z21.s +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: \ No newline at end of file diff --git a/llvm/test/MC/AArch64/SVE2/fmmla-f8f32mm.s b/llvm/test/MC/AArch64/SVE2/fmmla-f8f32mm.s new file mode 100644 index 00000000000000..8b59a112dc61b4 --- /dev/null +++ b/llvm/test/MC/AArch64/SVE2/fmmla-f8f32mm.s @@ -0,0 +1,39 @@ +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2,+f8f32mm < %s \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \ +// RUN: | FileCheck %s --check-prefix=CHECK-ERROR +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2,+f8f32mm < %s \ +// RUN: | llvm-objdump -d --mattr=+sve2,+f8f32mm - | FileCheck %s --check-prefix=CHECK-INST +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2,+f8f32mm < %s \ +// RUN: | llvm-objdump -d --mattr=-sve2 - | FileCheck %s --check-prefix=CHECK-UNKNOWN +// Disassemble encoding and check the re-encoding (-show-encoding) matches. +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2,+f8f32mm < %s \ +// RUN: | sed '/.text/d' | sed 's/.*encoding: //g' \ +// RUN: | llvm-mc -triple=aarch64 -mattr=+sve2,+f8f32mm -disassemble -show-encoding \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST + +movprfx z23, z31 +fmmla z23.s, z13.b, z8.b // 01100100-00101000-11100001-10110111 +// CHECK-INST: movprfx z23, z31 +// CHECK-INST: fmmla z23.s, z13.b, z8.b +// CHECK-ENCODING: [0xb7,0xe1,0x28,0x64] +// CHECK-ERROR: instruction requires: f8f32mm sve2 +// CHECK-UNKNOWN: 6428e1b7 + +fmmla z0.s, z0.b, z0.b // 01100100-00100000-11100000-00000000 +// CHECK-INST: fmmla z0.s, z0.b, z0.b +// CHECK-ENCODING: [0x00,0xe0,0x20,0x64] +// CHECK-ERROR: instruction requires: f8f32mm sve2 +// CHECK-UNKNOWN: 6420e000 + +fmmla z21.s, z10.b, z21.b // 01100100-00110101-11100001-01010101 +// CHECK-INST: fmmla z21.s, z10.b, z21.b +// CHECK-ENCODING: [0x55,0xe1,0x35,0x64] +// CHECK-ERROR: instruction requires: f8f32mm sve2 +// CHECK-UNKNOWN: 6435e155 + +fmmla z31.s, z31.b, z31.b // 01100100-00111111-11100011-11111111 +// CHECK-INST: fmmla z31.s, z31.b, z31.b +// CHECK-ENCODING: [0xff,0xe3,0x3f,0x64] +// CHECK-ERROR: instruction requires: f8f32mm sve2 +// CHECK-UNKNOWN: 643fe3ff diff --git a/llvm/test/MC/AArch64/SVE2p2/bfcvt_z-diagnostics.s b/llvm/test/MC/AArch64/SVE2p2/bfcvt_z-diagnostics.s new file mode 100644 index 00000000000000..30be5d19c4aae7 --- /dev/null +++ b/llvm/test/MC/AArch64/SVE2p2/bfcvt_z-diagnostics.s @@ -0,0 +1,60 @@ +// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2p2 2>&1 < %s| FileCheck %s + +// --------------------------------------------------------------------------// +// Invalid operand + +bfcvt z0.b, p0/z, z0.b +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction +// CHECK-NEXT: bfcvt z0.b, p0/z, z0.b +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +// --------------------------------------------------------------------------// +// Invalid element width + +bfcvt z0.h, p0/z, z0.h +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: bfcvt z0.h, p0/z, z0.h +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +bfcvt z0.h, p0/z, z0.d +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: bfcvt z0.h, p0/z, z0.d +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +bfcvt z0.s, p0/z, z0.s +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: bfcvt z0.s, p0/z, z0.s +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +bfcvt z0.s, p0/z, z0.d +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: bfcvt z0.s, p0/z, z0.d +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +bfcvt z0.d, p0/z, z0.d +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: bfcvt z0.d, p0/z, z0.d +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +// --------------------------------------------------------------------------// +// Predicate not in restricted predicate range + +bfcvt z0.h, p8/z, z0.s +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix) +// CHECK-NEXT: bfcvt z0.h, p8/z, z0.s +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +// --------------------------------------------------------------------------// +// Negative tests for instructions that are incompatible with movprfx + +movprfx z0.s, p0/m, z7.s +bfcvt z0.h, p7/z, z1.s +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: bfcvt z0.h, p7/z, z1.s +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +movprfx z0, z7 +bfcvt z0.h, p7/z, z1.s +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: bfcvt z0.h, p7/z, z1.s +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: diff --git a/llvm/test/MC/AArch64/SVE2p2/bfcvt_z.s b/llvm/test/MC/AArch64/SVE2p2/bfcvt_z.s new file mode 100644 index 00000000000000..9d63ebf1e83098 --- /dev/null +++ b/llvm/test/MC/AArch64/SVE2p2/bfcvt_z.s @@ -0,0 +1,33 @@ +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2p2 < %s \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2p2 < %s \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \ +// RUN: | FileCheck %s --check-prefix=CHECK-ERROR +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2p2 < %s \ +// RUN: | llvm-objdump -d --mattr=+sve2p2 - | FileCheck %s --check-prefix=CHECK-INST +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2p2 < %s \ +// RUN: | llvm-objdump -d --mattr=-sve2p2 - | FileCheck %s --check-prefix=CHECK-UNKNOWN +// Disassemble encoding and check the re-encoding (-show-encoding) matches. +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2p2 < %s \ +// RUN: | sed '/.text/d' | sed 's/.*encoding: //g' \ +// RUN: | llvm-mc -triple=aarch64 -mattr=+sve2p2 -disassemble -show-encoding \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST + +bfcvt z0.h, p0/z, z0.s // 01100100-10011010-11000000-00000000 +// CHECK-INST: bfcvt z0.h, p0/z, z0.s +// CHECK-ENCODING: [0x00,0xc0,0x9a,0x64] +// CHECK-ERROR: instruction requires: sme2p2 or sve2p2 +// CHECK-UNKNOWN: 649ac000 + +bfcvt z21.h, p5/z, z10.s // 01100100-10011010-11010101-01010101 +// CHECK-INST: bfcvt z21.h, p5/z, z10.s +// CHECK-ENCODING: [0x55,0xd5,0x9a,0x64] +// CHECK-ERROR: instruction requires: sme2p2 or sve2p2 +// CHECK-UNKNOWN: 649ad555 + +bfcvt z31.h, p7/z, z31.s // 01100100-10011010-11011111-11111111 +// CHECK-INST: bfcvt z31.h, p7/z, z31.s +// CHECK-ENCODING: [0xff,0xdf,0x9a,0x64] +// CHECK-ERROR: instruction requires: sme2p2 or sve2p2 +// CHECK-UNKNOWN: 649adfff \ No newline at end of file diff --git a/llvm/test/MC/AArch64/SVE2p2/compact-diagnostics.s b/llvm/test/MC/AArch64/SVE2p2/compact-diagnostics.s new file mode 100644 index 00000000000000..acf00e7f7a600f --- /dev/null +++ b/llvm/test/MC/AArch64/SVE2p2/compact-diagnostics.s @@ -0,0 +1,65 @@ +// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2p2 2>&1 < %s| FileCheck %s + +// --------------------------------------------------------------------------// +// Invalid element widths + +compact z31.h, p7, z31.b +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: compact z31.h, p7, z31.b +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +compact z31.b, p7, z31.h +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: compact z31.b, p7, z31.h +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +// --------------------------------------------------------------------------// +// Invalid predicate operation + +compact z23.b, p7/m, z13.b +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction +// CHECK-NEXT: compact z23.b, p7/m, z13.b +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +compact z23.b, p7.b, z13.b +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix) +// CHECK-NEXT: compact z23.b, p7.b, z13.b +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +compact z23.h, p7/z, z13.h +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction +// CHECK-NEXT: compact z23.h, p7/z, z13.h +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +compact z23.h, p7.h, z13.h +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix) +// CHECK-NEXT: compact z23.h, p7.h, z13.h +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +// --------------------------------------------------------------------------// +// Predicate not in restricted predicate range + +compact z23.b, p8, z13.b +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix) +// CHECK-NEXT: compact z23.b, p8, z13.b +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +compact z23.h, p8, z13.h +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix) +// CHECK-NEXT: compact z23.h, p8, z13.h +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +// --------------------------------------------------------------------------// +// Negative tests for instructions that are incompatible with movprfx + +movprfx z31.b, p7/z, z6.b +compact z31.b, p7, z31.b +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: compact z31.b, p7, z31.b +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +movprfx z31, z6 +compact z31.h, p7, z31.h +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: compact z31.h, p7, z31.h +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: diff --git a/llvm/test/MC/AArch64/SVE2p2/compact.s b/llvm/test/MC/AArch64/SVE2p2/compact.s new file mode 100644 index 00000000000000..0170b3832bea67 --- /dev/null +++ b/llvm/test/MC/AArch64/SVE2p2/compact.s @@ -0,0 +1,33 @@ +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2p2 < %s \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2p2 < %s \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \ +// RUN: | FileCheck %s --check-prefix=CHECK-ERROR +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2p2 < %s \ +// RUN: | llvm-objdump -d --mattr=+sve2p2 - | FileCheck %s --check-prefix=CHECK-INST +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2p2 < %s \ +// RUN: | llvm-objdump -d --mattr=-sve2p2 - | FileCheck %s --check-prefix=CHECK-UNKNOWN +// Disassemble encoding and check the re-encoding (-show-encoding) matches. +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2p2 < %s \ +// RUN: | sed '/.text/d' | sed 's/.*encoding: //g' \ +// RUN: | llvm-mc -triple=aarch64 -mattr=+sve2p2 -disassemble -show-encoding \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST + +compact z0.b, p0, z0.b // 00000101-00100001-10000000-00000000 +// CHECK-INST: compact z0.b, p0, z0.b +// CHECK-ENCODING: [0x00,0x80,0x21,0x05] +// CHECK-ERROR: instruction requires: sme2p2 or sve2p2 +// CHECK-UNKNOWN: 05218000 + +compact z21.b, p5, z10.b // 00000101-00100001-10010101-01010101 +// CHECK-INST: compact z21.b, p5, z10.b +// CHECK-ENCODING: [0x55,0x95,0x21,0x05] +// CHECK-ERROR: instruction requires: sme2p2 or sve2p2 +// CHECK-UNKNOWN: 05219555 + +compact z31.h, p7, z31.h // 00000101-01100001-10011111-11111111 +// CHECK-INST: compact z31.h, p7, z31.h +// CHECK-ENCODING: [0xff,0x9f,0x61,0x05] +// CHECK-ERROR: instruction requires: sme2p2 or sve2p2 +// CHECK-UNKNOWN: 05619fff \ No newline at end of file diff --git a/llvm/test/MC/AArch64/SVE2p2/expand-diagnostics.s b/llvm/test/MC/AArch64/SVE2p2/expand-diagnostics.s new file mode 100644 index 00000000000000..b9a95f399a168a --- /dev/null +++ b/llvm/test/MC/AArch64/SVE2p2/expand-diagnostics.s @@ -0,0 +1,120 @@ +// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2p2 2>&1 < %s| FileCheck %s + +// ------------------------------------------------------------------------- // +// Invalid element widths. + +expand z23.b, p3, z13.d +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: expand z23.b, p3, z13.d +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +expand z23.h, p3, z13.b +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: expand z23.h, p3, z13.b +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +expand z23.s, p3, z13.h +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: expand z23.s, p3, z13.h +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +expand z23.d, p3, z13.s +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: expand z23.d, p3, z13.s +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +expand z23.q, p3, z13.q +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: expand z23.q, p3, z13.q +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +// --------------------------------------------------------------------------// +// Invalid predicate operation + +expand z23.b, p3/z, z13.b +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction +// CHECK-NEXT: expand z23.b, p3/z, z13.b +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +expand z23.b, p3.b, z13.b +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix) +// CHECK-NEXT: expand z23.b, p3.b, z13.b +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +expand z23.h, p3/m, z13.h +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction +// CHECK-NEXT: expand z23.h, p3/m, z13.h +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +expand z23.h, p3.h, z13.h +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix) +// CHECK-NEXT: expand z23.h, p3.h, z13.h +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +expand z23.s, p3/z, z13.s +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction +// CHECK-NEXT: expand z23.s, p3/z, z13.s +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +expand z23.s, p3.s, z13.s +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix) +// CHECK-NEXT: expand z23.s, p3.s, z13.s +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +expand z23.d, p3/m, z13.d +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction +// CHECK-NEXT: expand z23.d, p3/m, z13.d +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +expand z23.d, p3.d, z13.d +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix) +// CHECK-NEXT: expand z23.d, p3.d, z13.d +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +// --------------------------------------------------------------------------// +// Predicate not in restricted predicate range + +expand z23.b, p8, z13.b +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix) +// CHECK-NEXT: expand z23.b, p8, z13.b +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +expand z23.b, p3.b, z13.b +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix) +// CHECK-NEXT: expand z23.b, p3.b, z13.b +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +expand z23.h, p8, z13.h +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix) +// CHECK-NEXT: expand z23.h, p8, z13.h +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +expand z23.h, p3.h, z13.h +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix) +// CHECK-NEXT: expand z23.h, p3.h, z13.h +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}} + +expand z23.s, p8, z13.s +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix) +// CHECK-NEXT: expand z23.s, p8, z13.s +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +expand z23.d, p8, z13.d +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix) +// CHECK-NEXT: expand z23.d, p8, z13.d +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +// --------------------------------------------------------------------------// +// Negative tests for instructions that are incompatible with movprfx + +movprfx z31, z6 +expand z31.b, p7, z31.b +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: expand z31.b, p7, z31.b +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +movprfx z31.b, p0/z, z6.b +expand z31.b, p0, z31.b +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: expand z31.b, p0, z31.b +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: diff --git a/llvm/test/MC/AArch64/SVE2p2/expand.s b/llvm/test/MC/AArch64/SVE2p2/expand.s new file mode 100644 index 00000000000000..7523978380fbd7 --- /dev/null +++ b/llvm/test/MC/AArch64/SVE2p2/expand.s @@ -0,0 +1,39 @@ +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2p2 < %s \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2p2 < %s \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \ +// RUN: | FileCheck %s --check-prefix=CHECK-ERROR +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2p2 < %s \ +// RUN: | llvm-objdump -d --mattr=+sve2p2 - | FileCheck %s --check-prefix=CHECK-INST +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2p2 < %s \ +// RUN: | llvm-objdump -d --mattr=-sve2p2 - | FileCheck %s --check-prefix=CHECK-UNKNOWN +// Disassemble encoding and check the re-encoding (-show-encoding) matches. +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2p2 < %s \ +// RUN: | sed '/.text/d' | sed 's/.*encoding: //g' \ +// RUN: | llvm-mc -triple=aarch64 -mattr=+sve2p2 -disassemble -show-encoding \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST + +expand z0.b, p0, z0.b // 00000101-00110001-10000000-00000000 +// CHECK-INST: expand z0.b, p0, z0.b +// CHECK-ENCODING: [0x00,0x80,0x31,0x05] +// CHECK-ERROR: instruction requires: sme2p2 or sve2p2 +// CHECK-UNKNOWN: 05318000 + +expand z21.h, p5, z10.h // 00000101-01110001-10010101-01010101 +// CHECK-INST: expand z21.h, p5, z10.h +// CHECK-ENCODING: [0x55,0x95,0x71,0x05] +// CHECK-ERROR: instruction requires: sme2p2 or sve2p2 +// CHECK-UNKNOWN: 05719555 + +expand z23.s, p3, z13.s // 00000101-10110001-10001101-10110111 +// CHECK-INST: expand z23.s, p3, z13.s +// CHECK-ENCODING: [0xb7,0x8d,0xb1,0x05] +// CHECK-ERROR: instruction requires: sme2p2 or sve2p2 +// CHECK-UNKNOWN: 05b18db7 + +expand z31.d, p7, z31.d // 00000101-11110001-10011111-11111111 +// CHECK-INST: expand z31.d, p7, z31.d +// CHECK-ENCODING: [0xff,0x9f,0xf1,0x05] +// CHECK-ERROR: instruction requires: sme2p2 or sve2p2 +// CHECK-UNKNOWN: 05f19fff \ No newline at end of file diff --git a/llvm/test/MC/AArch64/SVE2p2/fcvt_z-diagnostics.s b/llvm/test/MC/AArch64/SVE2p2/fcvt_z-diagnostics.s new file mode 100644 index 00000000000000..37f4a0ffbe6a2a --- /dev/null +++ b/llvm/test/MC/AArch64/SVE2p2/fcvt_z-diagnostics.s @@ -0,0 +1,50 @@ +// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2p2 2>&1 < %s| FileCheck %s + +// --------------------------------------------------------------------------// +// Invalid operand + +fcvt z0.b, p0/z, z0.h +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction +// CHECK-NEXT: fcvt z0.b, p0/z, z0.h +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +// --------------------------------------------------------------------------// +// Invalid element width + +fcvt z0.h, p0/z, z0.h +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: fcvt z0.h, p0/z, z0.h +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +fcvt z0.s, p0/z, z0.s +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: fcvt z0.s, p0/z, z0.s +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +fcvt z0.d, p0/z, z0.d +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: fcvt z0.d, p0/z, z0.d +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +// --------------------------------------------------------------------------// +// Predicate not in restricted predicate range + +fcvt z0.s, p8/z, z0.d +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix) +// CHECK-NEXT: fcvt z0.s, p8/z, z0.d +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +// --------------------------------------------------------------------------// +// Negative tests for instructions that are incompatible with movprfx + +movprfx z0.s, p0/m, z7.s +fcvt z0.s, p7/z, z1.d +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: fcvt z0.s, p7/z, z1.d +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +movprfx z0, z7 +fcvt z0.s, p7/z, z1.d +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: fcvt z0.s, p7/z, z1.d +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: diff --git a/llvm/test/MC/AArch64/SVE2p2/fcvt_z.s b/llvm/test/MC/AArch64/SVE2p2/fcvt_z.s new file mode 100644 index 00000000000000..6cd9f1ba503210 --- /dev/null +++ b/llvm/test/MC/AArch64/SVE2p2/fcvt_z.s @@ -0,0 +1,57 @@ +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2p2 < %s \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2p2 < %s \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \ +// RUN: | FileCheck %s --check-prefix=CHECK-ERROR +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2p2 < %s \ +// RUN: | llvm-objdump -d --mattr=+sve2p2 - | FileCheck %s --check-prefix=CHECK-INST +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2p2 < %s \ +// RUN: | llvm-objdump -d --mattr=-sve2p2 - | FileCheck %s --check-prefix=CHECK-UNKNOWN +// Disassemble encoding and check the re-encoding (-show-encoding) matches. +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2p2 < %s \ +// RUN: | sed '/.text/d' | sed 's/.*encoding: //g' \ +// RUN: | llvm-mc -triple=aarch64 -mattr=+sve2p2 -disassemble -show-encoding \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST + +// convert to half + +fcvt z0.h, p0/z, z0.s // 01100100-10011010-10000000-00000000 +// CHECK-INST: fcvt z0.h, p0/z, z0.s +// CHECK-ENCODING: [0x00,0x80,0x9a,0x64] +// CHECK-ERROR: instruction requires: sme2p2 or sve2p2 +// CHECK-UNKNOWN: 649a8000 + +fcvt z23.h, p3/z, z13.d // 01100100-11011010-10001101-10110111 +// CHECK-INST: fcvt z23.h, p3/z, z13.d +// CHECK-ENCODING: [0xb7,0x8d,0xda,0x64] +// CHECK-ERROR: instruction requires: sme2p2 or sve2p2 +// CHECK-UNKNOWN: 64da8db7 + +// convert to single + +fcvt z0.s, p0/z, z0.h // 01100100-10011010-10100000-00000000 +// CHECK-INST: fcvt z0.s, p0/z, z0.h +// CHECK-ENCODING: [0x00,0xa0,0x9a,0x64] +// CHECK-ERROR: instruction requires: sme2p2 or sve2p2 +// CHECK-UNKNOWN: 649aa000 + +fcvt z31.s, p7/z, z31.d // 01100100-11011010-11011111-11111111 +// CHECK-INST: fcvt z31.s, p7/z, z31.d +// CHECK-ENCODING: [0xff,0xdf,0xda,0x64] +// CHECK-ERROR: instruction requires: sme2p2 or sve2p2 +// CHECK-UNKNOWN: 64dadfff + +// convert to double + +fcvt z21.d, p5/z, z10.h // 01100100-11011010-10110101-01010101 +// CHECK-INST: fcvt z21.d, p5/z, z10.h +// CHECK-ENCODING: [0x55,0xb5,0xda,0x64] +// CHECK-ERROR: instruction requires: sme2p2 or sve2p2 +// CHECK-UNKNOWN: 64dab555 + +fcvt z31.d, p7/z, z31.s // 01100100-11011010-11111111-11111111 +// CHECK-INST: fcvt z31.d, p7/z, z31.s +// CHECK-ENCODING: [0xff,0xff,0xda,0x64] +// CHECK-ERROR: instruction requires: sme2p2 or sve2p2 +// CHECK-UNKNOWN: 64daffff &1 < %s| FileCheck %s + +// --------------------------------------------------------------------------// +// Invalid element width + +fcvtx z0.b, p0/z, z0.b +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: fcvtx z0.b, p0/z, z0.b +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +fcvtx z0.h, p0/z, z0.h +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: fcvtx z0.h, p0/z, z0.h +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +fcvtx z0.s, p0/z, z0.s +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: fcvtx z0.s, p0/z, z0.s +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +fcvtx z0.d, p0/z, z0.d +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: fcvtx z0.d, p0/z, z0.d +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +fcvtx z0.h, p0/z, z0.s +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: fcvtx z0.h, p0/z, z0.s +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +fcvtx z0.b, p0/z, z0.h +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: fcvtx z0.b, p0/z, z0.h +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +// --------------------------------------------------------------------------// +// Predicate not in restricted predicate range + +fcvtx z0.s, p8/z, z0.d +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix) +// CHECK-NEXT: fcvtx z0.s, p8/z, z0.d +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +// --------------------------------------------------------------------------// +// Negative tests for instructions that are incompatible with movprfx + +movprfx z0.s, p0/m, z7.s +fcvtx z0.s, p7/z, z1.d +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: fcvtx z0.s, p7/z, z1.d +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +movprfx z0, z7 +fcvtx z0.s, p7/z, z1.d +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: fcvtx z0.s, p7/z, z1.d +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: diff --git a/llvm/test/MC/AArch64/SVE2p2/fcvtx_z.s b/llvm/test/MC/AArch64/SVE2p2/fcvtx_z.s new file mode 100644 index 00000000000000..e5e2155ea5d878 --- /dev/null +++ b/llvm/test/MC/AArch64/SVE2p2/fcvtx_z.s @@ -0,0 +1,33 @@ +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2p2 < %s \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2p2 < %s \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \ +// RUN: | FileCheck %s --check-prefix=CHECK-ERROR +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2p2 < %s \ +// RUN: | llvm-objdump -d --mattr=+sve2p2 - | FileCheck %s --check-prefix=CHECK-INST +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2p2 < %s \ +// RUN: | llvm-objdump -d --mattr=-sve2p2 - | FileCheck %s --check-prefix=CHECK-UNKNOWN +// Disassemble encoding and check the re-encoding (-show-encoding) matches. +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2p2 < %s \ +// RUN: | sed '/.text/d' | sed 's/.*encoding: //g' \ +// RUN: | llvm-mc -triple=aarch64 -mattr=+sve2p2 -disassemble -show-encoding \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST + +fcvtx z0.s, p0/z, z0.d // 01100100-00011010-11000000-00000000 +// CHECK-INST: fcvtx z0.s, p0/z, z0.d +// CHECK-ENCODING: [0x00,0xc0,0x1a,0x64] +// CHECK-ERROR: instruction requires: sme2p2 or sve2p2 +// CHECK-UNKNOWN: 641ac000 + +fcvtx z23.s, p3/z, z13.d // 01100100-00011010-11001101-10110111 +// CHECK-INST: fcvtx z23.s, p3/z, z13.d +// CHECK-ENCODING: [0xb7,0xcd,0x1a,0x64] +// CHECK-ERROR: instruction requires: sme2p2 or sve2p2 +// CHECK-UNKNOWN: 641acdb7 + +fcvtx z31.s, p7/z, z31.d // 01100100-00011010-11011111-11111111 +// CHECK-INST: fcvtx z31.s, p7/z, z31.d +// CHECK-ENCODING: [0xff,0xdf,0x1a,0x64] +// CHECK-ERROR: instruction requires: sme2p2 or sve2p2 +// CHECK-UNKNOWN: 641adfff diff --git a/llvm/test/MC/AArch64/SVE2p2/firstp-diagnostics.s b/llvm/test/MC/AArch64/SVE2p2/firstp-diagnostics.s new file mode 100644 index 00000000000000..4309fd49ecf79f --- /dev/null +++ b/llvm/test/MC/AArch64/SVE2p2/firstp-diagnostics.s @@ -0,0 +1,32 @@ +// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2p2 2>&1 < %s| FileCheck %s + +// ------------------------------------------------------------------------- // +// Invalid predicate operand + +firstp x0, p15, p0 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate register. +// CHECK-NEXT: firstp x0, p15, p0 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +firstp x0, p15.b, p0.b +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate register. +// CHECK-NEXT: firstp x0, p15.b, p0.b +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +firstp x0, p15.q, p0.h +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate register. +// CHECK-NEXT: firstp x0, p15.q, p0.h +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +// ------------------------------------------------------------------------- // +// Invalid register types + +firstp sp, p15, p0.h +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction +// CHECK-NEXT: firstp sp, p15, p0.h +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +firstp w0, p15, p0.h +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction +// CHECK-NEXT: firstp w0, p15, p0.h +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: diff --git a/llvm/test/MC/AArch64/SVE2p2/firstp.s b/llvm/test/MC/AArch64/SVE2p2/firstp.s new file mode 100644 index 00000000000000..629bee5576fc7d --- /dev/null +++ b/llvm/test/MC/AArch64/SVE2p2/firstp.s @@ -0,0 +1,87 @@ +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2p2 < %s \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2p2 < %s \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \ +// RUN: | FileCheck %s --check-prefix=CHECK-ERROR +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2p2 < %s \ +// RUN: | llvm-objdump -d --mattr=+sve2p2 - | FileCheck %s --check-prefix=CHECK-INST +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2p2 < %s \ +// RUN: | llvm-objdump -d --mattr=-sme2 - | FileCheck %s --check-prefix=CHECK-UNKNOWN +// Disassemble encoding and check the re-encoding (-show-encoding) matches. +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2p2 < %s \ +// RUN: | sed '/.text/d' | sed 's/.*encoding: //g' \ +// RUN: | llvm-mc -triple=aarch64 -mattr=+sve2p2 -disassemble -show-encoding \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST + +firstp x0, p0, p0.b // 00100101-00100001-10000000-00000000 +// CHECK-INST: firstp x0, p0, p0.b +// CHECK-ENCODING: [0x00,0x80,0x21,0x25] +// CHECK-ERROR: instruction requires: sme2p2 or sve2p2 +// CHECK-UNKNOWN: 25218000 + +firstp x23, p11, p13.b // 00100101-00100001-10101101-10110111 +// CHECK-INST: firstp x23, p11, p13.b +// CHECK-ENCODING: [0xb7,0xad,0x21,0x25] +// CHECK-ERROR: instruction requires: sme2p2 or sve2p2 +// CHECK-UNKNOWN: 2521adb7 + +firstp xzr, p15, p15.b // 00100101-00100001-10111101-11111111 +// CHECK-INST: firstp xzr, p15, p15.b +// CHECK-ENCODING: [0xff,0xbd,0x21,0x25] +// CHECK-ERROR: instruction requires: sme2p2 or sve2p2 +// CHECK-UNKNOWN: 2521bdff + +firstp x0, p0, p0.h // 00100101-01100001-10000000-00000000 +// CHECK-INST: firstp x0, p0, p0.h +// CHECK-ENCODING: [0x00,0x80,0x61,0x25] +// CHECK-ERROR: instruction requires: sme2p2 or sve2p2 +// CHECK-UNKNOWN: 25618000 + +firstp x23, p11, p13.h // 00100101-01100001-10101101-10110111 +// CHECK-INST: firstp x23, p11, p13.h +// CHECK-ENCODING: [0xb7,0xad,0x61,0x25] +// CHECK-ERROR: instruction requires: sme2p2 or sve2p2 +// CHECK-UNKNOWN: 2561adb7 + +firstp xzr, p15, p15.h // 00100101-01100001-10111101-11111111 +// CHECK-INST: firstp xzr, p15, p15.h +// CHECK-ENCODING: [0xff,0xbd,0x61,0x25] +// CHECK-ERROR: instruction requires: sme2p2 or sve2p2 +// CHECK-UNKNOWN: 2561bdff + +firstp x0, p0, p0.s // 00100101-10100001-10000000-00000000 +// CHECK-INST: firstp x0, p0, p0.s +// CHECK-ENCODING: [0x00,0x80,0xa1,0x25] +// CHECK-ERROR: instruction requires: sme2p2 or sve2p2 +// CHECK-UNKNOWN: 25a18000 + +firstp x23, p11, p13.s // 00100101-10100001-10101101-10110111 +// CHECK-INST: firstp x23, p11, p13.s +// CHECK-ENCODING: [0xb7,0xad,0xa1,0x25] +// CHECK-ERROR: instruction requires: sme2p2 or sve2p2 +// CHECK-UNKNOWN: 25a1adb7 + +firstp xzr, p15, p15.s // 00100101-10100001-10111101-11111111 +// CHECK-INST: firstp xzr, p15, p15.s +// CHECK-ENCODING: [0xff,0xbd,0xa1,0x25] +// CHECK-ERROR: instruction requires: sme2p2 or sve2p2 +// CHECK-UNKNOWN: 25a1bdff + +firstp x0, p0, p0.d // 00100101-11100001-10000000-00000000 +// CHECK-INST: firstp x0, p0, p0.d +// CHECK-ENCODING: [0x00,0x80,0xe1,0x25] +// CHECK-ERROR: instruction requires: sme2p2 or sve2p2 +// CHECK-UNKNOWN: 25e18000 + +firstp x23, p11, p13.d // 00100101-11100001-10101101-10110111 +// CHECK-INST: firstp x23, p11, p13.d +// CHECK-ENCODING: [0xb7,0xad,0xe1,0x25] +// CHECK-ERROR: instruction requires: sme2p2 or sve2p2 +// CHECK-UNKNOWN: 25e1adb7 + +firstp xzr, p15, p15.d // 00100101-11100001-10111101-11111111 +// CHECK-INST: firstp xzr, p15, p15.d +// CHECK-ENCODING: [0xff,0xbd,0xe1,0x25] +// CHECK-ERROR: instruction requires: sme2p2 or sve2p2 +// CHECK-UNKNOWN: 25e1bdff \ No newline at end of file diff --git a/llvm/test/MC/AArch64/SVE2p2/lastp-diagnostics.s b/llvm/test/MC/AArch64/SVE2p2/lastp-diagnostics.s new file mode 100644 index 00000000000000..e277bdbc6aa8b3 --- /dev/null +++ b/llvm/test/MC/AArch64/SVE2p2/lastp-diagnostics.s @@ -0,0 +1,32 @@ +// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2p2 2>&1 < %s| FileCheck %s + +// ------------------------------------------------------------------------- // +// Invalid predicate operand + +lastp x0, p15, p0 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate register. +// CHECK-NEXT: lastp x0, p15, p0 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +lastp x0, p15.b, p0.b +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate register. +// CHECK-NEXT: lastp x0, p15.b, p0.b +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +lastp x0, p15.q, p0.h +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate register. +// CHECK-NEXT: lastp x0, p15.q, p0.h +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +// ------------------------------------------------------------------------- // +// Invalid register types + +lastp sp, p15, p0.h +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction +// CHECK-NEXT: lastp sp, p15, p0.h +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +lastp w0, p15, p0.h +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction +// CHECK-NEXT: lastp w0, p15, p0.h +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: \ No newline at end of file diff --git a/llvm/test/MC/AArch64/SVE2p2/lastp.s b/llvm/test/MC/AArch64/SVE2p2/lastp.s new file mode 100644 index 00000000000000..1ffa0a7d1fcc19 --- /dev/null +++ b/llvm/test/MC/AArch64/SVE2p2/lastp.s @@ -0,0 +1,87 @@ +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2p2 < %s \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2p2 < %s \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \ +// RUN: | FileCheck %s --check-prefix=CHECK-ERROR +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2p2 < %s \ +// RUN: | llvm-objdump -d --mattr=+sve2p2 - | FileCheck %s --check-prefix=CHECK-INST +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2p2 < %s \ +// RUN: | llvm-objdump -d --mattr=-sme2 - | FileCheck %s --check-prefix=CHECK-UNKNOWN +// Disassemble encoding and check the re-encoding (-show-encoding) matches. +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2p2 < %s \ +// RUN: | sed '/.text/d' | sed 's/.*encoding: //g' \ +// RUN: | llvm-mc -triple=aarch64 -mattr=+sve2p2 -disassemble -show-encoding \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST + +lastp x0, p0, p0.b // 00100101-00100010-10000000-00000000 +// CHECK-INST: lastp x0, p0, p0.b +// CHECK-ENCODING: [0x00,0x80,0x22,0x25] +// CHECK-ERROR: instruction requires: sme2p2 or sve2p2 +// CHECK-UNKNOWN: 25228000 + +lastp x23, p11, p13.b // 00100101-00100010-10101101-10110111 +// CHECK-INST: lastp x23, p11, p13.b +// CHECK-ENCODING: [0xb7,0xad,0x22,0x25] +// CHECK-ERROR: instruction requires: sme2p2 or sve2p2 +// CHECK-UNKNOWN: 2522adb7 + +lastp xzr, p15, p15.b // 00100101-00100010-10111101-11111111 +// CHECK-INST: lastp xzr, p15, p15.b +// CHECK-ENCODING: [0xff,0xbd,0x22,0x25] +// CHECK-ERROR: instruction requires: sme2p2 or sve2p2 +// CHECK-UNKNOWN: 2522bdff + +lastp x0, p0, p0.h // 00100101-01100010-10000000-00000000 +// CHECK-INST: lastp x0, p0, p0.h +// CHECK-ENCODING: [0x00,0x80,0x62,0x25] +// CHECK-ERROR: instruction requires: sme2p2 or sve2p2 +// CHECK-UNKNOWN: 25628000 + +lastp x23, p11, p13.h // 00100101-01100010-10101101-10110111 +// CHECK-INST: lastp x23, p11, p13.h +// CHECK-ENCODING: [0xb7,0xad,0x62,0x25] +// CHECK-ERROR: instruction requires: sme2p2 or sve2p2 +// CHECK-UNKNOWN: 2562adb7 + +lastp xzr, p15, p15.h // 00100101-01100010-10111101-11111111 +// CHECK-INST: lastp xzr, p15, p15.h +// CHECK-ENCODING: [0xff,0xbd,0x62,0x25] +// CHECK-ERROR: instruction requires: sme2p2 or sve2p2 +// CHECK-UNKNOWN: 2562bdff + +lastp x0, p0, p0.s // 00100101-10100010-10000000-00000000 +// CHECK-INST: lastp x0, p0, p0.s +// CHECK-ENCODING: [0x00,0x80,0xa2,0x25] +// CHECK-ERROR: instruction requires: sme2p2 or sve2p2 +// CHECK-UNKNOWN: 25a28000 + +lastp x23, p11, p13.s // 00100101-10100010-10101101-10110111 +// CHECK-INST: lastp x23, p11, p13.s +// CHECK-ENCODING: [0xb7,0xad,0xa2,0x25] +// CHECK-ERROR: instruction requires: sme2p2 or sve2p2 +// CHECK-UNKNOWN: 25a2adb7 + +lastp xzr, p15, p15.s // 00100101-10100010-10111101-11111111 +// CHECK-INST: lastp xzr, p15, p15.s +// CHECK-ENCODING: [0xff,0xbd,0xa2,0x25] +// CHECK-ERROR: instruction requires: sme2p2 or sve2p2 +// CHECK-UNKNOWN: 25a2bdff + +lastp x0, p0, p0.d // 00100101-11100010-10000000-00000000 +// CHECK-INST: lastp x0, p0, p0.d +// CHECK-ENCODING: [0x00,0x80,0xe2,0x25] +// CHECK-ERROR: instruction requires: sme2p2 or sve2p2 +// CHECK-UNKNOWN: 25e28000 + +lastp x23, p11, p13.d // 00100101-11100010-10101101-10110111 +// CHECK-INST: lastp x23, p11, p13.d +// CHECK-ENCODING: [0xb7,0xad,0xe2,0x25] +// CHECK-ERROR: instruction requires: sme2p2 or sve2p2 +// CHECK-UNKNOWN: 25e2adb7 + +lastp xzr, p15, p15.d // 00100101-11100010-10111101-11111111 +// CHECK-INST: lastp xzr, p15, p15.d +// CHECK-ENCODING: [0xff,0xbd,0xe2,0x25] +// CHECK-ERROR: instruction requires: sme2p2 or sve2p2 +// CHECK-UNKNOWN: 25e2bdff \ No newline at end of file diff --git a/llvm/test/MC/AMDGPU/gfx12_asm_vimage.s b/llvm/test/MC/AMDGPU/gfx12_asm_vimage.s index 196d75db426052..8bf9b92e8d1d8d 100644 --- a/llvm/test/MC/AMDGPU/gfx12_asm_vimage.s +++ b/llvm/test/MC/AMDGPU/gfx12_asm_vimage.s @@ -158,6 +158,12 @@ image_load v[0:2], [v4, v5], s[8:15] dmask:0xf dim:SQ_RSRC_IMG_2D_ARRAY th:TH_LO image_load v[4:7], [v1, v0], s[4:11] dmask:0xf dim:SQ_RSRC_IMG_2D // GFX12: encoding: [0x01,0x00,0xc0,0xd3,0x04,0x08,0x00,0x00,0x01,0x00,0x00,0x00] +image_load v[1:4], [v2, v1, v0], s[4:11] dmask:0xf dim:SQ_RSRC_IMG_3D +// GFX12: encoding: [0x02,0x00,0xc0,0xd3,0x01,0x08,0x00,0x00,0x02,0x01,0x00,0x00] + +image_load v[1:4], [v3, v2, v1, v0], s[4:11] dmask:0xf dim:SQ_RSRC_IMG_2D_MSAA_ARRAY +// GFX12: encoding: [0x07,0x00,0xc0,0xd3,0x01,0x08,0x00,0x00,0x03,0x02,0x01,0x00] + image_load_mip v[252:255], [v0, v1], s[0:7] dmask:0xf dim:SQ_RSRC_IMG_1D // GFX12: encoding: [0x00,0x40,0xc0,0xd3,0xfc,0x00,0x00,0x00,0x00,0x01,0x00,0x00] @@ -408,6 +414,12 @@ image_store v0, v0, s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_1D th:TH_STORE_BYPASS scope image_store v[1:4], [v2, v0], s[4:11] dmask:0xf dim:SQ_RSRC_IMG_2D // GFX12: encoding: [0x01,0x80,0xc1,0xd3,0x01,0x08,0x00,0x00,0x02,0x00,0x00,0x00] +image_store v[1:4], [v2, v1, v0], s[4:11] dmask:0xf dim:SQ_RSRC_IMG_3D +// GFX12: encoding: [0x02,0x80,0xc1,0xd3,0x01,0x08,0x00,0x00,0x02,0x01,0x00,0x00] + +image_store v[1:4], [v3, v2, v1, v0], s[4:11] dmask:0xf dim:SQ_RSRC_IMG_2D_MSAA_ARRAY +// GFX12: encoding: [0x07,0x80,0xc1,0xd3,0x01,0x08,0x00,0x00,0x03,0x02,0x01,0x00] + image_store_mip v[252:255], [v0, v1], s[0:7] dmask:0xf dim:SQ_RSRC_IMG_1D // GFX12: encoding: [0x00,0xc0,0xc1,0xd3,0xfc,0x00,0x00,0x00,0x00,0x01,0x00,0x00] @@ -568,6 +580,12 @@ image_atomic_swap v[254:255], [v4, v5], s[96:103] dmask:0x3 dim:SQ_RSRC_IMG_2D_M image_atomic_swap v1, [v2, v0], s[4:11] dmask:0x1 dim:SQ_RSRC_IMG_2D // GFX12: encoding: [0x01,0x80,0x42,0xd0,0x01,0x08,0x00,0x00,0x02,0x00,0x00,0x00] +image_atomic_swap v1, [v2, v1, v0], s[4:11] dmask:0x1 dim:SQ_RSRC_IMG_3D +// GFX12: encoding: [0x02,0x80,0x42,0xd0,0x01,0x08,0x00,0x00,0x02,0x01,0x00,0x00] + +image_atomic_swap v1, [v3, v2, v1, v0], s[4:11] dmask:0x1 dim:SQ_RSRC_IMG_2D_MSAA_ARRAY +// GFX12: encoding: [0x07,0x80,0x42,0xd0,0x01,0x08,0x00,0x00,0x03,0x02,0x01,0x00] + image_atomic_cmpswap v[0:1], v0, s[0:7] dmask:0x3 dim:SQ_RSRC_IMG_1D // GFX12: encoding: [0x00,0xc0,0xc2,0xd0,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00] @@ -625,6 +643,12 @@ image_atomic_add_uint v0, v0, s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_1D th:TH_ATOMIC_N image_atomic_add_uint v1, [v2, v0], s[4:11] dmask:0x1 dim:SQ_RSRC_IMG_2D // GFX12: encoding: [0x01,0x00,0x43,0xd0,0x01,0x08,0x00,0x00,0x02,0x00,0x00,0x00] +image_atomic_add_uint v1, [v2, v1, v0], s[4:11] dmask:0x1 dim:SQ_RSRC_IMG_3D +// GFX12: encoding: [0x02,0x00,0x43,0xd0,0x01,0x08,0x00,0x00,0x02,0x01,0x00,0x00] + +image_atomic_add_uint v1, [v3, v2, v1, v0], s[4:11] dmask:0x1 dim:SQ_RSRC_IMG_2D_MSAA_ARRAY +// GFX12: encoding: [0x07,0x00,0x43,0xd0,0x01,0x08,0x00,0x00,0x03,0x02,0x01,0x00] + image_atomic_sub_uint v0, v0, s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_1D // GFX12: encoding: [0x00,0x40,0x43,0xd0,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00] diff --git a/llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vimage.txt b/llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vimage.txt index 08e9bef8cf6785..233c2e1b9d083b 100644 --- a/llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vimage.txt +++ b/llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vimage.txt @@ -160,6 +160,12 @@ # GFX12: image_load v[4:7], [v1, v0], s[4:11] dmask:0xf dim:SQ_RSRC_IMG_2D ; encoding: [0x01,0x00,0xc0,0xd3,0x04,0x08,0x00,0x00,0x01,0x00,0x00,0x00] 0x01,0x00,0xc0,0xd3,0x04,0x08,0x00,0x00,0x01,0x00,0x00,0x00 +# GFX12: image_load v[1:4], [v2, v1, v0], s[4:11] dmask:0xf dim:SQ_RSRC_IMG_3D ; encoding: [0x02,0x00,0xc0,0xd3,0x01,0x08,0x00,0x00,0x02,0x01,0x00,0x00] +0x02,0x00,0xc0,0xd3,0x01,0x08,0x00,0x00,0x02,0x01,0x00,0x00 + +# GFX12: image_load v[1:4], [v3, v2, v1, v0], s[4:11] dmask:0xf dim:SQ_RSRC_IMG_2D_MSAA_ARRAY ; encoding: [0x07,0x00,0xc0,0xd3,0x01,0x08,0x00,0x00,0x03,0x02,0x01,0x00] +0x07,0x00,0xc0,0xd3,0x01,0x08,0x00,0x00,0x03,0x02,0x01,0x00 + # GFX12: image_load_mip v[252:255], [v0, v1], s[0:7] dmask:0xf dim:SQ_RSRC_IMG_1D ; encoding: [0x00,0x40,0xc0,0xd3,0xfc,0x00,0x00,0x00,0x00,0x01,0x00,0x00] 0x00,0x40,0xc0,0xd3,0xfc,0x00,0x00,0x00,0x00,0x01,0x00,0x00 @@ -409,6 +415,12 @@ # GFX12: image_store v[1:4], [v2, v0], s[4:11] dmask:0xf dim:SQ_RSRC_IMG_2D ; encoding: [0x01,0x80,0xc1,0xd3,0x01,0x08,0x00,0x00,0x02,0x00,0x00,0x00] 0x01,0x80,0xc1,0xd3,0x01,0x08,0x00,0x00,0x02,0x00,0x00,0x00 +# GFX12: image_store v[1:4], [v2, v1, v0], s[4:11] dmask:0xf dim:SQ_RSRC_IMG_3D ; encoding: [0x02,0x80,0xc1,0xd3,0x01,0x08,0x00,0x00,0x02,0x01,0x00,0x00] +0x02,0x80,0xc1,0xd3,0x01,0x08,0x00,0x00,0x02,0x01,0x00,0x00 + +# GFX12: image_store v[1:4], [v3, v2, v1, v0], s[4:11] dmask:0xf dim:SQ_RSRC_IMG_2D_MSAA_ARRAY ; encoding: [0x07,0x80,0xc1,0xd3,0x01,0x08,0x00,0x00,0x03,0x02,0x01,0x00] +0x07,0x80,0xc1,0xd3,0x01,0x08,0x00,0x00,0x03,0x02,0x01,0x00 + # GFX12: image_store_mip v[252:255], [v0, v1], s[0:7] dmask:0xf dim:SQ_RSRC_IMG_1D ; encoding: [0x00,0xc0,0xc1,0xd3,0xfc,0x00,0x00,0x00,0x00,0x01,0x00,0x00] 0x00,0xc0,0xc1,0xd3,0xfc,0x00,0x00,0x00,0x00,0x01,0x00,0x00 @@ -568,6 +580,12 @@ # GFX12: image_atomic_swap v1, [v2, v0], s[4:11] dmask:0x1 dim:SQ_RSRC_IMG_2D ; encoding: [0x01,0x80,0x42,0xd0,0x01,0x08,0x00,0x00,0x02,0x00,0x00,0x00] 0x01,0x80,0x42,0xd0,0x01,0x08,0x00,0x00,0x02,0x00,0x00,0x00 +# GFX12: image_atomic_swap v1, [v2, v1, v0], s[4:11] dmask:0x1 dim:SQ_RSRC_IMG_3D ; encoding: [0x02,0x80,0x42,0xd0,0x01,0x08,0x00,0x00,0x02,0x01,0x00,0x00] +0x02,0x80,0x42,0xd0,0x01,0x08,0x00,0x00,0x02,0x01,0x00,0x00 + +# GFX12: image_atomic_swap v1, [v3, v2, v1, v0], s[4:11] dmask:0x1 dim:SQ_RSRC_IMG_2D_MSAA_ARRAY ; encoding: [0x07,0x80,0x42,0xd0,0x01,0x08,0x00,0x00,0x03,0x02,0x01,0x00] +0x07,0x80,0x42,0xd0,0x01,0x08,0x00,0x00,0x03,0x02,0x01,0x00 + # GFX12: image_atomic_cmpswap v[0:1], v0, s[0:7] dmask:0x3 dim:SQ_RSRC_IMG_1D ; encoding: [0x00,0xc0,0xc2,0xd0,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00] 0x00,0xc0,0xc2,0xd0,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 @@ -625,6 +643,12 @@ # GFX12: image_atomic_add_uint v1, [v2, v0], s[4:11] dmask:0x1 dim:SQ_RSRC_IMG_2D ; encoding: [0x01,0x00,0x43,0xd0,0x01,0x08,0x00,0x00,0x02,0x00,0x00,0x00] 0x01,0x00,0x43,0xd0,0x01,0x08,0x00,0x00,0x02,0x00,0x00,0x00 +# GFX12: image_atomic_add_uint v1, [v2, v1, v0], s[4:11] dmask:0x1 dim:SQ_RSRC_IMG_3D ; encoding: [0x02,0x00,0x43,0xd0,0x01,0x08,0x00,0x00,0x02,0x01,0x00,0x00] +0x02,0x00,0x43,0xd0,0x01,0x08,0x00,0x00,0x02,0x01,0x00,0x00 + +# GFX12: image_atomic_add_uint v1, [v3, v2, v1, v0], s[4:11] dmask:0x1 dim:SQ_RSRC_IMG_2D_MSAA_ARRAY ; encoding: [0x07,0x00,0x43,0xd0,0x01,0x08,0x00,0x00,0x03,0x02,0x01,0x00] +0x07,0x00,0x43,0xd0,0x01,0x08,0x00,0x00,0x03,0x02,0x01,0x00 + # GFX12: image_atomic_sub_uint v0, v0, s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_1D ; encoding: [0x00,0x40,0x43,0xd0,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00] 0x00,0x40,0x43,0xd0,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 diff --git a/llvm/test/TableGen/64-bit-int.td b/llvm/test/TableGen/64-bit-int.td index 2d2bdb8b560e2c..d2a2999c14e991 100644 --- a/llvm/test/TableGen/64-bit-int.td +++ b/llvm/test/TableGen/64-bit-int.td @@ -16,7 +16,7 @@ def { #ifdef OOR3 bits<64> Val = 0x10000000000000000; #endif -// CHECK-OOR: error: Number out of range +// CHECK-OOR: error: number out of range bits<64> BinVal0 = 0x8000000000000000; bits<64> HexVal0 = 0b1000000000000000000000000000000000000000000000000000000000000000; diff --git a/llvm/test/TableGen/invalid-macro-name-command-line.td b/llvm/test/TableGen/invalid-macro-name-command-line.td index 0d2307997ebe54..7d19e8996639af 100644 --- a/llvm/test/TableGen/invalid-macro-name-command-line.td +++ b/llvm/test/TableGen/invalid-macro-name-command-line.td @@ -3,7 +3,7 @@ // RUN: not llvm-tblgen %s -D_MAC# 2>&1 | FileCheck %s --check-prefix=CHECK-TEST-3 // RUN: not llvm-tblgen %s -D 2>&1 | FileCheck %s --check-prefix=CHECK-TEST-4 -// CHECK-TEST-1: error: Invalid macro name `MACRO=1` specified on command line -// CHECK-TEST-2: error: Invalid macro name `0MAC` specified on command line -// CHECK-TEST-3: error: Invalid macro name `_MAC#` specified on command line +// CHECK-TEST-1: error: invalid macro name `MACRO=1` specified on command line +// CHECK-TEST-2: error: invalid macro name `0MAC` specified on command line +// CHECK-TEST-3: error: invalid macro name `_MAC#` specified on command line // CHECK-TEST-4: for the -D option: requires a value! diff --git a/llvm/test/TableGen/prep-diag1.td b/llvm/test/TableGen/prep-diag1.td index 41b7d477c6942e..27f428f4fe9598 100644 --- a/llvm/test/TableGen/prep-diag1.td +++ b/llvm/test/TableGen/prep-diag1.td @@ -4,22 +4,22 @@ // RUN: not llvm-tblgen -I %p %s 2>&1 | FileCheck --check-prefixes=DIAG3 %s #ifdef DIAG1 -// DIAG1: error: Only comments are supported after #define NAME +// DIAG1: error: only comments are supported after #define NAME #define ENABLED1/* */class C; #endif // DIAG1 #ifdef DIAG4 -// DIAG4: warning: Duplicate definition of macro: ENABLED1 +// DIAG4: warning: duplicate definition of macro: ENABLED1 #define ENABLED1 #define ENABLED1 #endif // DIAG4 #ifdef DIAG2 -// DIAG2: error: Only comments are supported after #ifdef NAME +// DIAG2: error: only comments are supported after #ifdef NAME // Invalid #ifdef below should be detected even if DIAG2 is not defined. -// DIAG3: error: Only comments are supported after #ifdef NAME +// DIAG3: error: only comments are supported after #ifdef NAME #ifdef DIAG2/* */class C; #endif diff --git a/llvm/test/TableGen/prep-diag10.td b/llvm/test/TableGen/prep-diag10.td index eb387a07b066ca..cfcbab094ad73b 100644 --- a/llvm/test/TableGen/prep-diag10.td +++ b/llvm/test/TableGen/prep-diag10.td @@ -1,6 +1,6 @@ // RUN: not llvm-tblgen -I %p %s 2>&1 | FileCheck %s -// CHECK: error: Reached EOF without matching #endif -// CHECK: error: The latest preprocessor control is here +// CHECK: error: reached EOF without matching #endif +// CHECK: error: the latest preprocessor control is here #ifdef DISABLED #else diff --git a/llvm/test/TableGen/prep-diag11.td b/llvm/test/TableGen/prep-diag11.td index 0042bc04f9e101..1fe8a8503076e5 100644 --- a/llvm/test/TableGen/prep-diag11.td +++ b/llvm/test/TableGen/prep-diag11.td @@ -1,7 +1,7 @@ // RUN: not llvm-tblgen -I %p %s 2>&1 | FileCheck %s -// CHECK: error: Reached EOF without matching #endif -// CHECK: error: The latest preprocessor control is here +// CHECK: error: reached EOF without matching #endif +// CHECK: error: the latest preprocessor control is here #ifdef DISABLED #else #define ENABLED diff --git a/llvm/test/TableGen/prep-diag12.td b/llvm/test/TableGen/prep-diag12.td index c26301ee17ac2b..02ffa672b2fa05 100644 --- a/llvm/test/TableGen/prep-diag12.td +++ b/llvm/test/TableGen/prep-diag12.td @@ -1,7 +1,7 @@ // RUN: not llvm-tblgen -I %p %s 2>&1 | FileCheck %s -// CHECK: error: Reached EOF without matching #endif -// CHECK: error: The latest preprocessor control is here +// CHECK: error: reached EOF without matching #endif +// CHECK: error: the latest preprocessor control is here #ifdef DISABLED #else #define ENABLED diff --git a/llvm/test/TableGen/prep-diag13.td b/llvm/test/TableGen/prep-diag13.td index aa3fdab4802d37..733a46a1618131 100644 --- a/llvm/test/TableGen/prep-diag13.td +++ b/llvm/test/TableGen/prep-diag13.td @@ -1,7 +1,7 @@ // RUN: not llvm-tblgen -I %p %s 2>&1 | FileCheck %s -// CHECK: error: Reached EOF without matching #endif -// CHECK: error: The latest preprocessor control is here +// CHECK: error: reached EOF without matching #endif +// CHECK: error: the latest preprocessor control is here #ifdef DISABLED /* #else diff --git a/llvm/test/TableGen/prep-diag14.td b/llvm/test/TableGen/prep-diag14.td index cae9bc3b7f5b6c..a3216ee4f47125 100644 --- a/llvm/test/TableGen/prep-diag14.td +++ b/llvm/test/TableGen/prep-diag14.td @@ -1,6 +1,6 @@ // RUN: not llvm-tblgen -I %p %s 2>&1 | FileCheck %s -// CHECK: error: Reached EOF without matching #endif -// CHECK: error: The latest preprocessor control is here +// CHECK: error: reached EOF without matching #endif +// CHECK: error: the latest preprocessor control is here #ifdef DISABLED // #endif diff --git a/llvm/test/TableGen/prep-diag2.td b/llvm/test/TableGen/prep-diag2.td index 741026b9c8a2d6..e51490600ff64f 100644 --- a/llvm/test/TableGen/prep-diag2.td +++ b/llvm/test/TableGen/prep-diag2.td @@ -2,10 +2,10 @@ // RUN: not llvm-tblgen -I %p %s 2>&1 | FileCheck --check-prefixes=DIAG2 %s #ifdef DIAG1 -// DIAG1: error: Only comments are supported after #else +// DIAG1: error: only comments are supported after #else // Invalid #else below should be detected even if DIAG1 is not defined. -// DIAG2: error: Only comments are supported after #else +// DIAG2: error: only comments are supported after #else #ifdef DIAG2//DIAG2 #else/* */class C; diff --git a/llvm/test/TableGen/prep-diag3.td b/llvm/test/TableGen/prep-diag3.td index fbedfa290b9947..0b4d40307b40b0 100644 --- a/llvm/test/TableGen/prep-diag3.td +++ b/llvm/test/TableGen/prep-diag3.td @@ -2,10 +2,10 @@ // RUN: not llvm-tblgen -I %p %s 2>&1 | FileCheck --check-prefixes=DIAG2 %s #ifdef DIAG1 -// DIAG1: error: Only comments are supported after #endif +// DIAG1: error: only comments are supported after #endif // Invalid #else below should be detected even if DIAG1 is not defined. -// DIAG2: error: Only comments are supported after #endif +// DIAG2: error: only comments are supported after #endif #ifdef DIAG2//DIAG2 #else/*!DIAG2*/ #endif/* !DIAG2 diff --git a/llvm/test/TableGen/prep-diag4.td b/llvm/test/TableGen/prep-diag4.td index 4661ef8667d23f..ead116ebde0de8 100644 --- a/llvm/test/TableGen/prep-diag4.td +++ b/llvm/test/TableGen/prep-diag4.td @@ -1,7 +1,7 @@ // RUN: not llvm-tblgen -I %p %s 2>&1 | FileCheck %s // CHECK: error: double #else -// CHECK: error: Previous #else is here +// CHECK: error: previous #else is here #ifdef DIAG1 #else #else diff --git a/llvm/test/TableGen/prep-diag6.td b/llvm/test/TableGen/prep-diag6.td index f4202d115da59a..bf1cd3d3490b5e 100644 --- a/llvm/test/TableGen/prep-diag6.td +++ b/llvm/test/TableGen/prep-diag6.td @@ -1,6 +1,6 @@ // RUN: not llvm-tblgen -I %p %s 2>&1 | FileCheck %s -// CHECK: error: Expected macro name after #ifdef +// CHECK: error: expected macro name after #ifdef #ifdef #else #else diff --git a/llvm/test/TableGen/prep-diag8.td b/llvm/test/TableGen/prep-diag8.td index 7a7bde62c79c4e..82797d6cf4a62d 100644 --- a/llvm/test/TableGen/prep-diag8.td +++ b/llvm/test/TableGen/prep-diag8.td @@ -1,5 +1,5 @@ // RUN: not llvm-tblgen -I %p %s 2>&1 | FileCheck %s -// CHECK: error: Expected macro name after #define +// CHECK: error: expected macro name after #define #define #endif diff --git a/llvm/test/TableGen/prep-diag9.td b/llvm/test/TableGen/prep-diag9.td index 4ecff575cdc7bb..6ad208104301bc 100644 --- a/llvm/test/TableGen/prep-diag9.td +++ b/llvm/test/TableGen/prep-diag9.td @@ -1,5 +1,5 @@ // RUN: not llvm-tblgen -I %p %s 2>&1 | FileCheck %s -// CHECK: error: Reached EOF without matching #endif -// CHECK: error: The latest preprocessor control is here +// CHECK: error: reached EOF without matching #endif +// CHECK: error: the latest preprocessor control is here #ifdef DISABLED diff --git a/llvm/test/TableGen/prep-ifndef-diag-1.td b/llvm/test/TableGen/prep-ifndef-diag-1.td index 941f2d377a98a7..4a0d0754ed7906 100644 --- a/llvm/test/TableGen/prep-ifndef-diag-1.td +++ b/llvm/test/TableGen/prep-ifndef-diag-1.td @@ -1,4 +1,4 @@ // RUN: not llvm-tblgen %s 2>&1 | FileCheck %s -// CHECK: error: Expected macro name after #ifndef +// CHECK: error: expected macro name after #ifndef #ifndef 1 diff --git a/llvm/test/TableGen/prep-ifndef-diag-2.td b/llvm/test/TableGen/prep-ifndef-diag-2.td index 7b5f9dfd24b786..c89cbab08e5c5c 100644 --- a/llvm/test/TableGen/prep-ifndef-diag-2.td +++ b/llvm/test/TableGen/prep-ifndef-diag-2.td @@ -1,4 +1,4 @@ // RUN: not llvm-tblgen %s 2>&1 | FileCheck %s -// CHECK: error: Only comments are supported after #ifndef NAME +// CHECK: error: only comments are supported after #ifndef NAME #ifndef MACRO 42 diff --git a/llvm/test/TableGen/unterminated-c-comment.td b/llvm/test/TableGen/unterminated-c-comment.td index 0f4cd9d633c66d..b5b995342be744 100644 --- a/llvm/test/TableGen/unterminated-c-comment.td +++ b/llvm/test/TableGen/unterminated-c-comment.td @@ -1,5 +1,5 @@ // RUN: not llvm-tblgen -I %p %s 2>&1 | FileCheck %s -// CHECK: error: Unterminated comment! +// CHECK: error: unterminated comment include "unterminated-c-comment-include.inc" */ diff --git a/llvm/test/TableGen/unterminated-code-block.td b/llvm/test/TableGen/unterminated-code-block.td index d6b6f50827a672..5bd4cd7e17d827 100644 --- a/llvm/test/TableGen/unterminated-code-block.td +++ b/llvm/test/TableGen/unterminated-code-block.td @@ -1,5 +1,5 @@ // RUN: not llvm-tblgen -I %p %s 2>&1 | FileCheck %s -// CHECK: error: Unterminated code block +// CHECK: error: unterminated code block include "unterminated-code-block-include.inc" }]>; diff --git a/llvm/test/TableGen/x86-fold-tables.inc b/llvm/test/TableGen/x86-fold-tables.inc index 43c206fa0af698..21f3c8593a710b 100644 --- a/llvm/test/TableGen/x86-fold-tables.inc +++ b/llvm/test/TableGen/x86-fold-tables.inc @@ -1959,8 +1959,11 @@ static const X86FoldTableEntry Table1[] = { {X86::VUCOMISSZrr_Int, X86::VUCOMISSZrm_Int, TB_NO_REVERSE}, {X86::VUCOMISSrr, X86::VUCOMISSrm, 0}, {X86::VUCOMISSrr_Int, X86::VUCOMISSrm_Int, TB_NO_REVERSE}, + {X86::VUCOMXSDZrr, X86::VUCOMXSDZrm, 0}, {X86::VUCOMXSDZrr_Int, X86::VUCOMXSDZrm_Int, TB_NO_REVERSE}, + {X86::VUCOMXSHZrr, X86::VUCOMXSHZrm, 0}, {X86::VUCOMXSHZrr_Int, X86::VUCOMXSHZrm_Int, TB_NO_REVERSE}, + {X86::VUCOMXSSZrr, X86::VUCOMXSSZrm, 0}, {X86::VUCOMXSSZrr_Int, X86::VUCOMXSSZrm_Int, TB_NO_REVERSE}, {X86::XOR16ri8_ND, X86::XOR16mi8_ND, 0}, {X86::XOR16ri8_NF_ND, X86::XOR16mi8_NF_ND, 0}, diff --git a/llvm/test/Transforms/Attributor/nofpclass-phiselect.ll b/llvm/test/Transforms/Attributor/nofpclass-phiselect.ll new file mode 100644 index 00000000000000..6635280bc43603 --- /dev/null +++ b/llvm/test/Transforms/Attributor/nofpclass-phiselect.ll @@ -0,0 +1,176 @@ +; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 2 +; RUN: opt -aa-pipeline=basic-aa -passes=attributor -attributor-manifest-internal -S < %s | FileCheck %s + +define float @phi_select(i1 %c, float nofpclass(inf) %base, float nofpclass(inf) %arg) { +; CHECK-LABEL: define float @phi_select +; CHECK-SAME: (i1 [[C:%.*]], float nofpclass(inf) [[BASE:%.*]], float nofpclass(inf) [[ARG:%.*]]) #[[ATTR0:[0-9]+]] { +; CHECK-NEXT: entry: +; CHECK-NEXT: br label [[LOOP:%.*]] +; CHECK: loop: +; CHECK-NEXT: [[PHI:%.*]] = phi float [ [[BASE]], [[ENTRY:%.*]] ], [ [[SELECT:%.*]], [[LOOP]] ] +; CHECK-NEXT: [[SELECT]] = select i1 [[C]], float [[PHI]], float [[ARG]] +; CHECK-NEXT: br i1 [[C]], label [[LOOP]], label [[EXIT:%.*]] +; CHECK: exit: +; CHECK-NEXT: ret float [[SELECT]] +; +entry: + br label %loop + +loop: + %phi = phi float [ %base, %entry ], [ %select, %loop ] + %select = select i1 %c, float %phi, float %arg + br i1 %c, label %loop, label %exit + +exit: + ret float %select +} + +define float @phi_select_onlybase(i1 %c, float nofpclass(inf) %base, float %arg) { +; CHECK-LABEL: define float @phi_select_onlybase +; CHECK-SAME: (i1 [[C:%.*]], float nofpclass(inf) [[BASE:%.*]], float [[ARG:%.*]]) #[[ATTR0]] { +; CHECK-NEXT: entry: +; CHECK-NEXT: br label [[LOOP:%.*]] +; CHECK: loop: +; CHECK-NEXT: [[PHI:%.*]] = phi float [ [[BASE]], [[ENTRY:%.*]] ], [ [[SELECT:%.*]], [[LOOP]] ] +; CHECK-NEXT: [[SELECT]] = select i1 [[C]], float [[PHI]], float [[ARG]] +; CHECK-NEXT: br i1 [[C]], label [[LOOP]], label [[EXIT:%.*]] +; CHECK: exit: +; CHECK-NEXT: ret float [[SELECT]] +; +entry: + br label %loop + +loop: + %phi = phi float [ %base, %entry ], [ %select, %loop ] + %select = select i1 %c, float %phi, float %arg + br i1 %c, label %loop, label %exit + +exit: + ret float %select +} + +define float @phi_select_onlyarg(i1 %c, float %base, float nofpclass(inf) %arg) { +; CHECK-LABEL: define float @phi_select_onlyarg +; CHECK-SAME: (i1 [[C:%.*]], float [[BASE:%.*]], float nofpclass(inf) [[ARG:%.*]]) #[[ATTR0]] { +; CHECK-NEXT: entry: +; CHECK-NEXT: br label [[LOOP:%.*]] +; CHECK: loop: +; CHECK-NEXT: [[PHI:%.*]] = phi float [ [[BASE]], [[ENTRY:%.*]] ], [ [[SELECT:%.*]], [[LOOP]] ] +; CHECK-NEXT: [[SELECT]] = select i1 [[C]], float [[PHI]], float [[ARG]] +; CHECK-NEXT: br i1 [[C]], label [[LOOP]], label [[EXIT:%.*]] +; CHECK: exit: +; CHECK-NEXT: ret float [[SELECT]] +; +entry: + br label %loop + +loop: + %phi = phi float [ %base, %entry ], [ %select, %loop ] + %select = select i1 %c, float %phi, float %arg + br i1 %c, label %loop, label %exit + +exit: + ret float %select +} + +define float @phi_phi(i1 %c, float nofpclass(inf) %base, float nofpclass(inf) %arg) { +; CHECK-LABEL: define float @phi_phi +; CHECK-SAME: (i1 [[C:%.*]], float nofpclass(inf) [[BASE:%.*]], float nofpclass(inf) [[ARG:%.*]]) #[[ATTR0]] { +; CHECK-NEXT: entry: +; CHECK-NEXT: br label [[LOOP:%.*]] +; CHECK: loop: +; CHECK-NEXT: [[PHI:%.*]] = phi float [ [[BASE]], [[ENTRY:%.*]] ], [ [[PHI2:%.*]], [[EXIT1:%.*]] ] +; CHECK-NEXT: br label [[INNER:%.*]] +; CHECK: inner: +; CHECK-NEXT: [[PHI2]] = phi float [ [[PHI]], [[LOOP]] ], [ [[ARG]], [[INNER]] ] +; CHECK-NEXT: br i1 [[C]], label [[INNER]], label [[EXIT1]] +; CHECK: exit1: +; CHECK-NEXT: br i1 [[C]], label [[LOOP]], label [[EXIT:%.*]] +; CHECK: exit: +; CHECK-NEXT: ret float [[PHI2]] +; +entry: + br label %loop + +loop: + %phi = phi float [ %base, %entry ], [ %phi2, %exit1 ] + br label %inner + +inner: + %phi2 = phi float [ %phi, %loop ], [ %arg, %inner ] + br i1 %c, label %inner, label %exit1 + +exit1: + br i1 %c, label %loop, label %exit + +exit: + ret float %phi2 +} + +define float @phi_phi_onlybase(i1 %c, float nofpclass(inf) %base, float %arg) { +; CHECK-LABEL: define float @phi_phi_onlybase +; CHECK-SAME: (i1 [[C:%.*]], float nofpclass(inf) [[BASE:%.*]], float [[ARG:%.*]]) #[[ATTR0]] { +; CHECK-NEXT: entry: +; CHECK-NEXT: br label [[LOOP:%.*]] +; CHECK: loop: +; CHECK-NEXT: [[PHI:%.*]] = phi float [ [[BASE]], [[ENTRY:%.*]] ], [ [[PHI2:%.*]], [[EXIT1:%.*]] ] +; CHECK-NEXT: br label [[INNER:%.*]] +; CHECK: inner: +; CHECK-NEXT: [[PHI2]] = phi float [ [[PHI]], [[LOOP]] ], [ [[ARG]], [[INNER]] ] +; CHECK-NEXT: br i1 [[C]], label [[INNER]], label [[EXIT1]] +; CHECK: exit1: +; CHECK-NEXT: br i1 [[C]], label [[LOOP]], label [[EXIT:%.*]] +; CHECK: exit: +; CHECK-NEXT: ret float [[PHI2]] +; +entry: + br label %loop + +loop: + %phi = phi float [ %base, %entry ], [ %phi2, %exit1 ] + br label %inner + +inner: + %phi2 = phi float [ %phi, %loop ], [ %arg, %inner ] + br i1 %c, label %inner, label %exit1 + +exit1: + br i1 %c, label %loop, label %exit + +exit: + ret float %phi2 +} + +define float @phi_phi_onlyarg(i1 %c, float %base, float nofpclass(inf) %arg) { +; CHECK-LABEL: define float @phi_phi_onlyarg +; CHECK-SAME: (i1 [[C:%.*]], float [[BASE:%.*]], float nofpclass(inf) [[ARG:%.*]]) #[[ATTR0]] { +; CHECK-NEXT: entry: +; CHECK-NEXT: br label [[LOOP:%.*]] +; CHECK: loop: +; CHECK-NEXT: [[PHI:%.*]] = phi float [ [[BASE]], [[ENTRY:%.*]] ], [ [[PHI2:%.*]], [[EXIT1:%.*]] ] +; CHECK-NEXT: br label [[INNER:%.*]] +; CHECK: inner: +; CHECK-NEXT: [[PHI2]] = phi float [ [[PHI]], [[LOOP]] ], [ [[ARG]], [[INNER]] ] +; CHECK-NEXT: br i1 [[C]], label [[INNER]], label [[EXIT1]] +; CHECK: exit1: +; CHECK-NEXT: br i1 [[C]], label [[LOOP]], label [[EXIT:%.*]] +; CHECK: exit: +; CHECK-NEXT: ret float [[PHI2]] +; +entry: + br label %loop + +loop: + %phi = phi float [ %base, %entry ], [ %phi2, %exit1 ] + br label %inner + +inner: + %phi2 = phi float [ %phi, %loop ], [ %arg, %inner ] + br i1 %c, label %inner, label %exit1 + +exit1: + br i1 %c, label %loop, label %exit + +exit: + ret float %phi2 +} diff --git a/llvm/test/Transforms/FunctionSpecialization/maxgrowth.ll b/llvm/test/Transforms/FunctionSpecialization/maxgrowth.ll new file mode 100644 index 00000000000000..82d1f7ae4a6e16 --- /dev/null +++ b/llvm/test/Transforms/FunctionSpecialization/maxgrowth.ll @@ -0,0 +1,44 @@ +; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --include-generated-funcs --version 5 +; RUN: opt -passes="ipsccp" -funcspec-min-function-size=1 \ +; RUN: -funcspec-for-literal-constant=true \ +; RUN: -funcspec-min-codesize-savings=50 \ +; RUN: -funcspec-min-latency-savings=50 \ +; RUN: -funcspec-max-codesize-growth=1 \ +; RUN: -S < %s | FileCheck %s + +; Verify that we are able to specialize a function successfully after analysis +; of other specializations that are found to not be profitable. +define void @test_specialize_after_failed_analysis(i32 %n) { +entry: + %notspec0 = call i32 @add(i32 0, i32 %n) + %notspec1 = call i32 @add(i32 1, i32 %n) + %spec = call i32 @add(i32 1, i32 1) + ret void +} + +define i32 @add(i32 %x, i32 %y) { +entry: + %res = add i32 %x, %y + ret i32 %res +} +; CHECK-LABEL: define void @test_specialize_after_failed_analysis( +; CHECK-SAME: i32 [[N:%.*]]) { +; CHECK-NEXT: [[ENTRY:.*:]] +; CHECK-NEXT: [[NOTSPEC0:%.*]] = call i32 @add(i32 0, i32 [[N]]) +; CHECK-NEXT: [[NOTSPEC1:%.*]] = call i32 @add(i32 1, i32 [[N]]) +; CHECK-NEXT: [[SPEC:%.*]] = call i32 @add.specialized.1(i32 1, i32 1) +; CHECK-NEXT: ret void +; +; +; CHECK-LABEL: define i32 @add( +; CHECK-SAME: i32 [[X:%.*]], i32 [[Y:%.*]]) { +; CHECK-NEXT: [[ENTRY:.*:]] +; CHECK-NEXT: [[RES:%.*]] = add i32 [[X]], [[Y]] +; CHECK-NEXT: ret i32 [[RES]] +; +; +; CHECK-LABEL: define internal i32 @add.specialized.1( +; CHECK-SAME: i32 [[X:%.*]], i32 [[Y:%.*]]) { +; CHECK-NEXT: [[ENTRY:.*:]] +; CHECK-NEXT: ret i32 poison +; diff --git a/llvm/test/Transforms/Inline/convergence-inline.ll b/llvm/test/Transforms/Inline/convergence-inline.ll index 8c67e6a59b7db1..4996a2376be638 100644 --- a/llvm/test/Transforms/Inline/convergence-inline.ll +++ b/llvm/test/Transforms/Inline/convergence-inline.ll @@ -185,6 +185,30 @@ define void @test_two_calls() convergent { ret void } +define i32 @token_not_first(i32 %x) convergent alwaysinline { +; CHECK-LABEL: @token_not_first( +; CHECK-NEXT: {{%.*}} = alloca ptr, align 8 +; CHECK-NEXT: [[TOKEN:%.*]] = call token @llvm.experimental.convergence.entry() +; CHECK-NEXT: [[Y:%.*]] = call i32 @g(i32 [[X:%.*]]) [ "convergencectrl"(token [[TOKEN]]) ] +; CHECK-NEXT: ret i32 [[Y]] +; + %p = alloca ptr, align 8 + %token = call token @llvm.experimental.convergence.entry() + %y = call i32 @g(i32 %x) [ "convergencectrl"(token %token) ] + ret i32 %y +} + +define void @test_token_not_first() convergent { +; CHECK-LABEL: @test_token_not_first( +; CHECK-NEXT: [[TOKEN:%.*]] = call token @llvm.experimental.convergence.entry() +; CHECK-NEXT: {{%.*}} = call i32 @g(i32 23) [ "convergencectrl"(token [[TOKEN]]) ] +; CHECK-NEXT: ret void +; + %token = call token @llvm.experimental.convergence.entry() + %x = call i32 @token_not_first(i32 23) [ "convergencectrl"(token %token) ] + ret void +} + declare void @f(i32) convergent declare i32 @g(i32) convergent diff --git a/llvm/test/Analysis/CostModel/AArch64/arith-fp-frem.ll b/llvm/test/Transforms/LoopVectorize/AArch64/arith-fp-frem-costs.ll similarity index 100% rename from llvm/test/Analysis/CostModel/AArch64/arith-fp-frem.ll rename to llvm/test/Transforms/LoopVectorize/AArch64/arith-fp-frem-costs.ll diff --git a/llvm/test/Analysis/CostModel/X86/gather-i16-with-i8-index.ll b/llvm/test/Transforms/LoopVectorize/X86/CostModel/gather-i16-with-i8-index.ll similarity index 100% rename from llvm/test/Analysis/CostModel/X86/gather-i16-with-i8-index.ll rename to llvm/test/Transforms/LoopVectorize/X86/CostModel/gather-i16-with-i8-index.ll diff --git a/llvm/test/Analysis/CostModel/X86/gather-i32-with-i8-index.ll b/llvm/test/Transforms/LoopVectorize/X86/CostModel/gather-i32-with-i8-index.ll similarity index 100% rename from llvm/test/Analysis/CostModel/X86/gather-i32-with-i8-index.ll rename to llvm/test/Transforms/LoopVectorize/X86/CostModel/gather-i32-with-i8-index.ll diff --git a/llvm/test/Analysis/CostModel/X86/gather-i64-with-i8-index.ll b/llvm/test/Transforms/LoopVectorize/X86/CostModel/gather-i64-with-i8-index.ll similarity index 100% rename from llvm/test/Analysis/CostModel/X86/gather-i64-with-i8-index.ll rename to llvm/test/Transforms/LoopVectorize/X86/CostModel/gather-i64-with-i8-index.ll diff --git a/llvm/test/Analysis/CostModel/X86/gather-i8-with-i8-index.ll b/llvm/test/Transforms/LoopVectorize/X86/CostModel/gather-i8-with-i8-index.ll similarity index 100% rename from llvm/test/Analysis/CostModel/X86/gather-i8-with-i8-index.ll rename to llvm/test/Transforms/LoopVectorize/X86/CostModel/gather-i8-with-i8-index.ll diff --git a/llvm/test/Analysis/CostModel/X86/handle-iptr-with-data-layout-to-not-assert.ll b/llvm/test/Transforms/LoopVectorize/X86/CostModel/handle-iptr-with-data-layout-to-not-assert.ll similarity index 100% rename from llvm/test/Analysis/CostModel/X86/handle-iptr-with-data-layout-to-not-assert.ll rename to llvm/test/Transforms/LoopVectorize/X86/CostModel/handle-iptr-with-data-layout-to-not-assert.ll diff --git a/llvm/test/Analysis/CostModel/X86/interleaved-load-f32-stride-2.ll b/llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-load-f32-stride-2.ll similarity index 100% rename from llvm/test/Analysis/CostModel/X86/interleaved-load-f32-stride-2.ll rename to llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-load-f32-stride-2.ll diff --git a/llvm/test/Analysis/CostModel/X86/interleaved-load-f32-stride-3.ll b/llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-load-f32-stride-3.ll similarity index 100% rename from llvm/test/Analysis/CostModel/X86/interleaved-load-f32-stride-3.ll rename to llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-load-f32-stride-3.ll diff --git a/llvm/test/Analysis/CostModel/X86/interleaved-load-f32-stride-4.ll b/llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-load-f32-stride-4.ll similarity index 100% rename from llvm/test/Analysis/CostModel/X86/interleaved-load-f32-stride-4.ll rename to llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-load-f32-stride-4.ll diff --git a/llvm/test/Analysis/CostModel/X86/interleaved-load-f32-stride-5.ll b/llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-load-f32-stride-5.ll similarity index 100% rename from llvm/test/Analysis/CostModel/X86/interleaved-load-f32-stride-5.ll rename to llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-load-f32-stride-5.ll diff --git a/llvm/test/Analysis/CostModel/X86/interleaved-load-f32-stride-6.ll b/llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-load-f32-stride-6.ll similarity index 100% rename from llvm/test/Analysis/CostModel/X86/interleaved-load-f32-stride-6.ll rename to llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-load-f32-stride-6.ll diff --git a/llvm/test/Analysis/CostModel/X86/interleaved-load-f32-stride-7.ll b/llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-load-f32-stride-7.ll similarity index 100% rename from llvm/test/Analysis/CostModel/X86/interleaved-load-f32-stride-7.ll rename to llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-load-f32-stride-7.ll diff --git a/llvm/test/Analysis/CostModel/X86/interleaved-load-f32-stride-8.ll b/llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-load-f32-stride-8.ll similarity index 100% rename from llvm/test/Analysis/CostModel/X86/interleaved-load-f32-stride-8.ll rename to llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-load-f32-stride-8.ll diff --git a/llvm/test/Analysis/CostModel/X86/interleaved-load-f64-stride-2.ll b/llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-load-f64-stride-2.ll similarity index 100% rename from llvm/test/Analysis/CostModel/X86/interleaved-load-f64-stride-2.ll rename to llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-load-f64-stride-2.ll diff --git a/llvm/test/Analysis/CostModel/X86/interleaved-load-f64-stride-3.ll b/llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-load-f64-stride-3.ll similarity index 100% rename from llvm/test/Analysis/CostModel/X86/interleaved-load-f64-stride-3.ll rename to llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-load-f64-stride-3.ll diff --git a/llvm/test/Analysis/CostModel/X86/interleaved-load-f64-stride-4.ll b/llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-load-f64-stride-4.ll similarity index 100% rename from llvm/test/Analysis/CostModel/X86/interleaved-load-f64-stride-4.ll rename to llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-load-f64-stride-4.ll diff --git a/llvm/test/Analysis/CostModel/X86/interleaved-load-f64-stride-5.ll b/llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-load-f64-stride-5.ll similarity index 100% rename from llvm/test/Analysis/CostModel/X86/interleaved-load-f64-stride-5.ll rename to llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-load-f64-stride-5.ll diff --git a/llvm/test/Analysis/CostModel/X86/interleaved-load-f64-stride-6.ll b/llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-load-f64-stride-6.ll similarity index 100% rename from llvm/test/Analysis/CostModel/X86/interleaved-load-f64-stride-6.ll rename to llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-load-f64-stride-6.ll diff --git a/llvm/test/Analysis/CostModel/X86/interleaved-load-f64-stride-7.ll b/llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-load-f64-stride-7.ll similarity index 100% rename from llvm/test/Analysis/CostModel/X86/interleaved-load-f64-stride-7.ll rename to llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-load-f64-stride-7.ll diff --git a/llvm/test/Analysis/CostModel/X86/interleaved-load-f64-stride-8.ll b/llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-load-f64-stride-8.ll similarity index 100% rename from llvm/test/Analysis/CostModel/X86/interleaved-load-f64-stride-8.ll rename to llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-load-f64-stride-8.ll diff --git a/llvm/test/Analysis/CostModel/X86/interleaved-load-half.ll b/llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-load-half.ll similarity index 100% rename from llvm/test/Analysis/CostModel/X86/interleaved-load-half.ll rename to llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-load-half.ll diff --git a/llvm/test/Analysis/CostModel/X86/interleaved-load-i16-stride-2.ll b/llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-load-i16-stride-2.ll similarity index 100% rename from llvm/test/Analysis/CostModel/X86/interleaved-load-i16-stride-2.ll rename to llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-load-i16-stride-2.ll diff --git a/llvm/test/Analysis/CostModel/X86/interleaved-load-i16-stride-3.ll b/llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-load-i16-stride-3.ll similarity index 100% rename from llvm/test/Analysis/CostModel/X86/interleaved-load-i16-stride-3.ll rename to llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-load-i16-stride-3.ll diff --git a/llvm/test/Analysis/CostModel/X86/interleaved-load-i16-stride-4.ll b/llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-load-i16-stride-4.ll similarity index 100% rename from llvm/test/Analysis/CostModel/X86/interleaved-load-i16-stride-4.ll rename to llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-load-i16-stride-4.ll diff --git a/llvm/test/Analysis/CostModel/X86/interleaved-load-i16-stride-5.ll b/llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-load-i16-stride-5.ll similarity index 100% rename from llvm/test/Analysis/CostModel/X86/interleaved-load-i16-stride-5.ll rename to llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-load-i16-stride-5.ll diff --git a/llvm/test/Analysis/CostModel/X86/interleaved-load-i16-stride-6.ll b/llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-load-i16-stride-6.ll similarity index 100% rename from llvm/test/Analysis/CostModel/X86/interleaved-load-i16-stride-6.ll rename to llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-load-i16-stride-6.ll diff --git a/llvm/test/Analysis/CostModel/X86/interleaved-load-i16-stride-7.ll b/llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-load-i16-stride-7.ll similarity index 100% rename from llvm/test/Analysis/CostModel/X86/interleaved-load-i16-stride-7.ll rename to llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-load-i16-stride-7.ll diff --git a/llvm/test/Analysis/CostModel/X86/interleaved-load-i16-stride-8.ll b/llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-load-i16-stride-8.ll similarity index 100% rename from llvm/test/Analysis/CostModel/X86/interleaved-load-i16-stride-8.ll rename to llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-load-i16-stride-8.ll diff --git a/llvm/test/Analysis/CostModel/X86/interleaved-load-i32-stride-2-indices-0u.ll b/llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-load-i32-stride-2-indices-0u.ll similarity index 100% rename from llvm/test/Analysis/CostModel/X86/interleaved-load-i32-stride-2-indices-0u.ll rename to llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-load-i32-stride-2-indices-0u.ll diff --git a/llvm/test/Analysis/CostModel/X86/interleaved-load-i32-stride-2.ll b/llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-load-i32-stride-2.ll similarity index 100% rename from llvm/test/Analysis/CostModel/X86/interleaved-load-i32-stride-2.ll rename to llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-load-i32-stride-2.ll diff --git a/llvm/test/Analysis/CostModel/X86/interleaved-load-i32-stride-3-indices-01u.ll b/llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-load-i32-stride-3-indices-01u.ll similarity index 100% rename from llvm/test/Analysis/CostModel/X86/interleaved-load-i32-stride-3-indices-01u.ll rename to llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-load-i32-stride-3-indices-01u.ll diff --git a/llvm/test/Analysis/CostModel/X86/interleaved-load-i32-stride-3-indices-0uu.ll b/llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-load-i32-stride-3-indices-0uu.ll similarity index 100% rename from llvm/test/Analysis/CostModel/X86/interleaved-load-i32-stride-3-indices-0uu.ll rename to llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-load-i32-stride-3-indices-0uu.ll diff --git a/llvm/test/Analysis/CostModel/X86/interleaved-load-i32-stride-3.ll b/llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-load-i32-stride-3.ll similarity index 100% rename from llvm/test/Analysis/CostModel/X86/interleaved-load-i32-stride-3.ll rename to llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-load-i32-stride-3.ll diff --git a/llvm/test/Analysis/CostModel/X86/interleaved-load-i32-stride-4-indices-012u.ll b/llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-load-i32-stride-4-indices-012u.ll similarity index 100% rename from llvm/test/Analysis/CostModel/X86/interleaved-load-i32-stride-4-indices-012u.ll rename to llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-load-i32-stride-4-indices-012u.ll diff --git a/llvm/test/Analysis/CostModel/X86/interleaved-load-i32-stride-4-indices-01uu.ll b/llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-load-i32-stride-4-indices-01uu.ll similarity index 100% rename from llvm/test/Analysis/CostModel/X86/interleaved-load-i32-stride-4-indices-01uu.ll rename to llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-load-i32-stride-4-indices-01uu.ll diff --git a/llvm/test/Analysis/CostModel/X86/interleaved-load-i32-stride-4-indices-0uuu.ll b/llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-load-i32-stride-4-indices-0uuu.ll similarity index 100% rename from llvm/test/Analysis/CostModel/X86/interleaved-load-i32-stride-4-indices-0uuu.ll rename to llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-load-i32-stride-4-indices-0uuu.ll diff --git a/llvm/test/Analysis/CostModel/X86/interleaved-load-i32-stride-4.ll b/llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-load-i32-stride-4.ll similarity index 100% rename from llvm/test/Analysis/CostModel/X86/interleaved-load-i32-stride-4.ll rename to llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-load-i32-stride-4.ll diff --git a/llvm/test/Analysis/CostModel/X86/interleaved-load-i32-stride-5.ll b/llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-load-i32-stride-5.ll similarity index 100% rename from llvm/test/Analysis/CostModel/X86/interleaved-load-i32-stride-5.ll rename to llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-load-i32-stride-5.ll diff --git a/llvm/test/Analysis/CostModel/X86/interleaved-load-i32-stride-6.ll b/llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-load-i32-stride-6.ll similarity index 100% rename from llvm/test/Analysis/CostModel/X86/interleaved-load-i32-stride-6.ll rename to llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-load-i32-stride-6.ll diff --git a/llvm/test/Analysis/CostModel/X86/interleaved-load-i32-stride-7.ll b/llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-load-i32-stride-7.ll similarity index 100% rename from llvm/test/Analysis/CostModel/X86/interleaved-load-i32-stride-7.ll rename to llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-load-i32-stride-7.ll diff --git a/llvm/test/Analysis/CostModel/X86/interleaved-load-i32-stride-8.ll b/llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-load-i32-stride-8.ll similarity index 100% rename from llvm/test/Analysis/CostModel/X86/interleaved-load-i32-stride-8.ll rename to llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-load-i32-stride-8.ll diff --git a/llvm/test/Analysis/CostModel/X86/interleaved-load-i64-stride-2.ll b/llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-load-i64-stride-2.ll similarity index 100% rename from llvm/test/Analysis/CostModel/X86/interleaved-load-i64-stride-2.ll rename to llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-load-i64-stride-2.ll diff --git a/llvm/test/Analysis/CostModel/X86/interleaved-load-i64-stride-3.ll b/llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-load-i64-stride-3.ll similarity index 100% rename from llvm/test/Analysis/CostModel/X86/interleaved-load-i64-stride-3.ll rename to llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-load-i64-stride-3.ll diff --git a/llvm/test/Analysis/CostModel/X86/interleaved-load-i64-stride-4.ll b/llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-load-i64-stride-4.ll similarity index 100% rename from llvm/test/Analysis/CostModel/X86/interleaved-load-i64-stride-4.ll rename to llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-load-i64-stride-4.ll diff --git a/llvm/test/Analysis/CostModel/X86/interleaved-load-i64-stride-5.ll b/llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-load-i64-stride-5.ll similarity index 100% rename from llvm/test/Analysis/CostModel/X86/interleaved-load-i64-stride-5.ll rename to llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-load-i64-stride-5.ll diff --git a/llvm/test/Analysis/CostModel/X86/interleaved-load-i64-stride-6.ll b/llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-load-i64-stride-6.ll similarity index 100% rename from llvm/test/Analysis/CostModel/X86/interleaved-load-i64-stride-6.ll rename to llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-load-i64-stride-6.ll diff --git a/llvm/test/Analysis/CostModel/X86/interleaved-load-i64-stride-7.ll b/llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-load-i64-stride-7.ll similarity index 100% rename from llvm/test/Analysis/CostModel/X86/interleaved-load-i64-stride-7.ll rename to llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-load-i64-stride-7.ll diff --git a/llvm/test/Analysis/CostModel/X86/interleaved-load-i64-stride-8.ll b/llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-load-i64-stride-8.ll similarity index 100% rename from llvm/test/Analysis/CostModel/X86/interleaved-load-i64-stride-8.ll rename to llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-load-i64-stride-8.ll diff --git a/llvm/test/Analysis/CostModel/X86/interleaved-load-i8-stride-2.ll b/llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-load-i8-stride-2.ll similarity index 100% rename from llvm/test/Analysis/CostModel/X86/interleaved-load-i8-stride-2.ll rename to llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-load-i8-stride-2.ll diff --git a/llvm/test/Analysis/CostModel/X86/interleaved-load-i8-stride-3.ll b/llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-load-i8-stride-3.ll similarity index 100% rename from llvm/test/Analysis/CostModel/X86/interleaved-load-i8-stride-3.ll rename to llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-load-i8-stride-3.ll diff --git a/llvm/test/Analysis/CostModel/X86/interleaved-load-i8-stride-4.ll b/llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-load-i8-stride-4.ll similarity index 100% rename from llvm/test/Analysis/CostModel/X86/interleaved-load-i8-stride-4.ll rename to llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-load-i8-stride-4.ll diff --git a/llvm/test/Analysis/CostModel/X86/interleaved-load-i8-stride-5.ll b/llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-load-i8-stride-5.ll similarity index 100% rename from llvm/test/Analysis/CostModel/X86/interleaved-load-i8-stride-5.ll rename to llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-load-i8-stride-5.ll diff --git a/llvm/test/Analysis/CostModel/X86/interleaved-load-i8-stride-6.ll b/llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-load-i8-stride-6.ll similarity index 100% rename from llvm/test/Analysis/CostModel/X86/interleaved-load-i8-stride-6.ll rename to llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-load-i8-stride-6.ll diff --git a/llvm/test/Analysis/CostModel/X86/interleaved-load-i8-stride-7.ll b/llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-load-i8-stride-7.ll similarity index 100% rename from llvm/test/Analysis/CostModel/X86/interleaved-load-i8-stride-7.ll rename to llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-load-i8-stride-7.ll diff --git a/llvm/test/Analysis/CostModel/X86/interleaved-load-i8-stride-8.ll b/llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-load-i8-stride-8.ll similarity index 100% rename from llvm/test/Analysis/CostModel/X86/interleaved-load-i8-stride-8.ll rename to llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-load-i8-stride-8.ll diff --git a/llvm/test/Analysis/CostModel/X86/interleaved-store-f32-stride-2.ll b/llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-store-f32-stride-2.ll similarity index 100% rename from llvm/test/Analysis/CostModel/X86/interleaved-store-f32-stride-2.ll rename to llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-store-f32-stride-2.ll diff --git a/llvm/test/Analysis/CostModel/X86/interleaved-store-f32-stride-3.ll b/llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-store-f32-stride-3.ll similarity index 100% rename from llvm/test/Analysis/CostModel/X86/interleaved-store-f32-stride-3.ll rename to llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-store-f32-stride-3.ll diff --git a/llvm/test/Analysis/CostModel/X86/interleaved-store-f32-stride-4.ll b/llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-store-f32-stride-4.ll similarity index 100% rename from llvm/test/Analysis/CostModel/X86/interleaved-store-f32-stride-4.ll rename to llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-store-f32-stride-4.ll diff --git a/llvm/test/Analysis/CostModel/X86/interleaved-store-f32-stride-5.ll b/llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-store-f32-stride-5.ll similarity index 100% rename from llvm/test/Analysis/CostModel/X86/interleaved-store-f32-stride-5.ll rename to llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-store-f32-stride-5.ll diff --git a/llvm/test/Analysis/CostModel/X86/interleaved-store-f32-stride-6.ll b/llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-store-f32-stride-6.ll similarity index 100% rename from llvm/test/Analysis/CostModel/X86/interleaved-store-f32-stride-6.ll rename to llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-store-f32-stride-6.ll diff --git a/llvm/test/Analysis/CostModel/X86/interleaved-store-f32-stride-7.ll b/llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-store-f32-stride-7.ll similarity index 100% rename from llvm/test/Analysis/CostModel/X86/interleaved-store-f32-stride-7.ll rename to llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-store-f32-stride-7.ll diff --git a/llvm/test/Analysis/CostModel/X86/interleaved-store-f32-stride-8.ll b/llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-store-f32-stride-8.ll similarity index 100% rename from llvm/test/Analysis/CostModel/X86/interleaved-store-f32-stride-8.ll rename to llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-store-f32-stride-8.ll diff --git a/llvm/test/Analysis/CostModel/X86/interleaved-store-f64-stride-2.ll b/llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-store-f64-stride-2.ll similarity index 100% rename from llvm/test/Analysis/CostModel/X86/interleaved-store-f64-stride-2.ll rename to llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-store-f64-stride-2.ll diff --git a/llvm/test/Analysis/CostModel/X86/interleaved-store-f64-stride-3.ll b/llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-store-f64-stride-3.ll similarity index 100% rename from llvm/test/Analysis/CostModel/X86/interleaved-store-f64-stride-3.ll rename to llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-store-f64-stride-3.ll diff --git a/llvm/test/Analysis/CostModel/X86/interleaved-store-f64-stride-4.ll b/llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-store-f64-stride-4.ll similarity index 100% rename from llvm/test/Analysis/CostModel/X86/interleaved-store-f64-stride-4.ll rename to llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-store-f64-stride-4.ll diff --git a/llvm/test/Analysis/CostModel/X86/interleaved-store-f64-stride-5.ll b/llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-store-f64-stride-5.ll similarity index 100% rename from llvm/test/Analysis/CostModel/X86/interleaved-store-f64-stride-5.ll rename to llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-store-f64-stride-5.ll diff --git a/llvm/test/Analysis/CostModel/X86/interleaved-store-f64-stride-6.ll b/llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-store-f64-stride-6.ll similarity index 100% rename from llvm/test/Analysis/CostModel/X86/interleaved-store-f64-stride-6.ll rename to llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-store-f64-stride-6.ll diff --git a/llvm/test/Analysis/CostModel/X86/interleaved-store-f64-stride-7.ll b/llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-store-f64-stride-7.ll similarity index 100% rename from llvm/test/Analysis/CostModel/X86/interleaved-store-f64-stride-7.ll rename to llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-store-f64-stride-7.ll diff --git a/llvm/test/Analysis/CostModel/X86/interleaved-store-f64-stride-8.ll b/llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-store-f64-stride-8.ll similarity index 100% rename from llvm/test/Analysis/CostModel/X86/interleaved-store-f64-stride-8.ll rename to llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-store-f64-stride-8.ll diff --git a/llvm/test/Analysis/CostModel/X86/interleaved-store-i16-stride-2.ll b/llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-store-i16-stride-2.ll similarity index 100% rename from llvm/test/Analysis/CostModel/X86/interleaved-store-i16-stride-2.ll rename to llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-store-i16-stride-2.ll diff --git a/llvm/test/Analysis/CostModel/X86/interleaved-store-i16-stride-3.ll b/llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-store-i16-stride-3.ll similarity index 100% rename from llvm/test/Analysis/CostModel/X86/interleaved-store-i16-stride-3.ll rename to llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-store-i16-stride-3.ll diff --git a/llvm/test/Analysis/CostModel/X86/interleaved-store-i16-stride-4.ll b/llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-store-i16-stride-4.ll similarity index 100% rename from llvm/test/Analysis/CostModel/X86/interleaved-store-i16-stride-4.ll rename to llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-store-i16-stride-4.ll diff --git a/llvm/test/Analysis/CostModel/X86/interleaved-store-i16-stride-5.ll b/llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-store-i16-stride-5.ll similarity index 100% rename from llvm/test/Analysis/CostModel/X86/interleaved-store-i16-stride-5.ll rename to llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-store-i16-stride-5.ll diff --git a/llvm/test/Analysis/CostModel/X86/interleaved-store-i16-stride-6.ll b/llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-store-i16-stride-6.ll similarity index 100% rename from llvm/test/Analysis/CostModel/X86/interleaved-store-i16-stride-6.ll rename to llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-store-i16-stride-6.ll diff --git a/llvm/test/Analysis/CostModel/X86/interleaved-store-i16-stride-7.ll b/llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-store-i16-stride-7.ll similarity index 100% rename from llvm/test/Analysis/CostModel/X86/interleaved-store-i16-stride-7.ll rename to llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-store-i16-stride-7.ll diff --git a/llvm/test/Analysis/CostModel/X86/interleaved-store-i16-stride-8.ll b/llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-store-i16-stride-8.ll similarity index 100% rename from llvm/test/Analysis/CostModel/X86/interleaved-store-i16-stride-8.ll rename to llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-store-i16-stride-8.ll diff --git a/llvm/test/Analysis/CostModel/X86/interleaved-store-i32-stride-2.ll b/llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-store-i32-stride-2.ll similarity index 100% rename from llvm/test/Analysis/CostModel/X86/interleaved-store-i32-stride-2.ll rename to llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-store-i32-stride-2.ll diff --git a/llvm/test/Analysis/CostModel/X86/interleaved-store-i32-stride-3.ll b/llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-store-i32-stride-3.ll similarity index 100% rename from llvm/test/Analysis/CostModel/X86/interleaved-store-i32-stride-3.ll rename to llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-store-i32-stride-3.ll diff --git a/llvm/test/Analysis/CostModel/X86/interleaved-store-i32-stride-4.ll b/llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-store-i32-stride-4.ll similarity index 100% rename from llvm/test/Analysis/CostModel/X86/interleaved-store-i32-stride-4.ll rename to llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-store-i32-stride-4.ll diff --git a/llvm/test/Analysis/CostModel/X86/interleaved-store-i32-stride-5.ll b/llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-store-i32-stride-5.ll similarity index 100% rename from llvm/test/Analysis/CostModel/X86/interleaved-store-i32-stride-5.ll rename to llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-store-i32-stride-5.ll diff --git a/llvm/test/Analysis/CostModel/X86/interleaved-store-i32-stride-6.ll b/llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-store-i32-stride-6.ll similarity index 100% rename from llvm/test/Analysis/CostModel/X86/interleaved-store-i32-stride-6.ll rename to llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-store-i32-stride-6.ll diff --git a/llvm/test/Analysis/CostModel/X86/interleaved-store-i32-stride-7.ll b/llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-store-i32-stride-7.ll similarity index 100% rename from llvm/test/Analysis/CostModel/X86/interleaved-store-i32-stride-7.ll rename to llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-store-i32-stride-7.ll diff --git a/llvm/test/Analysis/CostModel/X86/interleaved-store-i32-stride-8.ll b/llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-store-i32-stride-8.ll similarity index 100% rename from llvm/test/Analysis/CostModel/X86/interleaved-store-i32-stride-8.ll rename to llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-store-i32-stride-8.ll diff --git a/llvm/test/Analysis/CostModel/X86/interleaved-store-i64-stride-2.ll b/llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-store-i64-stride-2.ll similarity index 100% rename from llvm/test/Analysis/CostModel/X86/interleaved-store-i64-stride-2.ll rename to llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-store-i64-stride-2.ll diff --git a/llvm/test/Analysis/CostModel/X86/interleaved-store-i64-stride-3.ll b/llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-store-i64-stride-3.ll similarity index 100% rename from llvm/test/Analysis/CostModel/X86/interleaved-store-i64-stride-3.ll rename to llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-store-i64-stride-3.ll diff --git a/llvm/test/Analysis/CostModel/X86/interleaved-store-i64-stride-4.ll b/llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-store-i64-stride-4.ll similarity index 100% rename from llvm/test/Analysis/CostModel/X86/interleaved-store-i64-stride-4.ll rename to llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-store-i64-stride-4.ll diff --git a/llvm/test/Analysis/CostModel/X86/interleaved-store-i64-stride-5.ll b/llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-store-i64-stride-5.ll similarity index 100% rename from llvm/test/Analysis/CostModel/X86/interleaved-store-i64-stride-5.ll rename to llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-store-i64-stride-5.ll diff --git a/llvm/test/Analysis/CostModel/X86/interleaved-store-i64-stride-6.ll b/llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-store-i64-stride-6.ll similarity index 100% rename from llvm/test/Analysis/CostModel/X86/interleaved-store-i64-stride-6.ll rename to llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-store-i64-stride-6.ll diff --git a/llvm/test/Analysis/CostModel/X86/interleaved-store-i64-stride-7.ll b/llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-store-i64-stride-7.ll similarity index 100% rename from llvm/test/Analysis/CostModel/X86/interleaved-store-i64-stride-7.ll rename to llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-store-i64-stride-7.ll diff --git a/llvm/test/Analysis/CostModel/X86/interleaved-store-i64-stride-8.ll b/llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-store-i64-stride-8.ll similarity index 100% rename from llvm/test/Analysis/CostModel/X86/interleaved-store-i64-stride-8.ll rename to llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-store-i64-stride-8.ll diff --git a/llvm/test/Analysis/CostModel/X86/interleaved-store-i8-stride-2.ll b/llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-store-i8-stride-2.ll similarity index 100% rename from llvm/test/Analysis/CostModel/X86/interleaved-store-i8-stride-2.ll rename to llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-store-i8-stride-2.ll diff --git a/llvm/test/Analysis/CostModel/X86/interleaved-store-i8-stride-3.ll b/llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-store-i8-stride-3.ll similarity index 100% rename from llvm/test/Analysis/CostModel/X86/interleaved-store-i8-stride-3.ll rename to llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-store-i8-stride-3.ll diff --git a/llvm/test/Analysis/CostModel/X86/interleaved-store-i8-stride-4.ll b/llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-store-i8-stride-4.ll similarity index 100% rename from llvm/test/Analysis/CostModel/X86/interleaved-store-i8-stride-4.ll rename to llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-store-i8-stride-4.ll diff --git a/llvm/test/Analysis/CostModel/X86/interleaved-store-i8-stride-5.ll b/llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-store-i8-stride-5.ll similarity index 100% rename from llvm/test/Analysis/CostModel/X86/interleaved-store-i8-stride-5.ll rename to llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-store-i8-stride-5.ll diff --git a/llvm/test/Analysis/CostModel/X86/interleaved-store-i8-stride-6.ll b/llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-store-i8-stride-6.ll similarity index 100% rename from llvm/test/Analysis/CostModel/X86/interleaved-store-i8-stride-6.ll rename to llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-store-i8-stride-6.ll diff --git a/llvm/test/Analysis/CostModel/X86/interleaved-store-i8-stride-7.ll b/llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-store-i8-stride-7.ll similarity index 100% rename from llvm/test/Analysis/CostModel/X86/interleaved-store-i8-stride-7.ll rename to llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-store-i8-stride-7.ll diff --git a/llvm/test/Analysis/CostModel/X86/interleaved-store-i8-stride-8.ll b/llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-store-i8-stride-8.ll similarity index 100% rename from llvm/test/Analysis/CostModel/X86/interleaved-store-i8-stride-8.ll rename to llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-store-i8-stride-8.ll diff --git a/llvm/test/Analysis/CostModel/X86/masked-gather-i32-with-i8-index.ll b/llvm/test/Transforms/LoopVectorize/X86/CostModel/masked-gather-i32-with-i8-index.ll similarity index 100% rename from llvm/test/Analysis/CostModel/X86/masked-gather-i32-with-i8-index.ll rename to llvm/test/Transforms/LoopVectorize/X86/CostModel/masked-gather-i32-with-i8-index.ll diff --git a/llvm/test/Analysis/CostModel/X86/masked-gather-i64-with-i8-index.ll b/llvm/test/Transforms/LoopVectorize/X86/CostModel/masked-gather-i64-with-i8-index.ll similarity index 100% rename from llvm/test/Analysis/CostModel/X86/masked-gather-i64-with-i8-index.ll rename to llvm/test/Transforms/LoopVectorize/X86/CostModel/masked-gather-i64-with-i8-index.ll diff --git a/llvm/test/Analysis/CostModel/X86/masked-interleaved-load-i16.ll b/llvm/test/Transforms/LoopVectorize/X86/CostModel/masked-interleaved-load-i16.ll similarity index 100% rename from llvm/test/Analysis/CostModel/X86/masked-interleaved-load-i16.ll rename to llvm/test/Transforms/LoopVectorize/X86/CostModel/masked-interleaved-load-i16.ll diff --git a/llvm/test/Analysis/CostModel/X86/masked-interleaved-store-i16.ll b/llvm/test/Transforms/LoopVectorize/X86/CostModel/masked-interleaved-store-i16.ll similarity index 100% rename from llvm/test/Analysis/CostModel/X86/masked-interleaved-store-i16.ll rename to llvm/test/Transforms/LoopVectorize/X86/CostModel/masked-interleaved-store-i16.ll diff --git a/llvm/test/Analysis/CostModel/X86/masked-load-i16.ll b/llvm/test/Transforms/LoopVectorize/X86/CostModel/masked-load-i16.ll similarity index 100% rename from llvm/test/Analysis/CostModel/X86/masked-load-i16.ll rename to llvm/test/Transforms/LoopVectorize/X86/CostModel/masked-load-i16.ll diff --git a/llvm/test/Analysis/CostModel/X86/masked-load-i32.ll b/llvm/test/Transforms/LoopVectorize/X86/CostModel/masked-load-i32.ll similarity index 100% rename from llvm/test/Analysis/CostModel/X86/masked-load-i32.ll rename to llvm/test/Transforms/LoopVectorize/X86/CostModel/masked-load-i32.ll diff --git a/llvm/test/Analysis/CostModel/X86/masked-load-i64.ll b/llvm/test/Transforms/LoopVectorize/X86/CostModel/masked-load-i64.ll similarity index 100% rename from llvm/test/Analysis/CostModel/X86/masked-load-i64.ll rename to llvm/test/Transforms/LoopVectorize/X86/CostModel/masked-load-i64.ll diff --git a/llvm/test/Analysis/CostModel/X86/masked-load-i8.ll b/llvm/test/Transforms/LoopVectorize/X86/CostModel/masked-load-i8.ll similarity index 100% rename from llvm/test/Analysis/CostModel/X86/masked-load-i8.ll rename to llvm/test/Transforms/LoopVectorize/X86/CostModel/masked-load-i8.ll diff --git a/llvm/test/Analysis/CostModel/X86/masked-scatter-i32-with-i8-index.ll b/llvm/test/Transforms/LoopVectorize/X86/CostModel/masked-scatter-i32-with-i8-index.ll similarity index 100% rename from llvm/test/Analysis/CostModel/X86/masked-scatter-i32-with-i8-index.ll rename to llvm/test/Transforms/LoopVectorize/X86/CostModel/masked-scatter-i32-with-i8-index.ll diff --git a/llvm/test/Analysis/CostModel/X86/masked-scatter-i64-with-i8-index.ll b/llvm/test/Transforms/LoopVectorize/X86/CostModel/masked-scatter-i64-with-i8-index.ll similarity index 100% rename from llvm/test/Analysis/CostModel/X86/masked-scatter-i64-with-i8-index.ll rename to llvm/test/Transforms/LoopVectorize/X86/CostModel/masked-scatter-i64-with-i8-index.ll diff --git a/llvm/test/Analysis/CostModel/X86/masked-store-i16.ll b/llvm/test/Transforms/LoopVectorize/X86/CostModel/masked-store-i16.ll similarity index 100% rename from llvm/test/Analysis/CostModel/X86/masked-store-i16.ll rename to llvm/test/Transforms/LoopVectorize/X86/CostModel/masked-store-i16.ll diff --git a/llvm/test/Analysis/CostModel/X86/masked-store-i32.ll b/llvm/test/Transforms/LoopVectorize/X86/CostModel/masked-store-i32.ll similarity index 100% rename from llvm/test/Analysis/CostModel/X86/masked-store-i32.ll rename to llvm/test/Transforms/LoopVectorize/X86/CostModel/masked-store-i32.ll diff --git a/llvm/test/Analysis/CostModel/X86/masked-store-i64.ll b/llvm/test/Transforms/LoopVectorize/X86/CostModel/masked-store-i64.ll similarity index 100% rename from llvm/test/Analysis/CostModel/X86/masked-store-i64.ll rename to llvm/test/Transforms/LoopVectorize/X86/CostModel/masked-store-i64.ll diff --git a/llvm/test/Analysis/CostModel/X86/masked-store-i8.ll b/llvm/test/Transforms/LoopVectorize/X86/CostModel/masked-store-i8.ll similarity index 100% rename from llvm/test/Analysis/CostModel/X86/masked-store-i8.ll rename to llvm/test/Transforms/LoopVectorize/X86/CostModel/masked-store-i8.ll diff --git a/llvm/test/Analysis/CostModel/X86/scatter-i16-with-i8-index.ll b/llvm/test/Transforms/LoopVectorize/X86/CostModel/scatter-i16-with-i8-index.ll similarity index 100% rename from llvm/test/Analysis/CostModel/X86/scatter-i16-with-i8-index.ll rename to llvm/test/Transforms/LoopVectorize/X86/CostModel/scatter-i16-with-i8-index.ll diff --git a/llvm/test/Analysis/CostModel/X86/scatter-i32-with-i8-index.ll b/llvm/test/Transforms/LoopVectorize/X86/CostModel/scatter-i32-with-i8-index.ll similarity index 100% rename from llvm/test/Analysis/CostModel/X86/scatter-i32-with-i8-index.ll rename to llvm/test/Transforms/LoopVectorize/X86/CostModel/scatter-i32-with-i8-index.ll diff --git a/llvm/test/Analysis/CostModel/X86/scatter-i64-with-i8-index.ll b/llvm/test/Transforms/LoopVectorize/X86/CostModel/scatter-i64-with-i8-index.ll similarity index 100% rename from llvm/test/Analysis/CostModel/X86/scatter-i64-with-i8-index.ll rename to llvm/test/Transforms/LoopVectorize/X86/CostModel/scatter-i64-with-i8-index.ll diff --git a/llvm/test/Analysis/CostModel/X86/scatter-i8-with-i8-index.ll b/llvm/test/Transforms/LoopVectorize/X86/CostModel/scatter-i8-with-i8-index.ll similarity index 100% rename from llvm/test/Analysis/CostModel/X86/scatter-i8-with-i8-index.ll rename to llvm/test/Transforms/LoopVectorize/X86/CostModel/scatter-i8-with-i8-index.ll diff --git a/llvm/test/Analysis/CostModel/X86/strided-load-i16.ll b/llvm/test/Transforms/LoopVectorize/X86/CostModel/strided-load-i16.ll similarity index 100% rename from llvm/test/Analysis/CostModel/X86/strided-load-i16.ll rename to llvm/test/Transforms/LoopVectorize/X86/CostModel/strided-load-i16.ll diff --git a/llvm/test/Analysis/CostModel/X86/strided-load-i32.ll b/llvm/test/Transforms/LoopVectorize/X86/CostModel/strided-load-i32.ll similarity index 100% rename from llvm/test/Analysis/CostModel/X86/strided-load-i32.ll rename to llvm/test/Transforms/LoopVectorize/X86/CostModel/strided-load-i32.ll diff --git a/llvm/test/Analysis/CostModel/X86/strided-load-i64.ll b/llvm/test/Transforms/LoopVectorize/X86/CostModel/strided-load-i64.ll similarity index 100% rename from llvm/test/Analysis/CostModel/X86/strided-load-i64.ll rename to llvm/test/Transforms/LoopVectorize/X86/CostModel/strided-load-i64.ll diff --git a/llvm/test/Analysis/CostModel/X86/strided-load-i8.ll b/llvm/test/Transforms/LoopVectorize/X86/CostModel/strided-load-i8.ll similarity index 100% rename from llvm/test/Analysis/CostModel/X86/strided-load-i8.ll rename to llvm/test/Transforms/LoopVectorize/X86/CostModel/strided-load-i8.ll diff --git a/llvm/test/Transforms/PGOProfile/memprof.ll b/llvm/test/Transforms/PGOProfile/memprof.ll index e1457ca7251ed8..205eeb8878989d 100644 --- a/llvm/test/Transforms/PGOProfile/memprof.ll +++ b/llvm/test/Transforms/PGOProfile/memprof.ll @@ -66,6 +66,18 @@ ;; Check that the total sizes are reported if requested. ; RUN: opt < %s -passes='memprof-use' -pgo-warn-missing-function -S -memprof-report-hinted-sizes 2>&1 | FileCheck %s --check-prefixes=TOTALSIZES +;; Make sure we emit a random hotness seed if requested. +; RUN: llvm-profdata merge -memprof-random-hotness %S/Inputs/memprof.memprofraw --profiled-binary %S/Inputs/memprof.exe -o %t.memprofdatarand 2>&1 | FileCheck %s --check-prefix=RAND +; RAND: random hotness seed = +;; Can't check the exact values, but make sure applying the random profile +;; succeeds with the same stats +; RUN: opt < %s -passes='memprof-use' -pgo-warn-missing-function -S -stats 2>&1 | FileCheck %s --check-prefixes=ALL,MEMPROFONLY,MEMPROFSTATS + +;; Make sure we use a specific random hotness seed if requested. +; RUN: llvm-profdata merge -memprof-random-hotness -memprof-random-hotness-seed=1730170724 %S/Inputs/memprof.memprofraw --profiled-binary %S/Inputs/memprof.exe -o %t.memprofdatarand2 2>&1 | FileCheck %s --check-prefix=RAND2 +; RAND2: random hotness seed = 1730170724 +; RUN: opt < %s -passes='memprof-use' -pgo-warn-missing-function -S -stats 2>&1 | FileCheck %s --check-prefixes=MEMPROFRAND2,ALL,MEMPROFONLY,MEMPROFSTATS + ; MEMPROFMATCHINFO: MemProf notcold context with id 1093248920606587996 has total profiled size 10 is matched ; MEMPROFMATCHINFO: MemProf notcold context with id 5725971306423925017 has total profiled size 10 is matched ; MEMPROFMATCHINFO: MemProf notcold context with id 6792096022461663180 has total profiled size 10 is matched @@ -372,6 +384,13 @@ for.end: ; preds = %for.cond ; MEMPROFNOCOLINFO: ![[C10]] = !{i64 -4535090212904553409} ; MEMPROFNOCOLINFO: ![[C11]] = !{i64 3577763375057267810} +;; For the specific random seed, this is the expected order of hotness +; MEMPROFRAND2: !"cold" +; MEMPROFRAND2: !"cold" +; MEMPROFRAND2: !"cold" +; MEMPROFRAND2: !"hot" +; MEMPROFRAND2: !"hot" + ; MEMPROFSTATS: 8 memprof - Number of alloc contexts in memory profile. ; MEMPROFSTATS: 10 memprof - Number of callsites in memory profile. ; MEMPROFSTATS: 6 memprof - Number of functions having valid memory profile. diff --git a/llvm/test/Transforms/PhaseOrdering/X86/pr50392.ll b/llvm/test/Transforms/PhaseOrdering/X86/pr50392.ll new file mode 100644 index 00000000000000..4a024cc4c0309c --- /dev/null +++ b/llvm/test/Transforms/PhaseOrdering/X86/pr50392.ll @@ -0,0 +1,64 @@ +; NOTE: Assertions have been autogenerated by utils/update_test_checks.py +; RUN: opt -mtriple=x86_64-- -mcpu=x86-64 -O3 -S < %s | FileCheck %s --check-prefixes=SSE +; RUN: opt -mtriple=x86_64-- -mcpu=x86-64-v2 -O3 -S < %s | FileCheck %s --check-prefixes=SSE +; RUN: opt -mtriple=x86_64-- -mcpu=btver2 -O3 -S < %s | FileCheck %s --check-prefixes=AVX,AVX1 +; RUN: opt -mtriple=x86_64-- -mcpu=x86-64-v3 -O3 -S < %s | FileCheck %s --check-prefixes=AVX,AVX2 +; RUN: opt -mtriple=x86_64-- -mcpu=x86-64 -passes="default" -S < %s | FileCheck %s --check-prefixes=SSE +; RUN: opt -mtriple=x86_64-- -mcpu=x86-64-v2 -passes="default" -S < %s | FileCheck %s --check-prefixes=SSE +; RUN: opt -mtriple=x86_64-- -mcpu=btver2 -passes="default" -S < %s | FileCheck %s --check-prefixes=AVX,AVX1 +; RUN: opt -mtriple=x86_64-- -mcpu=x86-64-v3 -passes="default" -S < %s | FileCheck %s --check-prefixes=AVX,AVX2 + +define <4 x double> @PR50392(<4 x double> %a, <4 x double> %b) { +; SSE-LABEL: @PR50392( +; SSE-NEXT: [[TMP1:%.*]] = shufflevector <4 x double> [[A:%.*]], <4 x double> [[B:%.*]], <2 x i32> +; SSE-NEXT: [[TMP2:%.*]] = shufflevector <4 x double> [[A]], <4 x double> [[B]], <2 x i32> +; SSE-NEXT: [[TMP3:%.*]] = fadd <2 x double> [[TMP1]], [[TMP2]] +; SSE-NEXT: [[TMP4:%.*]] = shufflevector <2 x double> [[TMP3]], <2 x double> poison, <4 x i32> +; SSE-NEXT: [[VECEXT10:%.*]] = extractelement <4 x double> [[B]], i64 2 +; SSE-NEXT: [[VECEXT11:%.*]] = extractelement <4 x double> [[B]], i64 3 +; SSE-NEXT: [[ADD12:%.*]] = fadd double [[VECEXT10]], [[VECEXT11]] +; SSE-NEXT: [[SHUFFLE:%.*]] = insertelement <4 x double> [[TMP4]], double [[ADD12]], i64 3 +; SSE-NEXT: ret <4 x double> [[SHUFFLE]] +; +; AVX1-LABEL: @PR50392( +; AVX1-NEXT: [[TMP1:%.*]] = shufflevector <4 x double> [[A:%.*]], <4 x double> [[B:%.*]], <2 x i32> +; AVX1-NEXT: [[TMP2:%.*]] = shufflevector <4 x double> [[A]], <4 x double> [[B]], <2 x i32> +; AVX1-NEXT: [[TMP3:%.*]] = fadd <2 x double> [[TMP1]], [[TMP2]] +; AVX1-NEXT: [[TMP4:%.*]] = shufflevector <2 x double> [[TMP3]], <2 x double> poison, <4 x i32> +; AVX1-NEXT: [[VECEXT10:%.*]] = extractelement <4 x double> [[B]], i64 2 +; AVX1-NEXT: [[VECEXT11:%.*]] = extractelement <4 x double> [[B]], i64 3 +; AVX1-NEXT: [[ADD12:%.*]] = fadd double [[VECEXT10]], [[VECEXT11]] +; AVX1-NEXT: [[SHUFFLE:%.*]] = insertelement <4 x double> [[TMP4]], double [[ADD12]], i64 3 +; AVX1-NEXT: ret <4 x double> [[SHUFFLE]] +; +; AVX2-LABEL: @PR50392( +; AVX2-NEXT: [[TMP1:%.*]] = shufflevector <4 x double> [[A:%.*]], <4 x double> [[B:%.*]], <2 x i32> +; AVX2-NEXT: [[TMP2:%.*]] = shufflevector <4 x double> [[A]], <4 x double> [[B]], <2 x i32> +; AVX2-NEXT: [[TMP3:%.*]] = fadd <2 x double> [[TMP1]], [[TMP2]] +; AVX2-NEXT: [[TMP4:%.*]] = shufflevector <2 x double> [[TMP3]], <2 x double> poison, <4 x i32> +; AVX2-NEXT: [[SHIFT:%.*]] = shufflevector <4 x double> [[B]], <4 x double> poison, <4 x i32> +; AVX2-NEXT: [[TMP5:%.*]] = fadd <4 x double> [[B]], [[SHIFT]] +; AVX2-NEXT: [[SHUFFLE:%.*]] = shufflevector <4 x double> [[TMP4]], <4 x double> [[TMP5]], <4 x i32> +; AVX2-NEXT: ret <4 x double> [[SHUFFLE]] +; + %vecext = extractelement <4 x double> %a, i32 0 + %vecext1 = extractelement <4 x double> %a, i32 1 + %add = fadd double %vecext, %vecext1 + %vecinit = insertelement <4 x double> poison, double %add, i32 0 + %vecext2 = extractelement <4 x double> %a, i32 2 + %vecext3 = extractelement <4 x double> %a, i32 3 + %add4 = fadd double %vecext2, %vecext3 + %vecinit5 = insertelement <4 x double> %vecinit, double %add4, i32 1 + %vecext6 = extractelement <4 x double> %b, i32 0 + %vecext7 = extractelement <4 x double> %b, i32 1 + %add8 = fadd double %vecext6, %vecext7 + %vecinit9 = insertelement <4 x double> %vecinit5, double %add8, i32 2 + %vecext10 = extractelement <4 x double> %b, i32 2 + %vecext11 = extractelement <4 x double> %b, i32 3 + %add12 = fadd double %vecext10, %vecext11 + %vecinit13 = insertelement <4 x double> %vecinit9, double %add12, i32 3 + %shuffle = shufflevector <4 x double> %vecinit13, <4 x double> %a, <4 x i32> + ret <4 x double> %shuffle +} +;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line: +; AVX: {{.*}} diff --git a/llvm/test/Transforms/PhaseOrdering/X86/pr94546.ll b/llvm/test/Transforms/PhaseOrdering/X86/pr94546.ll new file mode 100644 index 00000000000000..1d4cee45b66856 --- /dev/null +++ b/llvm/test/Transforms/PhaseOrdering/X86/pr94546.ll @@ -0,0 +1,47 @@ +; NOTE: Assertions have been autogenerated by utils/update_test_checks.py +; RUN: opt -mtriple=x86_64-- -mcpu=x86-64 -O3 -S < %s | FileCheck %s --check-prefixes=SSE +; RUN: opt -mtriple=x86_64-- -mcpu=x86-64-v2 -O3 -S < %s | FileCheck %s --check-prefixes=SSE +; RUN: opt -mtriple=x86_64-- -mcpu=btver2 -O3 -S < %s | FileCheck %s --check-prefixes=AVX,AVX1 +; RUN: opt -mtriple=x86_64-- -mcpu=x86-64-v3 -O3 -S < %s | FileCheck %s --check-prefixes=AVX,AVX2 +; RUN: opt -mtriple=x86_64-- -mcpu=x86-64 -passes="default" -S < %s | FileCheck %s --check-prefixes=SSE +; RUN: opt -mtriple=x86_64-- -mcpu=x86-64-v2 -passes="default" -S < %s | FileCheck %s --check-prefixes=SSE +; RUN: opt -mtriple=x86_64-- -mcpu=btver2 -passes="default" -S < %s | FileCheck %s --check-prefixes=AVX,AVX1 +; RUN: opt -mtriple=x86_64-- -mcpu=x86-64-v3 -passes="default" -S < %s | FileCheck %s --check-prefixes=AVX,AVX2 + +define <4 x double> @PR94546(<4 x double> %a, <4 x double> %b) { +; SSE-LABEL: @PR94546( +; SSE-NEXT: [[TMP1:%.*]] = shufflevector <4 x double> [[A:%.*]], <4 x double> [[B:%.*]], <2 x i32> +; SSE-NEXT: [[TMP2:%.*]] = shufflevector <4 x double> [[A]], <4 x double> [[B]], <2 x i32> +; SSE-NEXT: [[TMP3:%.*]] = fadd <2 x double> [[TMP1]], [[TMP2]] +; SSE-NEXT: [[TMP4:%.*]] = shufflevector <2 x double> [[TMP3]], <2 x double> poison, <4 x i32> +; SSE-NEXT: ret <4 x double> [[TMP4]] +; +; AVX-LABEL: @PR94546( +; AVX-NEXT: [[TMP1:%.*]] = shufflevector <4 x double> [[A:%.*]], <4 x double> [[B:%.*]], <2 x i32> +; AVX-NEXT: [[TMP2:%.*]] = shufflevector <4 x double> [[A]], <4 x double> [[B]], <2 x i32> +; AVX-NEXT: [[TMP3:%.*]] = fadd <2 x double> [[TMP1]], [[TMP2]] +; AVX-NEXT: [[TMP4:%.*]] = shufflevector <2 x double> [[TMP3]], <2 x double> poison, <4 x i32> +; AVX-NEXT: ret <4 x double> [[TMP4]] +; + %vecext = extractelement <4 x double> %a, i32 0 + %vecext1 = extractelement <4 x double> %a, i32 1 + %add = fadd double %vecext, %vecext1 + %vecinit = insertelement <4 x double> poison, double %add, i32 0 + %vecext2 = extractelement <4 x double> %a, i32 2 + %vecext3 = extractelement <4 x double> %a, i32 3 + %add4 = fadd double %vecext2, %vecext3 + %vecinit5 = insertelement <4 x double> %vecinit, double %add4, i32 1 + %vecext6 = extractelement <4 x double> %b, i32 0 + %vecext7 = extractelement <4 x double> %b, i32 1 + %add8 = fadd double %vecext6, %vecext7 + %vecinit9 = insertelement <4 x double> %vecinit5, double %add8, i32 2 + %vecext10 = extractelement <4 x double> %b, i32 2 + %vecext11 = extractelement <4 x double> %b, i32 3 + %add12 = fadd double %vecext10, %vecext11 + %vecinit13 = insertelement <4 x double> %vecinit9, double %add12, i32 3 + %shuffle = shufflevector <4 x double> %vecinit13, <4 x double> %a, <4 x i32> + ret <4 x double> %shuffle +} +;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line: +; AVX1: {{.*}} +; AVX2: {{.*}} diff --git a/llvm/test/Transforms/SLPVectorizer/X86/conversion-fp16.ll b/llvm/test/Transforms/SLPVectorizer/X86/conversion-fp16.ll index bcea147d724f53..f23043f0c47f4a 100644 --- a/llvm/test/Transforms/SLPVectorizer/X86/conversion-fp16.ll +++ b/llvm/test/Transforms/SLPVectorizer/X86/conversion-fp16.ll @@ -453,14 +453,9 @@ define void @fpround_v16xf32_v16xf16(ptr %s0, ptr %d0) { ; ; CHECK-F16C-LABEL: define void @fpround_v16xf32_v16xf16( ; CHECK-F16C-SAME: ptr [[S0:%.*]], ptr [[D0:%.*]]) #[[ATTR0]] { -; CHECK-F16C-NEXT: [[S8:%.*]] = getelementptr inbounds float, ptr [[S0]], i64 8 -; CHECK-F16C-NEXT: [[D8:%.*]] = getelementptr inbounds half, ptr [[D0]], i64 8 -; CHECK-F16C-NEXT: [[TMP1:%.*]] = load <8 x float>, ptr [[S0]], align 4 -; CHECK-F16C-NEXT: [[TMP2:%.*]] = fptrunc <8 x float> [[TMP1]] to <8 x half> -; CHECK-F16C-NEXT: [[TMP3:%.*]] = load <8 x float>, ptr [[S8]], align 4 -; CHECK-F16C-NEXT: [[TMP4:%.*]] = fptrunc <8 x float> [[TMP3]] to <8 x half> -; CHECK-F16C-NEXT: store <8 x half> [[TMP2]], ptr [[D0]], align 2 -; CHECK-F16C-NEXT: store <8 x half> [[TMP4]], ptr [[D8]], align 2 +; CHECK-F16C-NEXT: [[TMP1:%.*]] = load <16 x float>, ptr [[S0]], align 4 +; CHECK-F16C-NEXT: [[TMP2:%.*]] = fptrunc <16 x float> [[TMP1]] to <16 x half> +; CHECK-F16C-NEXT: store <16 x half> [[TMP2]], ptr [[D0]], align 2 ; CHECK-F16C-NEXT: ret void ; ; CHECK-AVX512-LABEL: define void @fpround_v16xf32_v16xf16( diff --git a/llvm/test/Transforms/VectorCombine/X86/permute-of-binops.ll b/llvm/test/Transforms/VectorCombine/X86/permute-of-binops.ll new file mode 100644 index 00000000000000..e94868c7b9e5b3 --- /dev/null +++ b/llvm/test/Transforms/VectorCombine/X86/permute-of-binops.ll @@ -0,0 +1,146 @@ +; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 4 +; RUN: opt < %s -passes=vector-combine -S -mtriple=x86_64-- -mattr=sse2 | FileCheck %s --check-prefixes=CHECK,SSE +; RUN: opt < %s -passes=vector-combine -S -mtriple=x86_64-- -mattr=avx2 | FileCheck %s --check-prefixes=CHECK,AVX + +; Fold "shuffle (binop (shuffle, shuffle)), undef" --> "binop (shuffle), (shuffle)" + +declare void @use_v4f64(<4 x double>) + +define <4 x double> @fadd_v4f64(<4 x double> %a, <4 x double> %b) { +; CHECK-LABEL: define <4 x double> @fadd_v4f64( +; CHECK-SAME: <4 x double> [[A:%.*]], <4 x double> [[B:%.*]]) #[[ATTR0:[0-9]+]] { +; CHECK-NEXT: [[TMP1:%.*]] = shufflevector <4 x double> [[A]], <4 x double> poison, <4 x i32> +; CHECK-NEXT: [[TMP2:%.*]] = shufflevector <4 x double> [[B]], <4 x double> poison, <4 x i32> +; CHECK-NEXT: [[POST:%.*]] = fadd <4 x double> [[TMP1]], [[TMP2]] +; CHECK-NEXT: [[POST1:%.*]] = shufflevector <4 x double> [[POST]], <4 x double> poison, <4 x i32> +; CHECK-NEXT: ret <4 x double> [[POST1]] +; + %a1 = shufflevector <4 x double> %a, <4 x double> poison, <4 x i32> + %b1 = shufflevector <4 x double> %b, <4 x double> poison, <4 x i32> + %op = fadd <4 x double> %a1, %b1 + %post = shufflevector <4 x double> %op, <4 x double> poison, <4 x i32> + ret <4 x double> %post +} + +define <4 x double> @fadd_v4f64_poison_idx(<4 x double> %a, <4 x double> %b) { +; CHECK-LABEL: define <4 x double> @fadd_v4f64_poison_idx( +; CHECK-SAME: <4 x double> [[A:%.*]], <4 x double> [[B:%.*]]) #[[ATTR0]] { +; CHECK-NEXT: [[TMP1:%.*]] = shufflevector <4 x double> [[A]], <4 x double> poison, <4 x i32> +; CHECK-NEXT: [[TMP2:%.*]] = shufflevector <4 x double> [[B]], <4 x double> poison, <4 x i32> +; CHECK-NEXT: [[POST:%.*]] = fadd <4 x double> [[TMP1]], [[TMP2]] +; CHECK-NEXT: [[POST1:%.*]] = shufflevector <4 x double> [[POST]], <4 x double> poison, <4 x i32> +; CHECK-NEXT: ret <4 x double> [[POST1]] +; + %a1 = shufflevector <4 x double> %a, <4 x double> poison, <4 x i32> + %b1 = shufflevector <4 x double> %b, <4 x double> poison, <4 x i32> + %op = fadd <4 x double> %a1, %b1 + %post = shufflevector <4 x double> %op, <4 x double> poison, <4 x i32> + ret <4 x double> %post +} + +define <4 x double> @fadd_mixed_types(<4 x double> %a, <2 x double> %b) { +; CHECK-LABEL: define <4 x double> @fadd_mixed_types( +; CHECK-SAME: <4 x double> [[A:%.*]], <2 x double> [[B:%.*]]) #[[ATTR0]] { +; CHECK-NEXT: [[TMP1:%.*]] = shufflevector <4 x double> [[A]], <4 x double> poison, <4 x i32> +; CHECK-NEXT: [[TMP2:%.*]] = shufflevector <2 x double> [[B]], <2 x double> poison, <4 x i32> +; CHECK-NEXT: [[POST:%.*]] = fadd <4 x double> [[TMP1]], [[TMP2]] +; CHECK-NEXT: [[POST1:%.*]] = shufflevector <4 x double> [[POST]], <4 x double> poison, <4 x i32> +; CHECK-NEXT: ret <4 x double> [[POST1]] +; + %a1 = shufflevector <4 x double> %a, <4 x double> poison, <4 x i32> + %b1 = shufflevector <2 x double> %b, <2 x double> poison, <4 x i32> + %op = fadd <4 x double> %a1, %b1 + %post = shufflevector <4 x double> %op, <4 x double> poison, <4 x i32> + ret <4 x double> %post +} + +; Negative test - multiple use of fadd +define <4 x double> @fadd_v4f64_multiuse_op(<4 x double> %a, <4 x double> %b) { +; CHECK-LABEL: define <4 x double> @fadd_v4f64_multiuse_op( +; CHECK-SAME: <4 x double> [[A:%.*]], <4 x double> [[B:%.*]]) #[[ATTR0]] { +; CHECK-NEXT: [[A1:%.*]] = shufflevector <4 x double> [[A]], <4 x double> poison, <4 x i32> +; CHECK-NEXT: [[B1:%.*]] = shufflevector <4 x double> [[B]], <4 x double> poison, <4 x i32> +; CHECK-NEXT: [[OP:%.*]] = fadd <4 x double> [[A1]], [[B1]] +; CHECK-NEXT: [[POST:%.*]] = shufflevector <4 x double> [[OP]], <4 x double> poison, <4 x i32> +; CHECK-NEXT: call void @use_v4f64(<4 x double> [[OP]]) +; CHECK-NEXT: ret <4 x double> [[POST]] +; + %a1 = shufflevector <4 x double> %a, <4 x double> poison, <4 x i32> + %b1 = shufflevector <4 x double> %b, <4 x double> poison, <4 x i32> + %op = fadd <4 x double> %a1, %b1 + %post = shufflevector <4 x double> %op, <4 x double> poison, <4 x i32> + call void @use_v4f64(<4 x double> %op) + ret <4 x double> %post +} + +; Negative test - multiple use of inner shuffle +define <4 x double> @fadd_v4f64_multiuse_shuffle(<4 x double> %a, <4 x double> %b) { +; CHECK-LABEL: define <4 x double> @fadd_v4f64_multiuse_shuffle( +; CHECK-SAME: <4 x double> [[A:%.*]], <4 x double> [[B:%.*]]) #[[ATTR0]] { +; CHECK-NEXT: [[A1:%.*]] = shufflevector <4 x double> [[A]], <4 x double> poison, <4 x i32> +; CHECK-NEXT: [[B1:%.*]] = shufflevector <4 x double> [[B]], <4 x double> poison, <4 x i32> +; CHECK-NEXT: [[OP:%.*]] = fadd <4 x double> [[A1]], [[B1]] +; CHECK-NEXT: [[POST:%.*]] = shufflevector <4 x double> [[OP]], <4 x double> poison, <4 x i32> +; CHECK-NEXT: call void @use_v4f64(<4 x double> [[A1]]) +; CHECK-NEXT: ret <4 x double> [[POST]] +; + %a1 = shufflevector <4 x double> %a, <4 x double> poison, <4 x i32> + %b1 = shufflevector <4 x double> %b, <4 x double> poison, <4 x i32> + %op = fadd <4 x double> %a1, %b1 + %post = shufflevector <4 x double> %op, <4 x double> poison, <4 x i32> + call void @use_v4f64(<4 x double> %a1) + ret <4 x double> %post +} + +define <4 x i32> @sdiv_v4i32(<4 x i32> %a, <4 x i32> %b) { +; CHECK-LABEL: define <4 x i32> @sdiv_v4i32( +; CHECK-SAME: <4 x i32> [[A:%.*]], <4 x i32> [[B:%.*]]) #[[ATTR0]] { +; CHECK-NEXT: [[TMP1:%.*]] = shufflevector <4 x i32> [[A]], <4 x i32> poison, <4 x i32> +; CHECK-NEXT: [[TMP2:%.*]] = shufflevector <4 x i32> [[B]], <4 x i32> poison, <4 x i32> +; CHECK-NEXT: [[POST:%.*]] = sdiv <4 x i32> [[TMP1]], [[TMP2]] +; CHECK-NEXT: [[POST1:%.*]] = shufflevector <4 x i32> [[POST]], <4 x i32> poison, <4 x i32> +; CHECK-NEXT: ret <4 x i32> [[POST1]] +; + %a1 = shufflevector <4 x i32> %a, <4 x i32> poison, <4 x i32> + %b1 = shufflevector <4 x i32> %b, <4 x i32> poison, <4 x i32> + %op = sdiv <4 x i32> %a1, %b1 + %post = shufflevector <4 x i32> %op, <4 x i32> poison, <4 x i32> + ret <4 x i32> %post +} + +; Negative test - don't introduce poison element into div/rem instruction +define <4 x i32> @sdiv_v4i32_poison(<4 x i32> %a, <4 x i32> %b) { +; CHECK-LABEL: define <4 x i32> @sdiv_v4i32_poison( +; CHECK-SAME: <4 x i32> [[A:%.*]], <4 x i32> [[B:%.*]]) #[[ATTR0]] { +; CHECK-NEXT: [[A1:%.*]] = shufflevector <4 x i32> [[A]], <4 x i32> poison, <4 x i32> +; CHECK-NEXT: [[B1:%.*]] = shufflevector <4 x i32> [[B]], <4 x i32> poison, <4 x i32> +; CHECK-NEXT: [[OP:%.*]] = sdiv <4 x i32> [[A1]], [[B1]] +; CHECK-NEXT: [[POST:%.*]] = shufflevector <4 x i32> [[OP]], <4 x i32> poison, <4 x i32> +; CHECK-NEXT: ret <4 x i32> [[POST]] +; + %a1 = shufflevector <4 x i32> %a, <4 x i32> poison, <4 x i32> + %b1 = shufflevector <4 x i32> %b, <4 x i32> poison, <4 x i32> + %op = sdiv <4 x i32> %a1, %b1 + %post = shufflevector <4 x i32> %op, <4 x i32> poison, <4 x i32> + ret <4 x i32> %post +} + +; Negative test - don't introduce poison element into div/rem instruction +define <4 x i32> @sdiv_v4i32_poison_idx(<4 x i32> %a, <4 x i32> %b) { +; CHECK-LABEL: define <4 x i32> @sdiv_v4i32_poison_idx( +; CHECK-SAME: <4 x i32> [[A:%.*]], <4 x i32> [[B:%.*]]) #[[ATTR0]] { +; CHECK-NEXT: [[A1:%.*]] = shufflevector <4 x i32> [[A]], <4 x i32> poison, <4 x i32> +; CHECK-NEXT: [[B1:%.*]] = shufflevector <4 x i32> [[B]], <4 x i32> poison, <4 x i32> +; CHECK-NEXT: [[OP:%.*]] = sdiv <4 x i32> [[A1]], [[B1]] +; CHECK-NEXT: [[POST:%.*]] = shufflevector <4 x i32> [[OP]], <4 x i32> poison, <4 x i32> +; CHECK-NEXT: ret <4 x i32> [[POST]] +; + %a1 = shufflevector <4 x i32> %a, <4 x i32> poison, <4 x i32> + %b1 = shufflevector <4 x i32> %b, <4 x i32> poison, <4 x i32> + %op = sdiv <4 x i32> %a1, %b1 + %post = shufflevector <4 x i32> %op, <4 x i32> poison, <4 x i32> + ret <4 x i32> %post +} +;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line: +; AVX: {{.*}} +; SSE: {{.*}} diff --git a/llvm/test/tools/UpdateTestChecks/update_mc_test_checks/Inputs/amdgpu_asm.s.expected b/llvm/test/tools/UpdateTestChecks/update_mc_test_checks/Inputs/amdgpu_asm.s.expected index 7336947a3f57a0..2dc30cd112e465 100644 --- a/llvm/test/tools/UpdateTestChecks/update_mc_test_checks/Inputs/amdgpu_asm.s.expected +++ b/llvm/test/tools/UpdateTestChecks/update_mc_test_checks/Inputs/amdgpu_asm.s.expected @@ -1,4 +1,4 @@ -; NOTE: Assertions have been autogenerated by utils/update_mc_test_checks.py +// NOTE: Assertions have been autogenerated by utils/update_mc_test_checks.py // RUN: llvm-mc -triple=amdgcn -show-encoding %s 2>&1 | FileCheck --check-prefixes=CHECK %s v_bfrev_b32 v5, v1 diff --git a/llvm/test/tools/UpdateTestChecks/update_mc_test_checks/Inputs/amdgpu_asm_err.s b/llvm/test/tools/UpdateTestChecks/update_mc_test_checks/Inputs/amdgpu_asm_err.s index 489bd1801d864a..76f8e7880d836e 100644 --- a/llvm/test/tools/UpdateTestChecks/update_mc_test_checks/Inputs/amdgpu_asm_err.s +++ b/llvm/test/tools/UpdateTestChecks/update_mc_test_checks/Inputs/amdgpu_asm_err.s @@ -1,3 +1,6 @@ -// RUN: not llvm-mc -triple=amdgcn -show-encoding %s 2>&1 | FileCheck --check-prefixes=CHECK %s +// RUN: not llvm-mc -triple=amdgcn -show-encoding %s 2>&1 | FileCheck --check-prefixes=CHECKA %s +// RUN: not llvm-mc -triple=amdgcn %s 2>&1 | FileCheck --check-prefixes=CHECKB %s v_bfrev_b32 v5, v299 + +v_bfrev_b32 v5, v1 diff --git a/llvm/test/tools/UpdateTestChecks/update_mc_test_checks/Inputs/amdgpu_asm_err.s.expected b/llvm/test/tools/UpdateTestChecks/update_mc_test_checks/Inputs/amdgpu_asm_err.s.expected index 0a0ad51d15e056..fffe299f3d16f6 100644 --- a/llvm/test/tools/UpdateTestChecks/update_mc_test_checks/Inputs/amdgpu_asm_err.s.expected +++ b/llvm/test/tools/UpdateTestChecks/update_mc_test_checks/Inputs/amdgpu_asm_err.s.expected @@ -1,5 +1,11 @@ -; NOTE: Assertions have been autogenerated by utils/update_mc_test_checks.py -// RUN: not llvm-mc -triple=amdgcn -show-encoding %s 2>&1 | FileCheck --check-prefixes=CHECK %s +// NOTE: Assertions have been autogenerated by utils/update_mc_test_checks.py +// RUN: not llvm-mc -triple=amdgcn -show-encoding %s 2>&1 | FileCheck --check-prefixes=CHECKA %s +// RUN: not llvm-mc -triple=amdgcn %s 2>&1 | FileCheck --check-prefixes=CHECKB %s v_bfrev_b32 v5, v299 -// CHECK: :[[@LINE-1]]:17: error: register index is out of range +// CHECKA: :[[@LINE-1]]:17: error: register index is out of range +// CHECKB: :[[@LINE-2]]:17: error: register index is out of range + +v_bfrev_b32 v5, v1 +// CHECKA: v_bfrev_b32_e32 v5, v1 ; encoding: [0x01,0x71,0x0a,0x7e] +// CHECKB: v_bfrev_b32_e32 v5, v1 diff --git a/llvm/test/tools/UpdateTestChecks/update_mc_test_checks/Inputs/amdgpu_asm_sort.s b/llvm/test/tools/UpdateTestChecks/update_mc_test_checks/Inputs/amdgpu_asm_sort.s new file mode 100644 index 00000000000000..ea03c5a6911fad --- /dev/null +++ b/llvm/test/tools/UpdateTestChecks/update_mc_test_checks/Inputs/amdgpu_asm_sort.s @@ -0,0 +1,5 @@ +// RUN: llvm-mc -triple=amdgcn -show-encoding %s 2>&1 | FileCheck --check-prefixes=CHECK %s + +v_bfrev_b32 v5, v1 + +v_bfrev_b32 v1, v1 diff --git a/llvm/test/tools/UpdateTestChecks/update_mc_test_checks/Inputs/amdgpu_asm_sort.s.expected b/llvm/test/tools/UpdateTestChecks/update_mc_test_checks/Inputs/amdgpu_asm_sort.s.expected new file mode 100644 index 00000000000000..57f72ed406fb40 --- /dev/null +++ b/llvm/test/tools/UpdateTestChecks/update_mc_test_checks/Inputs/amdgpu_asm_sort.s.expected @@ -0,0 +1,8 @@ +// NOTE: Assertions have been autogenerated by utils/update_mc_test_checks.py UTC_ARGS: --sort +// RUN: llvm-mc -triple=amdgcn -show-encoding %s 2>&1 | FileCheck --check-prefixes=CHECK %s + +v_bfrev_b32 v1, v1 +// CHECK: v_bfrev_b32_e32 v1, v1 ; encoding: [0x01,0x71,0x02,0x7e] + +v_bfrev_b32 v5, v1 +// CHECK: v_bfrev_b32_e32 v5, v1 ; encoding: [0x01,0x71,0x0a,0x7e] diff --git a/llvm/test/tools/UpdateTestChecks/update_mc_test_checks/Inputs/amdgpu_asm_sort_with_comment.s b/llvm/test/tools/UpdateTestChecks/update_mc_test_checks/Inputs/amdgpu_asm_sort_with_comment.s new file mode 100644 index 00000000000000..d60b3bda29eda2 --- /dev/null +++ b/llvm/test/tools/UpdateTestChecks/update_mc_test_checks/Inputs/amdgpu_asm_sort_with_comment.s @@ -0,0 +1,9 @@ +// RUN: llvm-mc -triple=amdgcn -show-encoding %s 2>&1 | FileCheck --check-prefixes=CHECK %s + +v_bfrev_b32 v5, v1 //This is comment A + +v_bfrev_b32 v1, v1 +// This is comment B + +// This is comment C +v_bfrev_b32 v2, v1 diff --git a/llvm/test/tools/UpdateTestChecks/update_mc_test_checks/Inputs/amdgpu_asm_sort_with_comment.s.expected b/llvm/test/tools/UpdateTestChecks/update_mc_test_checks/Inputs/amdgpu_asm_sort_with_comment.s.expected new file mode 100644 index 00000000000000..6924880032717e --- /dev/null +++ b/llvm/test/tools/UpdateTestChecks/update_mc_test_checks/Inputs/amdgpu_asm_sort_with_comment.s.expected @@ -0,0 +1,13 @@ +// NOTE: Assertions have been autogenerated by utils/update_mc_test_checks.py UTC_ARGS: --sort +// RUN: llvm-mc -triple=amdgcn -show-encoding %s 2>&1 | FileCheck --check-prefixes=CHECK %s + +v_bfrev_b32 v1, v1 +// CHECK: v_bfrev_b32_e32 v1, v1 ; encoding: [0x01,0x71,0x02,0x7e] +// This is comment B + +// This is comment C +v_bfrev_b32 v2, v1 +// CHECK: v_bfrev_b32_e32 v2, v1 ; encoding: [0x01,0x71,0x04,0x7e] + +v_bfrev_b32 v5, v1 //This is comment A +// CHECK: v_bfrev_b32_e32 v5, v1 ; encoding: [0x01,0x71,0x0a,0x7e] diff --git a/llvm/test/tools/UpdateTestChecks/update_mc_test_checks/Inputs/amdgpu_asm_unique.s b/llvm/test/tools/UpdateTestChecks/update_mc_test_checks/Inputs/amdgpu_asm_unique.s new file mode 100644 index 00000000000000..63240174cdde55 --- /dev/null +++ b/llvm/test/tools/UpdateTestChecks/update_mc_test_checks/Inputs/amdgpu_asm_unique.s @@ -0,0 +1,10 @@ +// RUN: llvm-mc -triple=amdgcn -show-encoding %s 2>&1 | FileCheck --check-prefixes=CHECK %s + +//this is commentA +v_bfrev_b32 v5, v1 + +v_bfrev_b32 v5, v1 + +//this is commentB + +//this is commentB diff --git a/llvm/test/tools/UpdateTestChecks/update_mc_test_checks/Inputs/amdgpu_asm_unique.s.expected b/llvm/test/tools/UpdateTestChecks/update_mc_test_checks/Inputs/amdgpu_asm_unique.s.expected new file mode 100644 index 00000000000000..8203b90040ba4e --- /dev/null +++ b/llvm/test/tools/UpdateTestChecks/update_mc_test_checks/Inputs/amdgpu_asm_unique.s.expected @@ -0,0 +1,10 @@ +// NOTE: Assertions have been autogenerated by utils/update_mc_test_checks.py UTC_ARGS: --unique +// RUN: llvm-mc -triple=amdgcn -show-encoding %s 2>&1 | FileCheck --check-prefixes=CHECK %s + +//this is commentA +v_bfrev_b32 v5, v1 +// CHECK: v_bfrev_b32_e32 v5, v1 ; encoding: [0x01,0x71,0x0a,0x7e] + +//this is commentB + +//this is commentB diff --git a/llvm/test/tools/UpdateTestChecks/update_mc_test_checks/Inputs/amdgpu_dasm.txt.expected b/llvm/test/tools/UpdateTestChecks/update_mc_test_checks/Inputs/amdgpu_dasm.txt.expected index a6f7abcb1774ac..b3cbaff6d1c7ef 100644 --- a/llvm/test/tools/UpdateTestChecks/update_mc_test_checks/Inputs/amdgpu_dasm.txt.expected +++ b/llvm/test/tools/UpdateTestChecks/update_mc_test_checks/Inputs/amdgpu_dasm.txt.expected @@ -1,4 +1,4 @@ -; NOTE: Assertions have been autogenerated by utils/update_mc_test_checks.py +# NOTE: Assertions have been autogenerated by utils/update_mc_test_checks.py # RUN: llvm-mc -triple=amdgcn -mcpu=gfx1100 -disassemble -show-encoding %s 2>&1 | FileCheck -check-prefixes=CHECK %s 0x00,0x00,0x00,0x7e diff --git a/llvm/test/tools/UpdateTestChecks/update_mc_test_checks/Inputs/amdgpu_dasm_unique.txt b/llvm/test/tools/UpdateTestChecks/update_mc_test_checks/Inputs/amdgpu_dasm_unique.txt new file mode 100644 index 00000000000000..3d0d49ddeea425 --- /dev/null +++ b/llvm/test/tools/UpdateTestChecks/update_mc_test_checks/Inputs/amdgpu_dasm_unique.txt @@ -0,0 +1,5 @@ +# RUN: llvm-mc -triple=amdgcn -mcpu=gfx1100 -disassemble -show-encoding %s 2>&1 | FileCheck -check-prefixes=CHECK %s + +0x00,0x00,0x00,0x7e + +0x00,0x00,0x00,0x7e diff --git a/llvm/test/tools/UpdateTestChecks/update_mc_test_checks/Inputs/amdgpu_dasm_unique.txt.expected b/llvm/test/tools/UpdateTestChecks/update_mc_test_checks/Inputs/amdgpu_dasm_unique.txt.expected new file mode 100644 index 00000000000000..32bddb20628dad --- /dev/null +++ b/llvm/test/tools/UpdateTestChecks/update_mc_test_checks/Inputs/amdgpu_dasm_unique.txt.expected @@ -0,0 +1,5 @@ +# NOTE: Assertions have been autogenerated by utils/update_mc_test_checks.py UTC_ARGS: --unique +# RUN: llvm-mc -triple=amdgcn -mcpu=gfx1100 -disassemble -show-encoding %s 2>&1 | FileCheck -check-prefixes=CHECK %s + +0x00,0x00,0x00,0x7e +# CHECK: v_nop ; encoding: [0x00,0x00,0x00,0x7e] diff --git a/llvm/test/tools/UpdateTestChecks/update_mc_test_checks/Inputs/amdgpu_multirun_dasm.txt.expected b/llvm/test/tools/UpdateTestChecks/update_mc_test_checks/Inputs/amdgpu_multirun_dasm.txt.expected index 03a5ec3c559dbf..7b6b832801625b 100644 --- a/llvm/test/tools/UpdateTestChecks/update_mc_test_checks/Inputs/amdgpu_multirun_dasm.txt.expected +++ b/llvm/test/tools/UpdateTestChecks/update_mc_test_checks/Inputs/amdgpu_multirun_dasm.txt.expected @@ -1,4 +1,4 @@ -; NOTE: Assertions have been autogenerated by utils/update_mc_test_checks.py +# NOTE: Assertions have been autogenerated by utils/update_mc_test_checks.py # RUN: llvm-mc -triple=amdgcn -mcpu=tonga -disassemble -show-encoding %s 2>&1 | FileCheck -check-prefixes=CHECK,CHECKA %s # RUN: llvm-mc -triple=amdgcn -mcpu=gfx1100 -disassemble -show-encoding %s 2>&1 | FileCheck -check-prefixes=CHECK,CHECKB %s diff --git a/llvm/test/tools/UpdateTestChecks/update_mc_test_checks/amdgpu-sort.test b/llvm/test/tools/UpdateTestChecks/update_mc_test_checks/amdgpu-sort.test new file mode 100644 index 00000000000000..f8972ffabf0999 --- /dev/null +++ b/llvm/test/tools/UpdateTestChecks/update_mc_test_checks/amdgpu-sort.test @@ -0,0 +1,7 @@ +# REQUIRES: amdgpu-registered-target +## Check that sort is working + +# RUN: cp -f %S/Inputs/amdgpu_asm_sort.s %t.s && %update_mc_test_checks --sort %t.s +# RUN: diff -u %S/Inputs/amdgpu_asm_sort.s.expected %t.s +# RUN: cp -f %S/Inputs/amdgpu_asm_sort_with_comment.s %t.s && %update_mc_test_checks --sort %t.s +# RUN: diff -u %S/Inputs/amdgpu_asm_sort_with_comment.s.expected %t.s diff --git a/llvm/test/tools/UpdateTestChecks/update_mc_test_checks/amdgpu-unique.test b/llvm/test/tools/UpdateTestChecks/update_mc_test_checks/amdgpu-unique.test new file mode 100644 index 00000000000000..8a5d83462cad73 --- /dev/null +++ b/llvm/test/tools/UpdateTestChecks/update_mc_test_checks/amdgpu-unique.test @@ -0,0 +1,7 @@ +# REQUIRES: amdgpu-registered-target +## Check that unique is working + +# RUN: cp -f %S/Inputs/amdgpu_asm_unique.s %t.s && %update_mc_test_checks --unique %t.s +# RUN: diff -u %S/Inputs/amdgpu_asm_unique.s.expected %t.s +# RUN: cp -f %S/Inputs/amdgpu_dasm_unique.txt %t.txt && %update_mc_test_checks --unique %t.txt +# RUN: diff -u %S/Inputs/amdgpu_dasm_unique.txt.expected %t.txt diff --git a/llvm/test/tools/llvm-objdump/X86/disassemble-color.s b/llvm/test/tools/llvm-objdump/X86/disassemble-color.s new file mode 100644 index 00000000000000..4e1d82562fb546 --- /dev/null +++ b/llvm/test/tools/llvm-objdump/X86/disassemble-color.s @@ -0,0 +1,21 @@ +# UNSUPPORTED: system-windows +# RUN: llvm-mc -filetype=obj -triple=x86_64 %s -o %t +# RUN: llvm-objdump -d --no-show-raw-insn --disassembler-color=on %t | FileCheck %s --check-prefix=ATT +# RUN: llvm-objdump -d --no-show-raw-insn --disassembler-color=on -M intel %t | FileCheck %s --check-prefix=INTEL + +# ATT: <.text>: +# ATT-NEXT: leaq (%rdx,%rax,4), %rbx +# ATT-NEXT: movq (,%rax), %rbx +# ATT-NEXT: leaq 0x3(%rdx,%rax), %rbx +# ATT-NEXT: movq $0x3, %rax + +# INTEL: <.text>: +# INTEL-NEXT: lea rbx, [rdx + 4*rax] +# INTEL-NEXT: mov rbx, qword ptr [1*rax] +# INTEL-NEXT: lea rbx, [rdx + rax + 0x3] +# INTEL-NEXT: mov rax, 0x3 + +leaq (%rdx,%rax,4), %rbx +movq (,%rax), %rbx +leaq 3(%rdx,%rax), %rbx +movq $3, %rax diff --git a/llvm/tools/llvm-profdata/llvm-profdata.cpp b/llvm/tools/llvm-profdata/llvm-profdata.cpp index 59f0f1f1fae899..f7023aa966adf6 100644 --- a/llvm/tools/llvm-profdata/llvm-profdata.cpp +++ b/llvm/tools/llvm-profdata/llvm-profdata.cpp @@ -342,6 +342,15 @@ cl::opt MemProfFullSchema( "memprof-full-schema", cl::Hidden, cl::sub(MergeSubcommand), cl::desc("Use the full schema for serialization"), cl::init(false)); +static cl::opt + MemprofGenerateRandomHotness("memprof-random-hotness", cl::init(false), + cl::Hidden, cl::sub(MergeSubcommand), + cl::desc("Generate random hotness values")); +static cl::opt MemprofGenerateRandomHotnessSeed( + "memprof-random-hotness-seed", cl::init(0), cl::Hidden, + cl::sub(MergeSubcommand), + cl::desc("Random hotness seed to use (0 to generate new seed)")); + // Options specific to overlap subcommand. cl::opt BaseFilename(cl::Positional, cl::Required, cl::desc(""), @@ -641,7 +650,8 @@ struct WriterContext { SmallSet &WriterErrorCodes, uint64_t ReservoirSize = 0, uint64_t MaxTraceLength = 0) : Writer(IsSparse, ReservoirSize, MaxTraceLength, DoWritePrevVersion, - MemProfVersionRequested, MemProfFullSchema), + MemProfVersionRequested, MemProfFullSchema, + MemprofGenerateRandomHotness, MemprofGenerateRandomHotnessSeed), ErrLock(ErrLock), WriterErrorCodes(WriterErrorCodes) {} }; diff --git a/llvm/unittests/ADT/CMakeLists.txt b/llvm/unittests/ADT/CMakeLists.txt index 745e4d9fb74a4a..b0077d5b54a3ee 100644 --- a/llvm/unittests/ADT/CMakeLists.txt +++ b/llvm/unittests/ADT/CMakeLists.txt @@ -86,6 +86,7 @@ add_llvm_unittest(ADTTests StringSetTest.cpp StringSwitchTest.cpp TinyPtrVectorTest.cpp + TrieRawHashMapTest.cpp TwineTest.cpp TypeSwitchTest.cpp TypeTraitsTest.cpp diff --git a/llvm/unittests/ADT/TrieRawHashMapTest.cpp b/llvm/unittests/ADT/TrieRawHashMapTest.cpp new file mode 100644 index 00000000000000..c9081f547812e9 --- /dev/null +++ b/llvm/unittests/ADT/TrieRawHashMapTest.cpp @@ -0,0 +1,346 @@ +//===- TrieRawHashMapTest.cpp ---------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +#include "llvm/ADT/TrieRawHashMap.h" +#include "llvm/ADT/Twine.h" +#include "llvm/Support/Endian.h" +#include "llvm/Support/SHA1.h" +#include "gtest/gtest.h" + +using namespace llvm; + +namespace llvm { +class TrieRawHashMapTestHelper { +public: + TrieRawHashMapTestHelper() = default; + + void setTrie(ThreadSafeTrieRawHashMapBase *T) { Trie = T; } + + ThreadSafeTrieRawHashMapBase::PointerBase getRoot() const { + return Trie->getRoot(); + } + unsigned getStartBit(ThreadSafeTrieRawHashMapBase::PointerBase P) const { + return Trie->getStartBit(P); + } + unsigned getNumBits(ThreadSafeTrieRawHashMapBase::PointerBase P) const { + return Trie->getNumBits(P); + } + unsigned getNumSlotUsed(ThreadSafeTrieRawHashMapBase::PointerBase P) const { + return Trie->getNumSlotUsed(P); + } + unsigned getNumTries() const { return Trie->getNumTries(); } + std::string + getTriePrefixAsString(ThreadSafeTrieRawHashMapBase::PointerBase P) const { + return Trie->getTriePrefixAsString(P); + } + ThreadSafeTrieRawHashMapBase::PointerBase + getNextTrie(ThreadSafeTrieRawHashMapBase::PointerBase P) const { + return Trie->getNextTrie(P); + } + +private: + ThreadSafeTrieRawHashMapBase *Trie = nullptr; +}; +} // namespace llvm + +namespace { +template +class SimpleTrieHashMapTest : public TrieRawHashMapTestHelper, + public ::testing::Test { +public: + using NumType = DataType; + using HashType = std::array; + using TrieType = ThreadSafeTrieRawHashMap; + + TrieType &createTrie(size_t RootBits, size_t SubtrieBits) { + auto &Ret = Trie.emplace(RootBits, SubtrieBits); + TrieRawHashMapTestHelper::setTrie(&Ret); + return Ret; + } + + void destroyTrie() { Trie.reset(); } + ~SimpleTrieHashMapTest() { destroyTrie(); } + + // Use the number itself as hash to test the pathological case. + static HashType hash(uint64_t Num) { + uint64_t HashN = + llvm::support::endian::byte_swap(Num, llvm::endianness::big); + HashType Hash; + memcpy(&Hash[0], &HashN, sizeof(HashType)); + return Hash; + }; + +private: + std::optional Trie; +}; + +using SmallNodeTrieTest = SimpleTrieHashMapTest; + +TEST_F(SmallNodeTrieTest, TrieAllocation) { + NumType Numbers[] = { + 0x0, std::numeric_limits::max(), 0x1, 0x2, + 0x3, std::numeric_limits::max() - 1u, + }; + + unsigned ExpectedTries[] = { + 1, // Allocate Root. + 1, // Both on the root. + 64, // 0 and 1 sinks all the way down. + 64, // no new allocation needed. + 65, // need a new node between 2 and 3. + 65 + 63, // 63 new allocation to sink two big numbers all the way. + }; + + const char *ExpectedPrefix[] = { + "", // Root. + "", // Root. + "00000000000000[0000000]", + "00000000000000[0000000]", + "00000000000000[0000001]", + "ffffffffffffff[1111111]", + }; + + // Use root and subtrie sizes of 1 so this gets sunk quite deep. + auto &Trie = createTrie(/*RootBits=*/1, /*SubtrieBits=*/1); + + for (unsigned I = 0; I < 6; ++I) { + // Lookup first to exercise hint code for deep tries. + TrieType::pointer Lookup = Trie.find(hash(Numbers[I])); + EXPECT_FALSE(Lookup); + + Trie.insert(Lookup, TrieType::value_type(hash(Numbers[I]), Numbers[I])); + EXPECT_EQ(getNumTries(), ExpectedTries[I]); + EXPECT_EQ(getTriePrefixAsString(getNextTrie(getRoot())), ExpectedPrefix[I]); + } +} + +TEST_F(SmallNodeTrieTest, TrieStructure) { + NumType Numbers[] = { + // Three numbers that will nest deeply to test (1) sinking subtries and + // (2) deep, non-trivial hints. + std::numeric_limits::max(), + std::numeric_limits::max() - 2u, + std::numeric_limits::max() - 3u, + // One number to stay at the top-level. + 0x37, + }; + + // Use root and subtrie sizes of 1 so this gets sunk quite deep. + auto &Trie = createTrie(/*RootBits=*/1, /*SubtrieBits=*/1); + + for (NumType N : Numbers) { + // Lookup first to exercise hint code for deep tries. + TrieType::pointer Lookup = Trie.find(hash(N)); + EXPECT_FALSE(Lookup); + + Trie.insert(Lookup, TrieType::value_type(hash(N), N)); + } + for (NumType N : Numbers) { + TrieType::pointer Lookup = Trie.find(hash(N)); + EXPECT_TRUE(Lookup); + if (!Lookup) + continue; + EXPECT_EQ(hash(N), Lookup->Hash); + EXPECT_EQ(N, Lookup->Data); + + // Confirm a subsequent insertion fails to overwrite by trying to insert a + // bad value. + auto Result = Trie.insert(Lookup, TrieType::value_type(hash(N), N - 1)); + EXPECT_EQ(N, Result->Data); + } + + // Check the trie so we can confirm the structure is correct. Each subtrie + // should have 2 slots. The root's index=0 should have the content for + // 0x37 directly, and index=1 should be a linked-list of subtries, finally + // ending with content for (max-2) and (max-3). + // + // Note: This structure is not exhaustive (too expensive to update tests), + // but it does test that the dump format is somewhat readable and that the + // basic structure is correct. + // + // Note: This test requires that the trie reads bytes starting from index 0 + // of the array of uint8_t, and then reads each byte's bits from high to low. + + // Check the Trie. + // We should allocated a total of 64 SubTries for 64 bit hash. + ASSERT_EQ(getNumTries(), 64u); + // Check the root trie. Two slots and both are used. + ASSERT_EQ(getNumSlotUsed(getRoot()), 2u); + // Check last subtrie. + // Last allocated trie is the next node in the allocation chain. + auto LastAlloctedSubTrie = getNextTrie(getRoot()); + ASSERT_EQ(getTriePrefixAsString(LastAlloctedSubTrie), + "ffffffffffffff[1111110]"); + ASSERT_EQ(getStartBit(LastAlloctedSubTrie), 63u); + ASSERT_EQ(getNumBits(LastAlloctedSubTrie), 1u); + ASSERT_EQ(getNumSlotUsed(LastAlloctedSubTrie), 2u); +} + +TEST_F(SmallNodeTrieTest, TrieStructureSmallFinalSubtrie) { + NumType Numbers[] = { + // Three numbers that will nest deeply to test (1) sinking subtries and + // (2) deep, non-trivial hints. + std::numeric_limits::max(), + std::numeric_limits::max() - 2u, + std::numeric_limits::max() - 3u, + // One number to stay at the top-level. + 0x37, + }; + + // Use subtrie size of 5 to avoid hitting 64 evenly, making the final subtrie + // small. + auto &Trie = createTrie(/*RootBits=*/8, /*SubtrieBits=*/5); + + for (NumType N : Numbers) { + // Lookup first to exercise hint code for deep tries. + TrieType::pointer Lookup = Trie.find(hash(N)); + EXPECT_FALSE(Lookup); + + Trie.insert(Lookup, TrieType::value_type(hash(N), N)); + } + for (NumType N : Numbers) { + TrieType::pointer Lookup = Trie.find(hash(N)); + ASSERT_TRUE(Lookup); + EXPECT_EQ(hash(N), Lookup->Hash); + EXPECT_EQ(N, Lookup->Data); + + // Confirm a subsequent insertion fails to overwrite by trying to insert a + // bad value. + auto Result = Trie.insert(Lookup, TrieType::value_type(hash(N), N - 1)); + EXPECT_EQ(N, Result->Data); + } + + // Check the trie so we can confirm the structure is correct. The root + // should have 2^8=256 slots, most subtries should have 2^5=32 slots, and the + // deepest subtrie should have 2^1=2 slots (since (64-8)mod(5)=1). + // should have 2 slots. The root's index=0 should have the content for + // 0x37 directly, and index=1 should be a linked-list of subtries, finally + // ending with content for (max-2) and (max-3). + // + // Note: This structure is not exhaustive (too expensive to update tests), + // but it does test that the dump format is somewhat readable and that the + // basic structure is correct. + // + // Note: This test requires that the trie reads bytes starting from index 0 + // of the array of uint8_t, and then reads each byte's bits from high to low. + + // Check the Trie. + // 64 bit hash = 8 + 5 * 11 + 1, so 1 root, 11 8bit subtrie and 1 last level + // subtrie, 13 total. + ASSERT_EQ(getNumTries(), 13u); + // Check the root trie. Two slots and both are used. + ASSERT_EQ(getNumSlotUsed(getRoot()), 2u); + // Check last subtrie. + // Last allocated trie is the next node in the allocation chain. + auto LastAlloctedSubTrie = getNextTrie(getRoot()); + ASSERT_EQ(getTriePrefixAsString(LastAlloctedSubTrie), + "ffffffffffffff[1111110]"); + ASSERT_EQ(getStartBit(LastAlloctedSubTrie), 63u); + ASSERT_EQ(getNumBits(LastAlloctedSubTrie), 1u); + ASSERT_EQ(getNumSlotUsed(LastAlloctedSubTrie), 2u); +} + +TEST_F(SmallNodeTrieTest, TrieDestructionLoop) { + // Test destroying large Trie. Make sure there is no recursion that can + // overflow the stack. + + // Limit the tries to 2 slots (1 bit) to generate subtries at a higher rate. + auto &Trie = createTrie(/*NumRootBits=*/1, /*NumSubtrieBits=*/1); + + // Fill them up. Pick a MaxN high enough to cause a stack overflow in debug + // builds. + static constexpr uint64_t MaxN = 100000; + for (uint64_t N = 0; N != MaxN; ++N) { + HashType Hash = hash(N); + Trie.insert(TrieType::pointer(), TrieType::value_type(Hash, NumType{N})); + } + + // Destroy tries. If destruction is recursive and MaxN is high enough, these + // will both fail. + destroyTrie(); +} + +struct NumWithDestructorT { + uint64_t Num; + llvm::function_ref DestructorCallback; + ~NumWithDestructorT() { DestructorCallback(); } +}; + +using NodeWithDestructorTrieTest = SimpleTrieHashMapTest; + +TEST_F(NodeWithDestructorTrieTest, TrieDestructionLoop) { + // Test destroying large Trie. Make sure there is no recursion that can + // overflow the stack. + + // Limit the tries to 2 slots (1 bit) to generate subtries at a higher rate. + auto &Trie = createTrie(/*NumRootBits=*/1, /*NumSubtrieBits=*/1); + + // Fill them up. Pick a MaxN high enough to cause a stack overflow in debug + // builds. + static constexpr uint64_t MaxN = 100000; + + uint64_t DestructorCalled = 0; + auto DtorCallback = [&DestructorCalled]() { ++DestructorCalled; }; + for (uint64_t N = 0; N != MaxN; ++N) { + HashType Hash = hash(N); + Trie.insert(TrieType::pointer(), + TrieType::value_type(Hash, NumType{N, DtorCallback})); + } + // Reset the count after all the temporaries get destroyed. + DestructorCalled = 0; + + // Destroy tries. If destruction is recursive and MaxN is high enough, these + // will both fail. + destroyTrie(); + + // Count the number of destructor calls during `destroyTrie()`. + ASSERT_EQ(DestructorCalled, MaxN); +} + +using NumStrNodeTrieTest = SimpleTrieHashMapTest; + +TEST_F(NumStrNodeTrieTest, TrieInsertLazy) { + for (unsigned RootBits : {2, 3, 6, 10}) { + for (unsigned SubtrieBits : {2, 3, 4}) { + auto &Trie = createTrie(RootBits, SubtrieBits); + for (int I = 0, E = 1000; I != E; ++I) { + TrieType::pointer Lookup; + HashType H = hash(I); + if (I & 1) + Lookup = Trie.find(H); + + auto insertNum = [&](uint64_t Num) { + std::string S = Twine(I).str(); + auto Hash = hash(Num); + return Trie.insertLazy( + Hash, [&](TrieType::LazyValueConstructor C) { C(std::move(S)); }); + }; + auto S1 = insertNum(I); + // The address of the Data should be the same. + EXPECT_EQ(&S1->Data, &insertNum(I)->Data); + + auto insertStr = [&](std::string S) { + int Num = std::stoi(S); + return insertNum(Num); + }; + std::string S2 = S1->Data; + // The address of the Data should be the same. + EXPECT_EQ(&S1->Data, &insertStr(S2)->Data); + } + for (int I = 0, E = 1000; I != E; ++I) { + std::string S = Twine(I).str(); + TrieType::pointer Lookup = Trie.find(hash(I)); + EXPECT_TRUE(Lookup); + if (!Lookup) + continue; + EXPECT_EQ(S, Lookup->Data); + } + } + } +} +} // end anonymous namespace diff --git a/llvm/unittests/CodeGen/AArch64SelectionDAGTest.cpp b/llvm/unittests/CodeGen/AArch64SelectionDAGTest.cpp index 3df72ec8115b6a..ffedb2c74220f0 100644 --- a/llvm/unittests/CodeGen/AArch64SelectionDAGTest.cpp +++ b/llvm/unittests/CodeGen/AArch64SelectionDAGTest.cpp @@ -6,6 +6,7 @@ // //===----------------------------------------------------------------------===// +#include "../lib/Target/AArch64/AArch64ISelLowering.h" #include "llvm/Analysis/MemoryLocation.h" #include "llvm/Analysis/OptimizationRemarkEmitter.h" #include "llvm/AsmParser/Parser.h" @@ -167,6 +168,18 @@ TEST_F(AArch64SelectionDAGTest, ComputeNumSignBits_EXTRACT_SUBVECTOR) { EXPECT_EQ(DAG->ComputeNumSignBits(Op, DemandedElts), 7u); } +TEST_F(AArch64SelectionDAGTest, ComputeNumSignBits_VASHR) { + SDLoc Loc; + auto VecVT = MVT::v8i8; + auto Shift = DAG->getConstant(4, Loc, MVT::i32); + auto Vec0 = DAG->getConstant(1, Loc, VecVT); + auto Op1 = DAG->getNode(AArch64ISD::VASHR, Loc, VecVT, Vec0, Shift); + EXPECT_EQ(DAG->ComputeNumSignBits(Op1), 8u); + auto VecA = DAG->getConstant(0xaa, Loc, VecVT); + auto Op2 = DAG->getNode(AArch64ISD::VASHR, Loc, VecVT, VecA, Shift); + EXPECT_EQ(DAG->ComputeNumSignBits(Op2), 5u); +} + TEST_F(AArch64SelectionDAGTest, SimplifyDemandedVectorElts_EXTRACT_SUBVECTOR) { TargetLowering TL(*TM); diff --git a/llvm/unittests/ExecutionEngine/Orc/ObjectLinkingLayerTest.cpp b/llvm/unittests/ExecutionEngine/Orc/ObjectLinkingLayerTest.cpp index 63cf3a397cb30d..bc996711f7ec50 100644 --- a/llvm/unittests/ExecutionEngine/Orc/ObjectLinkingLayerTest.cpp +++ b/llvm/unittests/ExecutionEngine/Orc/ObjectLinkingLayerTest.cpp @@ -65,6 +65,36 @@ TEST_F(ObjectLinkingLayerTest, AddLinkGraph) { EXPECT_THAT_EXPECTED(ES.lookup(&JD, "_X"), Succeeded()); } +TEST_F(ObjectLinkingLayerTest, ResourceTracker) { + // This test transfers allocations to previously unknown ResourceTrackers, + // while increasing the number of trackers in the ObjectLinkingLayer, which + // may invalidate some iterators internally. + std::vector Trackers; + for (unsigned I = 0; I < 64; I++) { + auto G = std::make_unique("foo", Triple("x86_64-apple-darwin"), + 8, llvm::endianness::little, + x86_64::getEdgeKindName); + + auto &Sec1 = G->createSection("__data", MemProt::Read | MemProt::Write); + auto &B1 = G->createContentBlock(Sec1, BlockContent, + orc::ExecutorAddr(0x1000), 8, 0); + llvm::SmallString<0> SymbolName; + SymbolName += "_X"; + SymbolName += std::to_string(I); + G->addDefinedSymbol(B1, 4, SymbolName, 4, Linkage::Strong, Scope::Default, + false, false); + + auto RT1 = JD.createResourceTracker(); + EXPECT_THAT_ERROR(ObjLinkingLayer.add(RT1, std::move(G)), Succeeded()); + EXPECT_THAT_EXPECTED(ES.lookup(&JD, SymbolName), Succeeded()); + + auto RT2 = JD.createResourceTracker(); + RT1->transferTo(*RT2); + + Trackers.push_back(RT2); + } +} + TEST_F(ObjectLinkingLayerTest, ClaimLateDefinedWeakSymbols) { // Check that claiming weak symbols works as expected. // diff --git a/llvm/unittests/IR/VerifierTest.cpp b/llvm/unittests/IR/VerifierTest.cpp index 91cd35a10e9b92..462578a34da837 100644 --- a/llvm/unittests/IR/VerifierTest.cpp +++ b/llvm/unittests/IR/VerifierTest.cpp @@ -385,5 +385,35 @@ TEST(VerifierTest, AtomicRMW) { << Error; } +TEST(VerifierTest, GetElementPtrInst) { + LLVMContext C; + Module M("M", C); + FunctionType *FTy = FunctionType::get(Type::getVoidTy(C), /*isVarArg=*/false); + Function *F = Function::Create(FTy, Function::ExternalLinkage, "foo", M); + BasicBlock *Entry = BasicBlock::Create(C, "entry", F); + ReturnInst *RI = ReturnInst::Create(C, Entry); + + FixedVectorType *V2P1Ty = FixedVectorType::get(PointerType::get(C, 1), 2); + FixedVectorType *V2P2Ty = FixedVectorType::get(PointerType::get(C, 2), 2); + + Instruction *GEPVec = GetElementPtrInst::Create( + Type::getInt8Ty(C), ConstantAggregateZero::get(V2P1Ty), + {ConstantVector::getSplat(ElementCount::getFixed(2), + ConstantInt::get(Type::getInt64Ty(C), 0))}, + Entry); + + GEPVec->insertBefore(RI); + + // Break the address space of the source value + GEPVec->getOperandUse(0).set(ConstantAggregateZero::get(V2P2Ty)); + + std::string Error; + raw_string_ostream ErrorOS(Error); + EXPECT_TRUE(verifyFunction(*F, &ErrorOS)); + EXPECT_TRUE( + StringRef(Error).starts_with("GEP address space doesn't match type")) + << Error; +} + } // end anonymous namespace } // end namespace llvm diff --git a/llvm/unittests/SandboxIR/SandboxIRTest.cpp b/llvm/unittests/SandboxIR/SandboxIRTest.cpp index 97113b303f72e5..874c32c2d4398f 100644 --- a/llvm/unittests/SandboxIR/SandboxIRTest.cpp +++ b/llvm/unittests/SandboxIR/SandboxIRTest.cpp @@ -21,7 +21,7 @@ #include "llvm/SandboxIR/Utils.h" #include "llvm/SandboxIR/Value.h" #include "llvm/Support/SourceMgr.h" -#include "gmock/gmock-matchers.h" +#include "gmock/gmock.h" #include "gtest/gtest.h" using namespace llvm; @@ -5962,3 +5962,100 @@ TEST_F(SandboxIRTest, CheckClassof) { EXPECT_NE(&sandboxir::CLASS::classof, &sandboxir::Instruction::classof); #include "llvm/SandboxIR/Values.def" } + +TEST_F(SandboxIRTest, InstructionCallbacks) { + parseIR(C, R"IR( + define void @foo(ptr %ptr, i8 %val) { + ret void + } + )IR"); + Function &LLVMF = *M->getFunction("foo"); + sandboxir::Context Ctx(C); + + auto &F = *Ctx.createFunction(&LLVMF); + auto &BB = *F.begin(); + sandboxir::Argument *Ptr = F.getArg(0); + sandboxir::Argument *Val = F.getArg(1); + sandboxir::Instruction *Ret = &BB.front(); + + SmallVector Inserted; + auto InsertCbId = Ctx.registerCreateInstrCallback( + [&Inserted](sandboxir::Instruction *I) { Inserted.push_back(I); }); + + SmallVector Removed; + auto RemoveCbId = Ctx.registerEraseInstrCallback( + [&Removed](sandboxir::Instruction *I) { Removed.push_back(I); }); + + // Keep the moved instruction and the instruction pointed by the Where + // iterator so we can check both callback arguments work as expected. + SmallVector> + Moved; + auto MoveCbId = Ctx.registerMoveInstrCallback( + [&Moved](sandboxir::Instruction *I, const sandboxir::BBIterator &Where) { + // Use a nullptr to signal "move to end" to keep it single. We only + // have a basic block in this test case anyway. + if (Where == Where.getNodeParent()->end()) + Moved.push_back(std::make_pair(I, nullptr)); + else + Moved.push_back(std::make_pair(I, &*Where)); + }); + + // Two more insertion callbacks, to check that they're called in registration + // order. + SmallVector Order; + auto CheckOrderInsertCbId1 = Ctx.registerCreateInstrCallback( + [&Order](sandboxir::Instruction *I) { Order.push_back(1); }); + + auto CheckOrderInsertCbId2 = Ctx.registerCreateInstrCallback( + [&Order](sandboxir::Instruction *I) { Order.push_back(2); }); + + Ctx.save(); + auto *NewI = sandboxir::StoreInst::create(Val, Ptr, /*Align=*/std::nullopt, + Ret->getIterator(), Ctx); + EXPECT_THAT(Inserted, testing::ElementsAre(NewI)); + EXPECT_THAT(Removed, testing::IsEmpty()); + EXPECT_THAT(Moved, testing::IsEmpty()); + EXPECT_THAT(Order, testing::ElementsAre(1, 2)); + + Ret->moveBefore(NewI); + EXPECT_THAT(Inserted, testing::ElementsAre(NewI)); + EXPECT_THAT(Removed, testing::IsEmpty()); + EXPECT_THAT(Moved, testing::ElementsAre(std::make_pair(Ret, NewI))); + + Ret->eraseFromParent(); + EXPECT_THAT(Inserted, testing::ElementsAre(NewI)); + EXPECT_THAT(Removed, testing::ElementsAre(Ret)); + EXPECT_THAT(Moved, testing::ElementsAre(std::make_pair(Ret, NewI))); + + NewI->eraseFromParent(); + EXPECT_THAT(Inserted, testing::ElementsAre(NewI)); + EXPECT_THAT(Removed, testing::ElementsAre(Ret, NewI)); + EXPECT_THAT(Moved, testing::ElementsAre(std::make_pair(Ret, NewI))); + + // Check that after revert the callbacks have been called for the inverse + // operations of the changes made so far. + Ctx.revert(); + EXPECT_THAT(Inserted, testing::ElementsAre(NewI, NewI, Ret)); + EXPECT_THAT(Removed, testing::ElementsAre(Ret, NewI, NewI)); + EXPECT_THAT(Moved, testing::ElementsAre(std::make_pair(Ret, NewI), + std::make_pair(Ret, nullptr))); + EXPECT_THAT(Order, testing::ElementsAre(1, 2, 1, 2, 1, 2)); + + // Check that deregistration works. Do an operation of each type after + // deregistering callbacks and check. + Inserted.clear(); + Removed.clear(); + Moved.clear(); + Ctx.unregisterCreateInstrCallback(InsertCbId); + Ctx.unregisterEraseInstrCallback(RemoveCbId); + Ctx.unregisterMoveInstrCallback(MoveCbId); + Ctx.unregisterCreateInstrCallback(CheckOrderInsertCbId1); + Ctx.unregisterCreateInstrCallback(CheckOrderInsertCbId2); + auto *NewI2 = sandboxir::StoreInst::create(Val, Ptr, /*Align=*/std::nullopt, + Ret->getIterator(), Ctx); + Ret->moveBefore(NewI2); + Ret->eraseFromParent(); + EXPECT_THAT(Inserted, testing::IsEmpty()); + EXPECT_THAT(Removed, testing::IsEmpty()); + EXPECT_THAT(Moved, testing::IsEmpty()); +} diff --git a/llvm/unittests/Target/AMDGPU/CMakeLists.txt b/llvm/unittests/Target/AMDGPU/CMakeLists.txt index e0efb967b5941d..ca8f48bc393efd 100644 --- a/llvm/unittests/Target/AMDGPU/CMakeLists.txt +++ b/llvm/unittests/Target/AMDGPU/CMakeLists.txt @@ -11,6 +11,7 @@ set(LLVM_LINK_COMPONENTS CodeGen CodeGenTypes Core + GlobalISel MC Support TargetParser @@ -18,6 +19,7 @@ set(LLVM_LINK_COMPONENTS add_llvm_target_unittest(AMDGPUTests AMDGPUUnitTests.cpp + CSETest.cpp DwarfRegMappings.cpp ExecMayBeModifiedBeforeAnyUse.cpp PALMetadata.cpp diff --git a/llvm/unittests/Target/AMDGPU/CSETest.cpp b/llvm/unittests/Target/AMDGPU/CSETest.cpp new file mode 100644 index 00000000000000..3de5b88599649a --- /dev/null +++ b/llvm/unittests/Target/AMDGPU/CSETest.cpp @@ -0,0 +1,74 @@ +//===- llvm/unittests/Target/AMDGPU/CSETest.cpp ---------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +#include "AMDGPUTargetMachine.h" +#include "AMDGPUUnitTests.h" +#include "llvm/CodeGen/GlobalISel/CSEInfo.h" +#include "llvm/CodeGen/GlobalISel/CSEMIRBuilder.h" +#include "gtest/gtest.h" + +using namespace llvm; + +TEST(AMDGPU, TestCSEForRegisterClassOrBankAndLLT) { + auto TM = createAMDGPUTargetMachine("amdgcn-amd-", "gfx1100", ""); + if (!TM) + GTEST_SKIP(); + + GCNSubtarget ST(TM->getTargetTriple(), std::string(TM->getTargetCPU()), + std::string(TM->getTargetFeatureString()), *TM); + + LLVMContext Ctx; + Module Mod("Module", Ctx); + Mod.setDataLayout(TM->createDataLayout()); + + auto *Type = FunctionType::get(Type::getVoidTy(Ctx), false); + auto *F = Function::Create(Type, GlobalValue::ExternalLinkage, "Test", &Mod); + + MachineModuleInfo MMI(TM.get()); + auto MF = + std::make_unique(*F, *TM, ST, MMI.getContext(), 42); + auto *BB = MF->CreateMachineBasicBlock(); + MF->push_back(BB); + + MachineIRBuilder B(*MF); + B.setMBB(*BB); + + LLT S32{LLT::scalar(32)}; + Register R0 = B.buildCopy(S32, Register(AMDGPU::SGPR0)).getReg(0); + Register R1 = B.buildCopy(S32, Register(AMDGPU::SGPR1)).getReg(0); + + GISelCSEInfo CSEInfo; + CSEInfo.setCSEConfig(std::make_unique()); + CSEInfo.analyze(*MF); + B.setCSEInfo(&CSEInfo); + CSEMIRBuilder CSEB(B.getState()); + CSEB.setInsertPt(B.getMBB(), B.getInsertPt()); + + const RegisterBankInfo &RBI = *MF->getSubtarget().getRegBankInfo(); + + const TargetRegisterClass *SgprRC = &AMDGPU::SReg_32RegClass; + const RegisterBank *SgprRB = &RBI.getRegBank(AMDGPU::SGPRRegBankID); + MachineRegisterInfo::VRegAttrs SgprRCS32 = {SgprRC, S32}; + MachineRegisterInfo::VRegAttrs SgprRBS32 = {SgprRB, S32}; + + auto Add = CSEB.buildAdd(S32, R0, R1); + auto AddRC = CSEB.buildInstr(AMDGPU::G_ADD, {SgprRCS32}, {R0, R1}); + auto AddRB = CSEB.buildInstr(AMDGPU::G_ADD, {{SgprRB, S32}}, {R0, R1}); + + EXPECT_NE(Add, AddRC); + EXPECT_NE(Add, AddRB); + EXPECT_NE(AddRC, AddRB); + + auto Add_CSE = CSEB.buildAdd(S32, R0, R1); + auto AddRC_CSE = CSEB.buildInstr(AMDGPU::G_ADD, {{SgprRC, S32}}, {R0, R1}); + auto AddRB_CSE = CSEB.buildInstr(AMDGPU::G_ADD, {SgprRBS32}, {R0, R1}); + + EXPECT_EQ(Add, Add_CSE); + EXPECT_EQ(AddRC, AddRC_CSE); + EXPECT_EQ(AddRB, AddRB_CSE); +} diff --git a/llvm/unittests/TargetParser/RISCVISAInfoTest.cpp b/llvm/unittests/TargetParser/RISCVISAInfoTest.cpp index a1d493e12fda6d..30f80601d96cbb 100644 --- a/llvm/unittests/TargetParser/RISCVISAInfoTest.cpp +++ b/llvm/unittests/TargetParser/RISCVISAInfoTest.cpp @@ -643,60 +643,22 @@ TEST(ParseArchString, MissingDepency) { "'zvl*b' requires 'v' or 'zve*' extension to also be specified"); } - for (StringRef Input : {"rv32i_zvbb"}) { + // These all have an implication relationship, thus should pass + for (StringRef Input : { + "rv32i_zvbb", + "rv32i_zvbc32e0p7", + "rv32i_zvbc", + "rv32i_zvkb", + "rv32i_zvkg", + "rv32i_zvkgs0p7", + "rv32i_zvkned", + "rv32i_zvknha", + "rv32i_zvksed", + "rv32i_zvksh", + "rv32i_zvknhb", + }) { EXPECT_EQ(toString(RISCVISAInfo::parseArchString(Input, true).takeError()), - "'zvbb' requires 'v' or 'zve*' extension to also be specified"); - } - - for (StringRef Input : {"rv32i_zvbc32e0p7"}) { - EXPECT_EQ(toString(RISCVISAInfo::parseArchString(Input, true).takeError()), - "'zvbc32e' requires 'v' or 'zve*' extension to also be specified"); - } - - for (StringRef Input : {"rv32i_zvbc"}) { - EXPECT_EQ(toString(RISCVISAInfo::parseArchString(Input, true).takeError()), - "'zvbc' requires 'v' or 'zve64*' extension to also be specified"); - } - - for (StringRef Input : {"rv32i_zvkb"}) { - EXPECT_EQ(toString(RISCVISAInfo::parseArchString(Input, true).takeError()), - "'zvkb' requires 'v' or 'zve*' extension to also be specified"); - } - - for (StringRef Input : {"rv32i_zvkg"}) { - EXPECT_EQ(toString(RISCVISAInfo::parseArchString(Input, true).takeError()), - "'zvkg' requires 'v' or 'zve*' extension to also be specified"); - } - - for (StringRef Input : {"rv32i_zvkgs0p7"}) { - EXPECT_EQ(toString(RISCVISAInfo::parseArchString(Input, true).takeError()), - "'zvkg' requires 'v' or 'zve*' extension to also be specified"); - } - - for (StringRef Input : {"rv32i_zvkned"}) { - EXPECT_EQ(toString(RISCVISAInfo::parseArchString(Input, true).takeError()), - "'zvkned' requires 'v' or 'zve*' extension to also be specified"); - } - - for (StringRef Input : {"rv32i_zvknha"}) { - EXPECT_EQ(toString(RISCVISAInfo::parseArchString(Input, true).takeError()), - "'zvknha' requires 'v' or 'zve*' extension to also be specified"); - } - - for (StringRef Input : {"rv32i_zvksed"}) { - EXPECT_EQ(toString(RISCVISAInfo::parseArchString(Input, true).takeError()), - "'zvksed' requires 'v' or 'zve*' extension to also be specified"); - } - - for (StringRef Input : {"rv32i_zvksh"}) { - EXPECT_EQ(toString(RISCVISAInfo::parseArchString(Input, true).takeError()), - "'zvksh' requires 'v' or 'zve*' extension to also be specified"); - } - - for (StringRef Input : {"rv32i_zvknhb"}) { - EXPECT_EQ( - toString(RISCVISAInfo::parseArchString(Input, true).takeError()), - "'zvknhb' requires 'v' or 'zve64*' extension to also be specified"); + ""); } for (StringRef Input : {"rv32i_zacas1p0"}) { diff --git a/llvm/unittests/Transforms/Vectorize/SandboxVectorizer/LegalityTest.cpp b/llvm/unittests/Transforms/Vectorize/SandboxVectorizer/LegalityTest.cpp index aaa8e96de6d171..50b78f6f48afdf 100644 --- a/llvm/unittests/Transforms/Vectorize/SandboxVectorizer/LegalityTest.cpp +++ b/llvm/unittests/Transforms/Vectorize/SandboxVectorizer/LegalityTest.cpp @@ -29,7 +29,7 @@ struct LegalityTest : public testing::Test { TEST_F(LegalityTest, Legality) { parseIR(C, R"IR( -define void @foo(ptr %ptr, <2 x float> %vec2, <3 x float> %vec3, i8 %arg, float %farg0, float %farg1) { +define void @foo(ptr %ptr, <2 x float> %vec2, <3 x float> %vec3, i8 %arg, float %farg0, float %farg1, i64 %v0, i64 %v1) { %gep0 = getelementptr float, ptr %ptr, i32 0 %gep1 = getelementptr float, ptr %ptr, i32 1 %gep3 = getelementptr float, ptr %ptr, i32 3 @@ -42,6 +42,8 @@ define void @foo(ptr %ptr, <2 x float> %vec2, <3 x float> %vec3, i8 %arg, float store i8 %arg, ptr %gep1 %fadd0 = fadd float %farg0, %farg0 %fadd1 = fadd fast float %farg1, %farg1 + %trunc0 = trunc nuw nsw i64 %v0 to i8 + %trunc1 = trunc nsw i64 %v1 to i8 ret void } )IR"); @@ -62,6 +64,8 @@ define void @foo(ptr %ptr, <2 x float> %vec2, <3 x float> %vec3, i8 %arg, float auto *StI8 = cast(&*It++); auto *FAdd0 = cast(&*It++); auto *FAdd1 = cast(&*It++); + auto *Trunc0 = cast(&*It++); + auto *Trunc1 = cast(&*It++); sandboxir::LegalityAnalysis Legality; const auto &Result = Legality.canVectorize({St0, St1}); @@ -98,6 +102,13 @@ define void @foo(ptr %ptr, <2 x float> %vec2, <3 x float> %vec3, i8 %arg, float EXPECT_EQ(cast(Result).getReason(), sandboxir::ResultReason::DiffMathFlags); } + { + // Check DiffWrapFlags + const auto &Result = Legality.canVectorize({Trunc0, Trunc1}); + EXPECT_TRUE(isa(Result)); + EXPECT_EQ(cast(Result).getReason(), + sandboxir::ResultReason::DiffWrapFlags); + } } #ifndef NDEBUG @@ -124,5 +135,8 @@ TEST_F(LegalityTest, LegalityResultDump) { EXPECT_TRUE(Matches(Legality.createLegalityResult( sandboxir::ResultReason::DiffMathFlags), "Pack Reason: DiffMathFlags")); + EXPECT_TRUE(Matches(Legality.createLegalityResult( + sandboxir::ResultReason::DiffWrapFlags), + "Pack Reason: DiffWrapFlags")); } #endif // NDEBUG diff --git a/llvm/utils/TableGen/ARMTargetDefEmitter.cpp b/llvm/utils/TableGen/ARMTargetDefEmitter.cpp index 6b8ebf96cdf383..792d047139466c 100644 --- a/llvm/utils/TableGen/ARMTargetDefEmitter.cpp +++ b/llvm/utils/TableGen/ARMTargetDefEmitter.cpp @@ -25,19 +25,19 @@ using namespace llvm; /// Collect the full set of implied features for a SubtargetFeature. -static void CollectImpliedFeatures(std::set &SeenFeats, +static void collectImpliedFeatures(std::set &SeenFeats, const Record *Rec) { assert(Rec->isSubClassOf("SubtargetFeature") && "Rec is not a SubtargetFeature"); SeenFeats.insert(Rec); for (const Record *Implied : Rec->getValueAsListOfDefs("Implies")) - CollectImpliedFeatures(SeenFeats, Implied); + collectImpliedFeatures(SeenFeats, Implied); } -static void CheckFeatureTree(const Record *Root) { +static void checkFeatureTree(const Record *Root) { std::set SeenFeats; - CollectImpliedFeatures(SeenFeats, Root); + collectImpliedFeatures(SeenFeats, Root); // Check that each of the mandatory (implied) features which is an // ExtensionWithMArch is also enabled by default. @@ -53,12 +53,12 @@ static void CheckFeatureTree(const Record *Root) { } } -static void EmitARMTargetDef(const RecordKeeper &RK, raw_ostream &OS) { +static void emitARMTargetDef(const RecordKeeper &RK, raw_ostream &OS) { OS << "// Autogenerated by ARMTargetDefEmitter.cpp\n\n"; // Look through all SubtargetFeature defs with the given FieldName, and // collect the set of all Values that that FieldName is set to. - auto gatherSubtargetFeatureFieldValues = [&RK](StringRef FieldName) { + auto GatherSubtargetFeatureFieldValues = [&RK](StringRef FieldName) { llvm::StringSet<> Set; for (const Record *Rec : RK.getAllDerivedDefinitions("SubtargetFeature")) { if (Rec->getValueAsString("FieldName") == FieldName) { @@ -88,7 +88,7 @@ static void EmitARMTargetDef(const RecordKeeper &RK, raw_ostream &OS) { << "#define ARM_PROCESSOR_FAMILY(ENUM)\n" << "#endif\n\n"; const StringSet<> ARMProcFamilyVals = - gatherSubtargetFeatureFieldValues("ARMProcFamily"); + GatherSubtargetFeatureFieldValues("ARMProcFamily"); for (const StringRef &Family : ARMProcFamilyVals.keys()) OS << "ARM_PROCESSOR_FAMILY(" << Family << ")\n"; OS << "\n#undef ARM_PROCESSOR_FAMILY\n\n"; @@ -97,7 +97,7 @@ static void EmitARMTargetDef(const RecordKeeper &RK, raw_ostream &OS) { << "#define ARM_ARCHITECTURE(ENUM)\n" << "#endif\n\n"; // This should correspond to instances of the Architecture tablegen class. - const StringSet<> ARMArchVals = gatherSubtargetFeatureFieldValues("ARMArch"); + const StringSet<> ARMArchVals = GatherSubtargetFeatureFieldValues("ARMArch"); for (const StringRef &Arch : ARMArchVals.keys()) OS << "ARM_ARCHITECTURE(" << Arch << ")\n"; OS << "\n#undef ARM_ARCHITECTURE\n\n"; @@ -315,7 +315,7 @@ static void EmitARMTargetDef(const RecordKeeper &RK, raw_ostream &OS) { auto Profile = Arch->getValueAsString("Profile"); auto ArchInfo = ArchInfoName(Major, Minor, Profile); - CheckFeatureTree(Arch); + checkFeatureTree(Arch); OS << " {\n" << " \"" << Name << "\",\n" @@ -343,5 +343,5 @@ static void EmitARMTargetDef(const RecordKeeper &RK, raw_ostream &OS) { } static TableGen::Emitter::Opt - X("gen-arm-target-def", EmitARMTargetDef, + X("gen-arm-target-def", emitARMTargetDef, "Generate the ARM or AArch64 Architecture information header."); diff --git a/llvm/utils/TableGen/CallingConvEmitter.cpp b/llvm/utils/TableGen/CallingConvEmitter.cpp index c8f263e15d96b7..de20303a5bfd20 100644 --- a/llvm/utils/TableGen/CallingConvEmitter.cpp +++ b/llvm/utils/TableGen/CallingConvEmitter.cpp @@ -35,12 +35,12 @@ class CallingConvEmitter { public: explicit CallingConvEmitter(const RecordKeeper &R) : Records(R) {} - void run(raw_ostream &o); + void run(raw_ostream &O); private: - void EmitCallingConv(const Record *CC, raw_ostream &O); - void EmitAction(const Record *Action, indent Indent, raw_ostream &O); - void EmitArgRegisterLists(raw_ostream &O); + void emitCallingConv(const Record *CC, raw_ostream &O); + void emitAction(const Record *Action, indent Indent, raw_ostream &O); + void emitArgRegisterLists(raw_ostream &O); }; } // End anonymous namespace @@ -75,16 +75,16 @@ void CallingConvEmitter::run(raw_ostream &O) { Records.getTimer().startTimer("Emit full descriptions"); for (const Record *CC : CCs) { if (!CC->getValueAsBit("Custom")) { - EmitCallingConv(CC, O); + emitCallingConv(CC, O); } } - EmitArgRegisterLists(O); + emitArgRegisterLists(O); O << "\n#endif // CC_REGISTER_LIST\n"; } -void CallingConvEmitter::EmitCallingConv(const Record *CC, raw_ostream &O) { +void CallingConvEmitter::emitCallingConv(const Record *CC, raw_ostream &O) { const ListInit *CCActions = CC->getValueAsListInit("Actions"); Counter = 0; @@ -107,8 +107,8 @@ void CallingConvEmitter::EmitCallingConv(const Record *CC, raw_ostream &O) { << std::string(Pad, ' ') << "MVT LocVT, CCValAssign::LocInfo LocInfo,\n" << std::string(Pad, ' ') << "ISD::ArgFlagsTy ArgFlags, CCState &State) {\n"; // Emit all of the actions, in order. - for (unsigned i = 0, e = CCActions->size(); i != e; ++i) { - const Record *Action = CCActions->getElementAsRecord(i); + for (unsigned I = 0, E = CCActions->size(); I != E; ++I) { + const Record *Action = CCActions->getElementAsRecord(I); SwiftAction = llvm::any_of(Action->getSuperClasses(), [](const std::pair &Class) { @@ -117,23 +117,23 @@ void CallingConvEmitter::EmitCallingConv(const Record *CC, raw_ostream &O) { }); O << "\n"; - EmitAction(Action, indent(2), O); + emitAction(Action, indent(2), O); } O << "\n return true; // CC didn't match.\n"; O << "}\n"; } -void CallingConvEmitter::EmitAction(const Record *Action, indent Indent, +void CallingConvEmitter::emitAction(const Record *Action, indent Indent, raw_ostream &O) { if (Action->isSubClassOf("CCPredicateAction")) { O << Indent << "if ("; if (Action->isSubClassOf("CCIfType")) { const ListInit *VTs = Action->getValueAsListInit("VTs"); - for (unsigned i = 0, e = VTs->size(); i != e; ++i) { - const Record *VT = VTs->getElementAsRecord(i); - if (i != 0) + for (unsigned I = 0, E = VTs->size(); I != E; ++I) { + const Record *VT = VTs->getElementAsRecord(I); + if (I != 0) O << " ||\n " << Indent; O << "LocVT == " << getEnumName(getValueType(VT)); } @@ -146,7 +146,7 @@ void CallingConvEmitter::EmitAction(const Record *Action, indent Indent, } O << ") {\n"; - EmitAction(Action->getValueAsDef("SubAction"), Indent + 2, O); + emitAction(Action->getValueAsDef("SubAction"), Indent + 2, O); O << Indent << "}\n"; } else { if (Action->isSubClassOf("CCDelegateTo")) { @@ -171,8 +171,8 @@ void CallingConvEmitter::EmitAction(const Record *Action, indent Indent, << "[] = {\n"; O << Indent << " "; ListSeparator LS; - for (unsigned i = 0, e = RegList->size(); i != e; ++i) { - std::string Name = getQualifiedName(RegList->getElementAsRecord(i)); + for (unsigned I = 0, E = RegList->size(); I != E; ++I) { + std::string Name = getQualifiedName(RegList->getElementAsRecord(I)); if (SwiftAction) AssignedSwiftRegsMap[CurrentAction].insert(Name); else @@ -230,16 +230,16 @@ void CallingConvEmitter::EmitAction(const Record *Action, indent Indent, << "[] = {\n"; O << Indent << " "; ListSeparator LS; - for (unsigned i = 0, e = RegList->size(); i != e; ++i) - O << LS << getQualifiedName(RegList->getElementAsRecord(i)); + for (unsigned I = 0, E = RegList->size(); I != E; ++I) + O << LS << getQualifiedName(RegList->getElementAsRecord(I)); O << "\n" << Indent << "};\n"; O << Indent << "static const MCPhysReg RegList" << ShadowRegListNumber << "[] = {\n"; O << Indent << " "; ListSeparator LSS; - for (unsigned i = 0, e = ShadowRegList->size(); i != e; ++i) - O << LSS << getQualifiedName(ShadowRegList->getElementAsRecord(i)); + for (unsigned I = 0, E = ShadowRegList->size(); I != E; ++I) + O << LSS << getQualifiedName(ShadowRegList->getElementAsRecord(I)); O << "\n" << Indent << "};\n"; O << Indent << "if (MCRegister Reg = State.AllocateReg(RegList" @@ -287,8 +287,8 @@ void CallingConvEmitter::EmitAction(const Record *Action, indent Indent, << ShadowRegListNumber << "[] = {\n"; O << Indent << " "; ListSeparator LS; - for (unsigned i = 0, e = ShadowRegList->size(); i != e; ++i) - O << LS << getQualifiedName(ShadowRegList->getElementAsRecord(i)); + for (unsigned I = 0, E = ShadowRegList->size(); I != E; ++I) + O << LS << getQualifiedName(ShadowRegList->getElementAsRecord(I)); O << "\n" << Indent << "};\n"; O << Indent << "int64_t Offset" << ++Counter << " = State.AllocateStack(" @@ -357,7 +357,7 @@ void CallingConvEmitter::EmitAction(const Record *Action, indent Indent, } } -void CallingConvEmitter::EmitArgRegisterLists(raw_ostream &O) { +void CallingConvEmitter::emitArgRegisterLists(raw_ostream &O) { // Transitively merge all delegated CCs into AssignedRegsMap. using EntryTy = std::pair>; bool Redo; diff --git a/llvm/utils/TableGen/CodeEmitterGen.cpp b/llvm/utils/TableGen/CodeEmitterGen.cpp index be822c4815289c..407ee81b7e0b6c 100644 --- a/llvm/utils/TableGen/CodeEmitterGen.cpp +++ b/llvm/utils/TableGen/CodeEmitterGen.cpp @@ -52,10 +52,10 @@ class CodeEmitterGen { public: CodeEmitterGen(const RecordKeeper &R) : Records(R) {} - void run(raw_ostream &o); + void run(raw_ostream &O); private: - int getVariableBit(const std::string &VarName, const BitsInit *BI, int bit); + int getVariableBit(const std::string &VarName, const BitsInit *BI, int Bit); std::pair getInstructionCases(const Record *R, const CodeGenTarget &Target); void addInstructionCasesForEncoding(const Record *R, @@ -69,10 +69,10 @@ class CodeEmitterGen { const CodeGenTarget &Target); void emitInstructionBaseValues( - raw_ostream &o, ArrayRef NumberedInstructions, + raw_ostream &O, ArrayRef NumberedInstructions, const CodeGenTarget &Target, unsigned HwMode = DefaultMode); void - emitCaseMap(raw_ostream &o, + emitCaseMap(raw_ostream &O, const std::map> &CaseMap); unsigned BitWidth = 0u; bool UseAPInt = false; @@ -81,12 +81,12 @@ class CodeEmitterGen { // If the VarBitInit at position 'bit' matches the specified variable then // return the variable bit position. Otherwise return -1. int CodeEmitterGen::getVariableBit(const std::string &VarName, - const BitsInit *BI, int bit) { - if (const VarBitInit *VBI = dyn_cast(BI->getBit(bit))) { + const BitsInit *BI, int Bit) { + if (const VarBitInit *VBI = dyn_cast(BI->getBit(Bit))) { if (const VarInit *VI = dyn_cast(VBI->getBitVar())) if (VI->getName() == VarName) return VBI->getBitNum(); - } else if (const VarInit *VI = dyn_cast(BI->getBit(bit))) { + } else if (const VarInit *VI = dyn_cast(BI->getBit(Bit))) { if (VI->getName() == VarName) return 0; } @@ -104,19 +104,19 @@ bool CodeEmitterGen::addCodeToMergeInOperand(const Record *R, CodeGenInstruction &CGI = Target.getInstruction(R); // Determine if VarName actually contributes to the Inst encoding. - int bit = BI->getNumBits() - 1; + int Bit = BI->getNumBits() - 1; // Scan for a bit that this contributed to. - for (; bit >= 0;) { - if (getVariableBit(VarName, BI, bit) != -1) + for (; Bit >= 0;) { + if (getVariableBit(VarName, BI, Bit) != -1) break; - --bit; + --Bit; } // If we found no bits, ignore this value, otherwise emit the call to get the // operand encoding. - if (bit < 0) + if (Bit < 0) return true; // If the operand matches by name, reference according to that @@ -175,97 +175,97 @@ bool CodeEmitterGen::addCodeToMergeInOperand(const Record *R, // Precalculate the number of lits this variable contributes to in the // operand. If there is a single lit (consecutive range of bits) we can use a // destructive sequence on APInt that reduces memory allocations. - int numOperandLits = 0; - for (int tmpBit = bit; tmpBit >= 0;) { - int varBit = getVariableBit(VarName, BI, tmpBit); + int NumOperandLits = 0; + for (int TmpBit = Bit; TmpBit >= 0;) { + int VarBit = getVariableBit(VarName, BI, TmpBit); // If this bit isn't from a variable, skip it. - if (varBit == -1) { - --tmpBit; + if (VarBit == -1) { + --TmpBit; continue; } // Figure out the consecutive range of bits covered by this operand, in // order to generate better encoding code. - int beginVarBit = varBit; + int BeginVarBit = VarBit; int N = 1; - for (--tmpBit; tmpBit >= 0;) { - varBit = getVariableBit(VarName, BI, tmpBit); - if (varBit == -1 || varBit != (beginVarBit - N)) + for (--TmpBit; TmpBit >= 0;) { + VarBit = getVariableBit(VarName, BI, TmpBit); + if (VarBit == -1 || VarBit != (BeginVarBit - N)) break; ++N; - --tmpBit; + --TmpBit; } - ++numOperandLits; + ++NumOperandLits; } unsigned BitOffset = -1; - for (; bit >= 0;) { - int varBit = getVariableBit(VarName, BI, bit); + for (; Bit >= 0;) { + int VarBit = getVariableBit(VarName, BI, Bit); // If this bit isn't from a variable, skip it. - if (varBit == -1) { - --bit; + if (VarBit == -1) { + --Bit; continue; } // Figure out the consecutive range of bits covered by this operand, in // order to generate better encoding code. - int beginInstBit = bit; - int beginVarBit = varBit; + int BeginInstBit = Bit; + int BeginVarBit = VarBit; int N = 1; - for (--bit; bit >= 0;) { - varBit = getVariableBit(VarName, BI, bit); - if (varBit == -1 || varBit != (beginVarBit - N)) + for (--Bit; Bit >= 0;) { + VarBit = getVariableBit(VarName, BI, Bit); + if (VarBit == -1 || VarBit != (BeginVarBit - N)) break; ++N; - --bit; + --Bit; } - std::string maskStr; - int opShift; + std::string MaskStr; + int OpShift; - unsigned loBit = beginVarBit - N + 1; - unsigned hiBit = loBit + N; - unsigned loInstBit = beginInstBit - N + 1; - BitOffset = loInstBit; + unsigned LoBit = BeginVarBit - N + 1; + unsigned HiBit = LoBit + N; + unsigned LoInstBit = BeginInstBit - N + 1; + BitOffset = LoInstBit; if (UseAPInt) { - std::string extractStr; + std::string ExtractStr; if (N >= 64) { - extractStr = "op.extractBits(" + itostr(hiBit - loBit) + ", " + - itostr(loBit) + ")"; - Case += " Value.insertBits(" + extractStr + ", " + - itostr(loInstBit) + ");\n"; + ExtractStr = "op.extractBits(" + itostr(HiBit - LoBit) + ", " + + itostr(LoBit) + ")"; + Case += " Value.insertBits(" + ExtractStr + ", " + + itostr(LoInstBit) + ");\n"; } else { - extractStr = "op.extractBitsAsZExtValue(" + itostr(hiBit - loBit) + - ", " + itostr(loBit) + ")"; - Case += " Value.insertBits(" + extractStr + ", " + - itostr(loInstBit) + ", " + itostr(hiBit - loBit) + ");\n"; + ExtractStr = "op.extractBitsAsZExtValue(" + itostr(HiBit - LoBit) + + ", " + itostr(LoBit) + ")"; + Case += " Value.insertBits(" + ExtractStr + ", " + + itostr(LoInstBit) + ", " + itostr(HiBit - LoBit) + ");\n"; } } else { - uint64_t opMask = ~(uint64_t)0 >> (64 - N); - opShift = beginVarBit - N + 1; - opMask <<= opShift; - maskStr = "UINT64_C(" + utostr(opMask) + ")"; - opShift = beginInstBit - beginVarBit; - - if (numOperandLits == 1) { - Case += " op &= " + maskStr + ";\n"; - if (opShift > 0) { - Case += " op <<= " + itostr(opShift) + ";\n"; - } else if (opShift < 0) { - Case += " op >>= " + itostr(-opShift) + ";\n"; + uint64_t OpMask = ~(uint64_t)0 >> (64 - N); + OpShift = BeginVarBit - N + 1; + OpMask <<= OpShift; + MaskStr = "UINT64_C(" + utostr(OpMask) + ")"; + OpShift = BeginInstBit - BeginVarBit; + + if (NumOperandLits == 1) { + Case += " op &= " + MaskStr + ";\n"; + if (OpShift > 0) { + Case += " op <<= " + itostr(OpShift) + ";\n"; + } else if (OpShift < 0) { + Case += " op >>= " + itostr(-OpShift) + ";\n"; } Case += " Value |= op;\n"; } else { - if (opShift > 0) { - Case += " Value |= (op & " + maskStr + ") << " + - itostr(opShift) + ";\n"; - } else if (opShift < 0) { - Case += " Value |= (op & " + maskStr + ") >> " + - itostr(-opShift) + ";\n"; + if (OpShift > 0) { + Case += " Value |= (op & " + MaskStr + ") << " + + itostr(OpShift) + ";\n"; + } else if (OpShift < 0) { + Case += " Value |= (op & " + MaskStr + ") >> " + + itostr(-OpShift) + ";\n"; } else { - Case += " Value |= (op & " + maskStr + ");\n"; + Case += " Value |= (op & " + MaskStr + ");\n"; } } } @@ -285,7 +285,7 @@ CodeEmitterGen::getInstructionCases(const Record *R, const CodeGenTarget &Target) { std::string Case, BitOffsetCase; - auto append = [&](const std::string &S) { + auto Append = [&](const std::string &S) { Case += S; BitOffsetCase += S; }; @@ -298,7 +298,7 @@ CodeEmitterGen::getInstructionCases(const Record *R, // Invoke the interface to obtain the HwMode ID controlling the // EncodingInfo for the current subtarget. This interface will // mask off irrelevant HwMode IDs. - append(" unsigned HwMode = " + Append(" unsigned HwMode = " "STI.getHwMode(MCSubtargetInfo::HwMode_EncodingInfo);\n"); Case += " switch (HwMode) {\n"; Case += " default: llvm_unreachable(\"Unknown hardware mode!\"); " @@ -328,16 +328,16 @@ CodeEmitterGen::getInstructionCases(const Record *R, Case += " Value = InstBitsByHw[opcode];\n"; } - append(" switch (HwMode) {\n"); - append(" default: llvm_unreachable(\"Unhandled HwMode\");\n"); + Append(" switch (HwMode) {\n"); + Append(" default: llvm_unreachable(\"Unhandled HwMode\");\n"); for (auto &[ModeId, Encoding] : EBM) { - append(" case " + itostr(ModeId) + ": {\n"); + Append(" case " + itostr(ModeId) + ": {\n"); addInstructionCasesForEncoding(R, Encoding, Target, Case, BitOffsetCase); - append(" break;\n"); - append(" }\n"); + Append(" break;\n"); + Append(" }\n"); } - append(" }\n"); + Append(" }\n"); return std::pair(std::move(Case), std::move(BitOffsetCase)); } } @@ -397,13 +397,13 @@ static void emitInstBits(raw_ostream &OS, const APInt &Bits) { } void CodeEmitterGen::emitInstructionBaseValues( - raw_ostream &o, ArrayRef NumberedInstructions, + raw_ostream &O, ArrayRef NumberedInstructions, const CodeGenTarget &Target, unsigned HwMode) { const CodeGenHwModes &HWM = Target.getHwModes(); if (HwMode == DefaultMode) - o << " static const uint64_t InstBits[] = {\n"; + O << " static const uint64_t InstBits[] = {\n"; else - o << " static const uint64_t InstBits_" + O << " static const uint64_t InstBits_" << HWM.getModeName(HwMode, /*IncludeDefault=*/true) << "[] = {\n"; for (const CodeGenInstruction *CGI : NumberedInstructions) { @@ -411,9 +411,9 @@ void CodeEmitterGen::emitInstructionBaseValues( if (R->getValueAsString("Namespace") == "TargetOpcode" || R->getValueAsBit("isPseudo")) { - o << " "; - emitInstBits(o, APInt(BitWidth, 0)); - o << ",\n"; + O << " "; + emitInstBits(O, APInt(BitWidth, 0)); + O << ",\n"; continue; } @@ -427,9 +427,9 @@ void CodeEmitterGen::emitInstructionBaseValues( // If the HwMode does not match, then Encoding '0' // should be generated. APInt Value(BitWidth, 0); - o << " "; - emitInstBits(o, Value); - o << "," << '\t' << "// " << R->getName() << "\n"; + O << " "; + emitInstBits(O, Value); + O << "," << '\t' << "// " << R->getName() << "\n"; continue; } } @@ -438,37 +438,37 @@ void CodeEmitterGen::emitInstructionBaseValues( // Start by filling in fixed values. APInt Value(BitWidth, 0); - for (unsigned i = 0, e = BI->getNumBits(); i != e; ++i) { - if (const auto *B = dyn_cast(BI->getBit(i)); B && B->getValue()) - Value.setBit(i); + for (unsigned I = 0, E = BI->getNumBits(); I != E; ++I) { + if (const auto *B = dyn_cast(BI->getBit(I)); B && B->getValue()) + Value.setBit(I); } - o << " "; - emitInstBits(o, Value); - o << "," << '\t' << "// " << R->getName() << "\n"; + O << " "; + emitInstBits(O, Value); + O << "," << '\t' << "// " << R->getName() << "\n"; } - o << " UINT64_C(0)\n };\n"; + O << " UINT64_C(0)\n };\n"; } void CodeEmitterGen::emitCaseMap( - raw_ostream &o, + raw_ostream &O, const std::map> &CaseMap) { for (const auto &[Case, InstList] : CaseMap) { bool First = true; for (const auto &Inst : InstList) { if (!First) - o << "\n"; - o << " case " << Inst << ":"; + O << "\n"; + O << " case " << Inst << ":"; First = false; } - o << " {\n"; - o << Case; - o << " break;\n" + O << " {\n"; + O << Case; + O << " break;\n" << " }\n"; } } -void CodeEmitterGen::run(raw_ostream &o) { - emitSourceFileHeader("Machine Code Emitter", o); +void CodeEmitterGen::run(raw_ostream &O) { + emitSourceFileHeader("Machine Code Emitter", O); CodeGenTarget Target(Records); @@ -479,7 +479,7 @@ void CodeEmitterGen::run(raw_ostream &o) { Target.getInstructionsByEnumValue(); if (Target.hasVariableLengthEncodings()) { - emitVarLenCodeEmitter(Records, o); + emitVarLenCodeEmitter(Records, O); } else { const CodeGenHwModes &HWM = Target.getHwModes(); // The set of HwModes used by instruction encodings. @@ -509,31 +509,31 @@ void CodeEmitterGen::run(raw_ostream &o) { // Emit function declaration if (UseAPInt) { - o << "void " << Target.getName() + O << "void " << Target.getName() << "MCCodeEmitter::getBinaryCodeForInstr(const MCInst &MI,\n" << " SmallVectorImpl &Fixups,\n" << " APInt &Inst,\n" << " APInt &Scratch,\n" << " const MCSubtargetInfo &STI) const {\n"; } else { - o << "uint64_t " << Target.getName(); - o << "MCCodeEmitter::getBinaryCodeForInstr(const MCInst &MI,\n" + O << "uint64_t " << Target.getName(); + O << "MCCodeEmitter::getBinaryCodeForInstr(const MCInst &MI,\n" << " SmallVectorImpl &Fixups,\n" << " const MCSubtargetInfo &STI) const {\n"; } // Emit instruction base values - emitInstructionBaseValues(o, NumberedInstructions, Target, DefaultMode); + emitInstructionBaseValues(O, NumberedInstructions, Target, DefaultMode); if (!HwModes.empty()) { // Emit table for instrs whose encodings are controlled by HwModes. for (unsigned HwMode : HwModes) { if (HwMode == DefaultMode) continue; - emitInstructionBaseValues(o, NumberedInstructions, Target, HwMode); + emitInstructionBaseValues(O, NumberedInstructions, Target, HwMode); } // This pointer will be assigned to the HwMode table later. - o << " const uint64_t *InstBitsByHw;\n"; + O << " const uint64_t *InstBitsByHw;\n"; } // Map to accumulate all the cases. @@ -557,7 +557,7 @@ void CodeEmitterGen::run(raw_ostream &o) { // Emit initial function code if (UseAPInt) { int NumWords = APInt::getNumWords(BitWidth); - o << " const unsigned opcode = MI.getOpcode();\n" + O << " const unsigned opcode = MI.getOpcode();\n" << " if (Scratch.getBitWidth() != " << BitWidth << ")\n" << " Scratch = Scratch.zext(" << BitWidth << ");\n" << " Inst = APInt(" << BitWidth << ", ArrayRef(InstBits + opcode * " @@ -566,7 +566,7 @@ void CodeEmitterGen::run(raw_ostream &o) { << " APInt &op = Scratch;\n" << " switch (opcode) {\n"; } else { - o << " const unsigned opcode = MI.getOpcode();\n" + O << " const unsigned opcode = MI.getOpcode();\n" << " uint64_t Value = InstBits[opcode];\n" << " uint64_t op = 0;\n" << " (void)op; // suppress warning\n" @@ -574,30 +574,30 @@ void CodeEmitterGen::run(raw_ostream &o) { } // Emit each case statement - emitCaseMap(o, CaseMap); + emitCaseMap(O, CaseMap); // Default case: unhandled opcode - o << " default:\n" + O << " default:\n" << " std::string msg;\n" << " raw_string_ostream Msg(msg);\n" << " Msg << \"Not supported instr: \" << MI;\n" << " report_fatal_error(Msg.str().c_str());\n" << " }\n"; if (UseAPInt) - o << " Inst = Value;\n"; + O << " Inst = Value;\n"; else - o << " return Value;\n"; - o << "}\n\n"; + O << " return Value;\n"; + O << "}\n\n"; - o << "#ifdef GET_OPERAND_BIT_OFFSET\n" + O << "#ifdef GET_OPERAND_BIT_OFFSET\n" << "#undef GET_OPERAND_BIT_OFFSET\n\n" << "uint32_t " << Target.getName() << "MCCodeEmitter::getOperandBitOffset(const MCInst &MI,\n" << " unsigned OpNum,\n" << " const MCSubtargetInfo &STI) const {\n" << " switch (MI.getOpcode()) {\n"; - emitCaseMap(o, BitOffsetCaseMap); - o << " }\n" + emitCaseMap(O, BitOffsetCaseMap); + O << " }\n" << " std::string msg;\n" << " raw_string_ostream Msg(msg);\n" << " Msg << \"Not supported instr[opcode]: \" << MI << \"[\" << OpNum " diff --git a/llvm/utils/TableGen/CodeGenMapTable.cpp b/llvm/utils/TableGen/CodeGenMapTable.cpp index 7876db6f33dfdf..8d22c0013dda88 100644 --- a/llvm/utils/TableGen/CodeGenMapTable.cpp +++ b/llvm/utils/TableGen/CodeGenMapTable.cpp @@ -258,12 +258,12 @@ bool MapTableEmitter::isKeyColInstr(const Record *CurInstr) { // Check if the instruction is a KeyCol instruction. bool MatchFound = true; - for (unsigned j = 0, endCF = ColFields->size(); (j < endCF) && MatchFound; - j++) { + for (unsigned J = 0, EndCf = ColFields->size(); (J < EndCf) && MatchFound; + J++) { const RecordVal *ColFieldName = - CurInstr->getValue(ColFields->getElement(j)); + CurInstr->getValue(ColFields->getElement(J)); std::string CurInstrVal = ColFieldName->getValue()->getAsUnquotedString(); - std::string KeyColValue = KeyCol->getElement(j)->getAsUnquotedString(); + std::string KeyColValue = KeyCol->getElement(J)->getAsUnquotedString(); MatchFound = CurInstrVal == KeyColValue; } return MatchFound; @@ -318,12 +318,12 @@ const Record *MapTableEmitter::getInstrForColumn(const Record *KeyInstr, for (const Record *CurInstr : RelatedInstrVec) { bool MatchFound = true; - for (unsigned j = 0, endCF = ColFields->size(); (j < endCF) && MatchFound; - j++) { - const Init *ColFieldJ = ColFields->getElement(j); + for (unsigned J = 0, EndCf = ColFields->size(); (J < EndCf) && MatchFound; + J++) { + const Init *ColFieldJ = ColFields->getElement(J); const Init *CurInstrInit = CurInstr->getValue(ColFieldJ)->getValue(); std::string CurInstrVal = CurInstrInit->getAsUnquotedString(); - const Init *ColFieldJVallue = CurValueCol->getElement(j); + const Init *ColFieldJVallue = CurValueCol->getElement(J); MatchFound = CurInstrVal == ColFieldJVallue->getAsUnquotedString(); } @@ -368,19 +368,19 @@ unsigned MapTableEmitter::emitBinSearchTable(raw_ostream &OS) { // Number of columns in the table are NumCol+1 because key instructions are // emitted as first column. OS << "Table[][" << NumCol + 1 << "] = {\n"; - for (unsigned i = 0; i < TotalNumInstr; i++) { - const Record *CurInstr = NumberedInstructions[i]->TheDef; + for (unsigned I = 0; I < TotalNumInstr; I++) { + const Record *CurInstr = NumberedInstructions[I]->TheDef; ArrayRef ColInstrs = MapTable[CurInstr]; std::string OutStr; unsigned RelExists = 0; if (!ColInstrs.empty()) { - for (unsigned j = 0; j < NumCol; j++) { - if (ColInstrs[j] != nullptr) { + for (unsigned J = 0; J < NumCol; J++) { + if (ColInstrs[J] != nullptr) { RelExists = 1; OutStr += ", "; OutStr += Namespace; OutStr += "::"; - OutStr += ColInstrs[j]->getName(); + OutStr += ColInstrs[J]->getName(); } else { OutStr += ", (uint16_t)-1U"; } @@ -441,20 +441,20 @@ void MapTableEmitter::emitMapFuncBody(raw_ostream &OS, unsigned TableSize) { emitBinSearch(OS, TableSize); if (ValueCols.size() > 1) { - for (unsigned i = 0, e = ValueCols.size(); i < e; i++) { - const ListInit *ColumnI = ValueCols[i]; + for (unsigned I = 0, E = ValueCols.size(); I < E; I++) { + const ListInit *ColumnI = ValueCols[I]; OS << " if ("; - for (unsigned j = 0, ColSize = ColumnI->size(); j < ColSize; ++j) { - std::string ColName = ColFields->getElement(j)->getAsUnquotedString(); + for (unsigned J = 0, ColSize = ColumnI->size(); J < ColSize; ++J) { + std::string ColName = ColFields->getElement(J)->getAsUnquotedString(); OS << "in" << ColName; OS << " == "; - OS << ColName << "_" << ColumnI->getElement(j)->getAsUnquotedString(); - if (j < ColumnI->size() - 1) + OS << ColName << "_" << ColumnI->getElement(J)->getAsUnquotedString(); + if (J < ColumnI->size() - 1) OS << " && "; } OS << ")\n"; OS << " return " << InstrMapDesc.getName(); - OS << "Table[mid][" << i + 1 << "];\n"; + OS << "Table[mid][" << I + 1 << "];\n"; } OS << " return -1;"; } else @@ -509,8 +509,8 @@ static void emitEnums(raw_ostream &OS, const RecordKeeper &Records) { std::vector ValueCols; unsigned ListSize = List->size(); - for (unsigned j = 0; j < ListSize; j++) { - const auto *ListJ = cast(List->getElement(j)); + for (unsigned J = 0; J < ListSize; J++) { + const auto *ListJ = cast(List->getElement(J)); if (ListJ->size() != ColFields->size()) PrintFatalError("Record `" + CurMap->getName() + @@ -520,10 +520,10 @@ static void emitEnums(raw_ostream &OS, const RecordKeeper &Records) { ValueCols.push_back(ListJ); } - for (unsigned j = 0, endCF = ColFields->size(); j < endCF; j++) { - for (unsigned k = 0; k < ListSize; k++) { - std::string ColName = ColFields->getElement(j)->getAsUnquotedString(); - ColFieldValueMap[ColName].push_back((ValueCols[k])->getElement(j)); + for (unsigned J = 0, EndCf = ColFields->size(); J < EndCf; J++) { + for (unsigned K = 0; K < ListSize; K++) { + std::string ColName = ColFields->getElement(J)->getAsUnquotedString(); + ColFieldValueMap[ColName].push_back((ValueCols[K])->getElement(J)); } } } diff --git a/llvm/utils/TableGen/Common/CodeGenDAGPatterns.cpp b/llvm/utils/TableGen/Common/CodeGenDAGPatterns.cpp index d2228c902a56b4..f17c62dd1fd9d4 100644 --- a/llvm/utils/TableGen/Common/CodeGenDAGPatterns.cpp +++ b/llvm/utils/TableGen/Common/CodeGenDAGPatterns.cpp @@ -813,8 +813,8 @@ void TypeInfer::expandOverloads(TypeSetByHwMode &VTS) const { void TypeInfer::expandOverloads(TypeSetByHwMode::SetType &Out, const TypeSetByHwMode::SetType &Legal) const { - if (Out.count(MVT::iPTRAny)) { - Out.erase(MVT::iPTRAny); + if (Out.count(MVT::pAny)) { + Out.erase(MVT::pAny); Out.insert(MVT::iPTR); } else if (Out.count(MVT::iAny)) { Out.erase(MVT::iAny); @@ -2461,7 +2461,8 @@ bool TreePatternNode::ApplyTypeConstraints(TreePattern &TP, bool NotRegisters) { ValueTypeByHwMode VVT = TP.getInfer().getConcrete(Types[0], false); for (auto &P : VVT) { MVT::SimpleValueType VT = P.second.SimpleTy; - if (VT == MVT::iPTR || VT == MVT::iPTRAny) + // Can only check for types of a known size + if (VT == MVT::iPTR) continue; unsigned Size = MVT(VT).getFixedSizeInBits(); // Make sure that the value is representable for this type. diff --git a/llvm/utils/TableGen/Common/CodeGenTarget.cpp b/llvm/utils/TableGen/Common/CodeGenTarget.cpp index b358518c4290b0..4e75db689a0b57 100644 --- a/llvm/utils/TableGen/Common/CodeGenTarget.cpp +++ b/llvm/utils/TableGen/Common/CodeGenTarget.cpp @@ -47,19 +47,6 @@ MVT::SimpleValueType llvm::getValueType(const Record *Rec) { return (MVT::SimpleValueType)Rec->getValueAsInt("Value"); } -StringRef llvm::getName(MVT::SimpleValueType T) { - switch (T) { - case MVT::Other: - return "UNKNOWN"; - case MVT::iPTR: - return "TLI.getPointerTy()"; - case MVT::iPTRAny: - return "TLI.getPointerTy()"; - default: - return getEnumName(T); - } -} - StringRef llvm::getEnumName(MVT::SimpleValueType T) { // clang-format off switch (T) { diff --git a/llvm/utils/TableGen/Common/CodeGenTarget.h b/llvm/utils/TableGen/Common/CodeGenTarget.h index c7b44f7028eb5b..8bcb2f677a00b0 100644 --- a/llvm/utils/TableGen/Common/CodeGenTarget.h +++ b/llvm/utils/TableGen/Common/CodeGenTarget.h @@ -46,7 +46,6 @@ class CodeGenSubRegIndex; /// record corresponds to. MVT::SimpleValueType getValueType(const Record *Rec); -StringRef getName(MVT::SimpleValueType T); StringRef getEnumName(MVT::SimpleValueType T); /// getQualifiedName - Return the name of the specified record, with a diff --git a/llvm/utils/TableGen/DAGISelEmitter.cpp b/llvm/utils/TableGen/DAGISelEmitter.cpp index d3b653b0fba27f..3d39ee148373fd 100644 --- a/llvm/utils/TableGen/DAGISelEmitter.cpp +++ b/llvm/utils/TableGen/DAGISelEmitter.cpp @@ -55,8 +55,8 @@ static unsigned getResultPatternCost(TreePatternNode &P, if (II.usesCustomInserter) Cost += 10; } - for (unsigned i = 0, e = P.getNumChildren(); i != e; ++i) - Cost += getResultPatternCost(P.getChild(i), CGP); + for (unsigned I = 0, E = P.getNumChildren(); I != E; ++I) + Cost += getResultPatternCost(P.getChild(I), CGP); return Cost; } @@ -72,8 +72,8 @@ static unsigned getResultPatternSize(TreePatternNode &P, if (Op->isSubClassOf("Instruction")) { Cost += Op->getValueAsInt("CodeSize"); } - for (unsigned i = 0, e = P.getNumChildren(); i != e; ++i) - Cost += getResultPatternSize(P.getChild(i), CGP); + for (unsigned I = 0, E = P.getNumChildren(); I != E; ++I) + Cost += getResultPatternSize(P.getChild(I), CGP); return Cost; } diff --git a/llvm/utils/TableGen/DFAPacketizerEmitter.cpp b/llvm/utils/TableGen/DFAPacketizerEmitter.cpp index 537bee55978bd6..a6c0d09f69ba34 100644 --- a/llvm/utils/TableGen/DFAPacketizerEmitter.cpp +++ b/llvm/utils/TableGen/DFAPacketizerEmitter.cpp @@ -105,7 +105,7 @@ int DFAPacketizerEmitter::collectAllFuncUnits( for (const CodeGenProcModel *Model : ProcModels) ProcItinList.insert(Model->ItinsDef); - int totalFUs = 0; + int TotalFUs = 0; // Parse functional units for all the itineraries. for (const Record *Proc : ProcItinList) { std::vector FUs = Proc->getValueAsListOfDefs("FU"); @@ -123,10 +123,10 @@ int DFAPacketizerEmitter::collectAllFuncUnits( LLVM_DEBUG(dbgs() << " " << FUs[j]->getName() << ":0x" << Twine::utohexstr(FuncResources)); } - totalFUs += numFUs; + TotalFUs += numFUs; LLVM_DEBUG(dbgs() << "\n"); } - return totalFUs; + return TotalFUs; } int DFAPacketizerEmitter::collectAllComboFuncs( @@ -136,19 +136,19 @@ int DFAPacketizerEmitter::collectAllComboFuncs( LLVM_DEBUG(dbgs() << "collectAllComboFuncs"); LLVM_DEBUG(dbgs() << " (" << ComboFuncList.size() << " sets)\n"); - int numCombos = 0; - for (unsigned i = 0, N = ComboFuncList.size(); i < N; ++i) { - const Record *Func = ComboFuncList[i]; + int NumCombos = 0; + for (unsigned I = 0, N = ComboFuncList.size(); I < N; ++I) { + const Record *Func = ComboFuncList[I]; std::vector FUs = Func->getValueAsListOfDefs("CFD"); - LLVM_DEBUG(dbgs() << " CFD:" << i << " (" << FUs.size() << " combo FUs) " + LLVM_DEBUG(dbgs() << " CFD:" << I << " (" << FUs.size() << " combo FUs) " << Func->getName() << "\n"); // Convert macros to bits for each stage. - for (unsigned j = 0, N = FUs.size(); j < N; ++j) { - assert((j < DFA_MAX_RESOURCES) && + for (unsigned J = 0, N = FUs.size(); J < N; ++J) { + assert((J < DFA_MAX_RESOURCES) && "Exceeded maximum number of DFA resources"); - const Record *FuncData = FUs[j]; + const Record *FuncData = FUs[J]; const Record *ComboFunc = FuncData->getValueAsDef("TheComboFunc"); const std::vector FuncList = FuncData->getValueAsListOfDefs("FuncList"); @@ -165,13 +165,13 @@ int DFAPacketizerEmitter::collectAllComboFuncs( ComboResources |= FuncResources; } ComboBitToBitsMap[ComboBit] = ComboResources; - numCombos++; + NumCombos++; LLVM_DEBUG(dbgs() << " => combo bits: " << ComboFuncName << ":0x" << Twine::utohexstr(ComboBit) << " = 0x" << Twine::utohexstr(ComboResources) << "\n"); } } - return numCombos; + return NumCombos; } ResourceVector @@ -271,7 +271,7 @@ void DFAPacketizerEmitter::emitForItineraries( // Given a resource state, return all resource states by applying // InsnClass. - auto applyInsnClass = [&](const ResourceVector &InsnClass, + auto ApplyInsnClass = [&](const ResourceVector &InsnClass, NfaStateTy State) -> std::deque { std::deque V(1, State); // Apply every stage in the class individually. @@ -304,7 +304,7 @@ void DFAPacketizerEmitter::emitForItineraries( // Given a resource state, return a quick (conservative) guess as to whether // InsnClass can be applied. This is a filter for the more heavyweight - // applyInsnClass. + // ApplyInsnClass. auto canApplyInsnClass = [](const ResourceVector &InsnClass, NfaStateTy State) -> bool { for (NfaStateTy Resources : InsnClass) { @@ -325,7 +325,7 @@ void DFAPacketizerEmitter::emitForItineraries( if (!canApplyInsnClass(Resources, State)) continue; unsigned ResourcesID = UniqueResources.idFor(Resources); - for (uint64_t NewState : applyInsnClass(Resources, State)) { + for (uint64_t NewState : ApplyInsnClass(Resources, State)) { if (SeenStates.emplace(NewState).second) Worklist.emplace_back(NewState); Emitter.addTransition(State, NewState, ResourcesID); diff --git a/llvm/utils/TableGen/DXILEmitter.cpp b/llvm/utils/TableGen/DXILEmitter.cpp index 467a6163ae3b0c..8bebe608eece47 100644 --- a/llvm/utils/TableGen/DXILEmitter.cpp +++ b/llvm/utils/TableGen/DXILEmitter.cpp @@ -32,6 +32,20 @@ using namespace llvm::dxil; namespace { +struct DXILArgSelect { + enum class Type { + Index, + I32, + I8, + }; + Type Type = Type::Index; + int Value = -1; +}; +struct DXILIntrinsicSelect { + StringRef Intrinsic; + SmallVector Args; +}; + struct DXILOperationDesc { std::string OpName; // name of DXIL operation int OpCode; // ID of DXIL operation @@ -42,13 +56,12 @@ struct DXILOperationDesc { SmallVector OverloadRecs; SmallVector StageRecs; SmallVector AttrRecs; - StringRef Intrinsic; // The llvm intrinsic map to OpName. Default is "" which - // means no map exists + SmallVector IntrinsicSelects; SmallVector ShaderStages; // shader stages to which this applies, empty for all. int OverloadParamIndex; // Index of parameter with overload type. // -1 : no overload types - SmallVector counters; // counters for this inst. + SmallVector Counters; // counters for this inst. DXILOperationDesc(const Record *); }; } // end anonymous namespace @@ -56,7 +69,7 @@ struct DXILOperationDesc { /// In-place sort TableGen records of class with a field /// Version dxil_version /// in the ascending version order. -static void AscendingSortByVersion(std::vector &Recs) { +static void ascendingSortByVersion(std::vector &Recs) { sort(Recs, [](const Record *RecA, const Record *RecB) { unsigned RecAMaj = RecA->getValueAsDef("dxil_version")->getValueAsInt("Major"); @@ -71,6 +84,21 @@ static void AscendingSortByVersion(std::vector &Recs) { }); } +/// Take a `int_{intrinsic_name}` and return just the intrinsic_name part if +/// available. Otherwise return the empty string. +static StringRef GetIntrinsicName(const RecordVal *RV) { + if (RV && RV->getValue()) { + if (const DefInit *DI = dyn_cast(RV->getValue())) { + auto *IntrinsicDef = DI->getDef(); + auto DefName = IntrinsicDef->getName(); + assert(DefName.starts_with("int_") && "invalid intrinsic name"); + // Remove the int_ from intrinsic name. + return DefName.substr(4); + } + } + return ""; +} + /// Construct an object using the DXIL Operation records specified /// in DXIL.td. This serves as the single source of reference of /// the information extracted from the specified Record R, for @@ -97,8 +125,8 @@ DXILOperationDesc::DXILOperationDesc(const Record *R) { // the comment before the definition of class LLVMMatchType in // llvm/IR/Intrinsics.td OverloadParamIndex = -1; // A sigil meaning none. - for (unsigned i = 0; i < ParamTypeRecsSize; i++) { - const Record *TR = ParamTypeRecs[i]; + for (unsigned I = 0; I < ParamTypeRecsSize; I++) { + const Record *TR = ParamTypeRecs[I]; // Track operation parameter indices of any overload types if (TR->getValueAsInt("isOverload")) { if (OverloadParamIndex != -1) { @@ -109,7 +137,7 @@ DXILOperationDesc::DXILOperationDesc(const Record *R) { // Keep the earliest parameter index we see, but if it was the return type // overwrite it with the first overloaded argument. if (OverloadParamIndex <= 0) - OverloadParamIndex = i; + OverloadParamIndex = I; } OpTypes.emplace_back(TR); } @@ -118,7 +146,7 @@ DXILOperationDesc::DXILOperationDesc(const Record *R) { std::vector Recs = R->getValueAsListOfDefs("overloads"); // Sort records in ascending order of DXIL version - AscendingSortByVersion(Recs); + ascendingSortByVersion(Recs); for (const Record *CR : Recs) { OverloadRecs.push_back(CR); @@ -133,7 +161,7 @@ DXILOperationDesc::DXILOperationDesc(const Record *R) { } // Sort records in ascending order of DXIL version - AscendingSortByVersion(Recs); + ascendingSortByVersion(Recs); for (const Record *CR : Recs) { StageRecs.push_back(CR); @@ -143,7 +171,7 @@ DXILOperationDesc::DXILOperationDesc(const Record *R) { Recs = R->getValueAsListOfDefs("attributes"); // Sort records in ascending order of DXIL version - AscendingSortByVersion(Recs); + ascendingSortByVersion(Recs); for (const Record *CR : Recs) { AttrRecs.push_back(CR); @@ -157,14 +185,63 @@ DXILOperationDesc::DXILOperationDesc(const Record *R) { OpName); } - const RecordVal *RV = R->getValue("LLVMIntrinsic"); - if (RV && RV->getValue()) { - if (const DefInit *DI = dyn_cast(RV->getValue())) { - auto *IntrinsicDef = DI->getDef(); - auto DefName = IntrinsicDef->getName(); - assert(DefName.starts_with("int_") && "invalid intrinsic name"); - // Remove the int_ from intrinsic name. - Intrinsic = DefName.substr(4); + { + DXILIntrinsicSelect IntrSelect; + IntrSelect.Intrinsic = GetIntrinsicName(R->getValue("LLVMIntrinsic")); + if (IntrSelect.Intrinsic.size()) + IntrinsicSelects.emplace_back(std::move(IntrSelect)); + } + + auto IntrinsicSelectRecords = R->getValueAsListOfDefs("intrinsic_selects"); + if (IntrinsicSelectRecords.size()) { + if (IntrinsicSelects.size()) { + PrintFatalError( + R, Twine("LLVMIntrinsic and intrinsic_selects cannot be both " + "defined for DXIL operation - ") + + OpName); + } else { + for (const Record *R : IntrinsicSelectRecords) { + DXILIntrinsicSelect IntrSelect; + IntrSelect.Intrinsic = GetIntrinsicName(R->getValue("intrinsic")); + auto Args = R->getValueAsListOfDefs("args"); + for (const Record *Arg : Args) { + bool IsI8 = Arg->getValueAsBit("is_i8"); + bool IsI32 = Arg->getValueAsBit("is_i32"); + int Index = Arg->getValueAsInt("index"); + const Record *ValueRec = Arg->getValueAsOptionalDef("value"); + + DXILArgSelect ArgSelect; + if (IsI8) { + if (!ValueRec) { + PrintFatalError(R, Twine("'value' must be defined for i8 " + "ArgSelect for DXIL operation - ") + + OpName); + } + ArgSelect.Type = DXILArgSelect::Type::I8; + ArgSelect.Value = ValueRec->getValueAsInt("value"); + } else if (IsI32) { + if (!ValueRec) { + PrintFatalError(R, Twine("'value' must be defined for i32 " + "ArgSelect for DXIL operation - ") + + OpName); + } + ArgSelect.Type = DXILArgSelect::Type::I32; + ArgSelect.Value = ValueRec->getValueAsInt("value"); + } else { + if (Index < 0) { + PrintFatalError( + R, Twine("Index in ArgSelect must be equal to or " + "greater than 0 for DXIL operation - ") + + OpName); + } + ArgSelect.Type = DXILArgSelect::Type::Index; + ArgSelect.Value = Index; + } + + IntrSelect.Args.emplace_back(std::move(ArgSelect)); + } + IntrinsicSelects.emplace_back(std::move(IntrSelect)); + } } } } @@ -209,7 +286,7 @@ static std::string getOverloadMaskString(ArrayRef Recs) { if (Recs.empty()) { MaskString.append("{{1, 0}, OverloadKind::UNDEFINED}}"); } else { - for (auto Rec : Recs) { + for (const auto *Rec : Recs) { unsigned Major = Rec->getValueAsDef("dxil_version")->getValueAsInt("Major"); unsigned Minor = @@ -255,7 +332,7 @@ static std::string getStageMaskString(ArrayRef Recs) { "operation must be specified"); } - for (auto Rec : Recs) { + for (const auto *Rec : Recs) { unsigned Major = Rec->getValueAsDef("dxil_version")->getValueAsInt("Major"); unsigned Minor = Rec->getValueAsDef("dxil_version")->getValueAsInt("Minor"); MaskString.append(Prefix) @@ -293,7 +370,7 @@ static std::string getAttributeMaskString(ArrayRef Recs) { std::string Prefix = ""; MaskString.append("{"); - for (auto Rec : Recs) { + for (const auto *Rec : Recs) { unsigned Major = Rec->getValueAsDef("dxil_version")->getValueAsInt("Major"); unsigned Minor = Rec->getValueAsDef("dxil_version")->getValueAsInt("Minor"); MaskString.append(Prefix) @@ -377,10 +454,29 @@ static void emitDXILIntrinsicMap(ArrayRef Ops, OS << "#ifdef DXIL_OP_INTRINSIC\n"; OS << "\n"; for (const auto &Op : Ops) { - if (Op.Intrinsic.empty()) + if (Op.IntrinsicSelects.empty()) { continue; - OS << "DXIL_OP_INTRINSIC(dxil::OpCode::" << Op.OpName - << ", Intrinsic::" << Op.Intrinsic << ")\n"; + } + for (const DXILIntrinsicSelect &MappedIntr : Op.IntrinsicSelects) { + OS << "DXIL_OP_INTRINSIC(dxil::OpCode::" << Op.OpName + << ", Intrinsic::" << MappedIntr.Intrinsic; + for (const DXILArgSelect &ArgSelect : MappedIntr.Args) { + OS << ", (ArgSelect { "; + switch (ArgSelect.Type) { + case DXILArgSelect::Type::Index: + OS << "ArgSelect::Type::Index, "; + break; + case DXILArgSelect::Type::I8: + OS << "ArgSelect::Type::I8, "; + break; + case DXILArgSelect::Type::I32: + OS << "ArgSelect::Type::I32, "; + break; + } + OS << ArgSelect.Value << "})"; + } + OS << ")\n"; + } } OS << "\n"; OS << "#undef DXIL_OP_INTRINSIC\n"; @@ -480,21 +576,21 @@ static void emitDXILOperationTableDataStructs(const RecordKeeper &Records, size_t ShaderKindCount = ShaderKindRecs.size(); uint64_t ShaderKindTySz = PowerOf2Ceil(ShaderKindRecs.size() + 1); OS << "enum ShaderKind : uint" << ShaderKindTySz << "_t {\n"; - const std::string allStages("all_stages"); - const std::string removed("removed"); - int shiftVal = 1; - for (auto R : ShaderKindRecs) { + const std::string AllStages("all_stages"); + const std::string Removed("removed"); + int ShiftVal = 1; + for (const auto *R : ShaderKindRecs) { auto Name = R->getName(); - if (Name.compare(removed) == 0) { + if (Name.compare(Removed) == 0) { OS << " " << Name << " = 0, // Pseudo-stage indicating op not supported in any " "stage\n"; - } else if (Name.compare(allStages) == 0) { + } else if (Name.compare(AllStages) == 0) { OS << " " << Name << " = 0x" << utohexstr(((1 << ShaderKindCount) - 1), false, 0) << ", // Pseudo-stage indicating op is supported in all stages\n"; - } else if (Name.compare(allStages)) { - OS << " " << Name << " = 1 << " << std::to_string(shiftVal++) << ",\n"; + } else if (Name.compare(AllStages)) { + OS << " " << Name << " = 1 << " << std::to_string(ShiftVal++) << ",\n"; } } OS << "}; // enum ShaderKind\n\n"; @@ -503,7 +599,7 @@ static void emitDXILOperationTableDataStructs(const RecordKeeper &Records, /// Entry function call that invokes the functionality of this TableGen backend /// \param Records TableGen records of DXIL Operations defined in DXIL.td /// \param OS output stream -static void EmitDXILOperation(const RecordKeeper &Records, raw_ostream &OS) { +static void emitDxilOperation(const RecordKeeper &Records, raw_ostream &OS) { OS << "// Generated code, do not edit.\n"; OS << "\n"; // Get all DXIL Ops property records @@ -535,5 +631,5 @@ static void EmitDXILOperation(const RecordKeeper &Records, raw_ostream &OS) { OS << "#endif\n\n"; } -static TableGen::Emitter::Opt X("gen-dxil-operation", EmitDXILOperation, +static TableGen::Emitter::Opt X("gen-dxil-operation", emitDxilOperation, "Generate DXIL operation information"); diff --git a/llvm/utils/TableGen/DirectiveEmitter.cpp b/llvm/utils/TableGen/DirectiveEmitter.cpp index 9dc29d8262fa2c..fd815f4a31dad8 100644 --- a/llvm/utils/TableGen/DirectiveEmitter.cpp +++ b/llvm/utils/TableGen/DirectiveEmitter.cpp @@ -46,7 +46,7 @@ class IfDefScope { // Generate enum class. Entries are emitted in the order in which they appear // in the `Records` vector. -static void GenerateEnumClass(ArrayRef Records, raw_ostream &OS, +static void generateEnumClass(ArrayRef Records, raw_ostream &OS, StringRef Enum, StringRef Prefix, const DirectiveLanguage &DirLang, bool ExportEnums) { @@ -79,7 +79,7 @@ static void GenerateEnumClass(ArrayRef Records, raw_ostream &OS, // Generate enums for values that clauses can take. // Also generate function declarations for getName(StringRef Str). -static void GenerateEnumClauseVal(ArrayRef Records, +static void generateEnumClauseVal(ArrayRef Records, raw_ostream &OS, const DirectiveLanguage &DirLang, std::string &EnumHelperFuncs) { @@ -121,13 +121,13 @@ static void GenerateEnumClauseVal(ArrayRef Records, } } -static bool HasDuplicateClauses(ArrayRef Clauses, +static bool hasDuplicateClauses(ArrayRef Clauses, const Directive &Directive, StringSet<> &CrtClauses) { bool HasError = false; for (const VersionedClause VerClause : Clauses) { - const auto insRes = CrtClauses.insert(VerClause.getClause().getName()); - if (!insRes.second) { + const auto InsRes = CrtClauses.insert(VerClause.getClause().getName()); + if (!InsRes.second) { PrintError("Clause " + VerClause.getClause().getRecordName() + " already defined on directive " + Directive.getRecordName()); HasError = true; @@ -140,20 +140,20 @@ static bool HasDuplicateClauses(ArrayRef Clauses, // three allowed list. Also, since required implies allowed, clauses cannot // appear in both the allowedClauses and requiredClauses lists. static bool -HasDuplicateClausesInDirectives(ArrayRef Directives) { +hasDuplicateClausesInDirectives(ArrayRef Directives) { bool HasDuplicate = false; for (const Directive Dir : Directives) { StringSet<> Clauses; // Check for duplicates in the three allowed lists. - if (HasDuplicateClauses(Dir.getAllowedClauses(), Dir, Clauses) || - HasDuplicateClauses(Dir.getAllowedOnceClauses(), Dir, Clauses) || - HasDuplicateClauses(Dir.getAllowedExclusiveClauses(), Dir, Clauses)) { + if (hasDuplicateClauses(Dir.getAllowedClauses(), Dir, Clauses) || + hasDuplicateClauses(Dir.getAllowedOnceClauses(), Dir, Clauses) || + hasDuplicateClauses(Dir.getAllowedExclusiveClauses(), Dir, Clauses)) { HasDuplicate = true; } // Check for duplicate between allowedClauses and required Clauses.clear(); - if (HasDuplicateClauses(Dir.getAllowedClauses(), Dir, Clauses) || - HasDuplicateClauses(Dir.getRequiredClauses(), Dir, Clauses)) { + if (hasDuplicateClauses(Dir.getAllowedClauses(), Dir, Clauses) || + hasDuplicateClauses(Dir.getRequiredClauses(), Dir, Clauses)) { HasDuplicate = true; } if (HasDuplicate) @@ -173,11 +173,11 @@ bool DirectiveLanguage::HasValidityErrors() const { return true; } - return HasDuplicateClausesInDirectives(getDirectives()); + return hasDuplicateClausesInDirectives(getDirectives()); } // Count the maximum number of leaf constituents per construct. -static size_t GetMaxLeafCount(const DirectiveLanguage &DirLang) { +static size_t getMaxLeafCount(const DirectiveLanguage &DirLang) { size_t MaxCount = 0; for (const Directive D : DirLang.getDirectives()) MaxCount = std::max(MaxCount, D.getLeafConstructs().size()); @@ -186,7 +186,7 @@ static size_t GetMaxLeafCount(const DirectiveLanguage &DirLang) { // Generate the declaration section for the enumeration in the directive // language. -static void EmitDirectivesDecl(const RecordKeeper &Records, raw_ostream &OS) { +static void emitDirectivesDecl(const RecordKeeper &Records, raw_ostream &OS) { const auto DirLang = DirectiveLanguage(Records); if (DirLang.HasValidityErrors()) return; @@ -214,29 +214,29 @@ static void EmitDirectivesDecl(const RecordKeeper &Records, raw_ostream &OS) { OS << "\nLLVM_ENABLE_BITMASK_ENUMS_IN_NAMESPACE();\n"; // Emit Directive associations - std::vector associations; - copy_if(DirLang.getAssociations(), std::back_inserter(associations), + std::vector Associations; + copy_if(DirLang.getAssociations(), std::back_inserter(Associations), // Skip the "special" value [](const Record *Def) { return Def->getName() != "AS_FromLeaves"; }); - GenerateEnumClass(associations, OS, "Association", + generateEnumClass(Associations, OS, "Association", /*Prefix=*/"", DirLang, /*ExportEnums=*/false); - GenerateEnumClass(DirLang.getCategories(), OS, "Category", /*Prefix=*/"", + generateEnumClass(DirLang.getCategories(), OS, "Category", /*Prefix=*/"", DirLang, /*ExportEnums=*/false); // Emit Directive enumeration - GenerateEnumClass(DirLang.getDirectives(), OS, "Directive", + generateEnumClass(DirLang.getDirectives(), OS, "Directive", DirLang.getDirectivePrefix(), DirLang, DirLang.hasMakeEnumAvailableInNamespace()); // Emit Clause enumeration - GenerateEnumClass(DirLang.getClauses(), OS, "Clause", + generateEnumClass(DirLang.getClauses(), OS, "Clause", DirLang.getClausePrefix(), DirLang, DirLang.hasMakeEnumAvailableInNamespace()); // Emit ClauseVal enumeration std::string EnumHelperFuncs; - GenerateEnumClauseVal(DirLang.getClauses(), OS, DirLang, EnumHelperFuncs); + generateEnumClauseVal(DirLang.getClauses(), OS, DirLang, EnumHelperFuncs); // Generic function signatures OS << "\n"; @@ -259,7 +259,7 @@ static void EmitDirectivesDecl(const RecordKeeper &Records, raw_ostream &OS) { << "Clause C, unsigned Version);\n"; OS << "\n"; OS << "constexpr std::size_t getMaxLeafCount() { return " - << GetMaxLeafCount(DirLang) << "; }\n"; + << getMaxLeafCount(DirLang) << "; }\n"; OS << "LLVM_ABI Association getDirectiveAssociation(Directive D);\n"; OS << "LLVM_ABI Category getDirectiveCategory(Directive D);\n"; if (EnumHelperFuncs.length() > 0) { @@ -277,7 +277,7 @@ static void EmitDirectivesDecl(const RecordKeeper &Records, raw_ostream &OS) { } // Generate function implementation for getName(StringRef Str) -static void GenerateGetName(ArrayRef Records, raw_ostream &OS, +static void generateGetName(ArrayRef Records, raw_ostream &OS, StringRef Enum, const DirectiveLanguage &DirLang, StringRef Prefix) { OS << "\n"; @@ -300,11 +300,11 @@ static void GenerateGetName(ArrayRef Records, raw_ostream &OS, } // Generate function implementation for getKind(StringRef Str) -static void GenerateGetKind(ArrayRef Records, raw_ostream &OS, +static void generateGetKind(ArrayRef Records, raw_ostream &OS, StringRef Enum, const DirectiveLanguage &DirLang, StringRef Prefix, bool ImplicitAsUnknown) { - auto DefaultIt = find_if( + const auto *DefaultIt = find_if( Records, [](const Record *R) { return R->getValueAsBit("isDefault"); }); if (DefaultIt == Records.end()) { @@ -334,7 +334,7 @@ static void GenerateGetKind(ArrayRef Records, raw_ostream &OS, } // Generate function implementation for getKind(StringRef Str) -static void GenerateGetKindClauseVal(const DirectiveLanguage &DirLang, +static void generateGetKindClauseVal(const DirectiveLanguage &DirLang, raw_ostream &OS) { for (const Clause C : DirLang.getClauses()) { const auto &ClauseVals = C.getClauseVals(); @@ -389,7 +389,7 @@ static void GenerateGetKindClauseVal(const DirectiveLanguage &DirLang, } } -static void GenerateCaseForVersionedClauses(ArrayRef Clauses, +static void generateCaseForVersionedClauses(ArrayRef Clauses, raw_ostream &OS, StringRef DirectiveName, const DirectiveLanguage &DirLang, @@ -406,7 +406,7 @@ static void GenerateCaseForVersionedClauses(ArrayRef Clauses, } } -static std::string GetDirectiveName(const DirectiveLanguage &DirLang, +static std::string getDirectiveName(const DirectiveLanguage &DirLang, const Record *Rec) { Directive Dir(Rec); return (Twine("llvm::") + DirLang.getCppNamespace() + @@ -414,12 +414,12 @@ static std::string GetDirectiveName(const DirectiveLanguage &DirLang, .str(); } -static std::string GetDirectiveType(const DirectiveLanguage &DirLang) { +static std::string getDirectiveType(const DirectiveLanguage &DirLang) { return (Twine("llvm::") + DirLang.getCppNamespace() + "::Directive").str(); } // Generate the isAllowedClauseForDirective function implementation. -static void GenerateIsAllowedClause(const DirectiveLanguage &DirLang, +static void generateIsAllowedClause(const DirectiveLanguage &DirLang, raw_ostream &OS) { OS << "\n"; OS << "bool llvm::" << DirLang.getCppNamespace() @@ -445,16 +445,16 @@ static void GenerateIsAllowedClause(const DirectiveLanguage &DirLang, StringSet<> Cases; - GenerateCaseForVersionedClauses(Dir.getAllowedClauses(), OS, + generateCaseForVersionedClauses(Dir.getAllowedClauses(), OS, Dir.getName(), DirLang, Cases); - GenerateCaseForVersionedClauses(Dir.getAllowedOnceClauses(), OS, + generateCaseForVersionedClauses(Dir.getAllowedOnceClauses(), OS, Dir.getName(), DirLang, Cases); - GenerateCaseForVersionedClauses(Dir.getAllowedExclusiveClauses(), OS, + generateCaseForVersionedClauses(Dir.getAllowedExclusiveClauses(), OS, Dir.getName(), DirLang, Cases); - GenerateCaseForVersionedClauses(Dir.getRequiredClauses(), OS, + generateCaseForVersionedClauses(Dir.getRequiredClauses(), OS, Dir.getName(), DirLang, Cases); OS << " default:\n"; @@ -470,7 +470,7 @@ static void GenerateIsAllowedClause(const DirectiveLanguage &DirLang, OS << "}\n"; // End of function isAllowedClauseForDirective } -static void EmitLeafTable(const DirectiveLanguage &DirLang, raw_ostream &OS, +static void emitLeafTable(const DirectiveLanguage &DirLang, raw_ostream &OS, StringRef TableName) { // The leaf constructs are emitted in a form of a 2D table, where each // row corresponds to a directive (and there is a row for each directive). @@ -498,7 +498,7 @@ static void EmitLeafTable(const DirectiveLanguage &DirLang, raw_ostream &OS, DirId.insert(std::make_pair(Rec, Idx)); using LeafList = std::vector; - int MaxLeafCount = GetMaxLeafCount(DirLang); + int MaxLeafCount = getMaxLeafCount(DirLang); // The initial leaf table, rows order is same as directive order. std::vector LeafTable(Directives.size()); @@ -560,19 +560,19 @@ static void EmitLeafTable(const DirectiveLanguage &DirLang, raw_ostream &OS, // type is `int` (by default). The code above uses `int` to store directive // ids, so make sure that we catch it when something changes in the // underlying type. - std::string DirectiveType = GetDirectiveType(DirLang); + std::string DirectiveType = getDirectiveType(DirLang); OS << "\nstatic_assert(sizeof(" << DirectiveType << ") == sizeof(int));\n"; OS << "[[maybe_unused]] static const " << DirectiveType << ' ' << TableName << "[][" << MaxLeafCount + 2 << "] = {\n"; for (size_t I = 0, E = Directives.size(); I != E; ++I) { auto &Leaves = LeafTable[Ordering[I]]; - OS << " {" << GetDirectiveName(DirLang, Directives[Leaves[0]]); + OS << " {" << getDirectiveName(DirLang, Directives[Leaves[0]]); OS << ", static_cast<" << DirectiveType << ">(" << Leaves[1] << "),"; for (size_t I = 2, E = Leaves.size(); I != E; ++I) { int Idx = Leaves[I]; if (Idx >= 0) - OS << ' ' << GetDirectiveName(DirLang, Directives[Leaves[I]]) << ','; + OS << ' ' << getDirectiveName(DirLang, Directives[Leaves[I]]) << ','; else OS << " static_cast<" << DirectiveType << ">(-1),"; } @@ -600,7 +600,7 @@ static void EmitLeafTable(const DirectiveLanguage &DirLang, raw_ostream &OS, OS << "\n};\n"; } -static void GenerateGetDirectiveAssociation(const DirectiveLanguage &DirLang, +static void generateGetDirectiveAssociation(const DirectiveLanguage &DirLang, raw_ostream &OS) { enum struct Association { None = 0, // None should be the smallest value. @@ -613,10 +613,10 @@ static void GenerateGetDirectiveAssociation(const DirectiveLanguage &DirLang, Invalid, }; - ArrayRef associations = DirLang.getAssociations(); + ArrayRef Associations = DirLang.getAssociations(); - auto getAssocValue = [](StringRef name) -> Association { - return StringSwitch(name) + auto GetAssocValue = [](StringRef Name) -> Association { + return StringSwitch(Name) .Case("AS_Block", Association::Block) .Case("AS_Declaration", Association::Declaration) .Case("AS_Delimited", Association::Delimited) @@ -627,24 +627,24 @@ static void GenerateGetDirectiveAssociation(const DirectiveLanguage &DirLang, .Default(Association::Invalid); }; - auto getAssocName = [&](Association A) -> StringRef { + auto GetAssocName = [&](Association A) -> StringRef { if (A != Association::Invalid && A != Association::FromLeaves) { - auto F = find_if(associations, [&](const Record *R) { - return getAssocValue(R->getName()) == A; + const auto *F = find_if(Associations, [&](const Record *R) { + return GetAssocValue(R->getName()) == A; }); - if (F != associations.end()) + if (F != Associations.end()) return (*F)->getValueAsString("name"); // enum name } llvm_unreachable("Unexpected association value"); }; - auto errorPrefixFor = [&](Directive D) -> std::string { + auto ErrorPrefixFor = [&](Directive D) -> std::string { return (Twine("Directive '") + D.getName() + "' in namespace '" + DirLang.getCppNamespace() + "' ") .str(); }; - auto reduce = [&](Association A, Association B) -> Association { + auto Reduce = [&](Association A, Association B) -> Association { if (A > B) std::swap(A, B); @@ -663,14 +663,14 @@ static void GenerateGetDirectiveAssociation(const DirectiveLanguage &DirLang, DenseMap AsMap; - auto compAssocImpl = [&](const Record *R, auto &&Self) -> Association { + auto CompAssocImpl = [&](const Record *R, auto &&Self) -> Association { if (auto F = AsMap.find(R); F != AsMap.end()) return F->second; Directive D(R); - Association AS = getAssocValue(D.getAssociation()->getName()); + Association AS = GetAssocValue(D.getAssociation()->getName()); if (AS == Association::Invalid) { - PrintFatalError(errorPrefixFor(D) + + PrintFatalError(ErrorPrefixFor(D) + "has an unrecognized value for association: '" + D.getAssociation()->getName() + "'"); } @@ -679,22 +679,22 @@ static void GenerateGetDirectiveAssociation(const DirectiveLanguage &DirLang, return AS; } // Compute the association from leaf constructs. - std::vector leaves = D.getLeafConstructs(); - if (leaves.empty()) { + std::vector Leaves = D.getLeafConstructs(); + if (Leaves.empty()) { errs() << D.getName() << '\n'; - PrintFatalError(errorPrefixFor(D) + + PrintFatalError(ErrorPrefixFor(D) + "requests association to be computed from leaves, " "but it has no leaves"); } - Association Result = Self(leaves[0], Self); - for (int I = 1, E = leaves.size(); I < E; ++I) { - Association A = Self(leaves[I], Self); - Association R = reduce(Result, A); + Association Result = Self(Leaves[0], Self); + for (int I = 1, E = Leaves.size(); I < E; ++I) { + Association A = Self(Leaves[I], Self); + Association R = Reduce(Result, A); if (R == Association::Invalid) { - PrintFatalError(errorPrefixFor(D) + + PrintFatalError(ErrorPrefixFor(D) + "has leaves with incompatible association values: " + - getAssocName(A) + " and " + getAssocName(R)); + GetAssocName(A) + " and " + GetAssocName(R)); } Result = R; } @@ -706,11 +706,11 @@ static void GenerateGetDirectiveAssociation(const DirectiveLanguage &DirLang, }; for (const Record *R : DirLang.getDirectives()) - compAssocImpl(R, compAssocImpl); // Updates AsMap. + CompAssocImpl(R, CompAssocImpl); // Updates AsMap. OS << '\n'; - auto getQualifiedName = [&](StringRef Formatted) -> std::string { + auto GetQualifiedName = [&](StringRef Formatted) -> std::string { return (Twine("llvm::") + DirLang.getCppNamespace() + "::Directive::" + DirLang.getDirectivePrefix() + Formatted) .str(); @@ -727,9 +727,9 @@ static void GenerateGetDirectiveAssociation(const DirectiveLanguage &DirLang, for (const Record *R : DirLang.getDirectives()) { if (auto F = AsMap.find(R); F != AsMap.end()) { Directive Dir(R); - OS << " case " << getQualifiedName(Dir.getFormattedName()) << ":\n"; + OS << " case " << GetQualifiedName(Dir.getFormattedName()) << ":\n"; OS << " return " << AssociationTypeName - << "::" << getAssocName(F->second) << ";\n"; + << "::" << GetAssocName(F->second) << ";\n"; } } OS << " } // switch (Dir)\n"; @@ -737,7 +737,7 @@ static void GenerateGetDirectiveAssociation(const DirectiveLanguage &DirLang, OS << "}\n"; } -static void GenerateGetDirectiveCategory(const DirectiveLanguage &DirLang, +static void generateGetDirectiveCategory(const DirectiveLanguage &DirLang, raw_ostream &OS) { std::string LangNamespace = "llvm::" + DirLang.getCppNamespace().str(); std::string CategoryTypeName = LangNamespace + "::Category"; @@ -745,12 +745,12 @@ static void GenerateGetDirectiveCategory(const DirectiveLanguage &DirLang, OS << '\n'; OS << CategoryTypeName << ' ' << LangNamespace << "::getDirectiveCategory(" - << GetDirectiveType(DirLang) << " Dir) {\n"; + << getDirectiveType(DirLang) << " Dir) {\n"; OS << " switch (Dir) {\n"; for (const Record *R : DirLang.getDirectives()) { Directive D(R); - OS << " case " << GetDirectiveName(DirLang, R) << ":\n"; + OS << " case " << getDirectiveName(DirLang, R) << ":\n"; OS << " return " << CategoryNamespace << D.getCategory()->getValueAsString("name") << ";\n"; } @@ -760,7 +760,7 @@ static void GenerateGetDirectiveCategory(const DirectiveLanguage &DirLang, } // Generate a simple enum set with the give clauses. -static void GenerateClauseSet(ArrayRef Clauses, raw_ostream &OS, +static void generateClauseSet(ArrayRef Clauses, raw_ostream &OS, StringRef ClauseSetPrefix, const Directive &Dir, const DirectiveLanguage &DirLang) { @@ -778,7 +778,7 @@ static void GenerateClauseSet(ArrayRef Clauses, raw_ostream &OS, } // Generate an enum set for the 4 kinds of clauses linked to a directive. -static void GenerateDirectiveClauseSets(const DirectiveLanguage &DirLang, +static void generateDirectiveClauseSets(const DirectiveLanguage &DirLang, raw_ostream &OS) { IfDefScope Scope("GEN_FLANG_DIRECTIVE_CLAUSE_SETS", OS); @@ -796,13 +796,13 @@ static void GenerateDirectiveClauseSets(const DirectiveLanguage &DirLang, OS << "\n"; OS << " // Sets for " << Dir.getName() << "\n"; - GenerateClauseSet(Dir.getAllowedClauses(), OS, "allowedClauses_", Dir, + generateClauseSet(Dir.getAllowedClauses(), OS, "allowedClauses_", Dir, DirLang); - GenerateClauseSet(Dir.getAllowedOnceClauses(), OS, "allowedOnceClauses_", + generateClauseSet(Dir.getAllowedOnceClauses(), OS, "allowedOnceClauses_", Dir, DirLang); - GenerateClauseSet(Dir.getAllowedExclusiveClauses(), OS, + generateClauseSet(Dir.getAllowedExclusiveClauses(), OS, "allowedExclusiveClauses_", Dir, DirLang); - GenerateClauseSet(Dir.getRequiredClauses(), OS, "requiredClauses_", Dir, + generateClauseSet(Dir.getRequiredClauses(), OS, "requiredClauses_", Dir, DirLang); } @@ -816,7 +816,7 @@ static void GenerateDirectiveClauseSets(const DirectiveLanguage &DirLang, // Generate a map of directive (key) with DirectiveClauses struct as values. // The struct holds the 4 sets of enumeration for the 4 kinds of clauses // allowances (allowed, allowed once, allowed exclusive and required). -static void GenerateDirectiveClauseMap(const DirectiveLanguage &DirLang, +static void generateDirectiveClauseMap(const DirectiveLanguage &DirLang, raw_ostream &OS) { IfDefScope Scope("GEN_FLANG_DIRECTIVE_CLAUSE_MAP", OS); @@ -850,7 +850,7 @@ static void GenerateDirectiveClauseMap(const DirectiveLanguage &DirLang, // If the clause does not hold a value, an EMPTY_CLASS is used. // If the clause class is generic then a WRAPPER_CLASS is used. When the value // is optional, the value class is wrapped into a std::optional. -static void GenerateFlangClauseParserClass(const DirectiveLanguage &DirLang, +static void generateFlangClauseParserClass(const DirectiveLanguage &DirLang, raw_ostream &OS) { IfDefScope Scope("GEN_FLANG_CLAUSE_PARSER_CLASSES", OS); @@ -877,7 +877,7 @@ static void GenerateFlangClauseParserClass(const DirectiveLanguage &DirLang, } // Generate a list of the different clause classes for Flang. -static void GenerateFlangClauseParserClassList(const DirectiveLanguage &DirLang, +static void generateFlangClauseParserClassList(const DirectiveLanguage &DirLang, raw_ostream &OS) { IfDefScope Scope("GEN_FLANG_CLAUSE_PARSER_CLASSES_LIST", OS); @@ -890,7 +890,7 @@ static void GenerateFlangClauseParserClassList(const DirectiveLanguage &DirLang, } // Generate dump node list for the clauses holding a generic class name. -static void GenerateFlangClauseDump(const DirectiveLanguage &DirLang, +static void generateFlangClauseDump(const DirectiveLanguage &DirLang, raw_ostream &OS) { IfDefScope Scope("GEN_FLANG_DUMP_PARSE_TREE_CLAUSES", OS); @@ -904,7 +904,7 @@ static void GenerateFlangClauseDump(const DirectiveLanguage &DirLang, // Generate Unparse functions for clauses classes in the Flang parse-tree // If the clause is a non-generic class, no entry is generated. -static void GenerateFlangClauseUnparse(const DirectiveLanguage &DirLang, +static void generateFlangClauseUnparse(const DirectiveLanguage &DirLang, raw_ostream &OS) { IfDefScope Scope("GEN_FLANG_CLAUSE_UNPARSE", OS); @@ -955,7 +955,7 @@ static void GenerateFlangClauseUnparse(const DirectiveLanguage &DirLang, } // Generate check in the Enter functions for clauses classes. -static void GenerateFlangClauseCheckPrototypes(const DirectiveLanguage &DirLang, +static void generateFlangClauseCheckPrototypes(const DirectiveLanguage &DirLang, raw_ostream &OS) { IfDefScope Scope("GEN_FLANG_CLAUSE_CHECK_ENTER", OS); @@ -969,7 +969,7 @@ static void GenerateFlangClauseCheckPrototypes(const DirectiveLanguage &DirLang, // Generate the mapping for clauses between the parser class and the // corresponding clause Kind -static void GenerateFlangClauseParserKindMap(const DirectiveLanguage &DirLang, +static void generateFlangClauseParserKindMap(const DirectiveLanguage &DirLang, raw_ostream &OS) { IfDefScope Scope("GEN_FLANG_CLAUSE_PARSER_KIND_MAP", OS); @@ -996,7 +996,7 @@ static bool compareClauseName(const Record *R1, const Record *R2) { } // Generate the parser for the clauses. -static void GenerateFlangClausesParser(const DirectiveLanguage &DirLang, +static void generateFlangClausesParser(const DirectiveLanguage &DirLang, raw_ostream &OS) { std::vector Clauses = DirLang.getClauses(); // Sort clauses in reverse alphabetical order so with clauses with same @@ -1004,8 +1004,8 @@ static void GenerateFlangClausesParser(const DirectiveLanguage &DirLang, sort(Clauses, compareClauseName); IfDefScope Scope("GEN_FLANG_CLAUSES_PARSER", OS); OS << "\n"; - unsigned index = 0; - unsigned lastClauseIndex = Clauses.size() - 1; + unsigned Index = 0; + unsigned LastClauseIndex = Clauses.size() - 1; OS << "TYPE_PARSER(\n"; for (const Clause Clause : Clauses) { if (Clause.getAliases().empty()) { @@ -1013,8 +1013,8 @@ static void GenerateFlangClausesParser(const DirectiveLanguage &DirLang, } else { OS << " (" << "\"" << Clause.getName() << "\"_tok"; - for (StringRef alias : Clause.getAliases()) { - OS << " || \"" << alias << "\"_tok"; + for (StringRef Alias : Clause.getAliases()) { + OS << " || \"" << Alias << "\"_tok"; } OS << ")"; } @@ -1024,10 +1024,10 @@ static void GenerateFlangClausesParser(const DirectiveLanguage &DirLang, << "::" << Clause.getFormattedParserClassName() << ">("; if (Clause.getFlangClass().empty()) { OS << "))"; - if (index != lastClauseIndex) + if (Index != LastClauseIndex) OS << " ||"; OS << "\n"; - ++index; + ++Index; continue; } @@ -1064,38 +1064,38 @@ static void GenerateFlangClausesParser(const DirectiveLanguage &DirLang, if (Clause.isValueOptional()) // close maybe(. OS << ")"; OS << "))"; - if (index != lastClauseIndex) + if (Index != LastClauseIndex) OS << " ||"; OS << "\n"; - ++index; + ++Index; } OS << ")\n"; } // Generate the implementation section for the enumeration in the directive // language -static void EmitDirectivesFlangImpl(const DirectiveLanguage &DirLang, +static void emitDirectivesFlangImpl(const DirectiveLanguage &DirLang, raw_ostream &OS) { - GenerateDirectiveClauseSets(DirLang, OS); + generateDirectiveClauseSets(DirLang, OS); - GenerateDirectiveClauseMap(DirLang, OS); + generateDirectiveClauseMap(DirLang, OS); - GenerateFlangClauseParserClass(DirLang, OS); + generateFlangClauseParserClass(DirLang, OS); - GenerateFlangClauseParserClassList(DirLang, OS); + generateFlangClauseParserClassList(DirLang, OS); - GenerateFlangClauseDump(DirLang, OS); + generateFlangClauseDump(DirLang, OS); - GenerateFlangClauseUnparse(DirLang, OS); + generateFlangClauseUnparse(DirLang, OS); - GenerateFlangClauseCheckPrototypes(DirLang, OS); + generateFlangClauseCheckPrototypes(DirLang, OS); - GenerateFlangClauseParserKindMap(DirLang, OS); + generateFlangClauseParserKindMap(DirLang, OS); - GenerateFlangClausesParser(DirLang, OS); + generateFlangClausesParser(DirLang, OS); } -static void GenerateClauseClassMacro(const DirectiveLanguage &DirLang, +static void generateClauseClassMacro(const DirectiveLanguage &DirLang, raw_ostream &OS) { // Generate macros style information for legacy code in clang IfDefScope Scope("GEN_CLANG_CLAUSE_CLASS", OS); @@ -1163,63 +1163,63 @@ static void GenerateClauseClassMacro(const DirectiveLanguage &DirLang, // Generate the implemenation for the enumeration in the directive // language. This code can be included in library. -void EmitDirectivesBasicImpl(const DirectiveLanguage &DirLang, +void emitDirectivesBasicImpl(const DirectiveLanguage &DirLang, raw_ostream &OS) { IfDefScope Scope("GEN_DIRECTIVES_IMPL", OS); OS << "\n#include \"llvm/Support/ErrorHandling.h\"\n"; // getDirectiveKind(StringRef Str) - GenerateGetKind(DirLang.getDirectives(), OS, "Directive", DirLang, + generateGetKind(DirLang.getDirectives(), OS, "Directive", DirLang, DirLang.getDirectivePrefix(), /*ImplicitAsUnknown=*/false); // getDirectiveName(Directive Kind) - GenerateGetName(DirLang.getDirectives(), OS, "Directive", DirLang, + generateGetName(DirLang.getDirectives(), OS, "Directive", DirLang, DirLang.getDirectivePrefix()); // getClauseKind(StringRef Str) - GenerateGetKind(DirLang.getClauses(), OS, "Clause", DirLang, + generateGetKind(DirLang.getClauses(), OS, "Clause", DirLang, DirLang.getClausePrefix(), /*ImplicitAsUnknown=*/true); // getClauseName(Clause Kind) - GenerateGetName(DirLang.getClauses(), OS, "Clause", DirLang, + generateGetName(DirLang.getClauses(), OS, "Clause", DirLang, DirLang.getClausePrefix()); // getKind(StringRef Str) - GenerateGetKindClauseVal(DirLang, OS); + generateGetKindClauseVal(DirLang, OS); // isAllowedClauseForDirective(Directive D, Clause C, unsigned Version) - GenerateIsAllowedClause(DirLang, OS); + generateIsAllowedClause(DirLang, OS); // getDirectiveAssociation(Directive D) - GenerateGetDirectiveAssociation(DirLang, OS); + generateGetDirectiveAssociation(DirLang, OS); // getDirectiveCategory(Directive D) - GenerateGetDirectiveCategory(DirLang, OS); + generateGetDirectiveCategory(DirLang, OS); // Leaf table for getLeafConstructs, etc. - EmitLeafTable(DirLang, OS, "LeafConstructTable"); + emitLeafTable(DirLang, OS, "LeafConstructTable"); } // Generate the implemenation section for the enumeration in the directive // language. -static void EmitDirectivesImpl(const RecordKeeper &Records, raw_ostream &OS) { +static void emitDirectivesImpl(const RecordKeeper &Records, raw_ostream &OS) { const auto DirLang = DirectiveLanguage(Records); if (DirLang.HasValidityErrors()) return; - EmitDirectivesFlangImpl(DirLang, OS); + emitDirectivesFlangImpl(DirLang, OS); - GenerateClauseClassMacro(DirLang, OS); + generateClauseClassMacro(DirLang, OS); - EmitDirectivesBasicImpl(DirLang, OS); + emitDirectivesBasicImpl(DirLang, OS); } static TableGen::Emitter::Opt - X("gen-directive-decl", EmitDirectivesDecl, + X("gen-directive-decl", emitDirectivesDecl, "Generate directive related declaration code (header file)"); static TableGen::Emitter::Opt - Y("gen-directive-impl", EmitDirectivesImpl, + Y("gen-directive-impl", emitDirectivesImpl, "Generate directive related implementation code"); diff --git a/llvm/utils/TableGen/DisassemblerEmitter.cpp b/llvm/utils/TableGen/DisassemblerEmitter.cpp index eb15392272a3f3..70d835e699ffef 100644 --- a/llvm/utils/TableGen/DisassemblerEmitter.cpp +++ b/llvm/utils/TableGen/DisassemblerEmitter.cpp @@ -95,7 +95,7 @@ using namespace llvm::X86Disassembler; /// X86RecognizableInstr.cpp contains the implementation for a single /// instruction. -static void EmitDisassembler(const RecordKeeper &Records, raw_ostream &OS) { +static void emitDisassembler(const RecordKeeper &Records, raw_ostream &OS) { const CodeGenTarget Target(Records); emitSourceFileHeader(" * " + Target.getName().str() + " Disassembler", OS); @@ -132,5 +132,5 @@ static void EmitDisassembler(const RecordKeeper &Records, raw_ostream &OS) { cl::OptionCategory DisassemblerEmitterCat("Options for -gen-disassembler"); -static TableGen::Emitter::Opt X("gen-disassembler", EmitDisassembler, +static TableGen::Emitter::Opt X("gen-disassembler", emitDisassembler, "Generate disassembler"); diff --git a/llvm/utils/TableGen/FastISelEmitter.cpp b/llvm/utils/TableGen/FastISelEmitter.cpp index 17198c85f06009..2052222cae5e5f 100644 --- a/llvm/utils/TableGen/FastISelEmitter.cpp +++ b/llvm/utils/TableGen/FastISelEmitter.cpp @@ -718,19 +718,20 @@ void FastISelMap::printFunctionDefinitions(raw_ostream &OS) { const PredMap &PM = RI.second; OS << "unsigned fastEmit_" << getLegalCName(Opcode) << "_" - << getLegalCName(std::string(getName(VT))) << "_" - << getLegalCName(std::string(getName(RetVT))) << "_"; + << getLegalCName(std::string(getEnumName(VT))) << "_" + << getLegalCName(std::string(getEnumName(RetVT))) << "_"; Operands.PrintManglingSuffix(OS, ImmediatePredicates); OS << "("; Operands.PrintParameters(OS); OS << ") {\n"; - emitInstructionCode(OS, Operands, PM, std::string(getName(RetVT))); + emitInstructionCode(OS, Operands, PM, + std::string(getEnumName(RetVT))); } // Emit one function for the type that demultiplexes on return type. OS << "unsigned fastEmit_" << getLegalCName(Opcode) << "_" - << getLegalCName(std::string(getName(VT))) << "_"; + << getLegalCName(std::string(getEnumName(VT))) << "_"; Operands.PrintManglingSuffix(OS, ImmediatePredicates); OS << "(MVT RetVT"; if (!Operands.empty()) @@ -739,10 +740,10 @@ void FastISelMap::printFunctionDefinitions(raw_ostream &OS) { OS << ") {\nswitch (RetVT.SimpleTy) {\n"; for (const auto &RI : RM) { MVT::SimpleValueType RetVT = RI.first; - OS << " case " << getName(RetVT) << ": return fastEmit_" + OS << " case " << getEnumName(RetVT) << ": return fastEmit_" << getLegalCName(Opcode) << "_" - << getLegalCName(std::string(getName(VT))) << "_" - << getLegalCName(std::string(getName(RetVT))) << "_"; + << getLegalCName(std::string(getEnumName(VT))) << "_" + << getLegalCName(std::string(getEnumName(RetVT))) << "_"; Operands.PrintManglingSuffix(OS, ImmediatePredicates); OS << "("; Operands.PrintArguments(OS); @@ -753,7 +754,7 @@ void FastISelMap::printFunctionDefinitions(raw_ostream &OS) { } else { // Non-variadic return type. OS << "unsigned fastEmit_" << getLegalCName(Opcode) << "_" - << getLegalCName(std::string(getName(VT))) << "_"; + << getLegalCName(std::string(getEnumName(VT))) << "_"; Operands.PrintManglingSuffix(OS, ImmediatePredicates); OS << "(MVT RetVT"; if (!Operands.empty()) @@ -761,7 +762,7 @@ void FastISelMap::printFunctionDefinitions(raw_ostream &OS) { Operands.PrintParameters(OS); OS << ") {\n"; - OS << " if (RetVT.SimpleTy != " << getName(RM.begin()->first) + OS << " if (RetVT.SimpleTy != " << getEnumName(RM.begin()->first) << ")\n return 0;\n"; const PredMap &PM = RM.begin()->second; @@ -781,7 +782,7 @@ void FastISelMap::printFunctionDefinitions(raw_ostream &OS) { OS << " switch (VT.SimpleTy) {\n"; for (const auto &TI : TM) { MVT::SimpleValueType VT = TI.first; - std::string TypeName = std::string(getName(VT)); + std::string TypeName = std::string(getEnumName(VT)); OS << " case " << TypeName << ": return fastEmit_" << getLegalCName(Opcode) << "_" << getLegalCName(TypeName) << "_"; Operands.PrintManglingSuffix(OS, ImmediatePredicates); diff --git a/llvm/utils/TableGen/OptionParserEmitter.cpp b/llvm/utils/TableGen/OptionParserEmitter.cpp index cd7a140bb23143..86e8378ad5ac5d 100644 --- a/llvm/utils/TableGen/OptionParserEmitter.cpp +++ b/llvm/utils/TableGen/OptionParserEmitter.cpp @@ -26,7 +26,7 @@ static std::string getOptionName(const Record &R) { return std::string(R.getValueAsString("EnumName")); } -static raw_ostream &write_cstring(raw_ostream &OS, llvm::StringRef Str) { +static raw_ostream &writeCstring(raw_ostream &OS, llvm::StringRef Str) { OS << '"'; OS.write_escaped(Str); OS << '"'; @@ -117,7 +117,7 @@ struct SimpleEnumValueTable { OS << "static const SimpleEnumValue " << ValueTableName << "[] = {\n"; for (unsigned I = 0, E = Values.size(); I != E; ++I) { OS << "{"; - write_cstring(OS, Values[I]); + writeCstring(OS, Values[I]); OS << ","; OS << "static_cast("; emitScopedNormalizedValue(OS, NormalizedValues[I]); @@ -190,7 +190,7 @@ static MarshallingInfo createMarshallingInfo(const Record &R) { return Ret; } -static void EmitHelpTextsForVariants( +static void emitHelpTextsForVariants( raw_ostream &OS, std::vector, StringRef>> HelpTextsForVariants) { // OptTable must be constexpr so it uses std::arrays with these capacities. @@ -235,7 +235,7 @@ static void EmitHelpTextsForVariants( OS << "}}, "; if (Help.size()) - write_cstring(OS, Help); + writeCstring(OS, Help); else OS << "nullptr"; OS << ")"; @@ -249,7 +249,7 @@ static void EmitHelpTextsForVariants( /// OptionParserEmitter - This tablegen backend takes an input .td file /// describing a list of options and emits a data structure for parsing and /// working with those options when given an input command line. -static void EmitOptionParser(const RecordKeeper &Records, raw_ostream &OS) { +static void emitOptionParser(const RecordKeeper &Records, raw_ostream &OS) { // Get the option groups and options. ArrayRef Groups = Records.getAllDerivedDefinitions("OptionGroup"); @@ -363,12 +363,12 @@ static void EmitOptionParser(const RecordKeeper &Records, raw_ostream &OS) { if (!isa(R.getValueInit("HelpText"))) { OS << ",\n"; OS << " "; - write_cstring(OS, R.getValueAsString("HelpText")); + writeCstring(OS, R.getValueAsString("HelpText")); } else OS << ", nullptr"; // Not using Visibility specific text for group help. - EmitHelpTextsForVariants(OS, {}); + emitHelpTextsForVariants(OS, {}); // The option meta-variable name (unused). OS << ", nullptr"; @@ -387,7 +387,7 @@ static void EmitOptionParser(const RecordKeeper &Records, raw_ostream &OS) { OS << Prefixes[PrefixKeyT(RPrefixes.begin(), RPrefixes.end())] << ", "; // The option prefixed name. - write_cstring(OS, getOptionPrefixedName(R)); + writeCstring(OS, getOptionPrefixedName(R)); // The option identifier name. OS << ", " << getOptionName(R); @@ -464,7 +464,7 @@ static void EmitOptionParser(const RecordKeeper &Records, raw_ostream &OS) { if (!isa(R.getValueInit("HelpText"))) { OS << ",\n"; OS << " "; - write_cstring(OS, R.getValueAsString("HelpText")); + writeCstring(OS, R.getValueAsString("HelpText")); } else OS << ", nullptr"; @@ -482,19 +482,19 @@ static void EmitOptionParser(const RecordKeeper &Records, raw_ostream &OS) { HelpTextsForVariants.push_back(std::make_pair( VisibilityNames, VisibilityHelp->getValueAsString("Text"))); } - EmitHelpTextsForVariants(OS, HelpTextsForVariants); + emitHelpTextsForVariants(OS, HelpTextsForVariants); // The option meta-variable name. OS << ", "; if (!isa(R.getValueInit("MetaVarName"))) - write_cstring(OS, R.getValueAsString("MetaVarName")); + writeCstring(OS, R.getValueAsString("MetaVarName")); else OS << "nullptr"; // The option Values. Used for shell autocompletion. OS << ", "; if (!isa(R.getValueInit("Values"))) - write_cstring(OS, R.getValueAsString("Values")); + writeCstring(OS, R.getValueAsString("Values")); else if (!isa(R.getValueInit("ValuesCode"))) { OS << getOptionName(R) << "_Values"; } else @@ -571,5 +571,5 @@ static void EmitOptionParser(const RecordKeeper &Records, raw_ostream &OS) { OS << "\n"; } -static TableGen::Emitter::Opt X("gen-opt-parser-defs", EmitOptionParser, +static TableGen::Emitter::Opt X("gen-opt-parser-defs", emitOptionParser, "Generate option definitions"); diff --git a/llvm/utils/TableGen/OptionRSTEmitter.cpp b/llvm/utils/TableGen/OptionRSTEmitter.cpp index 1b4c4cad4f0a45..6eac10e1831f02 100644 --- a/llvm/utils/TableGen/OptionRSTEmitter.cpp +++ b/llvm/utils/TableGen/OptionRSTEmitter.cpp @@ -16,7 +16,7 @@ using namespace llvm; /// This tablegen backend takes an input .td file describing a list of options /// and emits a RST man page. -static void EmitOptionRST(const RecordKeeper &Records, raw_ostream &OS) { +static void emitOptionRst(const RecordKeeper &Records, raw_ostream &OS) { llvm::StringMap> OptionsByGroup; // Get the options. @@ -96,5 +96,5 @@ static void EmitOptionRST(const RecordKeeper &Records, raw_ostream &OS) { } } -static TableGen::Emitter::Opt X("gen-opt-rst", EmitOptionRST, +static TableGen::Emitter::Opt X("gen-opt-rst", emitOptionRst, "Generate option RST"); diff --git a/llvm/utils/TableGen/RISCVTargetDefEmitter.cpp b/llvm/utils/TableGen/RISCVTargetDefEmitter.cpp index 23496a37d5ea1c..39211aab6f2d1e 100644 --- a/llvm/utils/TableGen/RISCVTargetDefEmitter.cpp +++ b/llvm/utils/TableGen/RISCVTargetDefEmitter.cpp @@ -244,13 +244,13 @@ static void emitRISCVExtensionBitmask(const RecordKeeper &RK, raw_ostream &OS) { OS << "#endif\n"; } -static void EmitRISCVTargetDef(const RecordKeeper &RK, raw_ostream &OS) { +static void emitRiscvTargetDef(const RecordKeeper &RK, raw_ostream &OS) { emitRISCVExtensions(RK, OS); emitRISCVProfiles(RK, OS); emitRISCVProcs(RK, OS); emitRISCVExtensionBitmask(RK, OS); } -static TableGen::Emitter::Opt X("gen-riscv-target-def", EmitRISCVTargetDef, +static TableGen::Emitter::Opt X("gen-riscv-target-def", emitRiscvTargetDef, "Generate the list of CPUs and extensions for " "RISC-V"); diff --git a/llvm/utils/TableGen/SubtargetEmitter.cpp b/llvm/utils/TableGen/SubtargetEmitter.cpp index 17b84d06fe8573..02c799cb6f1471 100644 --- a/llvm/utils/TableGen/SubtargetEmitter.cpp +++ b/llvm/utils/TableGen/SubtargetEmitter.cpp @@ -87,65 +87,65 @@ class SubtargetEmitter { CodeGenSchedModels &SchedModels; std::string Target; - FeatureMapTy Enumeration(raw_ostream &OS); - void EmitSubtargetInfoMacroCalls(raw_ostream &OS); - unsigned FeatureKeyValues(raw_ostream &OS, const FeatureMapTy &FeatureMap); - unsigned CPUKeyValues(raw_ostream &OS, const FeatureMapTy &FeatureMap); - void FormItineraryStageString(const std::string &Names, + FeatureMapTy enumeration(raw_ostream &OS); + void emitSubtargetInfoMacroCalls(raw_ostream &OS); + unsigned featureKeyValues(raw_ostream &OS, const FeatureMapTy &FeatureMap); + unsigned cpuKeyValues(raw_ostream &OS, const FeatureMapTy &FeatureMap); + void formItineraryStageString(const std::string &Names, const Record *ItinData, std::string &ItinString, unsigned &NStages); - void FormItineraryOperandCycleString(const Record *ItinData, + void formItineraryOperandCycleString(const Record *ItinData, std::string &ItinString, unsigned &NOperandCycles); - void FormItineraryBypassString(const std::string &Names, + void formItineraryBypassString(const std::string &Names, const Record *ItinData, std::string &ItinString, unsigned NOperandCycles); - void EmitStageAndOperandCycleData( + void emitStageAndOperandCycleData( raw_ostream &OS, std::vector> &ProcItinLists); - void EmitItineraries(raw_ostream &OS, + void emitItineraries(raw_ostream &OS, std::vector> &ProcItinLists); - unsigned EmitRegisterFileTables(const CodeGenProcModel &ProcModel, + unsigned emitRegisterFileTables(const CodeGenProcModel &ProcModel, raw_ostream &OS); - void EmitLoadStoreQueueInfo(const CodeGenProcModel &ProcModel, + void emitLoadStoreQueueInfo(const CodeGenProcModel &ProcModel, raw_ostream &OS); - void EmitExtraProcessorInfo(const CodeGenProcModel &ProcModel, + void emitExtraProcessorInfo(const CodeGenProcModel &ProcModel, raw_ostream &OS); - void EmitProcessorProp(raw_ostream &OS, const Record *R, StringRef Name, + void emitProcessorProp(raw_ostream &OS, const Record *R, StringRef Name, char Separator); - void EmitProcessorResourceSubUnits(const CodeGenProcModel &ProcModel, + void emitProcessorResourceSubUnits(const CodeGenProcModel &ProcModel, raw_ostream &OS); - void EmitProcessorResources(const CodeGenProcModel &ProcModel, + void emitProcessorResources(const CodeGenProcModel &ProcModel, raw_ostream &OS); - const Record *FindWriteResources(const CodeGenSchedRW &SchedWrite, + const Record *findWriteResources(const CodeGenSchedRW &SchedWrite, const CodeGenProcModel &ProcModel); - const Record *FindReadAdvance(const CodeGenSchedRW &SchedRead, + const Record *findReadAdvance(const CodeGenSchedRW &SchedRead, const CodeGenProcModel &ProcModel); - void ExpandProcResources(ConstRecVec &PRVec, + void expandProcResources(ConstRecVec &PRVec, std::vector &ReleaseAtCycles, std::vector &AcquireAtCycles, const CodeGenProcModel &ProcModel); - void GenSchedClassTables(const CodeGenProcModel &ProcModel, + void genSchedClassTables(const CodeGenProcModel &ProcModel, SchedClassTables &SchedTables); - void EmitSchedClassTables(SchedClassTables &SchedTables, raw_ostream &OS); - void EmitProcessorModels(raw_ostream &OS); - void EmitSchedModelHelpers(const std::string &ClassName, raw_ostream &OS); + void emitSchedClassTables(SchedClassTables &SchedTables, raw_ostream &OS); + void emitProcessorModels(raw_ostream &OS); + void emitSchedModelHelpers(const std::string &ClassName, raw_ostream &OS); void emitSchedModelHelpersImpl(raw_ostream &OS, bool OnlyExpandMCInstPredicates = false); void emitGenMCSubtargetInfo(raw_ostream &OS); - void EmitMCInstrAnalysisPredicateFunctions(raw_ostream &OS); + void emitMcInstrAnalysisPredicateFunctions(raw_ostream &OS); - void EmitSchedModel(raw_ostream &OS); + void emitSchedModel(raw_ostream &OS); void emitGetMacroFusions(const std::string &ClassName, raw_ostream &OS); - void EmitHwModeCheck(const std::string &ClassName, raw_ostream &OS); - void ParseFeaturesFunction(raw_ostream &OS); + void emitHwModeCheck(const std::string &ClassName, raw_ostream &OS); + void parseFeaturesFunction(raw_ostream &OS); public: SubtargetEmitter(const RecordKeeper &R) : TGT(R), Records(R), SchedModels(TGT.getSchedModels()), Target(TGT.getName()) {} - void run(raw_ostream &o); + void run(raw_ostream &O); }; } // end anonymous namespace @@ -153,7 +153,7 @@ class SubtargetEmitter { // // Enumeration - Emit the specified class as an enumeration. // -FeatureMapTy SubtargetEmitter::Enumeration(raw_ostream &OS) { +FeatureMapTy SubtargetEmitter::enumeration(raw_ostream &OS) { ArrayRef DefList = Records.getAllDerivedDefinitions("SubtargetFeature"); @@ -171,15 +171,15 @@ FeatureMapTy SubtargetEmitter::Enumeration(raw_ostream &OS) { FeatureMapTy FeatureMap; // For each record - for (unsigned i = 0; i < N; ++i) { + for (unsigned I = 0; I < N; ++I) { // Next record - const Record *Def = DefList[i]; + const Record *Def = DefList[I]; // Get and emit name - OS << " " << Def->getName() << " = " << i << ",\n"; + OS << " " << Def->getName() << " = " << I << ",\n"; // Save the index for this feature. - FeatureMap[Def] = i; + FeatureMap[Def] = I; } OS << " " @@ -201,9 +201,9 @@ static void printFeatureMask(raw_ostream &OS, } OS << "{ { { "; - for (unsigned i = 0; i != Mask.size(); ++i) { + for (unsigned I = 0; I != Mask.size(); ++I) { OS << "0x"; - OS.write_hex(Mask[i]); + OS.write_hex(Mask[I]); OS << "ULL, "; } OS << "} } }"; @@ -211,7 +211,7 @@ static void printFeatureMask(raw_ostream &OS, /// Emit some information about the SubtargetFeature as calls to a macro so /// that they can be used from C++. -void SubtargetEmitter::EmitSubtargetInfoMacroCalls(raw_ostream &OS) { +void SubtargetEmitter::emitSubtargetInfoMacroCalls(raw_ostream &OS) { OS << "\n#ifdef GET_SUBTARGETINFO_MACRO\n"; std::vector FeatureList = @@ -252,7 +252,7 @@ void SubtargetEmitter::EmitSubtargetInfoMacroCalls(raw_ostream &OS) { // FeatureKeyValues - Emit data of all the subtarget features. Used by the // command line. // -unsigned SubtargetEmitter::FeatureKeyValues(raw_ostream &OS, +unsigned SubtargetEmitter::featureKeyValues(raw_ostream &OS, const FeatureMapTy &FeatureMap) { std::vector FeatureList = Records.getAllDerivedDefinitions("SubtargetFeature"); @@ -301,7 +301,7 @@ unsigned SubtargetEmitter::FeatureKeyValues(raw_ostream &OS, // CPUKeyValues - Emit data of all the subtarget processors. Used by command // line. // -unsigned SubtargetEmitter::CPUKeyValues(raw_ostream &OS, +unsigned SubtargetEmitter::cpuKeyValues(raw_ostream &OS, const FeatureMapTy &FeatureMap) { // Gather and sort processor information std::vector ProcessorList = @@ -349,7 +349,7 @@ unsigned SubtargetEmitter::CPUKeyValues(raw_ostream &OS, // data initialization for the specified itinerary. N is the number // of stages. // -void SubtargetEmitter::FormItineraryStageString(const std::string &Name, +void SubtargetEmitter::formItineraryStageString(const std::string &Name, const Record *ItinData, std::string &ItinString, unsigned &NStages) { @@ -358,9 +358,9 @@ void SubtargetEmitter::FormItineraryStageString(const std::string &Name, // For each stage unsigned N = NStages = StageList.size(); - for (unsigned i = 0; i < N;) { + for (unsigned I = 0; I < N;) { // Next stage - const Record *Stage = StageList[i]; + const Record *Stage = StageList[I]; // Form string as ,{ cycles, u1 | u2 | ... | un, timeinc, kind } int Cycles = Stage->getValueAsInt("Cycles"); @@ -370,10 +370,10 @@ void SubtargetEmitter::FormItineraryStageString(const std::string &Name, ConstRecVec UnitList = Stage->getValueAsListOfDefs("Units"); // For each unit - for (unsigned j = 0, M = UnitList.size(); j < M;) { + for (unsigned J = 0, M = UnitList.size(); J < M;) { // Add name and bitwise or - ItinString += Name + "FU::" + UnitList[j]->getName().str(); - if (++j < M) + ItinString += Name + "FU::" + UnitList[J]->getName().str(); + if (++J < M) ItinString += " | "; } @@ -385,7 +385,7 @@ void SubtargetEmitter::FormItineraryStageString(const std::string &Name, // Close off stage ItinString += " }"; - if (++i < N) + if (++I < N) ItinString += ", "; } } @@ -395,7 +395,7 @@ void SubtargetEmitter::FormItineraryStageString(const std::string &Name, // operand cycle initialization for the specified itinerary. N is the // number of operands that has cycles specified. // -void SubtargetEmitter::FormItineraryOperandCycleString( +void SubtargetEmitter::formItineraryOperandCycleString( const Record *ItinData, std::string &ItinString, unsigned &NOperandCycles) { // Get operand cycle list std::vector OperandCycleList = @@ -411,19 +411,19 @@ void SubtargetEmitter::FormItineraryOperandCycleString( } } -void SubtargetEmitter::FormItineraryBypassString(const std::string &Name, +void SubtargetEmitter::formItineraryBypassString(const std::string &Name, const Record *ItinData, std::string &ItinString, unsigned NOperandCycles) { ConstRecVec BypassList = ItinData->getValueAsListOfDefs("Bypasses"); unsigned N = BypassList.size(); - unsigned i = 0; + unsigned I = 0; ListSeparator LS; - for (; i < N; ++i) { + for (; I < N; ++I) { ItinString += LS; - ItinString += Name + "Bypass::" + BypassList[i]->getName().str(); + ItinString += Name + "Bypass::" + BypassList[I]->getName().str(); } - for (; i < NOperandCycles; ++i) { + for (; I < NOperandCycles; ++I) { ItinString += LS; ItinString += " 0"; } @@ -434,7 +434,7 @@ void SubtargetEmitter::FormItineraryBypassString(const std::string &Name, // cycle tables. Create a list of InstrItinerary objects (ProcItinLists) indexed // by CodeGenSchedClass::Index. // -void SubtargetEmitter::EmitStageAndOperandCycleData( +void SubtargetEmitter::emitStageAndOperandCycleData( raw_ostream &OS, std::vector> &ProcItinLists) { // Multiple processor models may share an itinerary record. Emit it once. SmallPtrSet ItinsDefSet; @@ -453,9 +453,9 @@ void SubtargetEmitter::EmitStageAndOperandCycleData( OS << "\n// Functional units for \"" << Name << "\"\n" << "namespace " << Name << "FU {\n"; - for (unsigned j = 0, FUN = FUs.size(); j < FUN; ++j) - OS << " const InstrStage::FuncUnits " << FUs[j]->getName() - << " = 1ULL << " << j << ";\n"; + for (unsigned J = 0, FUN = FUs.size(); J < FUN; ++J) + OS << " const InstrStage::FuncUnits " << FUs[J]->getName() + << " = 1ULL << " << J << ";\n"; OS << "} // end namespace " << Name << "FU\n"; @@ -466,8 +466,8 @@ void SubtargetEmitter::EmitStageAndOperandCycleData( << "namespace " << Name << "Bypass {\n"; OS << " const unsigned NoBypass = 0;\n"; - for (unsigned j = 0, BPN = BPs.size(); j < BPN; ++j) - OS << " const unsigned " << BPs[j]->getName() << " = 1 << " << j + for (unsigned J = 0, BPN = BPs.size(); J < BPN; ++J) + OS << " const unsigned " << BPs[J]->getName() << " = 1 << " << J << ";\n"; OS << "} // end namespace " << Name << "Bypass\n"; @@ -518,7 +518,7 @@ void SubtargetEmitter::EmitStageAndOperandCycleData( std::string ItinStageString; unsigned NStages = 0; if (ItinData) - FormItineraryStageString(std::string(Name), ItinData, ItinStageString, + formItineraryStageString(std::string(Name), ItinData, ItinStageString, NStages); // Get string and operand cycle count @@ -526,10 +526,10 @@ void SubtargetEmitter::EmitStageAndOperandCycleData( unsigned NOperandCycles = 0; std::string ItinBypassString; if (ItinData) { - FormItineraryOperandCycleString(ItinData, ItinOperandCycleString, + formItineraryOperandCycleString(ItinData, ItinOperandCycleString, NOperandCycles); - FormItineraryBypassString(std::string(Name), ItinData, ItinBypassString, + formItineraryBypassString(std::string(Name), ItinData, ItinBypassString, NOperandCycles); } @@ -610,7 +610,7 @@ void SubtargetEmitter::EmitStageAndOperandCycleData( // Itineraries for each processor. The Itinerary lists are indexed on // CodeGenSchedClass::Index. // -void SubtargetEmitter::EmitItineraries( +void SubtargetEmitter::emitItineraries( raw_ostream &OS, std::vector> &ProcItinLists) { // Multiple processor models may share an itinerary record. Emit it once. SmallPtrSet ItinsDefSet; @@ -642,15 +642,15 @@ void SubtargetEmitter::EmitItineraries( OS << ItinsDef->getName() << "[] = {\n"; // For each itinerary class in CodeGenSchedClass::Index order. - for (unsigned j = 0, M = ItinList.size(); j < M; ++j) { - InstrItinerary &Intinerary = ItinList[j]; + for (unsigned J = 0, M = ItinList.size(); J < M; ++J) { + InstrItinerary &Intinerary = ItinList[J]; // Emit Itinerary in the form of // { firstStage, lastStage, firstCycle, lastCycle } // index OS << " { " << Intinerary.NumMicroOps << ", " << Intinerary.FirstStage << ", " << Intinerary.LastStage << ", " << Intinerary.FirstOperandCycle << ", " << Intinerary.LastOperandCycle << " }" - << ", // " << j << " " << SchedModels.getSchedClass(j).Name << "\n"; + << ", // " << J << " " << SchedModels.getSchedClass(J).Name << "\n"; } // End processor itinerary table OS << " { 0, uint16_t(~0U), uint16_t(~0U), uint16_t(~0U), uint16_t(~0U) }" @@ -662,7 +662,7 @@ void SubtargetEmitter::EmitItineraries( // Emit either the value defined in the TableGen Record, or the default // value defined in the C++ header. The Record is null if the processor does not // define a model. -void SubtargetEmitter::EmitProcessorProp(raw_ostream &OS, const Record *R, +void SubtargetEmitter::emitProcessorProp(raw_ostream &OS, const Record *R, StringRef Name, char Separator) { OS << " "; int V = R ? R->getValueAsInt(Name) : -1; @@ -673,14 +673,14 @@ void SubtargetEmitter::EmitProcessorProp(raw_ostream &OS, const Record *R, OS << '\n'; } -void SubtargetEmitter::EmitProcessorResourceSubUnits( +void SubtargetEmitter::emitProcessorResourceSubUnits( const CodeGenProcModel &ProcModel, raw_ostream &OS) { OS << "\nstatic const unsigned " << ProcModel.ModelName << "ProcResourceSubUnits[] = {\n" << " 0, // Invalid\n"; - for (unsigned i = 0, e = ProcModel.ProcResourceDefs.size(); i < e; ++i) { - const Record *PRDef = ProcModel.ProcResourceDefs[i]; + for (unsigned I = 0, E = ProcModel.ProcResourceDefs.size(); I < E; ++I) { + const Record *PRDef = ProcModel.ProcResourceDefs[I]; if (!PRDef->isSubClassOf("ProcResGroup")) continue; for (const Record *RUDef : PRDef->getValueAsListOfDefs("Resources")) { @@ -695,7 +695,7 @@ void SubtargetEmitter::EmitProcessorResourceSubUnits( OS << "};\n"; } -static void EmitRetireControlUnitInfo(const CodeGenProcModel &ProcModel, +static void emitRetireControlUnitInfo(const CodeGenProcModel &ProcModel, raw_ostream &OS) { int64_t ReorderBufferSize = 0, MaxRetirePerCycle = 0; if (const Record *RCU = ProcModel.RetireControlUnit) { @@ -709,7 +709,7 @@ static void EmitRetireControlUnitInfo(const CodeGenProcModel &ProcModel, OS << MaxRetirePerCycle << ", // MaxRetirePerCycle\n "; } -static void EmitRegisterFileInfo(const CodeGenProcModel &ProcModel, +static void emitRegisterFileInfo(const CodeGenProcModel &ProcModel, unsigned NumRegisterFiles, unsigned NumCostEntries, raw_ostream &OS) { if (NumRegisterFiles) @@ -726,7 +726,7 @@ static void EmitRegisterFileInfo(const CodeGenProcModel &ProcModel, } unsigned -SubtargetEmitter::EmitRegisterFileTables(const CodeGenProcModel &ProcModel, +SubtargetEmitter::emitRegisterFileTables(const CodeGenProcModel &ProcModel, raw_ostream &OS) { if (llvm::all_of(ProcModel.RegisterFiles, [](const CodeGenRegisterFile &RF) { return RF.hasDefaultCosts(); @@ -778,7 +778,7 @@ SubtargetEmitter::EmitRegisterFileTables(const CodeGenProcModel &ProcModel, return CostTblIndex; } -void SubtargetEmitter::EmitLoadStoreQueueInfo(const CodeGenProcModel &ProcModel, +void SubtargetEmitter::emitLoadStoreQueueInfo(const CodeGenProcModel &ProcModel, raw_ostream &OS) { unsigned QueueID = 0; if (ProcModel.LoadQueue) { @@ -798,33 +798,33 @@ void SubtargetEmitter::EmitLoadStoreQueueInfo(const CodeGenProcModel &ProcModel, OS << " " << QueueID << ", // Resource Descriptor for the Store Queue\n"; } -void SubtargetEmitter::EmitExtraProcessorInfo(const CodeGenProcModel &ProcModel, +void SubtargetEmitter::emitExtraProcessorInfo(const CodeGenProcModel &ProcModel, raw_ostream &OS) { // Generate a table of register file descriptors (one entry per each user // defined register file), and a table of register costs. - unsigned NumCostEntries = EmitRegisterFileTables(ProcModel, OS); + unsigned NumCostEntries = emitRegisterFileTables(ProcModel, OS); // Now generate a table for the extra processor info. OS << "\nstatic const llvm::MCExtraProcessorInfo " << ProcModel.ModelName << "ExtraInfo = {\n "; // Add information related to the retire control unit. - EmitRetireControlUnitInfo(ProcModel, OS); + emitRetireControlUnitInfo(ProcModel, OS); // Add information related to the register files (i.e. where to find register // file descriptors and register costs). - EmitRegisterFileInfo(ProcModel, ProcModel.RegisterFiles.size(), + emitRegisterFileInfo(ProcModel, ProcModel.RegisterFiles.size(), NumCostEntries, OS); // Add information about load/store queues. - EmitLoadStoreQueueInfo(ProcModel, OS); + emitLoadStoreQueueInfo(ProcModel, OS); OS << "};\n"; } -void SubtargetEmitter::EmitProcessorResources(const CodeGenProcModel &ProcModel, +void SubtargetEmitter::emitProcessorResources(const CodeGenProcModel &ProcModel, raw_ostream &OS) { - EmitProcessorResourceSubUnits(ProcModel, OS); + emitProcessorResourceSubUnits(ProcModel, OS); OS << "\n// {Name, NumUnits, SuperIdx, BufferSize, SubUnitsIdxBegin}\n"; OS << "static const llvm::MCProcResourceDesc " << ProcModel.ModelName @@ -833,8 +833,8 @@ void SubtargetEmitter::EmitProcessorResources(const CodeGenProcModel &ProcModel, << " {\"InvalidUnit\", 0, 0, 0, 0},\n"; unsigned SubUnitsOffset = 1; - for (unsigned i = 0, e = ProcModel.ProcResourceDefs.size(); i < e; ++i) { - const Record *PRDef = ProcModel.ProcResourceDefs[i]; + for (unsigned I = 0, E = ProcModel.ProcResourceDefs.size(); I < E; ++I) { + const Record *PRDef = ProcModel.ProcResourceDefs[I]; const Record *SuperDef = nullptr; unsigned SuperIdx = 0; @@ -866,7 +866,7 @@ void SubtargetEmitter::EmitProcessorResources(const CodeGenProcModel &ProcModel, } else { OS << "nullptr"; } - OS << "}, // #" << i + 1; + OS << "}, // #" << I + 1; if (SuperDef) OS << ", Super=" << SuperDef->getName(); OS << "\n"; @@ -877,7 +877,7 @@ void SubtargetEmitter::EmitProcessorResources(const CodeGenProcModel &ProcModel, // Find the WriteRes Record that defines processor resources for this // SchedWrite. const Record * -SubtargetEmitter::FindWriteResources(const CodeGenSchedRW &SchedWrite, +SubtargetEmitter::findWriteResources(const CodeGenSchedRW &SchedWrite, const CodeGenProcModel &ProcModel) { // Check if the SchedWrite is already subtarget-specific and directly @@ -938,7 +938,7 @@ SubtargetEmitter::FindWriteResources(const CodeGenSchedRW &SchedWrite, /// Find the ReadAdvance record for the given SchedRead on this processor or /// return NULL. const Record * -SubtargetEmitter::FindReadAdvance(const CodeGenSchedRW &SchedRead, +SubtargetEmitter::findReadAdvance(const CodeGenSchedRW &SchedRead, const CodeGenProcModel &ProcModel) { // Check for SchedReads that directly specify a ReadAdvance. if (SchedRead.TheDef->isSubClassOf("SchedReadAdvance")) @@ -997,12 +997,12 @@ SubtargetEmitter::FindReadAdvance(const CodeGenSchedRW &SchedRead, // Expand an explicit list of processor resources into a full list of implied // resource groups and super resources that cover them. -void SubtargetEmitter::ExpandProcResources( +void SubtargetEmitter::expandProcResources( ConstRecVec &PRVec, std::vector &ReleaseAtCycles, std::vector &AcquireAtCycles, const CodeGenProcModel &PM) { assert(PRVec.size() == ReleaseAtCycles.size() && "failed precondition"); - for (unsigned i = 0, e = PRVec.size(); i != e; ++i) { - const Record *PRDef = PRVec[i]; + for (unsigned I = 0, E = PRVec.size(); I != E; ++I) { + const Record *PRDef = PRVec[I]; ConstRecVec SubResources; if (PRDef->isSubClassOf("ProcResGroup")) SubResources = PRDef->getValueAsListOfDefs("Resources"); @@ -1019,8 +1019,8 @@ void SubtargetEmitter::ExpandProcResources( const Record *SuperDef = SchedModels.findProcResUnits( SubDef->getValueAsDef("Super"), PM, SubDef->getLoc()); PRVec.push_back(SuperDef); - ReleaseAtCycles.push_back(ReleaseAtCycles[i]); - AcquireAtCycles.push_back(AcquireAtCycles[i]); + ReleaseAtCycles.push_back(ReleaseAtCycles[I]); + AcquireAtCycles.push_back(AcquireAtCycles[I]); SubDef = SuperDef; } } @@ -1036,8 +1036,8 @@ void SubtargetEmitter::ExpandProcResources( } if (SubI == SubE) { PRVec.push_back(PR); - ReleaseAtCycles.push_back(ReleaseAtCycles[i]); - AcquireAtCycles.push_back(AcquireAtCycles[i]); + ReleaseAtCycles.push_back(ReleaseAtCycles[I]); + AcquireAtCycles.push_back(AcquireAtCycles[I]); } } } @@ -1045,7 +1045,7 @@ void SubtargetEmitter::ExpandProcResources( // Generate the SchedClass table for this processor and update global // tables. Must be called for each processor in order. -void SubtargetEmitter::GenSchedClassTables(const CodeGenProcModel &ProcModel, +void SubtargetEmitter::genSchedClassTables(const CodeGenProcModel &ProcModel, SchedClassTables &SchedTables) { std::vector &SCTab = SchedTables.ProcSchedClasses.emplace_back(); @@ -1147,7 +1147,7 @@ void SubtargetEmitter::GenSchedClassTables(const CodeGenProcModel &ProcModel, for (unsigned WS : WriteSeq) { const Record *WriteRes = - FindWriteResources(SchedModels.getSchedWrite(WS), ProcModel); + findWriteResources(SchedModels.getSchedWrite(WS), ProcModel); // Mark the parent class as invalid for unsupported write types. if (WriteRes->getValueAsBit("Unsupported")) { @@ -1209,7 +1209,7 @@ void SubtargetEmitter::GenSchedClassTables(const CodeGenProcModel &ProcModel, assert(AcquireAtCycles.size() == ReleaseAtCycles.size()); - ExpandProcResources(PRVec, ReleaseAtCycles, AcquireAtCycles, ProcModel); + expandProcResources(PRVec, ReleaseAtCycles, AcquireAtCycles, ProcModel); assert(AcquireAtCycles.size() == ReleaseAtCycles.size()); for (unsigned PRIdx = 0, PREnd = PRVec.size(); PRIdx != PREnd; @@ -1263,7 +1263,7 @@ void SubtargetEmitter::GenSchedClassTables(const CodeGenProcModel &ProcModel, for (unsigned UseIdx = 0, EndIdx = Reads.size(); UseIdx != EndIdx; ++UseIdx) { const Record *ReadAdvance = - FindReadAdvance(SchedModels.getSchedRead(Reads[UseIdx]), ProcModel); + findReadAdvance(SchedModels.getSchedRead(Reads[UseIdx]), ProcModel); if (!ReadAdvance) continue; @@ -1323,12 +1323,12 @@ void SubtargetEmitter::GenSchedClassTables(const CodeGenProcModel &ProcModel, SchedTables.WriteLatencies.begin(), SchedTables.WriteLatencies.end(), WriteLatencies.begin(), WriteLatencies.end()); if (WLPos != SchedTables.WriteLatencies.end()) { - unsigned idx = WLPos - SchedTables.WriteLatencies.begin(); - SCDesc.WriteLatencyIdx = idx; - for (unsigned i = 0, e = WriteLatencies.size(); i < e; ++i) - if (SchedTables.WriterNames[idx + i].find(WriterNames[i]) == + unsigned Idx = WLPos - SchedTables.WriteLatencies.begin(); + SCDesc.WriteLatencyIdx = Idx; + for (unsigned I = 0, E = WriteLatencies.size(); I < E; ++I) + if (SchedTables.WriterNames[Idx + I].find(WriterNames[I]) == std::string::npos) { - SchedTables.WriterNames[idx + i] += std::string("_") + WriterNames[i]; + SchedTables.WriterNames[Idx + I] += std::string("_") + WriterNames[I]; } } else { SCDesc.WriteLatencyIdx = SchedTables.WriteLatencies.size(); @@ -1351,7 +1351,7 @@ void SubtargetEmitter::GenSchedClassTables(const CodeGenProcModel &ProcModel, } // Emit SchedClass tables for all processors and associated global tables. -void SubtargetEmitter::EmitSchedClassTables(SchedClassTables &SchedTables, +void SubtargetEmitter::emitSchedClassTables(SchedClassTables &SchedTables, raw_ostream &OS) { // Emit global WriteProcResTable. OS << "\n// {ProcResourceIdx, ReleaseAtCycle, AcquireAtCycle}\n" @@ -1446,15 +1446,15 @@ void SubtargetEmitter::EmitSchedClassTables(SchedClassTables &SchedTables, } } -void SubtargetEmitter::EmitProcessorModels(raw_ostream &OS) { +void SubtargetEmitter::emitProcessorModels(raw_ostream &OS) { // For each processor model. for (const CodeGenProcModel &PM : SchedModels.procModels()) { // Emit extra processor info if available. if (PM.hasExtraProcessorInfo()) - EmitExtraProcessorInfo(PM, OS); + emitExtraProcessorInfo(PM, OS); // Emit processor resource table. if (PM.hasInstrSchedModel()) - EmitProcessorResources(PM, OS); + emitProcessorResources(PM, OS); else if (!PM.ProcResourceDefs.empty()) PrintFatalError(PM.ModelDef->getLoc(), "SchedMachineModel defines " @@ -1463,12 +1463,12 @@ void SubtargetEmitter::EmitProcessorModels(raw_ostream &OS) { // Begin processor itinerary properties OS << "\n"; OS << "static const llvm::MCSchedModel " << PM.ModelName << " = {\n"; - EmitProcessorProp(OS, PM.ModelDef, "IssueWidth", ','); - EmitProcessorProp(OS, PM.ModelDef, "MicroOpBufferSize", ','); - EmitProcessorProp(OS, PM.ModelDef, "LoopMicroOpBufferSize", ','); - EmitProcessorProp(OS, PM.ModelDef, "LoadLatency", ','); - EmitProcessorProp(OS, PM.ModelDef, "HighLatency", ','); - EmitProcessorProp(OS, PM.ModelDef, "MispredictPenalty", ','); + emitProcessorProp(OS, PM.ModelDef, "IssueWidth", ','); + emitProcessorProp(OS, PM.ModelDef, "MicroOpBufferSize", ','); + emitProcessorProp(OS, PM.ModelDef, "LoopMicroOpBufferSize", ','); + emitProcessorProp(OS, PM.ModelDef, "LoadLatency", ','); + emitProcessorProp(OS, PM.ModelDef, "HighLatency", ','); + emitProcessorProp(OS, PM.ModelDef, "MispredictPenalty", ','); bool PostRAScheduler = (PM.ModelDef ? PM.ModelDef->getValueAsBit("PostRAScheduler") : false); @@ -1516,7 +1516,7 @@ void SubtargetEmitter::EmitProcessorModels(raw_ostream &OS) { // // EmitSchedModel - Emits all scheduling model tables, folding common patterns. // -void SubtargetEmitter::EmitSchedModel(raw_ostream &OS) { +void SubtargetEmitter::emitSchedModel(raw_ostream &OS) { OS << "#ifdef DBGFIELD\n" << "#error \"GenSubtargetInfo.inc requires a DBGFIELD macro\"\n" << "#endif\n" @@ -1529,22 +1529,22 @@ void SubtargetEmitter::EmitSchedModel(raw_ostream &OS) { if (SchedModels.hasItineraries()) { std::vector> ProcItinLists; // Emit the stage data - EmitStageAndOperandCycleData(OS, ProcItinLists); - EmitItineraries(OS, ProcItinLists); + emitStageAndOperandCycleData(OS, ProcItinLists); + emitItineraries(OS, ProcItinLists); } OS << "\n// ===============================================================\n" << "// Data tables for the new per-operand machine model.\n"; SchedClassTables SchedTables; for (const CodeGenProcModel &ProcModel : SchedModels.procModels()) { - GenSchedClassTables(ProcModel, SchedTables); + genSchedClassTables(ProcModel, SchedTables); } - EmitSchedClassTables(SchedTables, OS); + emitSchedClassTables(SchedTables, OS); OS << "\n#undef DBGFIELD\n"; // Emit the processor machine model - EmitProcessorModels(OS); + emitProcessorModels(OS); } static void emitPredicateProlog(const RecordKeeper &Records, raw_ostream &OS) { @@ -1756,7 +1756,7 @@ void SubtargetEmitter::emitSchedModelHelpersImpl( emitSchedModelHelperEpilogue(OS, OnlyExpandMCInstPredicates); } -void SubtargetEmitter::EmitSchedModelHelpers(const std::string &ClassName, +void SubtargetEmitter::emitSchedModelHelpers(const std::string &ClassName, raw_ostream &OS) { OS << "unsigned " << ClassName << "\n::resolveSchedClass(unsigned SchedClass, const MachineInstr *MI," @@ -1786,7 +1786,7 @@ void SubtargetEmitter::EmitSchedModelHelpers(const std::string &ClassName, PE.expandSTIPredicate(OS, Fn); } -void SubtargetEmitter::EmitHwModeCheck(const std::string &ClassName, +void SubtargetEmitter::emitHwModeCheck(const std::string &ClassName, raw_ostream &OS) { const CodeGenHwModes &CGH = TGT.getHwModes(); assert(CGH.getNumModeIds() > 0); @@ -1825,7 +1825,7 @@ void SubtargetEmitter::EmitHwModeCheck(const std::string &ClassName, OS << " return Modes;\n}\n"; // End emitting for getHwModeSet(). - auto handlePerMode = [&](std::string ModeType, unsigned ModeInBitSet) { + auto HandlePerMode = [&](std::string ModeType, unsigned ModeInBitSet) { OS << " case HwMode_" << ModeType << ":\n" << " Modes &= " << ModeInBitSet << ";\n" << " if (!Modes)\n return Modes;\n" @@ -1842,9 +1842,9 @@ void SubtargetEmitter::EmitHwModeCheck(const std::string &ClassName, OS << " if (!Modes)\n return Modes;\n\n"; OS << " switch (type) {\n"; OS << " case HwMode_Default:\n return llvm::countr_zero(Modes) + 1;\n"; - handlePerMode("ValueType", ValueTypeModes); - handlePerMode("RegInfo", RegInfoModes); - handlePerMode("EncodingInfo", EncodingInfoModes); + HandlePerMode("ValueType", ValueTypeModes); + HandlePerMode("RegInfo", RegInfoModes); + HandlePerMode("EncodingInfo", EncodingInfoModes); OS << " }\n"; OS << " llvm_unreachable(\"unexpected HwModeType\");\n" << " return 0; // should not get here\n}\n"; @@ -1871,7 +1871,7 @@ void SubtargetEmitter::emitGetMacroFusions(const std::string &ClassName, // Produces a subtarget specific function for parsing // the subtarget features string. -void SubtargetEmitter::ParseFeaturesFunction(raw_ostream &OS) { +void SubtargetEmitter::parseFeaturesFunction(raw_ostream &OS) { ArrayRef Features = Records.getAllDerivedDefinitions("SubtargetFeature"); @@ -1951,10 +1951,10 @@ void SubtargetEmitter::emitGenMCSubtargetInfo(raw_ostream &OS) { << " return MCSubtargetInfo::isCPUStringValid(CPU);\n" << " }\n"; OS << "};\n"; - EmitHwModeCheck(Target + "GenMCSubtargetInfo", OS); + emitHwModeCheck(Target + "GenMCSubtargetInfo", OS); } -void SubtargetEmitter::EmitMCInstrAnalysisPredicateFunctions(raw_ostream &OS) { +void SubtargetEmitter::emitMcInstrAnalysisPredicateFunctions(raw_ostream &OS) { OS << "\n#ifdef GET_STIPREDICATE_DECLS_FOR_MC_ANALYSIS\n"; OS << "#undef GET_STIPREDICATE_DECLS_FOR_MC_ANALYSIS\n\n"; @@ -1988,18 +1988,18 @@ void SubtargetEmitter::run(raw_ostream &OS) { OS << "#undef GET_SUBTARGETINFO_ENUM\n\n"; OS << "namespace llvm {\n"; - auto FeatureMap = Enumeration(OS); + auto FeatureMap = enumeration(OS); OS << "} // end namespace llvm\n\n"; OS << "#endif // GET_SUBTARGETINFO_ENUM\n\n"; - EmitSubtargetInfoMacroCalls(OS); + emitSubtargetInfoMacroCalls(OS); OS << "namespace llvm {\n"; - unsigned NumFeatures = FeatureKeyValues(OS, FeatureMap); + unsigned NumFeatures = featureKeyValues(OS, FeatureMap); OS << "\n"; - EmitSchedModel(OS); + emitSchedModel(OS); OS << "\n"; - unsigned NumProcs = CPUKeyValues(OS, FeatureMap); + unsigned NumProcs = cpuKeyValues(OS, FeatureMap); OS << "\n"; // MCInstrInfo initialization routine. @@ -2045,7 +2045,7 @@ void SubtargetEmitter::run(raw_ostream &OS) { OS << "#include \"llvm/Support/raw_ostream.h\"\n\n"; if (Target == "AArch64") OS << "#include \"llvm/TargetParser/AArch64TargetParser.h\"\n\n"; - ParseFeaturesFunction(OS); + parseFeaturesFunction(OS); OS << "#endif // GET_SUBTARGETINFO_TARGET_DESC\n\n"; @@ -2140,15 +2140,15 @@ void SubtargetEmitter::run(raw_ostream &OS) { OS << "nullptr, nullptr, nullptr"; OS << ") {}\n\n"; - EmitSchedModelHelpers(ClassName, OS); - EmitHwModeCheck(ClassName, OS); + emitSchedModelHelpers(ClassName, OS); + emitHwModeCheck(ClassName, OS); emitGetMacroFusions(ClassName, OS); OS << "} // end namespace llvm\n\n"; OS << "#endif // GET_SUBTARGETINFO_CTOR\n\n"; - EmitMCInstrAnalysisPredicateFunctions(OS); + emitMcInstrAnalysisPredicateFunctions(OS); } static TableGen::Emitter::OptClass diff --git a/llvm/utils/TableGen/TableGen.cpp b/llvm/utils/TableGen/TableGen.cpp index fff4c6b7c27ada..bea2a2e735dbe2 100644 --- a/llvm/utils/TableGen/TableGen.cpp +++ b/llvm/utils/TableGen/TableGen.cpp @@ -39,17 +39,17 @@ static cl::opt Class("class", cl::value_desc("class name"), cl::cat(PrintEnumsCat)); -static void PrintRecords(const RecordKeeper &Records, raw_ostream &OS) { +static void printRecords(const RecordKeeper &Records, raw_ostream &OS) { OS << Records; // No argument, dump all contents } -static void PrintEnums(const RecordKeeper &Records, raw_ostream &OS) { +static void printEnums(const RecordKeeper &Records, raw_ostream &OS) { for (const Record *Rec : Records.getAllDerivedDefinitions(Class)) OS << Rec->getName() << ", "; OS << "\n"; } -static void PrintSets(const RecordKeeper &Records, raw_ostream &OS) { +static void printSets(const RecordKeeper &Records, raw_ostream &OS) { SetTheory Sets; Sets.addFieldExpander("Set", "Elements"); for (const Record *Rec : Records.getAllDerivedDefinitions("Set")) { @@ -63,15 +63,15 @@ static void PrintSets(const RecordKeeper &Records, raw_ostream &OS) { } static TableGen::Emitter::Opt X[] = { - {"print-records", PrintRecords, "Print all records to stdout (default)", + {"print-records", printRecords, "Print all records to stdout (default)", true}, {"print-detailed-records", EmitDetailedRecords, "Print full details of all records to stdout"}, {"null-backend", [](const RecordKeeper &Records, raw_ostream &OS) {}, "Do nothing after parsing (useful for timing)"}, {"dump-json", EmitJSON, "Dump all records as machine-readable JSON"}, - {"print-enums", PrintEnums, "Print enum values for a class"}, - {"print-sets", PrintSets, "Print expanded sets for testing DAG exprs"}, + {"print-enums", printEnums, "Print enum values for a class"}, + {"print-sets", printSets, "Print expanded sets for testing DAG exprs"}, }; int main(int argc, char **argv) { diff --git a/llvm/utils/TableGen/VTEmitter.cpp b/llvm/utils/TableGen/VTEmitter.cpp index 4cbc7abd699d20..d02932dd5e7fca 100644 --- a/llvm/utils/TableGen/VTEmitter.cpp +++ b/llvm/utils/TableGen/VTEmitter.cpp @@ -28,7 +28,7 @@ class VTEmitter { } // End anonymous namespace. -static void VTtoGetLLVMTyString(raw_ostream &OS, const Record *VT) { +static void vTtoGetLlvmTyString(raw_ostream &OS, const Record *VT) { bool IsVector = VT->getValueAsBit("isVector"); bool IsRISCVVecTuple = VT->getValueAsBit("isRISCVVecTuple"); @@ -207,7 +207,7 @@ void VTEmitter::run(raw_ostream &OS) { continue; OS << " GET_VT_EVT(" << VT->getValueAsString("LLVMName") << ", "; - VTtoGetLLVMTyString(OS, VT); + vTtoGetLlvmTyString(OS, VT); OS << ")\n"; } OS << "#endif\n\n"; diff --git a/llvm/utils/UpdateTestChecks/common.py b/llvm/utils/UpdateTestChecks/common.py index 0fbb73431d2cfb..b108a21dbc52b8 100644 --- a/llvm/utils/UpdateTestChecks/common.py +++ b/llvm/utils/UpdateTestChecks/common.py @@ -275,8 +275,10 @@ def __init__( self.run_lines = find_run_lines(test, self.input_lines) self.comment_prefix = comment_prefix if self.comment_prefix is None: - if self.path.endswith(".mir"): + if self.path.endswith(".mir") or self.path.endswith(".txt"): self.comment_prefix = "#" + elif self.path.endswith(".s"): + self.comment_prefix = "//" else: self.comment_prefix = ";" self.autogenerated_note_prefix = self.comment_prefix + " " + UTC_ADVERT @@ -2468,6 +2470,7 @@ def get_autogennote_suffix(parser, args): "verbose", "force_update", "reset_variable_names", + "llvm_mc_binary", ): continue value = getattr(args, action.dest) diff --git a/llvm/utils/gn/secondary/compiler-rt/test/BUILD.gn b/llvm/utils/gn/secondary/compiler-rt/test/BUILD.gn index 020f3e7d9acd7b..5fbda794ff176e 100644 --- a/llvm/utils/gn/secondary/compiler-rt/test/BUILD.gn +++ b/llvm/utils/gn/secondary/compiler-rt/test/BUILD.gn @@ -55,8 +55,6 @@ write_cmake_config("lit_common_configured") { "COMPILER_RT_ENABLE_INTERNAL_SYMBOLIZER_PYBOOL=False", "COMPILER_RT_HAS_NO_DEFAULT_CONFIG_FLAG_PYBOOL=True", "COMPILER_RT_INTERCEPT_LIBDISPATCH_PYBOOL=False", - "COMPILER_RT_RESOLVED_EXEC_OUTPUT_DIR=" + - rebase_path("$root_build_dir/bin"), "COMPILER_RT_RESOLVED_LIBRARY_OUTPUT_DIR=" + rebase_path(crt_current_out_dir), "COMPILER_RT_RESOLVED_OUTPUT_DIR=" + rebase_path(crt_current_out_dir), diff --git a/llvm/utils/gn/secondary/libcxx/include/BUILD.gn b/llvm/utils/gn/secondary/libcxx/include/BUILD.gn index 8121e34dcf6eff..776f1d32c5f520 100644 --- a/llvm/utils/gn/secondary/libcxx/include/BUILD.gn +++ b/llvm/utils/gn/secondary/libcxx/include/BUILD.gn @@ -995,6 +995,7 @@ if (current_toolchain == default_toolchain) { "coroutine", "csetjmp", "csignal", + "cstdalign", "cstdarg", "cstdbool", "cstddef", diff --git a/llvm/utils/gn/secondary/llvm/lib/Support/BUILD.gn b/llvm/utils/gn/secondary/llvm/lib/Support/BUILD.gn index 64b03b57388cb2..d152aec19d1b58 100644 --- a/llvm/utils/gn/secondary/llvm/lib/Support/BUILD.gn +++ b/llvm/utils/gn/secondary/llvm/lib/Support/BUILD.gn @@ -152,6 +152,7 @@ static_library("Support") { "TimeProfiler.cpp", "Timer.cpp", "ToolOutputFile.cpp", + "TrieRawHashMap.cpp", "Twine.cpp", "TypeSize.cpp", "Unicode.cpp", diff --git a/llvm/utils/gn/secondary/llvm/unittests/ADT/BUILD.gn b/llvm/utils/gn/secondary/llvm/unittests/ADT/BUILD.gn index c27faaaecf30d1..07ed3b4718af50 100644 --- a/llvm/utils/gn/secondary/llvm/unittests/ADT/BUILD.gn +++ b/llvm/utils/gn/secondary/llvm/unittests/ADT/BUILD.gn @@ -94,6 +94,7 @@ unittest("ADTTests") { "StringSetTest.cpp", "StringSwitchTest.cpp", "TinyPtrVectorTest.cpp", + "TrieRawHashMapTest.cpp", "TwineTest.cpp", "TypeSwitchTest.cpp", "TypeTraitsTest.cpp", diff --git a/llvm/utils/gn/secondary/llvm/unittests/ExecutionEngine/JITLink/BUILD.gn b/llvm/utils/gn/secondary/llvm/unittests/ExecutionEngine/JITLink/BUILD.gn index 6f52677cb83338..7f74b335e30ed9 100644 --- a/llvm/utils/gn/secondary/llvm/unittests/ExecutionEngine/JITLink/BUILD.gn +++ b/llvm/utils/gn/secondary/llvm/unittests/ExecutionEngine/JITLink/BUILD.gn @@ -17,8 +17,9 @@ unittest("JITLinkTests") { "AArch32ErrorTests.cpp", "AArch32Tests.cpp", "EHFrameSupportTests.cpp", - "JITLinkMocks.cpp", + "JITLinkTestUtils.cpp", "LinkGraphTests.cpp", + "MachOLinkGraphTests.cpp", "MemoryManagerErrorTests.cpp", "StubsTests.cpp", ] diff --git a/llvm/utils/gn/secondary/llvm/unittests/Transforms/Vectorize/SandboxVectorizer/BUILD.gn b/llvm/utils/gn/secondary/llvm/unittests/Transforms/Vectorize/SandboxVectorizer/BUILD.gn index 44640c6527c903..97df71c6279efd 100644 --- a/llvm/utils/gn/secondary/llvm/unittests/Transforms/Vectorize/SandboxVectorizer/BUILD.gn +++ b/llvm/utils/gn/secondary/llvm/unittests/Transforms/Vectorize/SandboxVectorizer/BUILD.gn @@ -14,5 +14,6 @@ unittest("SandboxVectorizerTests") { "IntervalTest.cpp", "LegalityTest.cpp", "SchedulerTest.cpp", + "VecUtilsTest.cpp", ] } diff --git a/llvm/utils/update_mc_test_checks.py b/llvm/utils/update_mc_test_checks.py index f9f8cfdea418d0..c8a40b37088ae4 100755 --- a/llvm/utils/update_mc_test_checks.py +++ b/llvm/utils/update_mc_test_checks.py @@ -6,6 +6,7 @@ from __future__ import print_function import argparse +import functools import os # Used to advertise this file's name ("autogenerated_note"). from UpdateTestChecks import common @@ -15,7 +16,6 @@ mc_LIKE_TOOLS = [ "llvm-mc", - "not llvm-mc", ] ERROR_RE = re.compile(r":\d+: (warning|error): .*") ERROR_CHECK_RE = re.compile(r"# COM: .*") @@ -23,7 +23,7 @@ COMMENT = {"asm": "//", "dasm": "#"} -def invoke_tool(exe, cmd_args, testline, verbose=False): +def invoke_tool(exe, check_rc, cmd_args, testline, verbose=False): if isinstance(cmd_args, list): args = [applySubstitutions(a, substitutions) for a in cmd_args] else: @@ -32,7 +32,15 @@ def invoke_tool(exe, cmd_args, testline, verbose=False): cmd = 'echo "' + testline + '" | ' + exe + " " + args if verbose: print("Command: ", cmd) - out = subprocess.check_output(cmd, shell=True) + + out = subprocess.run( + cmd, + shell=True, + check=check_rc, + stdout=subprocess.PIPE, + stderr=subprocess.DEVNULL, + ).stdout + # Fix line endings to unix CR style. return out.decode().replace("\r\n", "\n") @@ -50,6 +58,10 @@ def isTestLine(input_line, mc_mode): return True +def isRunLine(l): + return common.RUN_LINE_RE.match(l) + + def hasErr(err): return err and ERROR_RE.search(err) is not None @@ -97,8 +109,16 @@ def getStdCheckLine(prefix, output, mc_mode): return o -def getErrCheckLine(prefix, output, mc_mode): - return COMMENT[mc_mode] + " " + prefix + ": " + ":[[@LINE-1]]" + output + "\n" +def getErrCheckLine(prefix, output, mc_mode, line_offset=1): + return ( + COMMENT[mc_mode] + + " " + + prefix + + ": " + + ":[[@LINE-{}]]".format(line_offset) + + output + + "\n" + ) def main(): @@ -118,6 +138,19 @@ def main(): default=None, help="Set a default -march for when neither triple nor arch are found in a RUN line", ) + parser.add_argument( + "--unique", + action="store_true", + default=False, + help="remove duplicated test line if found", + ) + parser.add_argument( + "--sort", + action="store_true", + default=False, + help="sort testline in alphabetic order (keep run-lines on top), this option could be dangerous as it" + "could change the order of lines that are not expected", + ) parser.add_argument("tests", nargs="+") initial_args = common.parse_commandline_args(parser) @@ -130,6 +163,11 @@ def main(): mc_mode = "asm" elif ti.path.endswith(".txt"): mc_mode = "dasm" + + if ti.args.sort: + print("sorting with dasm(.txt) file is not supported!") + return -1 + else: common.warn("Expected .s and .txt, Skipping file : ", ti.path) continue @@ -151,11 +189,19 @@ def main(): assert len(commands) >= 2 mc_cmd = " | ".join(commands[:-1]) filecheck_cmd = commands[-1] - mc_tool = mc_cmd.split(" ")[0] # special handling for negating exit status - if mc_tool == "not": - mc_tool = mc_tool + " " + mc_cmd.split(" ")[1] + # if not is used in runline, disable rc check, since + # the command might or might not + # return non-zero code on a single line run + check_rc = True + mc_cmd_args = mc_cmd.strip().split() + if mc_cmd_args[0] == "not": + check_rc = False + mc_tool = mc_cmd_args[1] + mc_cmd = mc_cmd[len(mc_cmd_args[0]) :].strip() + else: + mc_tool = mc_cmd_args[0] triple_in_cmd = None m = common.TRIPLE_ARG_RE.search(mc_cmd) @@ -188,6 +234,7 @@ def main(): ( check_prefixes, mc_tool, + check_rc, mc_cmd_args, triple_in_cmd, march_in_cmd, @@ -196,6 +243,10 @@ def main(): # find all test line from input testlines = [l for l in ti.input_lines if isTestLine(l, mc_mode)] + # remove duplicated lines to save running time + testlines = list(dict.fromkeys(testlines)) + common.debug("Valid test line found: ", len(testlines)) + run_list_size = len(run_list) testnum = len(testlines) @@ -204,6 +255,7 @@ def main(): for ( prefixes, mc_tool, + check_rc, mc_args, triple_in_cmd, march_in_cmd, @@ -222,6 +274,7 @@ def main(): # get output for each testline out = invoke_tool( ti.args.llvm_mc_binary or mc_tool, + check_rc, mc_args, line, verbose=ti.args.verbose, @@ -233,7 +286,7 @@ def main(): raw_prefixes.append(prefixes) output_lines = [] - generated_prefixes = [] + generated_prefixes = {} used_prefixes = set() prefix_set = set([prefix for p in run_list for prefix in p[0]]) common.debug("Rewriting FileCheck prefixes:", str(prefix_set)) @@ -278,6 +331,9 @@ def main(): # each run_id can only be used once gen_prefix = "" used_runid = set() + + # line number diff between generated prefix and testline + line_offset = 1 for prefix, tup in p_dict_sorted.items(): o, run_ids = tup @@ -294,27 +350,80 @@ def main(): used_prefixes.add(prefix) if hasErr(o): - gen_prefix += getErrCheckLine(prefix, o, mc_mode) + newline = getErrCheckLine(prefix, o, mc_mode, line_offset) else: - gen_prefix += getStdCheckLine(prefix, o, mc_mode) + newline = getStdCheckLine(prefix, o, mc_mode) + + if newline: + gen_prefix += newline + line_offset += 1 - generated_prefixes.append(gen_prefix.rstrip("\n")) + generated_prefixes[input_line] = gen_prefix.rstrip("\n") # write output - prefix_id = 0 for input_info in ti.iterlines(output_lines): input_line = input_info.line - if isTestLine(input_line, mc_mode): + if input_line in testlines: output_lines.append(input_line) - output_lines.append(generated_prefixes[prefix_id]) - prefix_id += 1 + output_lines.append(generated_prefixes[input_line]) elif should_add_line_to_output(input_line, prefix_set, mc_mode): output_lines.append(input_line) - elif input_line in ti.run_lines or input_line == "": - output_lines.append(input_line) + if ti.args.unique or ti.args.sort: + # split with double newlines + test_units = "\n".join(output_lines).split("\n\n") + + # select the key line for each test unit + test_dic = {} + for unit in test_units: + lines = unit.split("\n") + for l in lines: + # if contains multiple lines, use + # the first testline or runline as key + if isTestLine(l, mc_mode): + test_dic[unit] = l + break + if isRunLine(l): + test_dic[unit] = l + break + + # unique + if ti.args.unique: + new_test_units = [] + written_lines = set() + for unit in test_units: + # if not testline/runline, we just add it + if unit not in test_dic: + new_test_units.append(unit) + else: + if test_dic[unit] in written_lines: + common.debug("Duplicated test skipped: ", unit) + continue + + written_lines.add(test_dic[unit]) + new_test_units.append(unit) + test_units = new_test_units + + # sort + if ti.args.sort: + + def getkey(l): + # find key of test unit, otherwise use first line + if l in test_dic: + line = test_dic[l] + else: + line = l.split("\n")[0] + + # runline placed on the top + return (not isRunLine(line), line) + + test_units = sorted(test_units, key=getkey) + + # join back to be output string + output_lines = "\n\n".join(test_units).split("\n") + # output if ti.args.gen_unused_prefix_body: output_lines.extend( ti.get_checks_for_unused_prefixes(run_list, used_prefixes) diff --git a/mlir/docs/Rationale/SideEffectsAndSpeculation.md b/mlir/docs/Rationale/SideEffectsAndSpeculation.md index 8b08b757531bef..4d9021a356dfea 100644 --- a/mlir/docs/Rationale/SideEffectsAndSpeculation.md +++ b/mlir/docs/Rationale/SideEffectsAndSpeculation.md @@ -79,9 +79,9 @@ When adding a new op, ask: 1. Does it read from or write to the heap or stack? It should probably implement `MemoryEffectsOpInterface`. -1. Does these side effects ordered? It should probably set the stage of - side effects to make analysis more accurate. -1. Does These side effects act on every single value of resource? It probably +1. Are these side effects ordered? The op should probably set the stage of + side effects to make analyses more accurate. +1. Do these side effects act on every single value of a resource? It probably should set the FullEffect on effect. 1. Does it have side effects that must be preserved, like a volatile store or a syscall? It should probably implement `MemoryEffectsOpInterface` and model @@ -106,9 +106,9 @@ add side effect correctly. ### SIMD compute operation -If we have a SIMD backend dialect with a "simd.abs" operation, which reads all +Consider a SIMD backend dialect with a "simd.abs" operation which reads all values from the source memref, calculates their absolute values, and writes them -to the target memref. +to the target memref: ```mlir func.func @abs(%source : memref<10xf32>, %target : memref<10xf32>) { @@ -139,10 +139,10 @@ A typical approach is as follows: } ``` -In the above example, we attach the side effect [MemReadAt<0, FullEffect>] to +In the above example, we attach the side effect `[MemReadAt<0, FullEffect>]` to the source, indicating that the abs operation reads each individual value from the source during stage 0. Likewise, we attach the side effect -[MemWriteAt<1, FullEffect>] to the target, indicating that the abs operation +`[MemWriteAt<1, FullEffect>]` to the target, indicating that the abs operation writes to each individual value within the target during stage 1 (after reading from the source). @@ -174,7 +174,7 @@ A typical approach is as follows: } ``` -In the above example, we attach the side effect [MemReadAt<0, PartialEffect>] to +In the above example, we attach the side effect `[MemReadAt<0, PartialEffect>]` to the source, indicating that the load operation reads parts of values from the memref during stage 0. Since side effects typically occur at stage 0 and are -partial by default, we can abbreviate it as "[MemRead]". +partial by default, we can abbreviate it as `[MemRead]`. diff --git a/mlir/include/mlir/Dialect/Bufferization/IR/BufferizableOpInterface.h b/mlir/include/mlir/Dialect/Bufferization/IR/BufferizableOpInterface.h index aceb9d059b95f3..4866e31b19d5de 100644 --- a/mlir/include/mlir/Dialect/Bufferization/IR/BufferizableOpInterface.h +++ b/mlir/include/mlir/Dialect/Bufferization/IR/BufferizableOpInterface.h @@ -60,7 +60,8 @@ struct AliasingValue { bool isDefinite; }; -template class AliasList { +template +class AliasList { public: /// Create an empty list of aliases. AliasList() = default; @@ -259,7 +260,7 @@ struct BufferizationOptions { /// Initializer function for analysis state. using AnalysisStateInitFn = std::function; /// Tensor -> MemRef type converter. - /// Parameters: Value, memory space, func op, bufferization options + /// Parameters: tensor type, memory space, func op, bufferization options using FunctionArgTypeConverterFn = std::function; @@ -344,9 +345,9 @@ struct BufferizationOptions { void setFunctionBoundaryTypeConversion(LayoutMapOption layoutMapOption); /// Type converter from tensors to memrefs. This type converter is used to - /// determine bufferized function argument types. By default, a type - /// converter that returns a memref type with a fully dynamic layout map is - /// used. + /// determine bufferized function argument and result types. By default, a + /// type converter that returns a memref type with a fully dynamic layout map + /// is used. /// /// If `bufferizeFunctionBoundaries` is not set, this function isn't used. FunctionArgTypeConverterFn functionArgTypeConverterFn = nullptr; diff --git a/mlir/include/mlir/Dialect/Linalg/IR/LinalgStructuredOps.td b/mlir/include/mlir/Dialect/Linalg/IR/LinalgStructuredOps.td index bfc609bd708164..c2fee8ea55c960 100644 --- a/mlir/include/mlir/Dialect/Linalg/IR/LinalgStructuredOps.td +++ b/mlir/include/mlir/Dialect/Linalg/IR/LinalgStructuredOps.td @@ -30,6 +30,7 @@ class LinalgStructuredBase_Op props> SingleBlockImplicitTerminator<"YieldOp">, DeclareOpInterfaceMethods, DeclareOpInterfaceMethods, + RecursiveMemoryEffects, DestinationStyleOpInterface, LinalgStructuredInterface, ReifyRankedShapedTypeOpInterface], props)> { diff --git a/mlir/include/mlir/Dialect/Linalg/Transforms/Transforms.h b/mlir/include/mlir/Dialect/Linalg/Transforms/Transforms.h index 70b086641bdc18..b5710bd78f0089 100644 --- a/mlir/include/mlir/Dialect/Linalg/Transforms/Transforms.h +++ b/mlir/include/mlir/Dialect/Linalg/Transforms/Transforms.h @@ -1503,18 +1503,13 @@ using OptimizeCopyFn = /// Rewrite a tensor::PadOp into a sequence of EmptyOp, FillOp and /// InsertSliceOp. For now, only constant padding values are supported. -/// `OptimizeCopyFn` can be used to customize copying step optimization. struct GeneralizePadOpPattern : public OpRewritePattern { - GeneralizePadOpPattern(MLIRContext *context, - OptimizeCopyFn optimizeCopyFn = nullptr, - PatternBenefit benefit = 1) - : OpRewritePattern(context, benefit), - optimizeCopyFn(std::move(optimizeCopyFn)) {} + GeneralizePadOpPattern(MLIRContext *context, PatternBenefit benefit = 1) + : OpRewritePattern(context, benefit) {} LogicalResult matchAndRewrite(tensor::PadOp padOp, PatternRewriter &rewriter) const override; protected: - OptimizeCopyFn optimizeCopyFn; Value createFillOrGenerateOp(RewriterBase &rewriter, tensor::PadOp padOp, Value dest, const SmallVector &dynSizes) const; @@ -1663,6 +1658,11 @@ void populateDecomposeConvolutionPatterns(RewritePatternSet &patterns, /// \see rewriteInIm2Col for more details. void populateConvertConv2DToImg2ColPatterns(RewritePatternSet &patterns); +/// Populates `patterns` with vectorisation patterns for tensor.insert_slice. +/// TODO: Avoid having a dedicated `populate{}` for one pattern. Instead, either +/// expand or merge with other `populate{}`. +void populateInsertSliceVectorizationPatterns(RewritePatternSet &patterns); + /// Populates `patterns` with patterns that vectorize tensor.pad. /// These patterns are meant to apply in a complementary fashion. Benefits /// are used to encode a certain ordering of pattern application. To avoid diff --git a/mlir/include/mlir/Dialect/MemRef/Utils/MemRefUtils.h b/mlir/include/mlir/Dialect/MemRef/Utils/MemRefUtils.h index ca3326dbbef519..a761a77a407e87 100644 --- a/mlir/include/mlir/Dialect/MemRef/Utils/MemRefUtils.h +++ b/mlir/include/mlir/Dialect/MemRef/Utils/MemRefUtils.h @@ -32,7 +32,8 @@ namespace memref { bool isStaticShapeAndContiguousRowMajor(MemRefType type); /// For a `memref` with `offset`, `sizes` and `strides`, returns the -/// offset and size to use for the linearized `memref`. +/// offset, size, and potentially the size padded at the front to use for the +/// linearized `memref`. /// - If the linearization is done for emulating load/stores of /// element type with bitwidth `srcBits` using element type with /// bitwidth `dstBits`, the linearized offset and size are @@ -42,9 +43,14 @@ bool isStaticShapeAndContiguousRowMajor(MemRefType type); /// index to use in the linearized `memref`. The linearized index /// is also scaled down by `dstBits`/`srcBits`. If `indices` is not provided /// 0, is returned for the linearized index. +/// - If the size of the load/store is smaller than the linearized memref +/// load/store, the memory region emulated is larger than the actual memory +/// region needed. `intraDataOffset` returns the element offset of the data +/// relevant at the beginning. struct LinearizedMemRefInfo { OpFoldResult linearizedOffset; OpFoldResult linearizedSize; + OpFoldResult intraDataOffset; }; std::pair getLinearizedMemRefOffsetAndSize( OpBuilder &builder, Location loc, int srcBits, int dstBits, diff --git a/mlir/include/mlir/Dialect/SCF/TransformOps/SCFTransformOps.td b/mlir/include/mlir/Dialect/SCF/TransformOps/SCFTransformOps.td index 20880d94a83cac..5dba8c5e57ba86 100644 --- a/mlir/include/mlir/Dialect/SCF/TransformOps/SCFTransformOps.td +++ b/mlir/include/mlir/Dialect/SCF/TransformOps/SCFTransformOps.td @@ -146,7 +146,7 @@ def LoopPeelOp : Op Value { + if (inputs.size() != 1) + return Value(); + + return builder.create(loc, resultType, inputs) + .getResult(0); + }; + + converter.addSourceMaterialization(materializeAsUnrealizedCast); + converter.addTargetMaterialization(materializeAsUnrealizedCast); + RewritePatternSet patterns(&getContext()); populateMemRefToEmitCConversionPatterns(patterns, converter); diff --git a/mlir/lib/Dialect/Bufferization/Transforms/FuncBufferizableOpInterfaceImpl.cpp b/mlir/lib/Dialect/Bufferization/Transforms/FuncBufferizableOpInterfaceImpl.cpp index 9fbe574ec392dc..6e91d3b89a7c79 100644 --- a/mlir/lib/Dialect/Bufferization/Transforms/FuncBufferizableOpInterfaceImpl.cpp +++ b/mlir/lib/Dialect/Bufferization/Transforms/FuncBufferizableOpInterfaceImpl.cpp @@ -82,7 +82,8 @@ getBufferizedFunctionArgType(FuncOp funcOp, int64_t index, /// Return the FuncOp called by `callOp`. static FuncOp getCalledFunction(CallOpInterface callOp) { - SymbolRefAttr sym = llvm::dyn_cast_if_present(callOp.getCallableForCallee()); + SymbolRefAttr sym = + llvm::dyn_cast_if_present(callOp.getCallableForCallee()); if (!sym) return nullptr; return dyn_cast_or_null( @@ -392,11 +393,11 @@ struct FuncOpInterface auto funcOp = cast(op); FunctionType funcType = funcOp.getFunctionType(); - // Construct the bufferized function type. + // Compute the argument types. SmallVector argTypes; for (const auto &it : llvm::enumerate(funcType.getInputs())) { Type argType = it.value(); - if (dyn_cast(argType)) { + if (isa(argType)) { argTypes.push_back( getBufferizedFunctionArgType(funcOp, it.index(), options)); continue; @@ -404,24 +405,33 @@ struct FuncOpInterface argTypes.push_back(argType); } - // Bodiless functions are assumed opaque and we cannot know the - // bufferization contract they want to enforce. As a consequence, only - // support functions that don't return any tensors atm. - if (funcOp.isExternal()) { - SmallVector retTypes; - for (Type resultType : funcType.getResults()) { - if (isa(resultType)) - return funcOp->emitError() << "cannot bufferize bodiless function " - << "that returns a tensor"; + // Compute the result types. + SmallVector retTypes; + for (Type resultType : funcType.getResults()) { + if (auto tensorType = dyn_cast(resultType)) { + BaseMemRefType resultType = options.functionArgTypeConverterFn( + tensorType, *options.defaultMemorySpaceFn(tensorType), funcOp, + options); retTypes.push_back(resultType); + continue; } - funcOp.setType(FunctionType::get(op->getContext(), argTypes, retTypes)); + retTypes.push_back(resultType); + } + + // Compute the new function type. + auto newFuncType = FunctionType::get(op->getContext(), argTypes, retTypes); + + // If the function has no body, set the new function type and we are done. + if (funcOp.isExternal()) { + funcOp.setType(newFuncType); return success(); } // TODO: Support functions with multiple returns. func::ReturnOp returnOp = getAssumedUniqueReturnOp(funcOp); assert(returnOp && "expected func with single return op"); + assert(returnOp->getNumOperands() == retTypes.size() && + "incorrect number of return values"); Location loc = returnOp.getLoc(); // 1. Bufferize every block. @@ -430,10 +440,10 @@ struct FuncOpInterface options))) return failure(); - // 2. For each result, keep track of which inplace argument it reuses. + // 2. Bufferize all operands of the return op. SmallVector returnValues; - for (OpOperand &returnOperand : returnOp->getOpOperands()) { - Value returnVal = returnOperand.get(); + for (auto [returnVal, bufferizedType] : + llvm::zip_equal(returnOp->getOperands(), retTypes)) { auto tensorType = dyn_cast(returnVal.getType()); rewriter.setInsertionPoint(returnOp); @@ -443,23 +453,17 @@ struct FuncOpInterface continue; } - // Note: If `inferFunctionResultLayout = true`, cast are later folded + // Note: If `inferFunctionResultLayout = true`, casts are later folded // away. - BaseMemRefType resultType = options.functionArgTypeConverterFn( - tensorType, *options.defaultMemorySpaceFn(tensorType), funcOp, - options); Value toMemrefOp = rewriter.create( - loc, resultType, returnVal); + loc, bufferizedType, returnVal); returnValues.push_back(toMemrefOp); } - // 3. Rewrite the terminator without the in-place bufferizable values. returnOp.getOperandsMutable().assign(returnValues); - // 4. Rewrite the FuncOp type to buffer form. - funcOp.setType(FunctionType::get(op->getContext(), argTypes, - ValueRange(returnValues).getTypes())); - + // 3. Set the new function type. + funcOp.setType(newFuncType); return success(); } diff --git a/mlir/lib/Dialect/Linalg/TransformOps/LinalgTransformOps.cpp b/mlir/lib/Dialect/Linalg/TransformOps/LinalgTransformOps.cpp index 3d3f0a93a3829b..9c0ab4f41b855a 100644 --- a/mlir/lib/Dialect/Linalg/TransformOps/LinalgTransformOps.cpp +++ b/mlir/lib/Dialect/Linalg/TransformOps/LinalgTransformOps.cpp @@ -256,6 +256,7 @@ void transform::ApplyFoldAddIntoDestPatternsOp::populatePatterns( void transform::ApplyPadVectorizationPatternsOp::populatePatterns( RewritePatternSet &patterns) { linalg::populatePadOpVectorizationPatterns(patterns); + linalg::populateInsertSliceVectorizationPatterns(patterns); } //===----------------------------------------------------------------------===// @@ -3482,6 +3483,9 @@ transform::VectorizeChildrenAndApplyPatternsOp::applyToOne( patterns.add(ctx); + // Add misc. vectorization patterns (e.g. for tensor.insert_slice) + linalg::populateInsertSliceVectorizationPatterns(patterns); + if (getVectorizePadding()) linalg::populatePadOpVectorizationPatterns(patterns); diff --git a/mlir/lib/Dialect/Linalg/Transforms/Transforms.cpp b/mlir/lib/Dialect/Linalg/Transforms/Transforms.cpp index 0fe096863d7b01..da5233049aaf69 100644 --- a/mlir/lib/Dialect/Linalg/Transforms/Transforms.cpp +++ b/mlir/lib/Dialect/Linalg/Transforms/Transforms.cpp @@ -973,12 +973,7 @@ GeneralizePadOpPattern::matchAndRewrite(tensor::PadOp padOp, padOp.getLoc(), staticSizes, resultType.getElementType(), dynSizes); Value fill = createFillOrGenerateOp(rewriter, padOp, emptyTensor, dynSizes); - // Try optimize the copy of source. - if (optimizeCopyFn && optimizeCopyFn(rewriter, padOp, fill).succeeded()) - return success(); - - // tensor::PadOps cannot be optimized. Generate a InsertSliceOp instead - // for copying the PadOp source. + // Generate a InsertSliceOp for copying the PadOp source. auto sourceType = padOp.getSourceType(); // Compute size of source of tensor::PadOp. SmallVector srcSizes = diff --git a/mlir/lib/Dialect/Linalg/Transforms/Vectorization.cpp b/mlir/lib/Dialect/Linalg/Transforms/Vectorization.cpp index 0a2457176a1d47..090e0b46768d7e 100644 --- a/mlir/lib/Dialect/Linalg/Transforms/Vectorization.cpp +++ b/mlir/lib/Dialect/Linalg/Transforms/Vectorization.cpp @@ -2281,115 +2281,6 @@ LogicalResult mlir::linalg::vectorizeCopy(RewriterBase &rewriter, //----------------------------------------------------------------------------// // Misc. vectorization patterns. //----------------------------------------------------------------------------// - -/// Helper function that retrieves the value of an IntegerAttr. -static int64_t getIntFromAttr(Attribute attr) { - return cast(attr).getInt(); -} - -/// Given an ArrayRef of OpFoldResults, return a vector of Values. -/// IntegerAttrs are converted to ConstantIndexOps. Other attribute types are -/// not supported. -static SmallVector ofrToIndexValues(RewriterBase &rewriter, Location loc, - ArrayRef ofrs) { - SmallVector result; - for (auto o : ofrs) { - if (auto val = llvm::dyn_cast_if_present(o)) { - result.push_back(val); - } else { - result.push_back(rewriter.create( - loc, getIntFromAttr(o.template get()))); - } - } - return result; -} - -/// Rewrite a tensor::PadOp into a sequence of EmptyOp, FillOp and -/// InsertSliceOp. For now, only constant padding values are supported. -/// If there is enough static type information, TransferReadOps and -/// TransferWriteOps may be generated instead of InsertSliceOps. -struct GenericPadOpVectorizationPattern : public GeneralizePadOpPattern { - GenericPadOpVectorizationPattern(MLIRContext *context, - PatternBenefit benefit = 1) - : GeneralizePadOpPattern(context, tryVectorizeCopy, benefit) {} - /// Vectorize the copying of a tensor::PadOp's source. This is possible if - /// each dimension size is statically know in the source type or the result - /// type (or both). - static LogicalResult tryVectorizeCopy(RewriterBase &rewriter, - tensor::PadOp padOp, Value dest) { - auto sourceType = padOp.getSourceType(); - auto resultType = padOp.getResultType(); - if (!VectorType::isValidElementType(sourceType.getElementType())) - return failure(); - - // Copy cannot be vectorized if pad value is non-constant and source shape - // is dynamic. In case of a dynamic source shape, padding must be appended - // by TransferReadOp, but TransferReadOp supports only constant padding. - auto padValue = padOp.getConstantPaddingValue(); - if (!padValue) { - if (!sourceType.hasStaticShape()) - return failure(); - // Create dummy padding value. - auto elemType = sourceType.getElementType(); - padValue = rewriter.create( - padOp.getLoc(), elemType, rewriter.getZeroAttr(elemType)); - } - - SmallVector vecShape; - SmallVector readInBounds; - SmallVector writeInBounds; - for (unsigned i = 0; i < sourceType.getRank(); ++i) { - if (!sourceType.isDynamicDim(i)) { - vecShape.push_back(sourceType.getDimSize(i)); - // Source shape is statically known: Neither read nor write are - // out-of- bounds. - readInBounds.push_back(true); - writeInBounds.push_back(true); - } else if (!resultType.isDynamicDim(i)) { - // Source shape is not statically known, but result shape is. - // Vectorize with size of result shape. This may be larger than the - // source size. - vecShape.push_back(resultType.getDimSize(i)); - // Read may be out-of-bounds because the result size could be larger - // than the source size. - readInBounds.push_back(false); - // Write is out-of-bounds if low padding > 0. - writeInBounds.push_back( - getConstantIntValue(padOp.getMixedLowPad()[i]) == - static_cast(0)); - } else { - // Neither source nor result dim of padOp is static. Cannot vectorize - // the copy. - return failure(); - } - } - auto vecType = VectorType::get(vecShape, sourceType.getElementType()); - - // Generate TransferReadOp. - SmallVector readIndices( - vecType.getRank(), - rewriter.create(padOp.getLoc(), 0)); - auto read = rewriter.create( - padOp.getLoc(), vecType, padOp.getSource(), readIndices, padValue, - ArrayRef{readInBounds}); - - // If `dest` is a FillOp and the TransferWriteOp would overwrite the - // entire tensor, write directly to the FillOp's operand. - if (llvm::equal(vecShape, resultType.getShape()) && - llvm::all_of(writeInBounds, [](bool b) { return b; })) - if (auto fill = dest.getDefiningOp()) - dest = fill.output(); - - // Generate TransferWriteOp. - auto writeIndices = - ofrToIndexValues(rewriter, padOp.getLoc(), padOp.getMixedLowPad()); - rewriter.replaceOpWithNewOp( - padOp, read, dest, writeIndices, ArrayRef{writeInBounds}); - - return success(); - } -}; - /// Base pattern for rewriting tensor::PadOps whose result is consumed by a /// given operation type OpTy. template @@ -2623,6 +2514,163 @@ struct PadOpVectorizationWithTransferWritePattern } }; +/// Returns the effective Pad value for the input op, provided it's a scalar. +/// +/// Many Ops exhibit pad-like behaviour, but this isn't always explicit. If +/// this Op performs padding, retrieve the padding value provided that it's +/// a scalar and static/fixed for all the padded values. Returns an empty value +/// otherwise. +static Value getStaticPadVal(Operation *op) { + if (!op) + return {}; + + // 1. vector.broadcast (f32 -> vector <...xf32>) - return the value that's + // being broadcast, provided that it's a scalar. + if (auto bcast = llvm::dyn_cast(op)) { + auto source = bcast.getSource(); + if (llvm::dyn_cast(source.getType())) + return {}; + + return source; + } + + // 2. linalg.fill - use the scalar input value that used to fill the output + // tensor. + if (auto fill = llvm::dyn_cast(op)) { + return fill.getInputs()[0]; + } + + // 3. tensor.generateOp - can't guarantee the value is fixed without + // analysing, bail out. + if (auto generate = llvm::dyn_cast(op)) { + return {}; + } + + // 4. vector.transfer_write - inspect the input vector that's written from. If + // if contains a single value that has been broadcast (e.g. via + // vector.broadcast), extract it, fail otherwise. + if (auto xferWrite = llvm::dyn_cast(op)) + return getStaticPadVal(xferWrite.getVector().getDefiningOp()); + + // 5. tensor.insert_slice - inspect the destination tensor. If it's larger + // than the input tensor, then, provided it's constant, we'll extract the + // value that was used to generate it (via e.g. linalg.fill), fail otherwise. + // TODO: Clarify the semantics when the input tensor is larger than the + // destination. + if (auto slice = llvm::dyn_cast(op)) + return getStaticPadVal(slice.getDest().getDefiningOp()); + + return {}; +} + +/// Rewrite tensor.insert.slice as a vector.transfer_read + +/// vector.transfer_write pair. The vector size is inferred from the static +/// dims in the input and output tensors. If a dim is dynamic in both the input +/// and output tensors, bails out. +/// +/// Before: +/// !t_in_type = tensor<1x2x3xf32> +/// !t_out_type = tensor<9x8x7x1x2x3xf32> +/// !v_type = vector<1x2x3xf32> +/// %inserted_slice = tensor.insert_slice %src into %dest ... : !t_in_type +/// into !t_out_type +/// After: +/// %read = vector.transfer_read %src[...], %pad ... : !t_in_type, !v_type +/// %write = vector.transfer_write %read, %dest ... : !v_type, !t_out_type +/// +/// TODO: Support masking +struct InsertSliceVectorizePattern + : public OpRewritePattern { + using OpRewritePattern::OpRewritePattern; + + LogicalResult matchAndRewrite(tensor::InsertSliceOp sliceOp, + PatternRewriter &rewriter) const final { + auto sourceType = sliceOp.getSource().getType(); + if (!VectorType::isValidElementType(sourceType.getElementType())) + return failure(); + + auto resultType = sliceOp.getResultType(); + + // 1. Get the pad value. + // TransferReadOp requires a scalar padding value. Note that: + // * for in-bounds access, the value is actually irrelevant. + // There are 2 cases in which xfer.read accesses are known to be in-bounds: + // 1. The source shape is static (output vector sizes would be based on + // the source shape and hence all memory accesses would be in-bounds), + // 2. Masking is used (output vector sizes would be user-provided, in which + // case it is assumed that all memory accesses are in-bounds). This + // remains a TODO. + // + // When the value is not known and not needed, use 0. Otherwise, bail out. + Value padValue = getStaticPadVal(sliceOp); + bool isOutOfBoundsRead = !sourceType.hasStaticShape(); + + if (!padValue && isOutOfBoundsRead) { + LDBG("Failed to get a pad value for out-of-bounds read access\n"); + return failure(); + } + + if (!padValue) { + auto elemType = sourceType.getElementType(); + padValue = rewriter.create( + sliceOp.getLoc(), elemType, rewriter.getZeroAttr(elemType)); + } + + // 2. Get the vector shape and in-bounds attributes + SmallVector vecShape; + SmallVector readInBounds; + SmallVector writeInBounds; + size_t rankDiff = resultType.getRank() - sourceType.getRank(); + for (unsigned i = 0; i < sourceType.getRank(); ++i) { + if (!sourceType.isDynamicDim(i)) { + vecShape.push_back(sourceType.getDimSize(i)); + // Source shape is statically known: Neither read nor write are + // out-of-bounds. + readInBounds.push_back(true); + writeInBounds.push_back(true); + } else if (!resultType.isDynamicDim(i)) { + // Source shape is not statically known, but result shape is. + // Vectorize with size of result shape. This may be larger than the + // source size. + // FIXME: Using rankDiff implies that the source tensor is inserted at + // the end of the destination tensor. However, that's not required. + vecShape.push_back(resultType.getDimSize(rankDiff + i)); + // Read may be out-of-bounds because the result size could be larger + // than the source size. + readInBounds.push_back(false); + // Write will in-bounds provided that the corresponding write idx is 0. + // To keep this logic simple, conservatively mark as out-of-bounds. + writeInBounds.push_back(false); + } else { + // Neither source nor result dim of padOp is static. Cannot vectorize + // the copy. + // TODO: Add support for masking + return failure(); + } + } + auto vecType = VectorType::get(vecShape, sourceType.getElementType()); + + // 3. Generate TransferReadOp. + SmallVector readIndices( + vecType.getRank(), + rewriter.create(sliceOp.getLoc(), 0)); + auto read = rewriter.create( + sliceOp.getLoc(), vecType, sliceOp.getSource(), readIndices, padValue, + ArrayRef{readInBounds}); + + // 4. Generate TransferWriteOp. + auto writeIndices = getValueOrCreateConstantIndexOp( + rewriter, sliceOp.getLoc(), sliceOp.getMixedOffsets()); + + // 5. Finalize + rewriter.replaceOpWithNewOp( + sliceOp, read, sliceOp.getDest(), writeIndices, + ArrayRef{writeInBounds}); + + return success(); + } +}; + /// Rewrite use of tensor::PadOp result in InsertSliceOp. E.g.: /// ``` /// %0 = tensor.pad %src ... : tensor to tensor<17x5xf32> @@ -2699,8 +2747,8 @@ struct PadOpVectorizationWithInsertSlicePattern // Generate TransferWriteOp: Write to InsertSliceOp's dest tensor at // specified offsets. Write is fully in-bounds because a InsertSliceOp's // source must fit into the destination at the specified offsets. - auto writeIndices = - ofrToIndexValues(rewriter, padOp.getLoc(), insertOp.getMixedOffsets()); + auto writeIndices = getValueOrCreateConstantIndexOp( + rewriter, padOp.getLoc(), insertOp.getMixedOffsets()); SmallVector inBounds(vecRank, true); rewriter.replaceOpWithNewOp( insertOp, read, insertOp.getDest(), writeIndices, @@ -2710,13 +2758,18 @@ struct PadOpVectorizationWithInsertSlicePattern } }; +void mlir::linalg::populateInsertSliceVectorizationPatterns( + RewritePatternSet &patterns) { + patterns.add(patterns.getContext()); +} + void mlir::linalg::populatePadOpVectorizationPatterns( RewritePatternSet &patterns, PatternBenefit baseBenefit) { // TODO: The following pattern implements "decomposition" and // optional "vectorization". Seperate "decomposition" into a sepereate // pre-processing pattern group. - patterns.add(patterns.getContext(), - baseBenefit); + patterns.add(patterns.getContext(), baseBenefit); + // Try these specialized patterns first before resorting to the generic one. patterns.add getLinearizedMemRefOffsetAndSize( // Adjust linearizedIndices and size by the scale factor (dstBits / srcBits). int64_t scaler = dstBits / srcBits; - addMulMap = addMulMap.floorDiv(scaler); mulMap = mulMap.floorDiv(scaler); OpFoldResult linearizedIndices = affine::makeComposedFoldedAffineApply( - builder, loc, addMulMap, offsetValues); + builder, loc, addMulMap.floorDiv(scaler), offsetValues); OpFoldResult linearizedSize = affine::makeComposedFoldedAffineApply(builder, loc, mulMap, sizes); @@ -95,7 +94,11 @@ std::pair getLinearizedMemRefOffsetAndSize( OpFoldResult adjustBaseOffset = affine::makeComposedFoldedAffineApply( builder, loc, s0.floorDiv(scaler), {offset}); - return {{adjustBaseOffset, linearizedSize}, linearizedIndices}; + OpFoldResult intraVectorOffset = affine::makeComposedFoldedAffineApply( + builder, loc, addMulMap % scaler, offsetValues); + + return {{adjustBaseOffset, linearizedSize, intraVectorOffset}, + linearizedIndices}; } LinearizedMemRefInfo diff --git a/mlir/lib/Dialect/SCF/Transforms/LoopSpecialization.cpp b/mlir/lib/Dialect/SCF/Transforms/LoopSpecialization.cpp index a30e349d49136c..5104ad4b3a3038 100644 --- a/mlir/lib/Dialect/SCF/Transforms/LoopSpecialization.cpp +++ b/mlir/lib/Dialect/SCF/Transforms/LoopSpecialization.cpp @@ -206,12 +206,11 @@ LogicalResult mlir::scf::peelForLoopAndSimplifyBounds(RewriterBase &rewriter, return success(); } -/// When the `peelFront` option is set as true, the first iteration of the loop -/// is peeled off. This function rewrites the original scf::ForOp as two -/// scf::ForOp Ops, the first scf::ForOp corresponds to the first iteration of -/// the loop which can be canonicalized away in the following optimization. The -/// second loop Op contains the remaining iteration, and the new lower bound is -/// the original lower bound plus the number of steps. +/// Rewrites the original scf::ForOp as two scf::ForOp Ops, the first +/// scf::ForOp corresponds to the first iteration of the loop which can be +/// canonicalized away in the following optimizations. The second loop Op +/// contains the remaining iterations, with a lower bound updated as the +/// original lower bound plus the step (i.e. skips the first iteration). LogicalResult mlir::scf::peelForLoopFirstIteration(RewriterBase &b, ForOp forOp, ForOp &firstIteration) { RewriterBase::InsertionGuard guard(b); diff --git a/mlir/lib/Dialect/Vector/IR/VectorOps.cpp b/mlir/lib/Dialect/Vector/IR/VectorOps.cpp index d71a236f62f454..1853ae04f45d90 100644 --- a/mlir/lib/Dialect/Vector/IR/VectorOps.cpp +++ b/mlir/lib/Dialect/Vector/IR/VectorOps.cpp @@ -2951,11 +2951,11 @@ void InsertOp::getCanonicalizationPatterns(RewritePatternSet &results, InsertOpConstantFolder>(context); } -// Eliminates insert operations that produce values identical to their source -// value. This happens when the source and destination vectors have identical -// sizes. OpFoldResult vector::InsertOp::fold(FoldAdaptor adaptor) { - if (getNumIndices() == 0) + // Fold "vector.insert %v, %dest [] : vector<2x2xf32> from vector<2x2xf32>" to + // %v. Note: Do not fold "vector.insert %v, %dest [] : f32 into vector" + // (type mismatch). + if (getNumIndices() == 0 && getSourceType() == getType()) return getSource(); return {}; } diff --git a/mlir/lib/Dialect/Vector/Transforms/VectorEmulateNarrowType.cpp b/mlir/lib/Dialect/Vector/Transforms/VectorEmulateNarrowType.cpp index 66362d3ca70fb6..1d6f8a991d9b5b 100644 --- a/mlir/lib/Dialect/Vector/Transforms/VectorEmulateNarrowType.cpp +++ b/mlir/lib/Dialect/Vector/Transforms/VectorEmulateNarrowType.cpp @@ -13,6 +13,7 @@ #include "mlir/Dialect/Arith/Utils/Utils.h" #include "mlir/Dialect/MemRef/IR/MemRef.h" #include "mlir/Dialect/MemRef/Utils/MemRefUtils.h" +#include "mlir/Dialect/Utils/StaticValueUtils.h" #include "mlir/Dialect/Vector/IR/VectorOps.h" #include "mlir/Dialect/Vector/Transforms/VectorRewritePatterns.h" #include "mlir/IR/BuiltinAttributes.h" @@ -22,8 +23,10 @@ #include "mlir/Transforms/DialectConversion.h" #include "llvm/ADT/SmallVector.h" #include "llvm/Support/Debug.h" +#include "llvm/Support/MathExtras.h" #include "llvm/Support/raw_ostream.h" #include +#include using namespace mlir; @@ -33,17 +36,22 @@ using namespace mlir; #define LDBG(X) LLVM_DEBUG(DBGS() << X << "\n") /// Returns a compressed mask. The mask value is set only if any mask is present -/// in the scale range. E.g., if `scale` equals to 2, the following mask: +/// in the scale range. E.g., if `scale` equals to 2, and `intraDataOffset` +/// equals to 2, the following mask: /// /// %mask = [1, 1, 1, 0, 0, 0] /// -/// will return the following new compressed mask: +/// will first be padded with number of `intraDataOffset` zeros: +/// %mask = [0, 0, 1, 1, 1, 0, 0, 0] /// -/// %mask = [1, 1, 0] +/// then it will return the following new compressed mask: +/// +/// %mask = [0, 1, 1, 0] static FailureOr getCompressedMaskOp(OpBuilder &rewriter, Location loc, Value mask, - int origElements, int scale) { - auto numElements = (origElements + scale - 1) / scale; + int origElements, int scale, + int intraDataOffset = 0) { + auto numElements = (intraDataOffset + origElements + scale - 1) / scale; Operation *maskOp = mask.getDefiningOp(); SmallVector extractOps; @@ -67,6 +75,9 @@ static FailureOr getCompressedMaskOp(OpBuilder &rewriter, shape.back() = numElements; auto newMaskType = VectorType::get(shape, rewriter.getI1Type()); if (createMaskOp) { + // TODO: handle the case with non-zero intraDataOffset for CreateMaskOp. + if (intraDataOffset != 0) + return failure(); OperandRange maskOperands = createMaskOp.getOperands(); size_t numMaskOperands = maskOperands.size(); AffineExpr s0; @@ -86,11 +97,27 @@ static FailureOr getCompressedMaskOp(OpBuilder &rewriter, ArrayRef maskDimSizes = constantMaskOp.getMaskDimSizes(); size_t numMaskOperands = maskDimSizes.size(); int64_t origIndex = maskDimSizes[numMaskOperands - 1]; - int64_t maskIndex = (origIndex + scale - 1) / scale; + int64_t startIndex = intraDataOffset / scale; + int64_t maskIndex = llvm::divideCeil(intraDataOffset + origIndex, scale); + + // TODO: we only want the mask between [startIndex, maskIndex] to be true, + // the rest are false. + if (intraDataOffset != 0 && maskDimSizes.size() > 1) + return failure(); + SmallVector newMaskDimSizes(maskDimSizes.drop_back()); newMaskDimSizes.push_back(maskIndex); - newMask = rewriter.create(loc, newMaskType, - newMaskDimSizes); + + if (intraDataOffset == 0) { + newMask = rewriter.create(loc, newMaskType, + newMaskDimSizes); + } else { + SmallVector newMaskValues; + for (int64_t i = 0; i < numElements; ++i) + newMaskValues.push_back(i >= startIndex && i < maskIndex); + auto denseAttr = DenseElementsAttr::get(newMaskType, newMaskValues); + newMask = rewriter.create(loc, newMaskType, denseAttr); + } } while (!extractOps.empty()) { @@ -102,6 +129,26 @@ static FailureOr getCompressedMaskOp(OpBuilder &rewriter, return newMask; } +static Value extractSubvectorFrom(RewriterBase &rewriter, Location loc, + VectorType extractType, Value vector, + int64_t frontOffset, int64_t subvecSize) { + auto offsets = rewriter.getI64ArrayAttr({frontOffset}); + auto sizes = rewriter.getI64ArrayAttr({subvecSize}); + auto strides = rewriter.getI64ArrayAttr({1}); + return rewriter + .create(loc, extractType, vector, offsets, + sizes, strides) + ->getResult(0); +} + +static Value insertSubvectorInto(RewriterBase &rewriter, Location loc, + Value src, Value dest, int64_t offset) { + auto offsets = rewriter.getI64ArrayAttr({offset}); + auto strides = rewriter.getI64ArrayAttr({1}); + return rewriter.create(loc, dest.getType(), src, + dest, offsets, strides); +} + namespace { //===----------------------------------------------------------------------===// @@ -201,7 +248,8 @@ struct ConvertVectorMaskedStore final auto stridedMetadata = rewriter.create(loc, op.getBase()); OpFoldResult linearizedIndicesOfr; - std::tie(std::ignore, linearizedIndicesOfr) = + memref::LinearizedMemRefInfo linearizedInfo; + std::tie(linearizedInfo, linearizedIndicesOfr) = memref::getLinearizedMemRefOffsetAndSize( rewriter, loc, srcBits, dstBits, stridedMetadata.getConstifiedMixedOffset(), @@ -214,19 +262,19 @@ struct ConvertVectorMaskedStore final // Load the whole data and use arith.select to handle the corner cases. // E.g., given these input values: // - // %mask = [1, 1, 1, 0, 0, 0] - // %0[%c0, %c0] contains [0x1, 0x2, 0x3, 0x4, 0x5, 0x6] - // %value_to_store = [0x7, 0x8, 0x9, 0xA, 0xB, 0xC] + // %mask = [0, 1, 1, 1, 1, 1, 0, 0] + // %0[%c0, %c0] contains [0x1, 0x2, 0x3, 0x4, 0x5, 0x6, 0x7, 0x8] + // %value_to_store = [0x9, 0xA, 0xB, 0xC, 0xD, 0xE, 0xF, 0x0] // // we'll have // - // expected output: [0x7, 0x8, 0x9, 0x4, 0x5, 0x6] + // expected output: [0x1, 0xA, 0xB, 0xC, 0xD, 0xE, 0x7, 0x8] // - // %new_mask = [1, 1, 0] - // %maskedload = [0x12, 0x34, 0x0] - // %bitcast = [0x1, 0x2, 0x3, 0x4, 0x0, 0x0] - // %select_using_original_mask = [0x7, 0x8, 0x9, 0x4, 0x0, 0x0] - // %packed_data = [0x78, 0x94, 0x00] + // %new_mask = [1, 1, 1, 0] + // %maskedload = [0x12, 0x34, 0x56, 0x00] + // %bitcast = [0x1, 0x2, 0x3, 0x4, 0x5, 0x6, 0x0, 0x0] + // %select_using_shifted_mask = [0x1, 0xA, 0xB, 0xC, 0xD, 0xE, 0x0, 0x0] + // %packed_data = [0x1A, 0xBC, 0xDE, 0x00] // // Using the new mask to store %packed_data results in expected output. FailureOr newMask = @@ -243,8 +291,9 @@ struct ConvertVectorMaskedStore final loc, newType, adaptor.getBase(), linearizedIndices, newMask.value()->getResult(0), passThru); - Value valueToStore = rewriter.create( - loc, op.getValueToStore().getType(), newLoad); + auto newBitCastType = VectorType::get(numElements * scale, oldElementType); + Value valueToStore = + rewriter.create(loc, newBitCastType, newLoad); valueToStore = rewriter.create( loc, op.getMask(), op.getValueToStore(), valueToStore); valueToStore = @@ -294,19 +343,31 @@ struct ConvertVectorLoad final : OpConversionPattern { // %1 = vector.load %0[%linear_index] : memref<6xi8>, vector<2xi8> // %2 = vector.bitcast %1 : vector<2xi8> to vector<4xi4> // - // TODO: Currently, only the even number of elements loading is supported. - // To deal with the odd number of elements, one has to extract the - // subvector at the proper offset after bit-casting. + // There are cases where the number of elements to load is not byte-aligned, + // for example: + // + // %1 = vector.load %0[%c1, %c0] : memref<3x3xi2>, vector<3xi2> + // + // we will have to load extra bytes and extract the exact slice in between. + // + // %1 = vector.load %0[%c2] : memref<3xi8>, vector<2xi8> + // %2 = vector.bitcast %1 : vector<2xi8> to vector<8xi2> + // %3 = vector.extract_strided_slice %1 {offsets = [2], sizes = [3], strides + // = [1]} + // : vector<8xi2> to vector<3xi2> + // + // TODO: Currently the extract_strided_slice's attributes must be known at + // compile time as they must be constants. auto origElements = op.getVectorType().getNumElements(); - if (origElements % scale != 0) - return failure(); + bool isUnalignedEmulation = origElements % scale != 0; auto stridedMetadata = rewriter.create(loc, op.getBase()); OpFoldResult linearizedIndices; - std::tie(std::ignore, linearizedIndices) = + memref::LinearizedMemRefInfo linearizedInfo; + std::tie(linearizedInfo, linearizedIndices) = memref::getLinearizedMemRefOffsetAndSize( rewriter, loc, srcBits, dstBits, stridedMetadata.getConstifiedMixedOffset(), @@ -314,15 +375,31 @@ struct ConvertVectorLoad final : OpConversionPattern { stridedMetadata.getConstifiedMixedStrides(), getAsOpFoldResult(adaptor.getIndices())); - auto numElements = (origElements + scale - 1) / scale; + std::optional foldedIntraVectorOffset = + isUnalignedEmulation + ? getConstantIntValue(linearizedInfo.intraDataOffset) + : 0; + + if (!foldedIntraVectorOffset) { + // unimplemented case for dynamic intra vector offset + return failure(); + } + + auto numElements = + llvm::divideCeil(*foldedIntraVectorOffset + origElements, scale); auto newLoad = rewriter.create( loc, VectorType::get(numElements, newElementType), adaptor.getBase(), getValueOrCreateConstantIndexOp(rewriter, loc, linearizedIndices)); - auto bitCast = - rewriter.create(loc, op.getType(), newLoad); + Value result = rewriter.create( + loc, VectorType::get(numElements * scale, oldElementType), newLoad); - rewriter.replaceOp(op, bitCast->getResult(0)); + if (isUnalignedEmulation) { + result = extractSubvectorFrom(rewriter, loc, op.getType(), result, + *foldedIntraVectorOffset, origElements); + } + + rewriter.replaceOp(op, result); return success(); } }; @@ -396,13 +473,13 @@ struct ConvertVectorMaskedLoad final // subvector at the proper offset after bit-casting. auto origType = op.getVectorType(); auto origElements = origType.getNumElements(); - if (origElements % scale != 0) - return failure(); + bool isUnalignedEmulation = origElements % scale != 0; auto stridedMetadata = rewriter.create(loc, op.getBase()); OpFoldResult linearizedIndices; - std::tie(std::ignore, linearizedIndices) = + memref::LinearizedMemRefInfo linearizedInfo; + std::tie(linearizedInfo, linearizedIndices) = memref::getLinearizedMemRefOffsetAndSize( rewriter, loc, srcBits, dstBits, stridedMetadata.getConstifiedMixedOffset(), @@ -410,29 +487,68 @@ struct ConvertVectorMaskedLoad final stridedMetadata.getConstifiedMixedStrides(), getAsOpFoldResult(adaptor.getIndices())); + std::optional foldedIntraVectorOffset = + isUnalignedEmulation + ? getConstantIntValue(linearizedInfo.intraDataOffset) + : 0; + + if (!foldedIntraVectorOffset) { + // unimplemented case for dynamic intra vector offset + return failure(); + } + FailureOr newMask = - getCompressedMaskOp(rewriter, loc, op.getMask(), origElements, scale); + getCompressedMaskOp(rewriter, loc, op.getMask(), origElements, scale, + *foldedIntraVectorOffset); if (failed(newMask)) return failure(); - auto numElements = (origElements + scale - 1) / scale; - auto newType = VectorType::get(numElements, newElementType); + auto numElements = + llvm::divideCeil(*foldedIntraVectorOffset + origElements, scale); + auto loadType = VectorType::get(numElements, newElementType); + auto newBitcastType = VectorType::get(numElements * scale, oldElementType); + + Value passthru = op.getPassThru(); + if (isUnalignedEmulation) { + // create an empty vector of the new type + auto emptyVector = rewriter.create( + loc, newBitcastType, rewriter.getZeroAttr(newBitcastType)); + passthru = insertSubvectorInto(rewriter, loc, passthru, emptyVector, + *foldedIntraVectorOffset); + } auto newPassThru = - rewriter.create(loc, newType, op.getPassThru()); + rewriter.create(loc, loadType, passthru); // Generating the new masked load. auto newLoad = rewriter.create( - loc, newType, adaptor.getBase(), + loc, loadType, adaptor.getBase(), getValueOrCreateConstantIndexOp(rewriter, loc, linearizedIndices), newMask.value()->getResult(0), newPassThru); // Setting the part that originally was not effectively loaded from memory // to pass through. auto bitCast = - rewriter.create(loc, op.getType(), newLoad); - auto select = rewriter.create(loc, op.getMask(), bitCast, - op.getPassThru()); - rewriter.replaceOp(op, select->getResult(0)); + rewriter.create(loc, newBitcastType, newLoad); + + Value mask = op.getMask(); + if (isUnalignedEmulation) { + auto newSelectMaskType = + VectorType::get(numElements * scale, rewriter.getI1Type()); + // TODO: can fold if op's mask is constant + auto emptyVector = rewriter.create( + loc, newSelectMaskType, rewriter.getZeroAttr(newSelectMaskType)); + mask = insertSubvectorInto(rewriter, loc, op.getMask(), emptyVector, + *foldedIntraVectorOffset); + } + + Value result = + rewriter.create(loc, mask, bitCast, passthru); + + if (isUnalignedEmulation) { + result = extractSubvectorFrom(rewriter, loc, op.getType(), result, + *foldedIntraVectorOffset, origElements); + } + rewriter.replaceOp(op, result); return success(); } @@ -464,8 +580,8 @@ struct ConvertVectorTransferRead final int scale = dstBits / srcBits; auto origElements = op.getVectorType().getNumElements(); - if (origElements % scale != 0) - return failure(); + + bool isUnalignedEmulation = origElements % scale != 0; auto newPadding = rewriter.create(loc, newElementType, adaptor.getPadding()); @@ -474,7 +590,8 @@ struct ConvertVectorTransferRead final rewriter.create(loc, op.getSource()); OpFoldResult linearizedIndices; - std::tie(std::ignore, linearizedIndices) = + memref::LinearizedMemRefInfo linearizedInfo; + std::tie(linearizedInfo, linearizedIndices) = memref::getLinearizedMemRefOffsetAndSize( rewriter, loc, srcBits, dstBits, stridedMetadata.getConstifiedMixedOffset(), @@ -482,18 +599,34 @@ struct ConvertVectorTransferRead final stridedMetadata.getConstifiedMixedStrides(), getAsOpFoldResult(adaptor.getIndices())); - auto numElements = (origElements + scale - 1) / scale; - auto newReadType = VectorType::get(numElements, newElementType); + std::optional foldedIntraVectorOffset = + isUnalignedEmulation + ? getConstantIntValue(linearizedInfo.intraDataOffset) + : 0; + + if (!foldedIntraVectorOffset) { + // unimplemented case for dynamic inra-vector offset + return failure(); + } + + auto numElements = + llvm::divideCeil(*foldedIntraVectorOffset + origElements, scale); auto newRead = rewriter.create( - loc, newReadType, adaptor.getSource(), + loc, VectorType::get(numElements, newElementType), adaptor.getSource(), getValueOrCreateConstantIndexOp(rewriter, loc, linearizedIndices), newPadding); - auto bitCast = - rewriter.create(loc, op.getType(), newRead); + auto bitCast = rewriter.create( + loc, VectorType::get(numElements * scale, oldElementType), newRead); + + Value result = bitCast->getResult(0); + if (isUnalignedEmulation) { + result = extractSubvectorFrom(rewriter, loc, op.getType(), result, + *foldedIntraVectorOffset, origElements); + } + rewriter.replaceOp(op, result); - rewriter.replaceOp(op, bitCast->getResult(0)); return success(); } }; diff --git a/mlir/lib/Interfaces/Utils/InferIntRangeCommon.cpp b/mlir/lib/Interfaces/Utils/InferIntRangeCommon.cpp index ec9ed87723e1cc..a2acf3e732adab 100644 --- a/mlir/lib/Interfaces/Utils/InferIntRangeCommon.cpp +++ b/mlir/lib/Interfaces/Utils/InferIntRangeCommon.cpp @@ -298,8 +298,14 @@ static ConstantIntRanges inferDivURange(const ConstantIntRanges &lhs, return minMaxBy(udiv, {lhsMin, lhsMax}, {rhsMin, rhsMax}, /*isSigned=*/false); } - // Otherwise, it's possible we might divide by 0. - return ConstantIntRanges::maxRange(rhsMin.getBitWidth()); + + APInt umin = APInt::getZero(rhsMin.getBitWidth()); + if (lhsMin.uge(rhsMax) && !rhsMax.isZero()) + umin = lhsMin.udiv(rhsMax); + + // X u/ Y u<= X. + APInt umax = lhsMax; + return ConstantIntRanges::fromUnsigned(umin, umax); } ConstantIntRanges diff --git a/mlir/lib/Target/LLVMIR/Dialect/OpenMP/OpenMPToLLVMIRTranslation.cpp b/mlir/lib/Target/LLVMIR/Dialect/OpenMP/OpenMPToLLVMIRTranslation.cpp index fc2f88b766f1c5..d20e5e40076bc3 100644 --- a/mlir/lib/Target/LLVMIR/Dialect/OpenMP/OpenMPToLLVMIRTranslation.cpp +++ b/mlir/lib/Target/LLVMIR/Dialect/OpenMP/OpenMPToLLVMIRTranslation.cpp @@ -262,6 +262,62 @@ static llvm::omp::ProcBindKind getProcBindKind(omp::ClauseProcBindKind kind) { llvm_unreachable("Unknown ClauseProcBindKind kind"); } +/// Helper function to map block arguments defined by ignored loop wrappers to +/// LLVM values and prevent any uses of those from triggering null pointer +/// dereferences. +/// +/// This must be called after block arguments of parent wrappers have already +/// been mapped to LLVM IR values. +static LogicalResult +convertIgnoredWrapper(omp::LoopWrapperInterface &opInst, + LLVM::ModuleTranslation &moduleTranslation) { + // Map block arguments directly to the LLVM value associated to the + // corresponding operand. This is semantically equivalent to this wrapper not + // being present. + auto forwardArgs = + [&moduleTranslation](llvm::ArrayRef blockArgs, + OperandRange operands) { + for (auto [arg, var] : llvm::zip_equal(blockArgs, operands)) + moduleTranslation.mapValue(arg, moduleTranslation.lookupValue(var)); + }; + + return llvm::TypeSwitch(opInst) + .Case([&](omp::SimdOp op) { + auto blockArgIface = cast(*op); + forwardArgs(blockArgIface.getPrivateBlockArgs(), op.getPrivateVars()); + forwardArgs(blockArgIface.getReductionBlockArgs(), + op.getReductionVars()); + return success(); + }) + .Default([&](Operation *op) { + return op->emitError() << "cannot ignore nested wrapper"; + }); +} + +/// Helper function to call \c convertIgnoredWrapper() for all wrappers of the +/// given \c loopOp nested inside of \c parentOp. This has the effect of mapping +/// entry block arguments defined by these operations to outside values. +/// +/// It must be called after block arguments of \c parentOp have already been +/// mapped themselves. +static LogicalResult +convertIgnoredWrappers(omp::LoopNestOp loopOp, + omp::LoopWrapperInterface parentOp, + LLVM::ModuleTranslation &moduleTranslation) { + SmallVector wrappers; + loopOp.gatherWrappers(wrappers); + + // Process wrappers nested inside of `parentOp` from outermost to innermost. + for (auto it = + std::next(std::find(wrappers.rbegin(), wrappers.rend(), parentOp)); + it != wrappers.rend(); ++it) { + if (failed(convertIgnoredWrapper(*it, moduleTranslation))) + return failure(); + } + + return success(); +} + /// Converts an OpenMP 'masked' operation into LLVM IR using OpenMPIRBuilder. static LogicalResult convertOmpMasked(Operation &opInst, llvm::IRBuilderBase &builder, @@ -1262,9 +1318,6 @@ convertOmpWsloop(Operation &opInst, llvm::IRBuilderBase &builder, !wsloopOp.getPrivateVars().empty() || wsloopOp.getPrivateSyms()) return opInst.emitError("unhandled clauses for translation to LLVM IR"); - // FIXME: Here any other nested wrappers (e.g. omp.simd) are skipped, so - // codegen for composite constructs like 'DO/FOR SIMD' will be the same as for - // 'DO/FOR'. auto loopOp = cast(wsloopOp.getWrappedLoop()); llvm::ArrayRef isByRef = getIsByRef(wsloopOp.getReductionByref()); @@ -1302,6 +1355,13 @@ convertOmpWsloop(Operation &opInst, llvm::IRBuilderBase &builder, isByRef))) return failure(); + // TODO: Replace this with proper composite translation support. + // Currently, all nested wrappers are ignored, so 'do/for simd' will be + // treated the same as a standalone 'do/for'. This is allowed by the spec, + // since it's equivalent to always using a SIMD length of 1. + if (failed(convertIgnoredWrappers(loopOp, wsloopOp, moduleTranslation))) + return failure(); + // Store the mapping between reduction variables and their private copies on // ModuleTranslation stack. It can be then recovered when translating // omp.reduce operations in a separate call. diff --git a/mlir/lib/Transforms/Utils/DialectConversion.cpp b/mlir/lib/Transforms/Utils/DialectConversion.cpp index 9f8a482d6e2d22..0a62628b9ad240 100644 --- a/mlir/lib/Transforms/Utils/DialectConversion.cpp +++ b/mlir/lib/Transforms/Utils/DialectConversion.cpp @@ -1382,16 +1382,21 @@ void ConversionPatternRewriterImpl::notifyOpReplaced(Operation *op, assert(newValues.size() == op->getNumResults()); assert(!ignoredOps.contains(op) && "operation was already replaced"); + // Check if replaced op is an unresolved materialization, i.e., an + // unrealized_conversion_cast op that was created by the conversion driver. + bool isUnresolvedMaterialization = false; + if (auto castOp = dyn_cast(op)) + if (unresolvedMaterializations.contains(castOp)) + isUnresolvedMaterialization = true; + // Create mappings for each of the new result values. for (auto [newValue, result] : llvm::zip(newValues, op->getResults())) { if (!newValue) { // This result was dropped and no replacement value was provided. - if (auto castOp = dyn_cast(op)) { - if (unresolvedMaterializations.contains(castOp)) { - // Do not create another materializations if we are erasing a - // materialization. - continue; - } + if (isUnresolvedMaterialization) { + // Do not create another materializations if we are erasing a + // materialization. + continue; } // Materialize a replacement value "out of thin air". @@ -1400,10 +1405,20 @@ void ConversionPatternRewriterImpl::notifyOpReplaced(Operation *op, result.getLoc(), /*inputs=*/ValueRange(), /*outputType=*/result.getType(), /*originalType=*/Type(), currentTypeConverter); + } else { + // Make sure that the user does not mess with unresolved materializations + // that were inserted by the conversion driver. We keep track of these + // ops in internal data structures. Erasing them must be allowed because + // this can happen when the user is erasing an entire block (including + // its body). But replacing them with another value should be forbidden + // to avoid problems with the `mapping`. + assert(!isUnresolvedMaterialization && + "attempting to replace an unresolved materialization"); } - // Remap, and check for any result type changes. - mapping.map(result, newValue); + // Remap result to replacement value. + if (newValue) + mapping.map(result, newValue); } appendRewrite(op, currentTypeConverter); @@ -2442,11 +2457,11 @@ legalizeUnresolvedMaterialization(RewriterBase &rewriter, } } - InFlightDiagnostic diag = op->emitError() - << "failed to legalize unresolved materialization " - "from (" - << inputOperands.getTypes() << ") to " << outputType - << " that remained live after conversion"; + InFlightDiagnostic diag = + op->emitError() << "failed to legalize unresolved materialization " + "from (" + << inputOperands.getTypes() << ") to (" << outputType + << ") that remained live after conversion"; diag.attachNote(op->getUsers().begin()->getLoc()) << "see existing live user here: " << *op->getUsers().begin(); return failure(); diff --git a/mlir/test/Conversion/MemRefToEmitC/memref-to-emitc.mlir b/mlir/test/Conversion/MemRefToEmitC/memref-to-emitc.mlir index f4722da08cc40f..f5ef821cc9c058 100644 --- a/mlir/test/Conversion/MemRefToEmitC/memref-to-emitc.mlir +++ b/mlir/test/Conversion/MemRefToEmitC/memref-to-emitc.mlir @@ -1,28 +1,35 @@ // RUN: mlir-opt -convert-memref-to-emitc %s -split-input-file | FileCheck %s -// CHECK-LABEL: memref_store -// CHECK-SAME: %[[v:.*]]: f32, %[[i:.*]]: index, %[[j:.*]]: index -func.func @memref_store(%v : f32, %i: index, %j: index) { - // CHECK-NEXT: %[[ALLOCA:.*]] = "emitc.variable"() <{value = #emitc.opaque<"">}> : () -> !emitc.array<4x8xf32> - %0 = memref.alloca() : memref<4x8xf32> +// CHECK-LABEL: alloca() +func.func @alloca() { + // CHECK-NEXT: %[[ALLOCA:.*]] = "emitc.variable"() <{value = #emitc.opaque<"">}> : () -> !emitc.array<2xf32> + %0 = memref.alloca() : memref<2xf32> + return +} - // CHECK-NEXT: %[[SUBSCRIPT:.*]] = emitc.subscript %[[ALLOCA]][%[[i]], %[[j]]] : (!emitc.array<4x8xf32>, index, index) -> !emitc.lvalue +// ----- + +// CHECK-LABEL: memref_store +// CHECK-SAME: %[[buff:.*]]: memref<4x8xf32>, %[[v:.*]]: f32, %[[i:.*]]: index, %[[j:.*]]: index +func.func @memref_store(%buff : memref<4x8xf32>, %v : f32, %i: index, %j: index) { + // CHECK-NEXT: %[[BUFFER:.*]] = builtin.unrealized_conversion_cast %[[buff]] : memref<4x8xf32> to !emitc.array<4x8xf32> + + // CHECK-NEXT: %[[SUBSCRIPT:.*]] = emitc.subscript %[[BUFFER]][%[[i]], %[[j]]] : (!emitc.array<4x8xf32>, index, index) -> !emitc.lvalue // CHECK-NEXT: emitc.assign %[[v]] : f32 to %[[SUBSCRIPT]] : - memref.store %v, %0[%i, %j] : memref<4x8xf32> + memref.store %v, %buff[%i, %j] : memref<4x8xf32> return } // ----- // CHECK-LABEL: memref_load -// CHECK-SAME: %[[i:.*]]: index, %[[j:.*]]: index -func.func @memref_load(%i: index, %j: index) -> f32 { - // CHECK-NEXT: %[[ALLOCA:.*]] = "emitc.variable"() <{value = #emitc.opaque<"">}> : () -> !emitc.array<4x8xf32> - %0 = memref.alloca() : memref<4x8xf32> - - // CHECK-NEXT: %[[SUBSCRIPT:.*]] = emitc.subscript %[[ALLOCA]][%[[i]], %[[j]]] : (!emitc.array<4x8xf32>, index, index) -> !emitc.lvalue +// CHECK-SAME: %[[buff:.*]]: memref<4x8xf32>, %[[i:.*]]: index, %[[j:.*]]: index +func.func @memref_load(%buff : memref<4x8xf32>, %i: index, %j: index) -> f32 { + // CHECK-NEXT: %[[BUFFER:.*]] = builtin.unrealized_conversion_cast %[[buff]] : memref<4x8xf32> to !emitc.array<4x8xf32> + + // CHECK-NEXT: %[[SUBSCRIPT:.*]] = emitc.subscript %[[BUFFER]][%[[i]], %[[j]]] : (!emitc.array<4x8xf32>, index, index) -> !emitc.lvalue // CHECK-NEXT: %[[LOAD:.*]] = emitc.load %[[SUBSCRIPT]] : - %1 = memref.load %0[%i, %j] : memref<4x8xf32> + %1 = memref.load %buff[%i, %j] : memref<4x8xf32> // CHECK-NEXT: return %[[LOAD]] : f32 return %1 : f32 } diff --git a/mlir/test/Dialect/Arith/int-range-interface.mlir b/mlir/test/Dialect/Arith/int-range-interface.mlir index 4b04229e5db52f..6d66da2fc1eb35 100644 --- a/mlir/test/Dialect/Arith/int-range-interface.mlir +++ b/mlir/test/Dialect/Arith/int-range-interface.mlir @@ -178,8 +178,8 @@ func.func @div_bounds_negative(%arg0 : index) -> i1 { } // CHECK-LABEL: func @div_zero_undefined -// CHECK: %[[ret:.*]] = arith.cmpi ule -// CHECK: return %[[ret]] +// CHECK: %[[true:.*]] = arith.constant true +// CHECK: return %[[true]] func.func @div_zero_undefined(%arg0 : index) -> i1 { %c0 = arith.constant 0 : index %c1 = arith.constant 1 : index @@ -190,6 +190,19 @@ func.func @div_zero_undefined(%arg0 : index) -> i1 { func.return %2 : i1 } +// CHECK-LABEL: func @div_refine_min +// CHECK: %[[true:.*]] = arith.constant true +// CHECK: return %[[true]] +func.func @div_refine_min(%arg0 : index) -> i1 { + %c0 = arith.constant 1 : index + %c1 = arith.constant 2 : index + %c4 = arith.constant 4 : index + %0 = arith.andi %arg0, %c1 : index + %1 = arith.divui %c4, %0 : index + %2 = arith.cmpi uge, %1, %c0 : index + func.return %2 : i1 +} + // CHECK-LABEL: func @ceil_divui // CHECK: %[[ret:.*]] = arith.cmpi eq // CHECK: return %[[ret]] @@ -271,13 +284,13 @@ func.func @remui_base(%arg0 : index, %arg1 : index ) -> i1 { // CHECK: return %[[true]] func.func @remui_base_maybe_zero(%arg0 : index, %arg1 : index ) -> i1 { %c4 = arith.constant 4 : index - %c5 = arith.constant 5 : index + %c5 = arith.constant 5 : index %0 = arith.minui %arg1, %c4 : index %1 = arith.remui %arg0, %0 : index %2 = arith.cmpi ult, %1, %c5 : index func.return %2 : i1 -} +} // CHECK-LABEL: func @remsi_base // CHECK: %[[ret:.*]] = arith.cmpi sge diff --git a/mlir/test/Dialect/Bufferization/Transforms/finalizing-bufferize.mlir b/mlir/test/Dialect/Bufferization/Transforms/finalizing-bufferize.mlir index ab18ce05e355d3..bae94c1be4da90 100644 --- a/mlir/test/Dialect/Bufferization/Transforms/finalizing-bufferize.mlir +++ b/mlir/test/Dialect/Bufferization/Transforms/finalizing-bufferize.mlir @@ -78,7 +78,7 @@ func.func @static_layout_to_no_layout_cast(%m: memref) -> memref> { %0 = bufferization.to_tensor %m : memref - // expected-error @+1 {{failed to legalize unresolved materialization from ('memref') to 'memref>' that remained live after conversion}} + // expected-error @+1 {{failed to legalize unresolved materialization from ('memref') to ('memref>') that remained live after conversion}} %1 = bufferization.to_memref %0 : memref> // expected-note @below{{see existing live user here}} return %1 : memref> diff --git a/mlir/test/Dialect/Bufferization/Transforms/one-shot-module-bufferize-invalid.mlir b/mlir/test/Dialect/Bufferization/Transforms/one-shot-module-bufferize-invalid.mlir index ee0f71f668dc74..2829eafb7c1c59 100644 --- a/mlir/test/Dialect/Bufferization/Transforms/one-shot-module-bufferize-invalid.mlir +++ b/mlir/test/Dialect/Bufferization/Transforms/one-shot-module-bufferize-invalid.mlir @@ -1,11 +1,5 @@ // RUN: mlir-opt %s -allow-unregistered-dialect -one-shot-bufferize="bufferize-function-boundaries=1" -split-input-file -verify-diagnostics -// expected-error @+2 {{cannot bufferize bodiless function that returns a tensor}} -// expected-error @+1 {{failed to bufferize op}} -func.func private @foo() -> tensor - -// ----- - // expected-error @+1 {{cannot bufferize a FuncOp with tensors and without a unique ReturnOp}} func.func @swappy(%cond1 : i1, %cond2 : i1, %t1 : tensor, %t2 : tensor) -> (tensor, tensor) @@ -123,17 +117,6 @@ func.func @to_tensor_op_unsupported(%m: memref, %idx: index) -> (f32) { // ----- -// expected-error @+2 {{failed to bufferize op}} -// expected-error @+1 {{cannot bufferize bodiless function that returns a tensor}} -func.func private @foo(%t : tensor) -> (f32, tensor, f32) - -func.func @call_to_unknown_tensor_returning_func(%t : tensor) { - call @foo(%t) : (tensor) -> (f32, tensor, f32) - return -} - -// ----- - func.func @yield_alloc_dominance_test_2(%cst : f32, %idx : index, %idx2 : index) -> f32 { %1 = bufferization.alloc_tensor(%idx) : tensor diff --git a/mlir/test/Dialect/Bufferization/Transforms/one-shot-module-bufferize.mlir b/mlir/test/Dialect/Bufferization/Transforms/one-shot-module-bufferize.mlir index 0d5224514e3a02..d31b43477beb9f 100644 --- a/mlir/test/Dialect/Bufferization/Transforms/one-shot-module-bufferize.mlir +++ b/mlir/test/Dialect/Bufferization/Transforms/one-shot-module-bufferize.mlir @@ -42,6 +42,21 @@ func.func private @external_func_with_return_val(tensor<4xi32>) -> f32 // ----- +// Bufferization of bodiless function that returns a tensor. + +// CHECK: func.func private @foo(memref>) -> (f32, memref>, f32) +func.func private @foo(%t : tensor) -> (f32, tensor, f32) + +// CHECK: func.func @call_to_unknown_tensor_returning_func( +// CHECK-SAME: %[[arg0:.*]]: memref>) { +func.func @call_to_unknown_tensor_returning_func(%t : tensor) { + // CHECK: call @foo(%[[arg0]]) : (memref>) -> (f32, memref>, f32) + call @foo(%t) : (tensor) -> (f32, tensor, f32) + return +} + +// ----- + // A function that returns a non-equivalent tensor with layout map. // CHECK-LABEL: func @return_extract_slice(%{{.*}}) -> memref<2x?xf32, strided<[10, 1], offset: ?>> diff --git a/mlir/test/Dialect/Linalg/canonicalize.mlir b/mlir/test/Dialect/Linalg/canonicalize.mlir index 4bc2ed140da91a..5de007b390c51d 100644 --- a/mlir/test/Dialect/Linalg/canonicalize.mlir +++ b/mlir/test/Dialect/Linalg/canonicalize.mlir @@ -1232,3 +1232,20 @@ func.func @transpose_buffer(%input: memref, // CHECK-SAME: %[[VAL_1:.*]]: memref) { // CHECK: linalg.transpose ins(%[[VAL_0]] : memref) // CHECK-SAME: outs(%[[VAL_1]] : memref) permutation = [0] + +// ----- + +// This test checks linalg op has a recursive memory effect. Otherwise +// linalg.map without a user would be DCEd. +func.func @recursive_effect(%arg : tensor<1xf32>) { + %init = arith.constant dense<0.0> : tensor<1xf32> + %mapped = linalg.map ins(%arg:tensor<1xf32>) outs(%init :tensor<1xf32>) + (%in : f32) { + vector.print %in : f32 + linalg.yield %in : f32 + } + func.return +} + +// CHECK-LABEL: @recursive_effect +// CHECK: linalg.map diff --git a/mlir/test/Dialect/Linalg/invalid.mlir b/mlir/test/Dialect/Linalg/invalid.mlir index c481a723c5623c..4b5a66f8fb5b92 100644 --- a/mlir/test/Dialect/Linalg/invalid.mlir +++ b/mlir/test/Dialect/Linalg/invalid.mlir @@ -352,6 +352,15 @@ func.func @illegal_fill_tensor_with_memref_return // ----- +func.func @illegal_fill_value_type(%arg0 : tensor<2x2xf32>, %arg1 : tensor<2xf32>) -> tensor<2x2xf32> +{ + // expected-error @+1 {{expected op with scalar input}} + %0 = linalg.fill ins(%arg1 : tensor<2xf32>) outs(%arg0 : tensor<2x2xf32>) -> tensor<2x2xf32> + return %0 : tensor<2x2xf32> +} + +// ----- + func.func @invalid_static_matmul(%arg0: memref<2x4xf32>, %arg1: memref<3x4xf32>, %arg2: memref<2x4xf32>) { // expected-error @+1 {{inferred input/output operand #1 has shape's dimension #0 to be 4, but found 3}} linalg.matmul ins(%arg0, %arg1 : memref<2x4xf32>, memref<3x4xf32>) diff --git a/mlir/test/Dialect/Linalg/vectorization-pad-patterns.mlir b/mlir/test/Dialect/Linalg/vectorization-pad-patterns.mlir index 2aa4638af3f0f3..640de85cc5f12e 100644 --- a/mlir/test/Dialect/Linalg/vectorization-pad-patterns.mlir +++ b/mlir/test/Dialect/Linalg/vectorization-pad-patterns.mlir @@ -161,7 +161,8 @@ module attributes {transform.with_named_sequence} { ///---------------------------------------------------------------------------------------- /// tensor::PadOp -> tensor::EmptyOp + linalg::FillOp/tensor::GenerateOp + tensor::InsertSliceOp -/// [Pattern: GenericPadOpVectorizationPattern] +/// [Pattern: GenericPadOpVectorizationPattern + InsertSliceVectorizePattern] +/// TODO: Split the test into two, one for each pattern. ///---------------------------------------------------------------------------------------- func.func private @make_vector() -> tensor<12x13xf32> @@ -174,12 +175,14 @@ func.func private @make_vector() -> tensor<12x13xf32> // CHECK-NOT: tensor.pad // CHECK-DAG: %[[C0:.*]] = arith.constant 0 : index // CHECK-DAG: %[[PAD:.*]] = arith.constant 5.000000e+00 : f32 +// CHECK-DAG: %[[PAD_READ:.*]] = arith.constant 0.000000e+00 : f32 // CHECK: %[[EMPTY:.*]] = tensor.empty() : tensor<1x12x13xf32> // CHECK: %[[FILL:.*]] = linalg.fill ins(%[[PAD]] : f32) outs(%[[EMPTY]] : tensor<1x12x13xf32>) -> tensor<1x12x13xf32> -// CHECK: %[[READ:.*]] = vector.transfer_read %[[ARG_0]]{{\[}}%[[C0]], %[[C0]], %[[C0]]], %[[PAD]] {in_bounds = [true, true, true]} : tensor<1x5x6xf32>, vector<1x5x6xf32> -// CHECK: %[[WRITE:.*]] = vector.transfer_write %[[READ]], %[[FILL]]{{\[}}%[[C0]], %[[C0]], %[[C0]]] {in_bounds = [true, true, true]} : vector<1x5x6xf32>, tensor<1x12x13xf32> +// CHECK: %[[READ_1:.*]] = vector.transfer_read %[[ARG_0]]{{\[}}%[[C0]], %[[C0]], %[[C0]]], %[[PAD]] {in_bounds = [true, true, true]} : tensor<1x5x6xf32>, vector<1x5x6xf32> +// CHECK: %[[WRITE_1:.*]] = vector.transfer_write %[[READ_1]], %[[FILL]]{{\[}}%[[C0]], %[[C0]], %[[C0]]] {in_bounds = [true, true, true]} : vector<1x5x6xf32>, tensor<1x12x13xf32> // CHECK: %[[VEC:.*]] = call @make_vector() : () -> tensor<12x13xf32> -// CHECK: %[[RES:.*]] = tensor.insert_slice %[[VEC]] into %[[WRITE]][0, 0, 0] [1, 12, 13] [1, 1, 1] : tensor<12x13xf32> into tensor<1x12x13xf32> +// CHECK: %[[READ_2:.*]] = vector.transfer_read %[[VEC]]{{\[}}%[[C0]], %[[C0]]], %[[PAD_READ]] {in_bounds = [true, true]} : tensor<12x13xf32>, vector<12x13xf32> +// CHECK: %[[RES:.*]] = vector.transfer_write %[[READ_2]], %[[WRITE_1]]{{\[}}%[[C0]], %[[C0]], %[[C0]]] {in_bounds = [true, true]} : vector<12x13xf32>, tensor<1x12x13xf32> // CHECK: return %[[RES]] : tensor<1x12x13xf32> func.func @pad_and_insert_slice_dest( diff --git a/mlir/test/Dialect/Linalg/vectorization-unsupported.mlir b/mlir/test/Dialect/Linalg/vectorization-unsupported.mlir index e9f8e08ca0c6b4..8fbc74ec345c6b 100644 --- a/mlir/test/Dialect/Linalg/vectorization-unsupported.mlir +++ b/mlir/test/Dialect/Linalg/vectorization-unsupported.mlir @@ -1,4 +1,4 @@ -// RUN: mlir-opt %s -transform-interpreter -split-input-file -verify-diagnostics +// RUN: mlir-opt %s -transform-interpreter -split-input-file -verify-diagnostics | FileCheck %s func.func @conv1d_nwc_wcf_dyn_ch_dim(%input: memref<4x6x?xf32>, %filter: memref<1x?x8xf32>, %output: memref<4x2x8xf32>) { // expected-error @+1 {{Attempted to vectorize, but failed}} @@ -253,3 +253,30 @@ module attributes {transform.with_named_sequence} { transform.yield } } + +// ----- + +// With dynamically shaped source, the vectorizer infers the vector size for +// xfer Ops from the destination tensor and, conservatively, assumes +// out-of-bounds accesses. Out-of-bounds accesses require a pad value, but +// that's impossible to recover in this example. Hence no vectorization. + +// TODO: Use diagnostics once we can vectorize tensor.insert_slice with +// transform.structured.vectorize + +// CHECK-LABEL: @insert_dynamic_slice_unknown_pad +// CHECK-NOT: vector +// CHECK: tensor.insert_slice +func.func @insert_dynamic_slice_unknown_pad(%arg0: tensor<1x?x3xf32>, %arg1: tensor<9x8x7x1x2x3xf32>, %size: index) -> tensor<9x8x7x1x2x3xf32> { + %res = tensor.insert_slice %arg0 into %arg1[0, 0, 0, 0, 0, 0] [1, 1, 1, 1, %size, 3][1, 1, 1, 1, 1, 1] : tensor<1x?x3xf32> into tensor<9x8x7x1x2x3xf32> + return %res : tensor<9x8x7x1x2x3xf32> +} + +module attributes {transform.with_named_sequence} { + transform.named_sequence @__transform_main(%arg1: !transform.any_op {transform.readonly}) { + %0 = transform.structured.match ops{["tensor.insert_slice"]} in %arg1 : (!transform.any_op) -> !transform.any_op + %1 = transform.get_parent_op %0 {isolated_from_above} : (!transform.any_op) -> !transform.any_op + %2 = transform.structured.vectorize_children_and_apply_patterns %1 : (!transform.any_op) -> !transform.any_op + transform.yield + } +} diff --git a/mlir/test/Dialect/Linalg/vectorization-with-patterns.mlir b/mlir/test/Dialect/Linalg/vectorization-with-patterns.mlir index 189507d97d6dc2..d2fb3730a2d2b0 100644 --- a/mlir/test/Dialect/Linalg/vectorization-with-patterns.mlir +++ b/mlir/test/Dialect/Linalg/vectorization-with-patterns.mlir @@ -939,16 +939,20 @@ module attributes {transform.with_named_sequence} { func.func private @make_vector() -> tensor<12x13xf32> -// CHECK-LABEL: func @pad_and_insert_slice_dest -// CHECK-SAME: %[[ARG0:.*]]: tensor<1x5x6xf32> -// Check the insert slice is not rewritten if the padded result is used by the destination operand. -// CHECK-NOT: tensor.pad -// CHECK: %[[EMPTY:.*]] = tensor.empty() : tensor<1x12x13xf32> -// CHECK: %[[WRITE_1:.*]] = vector.transfer_write %{{.*}}, %[[EMPTY]]{{.*}} : vector<1x12x13xf32>, tensor<1x12x13xf32> -// CHECK: %[[READ:.*]] = vector.transfer_read %[[ARG0:.*]]{{.*}} : tensor<1x5x6xf32>, vector<1x5x6xf32> -// CHECK: %[[WRITE_2:.*]] = vector.transfer_write %[[READ]], %[[WRITE_1]]{{.*}} : vector<1x5x6xf32>, tensor<1x12x13xf32> -// CHECK: %[[T1:.*]] = call @make_vector() : () -> tensor<12x13xf32> -// CHECK: tensor.insert_slice %[[T1]] into %[[WRITE_2]] +// CHECK-LABEL: func.func @pad_and_insert_slice_dest( +// CHECK-SAME: %[[ARG_0:.*]]: tensor<1x5x6xf32>) -> tensor<1x12x13xf32> { +// CHECK: %[[C0:.*]] = arith.constant 0.000000e+00 : f32 +// CHECK: %[[CST:.*]] = arith.constant dense<5.000000e+00> : vector<1x12x13xf32> +// CHECK: %[[C0_IDX:.*]] = arith.constant 0 : index +// CHECK: %[[PAD_VAL:.*]] = arith.constant 5.000000e+00 : f32 +// CHECK: %[[EMPTY:.*]] = tensor.empty() : tensor<1x12x13xf32> +// CHECK: %[[WRITE_1:.*]] = vector.transfer_write %[[CST]], %[[EMPTY]]{{\[}}%[[C0_IDX]], %[[C0_IDX]], %[[C0_IDX]]] {in_bounds = [true, true, true]} : vector<1x12x13xf32>, tensor<1x12x13xf32> +// CHECK: %[[READ_1:.*]] = vector.transfer_read %[[ARG_0]]{{\[}}%[[C0_IDX]], %[[C0_IDX]], %[[C0_IDX]]], %[[PAD_VAL]] {in_bounds = [true, true, true]} : tensor<1x5x6xf32>, vector<1x5x6xf32> +// CHECK: %[[WRITE_2:.*]] = vector.transfer_write %[[READ_1]], %[[WRITE_1]]{{\[}}%[[C0_IDX]], %[[C0_IDX]], %[[C0_IDX]]] {in_bounds = [true, true, true]} : vector<1x5x6xf32>, tensor<1x12x13xf32> +// CHECK: %[[MAKE_VEC:.*]] = call @make_vector() : () -> tensor<12x13xf32> +// CHECK: %[[READ_2:.*]] = vector.transfer_read %[[MAKE_VEC]]{{\[}}%[[C0_IDX]], %[[C0_IDX]]], %[[C0]] {in_bounds = [true, true]} : tensor<12x13xf32>, vector<12x13xf32> +// CHECK: %[[RES:.*]] = vector.transfer_write %[[READ_2]], %[[WRITE_2]]{{\[}}%[[C0_IDX]], %[[C0_IDX]], %[[C0_IDX]]] {in_bounds = [true, true]} : vector<12x13xf32>, tensor<1x12x13xf32> +// CHECK: return %[[RES]] : tensor<1x12x13xf32> func.func @pad_and_insert_slice_dest( %arg0: tensor<1x5x6xf32>) -> tensor<1x12x13xf32> { %c5 = arith.constant 5.0 : f32 @@ -1924,3 +1928,94 @@ module attributes {transform.with_named_sequence} { transform.yield } } + +// ----- + +///---------------------------------------------------------------------------------------- +/// tensor.insert_slice +///---------------------------------------------------------------------------------------- + +// The pad value for xfer-read is neither needed nor available - use the default (0.0). + +// CHECK-LABEL: func @insert_static_slice_default_pad +// CHECK-SAME: %[[ARG_0:.*]]: tensor<1x2x3xf32>, +// CHECK-SAME: %[[ARG_1:.*]]: tensor<9x8x7x1x2x3xf32>) -> tensor<9x8x7x1x2x3xf32> { +// CHECK: %[[PAD:.*]] = arith.constant 0.000000e+00 : f32 +// CHECK: %[[C0:.*]] = arith.constant 0 : index +// CHECK: %[[READ:.*]] = vector.transfer_read %[[ARG_0]]{{\[}}%[[C0]], %[[C0]], %[[C0]]], %[[PAD]] {in_bounds = [true, true, true]} : tensor<1x2x3xf32>, vector<1x2x3xf32> +// CHECK: %[[WRITE:.*]] = vector.transfer_write %[[READ]], %[[ARG_1]]{{\[}}%[[C0]], %[[C0]], %[[C0]], %[[C0]], %[[C0]], %[[C0]]] {in_bounds = [true, true, true]} : vector<1x2x3xf32>, tensor<9x8x7x1x2x3xf32> +// CHECK: return %[[WRITE]] : tensor<9x8x7x1x2x3xf32> +func.func @insert_static_slice_default_pad(%arg0: tensor<1x2x3xf32>, %arg1: tensor<9x8x7x1x2x3xf32>) -> tensor<9x8x7x1x2x3xf32> { + %res = tensor.insert_slice %arg0 into %arg1[0, 0, 0, 0, 0, 0] [1, 1, 1, 1, 2, 3][1, 1, 1, 1, 1, 1] : tensor<1x2x3xf32> into tensor<9x8x7x1x2x3xf32> + return %res : tensor<9x8x7x1x2x3xf32> +} + +module attributes {transform.with_named_sequence} { + transform.named_sequence @__transform_main(%arg1: !transform.any_op {transform.readonly}) { + %0 = transform.structured.match ops{["tensor.insert_slice"]} in %arg1 : (!transform.any_op) -> !transform.any_op + %1 = transform.get_parent_op %0 {isolated_from_above} : (!transform.any_op) -> !transform.any_op + %2 = transform.structured.vectorize_children_and_apply_patterns %1 { vectorize_padding } : (!transform.any_op) -> !transform.any_op + transform.yield + } +} + +// ----- + +// Same as above, but there's a pad value available that should be used instead of the default value. + +// CHECK-LABEL: func.func @insert_static_slice_non_zero_pad +// CHECK-SAME: %[[ARG_0:.*]]: tensor<1x2x3xf32>, +// CHECK-SAME: %[[PAD:.*]]: f32) -> tensor<9x8x7x1x2x3xf32> { +// CHECK: %[[EMPTY:.*]] = tensor.empty() : tensor<9x8x7x1x2x3xf32> +// CHECK: %[[BC:.*]] = vector.broadcast %[[PAD]] : f32 to vector<9x8x7x1x2x3xf32> +// CHECK: %[[WRITE:.*]] = vector.transfer_write %[[BC]], %[[EMPTY]]{{.*}} {in_bounds = [true, true, true, true, true, true]} : vector<9x8x7x1x2x3xf32>, tensor<9x8x7x1x2x3xf32> +// CHECK: %[[READ:.*]] = vector.transfer_read %[[ARG_0]]{{.*}}, %[[PAD]] {in_bounds = [true, true, true]} : tensor<1x2x3xf32>, vector<1x2x3xf32> +// CHECK: %[[RES:.*]] = vector.transfer_write %[[READ]], %[[WRITE]]{{.*}} {in_bounds = [true, true, true]} : vector<1x2x3xf32>, tensor<9x8x7x1x2x3xf32> +// CHECK: return %[[RES]] : tensor<9x8x7x1x2x3xf32> +func.func @insert_static_slice_non_zero_pad(%arg0: tensor<1x2x3xf32>, %pad : f32) -> tensor<9x8x7x1x2x3xf32> { + %init = tensor.empty() : tensor<9x8x7x1x2x3xf32> + %fill = linalg.fill ins(%pad : f32) outs(%init : tensor<9x8x7x1x2x3xf32>) -> tensor<9x8x7x1x2x3xf32> + %res = tensor.insert_slice %arg0 into %fill[0, 0, 0, 0, 0, 0] [1, 1, 1, 1, 2, 3][1, 1, 1, 1, 1, 1] : tensor<1x2x3xf32> into tensor<9x8x7x1x2x3xf32> + return %res : tensor<9x8x7x1x2x3xf32> +} + +module attributes {transform.with_named_sequence} { + transform.named_sequence @__transform_main(%arg1: !transform.any_op {transform.readonly}) { + %0 = transform.structured.match ops{["tensor.insert_slice"]} in %arg1 : (!transform.any_op) -> !transform.any_op + %1 = transform.get_parent_op %0 {isolated_from_above} : (!transform.any_op) -> !transform.any_op + %2 = transform.structured.vectorize_children_and_apply_patterns %1 : (!transform.any_op) -> !transform.any_op + transform.yield + } +} + +// ----- + +// Same as above, but the source type has is dynamically shaped. This means +// that the pad value is now required and the vector dim corresponding to the +// dynamic shape has to be inferred from the shape of the destination tensor. + +// CHECK-LABEL: func.func @insert_dynamic_slice_non_zero_pad( +// CHECK-SAME: %[[ARG_0:.*]]: tensor<1x?x3xf32>, +// CHECK-SAME: %[[PAD:.*]]: f32, +// CHECK-SAME: %[[SIZE:.*]]: index) -> tensor<9x8x7x1x2x3xf32> { +// CHECK: %[[EMPTY:.*]] = tensor.empty() : tensor<9x8x7x1x2x3xf32> +// CHECK: %[[BC:.*]] = vector.broadcast %[[PAD]] : f32 to vector<9x8x7x1x2x3xf32> +// CHECK: %[[WRITE:.*]] = vector.transfer_write %[[BC]], %[[EMPTY]]{{.*}} {in_bounds = [true, true, true, true, true, true]} : vector<9x8x7x1x2x3xf32>, tensor<9x8x7x1x2x3xf32> +// CHECK: %[[READ:.*]] = vector.transfer_read %[[ARG_0]]{{.*}}, %[[PAD]] {in_bounds = [true, false, true]} : tensor<1x?x3xf32>, vector<1x2x3xf32> +// CHECK: %[[RES:.*]] = vector.transfer_write %[[READ]], %[[WRITE]]{{.*}} {in_bounds = [true, true, true]} : vector<1x2x3xf32>, tensor<9x8x7x1x2x3xf32> +// CHECK: return %[[RES]] : tensor<9x8x7x1x2x3xf32> +func.func @insert_dynamic_slice_non_zero_pad(%arg0: tensor<1x?x3xf32>, %pad : f32, %size: index) -> tensor<9x8x7x1x2x3xf32> { + %init = tensor.empty() : tensor<9x8x7x1x2x3xf32> + %fill = linalg.fill ins(%pad : f32) outs(%init : tensor<9x8x7x1x2x3xf32>) -> tensor<9x8x7x1x2x3xf32> + %res = tensor.insert_slice %arg0 into %fill[0, 0, 0, 0, 0, 0] [1, 1, 1, 1, %size, 3][1, 1, 1, 1, 1, 1] : tensor<1x?x3xf32> into tensor<9x8x7x1x2x3xf32> + return %res : tensor<9x8x7x1x2x3xf32> +} + +module attributes {transform.with_named_sequence} { + transform.named_sequence @__transform_main(%arg1: !transform.any_op {transform.readonly}) { + %0 = transform.structured.match ops{["tensor.insert_slice"]} in %arg1 : (!transform.any_op) -> !transform.any_op + %1 = transform.get_parent_op %0 {isolated_from_above} : (!transform.any_op) -> !transform.any_op + %2 = transform.structured.vectorize_children_and_apply_patterns %1 : (!transform.any_op) -> !transform.any_op + transform.yield + } +} diff --git a/mlir/test/Dialect/Vector/canonicalize.mlir b/mlir/test/Dialect/Vector/canonicalize.mlir index 6d6bc199e601c0..c963460e7259fb 100644 --- a/mlir/test/Dialect/Vector/canonicalize.mlir +++ b/mlir/test/Dialect/Vector/canonicalize.mlir @@ -800,6 +800,43 @@ func.func @fold_extract_shapecast_to_shapecast(%arg0 : vector<3x4xf32>) -> vecto // ----- +// CHECK-LABEL: func @extract_no_fold_scalar_to_0d( +// CHECK-SAME: %[[v:.*]]: vector) +// CHECK: %[[extract:.*]] = vector.extract %[[v]][] : f32 from vector +// CHECK: return %[[extract]] +func.func @extract_no_fold_scalar_to_0d(%v: vector) -> f32 { + %0 = vector.extract %v[] : f32 from vector + return %0 : f32 +} + +// ----- + +// CHECK-LABEL: func @insert_fold_same_rank( +// CHECK-SAME: %[[v:.*]]: vector<2x2xf32>) +// CHECK: %[[CST:.+]] = arith.constant +// CHECK-SAME: : vector<2x2xf32> +// CHECK-NOT: vector.insert +// CHECK: return %[[CST]] +func.func @insert_fold_same_rank(%v: vector<2x2xf32>) -> vector<2x2xf32> { + %cst = arith.constant dense<0.000000e+00> : vector<2x2xf32> + %0 = vector.insert %cst, %v [] : vector<2x2xf32> into vector<2x2xf32> + return %0 : vector<2x2xf32> +} + +// ----- + +// CHECK-LABEL: func @insert_no_fold_scalar_to_0d( +// CHECK-SAME: %[[v:.*]]: vector) +// CHECK: %[[extract:.*]] = vector.insert %{{.*}}, %[[v]] [] : f32 into vector +// CHECK: return %[[extract]] +func.func @insert_no_fold_scalar_to_0d(%v: vector) -> vector { + %cst = arith.constant 0.000000e+00 : f32 + %0 = vector.insert %cst, %v [] : f32 into vector + return %0 : vector +} + +// ----- + // CHECK-LABEL: dont_fold_expand_collapse // CHECK: %[[A:.*]] = vector.shape_cast %{{.*}} : vector<1x1x64xf32> to vector<1x1x8x8xf32> // CHECK: %[[B:.*]] = vector.shape_cast %{{.*}} : vector<1x1x8x8xf32> to vector<8x8xf32> @@ -2606,17 +2643,6 @@ func.func @rank_1_shuffle_to_interleave(%arg0: vector<6xi32>, %arg1: vector<6xi3 // ----- -// CHECK-LABEL: func @extract_from_0d_regression( -// CHECK-SAME: %[[v:.*]]: vector) -// CHECK: %[[extract:.*]] = vector.extract %[[v]][] : f32 from vector -// CHECK: return %[[extract]] -func.func @extract_from_0d_regression(%v: vector) -> f32 { - %0 = vector.extract %v[] : f32 from vector - return %0 : f32 -} - -// ----- - // CHECK-LABEL: func @extract_from_0d_splat_broadcast_regression( // CHECK-SAME: %[[a:.*]]: f32, %[[b:.*]]: vector, %[[c:.*]]: vector<2xf32>) func.func @extract_from_0d_splat_broadcast_regression(%a: f32, %b: vector, %c: vector<2xf32>) -> (f32, f32, f32, f32, f32, vector<6x7xf32>, vector<3xf32>) { diff --git a/mlir/test/Dialect/Vector/vector-emulate-narrow-type-unaligned.mlir b/mlir/test/Dialect/Vector/vector-emulate-narrow-type-unaligned.mlir new file mode 100644 index 00000000000000..7ecbad7968225d --- /dev/null +++ b/mlir/test/Dialect/Vector/vector-emulate-narrow-type-unaligned.mlir @@ -0,0 +1,67 @@ +// RUN: mlir-opt --test-emulate-narrow-int="arith-compute-bitwidth=1 memref-load-bitwidth=8" --cse --split-input-file %s | FileCheck %s + +func.func @vector_load_i2(%arg1: index, %arg2: index) -> vector<3x3xi2> { + %0 = memref.alloc() : memref<3x3xi2> + %c0 = arith.constant 0 : index + %c2 = arith.constant 2 : index + %cst = arith.constant dense<0> : vector<3x3xi2> + %1 = vector.load %0[%c2, %c0] : memref<3x3xi2>, vector<3xi2> + %2 = vector.insert %1, %cst [0] : vector<3xi2> into vector<3x3xi2> + return %2 : vector<3x3xi2> +} + +// CHECK: func @vector_load_i2 +// CHECK: %[[ALLOC:.+]] = memref.alloc() : memref<3xi8> +// CHECK: %[[INDEX:.+]] = arith.constant 1 : index +// CHECK: %[[VEC:.+]] = vector.load %[[ALLOC]][%[[INDEX]]] : memref<3xi8>, vector<2xi8> +// CHECK: %[[VEC_I2:.+]] = vector.bitcast %[[VEC]] : vector<2xi8> to vector<8xi2> +// CHECK: %[[EXCTRACT:.+]] = vector.extract_strided_slice %[[VEC_I2]] {offsets = [2], sizes = [3], strides = [1]} : vector<8xi2> to vector<3xi2> + +//----- + +func.func @vector_transfer_read_i2() -> vector<3xi2> { + %0 = memref.alloc() : memref<3x3xi2> + %c0i2 = arith.constant 0 : i2 + %c0 = arith.constant 0 : index + %c2 = arith.constant 2 : index + %1 = vector.transfer_read %0[%c2, %c0], %c0i2 {in_bounds = [true]} : memref<3x3xi2>, vector<3xi2> + return %1 : vector<3xi2> +} + +// CHECK: func @vector_transfer_read_i2 +// CHECK: %[[ALLOC:.+]] = memref.alloc() : memref<3xi8> +// CHECK: %[[INDEX:.+]] = arith.constant 1 : index +// CHECK: %[[READ:.+]] = vector.transfer_read %[[ALLOC]][%[[INDEX]]], %0 : memref<3xi8>, vector<2xi8> +// CHECK: %[[BITCAST:.+]] = vector.bitcast %[[READ]] : vector<2xi8> to vector<8xi2> +// CHECK: vector.extract_strided_slice %[[BITCAST]] {offsets = [2], sizes = [3], strides = [1]} : vector<8xi2> to vector<3xi2> + +//----- + +func.func @vector_cst_maskedload_i2(%passthru: vector<5xi2>) -> vector<3x5xi2> { + %0 = memref.alloc() : memref<3x5xi2> + %cst = arith.constant dense<0> : vector<3x5xi2> + %mask = vector.constant_mask [3] : vector<5xi1> + %c0 = arith.constant 0 : index + %c2 = arith.constant 2 : index + %1 = vector.maskedload %0[%c2, %c0], %mask, %passthru : + memref<3x5xi2>, vector<5xi1>, vector<5xi2> into vector<5xi2> + %2 = vector.insert %1, %cst [0] : vector<5xi2> into vector<3x5xi2> + return %2 : vector<3x5xi2> +} + +// CHECK: func @vector_cst_maskedload_i2 +// CHECK: %[[ORIGINMASK:.+]] = vector.constant_mask [3] : vector<5xi1> +// CHECK: %[[NEWMASK:.+]] = arith.constant dense : vector<2xi1> +// CHECK: %[[VESSEL:.+]] = arith.constant dense<0> : vector<8xi2> +// CHECK: %[[INSERT1:.+]] = vector.insert_strided_slice %arg0, %[[VESSEL]] +// CHECK-SAME: {offsets = [2], strides = [1]} : vector<5xi2> into vector<8xi2> +// CHECK: %[[BITCAST1:.+]] = vector.bitcast %[[INSERT1]] : vector<8xi2> to vector<2xi8> +// CHECK: %[[C2:.+]] = arith.constant 2 : index +// CHECK: %[[MASKEDLOAD:.+]] = vector.maskedload %alloc[%[[C2]]], %[[NEWMASK:.+]], %[[BITCAST1]] +// CHECK-SAME: : memref<4xi8>, vector<2xi1>, vector<2xi8> into vector<2xi8> +// CHECK: %[[BITCAST2:.+]] = vector.bitcast %[[MASKEDLOAD]] : vector<2xi8> to vector<8xi2> +// CHECK: %[[CST2:.+]] = arith.constant dense : vector<8xi1> +// CHECK: %[[INSERT2:.+]] = vector.insert_strided_slice %[[ORIGINMASK]], %[[CST2]] +// CHECK-SAME: {offsets = [2], strides = [1]} : vector<5xi1> into vector<8xi1> +// CHECK: %[[SELECT:.+]] = arith.select %[[INSERT2]], %[[BITCAST2]], %[[INSERT1]] : vector<8xi1>, vector<8xi2> +// CHECK: vector.extract_strided_slice %[[SELECT]] {offsets = [2], sizes = [5], strides = [1]} : vector<8xi2> to vector<5xi2> diff --git a/mlir/test/Target/LLVMIR/openmp-reduction.mlir b/mlir/test/Target/LLVMIR/openmp-reduction.mlir index 6d74a925b87b5c..11c8559044be02 100644 --- a/mlir/test/Target/LLVMIR/openmp-reduction.mlir +++ b/mlir/test/Target/LLVMIR/openmp-reduction.mlir @@ -586,3 +586,83 @@ llvm.func @parallel_nested_workshare_reduction(%ub : i64) { // Reduction function. // CHECK: define internal void @[[REDFUNC]] // CHECK: add i32 + +// ----- + +omp.declare_reduction @add_f32 : f32 +init { +^bb0(%arg: f32): + %0 = llvm.mlir.constant(0.0 : f32) : f32 + omp.yield (%0 : f32) +} +combiner { +^bb1(%arg0: f32, %arg1: f32): + %1 = llvm.fadd %arg0, %arg1 : f32 + omp.yield (%1 : f32) +} +atomic { +^bb2(%arg2: !llvm.ptr, %arg3: !llvm.ptr): + %2 = llvm.load %arg3 : !llvm.ptr -> f32 + llvm.atomicrmw fadd %arg2, %2 monotonic : !llvm.ptr, f32 + omp.yield +} + +// CHECK-LABEL: @wsloop_simd_reduction +llvm.func @wsloop_simd_reduction(%lb : i64, %ub : i64, %step : i64) { + %c1 = llvm.mlir.constant(1 : i32) : i32 + %0 = llvm.alloca %c1 x i32 : (i32) -> !llvm.ptr + omp.parallel { + omp.wsloop reduction(@add_f32 %0 -> %prv1 : !llvm.ptr) { + omp.simd reduction(@add_f32 %prv1 -> %prv2 : !llvm.ptr) { + omp.loop_nest (%iv) : i64 = (%lb) to (%ub) step (%step) { + %1 = llvm.mlir.constant(2.0 : f32) : f32 + %2 = llvm.load %prv2 : !llvm.ptr -> f32 + %3 = llvm.fadd %1, %2 : f32 + llvm.store %3, %prv2 : f32, !llvm.ptr + omp.yield + } + } {omp.composite} + } {omp.composite} + omp.terminator + } + llvm.return +} + +// Same checks as for wsloop reduction, because currently omp.simd is ignored in +// a composite 'do/for simd' construct. +// Call to the outlined function. +// CHECK: call void {{.*}} @__kmpc_fork_call +// CHECK-SAME: @[[OUTLINED:[A-Za-z_.][A-Za-z0-9_.]*]] + +// Outlined function. +// CHECK: define internal void @[[OUTLINED]] + +// Private reduction variable and its initialization. +// CHECK: %[[PRIVATE:.+]] = alloca float +// CHECK: store float 0.000000e+00, ptr %[[PRIVATE]] + +// Call to the reduction function. +// CHECK: call i32 @__kmpc_reduce +// CHECK-SAME: @[[REDFUNC:[A-Za-z_.][A-Za-z0-9_.]*]] + +// Atomic reduction. +// CHECK: %[[PARTIAL:.+]] = load float, ptr %[[PRIVATE]] +// CHECK: atomicrmw fadd ptr %{{.*}}, float %[[PARTIAL]] + +// Non-atomic reduction: +// CHECK: fadd float +// CHECK: call void @__kmpc_end_reduce +// CHECK: br label %[[FINALIZE:.+]] + +// CHECK: [[FINALIZE]]: +// CHECK: call void @__kmpc_barrier + +// Update of the private variable using the reduction region +// (the body block currently comes after all the other blocks). +// CHECK: %[[PARTIAL:.+]] = load float, ptr %[[PRIVATE]] +// CHECK: %[[UPDATED:.+]] = fadd float 2.000000e+00, %[[PARTIAL]] +// CHECK: store float %[[UPDATED]], ptr %[[PRIVATE]] + +// Reduction function. +// CHECK: define internal void @[[REDFUNC]] +// CHECK: fadd float diff --git a/mlir/test/Transforms/test-legalize-erased-op-with-uses.mlir b/mlir/test/Transforms/test-legalize-erased-op-with-uses.mlir index 6e8f0162e505d0..031442b0ee2daf 100644 --- a/mlir/test/Transforms/test-legalize-erased-op-with-uses.mlir +++ b/mlir/test/Transforms/test-legalize-erased-op-with-uses.mlir @@ -3,7 +3,7 @@ // Test that an error is emitted when an operation is marked as "erased", but // has users that live across the conversion. func.func @remove_all_ops(%arg0: i32) -> i32 { - // expected-error@below {{failed to legalize unresolved materialization from () to 'i32' that remained live after conversion}} + // expected-error@below {{failed to legalize unresolved materialization from () to ('i32') that remained live after conversion}} %0 = "test.illegal_op_a"() : () -> i32 // expected-note@below {{see existing live user here}} return %0 : i32 diff --git a/mlir/test/Transforms/test-legalize-type-conversion.mlir b/mlir/test/Transforms/test-legalize-type-conversion.mlir index f130adff42f8cd..db8bd0f6378d29 100644 --- a/mlir/test/Transforms/test-legalize-type-conversion.mlir +++ b/mlir/test/Transforms/test-legalize-type-conversion.mlir @@ -2,7 +2,7 @@ func.func @test_invalid_arg_materialization( - // expected-error@below {{failed to legalize unresolved materialization from () to 'i16' that remained live after conversion}} + // expected-error@below {{failed to legalize unresolved materialization from () to ('i16') that remained live after conversion}} %arg0: i16) { // expected-note@below{{see existing live user here}} "foo.return"(%arg0) : (i16) -> () @@ -21,7 +21,7 @@ func.func @test_valid_arg_materialization(%arg0: i64) { // ----- func.func @test_invalid_result_materialization() { - // expected-error@below {{failed to legalize unresolved materialization from ('f64') to 'f16' that remained live after conversion}} + // expected-error@below {{failed to legalize unresolved materialization from ('f64') to ('f16') that remained live after conversion}} %result = "test.type_producer"() : () -> f16 // expected-note@below{{see existing live user here}} "foo.return"(%result) : (f16) -> () @@ -30,7 +30,7 @@ func.func @test_invalid_result_materialization() { // ----- func.func @test_invalid_result_materialization() { - // expected-error@below {{failed to legalize unresolved materialization from ('f64') to 'f16' that remained live after conversion}} + // expected-error@below {{failed to legalize unresolved materialization from ('f64') to ('f16') that remained live after conversion}} %result = "test.type_producer"() : () -> f16 // expected-note@below{{see existing live user here}} "foo.return"(%result) : (f16) -> () @@ -50,7 +50,7 @@ func.func @test_transitive_use_materialization() { // ----- func.func @test_transitive_use_invalid_materialization() { - // expected-error@below {{failed to legalize unresolved materialization from ('f64') to 'f16' that remained live after conversion}} + // expected-error@below {{failed to legalize unresolved materialization from ('f64') to ('f16') that remained live after conversion}} %result = "test.another_type_producer"() : () -> f16 // expected-note@below{{see existing live user here}} "foo.return"(%result) : (f16) -> () @@ -102,7 +102,7 @@ func.func @test_block_argument_not_converted() { // Make sure argument type changes aren't implicitly forwarded. func.func @test_signature_conversion_no_converter() { "test.signature_conversion_no_converter"() ({ - // expected-error@below {{failed to legalize unresolved materialization from ('f64') to 'f32' that remained live after conversion}} + // expected-error@below {{failed to legalize unresolved materialization from ('f64') to ('f32') that remained live after conversion}} ^bb0(%arg0: f32): "test.type_consumer"(%arg0) : (f32) -> () // expected-note@below{{see existing live user here}} diff --git a/mlir/tools/mlir-tblgen/LLVMIRIntrinsicGen.cpp b/mlir/tools/mlir-tblgen/LLVMIRIntrinsicGen.cpp index 411a98a48bfb28..525c8d6d3e89bc 100644 --- a/mlir/tools/mlir-tblgen/LLVMIRIntrinsicGen.cpp +++ b/mlir/tools/mlir-tblgen/LLVMIRIntrinsicGen.cpp @@ -76,7 +76,7 @@ static IndicesTy getOverloadableTypeIdxs(const Record &record, case llvm::MVT::iAny: case llvm::MVT::fAny: case llvm::MVT::Any: - case llvm::MVT::iPTRAny: + case llvm::MVT::pAny: case llvm::MVT::vAny: overloadedOps.set(r.index()); break; diff --git a/offload/plugins-nextgen/amdgpu/src/rtl.cpp b/offload/plugins-nextgen/amdgpu/src/rtl.cpp index f0cc0c2e4d08e5..bdb33d4f4ab27c 100644 --- a/offload/plugins-nextgen/amdgpu/src/rtl.cpp +++ b/offload/plugins-nextgen/amdgpu/src/rtl.cpp @@ -927,6 +927,8 @@ struct AMDGPUStreamTy { AMDGPUSignalManagerTy *SignalManager; }; + using AMDGPUStreamCallbackTy = Error(void *Data); + /// The stream is composed of N stream's slots. The struct below represents /// the fields of each slot. Each slot has a signal and an optional action /// function. When appending an HSA asynchronous operation to the stream, one @@ -942,65 +944,82 @@ struct AMDGPUStreamTy { /// operation as input signal. AMDGPUSignalTy *Signal; - /// The action that must be performed after the operation's completion. Set + /// The actions that must be performed after the operation's completion. Set /// to nullptr when there is no action to perform. - Error (*ActionFunction)(void *); + llvm::SmallVector Callbacks; /// Space for the action's arguments. A pointer to these arguments is passed /// to the action function. Notice the space of arguments is limited. - union { + union ActionArgsTy { MemcpyArgsTy MemcpyArgs; ReleaseBufferArgsTy ReleaseBufferArgs; ReleaseSignalArgsTy ReleaseSignalArgs; - } ActionArgs; + void *CallbackArgs; + }; + + llvm::SmallVector ActionArgs; /// Create an empty slot. - StreamSlotTy() : Signal(nullptr), ActionFunction(nullptr) {} + StreamSlotTy() : Signal(nullptr), Callbacks({}), ActionArgs({}) {} /// Schedule a host memory copy action on the slot. Error schedHostMemoryCopy(void *Dst, const void *Src, size_t Size) { - ActionFunction = memcpyAction; - ActionArgs.MemcpyArgs = MemcpyArgsTy{Dst, Src, Size}; + Callbacks.emplace_back(memcpyAction); + ActionArgs.emplace_back().MemcpyArgs = MemcpyArgsTy{Dst, Src, Size}; return Plugin::success(); } /// Schedule a release buffer action on the slot. Error schedReleaseBuffer(void *Buffer, AMDGPUMemoryManagerTy &Manager) { - ActionFunction = releaseBufferAction; - ActionArgs.ReleaseBufferArgs = ReleaseBufferArgsTy{Buffer, &Manager}; + Callbacks.emplace_back(releaseBufferAction); + ActionArgs.emplace_back().ReleaseBufferArgs = + ReleaseBufferArgsTy{Buffer, &Manager}; return Plugin::success(); } /// Schedule a signal release action on the slot. Error schedReleaseSignal(AMDGPUSignalTy *SignalToRelease, AMDGPUSignalManagerTy *SignalManager) { - ActionFunction = releaseSignalAction; - ActionArgs.ReleaseSignalArgs = + Callbacks.emplace_back(releaseSignalAction); + ActionArgs.emplace_back().ReleaseSignalArgs = ReleaseSignalArgsTy{SignalToRelease, SignalManager}; return Plugin::success(); } + /// Register a callback to be called on compleition + Error schedCallback(AMDGPUStreamCallbackTy *Func, void *Data) { + Callbacks.emplace_back(Func); + ActionArgs.emplace_back().CallbackArgs = Data; + + return Plugin::success(); + } + // Perform the action if needed. Error performAction() { - if (!ActionFunction) + if (Callbacks.empty()) return Plugin::success(); - // Perform the action. - if (ActionFunction == memcpyAction) { - if (auto Err = memcpyAction(&ActionArgs)) - return Err; - } else if (ActionFunction == releaseBufferAction) { - if (auto Err = releaseBufferAction(&ActionArgs)) - return Err; - } else if (ActionFunction == releaseSignalAction) { - if (auto Err = releaseSignalAction(&ActionArgs)) - return Err; - } else { - return Plugin::error("Unknown action function!"); + assert(Callbacks.size() == ActionArgs.size() && "Size mismatch"); + for (auto [Callback, ActionArg] : llvm::zip(Callbacks, ActionArgs)) { + // Perform the action. + if (Callback == memcpyAction) { + if (auto Err = memcpyAction(&ActionArg)) + return Err; + } else if (Callback == releaseBufferAction) { + if (auto Err = releaseBufferAction(&ActionArg)) + return Err; + } else if (Callback == releaseSignalAction) { + if (auto Err = releaseSignalAction(&ActionArg)) + return Err; + } else if (Callback) { + if (auto Err = Callback(ActionArg.CallbackArgs)) + return Err; + } } // Invalidate the action. - ActionFunction = nullptr; + Callbacks.clear(); + ActionArgs.clear(); return Plugin::success(); } diff --git a/utils/bazel/llvm-project-overlay/clang/BUILD.bazel b/utils/bazel/llvm-project-overlay/clang/BUILD.bazel index db928deb170602..5e756e2ed9629f 100644 --- a/utils/bazel/llvm-project-overlay/clang/BUILD.bazel +++ b/utils/bazel/llvm-project-overlay/clang/BUILD.bazel @@ -364,6 +364,20 @@ gentbl( ], ) +gentbl( + name="basic_builtins_x86_gen", + tbl_outs = [( + "-gen-clang-builtins", + "include/clang/Basic/BuiltinsX86.inc", + )], + tblgen = ":clang-tblgen", + td_file = "include/clang/Basic/BuiltinsX86.td", + td_srcs = [ + "include/clang/Basic/BuiltinsX86.td", + "include/clang/Basic/BuiltinsBase.td", + ], +) + gentbl( name = "basic_builtins_gen", tbl_outs = [( @@ -701,6 +715,7 @@ cc_library( ":basic_builtins_bpf_gen", ":basic_builtins_gen", ":basic_builtins_riscv_gen", + ":basic_builtins_x86_gen", ":basic_internal_headers", ":basic_riscv_sifive_vector_builtins_gen", ":basic_riscv_vector_builtin_cg_gen", diff --git a/utils/bazel/llvm-project-overlay/libc/BUILD.bazel b/utils/bazel/llvm-project-overlay/libc/BUILD.bazel index 774366d48a2161..d4aeaea6fac845 100644 --- a/utils/bazel/llvm-project-overlay/libc/BUILD.bazel +++ b/utils/bazel/llvm-project-overlay/libc/BUILD.bazel @@ -136,6 +136,17 @@ libc_support_library( hdrs = ["hdr/fenv_macros.h"], ) +libc_support_library( + name = "hdr_fcntl_macros", + hdrs = ["hdr/fcntl_macros.h"], + deps = [":hdr_fcntl_overlay"], +) + +libc_support_library( + name = "hdr_fcntl_overlay", + hdrs = ["hdr/fcntl_overlay.h"], +) + libc_support_library( name = "hdr_signal_macros", hdrs = ["hdr/signal_macros.h"], @@ -201,6 +212,12 @@ libc_support_library( hdrs = ["hdr/types/fexcept_t.h"], ) +libc_support_library( + name = "types_mode_t", + hdrs = ["hdr/types/mode_t.h"], + deps = [":hdr_fcntl_overlay"], +) + libc_support_library( name = "types_sigset_t", hdrs = ["hdr/types/sigset_t.h"], @@ -3488,6 +3505,8 @@ libc_function( ":__support_common", ":__support_osutil_syscall", ":errno", + ":hdr_fcntl_macros", + ":types_mode_t", ], ) @@ -3503,6 +3522,8 @@ libc_function( ":__support_common", ":__support_osutil_syscall", ":errno", + ":hdr_fcntl_macros", + ":types_mode_t", ], ) @@ -3514,6 +3535,7 @@ libc_function( ":__support_common", ":__support_osutil_syscall", ":errno", + ":hdr_fcntl_macros", ], ) @@ -3527,6 +3549,7 @@ libc_function( ":__support_common", ":__support_osutil_syscall", ":errno", + ":hdr_fcntl_macros", ], ) @@ -3571,6 +3594,7 @@ libc_function( ":__support_common", ":__support_osutil_syscall", ":errno", + ":hdr_fcntl_macros", ], ) @@ -3710,6 +3734,7 @@ libc_function( ":__support_common", ":__support_osutil_syscall", ":errno", + ":hdr_fcntl_macros", ], ) @@ -3721,6 +3746,7 @@ libc_function( ":__support_common", ":__support_osutil_syscall", ":errno", + ":hdr_fcntl_macros", ], ) @@ -3800,6 +3826,7 @@ libc_function( ":__support_common", ":__support_osutil_syscall", ":errno", + ":hdr_fcntl_macros", ], ) @@ -3811,6 +3838,7 @@ libc_function( ":__support_common", ":__support_osutil_syscall", ":errno", + ":hdr_fcntl_macros", ], ) @@ -3822,6 +3850,7 @@ libc_function( ":__support_common", ":__support_osutil_syscall", ":errno", + ":hdr_fcntl_macros", ], ) @@ -3833,6 +3862,7 @@ libc_function( ":__support_common", ":__support_osutil_syscall", ":errno", + ":hdr_fcntl_macros", ], ) @@ -3844,6 +3874,7 @@ libc_function( ":__support_common", ":__support_osutil_syscall", ":errno", + ":hdr_fcntl_macros", ], ) @@ -3891,6 +3922,7 @@ libc_function( ":__support_common", ":__support_osutil_syscall", ":errno", + ":hdr_fcntl_macros", ], ) @@ -3902,6 +3934,7 @@ libc_function( ":__support_common", ":__support_osutil_syscall", ":errno", + ":hdr_fcntl_macros", ], ) @@ -4161,6 +4194,7 @@ libc_function( ":__support_common", ":__support_osutil_syscall", ":errno", + ":hdr_fcntl_macros", ":hdr_stdio_overlay", ":types_FILE", ], @@ -4178,6 +4212,7 @@ libc_function( ":__support_common", ":__support_osutil_syscall", ":errno", + ":hdr_fcntl_macros", ":llvm_libc_macros_fcntl_macros", ], ) @@ -4192,6 +4227,8 @@ libc_function( ":__support_common", ":__support_osutil_syscall", ":errno", + ":hdr_fcntl_macros", + ":types_mode_t", ], )