diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp index 942a1ce950cec7..682bdc7071bc42 100644 --- a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp +++ b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp @@ -1080,6 +1080,8 @@ RISCVTargetLowering::RISCVTargetLowering(const TargetMachine &TM, VT, Custom); if (Subtarget.hasStdExtZfhmin()) setOperationAction(ISD::SPLAT_VECTOR, VT, Custom); + else + setOperationAction(ISD::SPLAT_VECTOR, MVT::f16, Custom); // load/store setOperationAction({ISD::LOAD, ISD::STORE}, VT, Custom); @@ -1117,6 +1119,8 @@ RISCVTargetLowering::RISCVTargetLowering(const TargetMachine &TM, VT, Custom); if (Subtarget.hasStdExtZfbfmin()) setOperationAction(ISD::SPLAT_VECTOR, VT, Custom); + else + setOperationAction(ISD::SPLAT_VECTOR, MVT::bf16, Custom); setOperationAction({ISD::LOAD, ISD::STORE}, VT, Custom); setOperationAction(ISD::FNEG, VT, Expand); @@ -6988,30 +6992,28 @@ SDValue RISCVTargetLowering::LowerOperation(SDValue Op, return lowerVECTOR_SPLICE(Op, DAG); case ISD::BUILD_VECTOR: return lowerBUILD_VECTOR(Op, DAG, Subtarget); - case ISD::SPLAT_VECTOR: - if ((Op.getValueType().getScalarType() == MVT::f16 && - (Subtarget.hasVInstructionsF16Minimal() && - Subtarget.hasStdExtZfhminOrZhinxmin() && - !Subtarget.hasVInstructionsF16())) || - (Op.getValueType().getScalarType() == MVT::bf16 && - (Subtarget.hasVInstructionsBF16Minimal() && - Subtarget.hasStdExtZfbfmin()))) { - if (Op.getValueType() == MVT::nxv32f16 || - Op.getValueType() == MVT::nxv32bf16) - return SplitVectorOp(Op, DAG); + case ISD::SPLAT_VECTOR: { + MVT VT = Op.getSimpleValueType(); + MVT EltVT = VT.getVectorElementType(); + if ((EltVT == MVT::f16 && !Subtarget.hasStdExtZvfh()) || + EltVT == MVT::bf16) { SDLoc DL(Op); - SDValue NewScalar = - DAG.getNode(ISD::FP_EXTEND, DL, MVT::f32, Op.getOperand(0)); - SDValue NewSplat = DAG.getNode( - ISD::SPLAT_VECTOR, DL, - MVT::getVectorVT(MVT::f32, Op.getValueType().getVectorElementCount()), - NewScalar); - return DAG.getNode(ISD::FP_ROUND, DL, Op.getValueType(), NewSplat, - DAG.getIntPtrConstant(0, DL, /*isTarget=*/true)); + SDValue Elt; + if ((EltVT == MVT::bf16 && Subtarget.hasStdExtZfbfmin()) || + (EltVT == MVT::f16 && Subtarget.hasStdExtZfhmin())) + Elt = DAG.getNode(RISCVISD::FMV_X_ANYEXTH, DL, Subtarget.getXLenVT(), + Op.getOperand(0)); + else + Elt = DAG.getNode(ISD::BITCAST, DL, MVT::i16, Op.getOperand(0)); + MVT IVT = VT.changeVectorElementType(MVT::i16); + return DAG.getNode(ISD::BITCAST, DL, VT, + DAG.getNode(ISD::SPLAT_VECTOR, DL, IVT, Elt)); } - if (Op.getValueType().getVectorElementType() == MVT::i1) + + if (EltVT == MVT::i1) return lowerVectorMaskSplat(Op, DAG); return SDValue(); + } case ISD::VECTOR_SHUFFLE: return lowerVECTOR_SHUFFLE(Op, DAG, Subtarget); case ISD::CONCAT_VECTORS: { diff --git a/llvm/test/CodeGen/RISCV/rvv/setcc-fp-vp.ll b/llvm/test/CodeGen/RISCV/rvv/setcc-fp-vp.ll index 12604711be1911..e9b6126323de02 100644 --- a/llvm/test/CodeGen/RISCV/rvv/setcc-fp-vp.ll +++ b/llvm/test/CodeGen/RISCV/rvv/setcc-fp-vp.ll @@ -38,15 +38,13 @@ define @fcmp_oeq_vf_nxv1f16( %va, half %b, ; ; ZVFHMIN-LABEL: fcmp_oeq_vf_nxv1f16: ; ZVFHMIN: # %bb.0: -; ZVFHMIN-NEXT: fcvt.s.h fa5, fa0 -; ZVFHMIN-NEXT: vsetvli a1, zero, e32, mf2, ta, ma -; ZVFHMIN-NEXT: vfmv.v.f v9, fa5 -; ZVFHMIN-NEXT: vsetvli zero, zero, e16, mf4, ta, ma -; ZVFHMIN-NEXT: vfncvt.f.f.w v10, v9 -; ZVFHMIN-NEXT: vfwcvt.f.f.v v9, v8 -; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v10 +; ZVFHMIN-NEXT: fmv.x.h a1, fa0 +; ZVFHMIN-NEXT: vsetvli a2, zero, e16, mf4, ta, ma +; ZVFHMIN-NEXT: vmv.v.x v9, a1 +; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v8 +; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v9 ; ZVFHMIN-NEXT: vsetvli zero, a0, e32, mf2, ta, ma -; ZVFHMIN-NEXT: vmfeq.vv v0, v9, v8, v0.t +; ZVFHMIN-NEXT: vmfeq.vv v0, v10, v8, v0.t ; ZVFHMIN-NEXT: ret %elt.head = insertelement poison, half %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer @@ -63,15 +61,13 @@ define @fcmp_oeq_vf_swap_nxv1f16( %va, half ; ; ZVFHMIN-LABEL: fcmp_oeq_vf_swap_nxv1f16: ; ZVFHMIN: # %bb.0: -; ZVFHMIN-NEXT: fcvt.s.h fa5, fa0 -; ZVFHMIN-NEXT: vsetvli a1, zero, e32, mf2, ta, ma -; ZVFHMIN-NEXT: vfmv.v.f v9, fa5 -; ZVFHMIN-NEXT: vsetvli zero, zero, e16, mf4, ta, ma -; ZVFHMIN-NEXT: vfncvt.f.f.w v10, v9 -; ZVFHMIN-NEXT: vfwcvt.f.f.v v9, v8 -; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v10 +; ZVFHMIN-NEXT: fmv.x.h a1, fa0 +; ZVFHMIN-NEXT: vsetvli a2, zero, e16, mf4, ta, ma +; ZVFHMIN-NEXT: vmv.v.x v9, a1 +; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v8 +; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v9 ; ZVFHMIN-NEXT: vsetvli zero, a0, e32, mf2, ta, ma -; ZVFHMIN-NEXT: vmfeq.vv v0, v8, v9, v0.t +; ZVFHMIN-NEXT: vmfeq.vv v0, v8, v10, v0.t ; ZVFHMIN-NEXT: ret %elt.head = insertelement poison, half %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer @@ -107,15 +103,13 @@ define @fcmp_ogt_vf_nxv1f16( %va, half %b, ; ; ZVFHMIN-LABEL: fcmp_ogt_vf_nxv1f16: ; ZVFHMIN: # %bb.0: -; ZVFHMIN-NEXT: fcvt.s.h fa5, fa0 -; ZVFHMIN-NEXT: vsetvli a1, zero, e32, mf2, ta, ma -; ZVFHMIN-NEXT: vfmv.v.f v9, fa5 -; ZVFHMIN-NEXT: vsetvli zero, zero, e16, mf4, ta, ma -; ZVFHMIN-NEXT: vfncvt.f.f.w v10, v9 -; ZVFHMIN-NEXT: vfwcvt.f.f.v v9, v8 -; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v10 +; ZVFHMIN-NEXT: fmv.x.h a1, fa0 +; ZVFHMIN-NEXT: vsetvli a2, zero, e16, mf4, ta, ma +; ZVFHMIN-NEXT: vmv.v.x v9, a1 +; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v8 +; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v9 ; ZVFHMIN-NEXT: vsetvli zero, a0, e32, mf2, ta, ma -; ZVFHMIN-NEXT: vmflt.vv v0, v8, v9, v0.t +; ZVFHMIN-NEXT: vmflt.vv v0, v8, v10, v0.t ; ZVFHMIN-NEXT: ret %elt.head = insertelement poison, half %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer @@ -132,15 +126,13 @@ define @fcmp_ogt_vf_swap_nxv1f16( %va, half ; ; ZVFHMIN-LABEL: fcmp_ogt_vf_swap_nxv1f16: ; ZVFHMIN: # %bb.0: -; ZVFHMIN-NEXT: fcvt.s.h fa5, fa0 -; ZVFHMIN-NEXT: vsetvli a1, zero, e32, mf2, ta, ma -; ZVFHMIN-NEXT: vfmv.v.f v9, fa5 -; ZVFHMIN-NEXT: vsetvli zero, zero, e16, mf4, ta, ma -; ZVFHMIN-NEXT: vfncvt.f.f.w v10, v9 -; ZVFHMIN-NEXT: vfwcvt.f.f.v v9, v8 -; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v10 +; ZVFHMIN-NEXT: fmv.x.h a1, fa0 +; ZVFHMIN-NEXT: vsetvli a2, zero, e16, mf4, ta, ma +; ZVFHMIN-NEXT: vmv.v.x v9, a1 +; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v8 +; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v9 ; ZVFHMIN-NEXT: vsetvli zero, a0, e32, mf2, ta, ma -; ZVFHMIN-NEXT: vmflt.vv v0, v9, v8, v0.t +; ZVFHMIN-NEXT: vmflt.vv v0, v10, v8, v0.t ; ZVFHMIN-NEXT: ret %elt.head = insertelement poison, half %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer @@ -176,15 +168,13 @@ define @fcmp_oge_vf_nxv1f16( %va, half %b, ; ; ZVFHMIN-LABEL: fcmp_oge_vf_nxv1f16: ; ZVFHMIN: # %bb.0: -; ZVFHMIN-NEXT: fcvt.s.h fa5, fa0 -; ZVFHMIN-NEXT: vsetvli a1, zero, e32, mf2, ta, ma -; ZVFHMIN-NEXT: vfmv.v.f v9, fa5 -; ZVFHMIN-NEXT: vsetvli zero, zero, e16, mf4, ta, ma -; ZVFHMIN-NEXT: vfncvt.f.f.w v10, v9 -; ZVFHMIN-NEXT: vfwcvt.f.f.v v9, v8 -; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v10 +; ZVFHMIN-NEXT: fmv.x.h a1, fa0 +; ZVFHMIN-NEXT: vsetvli a2, zero, e16, mf4, ta, ma +; ZVFHMIN-NEXT: vmv.v.x v9, a1 +; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v8 +; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v9 ; ZVFHMIN-NEXT: vsetvli zero, a0, e32, mf2, ta, ma -; ZVFHMIN-NEXT: vmfle.vv v0, v8, v9, v0.t +; ZVFHMIN-NEXT: vmfle.vv v0, v8, v10, v0.t ; ZVFHMIN-NEXT: ret %elt.head = insertelement poison, half %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer @@ -201,15 +191,13 @@ define @fcmp_oge_vf_swap_nxv1f16( %va, half ; ; ZVFHMIN-LABEL: fcmp_oge_vf_swap_nxv1f16: ; ZVFHMIN: # %bb.0: -; ZVFHMIN-NEXT: fcvt.s.h fa5, fa0 -; ZVFHMIN-NEXT: vsetvli a1, zero, e32, mf2, ta, ma -; ZVFHMIN-NEXT: vfmv.v.f v9, fa5 -; ZVFHMIN-NEXT: vsetvli zero, zero, e16, mf4, ta, ma -; ZVFHMIN-NEXT: vfncvt.f.f.w v10, v9 -; ZVFHMIN-NEXT: vfwcvt.f.f.v v9, v8 -; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v10 +; ZVFHMIN-NEXT: fmv.x.h a1, fa0 +; ZVFHMIN-NEXT: vsetvli a2, zero, e16, mf4, ta, ma +; ZVFHMIN-NEXT: vmv.v.x v9, a1 +; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v8 +; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v9 ; ZVFHMIN-NEXT: vsetvli zero, a0, e32, mf2, ta, ma -; ZVFHMIN-NEXT: vmfle.vv v0, v9, v8, v0.t +; ZVFHMIN-NEXT: vmfle.vv v0, v10, v8, v0.t ; ZVFHMIN-NEXT: ret %elt.head = insertelement poison, half %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer @@ -245,15 +233,13 @@ define @fcmp_olt_vf_nxv1f16( %va, half %b, ; ; ZVFHMIN-LABEL: fcmp_olt_vf_nxv1f16: ; ZVFHMIN: # %bb.0: -; ZVFHMIN-NEXT: fcvt.s.h fa5, fa0 -; ZVFHMIN-NEXT: vsetvli a1, zero, e32, mf2, ta, ma -; ZVFHMIN-NEXT: vfmv.v.f v9, fa5 -; ZVFHMIN-NEXT: vsetvli zero, zero, e16, mf4, ta, ma -; ZVFHMIN-NEXT: vfncvt.f.f.w v10, v9 -; ZVFHMIN-NEXT: vfwcvt.f.f.v v9, v8 -; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v10 +; ZVFHMIN-NEXT: fmv.x.h a1, fa0 +; ZVFHMIN-NEXT: vsetvli a2, zero, e16, mf4, ta, ma +; ZVFHMIN-NEXT: vmv.v.x v9, a1 +; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v8 +; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v9 ; ZVFHMIN-NEXT: vsetvli zero, a0, e32, mf2, ta, ma -; ZVFHMIN-NEXT: vmflt.vv v0, v9, v8, v0.t +; ZVFHMIN-NEXT: vmflt.vv v0, v10, v8, v0.t ; ZVFHMIN-NEXT: ret %elt.head = insertelement poison, half %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer @@ -270,15 +256,13 @@ define @fcmp_olt_vf_swap_nxv1f16( %va, half ; ; ZVFHMIN-LABEL: fcmp_olt_vf_swap_nxv1f16: ; ZVFHMIN: # %bb.0: -; ZVFHMIN-NEXT: fcvt.s.h fa5, fa0 -; ZVFHMIN-NEXT: vsetvli a1, zero, e32, mf2, ta, ma -; ZVFHMIN-NEXT: vfmv.v.f v9, fa5 -; ZVFHMIN-NEXT: vsetvli zero, zero, e16, mf4, ta, ma -; ZVFHMIN-NEXT: vfncvt.f.f.w v10, v9 -; ZVFHMIN-NEXT: vfwcvt.f.f.v v9, v8 -; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v10 +; ZVFHMIN-NEXT: fmv.x.h a1, fa0 +; ZVFHMIN-NEXT: vsetvli a2, zero, e16, mf4, ta, ma +; ZVFHMIN-NEXT: vmv.v.x v9, a1 +; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v8 +; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v9 ; ZVFHMIN-NEXT: vsetvli zero, a0, e32, mf2, ta, ma -; ZVFHMIN-NEXT: vmflt.vv v0, v8, v9, v0.t +; ZVFHMIN-NEXT: vmflt.vv v0, v8, v10, v0.t ; ZVFHMIN-NEXT: ret %elt.head = insertelement poison, half %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer @@ -314,15 +298,13 @@ define @fcmp_ole_vf_nxv1f16( %va, half %b, ; ; ZVFHMIN-LABEL: fcmp_ole_vf_nxv1f16: ; ZVFHMIN: # %bb.0: -; ZVFHMIN-NEXT: fcvt.s.h fa5, fa0 -; ZVFHMIN-NEXT: vsetvli a1, zero, e32, mf2, ta, ma -; ZVFHMIN-NEXT: vfmv.v.f v9, fa5 -; ZVFHMIN-NEXT: vsetvli zero, zero, e16, mf4, ta, ma -; ZVFHMIN-NEXT: vfncvt.f.f.w v10, v9 -; ZVFHMIN-NEXT: vfwcvt.f.f.v v9, v8 -; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v10 +; ZVFHMIN-NEXT: fmv.x.h a1, fa0 +; ZVFHMIN-NEXT: vsetvli a2, zero, e16, mf4, ta, ma +; ZVFHMIN-NEXT: vmv.v.x v9, a1 +; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v8 +; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v9 ; ZVFHMIN-NEXT: vsetvli zero, a0, e32, mf2, ta, ma -; ZVFHMIN-NEXT: vmfle.vv v0, v9, v8, v0.t +; ZVFHMIN-NEXT: vmfle.vv v0, v10, v8, v0.t ; ZVFHMIN-NEXT: ret %elt.head = insertelement poison, half %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer @@ -339,15 +321,13 @@ define @fcmp_ole_vf_swap_nxv1f16( %va, half ; ; ZVFHMIN-LABEL: fcmp_ole_vf_swap_nxv1f16: ; ZVFHMIN: # %bb.0: -; ZVFHMIN-NEXT: fcvt.s.h fa5, fa0 -; ZVFHMIN-NEXT: vsetvli a1, zero, e32, mf2, ta, ma -; ZVFHMIN-NEXT: vfmv.v.f v9, fa5 -; ZVFHMIN-NEXT: vsetvli zero, zero, e16, mf4, ta, ma -; ZVFHMIN-NEXT: vfncvt.f.f.w v10, v9 -; ZVFHMIN-NEXT: vfwcvt.f.f.v v9, v8 -; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v10 +; ZVFHMIN-NEXT: fmv.x.h a1, fa0 +; ZVFHMIN-NEXT: vsetvli a2, zero, e16, mf4, ta, ma +; ZVFHMIN-NEXT: vmv.v.x v9, a1 +; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v8 +; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v9 ; ZVFHMIN-NEXT: vsetvli zero, a0, e32, mf2, ta, ma -; ZVFHMIN-NEXT: vmfle.vv v0, v8, v9, v0.t +; ZVFHMIN-NEXT: vmfle.vv v0, v8, v10, v0.t ; ZVFHMIN-NEXT: ret %elt.head = insertelement poison, half %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer @@ -389,17 +369,15 @@ define @fcmp_one_vf_nxv1f16( %va, half %b, ; ; ZVFHMIN-LABEL: fcmp_one_vf_nxv1f16: ; ZVFHMIN: # %bb.0: -; ZVFHMIN-NEXT: fcvt.s.h fa5, fa0 -; ZVFHMIN-NEXT: vsetvli a1, zero, e32, mf2, ta, ma -; ZVFHMIN-NEXT: vfmv.v.f v9, fa5 -; ZVFHMIN-NEXT: vsetvli zero, zero, e16, mf4, ta, ma -; ZVFHMIN-NEXT: vfncvt.f.f.w v10, v9 -; ZVFHMIN-NEXT: vfwcvt.f.f.v v9, v8 -; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v10 +; ZVFHMIN-NEXT: fmv.x.h a1, fa0 +; ZVFHMIN-NEXT: vsetvli a2, zero, e16, mf4, ta, ma +; ZVFHMIN-NEXT: vmv.v.x v9, a1 +; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v8 +; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v9 ; ZVFHMIN-NEXT: vsetvli zero, a0, e32, mf2, ta, ma -; ZVFHMIN-NEXT: vmflt.vv v10, v9, v8, v0.t -; ZVFHMIN-NEXT: vmflt.vv v8, v8, v9, v0.t -; ZVFHMIN-NEXT: vmor.mm v0, v8, v10 +; ZVFHMIN-NEXT: vmflt.vv v9, v10, v8, v0.t +; ZVFHMIN-NEXT: vmflt.vv v8, v8, v10, v0.t +; ZVFHMIN-NEXT: vmor.mm v0, v8, v9 ; ZVFHMIN-NEXT: ret %elt.head = insertelement poison, half %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer @@ -418,17 +396,15 @@ define @fcmp_one_vf_swap_nxv1f16( %va, half ; ; ZVFHMIN-LABEL: fcmp_one_vf_swap_nxv1f16: ; ZVFHMIN: # %bb.0: -; ZVFHMIN-NEXT: fcvt.s.h fa5, fa0 -; ZVFHMIN-NEXT: vsetvli a1, zero, e32, mf2, ta, ma -; ZVFHMIN-NEXT: vfmv.v.f v9, fa5 -; ZVFHMIN-NEXT: vsetvli zero, zero, e16, mf4, ta, ma -; ZVFHMIN-NEXT: vfncvt.f.f.w v10, v9 -; ZVFHMIN-NEXT: vfwcvt.f.f.v v9, v8 -; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v10 +; ZVFHMIN-NEXT: fmv.x.h a1, fa0 +; ZVFHMIN-NEXT: vsetvli a2, zero, e16, mf4, ta, ma +; ZVFHMIN-NEXT: vmv.v.x v9, a1 +; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v8 +; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v9 ; ZVFHMIN-NEXT: vsetvli zero, a0, e32, mf2, ta, ma -; ZVFHMIN-NEXT: vmflt.vv v10, v8, v9, v0.t -; ZVFHMIN-NEXT: vmflt.vv v8, v9, v8, v0.t -; ZVFHMIN-NEXT: vmor.mm v0, v8, v10 +; ZVFHMIN-NEXT: vmflt.vv v9, v8, v10, v0.t +; ZVFHMIN-NEXT: vmflt.vv v8, v10, v8, v0.t +; ZVFHMIN-NEXT: vmor.mm v0, v8, v9 ; ZVFHMIN-NEXT: ret %elt.head = insertelement poison, half %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer @@ -474,18 +450,16 @@ define @fcmp_ord_vf_nxv1f16( %va, half %b, ; ; ZVFHMIN-LABEL: fcmp_ord_vf_nxv1f16: ; ZVFHMIN: # %bb.0: -; ZVFHMIN-NEXT: fcvt.s.h fa5, fa0 -; ZVFHMIN-NEXT: vsetvli a1, zero, e32, mf2, ta, ma -; ZVFHMIN-NEXT: vfmv.v.f v9, fa5 -; ZVFHMIN-NEXT: vsetvli zero, zero, e16, mf4, ta, ma -; ZVFHMIN-NEXT: vfncvt.f.f.w v10, v9 -; ZVFHMIN-NEXT: vfwcvt.f.f.v v9, v8 +; ZVFHMIN-NEXT: fmv.x.h a1, fa0 +; ZVFHMIN-NEXT: vsetvli a2, zero, e16, mf4, ta, ma +; ZVFHMIN-NEXT: vmv.v.x v9, a1 +; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v8 ; ZVFHMIN-NEXT: vsetvli zero, a0, e32, mf2, ta, ma -; ZVFHMIN-NEXT: vmfeq.vv v8, v9, v9, v0.t +; ZVFHMIN-NEXT: vmfeq.vv v8, v10, v10, v0.t ; ZVFHMIN-NEXT: vsetvli a1, zero, e16, mf4, ta, ma -; ZVFHMIN-NEXT: vfwcvt.f.f.v v9, v10 +; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v9 ; ZVFHMIN-NEXT: vsetvli zero, a0, e32, mf2, ta, ma -; ZVFHMIN-NEXT: vmfeq.vv v9, v9, v9, v0.t +; ZVFHMIN-NEXT: vmfeq.vv v9, v10, v10, v0.t ; ZVFHMIN-NEXT: vmand.mm v0, v8, v9 ; ZVFHMIN-NEXT: ret %elt.head = insertelement poison, half %b, i32 0 @@ -507,18 +481,16 @@ define @fcmp_ord_vf_swap_nxv1f16( %va, half ; ; ZVFHMIN-LABEL: fcmp_ord_vf_swap_nxv1f16: ; ZVFHMIN: # %bb.0: -; ZVFHMIN-NEXT: fcvt.s.h fa5, fa0 -; ZVFHMIN-NEXT: vsetvli a1, zero, e32, mf2, ta, ma -; ZVFHMIN-NEXT: vfmv.v.f v9, fa5 -; ZVFHMIN-NEXT: vsetvli zero, zero, e16, mf4, ta, ma -; ZVFHMIN-NEXT: vfncvt.f.f.w v10, v9 -; ZVFHMIN-NEXT: vfwcvt.f.f.v v9, v8 +; ZVFHMIN-NEXT: fmv.x.h a1, fa0 +; ZVFHMIN-NEXT: vsetvli a2, zero, e16, mf4, ta, ma +; ZVFHMIN-NEXT: vmv.v.x v9, a1 +; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v8 ; ZVFHMIN-NEXT: vsetvli zero, a0, e32, mf2, ta, ma -; ZVFHMIN-NEXT: vmfeq.vv v8, v9, v9, v0.t +; ZVFHMIN-NEXT: vmfeq.vv v8, v10, v10, v0.t ; ZVFHMIN-NEXT: vsetvli a1, zero, e16, mf4, ta, ma -; ZVFHMIN-NEXT: vfwcvt.f.f.v v9, v10 +; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v9 ; ZVFHMIN-NEXT: vsetvli zero, a0, e32, mf2, ta, ma -; ZVFHMIN-NEXT: vmfeq.vv v9, v9, v9, v0.t +; ZVFHMIN-NEXT: vmfeq.vv v9, v10, v10, v0.t ; ZVFHMIN-NEXT: vmand.mm v0, v9, v8 ; ZVFHMIN-NEXT: ret %elt.head = insertelement poison, half %b, i32 0 @@ -561,17 +533,15 @@ define @fcmp_ueq_vf_nxv1f16( %va, half %b, ; ; ZVFHMIN-LABEL: fcmp_ueq_vf_nxv1f16: ; ZVFHMIN: # %bb.0: -; ZVFHMIN-NEXT: fcvt.s.h fa5, fa0 -; ZVFHMIN-NEXT: vsetvli a1, zero, e32, mf2, ta, ma -; ZVFHMIN-NEXT: vfmv.v.f v9, fa5 -; ZVFHMIN-NEXT: vsetvli zero, zero, e16, mf4, ta, ma -; ZVFHMIN-NEXT: vfncvt.f.f.w v10, v9 -; ZVFHMIN-NEXT: vfwcvt.f.f.v v9, v8 -; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v10 +; ZVFHMIN-NEXT: fmv.x.h a1, fa0 +; ZVFHMIN-NEXT: vsetvli a2, zero, e16, mf4, ta, ma +; ZVFHMIN-NEXT: vmv.v.x v9, a1 +; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v8 +; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v9 ; ZVFHMIN-NEXT: vsetvli zero, a0, e32, mf2, ta, ma -; ZVFHMIN-NEXT: vmflt.vv v10, v9, v8, v0.t -; ZVFHMIN-NEXT: vmflt.vv v8, v8, v9, v0.t -; ZVFHMIN-NEXT: vmnor.mm v0, v8, v10 +; ZVFHMIN-NEXT: vmflt.vv v9, v10, v8, v0.t +; ZVFHMIN-NEXT: vmflt.vv v8, v8, v10, v0.t +; ZVFHMIN-NEXT: vmnor.mm v0, v8, v9 ; ZVFHMIN-NEXT: ret %elt.head = insertelement poison, half %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer @@ -590,17 +560,15 @@ define @fcmp_ueq_vf_swap_nxv1f16( %va, half ; ; ZVFHMIN-LABEL: fcmp_ueq_vf_swap_nxv1f16: ; ZVFHMIN: # %bb.0: -; ZVFHMIN-NEXT: fcvt.s.h fa5, fa0 -; ZVFHMIN-NEXT: vsetvli a1, zero, e32, mf2, ta, ma -; ZVFHMIN-NEXT: vfmv.v.f v9, fa5 -; ZVFHMIN-NEXT: vsetvli zero, zero, e16, mf4, ta, ma -; ZVFHMIN-NEXT: vfncvt.f.f.w v10, v9 -; ZVFHMIN-NEXT: vfwcvt.f.f.v v9, v8 -; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v10 +; ZVFHMIN-NEXT: fmv.x.h a1, fa0 +; ZVFHMIN-NEXT: vsetvli a2, zero, e16, mf4, ta, ma +; ZVFHMIN-NEXT: vmv.v.x v9, a1 +; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v8 +; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v9 ; ZVFHMIN-NEXT: vsetvli zero, a0, e32, mf2, ta, ma -; ZVFHMIN-NEXT: vmflt.vv v10, v8, v9, v0.t -; ZVFHMIN-NEXT: vmflt.vv v8, v9, v8, v0.t -; ZVFHMIN-NEXT: vmnor.mm v0, v8, v10 +; ZVFHMIN-NEXT: vmflt.vv v9, v8, v10, v0.t +; ZVFHMIN-NEXT: vmflt.vv v8, v10, v8, v0.t +; ZVFHMIN-NEXT: vmnor.mm v0, v8, v9 ; ZVFHMIN-NEXT: ret %elt.head = insertelement poison, half %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer @@ -639,15 +607,13 @@ define @fcmp_ugt_vf_nxv1f16( %va, half %b, ; ; ZVFHMIN-LABEL: fcmp_ugt_vf_nxv1f16: ; ZVFHMIN: # %bb.0: -; ZVFHMIN-NEXT: fcvt.s.h fa5, fa0 -; ZVFHMIN-NEXT: vsetvli a1, zero, e32, mf2, ta, ma -; ZVFHMIN-NEXT: vfmv.v.f v9, fa5 -; ZVFHMIN-NEXT: vsetvli zero, zero, e16, mf4, ta, ma -; ZVFHMIN-NEXT: vfncvt.f.f.w v10, v9 -; ZVFHMIN-NEXT: vfwcvt.f.f.v v9, v8 -; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v10 +; ZVFHMIN-NEXT: fmv.x.h a1, fa0 +; ZVFHMIN-NEXT: vsetvli a2, zero, e16, mf4, ta, ma +; ZVFHMIN-NEXT: vmv.v.x v9, a1 +; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v8 +; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v9 ; ZVFHMIN-NEXT: vsetvli zero, a0, e32, mf2, ta, ma -; ZVFHMIN-NEXT: vmfle.vv v8, v9, v8, v0.t +; ZVFHMIN-NEXT: vmfle.vv v8, v10, v8, v0.t ; ZVFHMIN-NEXT: vmnot.m v0, v8 ; ZVFHMIN-NEXT: ret %elt.head = insertelement poison, half %b, i32 0 @@ -666,15 +632,13 @@ define @fcmp_ugt_vf_swap_nxv1f16( %va, half ; ; ZVFHMIN-LABEL: fcmp_ugt_vf_swap_nxv1f16: ; ZVFHMIN: # %bb.0: -; ZVFHMIN-NEXT: fcvt.s.h fa5, fa0 -; ZVFHMIN-NEXT: vsetvli a1, zero, e32, mf2, ta, ma -; ZVFHMIN-NEXT: vfmv.v.f v9, fa5 -; ZVFHMIN-NEXT: vsetvli zero, zero, e16, mf4, ta, ma -; ZVFHMIN-NEXT: vfncvt.f.f.w v10, v9 -; ZVFHMIN-NEXT: vfwcvt.f.f.v v9, v8 -; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v10 +; ZVFHMIN-NEXT: fmv.x.h a1, fa0 +; ZVFHMIN-NEXT: vsetvli a2, zero, e16, mf4, ta, ma +; ZVFHMIN-NEXT: vmv.v.x v9, a1 +; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v8 +; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v9 ; ZVFHMIN-NEXT: vsetvli zero, a0, e32, mf2, ta, ma -; ZVFHMIN-NEXT: vmfle.vv v8, v8, v9, v0.t +; ZVFHMIN-NEXT: vmfle.vv v8, v8, v10, v0.t ; ZVFHMIN-NEXT: vmnot.m v0, v8 ; ZVFHMIN-NEXT: ret %elt.head = insertelement poison, half %b, i32 0 @@ -714,15 +678,13 @@ define @fcmp_uge_vf_nxv1f16( %va, half %b, ; ; ZVFHMIN-LABEL: fcmp_uge_vf_nxv1f16: ; ZVFHMIN: # %bb.0: -; ZVFHMIN-NEXT: fcvt.s.h fa5, fa0 -; ZVFHMIN-NEXT: vsetvli a1, zero, e32, mf2, ta, ma -; ZVFHMIN-NEXT: vfmv.v.f v9, fa5 -; ZVFHMIN-NEXT: vsetvli zero, zero, e16, mf4, ta, ma -; ZVFHMIN-NEXT: vfncvt.f.f.w v10, v9 -; ZVFHMIN-NEXT: vfwcvt.f.f.v v9, v8 -; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v10 +; ZVFHMIN-NEXT: fmv.x.h a1, fa0 +; ZVFHMIN-NEXT: vsetvli a2, zero, e16, mf4, ta, ma +; ZVFHMIN-NEXT: vmv.v.x v9, a1 +; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v8 +; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v9 ; ZVFHMIN-NEXT: vsetvli zero, a0, e32, mf2, ta, ma -; ZVFHMIN-NEXT: vmflt.vv v8, v9, v8, v0.t +; ZVFHMIN-NEXT: vmflt.vv v8, v10, v8, v0.t ; ZVFHMIN-NEXT: vmnot.m v0, v8 ; ZVFHMIN-NEXT: ret %elt.head = insertelement poison, half %b, i32 0 @@ -741,15 +703,13 @@ define @fcmp_uge_vf_swap_nxv1f16( %va, half ; ; ZVFHMIN-LABEL: fcmp_uge_vf_swap_nxv1f16: ; ZVFHMIN: # %bb.0: -; ZVFHMIN-NEXT: fcvt.s.h fa5, fa0 -; ZVFHMIN-NEXT: vsetvli a1, zero, e32, mf2, ta, ma -; ZVFHMIN-NEXT: vfmv.v.f v9, fa5 -; ZVFHMIN-NEXT: vsetvli zero, zero, e16, mf4, ta, ma -; ZVFHMIN-NEXT: vfncvt.f.f.w v10, v9 -; ZVFHMIN-NEXT: vfwcvt.f.f.v v9, v8 -; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v10 +; ZVFHMIN-NEXT: fmv.x.h a1, fa0 +; ZVFHMIN-NEXT: vsetvli a2, zero, e16, mf4, ta, ma +; ZVFHMIN-NEXT: vmv.v.x v9, a1 +; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v8 +; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v9 ; ZVFHMIN-NEXT: vsetvli zero, a0, e32, mf2, ta, ma -; ZVFHMIN-NEXT: vmflt.vv v8, v8, v9, v0.t +; ZVFHMIN-NEXT: vmflt.vv v8, v8, v10, v0.t ; ZVFHMIN-NEXT: vmnot.m v0, v8 ; ZVFHMIN-NEXT: ret %elt.head = insertelement poison, half %b, i32 0 @@ -789,15 +749,13 @@ define @fcmp_ult_vf_nxv1f16( %va, half %b, ; ; ZVFHMIN-LABEL: fcmp_ult_vf_nxv1f16: ; ZVFHMIN: # %bb.0: -; ZVFHMIN-NEXT: fcvt.s.h fa5, fa0 -; ZVFHMIN-NEXT: vsetvli a1, zero, e32, mf2, ta, ma -; ZVFHMIN-NEXT: vfmv.v.f v9, fa5 -; ZVFHMIN-NEXT: vsetvli zero, zero, e16, mf4, ta, ma -; ZVFHMIN-NEXT: vfncvt.f.f.w v10, v9 -; ZVFHMIN-NEXT: vfwcvt.f.f.v v9, v8 -; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v10 +; ZVFHMIN-NEXT: fmv.x.h a1, fa0 +; ZVFHMIN-NEXT: vsetvli a2, zero, e16, mf4, ta, ma +; ZVFHMIN-NEXT: vmv.v.x v9, a1 +; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v8 +; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v9 ; ZVFHMIN-NEXT: vsetvli zero, a0, e32, mf2, ta, ma -; ZVFHMIN-NEXT: vmfle.vv v8, v8, v9, v0.t +; ZVFHMIN-NEXT: vmfle.vv v8, v8, v10, v0.t ; ZVFHMIN-NEXT: vmnot.m v0, v8 ; ZVFHMIN-NEXT: ret %elt.head = insertelement poison, half %b, i32 0 @@ -816,15 +774,13 @@ define @fcmp_ult_vf_swap_nxv1f16( %va, half ; ; ZVFHMIN-LABEL: fcmp_ult_vf_swap_nxv1f16: ; ZVFHMIN: # %bb.0: -; ZVFHMIN-NEXT: fcvt.s.h fa5, fa0 -; ZVFHMIN-NEXT: vsetvli a1, zero, e32, mf2, ta, ma -; ZVFHMIN-NEXT: vfmv.v.f v9, fa5 -; ZVFHMIN-NEXT: vsetvli zero, zero, e16, mf4, ta, ma -; ZVFHMIN-NEXT: vfncvt.f.f.w v10, v9 -; ZVFHMIN-NEXT: vfwcvt.f.f.v v9, v8 -; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v10 +; ZVFHMIN-NEXT: fmv.x.h a1, fa0 +; ZVFHMIN-NEXT: vsetvli a2, zero, e16, mf4, ta, ma +; ZVFHMIN-NEXT: vmv.v.x v9, a1 +; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v8 +; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v9 ; ZVFHMIN-NEXT: vsetvli zero, a0, e32, mf2, ta, ma -; ZVFHMIN-NEXT: vmfle.vv v8, v9, v8, v0.t +; ZVFHMIN-NEXT: vmfle.vv v8, v10, v8, v0.t ; ZVFHMIN-NEXT: vmnot.m v0, v8 ; ZVFHMIN-NEXT: ret %elt.head = insertelement poison, half %b, i32 0 @@ -864,15 +820,13 @@ define @fcmp_ule_vf_nxv1f16( %va, half %b, ; ; ZVFHMIN-LABEL: fcmp_ule_vf_nxv1f16: ; ZVFHMIN: # %bb.0: -; ZVFHMIN-NEXT: fcvt.s.h fa5, fa0 -; ZVFHMIN-NEXT: vsetvli a1, zero, e32, mf2, ta, ma -; ZVFHMIN-NEXT: vfmv.v.f v9, fa5 -; ZVFHMIN-NEXT: vsetvli zero, zero, e16, mf4, ta, ma -; ZVFHMIN-NEXT: vfncvt.f.f.w v10, v9 -; ZVFHMIN-NEXT: vfwcvt.f.f.v v9, v8 -; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v10 +; ZVFHMIN-NEXT: fmv.x.h a1, fa0 +; ZVFHMIN-NEXT: vsetvli a2, zero, e16, mf4, ta, ma +; ZVFHMIN-NEXT: vmv.v.x v9, a1 +; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v8 +; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v9 ; ZVFHMIN-NEXT: vsetvli zero, a0, e32, mf2, ta, ma -; ZVFHMIN-NEXT: vmflt.vv v8, v8, v9, v0.t +; ZVFHMIN-NEXT: vmflt.vv v8, v8, v10, v0.t ; ZVFHMIN-NEXT: vmnot.m v0, v8 ; ZVFHMIN-NEXT: ret %elt.head = insertelement poison, half %b, i32 0 @@ -891,15 +845,13 @@ define @fcmp_ule_vf_swap_nxv1f16( %va, half ; ; ZVFHMIN-LABEL: fcmp_ule_vf_swap_nxv1f16: ; ZVFHMIN: # %bb.0: -; ZVFHMIN-NEXT: fcvt.s.h fa5, fa0 -; ZVFHMIN-NEXT: vsetvli a1, zero, e32, mf2, ta, ma -; ZVFHMIN-NEXT: vfmv.v.f v9, fa5 -; ZVFHMIN-NEXT: vsetvli zero, zero, e16, mf4, ta, ma -; ZVFHMIN-NEXT: vfncvt.f.f.w v10, v9 -; ZVFHMIN-NEXT: vfwcvt.f.f.v v9, v8 -; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v10 +; ZVFHMIN-NEXT: fmv.x.h a1, fa0 +; ZVFHMIN-NEXT: vsetvli a2, zero, e16, mf4, ta, ma +; ZVFHMIN-NEXT: vmv.v.x v9, a1 +; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v8 +; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v9 ; ZVFHMIN-NEXT: vsetvli zero, a0, e32, mf2, ta, ma -; ZVFHMIN-NEXT: vmflt.vv v8, v9, v8, v0.t +; ZVFHMIN-NEXT: vmflt.vv v8, v10, v8, v0.t ; ZVFHMIN-NEXT: vmnot.m v0, v8 ; ZVFHMIN-NEXT: ret %elt.head = insertelement poison, half %b, i32 0 @@ -936,15 +888,13 @@ define @fcmp_une_vf_nxv1f16( %va, half %b, ; ; ZVFHMIN-LABEL: fcmp_une_vf_nxv1f16: ; ZVFHMIN: # %bb.0: -; ZVFHMIN-NEXT: fcvt.s.h fa5, fa0 -; ZVFHMIN-NEXT: vsetvli a1, zero, e32, mf2, ta, ma -; ZVFHMIN-NEXT: vfmv.v.f v9, fa5 -; ZVFHMIN-NEXT: vsetvli zero, zero, e16, mf4, ta, ma -; ZVFHMIN-NEXT: vfncvt.f.f.w v10, v9 -; ZVFHMIN-NEXT: vfwcvt.f.f.v v9, v8 -; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v10 +; ZVFHMIN-NEXT: fmv.x.h a1, fa0 +; ZVFHMIN-NEXT: vsetvli a2, zero, e16, mf4, ta, ma +; ZVFHMIN-NEXT: vmv.v.x v9, a1 +; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v8 +; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v9 ; ZVFHMIN-NEXT: vsetvli zero, a0, e32, mf2, ta, ma -; ZVFHMIN-NEXT: vmfne.vv v0, v9, v8, v0.t +; ZVFHMIN-NEXT: vmfne.vv v0, v10, v8, v0.t ; ZVFHMIN-NEXT: ret %elt.head = insertelement poison, half %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer @@ -961,15 +911,13 @@ define @fcmp_une_vf_swap_nxv1f16( %va, half ; ; ZVFHMIN-LABEL: fcmp_une_vf_swap_nxv1f16: ; ZVFHMIN: # %bb.0: -; ZVFHMIN-NEXT: fcvt.s.h fa5, fa0 -; ZVFHMIN-NEXT: vsetvli a1, zero, e32, mf2, ta, ma -; ZVFHMIN-NEXT: vfmv.v.f v9, fa5 -; ZVFHMIN-NEXT: vsetvli zero, zero, e16, mf4, ta, ma -; ZVFHMIN-NEXT: vfncvt.f.f.w v10, v9 -; ZVFHMIN-NEXT: vfwcvt.f.f.v v9, v8 -; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v10 +; ZVFHMIN-NEXT: fmv.x.h a1, fa0 +; ZVFHMIN-NEXT: vsetvli a2, zero, e16, mf4, ta, ma +; ZVFHMIN-NEXT: vmv.v.x v9, a1 +; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v8 +; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v9 ; ZVFHMIN-NEXT: vsetvli zero, a0, e32, mf2, ta, ma -; ZVFHMIN-NEXT: vmfne.vv v0, v8, v9, v0.t +; ZVFHMIN-NEXT: vmfne.vv v0, v8, v10, v0.t ; ZVFHMIN-NEXT: ret %elt.head = insertelement poison, half %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer @@ -1015,18 +963,16 @@ define @fcmp_uno_vf_nxv1f16( %va, half %b, ; ; ZVFHMIN-LABEL: fcmp_uno_vf_nxv1f16: ; ZVFHMIN: # %bb.0: -; ZVFHMIN-NEXT: fcvt.s.h fa5, fa0 -; ZVFHMIN-NEXT: vsetvli a1, zero, e32, mf2, ta, ma -; ZVFHMIN-NEXT: vfmv.v.f v9, fa5 -; ZVFHMIN-NEXT: vsetvli zero, zero, e16, mf4, ta, ma -; ZVFHMIN-NEXT: vfncvt.f.f.w v10, v9 -; ZVFHMIN-NEXT: vfwcvt.f.f.v v9, v8 +; ZVFHMIN-NEXT: fmv.x.h a1, fa0 +; ZVFHMIN-NEXT: vsetvli a2, zero, e16, mf4, ta, ma +; ZVFHMIN-NEXT: vmv.v.x v9, a1 +; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v8 ; ZVFHMIN-NEXT: vsetvli zero, a0, e32, mf2, ta, ma -; ZVFHMIN-NEXT: vmfne.vv v8, v9, v9, v0.t +; ZVFHMIN-NEXT: vmfne.vv v8, v10, v10, v0.t ; ZVFHMIN-NEXT: vsetvli a1, zero, e16, mf4, ta, ma -; ZVFHMIN-NEXT: vfwcvt.f.f.v v9, v10 +; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v9 ; ZVFHMIN-NEXT: vsetvli zero, a0, e32, mf2, ta, ma -; ZVFHMIN-NEXT: vmfne.vv v9, v9, v9, v0.t +; ZVFHMIN-NEXT: vmfne.vv v9, v10, v10, v0.t ; ZVFHMIN-NEXT: vmor.mm v0, v8, v9 ; ZVFHMIN-NEXT: ret %elt.head = insertelement poison, half %b, i32 0 @@ -1048,18 +994,16 @@ define @fcmp_uno_vf_swap_nxv1f16( %va, half ; ; ZVFHMIN-LABEL: fcmp_uno_vf_swap_nxv1f16: ; ZVFHMIN: # %bb.0: -; ZVFHMIN-NEXT: fcvt.s.h fa5, fa0 -; ZVFHMIN-NEXT: vsetvli a1, zero, e32, mf2, ta, ma -; ZVFHMIN-NEXT: vfmv.v.f v9, fa5 -; ZVFHMIN-NEXT: vsetvli zero, zero, e16, mf4, ta, ma -; ZVFHMIN-NEXT: vfncvt.f.f.w v10, v9 -; ZVFHMIN-NEXT: vfwcvt.f.f.v v9, v8 +; ZVFHMIN-NEXT: fmv.x.h a1, fa0 +; ZVFHMIN-NEXT: vsetvli a2, zero, e16, mf4, ta, ma +; ZVFHMIN-NEXT: vmv.v.x v9, a1 +; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v8 ; ZVFHMIN-NEXT: vsetvli zero, a0, e32, mf2, ta, ma -; ZVFHMIN-NEXT: vmfne.vv v8, v9, v9, v0.t +; ZVFHMIN-NEXT: vmfne.vv v8, v10, v10, v0.t ; ZVFHMIN-NEXT: vsetvli a1, zero, e16, mf4, ta, ma -; ZVFHMIN-NEXT: vfwcvt.f.f.v v9, v10 +; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v9 ; ZVFHMIN-NEXT: vsetvli zero, a0, e32, mf2, ta, ma -; ZVFHMIN-NEXT: vmfne.vv v9, v9, v9, v0.t +; ZVFHMIN-NEXT: vmfne.vv v9, v10, v10, v0.t ; ZVFHMIN-NEXT: vmor.mm v0, v9, v8 ; ZVFHMIN-NEXT: ret %elt.head = insertelement poison, half %b, i32 0 @@ -1123,11 +1067,9 @@ define @fcmp_oeq_vf_nxv8f16( %va, half %b, ; ; ZVFHMIN-LABEL: fcmp_oeq_vf_nxv8f16: ; ZVFHMIN: # %bb.0: -; ZVFHMIN-NEXT: fcvt.s.h fa5, fa0 -; ZVFHMIN-NEXT: vsetvli a1, zero, e32, m4, ta, ma -; ZVFHMIN-NEXT: vfmv.v.f v12, fa5 -; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m2, ta, ma -; ZVFHMIN-NEXT: vfncvt.f.f.w v10, v12 +; ZVFHMIN-NEXT: fmv.x.h a1, fa0 +; ZVFHMIN-NEXT: vsetvli a2, zero, e16, m2, ta, ma +; ZVFHMIN-NEXT: vmv.v.x v10, a1 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v8 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v10 ; ZVFHMIN-NEXT: vsetvli zero, a0, e32, m4, ta, ma @@ -1150,11 +1092,9 @@ define @fcmp_oeq_vf_swap_nxv8f16( %va, half ; ; ZVFHMIN-LABEL: fcmp_oeq_vf_swap_nxv8f16: ; ZVFHMIN: # %bb.0: -; ZVFHMIN-NEXT: fcvt.s.h fa5, fa0 -; ZVFHMIN-NEXT: vsetvli a1, zero, e32, m4, ta, ma -; ZVFHMIN-NEXT: vfmv.v.f v12, fa5 -; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m2, ta, ma -; ZVFHMIN-NEXT: vfncvt.f.f.w v10, v12 +; ZVFHMIN-NEXT: fmv.x.h a1, fa0 +; ZVFHMIN-NEXT: vsetvli a2, zero, e16, m2, ta, ma +; ZVFHMIN-NEXT: vmv.v.x v10, a1 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v8 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v10 ; ZVFHMIN-NEXT: vsetvli zero, a0, e32, m4, ta, ma @@ -1198,11 +1138,9 @@ define @fcmp_ogt_vf_nxv8f16( %va, half %b, ; ; ZVFHMIN-LABEL: fcmp_ogt_vf_nxv8f16: ; ZVFHMIN: # %bb.0: -; ZVFHMIN-NEXT: fcvt.s.h fa5, fa0 -; ZVFHMIN-NEXT: vsetvli a1, zero, e32, m4, ta, ma -; ZVFHMIN-NEXT: vfmv.v.f v12, fa5 -; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m2, ta, ma -; ZVFHMIN-NEXT: vfncvt.f.f.w v10, v12 +; ZVFHMIN-NEXT: fmv.x.h a1, fa0 +; ZVFHMIN-NEXT: vsetvli a2, zero, e16, m2, ta, ma +; ZVFHMIN-NEXT: vmv.v.x v10, a1 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v8 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v10 ; ZVFHMIN-NEXT: vsetvli zero, a0, e32, m4, ta, ma @@ -1225,11 +1163,9 @@ define @fcmp_ogt_vf_swap_nxv8f16( %va, half ; ; ZVFHMIN-LABEL: fcmp_ogt_vf_swap_nxv8f16: ; ZVFHMIN: # %bb.0: -; ZVFHMIN-NEXT: fcvt.s.h fa5, fa0 -; ZVFHMIN-NEXT: vsetvli a1, zero, e32, m4, ta, ma -; ZVFHMIN-NEXT: vfmv.v.f v12, fa5 -; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m2, ta, ma -; ZVFHMIN-NEXT: vfncvt.f.f.w v10, v12 +; ZVFHMIN-NEXT: fmv.x.h a1, fa0 +; ZVFHMIN-NEXT: vsetvli a2, zero, e16, m2, ta, ma +; ZVFHMIN-NEXT: vmv.v.x v10, a1 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v8 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v10 ; ZVFHMIN-NEXT: vsetvli zero, a0, e32, m4, ta, ma @@ -1273,11 +1209,9 @@ define @fcmp_oge_vf_nxv8f16( %va, half %b, ; ; ZVFHMIN-LABEL: fcmp_oge_vf_nxv8f16: ; ZVFHMIN: # %bb.0: -; ZVFHMIN-NEXT: fcvt.s.h fa5, fa0 -; ZVFHMIN-NEXT: vsetvli a1, zero, e32, m4, ta, ma -; ZVFHMIN-NEXT: vfmv.v.f v12, fa5 -; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m2, ta, ma -; ZVFHMIN-NEXT: vfncvt.f.f.w v10, v12 +; ZVFHMIN-NEXT: fmv.x.h a1, fa0 +; ZVFHMIN-NEXT: vsetvli a2, zero, e16, m2, ta, ma +; ZVFHMIN-NEXT: vmv.v.x v10, a1 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v8 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v10 ; ZVFHMIN-NEXT: vsetvli zero, a0, e32, m4, ta, ma @@ -1300,11 +1234,9 @@ define @fcmp_oge_vf_swap_nxv8f16( %va, half ; ; ZVFHMIN-LABEL: fcmp_oge_vf_swap_nxv8f16: ; ZVFHMIN: # %bb.0: -; ZVFHMIN-NEXT: fcvt.s.h fa5, fa0 -; ZVFHMIN-NEXT: vsetvli a1, zero, e32, m4, ta, ma -; ZVFHMIN-NEXT: vfmv.v.f v12, fa5 -; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m2, ta, ma -; ZVFHMIN-NEXT: vfncvt.f.f.w v10, v12 +; ZVFHMIN-NEXT: fmv.x.h a1, fa0 +; ZVFHMIN-NEXT: vsetvli a2, zero, e16, m2, ta, ma +; ZVFHMIN-NEXT: vmv.v.x v10, a1 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v8 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v10 ; ZVFHMIN-NEXT: vsetvli zero, a0, e32, m4, ta, ma @@ -1348,11 +1280,9 @@ define @fcmp_olt_vf_nxv8f16( %va, half %b, ; ; ZVFHMIN-LABEL: fcmp_olt_vf_nxv8f16: ; ZVFHMIN: # %bb.0: -; ZVFHMIN-NEXT: fcvt.s.h fa5, fa0 -; ZVFHMIN-NEXT: vsetvli a1, zero, e32, m4, ta, ma -; ZVFHMIN-NEXT: vfmv.v.f v12, fa5 -; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m2, ta, ma -; ZVFHMIN-NEXT: vfncvt.f.f.w v10, v12 +; ZVFHMIN-NEXT: fmv.x.h a1, fa0 +; ZVFHMIN-NEXT: vsetvli a2, zero, e16, m2, ta, ma +; ZVFHMIN-NEXT: vmv.v.x v10, a1 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v8 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v10 ; ZVFHMIN-NEXT: vsetvli zero, a0, e32, m4, ta, ma @@ -1375,11 +1305,9 @@ define @fcmp_olt_vf_swap_nxv8f16( %va, half ; ; ZVFHMIN-LABEL: fcmp_olt_vf_swap_nxv8f16: ; ZVFHMIN: # %bb.0: -; ZVFHMIN-NEXT: fcvt.s.h fa5, fa0 -; ZVFHMIN-NEXT: vsetvli a1, zero, e32, m4, ta, ma -; ZVFHMIN-NEXT: vfmv.v.f v12, fa5 -; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m2, ta, ma -; ZVFHMIN-NEXT: vfncvt.f.f.w v10, v12 +; ZVFHMIN-NEXT: fmv.x.h a1, fa0 +; ZVFHMIN-NEXT: vsetvli a2, zero, e16, m2, ta, ma +; ZVFHMIN-NEXT: vmv.v.x v10, a1 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v8 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v10 ; ZVFHMIN-NEXT: vsetvli zero, a0, e32, m4, ta, ma @@ -1423,11 +1351,9 @@ define @fcmp_ole_vf_nxv8f16( %va, half %b, ; ; ZVFHMIN-LABEL: fcmp_ole_vf_nxv8f16: ; ZVFHMIN: # %bb.0: -; ZVFHMIN-NEXT: fcvt.s.h fa5, fa0 -; ZVFHMIN-NEXT: vsetvli a1, zero, e32, m4, ta, ma -; ZVFHMIN-NEXT: vfmv.v.f v12, fa5 -; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m2, ta, ma -; ZVFHMIN-NEXT: vfncvt.f.f.w v10, v12 +; ZVFHMIN-NEXT: fmv.x.h a1, fa0 +; ZVFHMIN-NEXT: vsetvli a2, zero, e16, m2, ta, ma +; ZVFHMIN-NEXT: vmv.v.x v10, a1 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v8 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v10 ; ZVFHMIN-NEXT: vsetvli zero, a0, e32, m4, ta, ma @@ -1450,11 +1376,9 @@ define @fcmp_ole_vf_swap_nxv8f16( %va, half ; ; ZVFHMIN-LABEL: fcmp_ole_vf_swap_nxv8f16: ; ZVFHMIN: # %bb.0: -; ZVFHMIN-NEXT: fcvt.s.h fa5, fa0 -; ZVFHMIN-NEXT: vsetvli a1, zero, e32, m4, ta, ma -; ZVFHMIN-NEXT: vfmv.v.f v12, fa5 -; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m2, ta, ma -; ZVFHMIN-NEXT: vfncvt.f.f.w v10, v12 +; ZVFHMIN-NEXT: fmv.x.h a1, fa0 +; ZVFHMIN-NEXT: vsetvli a2, zero, e16, m2, ta, ma +; ZVFHMIN-NEXT: vmv.v.x v10, a1 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v8 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v10 ; ZVFHMIN-NEXT: vsetvli zero, a0, e32, m4, ta, ma @@ -1501,11 +1425,9 @@ define @fcmp_one_vf_nxv8f16( %va, half %b, ; ; ZVFHMIN-LABEL: fcmp_one_vf_nxv8f16: ; ZVFHMIN: # %bb.0: -; ZVFHMIN-NEXT: fcvt.s.h fa5, fa0 -; ZVFHMIN-NEXT: vsetvli a1, zero, e32, m4, ta, ma -; ZVFHMIN-NEXT: vfmv.v.f v12, fa5 -; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m2, ta, ma -; ZVFHMIN-NEXT: vfncvt.f.f.w v10, v12 +; ZVFHMIN-NEXT: fmv.x.h a1, fa0 +; ZVFHMIN-NEXT: vsetvli a2, zero, e16, m2, ta, ma +; ZVFHMIN-NEXT: vmv.v.x v10, a1 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v8 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v10 ; ZVFHMIN-NEXT: vsetvli zero, a0, e32, m4, ta, ma @@ -1530,11 +1452,9 @@ define @fcmp_one_vf_swap_nxv8f16( %va, half ; ; ZVFHMIN-LABEL: fcmp_one_vf_swap_nxv8f16: ; ZVFHMIN: # %bb.0: -; ZVFHMIN-NEXT: fcvt.s.h fa5, fa0 -; ZVFHMIN-NEXT: vsetvli a1, zero, e32, m4, ta, ma -; ZVFHMIN-NEXT: vfmv.v.f v12, fa5 -; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m2, ta, ma -; ZVFHMIN-NEXT: vfncvt.f.f.w v10, v12 +; ZVFHMIN-NEXT: fmv.x.h a1, fa0 +; ZVFHMIN-NEXT: vsetvli a2, zero, e16, m2, ta, ma +; ZVFHMIN-NEXT: vmv.v.x v10, a1 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v8 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v10 ; ZVFHMIN-NEXT: vsetvli zero, a0, e32, m4, ta, ma @@ -1586,11 +1506,9 @@ define @fcmp_ord_vf_nxv8f16( %va, half %b, ; ; ZVFHMIN-LABEL: fcmp_ord_vf_nxv8f16: ; ZVFHMIN: # %bb.0: -; ZVFHMIN-NEXT: fcvt.s.h fa5, fa0 -; ZVFHMIN-NEXT: vsetvli a1, zero, e32, m4, ta, ma -; ZVFHMIN-NEXT: vfmv.v.f v12, fa5 -; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m2, ta, ma -; ZVFHMIN-NEXT: vfncvt.f.f.w v10, v12 +; ZVFHMIN-NEXT: fmv.x.h a1, fa0 +; ZVFHMIN-NEXT: vsetvli a2, zero, e16, m2, ta, ma +; ZVFHMIN-NEXT: vmv.v.x v10, a1 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v8 ; ZVFHMIN-NEXT: vsetvli zero, a0, e32, m4, ta, ma ; ZVFHMIN-NEXT: vmfeq.vv v8, v12, v12, v0.t @@ -1619,11 +1537,9 @@ define @fcmp_ord_vf_swap_nxv8f16( %va, half ; ; ZVFHMIN-LABEL: fcmp_ord_vf_swap_nxv8f16: ; ZVFHMIN: # %bb.0: -; ZVFHMIN-NEXT: fcvt.s.h fa5, fa0 -; ZVFHMIN-NEXT: vsetvli a1, zero, e32, m4, ta, ma -; ZVFHMIN-NEXT: vfmv.v.f v12, fa5 -; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m2, ta, ma -; ZVFHMIN-NEXT: vfncvt.f.f.w v10, v12 +; ZVFHMIN-NEXT: fmv.x.h a1, fa0 +; ZVFHMIN-NEXT: vsetvli a2, zero, e16, m2, ta, ma +; ZVFHMIN-NEXT: vmv.v.x v10, a1 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v8 ; ZVFHMIN-NEXT: vsetvli zero, a0, e32, m4, ta, ma ; ZVFHMIN-NEXT: vmfeq.vv v8, v12, v12, v0.t @@ -1673,11 +1589,9 @@ define @fcmp_ueq_vf_nxv8f16( %va, half %b, ; ; ZVFHMIN-LABEL: fcmp_ueq_vf_nxv8f16: ; ZVFHMIN: # %bb.0: -; ZVFHMIN-NEXT: fcvt.s.h fa5, fa0 -; ZVFHMIN-NEXT: vsetvli a1, zero, e32, m4, ta, ma -; ZVFHMIN-NEXT: vfmv.v.f v12, fa5 -; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m2, ta, ma -; ZVFHMIN-NEXT: vfncvt.f.f.w v10, v12 +; ZVFHMIN-NEXT: fmv.x.h a1, fa0 +; ZVFHMIN-NEXT: vsetvli a2, zero, e16, m2, ta, ma +; ZVFHMIN-NEXT: vmv.v.x v10, a1 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v8 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v10 ; ZVFHMIN-NEXT: vsetvli zero, a0, e32, m4, ta, ma @@ -1702,11 +1616,9 @@ define @fcmp_ueq_vf_swap_nxv8f16( %va, half ; ; ZVFHMIN-LABEL: fcmp_ueq_vf_swap_nxv8f16: ; ZVFHMIN: # %bb.0: -; ZVFHMIN-NEXT: fcvt.s.h fa5, fa0 -; ZVFHMIN-NEXT: vsetvli a1, zero, e32, m4, ta, ma -; ZVFHMIN-NEXT: vfmv.v.f v12, fa5 -; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m2, ta, ma -; ZVFHMIN-NEXT: vfncvt.f.f.w v10, v12 +; ZVFHMIN-NEXT: fmv.x.h a1, fa0 +; ZVFHMIN-NEXT: vsetvli a2, zero, e16, m2, ta, ma +; ZVFHMIN-NEXT: vmv.v.x v10, a1 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v8 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v10 ; ZVFHMIN-NEXT: vsetvli zero, a0, e32, m4, ta, ma @@ -1751,11 +1663,9 @@ define @fcmp_ugt_vf_nxv8f16( %va, half %b, ; ; ZVFHMIN-LABEL: fcmp_ugt_vf_nxv8f16: ; ZVFHMIN: # %bb.0: -; ZVFHMIN-NEXT: fcvt.s.h fa5, fa0 -; ZVFHMIN-NEXT: vsetvli a1, zero, e32, m4, ta, ma -; ZVFHMIN-NEXT: vfmv.v.f v12, fa5 -; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m2, ta, ma -; ZVFHMIN-NEXT: vfncvt.f.f.w v10, v12 +; ZVFHMIN-NEXT: fmv.x.h a1, fa0 +; ZVFHMIN-NEXT: vsetvli a2, zero, e16, m2, ta, ma +; ZVFHMIN-NEXT: vmv.v.x v10, a1 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v8 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v10 ; ZVFHMIN-NEXT: vsetvli zero, a0, e32, m4, ta, ma @@ -1778,11 +1688,9 @@ define @fcmp_ugt_vf_swap_nxv8f16( %va, half ; ; ZVFHMIN-LABEL: fcmp_ugt_vf_swap_nxv8f16: ; ZVFHMIN: # %bb.0: -; ZVFHMIN-NEXT: fcvt.s.h fa5, fa0 -; ZVFHMIN-NEXT: vsetvli a1, zero, e32, m4, ta, ma -; ZVFHMIN-NEXT: vfmv.v.f v12, fa5 -; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m2, ta, ma -; ZVFHMIN-NEXT: vfncvt.f.f.w v10, v12 +; ZVFHMIN-NEXT: fmv.x.h a1, fa0 +; ZVFHMIN-NEXT: vsetvli a2, zero, e16, m2, ta, ma +; ZVFHMIN-NEXT: vmv.v.x v10, a1 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v8 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v10 ; ZVFHMIN-NEXT: vsetvli zero, a0, e32, m4, ta, ma @@ -1826,11 +1734,9 @@ define @fcmp_uge_vf_nxv8f16( %va, half %b, ; ; ZVFHMIN-LABEL: fcmp_uge_vf_nxv8f16: ; ZVFHMIN: # %bb.0: -; ZVFHMIN-NEXT: fcvt.s.h fa5, fa0 -; ZVFHMIN-NEXT: vsetvli a1, zero, e32, m4, ta, ma -; ZVFHMIN-NEXT: vfmv.v.f v12, fa5 -; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m2, ta, ma -; ZVFHMIN-NEXT: vfncvt.f.f.w v10, v12 +; ZVFHMIN-NEXT: fmv.x.h a1, fa0 +; ZVFHMIN-NEXT: vsetvli a2, zero, e16, m2, ta, ma +; ZVFHMIN-NEXT: vmv.v.x v10, a1 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v8 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v10 ; ZVFHMIN-NEXT: vsetvli zero, a0, e32, m4, ta, ma @@ -1853,11 +1759,9 @@ define @fcmp_uge_vf_swap_nxv8f16( %va, half ; ; ZVFHMIN-LABEL: fcmp_uge_vf_swap_nxv8f16: ; ZVFHMIN: # %bb.0: -; ZVFHMIN-NEXT: fcvt.s.h fa5, fa0 -; ZVFHMIN-NEXT: vsetvli a1, zero, e32, m4, ta, ma -; ZVFHMIN-NEXT: vfmv.v.f v12, fa5 -; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m2, ta, ma -; ZVFHMIN-NEXT: vfncvt.f.f.w v10, v12 +; ZVFHMIN-NEXT: fmv.x.h a1, fa0 +; ZVFHMIN-NEXT: vsetvli a2, zero, e16, m2, ta, ma +; ZVFHMIN-NEXT: vmv.v.x v10, a1 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v8 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v10 ; ZVFHMIN-NEXT: vsetvli zero, a0, e32, m4, ta, ma @@ -1901,11 +1805,9 @@ define @fcmp_ult_vf_nxv8f16( %va, half %b, ; ; ZVFHMIN-LABEL: fcmp_ult_vf_nxv8f16: ; ZVFHMIN: # %bb.0: -; ZVFHMIN-NEXT: fcvt.s.h fa5, fa0 -; ZVFHMIN-NEXT: vsetvli a1, zero, e32, m4, ta, ma -; ZVFHMIN-NEXT: vfmv.v.f v12, fa5 -; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m2, ta, ma -; ZVFHMIN-NEXT: vfncvt.f.f.w v10, v12 +; ZVFHMIN-NEXT: fmv.x.h a1, fa0 +; ZVFHMIN-NEXT: vsetvli a2, zero, e16, m2, ta, ma +; ZVFHMIN-NEXT: vmv.v.x v10, a1 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v8 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v10 ; ZVFHMIN-NEXT: vsetvli zero, a0, e32, m4, ta, ma @@ -1928,11 +1830,9 @@ define @fcmp_ult_vf_swap_nxv8f16( %va, half ; ; ZVFHMIN-LABEL: fcmp_ult_vf_swap_nxv8f16: ; ZVFHMIN: # %bb.0: -; ZVFHMIN-NEXT: fcvt.s.h fa5, fa0 -; ZVFHMIN-NEXT: vsetvli a1, zero, e32, m4, ta, ma -; ZVFHMIN-NEXT: vfmv.v.f v12, fa5 -; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m2, ta, ma -; ZVFHMIN-NEXT: vfncvt.f.f.w v10, v12 +; ZVFHMIN-NEXT: fmv.x.h a1, fa0 +; ZVFHMIN-NEXT: vsetvli a2, zero, e16, m2, ta, ma +; ZVFHMIN-NEXT: vmv.v.x v10, a1 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v8 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v10 ; ZVFHMIN-NEXT: vsetvli zero, a0, e32, m4, ta, ma @@ -1976,11 +1876,9 @@ define @fcmp_ule_vf_nxv8f16( %va, half %b, ; ; ZVFHMIN-LABEL: fcmp_ule_vf_nxv8f16: ; ZVFHMIN: # %bb.0: -; ZVFHMIN-NEXT: fcvt.s.h fa5, fa0 -; ZVFHMIN-NEXT: vsetvli a1, zero, e32, m4, ta, ma -; ZVFHMIN-NEXT: vfmv.v.f v12, fa5 -; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m2, ta, ma -; ZVFHMIN-NEXT: vfncvt.f.f.w v10, v12 +; ZVFHMIN-NEXT: fmv.x.h a1, fa0 +; ZVFHMIN-NEXT: vsetvli a2, zero, e16, m2, ta, ma +; ZVFHMIN-NEXT: vmv.v.x v10, a1 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v8 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v10 ; ZVFHMIN-NEXT: vsetvli zero, a0, e32, m4, ta, ma @@ -2003,11 +1901,9 @@ define @fcmp_ule_vf_swap_nxv8f16( %va, half ; ; ZVFHMIN-LABEL: fcmp_ule_vf_swap_nxv8f16: ; ZVFHMIN: # %bb.0: -; ZVFHMIN-NEXT: fcvt.s.h fa5, fa0 -; ZVFHMIN-NEXT: vsetvli a1, zero, e32, m4, ta, ma -; ZVFHMIN-NEXT: vfmv.v.f v12, fa5 -; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m2, ta, ma -; ZVFHMIN-NEXT: vfncvt.f.f.w v10, v12 +; ZVFHMIN-NEXT: fmv.x.h a1, fa0 +; ZVFHMIN-NEXT: vsetvli a2, zero, e16, m2, ta, ma +; ZVFHMIN-NEXT: vmv.v.x v10, a1 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v8 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v10 ; ZVFHMIN-NEXT: vsetvli zero, a0, e32, m4, ta, ma @@ -2051,11 +1947,9 @@ define @fcmp_une_vf_nxv8f16( %va, half %b, ; ; ZVFHMIN-LABEL: fcmp_une_vf_nxv8f16: ; ZVFHMIN: # %bb.0: -; ZVFHMIN-NEXT: fcvt.s.h fa5, fa0 -; ZVFHMIN-NEXT: vsetvli a1, zero, e32, m4, ta, ma -; ZVFHMIN-NEXT: vfmv.v.f v12, fa5 -; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m2, ta, ma -; ZVFHMIN-NEXT: vfncvt.f.f.w v10, v12 +; ZVFHMIN-NEXT: fmv.x.h a1, fa0 +; ZVFHMIN-NEXT: vsetvli a2, zero, e16, m2, ta, ma +; ZVFHMIN-NEXT: vmv.v.x v10, a1 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v8 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v10 ; ZVFHMIN-NEXT: vsetvli zero, a0, e32, m4, ta, ma @@ -2078,11 +1972,9 @@ define @fcmp_une_vf_swap_nxv8f16( %va, half ; ; ZVFHMIN-LABEL: fcmp_une_vf_swap_nxv8f16: ; ZVFHMIN: # %bb.0: -; ZVFHMIN-NEXT: fcvt.s.h fa5, fa0 -; ZVFHMIN-NEXT: vsetvli a1, zero, e32, m4, ta, ma -; ZVFHMIN-NEXT: vfmv.v.f v12, fa5 -; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m2, ta, ma -; ZVFHMIN-NEXT: vfncvt.f.f.w v10, v12 +; ZVFHMIN-NEXT: fmv.x.h a1, fa0 +; ZVFHMIN-NEXT: vsetvli a2, zero, e16, m2, ta, ma +; ZVFHMIN-NEXT: vmv.v.x v10, a1 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v8 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v10 ; ZVFHMIN-NEXT: vsetvli zero, a0, e32, m4, ta, ma @@ -2133,11 +2025,9 @@ define @fcmp_uno_vf_nxv8f16( %va, half %b, ; ; ZVFHMIN-LABEL: fcmp_uno_vf_nxv8f16: ; ZVFHMIN: # %bb.0: -; ZVFHMIN-NEXT: fcvt.s.h fa5, fa0 -; ZVFHMIN-NEXT: vsetvli a1, zero, e32, m4, ta, ma -; ZVFHMIN-NEXT: vfmv.v.f v12, fa5 -; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m2, ta, ma -; ZVFHMIN-NEXT: vfncvt.f.f.w v10, v12 +; ZVFHMIN-NEXT: fmv.x.h a1, fa0 +; ZVFHMIN-NEXT: vsetvli a2, zero, e16, m2, ta, ma +; ZVFHMIN-NEXT: vmv.v.x v10, a1 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v8 ; ZVFHMIN-NEXT: vsetvli zero, a0, e32, m4, ta, ma ; ZVFHMIN-NEXT: vmfne.vv v8, v12, v12, v0.t @@ -2166,11 +2056,9 @@ define @fcmp_uno_vf_swap_nxv8f16( %va, half ; ; ZVFHMIN-LABEL: fcmp_uno_vf_swap_nxv8f16: ; ZVFHMIN: # %bb.0: -; ZVFHMIN-NEXT: fcvt.s.h fa5, fa0 -; ZVFHMIN-NEXT: vsetvli a1, zero, e32, m4, ta, ma -; ZVFHMIN-NEXT: vfmv.v.f v12, fa5 -; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m2, ta, ma -; ZVFHMIN-NEXT: vfncvt.f.f.w v10, v12 +; ZVFHMIN-NEXT: fmv.x.h a1, fa0 +; ZVFHMIN-NEXT: vsetvli a2, zero, e16, m2, ta, ma +; ZVFHMIN-NEXT: vmv.v.x v10, a1 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v8 ; ZVFHMIN-NEXT: vsetvli zero, a0, e32, m4, ta, ma ; ZVFHMIN-NEXT: vmfne.vv v8, v12, v12, v0.t diff --git a/llvm/test/CodeGen/RISCV/rvv/setcc-fp.ll b/llvm/test/CodeGen/RISCV/rvv/setcc-fp.ll index aee255196ce2e8..c2c977bec60555 100644 --- a/llvm/test/CodeGen/RISCV/rvv/setcc-fp.ll +++ b/llvm/test/CodeGen/RISCV/rvv/setcc-fp.ll @@ -39,11 +39,9 @@ define @fcmp_oeq_vf_nxv8f16( %va, half %b) ; ; ZVFHMIN-LABEL: fcmp_oeq_vf_nxv8f16: ; ZVFHMIN: # %bb.0: -; ZVFHMIN-NEXT: fcvt.s.h fa5, fa0 -; ZVFHMIN-NEXT: vsetvli a0, zero, e32, m4, ta, ma -; ZVFHMIN-NEXT: vfmv.v.f v12, fa5 -; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m2, ta, ma -; ZVFHMIN-NEXT: vfncvt.f.f.w v10, v12 +; ZVFHMIN-NEXT: fmv.x.h a0, fa0 +; ZVFHMIN-NEXT: vsetvli a1, zero, e16, m2, ta, ma +; ZVFHMIN-NEXT: vmv.v.x v10, a0 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v8 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v10 ; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m4, ta, ma @@ -64,11 +62,9 @@ define @fcmp_oeq_fv_nxv8f16( %va, half %b) ; ; ZVFHMIN-LABEL: fcmp_oeq_fv_nxv8f16: ; ZVFHMIN: # %bb.0: -; ZVFHMIN-NEXT: fcvt.s.h fa5, fa0 -; ZVFHMIN-NEXT: vsetvli a0, zero, e32, m4, ta, ma -; ZVFHMIN-NEXT: vfmv.v.f v12, fa5 -; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m2, ta, ma -; ZVFHMIN-NEXT: vfncvt.f.f.w v10, v12 +; ZVFHMIN-NEXT: fmv.x.h a0, fa0 +; ZVFHMIN-NEXT: vsetvli a1, zero, e16, m2, ta, ma +; ZVFHMIN-NEXT: vmv.v.x v10, a0 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v8 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v10 ; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m4, ta, ma @@ -108,11 +104,9 @@ define @fcmp_oeq_vf_nxv8f16_nonans( %va, ha ; ; ZVFHMIN-LABEL: fcmp_oeq_vf_nxv8f16_nonans: ; ZVFHMIN: # %bb.0: -; ZVFHMIN-NEXT: fcvt.s.h fa5, fa0 -; ZVFHMIN-NEXT: vsetvli a0, zero, e32, m4, ta, ma -; ZVFHMIN-NEXT: vfmv.v.f v12, fa5 -; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m2, ta, ma -; ZVFHMIN-NEXT: vfncvt.f.f.w v10, v12 +; ZVFHMIN-NEXT: fmv.x.h a0, fa0 +; ZVFHMIN-NEXT: vsetvli a1, zero, e16, m2, ta, ma +; ZVFHMIN-NEXT: vmv.v.x v10, a0 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v8 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v10 ; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m4, ta, ma @@ -152,11 +146,9 @@ define @fcmp_ogt_vf_nxv8f16( %va, half %b) ; ; ZVFHMIN-LABEL: fcmp_ogt_vf_nxv8f16: ; ZVFHMIN: # %bb.0: -; ZVFHMIN-NEXT: fcvt.s.h fa5, fa0 -; ZVFHMIN-NEXT: vsetvli a0, zero, e32, m4, ta, ma -; ZVFHMIN-NEXT: vfmv.v.f v12, fa5 -; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m2, ta, ma -; ZVFHMIN-NEXT: vfncvt.f.f.w v10, v12 +; ZVFHMIN-NEXT: fmv.x.h a0, fa0 +; ZVFHMIN-NEXT: vsetvli a1, zero, e16, m2, ta, ma +; ZVFHMIN-NEXT: vmv.v.x v10, a0 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v8 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v10 ; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m4, ta, ma @@ -177,11 +169,9 @@ define @fcmp_ogt_fv_nxv8f16( %va, half %b) ; ; ZVFHMIN-LABEL: fcmp_ogt_fv_nxv8f16: ; ZVFHMIN: # %bb.0: -; ZVFHMIN-NEXT: fcvt.s.h fa5, fa0 -; ZVFHMIN-NEXT: vsetvli a0, zero, e32, m4, ta, ma -; ZVFHMIN-NEXT: vfmv.v.f v12, fa5 -; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m2, ta, ma -; ZVFHMIN-NEXT: vfncvt.f.f.w v10, v12 +; ZVFHMIN-NEXT: fmv.x.h a0, fa0 +; ZVFHMIN-NEXT: vsetvli a1, zero, e16, m2, ta, ma +; ZVFHMIN-NEXT: vmv.v.x v10, a0 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v8 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v10 ; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m4, ta, ma @@ -221,11 +211,9 @@ define @fcmp_ogt_vf_nxv8f16_nonans( %va, ha ; ; ZVFHMIN-LABEL: fcmp_ogt_vf_nxv8f16_nonans: ; ZVFHMIN: # %bb.0: -; ZVFHMIN-NEXT: fcvt.s.h fa5, fa0 -; ZVFHMIN-NEXT: vsetvli a0, zero, e32, m4, ta, ma -; ZVFHMIN-NEXT: vfmv.v.f v12, fa5 -; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m2, ta, ma -; ZVFHMIN-NEXT: vfncvt.f.f.w v10, v12 +; ZVFHMIN-NEXT: fmv.x.h a0, fa0 +; ZVFHMIN-NEXT: vsetvli a1, zero, e16, m2, ta, ma +; ZVFHMIN-NEXT: vmv.v.x v10, a0 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v8 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v10 ; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m4, ta, ma @@ -265,11 +253,9 @@ define @fcmp_oge_vf_nxv8f16( %va, half %b) ; ; ZVFHMIN-LABEL: fcmp_oge_vf_nxv8f16: ; ZVFHMIN: # %bb.0: -; ZVFHMIN-NEXT: fcvt.s.h fa5, fa0 -; ZVFHMIN-NEXT: vsetvli a0, zero, e32, m4, ta, ma -; ZVFHMIN-NEXT: vfmv.v.f v12, fa5 -; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m2, ta, ma -; ZVFHMIN-NEXT: vfncvt.f.f.w v10, v12 +; ZVFHMIN-NEXT: fmv.x.h a0, fa0 +; ZVFHMIN-NEXT: vsetvli a1, zero, e16, m2, ta, ma +; ZVFHMIN-NEXT: vmv.v.x v10, a0 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v8 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v10 ; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m4, ta, ma @@ -290,11 +276,9 @@ define @fcmp_oge_fv_nxv8f16( %va, half %b) ; ; ZVFHMIN-LABEL: fcmp_oge_fv_nxv8f16: ; ZVFHMIN: # %bb.0: -; ZVFHMIN-NEXT: fcvt.s.h fa5, fa0 -; ZVFHMIN-NEXT: vsetvli a0, zero, e32, m4, ta, ma -; ZVFHMIN-NEXT: vfmv.v.f v12, fa5 -; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m2, ta, ma -; ZVFHMIN-NEXT: vfncvt.f.f.w v10, v12 +; ZVFHMIN-NEXT: fmv.x.h a0, fa0 +; ZVFHMIN-NEXT: vsetvli a1, zero, e16, m2, ta, ma +; ZVFHMIN-NEXT: vmv.v.x v10, a0 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v8 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v10 ; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m4, ta, ma @@ -334,11 +318,9 @@ define @fcmp_oge_vf_nxv8f16_nonans( %va, ha ; ; ZVFHMIN-LABEL: fcmp_oge_vf_nxv8f16_nonans: ; ZVFHMIN: # %bb.0: -; ZVFHMIN-NEXT: fcvt.s.h fa5, fa0 -; ZVFHMIN-NEXT: vsetvli a0, zero, e32, m4, ta, ma -; ZVFHMIN-NEXT: vfmv.v.f v12, fa5 -; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m2, ta, ma -; ZVFHMIN-NEXT: vfncvt.f.f.w v10, v12 +; ZVFHMIN-NEXT: fmv.x.h a0, fa0 +; ZVFHMIN-NEXT: vsetvli a1, zero, e16, m2, ta, ma +; ZVFHMIN-NEXT: vmv.v.x v10, a0 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v8 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v10 ; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m4, ta, ma @@ -378,11 +360,9 @@ define @fcmp_olt_vf_nxv8f16( %va, half %b) ; ; ZVFHMIN-LABEL: fcmp_olt_vf_nxv8f16: ; ZVFHMIN: # %bb.0: -; ZVFHMIN-NEXT: fcvt.s.h fa5, fa0 -; ZVFHMIN-NEXT: vsetvli a0, zero, e32, m4, ta, ma -; ZVFHMIN-NEXT: vfmv.v.f v12, fa5 -; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m2, ta, ma -; ZVFHMIN-NEXT: vfncvt.f.f.w v10, v12 +; ZVFHMIN-NEXT: fmv.x.h a0, fa0 +; ZVFHMIN-NEXT: vsetvli a1, zero, e16, m2, ta, ma +; ZVFHMIN-NEXT: vmv.v.x v10, a0 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v8 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v10 ; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m4, ta, ma @@ -403,11 +383,9 @@ define @fcmp_olt_fv_nxv8f16( %va, half %b) ; ; ZVFHMIN-LABEL: fcmp_olt_fv_nxv8f16: ; ZVFHMIN: # %bb.0: -; ZVFHMIN-NEXT: fcvt.s.h fa5, fa0 -; ZVFHMIN-NEXT: vsetvli a0, zero, e32, m4, ta, ma -; ZVFHMIN-NEXT: vfmv.v.f v12, fa5 -; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m2, ta, ma -; ZVFHMIN-NEXT: vfncvt.f.f.w v10, v12 +; ZVFHMIN-NEXT: fmv.x.h a0, fa0 +; ZVFHMIN-NEXT: vsetvli a1, zero, e16, m2, ta, ma +; ZVFHMIN-NEXT: vmv.v.x v10, a0 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v8 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v10 ; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m4, ta, ma @@ -447,11 +425,9 @@ define @fcmp_olt_vf_nxv8f16_nonans( %va, ha ; ; ZVFHMIN-LABEL: fcmp_olt_vf_nxv8f16_nonans: ; ZVFHMIN: # %bb.0: -; ZVFHMIN-NEXT: fcvt.s.h fa5, fa0 -; ZVFHMIN-NEXT: vsetvli a0, zero, e32, m4, ta, ma -; ZVFHMIN-NEXT: vfmv.v.f v12, fa5 -; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m2, ta, ma -; ZVFHMIN-NEXT: vfncvt.f.f.w v10, v12 +; ZVFHMIN-NEXT: fmv.x.h a0, fa0 +; ZVFHMIN-NEXT: vsetvli a1, zero, e16, m2, ta, ma +; ZVFHMIN-NEXT: vmv.v.x v10, a0 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v8 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v10 ; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m4, ta, ma @@ -491,11 +467,9 @@ define @fcmp_ole_vf_nxv8f16( %va, half %b) ; ; ZVFHMIN-LABEL: fcmp_ole_vf_nxv8f16: ; ZVFHMIN: # %bb.0: -; ZVFHMIN-NEXT: fcvt.s.h fa5, fa0 -; ZVFHMIN-NEXT: vsetvli a0, zero, e32, m4, ta, ma -; ZVFHMIN-NEXT: vfmv.v.f v12, fa5 -; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m2, ta, ma -; ZVFHMIN-NEXT: vfncvt.f.f.w v10, v12 +; ZVFHMIN-NEXT: fmv.x.h a0, fa0 +; ZVFHMIN-NEXT: vsetvli a1, zero, e16, m2, ta, ma +; ZVFHMIN-NEXT: vmv.v.x v10, a0 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v8 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v10 ; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m4, ta, ma @@ -516,11 +490,9 @@ define @fcmp_ole_fv_nxv8f16( %va, half %b) ; ; ZVFHMIN-LABEL: fcmp_ole_fv_nxv8f16: ; ZVFHMIN: # %bb.0: -; ZVFHMIN-NEXT: fcvt.s.h fa5, fa0 -; ZVFHMIN-NEXT: vsetvli a0, zero, e32, m4, ta, ma -; ZVFHMIN-NEXT: vfmv.v.f v12, fa5 -; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m2, ta, ma -; ZVFHMIN-NEXT: vfncvt.f.f.w v10, v12 +; ZVFHMIN-NEXT: fmv.x.h a0, fa0 +; ZVFHMIN-NEXT: vsetvli a1, zero, e16, m2, ta, ma +; ZVFHMIN-NEXT: vmv.v.x v10, a0 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v8 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v10 ; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m4, ta, ma @@ -560,11 +532,9 @@ define @fcmp_ole_vf_nxv8f16_nonans( %va, ha ; ; ZVFHMIN-LABEL: fcmp_ole_vf_nxv8f16_nonans: ; ZVFHMIN: # %bb.0: -; ZVFHMIN-NEXT: fcvt.s.h fa5, fa0 -; ZVFHMIN-NEXT: vsetvli a0, zero, e32, m4, ta, ma -; ZVFHMIN-NEXT: vfmv.v.f v12, fa5 -; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m2, ta, ma -; ZVFHMIN-NEXT: vfncvt.f.f.w v10, v12 +; ZVFHMIN-NEXT: fmv.x.h a0, fa0 +; ZVFHMIN-NEXT: vsetvli a1, zero, e16, m2, ta, ma +; ZVFHMIN-NEXT: vmv.v.x v10, a0 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v8 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v10 ; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m4, ta, ma @@ -610,11 +580,9 @@ define @fcmp_one_vf_nxv8f16( %va, half %b) ; ; ZVFHMIN-LABEL: fcmp_one_vf_nxv8f16: ; ZVFHMIN: # %bb.0: -; ZVFHMIN-NEXT: fcvt.s.h fa5, fa0 -; ZVFHMIN-NEXT: vsetvli a0, zero, e32, m4, ta, ma -; ZVFHMIN-NEXT: vfmv.v.f v12, fa5 -; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m2, ta, ma -; ZVFHMIN-NEXT: vfncvt.f.f.w v10, v12 +; ZVFHMIN-NEXT: fmv.x.h a0, fa0 +; ZVFHMIN-NEXT: vsetvli a1, zero, e16, m2, ta, ma +; ZVFHMIN-NEXT: vmv.v.x v10, a0 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v8 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v10 ; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m4, ta, ma @@ -639,11 +607,9 @@ define @fcmp_one_fv_nxv8f16( %va, half %b) ; ; ZVFHMIN-LABEL: fcmp_one_fv_nxv8f16: ; ZVFHMIN: # %bb.0: -; ZVFHMIN-NEXT: fcvt.s.h fa5, fa0 -; ZVFHMIN-NEXT: vsetvli a0, zero, e32, m4, ta, ma -; ZVFHMIN-NEXT: vfmv.v.f v12, fa5 -; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m2, ta, ma -; ZVFHMIN-NEXT: vfncvt.f.f.w v10, v12 +; ZVFHMIN-NEXT: fmv.x.h a0, fa0 +; ZVFHMIN-NEXT: vsetvli a1, zero, e16, m2, ta, ma +; ZVFHMIN-NEXT: vmv.v.x v10, a0 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v8 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v10 ; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m4, ta, ma @@ -685,11 +651,9 @@ define @fcmp_one_vf_nxv8f16_nonans( %va, ha ; ; ZVFHMIN-LABEL: fcmp_one_vf_nxv8f16_nonans: ; ZVFHMIN: # %bb.0: -; ZVFHMIN-NEXT: fcvt.s.h fa5, fa0 -; ZVFHMIN-NEXT: vsetvli a0, zero, e32, m4, ta, ma -; ZVFHMIN-NEXT: vfmv.v.f v12, fa5 -; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m2, ta, ma -; ZVFHMIN-NEXT: vfncvt.f.f.w v10, v12 +; ZVFHMIN-NEXT: fmv.x.h a0, fa0 +; ZVFHMIN-NEXT: vsetvli a1, zero, e16, m2, ta, ma +; ZVFHMIN-NEXT: vmv.v.x v10, a0 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v8 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v10 ; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m4, ta, ma @@ -738,11 +702,9 @@ define @fcmp_ord_vf_nxv8f16( %va, half %b) ; ; ZVFHMIN-LABEL: fcmp_ord_vf_nxv8f16: ; ZVFHMIN: # %bb.0: -; ZVFHMIN-NEXT: fcvt.s.h fa5, fa0 -; ZVFHMIN-NEXT: vsetvli a0, zero, e32, m4, ta, ma -; ZVFHMIN-NEXT: vfmv.v.f v12, fa5 -; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m2, ta, ma -; ZVFHMIN-NEXT: vfncvt.f.f.w v10, v12 +; ZVFHMIN-NEXT: fmv.x.h a0, fa0 +; ZVFHMIN-NEXT: vsetvli a1, zero, e16, m2, ta, ma +; ZVFHMIN-NEXT: vmv.v.x v10, a0 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v8 ; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m4, ta, ma ; ZVFHMIN-NEXT: vmfeq.vv v8, v12, v12 @@ -770,11 +732,9 @@ define @fcmp_ord_fv_nxv8f16( %va, half %b) ; ; ZVFHMIN-LABEL: fcmp_ord_fv_nxv8f16: ; ZVFHMIN: # %bb.0: -; ZVFHMIN-NEXT: fcvt.s.h fa5, fa0 -; ZVFHMIN-NEXT: vsetvli a0, zero, e32, m4, ta, ma -; ZVFHMIN-NEXT: vfmv.v.f v12, fa5 -; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m2, ta, ma -; ZVFHMIN-NEXT: vfncvt.f.f.w v10, v12 +; ZVFHMIN-NEXT: fmv.x.h a0, fa0 +; ZVFHMIN-NEXT: vsetvli a1, zero, e16, m2, ta, ma +; ZVFHMIN-NEXT: vmv.v.x v10, a0 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v8 ; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m4, ta, ma ; ZVFHMIN-NEXT: vmfeq.vv v8, v12, v12 @@ -827,11 +787,9 @@ define @fcmp_ord_vf_nxv8f16_nonans( %va, ha ; ; ZVFHMIN-LABEL: fcmp_ord_vf_nxv8f16_nonans: ; ZVFHMIN: # %bb.0: -; ZVFHMIN-NEXT: fcvt.s.h fa5, fa0 -; ZVFHMIN-NEXT: vsetvli a0, zero, e32, m4, ta, ma -; ZVFHMIN-NEXT: vfmv.v.f v12, fa5 -; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m2, ta, ma -; ZVFHMIN-NEXT: vfncvt.f.f.w v10, v12 +; ZVFHMIN-NEXT: fmv.x.h a0, fa0 +; ZVFHMIN-NEXT: vsetvli a1, zero, e16, m2, ta, ma +; ZVFHMIN-NEXT: vmv.v.x v10, a0 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v8 ; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m4, ta, ma ; ZVFHMIN-NEXT: vmfeq.vv v8, v12, v12 @@ -881,11 +839,9 @@ define @fcmp_ueq_vf_nxv8f16( %va, half %b) ; ; ZVFHMIN-LABEL: fcmp_ueq_vf_nxv8f16: ; ZVFHMIN: # %bb.0: -; ZVFHMIN-NEXT: fcvt.s.h fa5, fa0 -; ZVFHMIN-NEXT: vsetvli a0, zero, e32, m4, ta, ma -; ZVFHMIN-NEXT: vfmv.v.f v12, fa5 -; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m2, ta, ma -; ZVFHMIN-NEXT: vfncvt.f.f.w v10, v12 +; ZVFHMIN-NEXT: fmv.x.h a0, fa0 +; ZVFHMIN-NEXT: vsetvli a1, zero, e16, m2, ta, ma +; ZVFHMIN-NEXT: vmv.v.x v10, a0 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v8 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v10 ; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m4, ta, ma @@ -910,11 +866,9 @@ define @fcmp_ueq_fv_nxv8f16( %va, half %b) ; ; ZVFHMIN-LABEL: fcmp_ueq_fv_nxv8f16: ; ZVFHMIN: # %bb.0: -; ZVFHMIN-NEXT: fcvt.s.h fa5, fa0 -; ZVFHMIN-NEXT: vsetvli a0, zero, e32, m4, ta, ma -; ZVFHMIN-NEXT: vfmv.v.f v12, fa5 -; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m2, ta, ma -; ZVFHMIN-NEXT: vfncvt.f.f.w v10, v12 +; ZVFHMIN-NEXT: fmv.x.h a0, fa0 +; ZVFHMIN-NEXT: vsetvli a1, zero, e16, m2, ta, ma +; ZVFHMIN-NEXT: vmv.v.x v10, a0 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v8 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v10 ; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m4, ta, ma @@ -956,11 +910,9 @@ define @fcmp_ueq_vf_nxv8f16_nonans( %va, ha ; ; ZVFHMIN-LABEL: fcmp_ueq_vf_nxv8f16_nonans: ; ZVFHMIN: # %bb.0: -; ZVFHMIN-NEXT: fcvt.s.h fa5, fa0 -; ZVFHMIN-NEXT: vsetvli a0, zero, e32, m4, ta, ma -; ZVFHMIN-NEXT: vfmv.v.f v12, fa5 -; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m2, ta, ma -; ZVFHMIN-NEXT: vfncvt.f.f.w v10, v12 +; ZVFHMIN-NEXT: fmv.x.h a0, fa0 +; ZVFHMIN-NEXT: vsetvli a1, zero, e16, m2, ta, ma +; ZVFHMIN-NEXT: vmv.v.x v10, a0 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v8 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v10 ; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m4, ta, ma @@ -1003,11 +955,9 @@ define @fcmp_ugt_vf_nxv8f16( %va, half %b) ; ; ZVFHMIN-LABEL: fcmp_ugt_vf_nxv8f16: ; ZVFHMIN: # %bb.0: -; ZVFHMIN-NEXT: fcvt.s.h fa5, fa0 -; ZVFHMIN-NEXT: vsetvli a0, zero, e32, m4, ta, ma -; ZVFHMIN-NEXT: vfmv.v.f v12, fa5 -; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m2, ta, ma -; ZVFHMIN-NEXT: vfncvt.f.f.w v10, v12 +; ZVFHMIN-NEXT: fmv.x.h a0, fa0 +; ZVFHMIN-NEXT: vsetvli a1, zero, e16, m2, ta, ma +; ZVFHMIN-NEXT: vmv.v.x v10, a0 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v8 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v10 ; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m4, ta, ma @@ -1030,11 +980,9 @@ define @fcmp_ugt_fv_nxv8f16( %va, half %b) ; ; ZVFHMIN-LABEL: fcmp_ugt_fv_nxv8f16: ; ZVFHMIN: # %bb.0: -; ZVFHMIN-NEXT: fcvt.s.h fa5, fa0 -; ZVFHMIN-NEXT: vsetvli a0, zero, e32, m4, ta, ma -; ZVFHMIN-NEXT: vfmv.v.f v12, fa5 -; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m2, ta, ma -; ZVFHMIN-NEXT: vfncvt.f.f.w v10, v12 +; ZVFHMIN-NEXT: fmv.x.h a0, fa0 +; ZVFHMIN-NEXT: vsetvli a1, zero, e16, m2, ta, ma +; ZVFHMIN-NEXT: vmv.v.x v10, a0 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v8 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v10 ; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m4, ta, ma @@ -1075,11 +1023,9 @@ define @fcmp_ugt_vf_nxv8f16_nonans( %va, ha ; ; ZVFHMIN-LABEL: fcmp_ugt_vf_nxv8f16_nonans: ; ZVFHMIN: # %bb.0: -; ZVFHMIN-NEXT: fcvt.s.h fa5, fa0 -; ZVFHMIN-NEXT: vsetvli a0, zero, e32, m4, ta, ma -; ZVFHMIN-NEXT: vfmv.v.f v12, fa5 -; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m2, ta, ma -; ZVFHMIN-NEXT: vfncvt.f.f.w v10, v12 +; ZVFHMIN-NEXT: fmv.x.h a0, fa0 +; ZVFHMIN-NEXT: vsetvli a1, zero, e16, m2, ta, ma +; ZVFHMIN-NEXT: vmv.v.x v10, a0 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v8 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v10 ; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m4, ta, ma @@ -1122,11 +1068,9 @@ define @fcmp_uge_vf_nxv8f16( %va, half %b) ; ; ZVFHMIN-LABEL: fcmp_uge_vf_nxv8f16: ; ZVFHMIN: # %bb.0: -; ZVFHMIN-NEXT: fcvt.s.h fa5, fa0 -; ZVFHMIN-NEXT: vsetvli a0, zero, e32, m4, ta, ma -; ZVFHMIN-NEXT: vfmv.v.f v12, fa5 -; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m2, ta, ma -; ZVFHMIN-NEXT: vfncvt.f.f.w v10, v12 +; ZVFHMIN-NEXT: fmv.x.h a0, fa0 +; ZVFHMIN-NEXT: vsetvli a1, zero, e16, m2, ta, ma +; ZVFHMIN-NEXT: vmv.v.x v10, a0 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v8 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v10 ; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m4, ta, ma @@ -1149,11 +1093,9 @@ define @fcmp_uge_fv_nxv8f16( %va, half %b) ; ; ZVFHMIN-LABEL: fcmp_uge_fv_nxv8f16: ; ZVFHMIN: # %bb.0: -; ZVFHMIN-NEXT: fcvt.s.h fa5, fa0 -; ZVFHMIN-NEXT: vsetvli a0, zero, e32, m4, ta, ma -; ZVFHMIN-NEXT: vfmv.v.f v12, fa5 -; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m2, ta, ma -; ZVFHMIN-NEXT: vfncvt.f.f.w v10, v12 +; ZVFHMIN-NEXT: fmv.x.h a0, fa0 +; ZVFHMIN-NEXT: vsetvli a1, zero, e16, m2, ta, ma +; ZVFHMIN-NEXT: vmv.v.x v10, a0 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v8 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v10 ; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m4, ta, ma @@ -1194,11 +1136,9 @@ define @fcmp_uge_vf_nxv8f16_nonans( %va, ha ; ; ZVFHMIN-LABEL: fcmp_uge_vf_nxv8f16_nonans: ; ZVFHMIN: # %bb.0: -; ZVFHMIN-NEXT: fcvt.s.h fa5, fa0 -; ZVFHMIN-NEXT: vsetvli a0, zero, e32, m4, ta, ma -; ZVFHMIN-NEXT: vfmv.v.f v12, fa5 -; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m2, ta, ma -; ZVFHMIN-NEXT: vfncvt.f.f.w v10, v12 +; ZVFHMIN-NEXT: fmv.x.h a0, fa0 +; ZVFHMIN-NEXT: vsetvli a1, zero, e16, m2, ta, ma +; ZVFHMIN-NEXT: vmv.v.x v10, a0 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v8 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v10 ; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m4, ta, ma @@ -1241,11 +1181,9 @@ define @fcmp_ult_vf_nxv8f16( %va, half %b) ; ; ZVFHMIN-LABEL: fcmp_ult_vf_nxv8f16: ; ZVFHMIN: # %bb.0: -; ZVFHMIN-NEXT: fcvt.s.h fa5, fa0 -; ZVFHMIN-NEXT: vsetvli a0, zero, e32, m4, ta, ma -; ZVFHMIN-NEXT: vfmv.v.f v12, fa5 -; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m2, ta, ma -; ZVFHMIN-NEXT: vfncvt.f.f.w v10, v12 +; ZVFHMIN-NEXT: fmv.x.h a0, fa0 +; ZVFHMIN-NEXT: vsetvli a1, zero, e16, m2, ta, ma +; ZVFHMIN-NEXT: vmv.v.x v10, a0 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v8 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v10 ; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m4, ta, ma @@ -1268,11 +1206,9 @@ define @fcmp_ult_fv_nxv8f16( %va, half %b) ; ; ZVFHMIN-LABEL: fcmp_ult_fv_nxv8f16: ; ZVFHMIN: # %bb.0: -; ZVFHMIN-NEXT: fcvt.s.h fa5, fa0 -; ZVFHMIN-NEXT: vsetvli a0, zero, e32, m4, ta, ma -; ZVFHMIN-NEXT: vfmv.v.f v12, fa5 -; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m2, ta, ma -; ZVFHMIN-NEXT: vfncvt.f.f.w v10, v12 +; ZVFHMIN-NEXT: fmv.x.h a0, fa0 +; ZVFHMIN-NEXT: vsetvli a1, zero, e16, m2, ta, ma +; ZVFHMIN-NEXT: vmv.v.x v10, a0 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v8 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v10 ; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m4, ta, ma @@ -1313,11 +1249,9 @@ define @fcmp_ult_vf_nxv8f16_nonans( %va, ha ; ; ZVFHMIN-LABEL: fcmp_ult_vf_nxv8f16_nonans: ; ZVFHMIN: # %bb.0: -; ZVFHMIN-NEXT: fcvt.s.h fa5, fa0 -; ZVFHMIN-NEXT: vsetvli a0, zero, e32, m4, ta, ma -; ZVFHMIN-NEXT: vfmv.v.f v12, fa5 -; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m2, ta, ma -; ZVFHMIN-NEXT: vfncvt.f.f.w v10, v12 +; ZVFHMIN-NEXT: fmv.x.h a0, fa0 +; ZVFHMIN-NEXT: vsetvli a1, zero, e16, m2, ta, ma +; ZVFHMIN-NEXT: vmv.v.x v10, a0 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v8 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v10 ; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m4, ta, ma @@ -1360,11 +1294,9 @@ define @fcmp_ule_vf_nxv8f16( %va, half %b) ; ; ZVFHMIN-LABEL: fcmp_ule_vf_nxv8f16: ; ZVFHMIN: # %bb.0: -; ZVFHMIN-NEXT: fcvt.s.h fa5, fa0 -; ZVFHMIN-NEXT: vsetvli a0, zero, e32, m4, ta, ma -; ZVFHMIN-NEXT: vfmv.v.f v12, fa5 -; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m2, ta, ma -; ZVFHMIN-NEXT: vfncvt.f.f.w v10, v12 +; ZVFHMIN-NEXT: fmv.x.h a0, fa0 +; ZVFHMIN-NEXT: vsetvli a1, zero, e16, m2, ta, ma +; ZVFHMIN-NEXT: vmv.v.x v10, a0 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v8 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v10 ; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m4, ta, ma @@ -1387,11 +1319,9 @@ define @fcmp_ule_fv_nxv8f16( %va, half %b) ; ; ZVFHMIN-LABEL: fcmp_ule_fv_nxv8f16: ; ZVFHMIN: # %bb.0: -; ZVFHMIN-NEXT: fcvt.s.h fa5, fa0 -; ZVFHMIN-NEXT: vsetvli a0, zero, e32, m4, ta, ma -; ZVFHMIN-NEXT: vfmv.v.f v12, fa5 -; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m2, ta, ma -; ZVFHMIN-NEXT: vfncvt.f.f.w v10, v12 +; ZVFHMIN-NEXT: fmv.x.h a0, fa0 +; ZVFHMIN-NEXT: vsetvli a1, zero, e16, m2, ta, ma +; ZVFHMIN-NEXT: vmv.v.x v10, a0 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v8 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v10 ; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m4, ta, ma @@ -1432,11 +1362,9 @@ define @fcmp_ule_vf_nxv8f16_nonans( %va, ha ; ; ZVFHMIN-LABEL: fcmp_ule_vf_nxv8f16_nonans: ; ZVFHMIN: # %bb.0: -; ZVFHMIN-NEXT: fcvt.s.h fa5, fa0 -; ZVFHMIN-NEXT: vsetvli a0, zero, e32, m4, ta, ma -; ZVFHMIN-NEXT: vfmv.v.f v12, fa5 -; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m2, ta, ma -; ZVFHMIN-NEXT: vfncvt.f.f.w v10, v12 +; ZVFHMIN-NEXT: fmv.x.h a0, fa0 +; ZVFHMIN-NEXT: vsetvli a1, zero, e16, m2, ta, ma +; ZVFHMIN-NEXT: vmv.v.x v10, a0 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v8 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v10 ; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m4, ta, ma @@ -1476,11 +1404,9 @@ define @fcmp_une_vf_nxv8f16( %va, half %b) ; ; ZVFHMIN-LABEL: fcmp_une_vf_nxv8f16: ; ZVFHMIN: # %bb.0: -; ZVFHMIN-NEXT: fcvt.s.h fa5, fa0 -; ZVFHMIN-NEXT: vsetvli a0, zero, e32, m4, ta, ma -; ZVFHMIN-NEXT: vfmv.v.f v12, fa5 -; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m2, ta, ma -; ZVFHMIN-NEXT: vfncvt.f.f.w v10, v12 +; ZVFHMIN-NEXT: fmv.x.h a0, fa0 +; ZVFHMIN-NEXT: vsetvli a1, zero, e16, m2, ta, ma +; ZVFHMIN-NEXT: vmv.v.x v10, a0 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v8 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v10 ; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m4, ta, ma @@ -1501,11 +1427,9 @@ define @fcmp_une_fv_nxv8f16( %va, half %b) ; ; ZVFHMIN-LABEL: fcmp_une_fv_nxv8f16: ; ZVFHMIN: # %bb.0: -; ZVFHMIN-NEXT: fcvt.s.h fa5, fa0 -; ZVFHMIN-NEXT: vsetvli a0, zero, e32, m4, ta, ma -; ZVFHMIN-NEXT: vfmv.v.f v12, fa5 -; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m2, ta, ma -; ZVFHMIN-NEXT: vfncvt.f.f.w v10, v12 +; ZVFHMIN-NEXT: fmv.x.h a0, fa0 +; ZVFHMIN-NEXT: vsetvli a1, zero, e16, m2, ta, ma +; ZVFHMIN-NEXT: vmv.v.x v10, a0 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v8 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v10 ; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m4, ta, ma @@ -1545,11 +1469,9 @@ define @fcmp_une_vf_nxv8f16_nonans( %va, ha ; ; ZVFHMIN-LABEL: fcmp_une_vf_nxv8f16_nonans: ; ZVFHMIN: # %bb.0: -; ZVFHMIN-NEXT: fcvt.s.h fa5, fa0 -; ZVFHMIN-NEXT: vsetvli a0, zero, e32, m4, ta, ma -; ZVFHMIN-NEXT: vfmv.v.f v12, fa5 -; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m2, ta, ma -; ZVFHMIN-NEXT: vfncvt.f.f.w v10, v12 +; ZVFHMIN-NEXT: fmv.x.h a0, fa0 +; ZVFHMIN-NEXT: vsetvli a1, zero, e16, m2, ta, ma +; ZVFHMIN-NEXT: vmv.v.x v10, a0 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v8 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v10 ; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m4, ta, ma @@ -1598,11 +1520,9 @@ define @fcmp_uno_vf_nxv8f16( %va, half %b) ; ; ZVFHMIN-LABEL: fcmp_uno_vf_nxv8f16: ; ZVFHMIN: # %bb.0: -; ZVFHMIN-NEXT: fcvt.s.h fa5, fa0 -; ZVFHMIN-NEXT: vsetvli a0, zero, e32, m4, ta, ma -; ZVFHMIN-NEXT: vfmv.v.f v12, fa5 -; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m2, ta, ma -; ZVFHMIN-NEXT: vfncvt.f.f.w v10, v12 +; ZVFHMIN-NEXT: fmv.x.h a0, fa0 +; ZVFHMIN-NEXT: vsetvli a1, zero, e16, m2, ta, ma +; ZVFHMIN-NEXT: vmv.v.x v10, a0 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v8 ; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m4, ta, ma ; ZVFHMIN-NEXT: vmfne.vv v8, v12, v12 @@ -1630,11 +1550,9 @@ define @fcmp_uno_fv_nxv8f16( %va, half %b) ; ; ZVFHMIN-LABEL: fcmp_uno_fv_nxv8f16: ; ZVFHMIN: # %bb.0: -; ZVFHMIN-NEXT: fcvt.s.h fa5, fa0 -; ZVFHMIN-NEXT: vsetvli a0, zero, e32, m4, ta, ma -; ZVFHMIN-NEXT: vfmv.v.f v12, fa5 -; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m2, ta, ma -; ZVFHMIN-NEXT: vfncvt.f.f.w v10, v12 +; ZVFHMIN-NEXT: fmv.x.h a0, fa0 +; ZVFHMIN-NEXT: vsetvli a1, zero, e16, m2, ta, ma +; ZVFHMIN-NEXT: vmv.v.x v10, a0 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v8 ; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m4, ta, ma ; ZVFHMIN-NEXT: vmfne.vv v8, v12, v12 @@ -1687,11 +1605,9 @@ define @fcmp_uno_vf_nxv8f16_nonans( %va, ha ; ; ZVFHMIN-LABEL: fcmp_uno_vf_nxv8f16_nonans: ; ZVFHMIN: # %bb.0: -; ZVFHMIN-NEXT: fcvt.s.h fa5, fa0 -; ZVFHMIN-NEXT: vsetvli a0, zero, e32, m4, ta, ma -; ZVFHMIN-NEXT: vfmv.v.f v12, fa5 -; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m2, ta, ma -; ZVFHMIN-NEXT: vfncvt.f.f.w v10, v12 +; ZVFHMIN-NEXT: fmv.x.h a0, fa0 +; ZVFHMIN-NEXT: vsetvli a1, zero, e16, m2, ta, ma +; ZVFHMIN-NEXT: vmv.v.x v10, a0 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v8 ; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m4, ta, ma ; ZVFHMIN-NEXT: vmfne.vv v8, v12, v12 diff --git a/llvm/test/CodeGen/RISCV/rvv/vfadd-constrained-sdnode.ll b/llvm/test/CodeGen/RISCV/rvv/vfadd-constrained-sdnode.ll index b4801922398d48..af80e627b43fa1 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vfadd-constrained-sdnode.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vfadd-constrained-sdnode.ll @@ -40,15 +40,13 @@ define @vfadd_vf_nxv1f16( %va, half %b) s ; ; ZVFHMIN-LABEL: vfadd_vf_nxv1f16: ; ZVFHMIN: # %bb.0: -; ZVFHMIN-NEXT: fcvt.s.h fa5, fa0 -; ZVFHMIN-NEXT: vsetvli a0, zero, e32, mf2, ta, ma -; ZVFHMIN-NEXT: vfmv.v.f v9, fa5 -; ZVFHMIN-NEXT: vsetvli zero, zero, e16, mf4, ta, ma -; ZVFHMIN-NEXT: vfncvt.f.f.w v10, v9 -; ZVFHMIN-NEXT: vfwcvt.f.f.v v9, v8 -; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v10 +; ZVFHMIN-NEXT: fmv.x.h a0, fa0 +; ZVFHMIN-NEXT: vsetvli a1, zero, e16, mf4, ta, ma +; ZVFHMIN-NEXT: vmv.v.x v9, a0 +; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v8 +; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v9 ; ZVFHMIN-NEXT: vsetvli zero, zero, e32, mf2, ta, ma -; ZVFHMIN-NEXT: vfadd.vv v9, v9, v8 +; ZVFHMIN-NEXT: vfadd.vv v9, v10, v8 ; ZVFHMIN-NEXT: vsetvli zero, zero, e16, mf4, ta, ma ; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v9 ; ZVFHMIN-NEXT: ret @@ -90,15 +88,13 @@ define @vfadd_vf_nxv2f16( %va, half %b) s ; ; ZVFHMIN-LABEL: vfadd_vf_nxv2f16: ; ZVFHMIN: # %bb.0: -; ZVFHMIN-NEXT: fcvt.s.h fa5, fa0 -; ZVFHMIN-NEXT: vsetvli a0, zero, e32, m1, ta, ma -; ZVFHMIN-NEXT: vfmv.v.f v9, fa5 -; ZVFHMIN-NEXT: vsetvli zero, zero, e16, mf2, ta, ma -; ZVFHMIN-NEXT: vfncvt.f.f.w v10, v9 -; ZVFHMIN-NEXT: vfwcvt.f.f.v v9, v8 -; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v10 +; ZVFHMIN-NEXT: fmv.x.h a0, fa0 +; ZVFHMIN-NEXT: vsetvli a1, zero, e16, mf2, ta, ma +; ZVFHMIN-NEXT: vmv.v.x v9, a0 +; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v8 +; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v9 ; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m1, ta, ma -; ZVFHMIN-NEXT: vfadd.vv v9, v9, v8 +; ZVFHMIN-NEXT: vfadd.vv v9, v10, v8 ; ZVFHMIN-NEXT: vsetvli zero, zero, e16, mf2, ta, ma ; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v9 ; ZVFHMIN-NEXT: ret @@ -140,11 +136,9 @@ define @vfadd_vf_nxv4f16( %va, half %b) s ; ; ZVFHMIN-LABEL: vfadd_vf_nxv4f16: ; ZVFHMIN: # %bb.0: -; ZVFHMIN-NEXT: fcvt.s.h fa5, fa0 -; ZVFHMIN-NEXT: vsetvli a0, zero, e32, m2, ta, ma -; ZVFHMIN-NEXT: vfmv.v.f v10, fa5 -; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m1, ta, ma -; ZVFHMIN-NEXT: vfncvt.f.f.w v9, v10 +; ZVFHMIN-NEXT: fmv.x.h a0, fa0 +; ZVFHMIN-NEXT: vsetvli a1, zero, e16, m1, ta, ma +; ZVFHMIN-NEXT: vmv.v.x v9, a0 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v8 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v9 ; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m2, ta, ma @@ -190,11 +184,9 @@ define @vfadd_vf_nxv8f16( %va, half %b) s ; ; ZVFHMIN-LABEL: vfadd_vf_nxv8f16: ; ZVFHMIN: # %bb.0: -; ZVFHMIN-NEXT: fcvt.s.h fa5, fa0 -; ZVFHMIN-NEXT: vsetvli a0, zero, e32, m4, ta, ma -; ZVFHMIN-NEXT: vfmv.v.f v12, fa5 -; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m2, ta, ma -; ZVFHMIN-NEXT: vfncvt.f.f.w v10, v12 +; ZVFHMIN-NEXT: fmv.x.h a0, fa0 +; ZVFHMIN-NEXT: vsetvli a1, zero, e16, m2, ta, ma +; ZVFHMIN-NEXT: vmv.v.x v10, a0 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v8 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v10 ; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m4, ta, ma @@ -240,11 +232,9 @@ define @vfadd_vf_nxv16f16( %va, half %b ; ; ZVFHMIN-LABEL: vfadd_vf_nxv16f16: ; ZVFHMIN: # %bb.0: -; ZVFHMIN-NEXT: fcvt.s.h fa5, fa0 -; ZVFHMIN-NEXT: vsetvli a0, zero, e32, m8, ta, ma -; ZVFHMIN-NEXT: vfmv.v.f v16, fa5 -; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m4, ta, ma -; ZVFHMIN-NEXT: vfncvt.f.f.w v12, v16 +; ZVFHMIN-NEXT: fmv.x.h a0, fa0 +; ZVFHMIN-NEXT: vsetvli a1, zero, e16, m4, ta, ma +; ZVFHMIN-NEXT: vmv.v.x v12, a0 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v8 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v24, v12 ; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma @@ -296,21 +286,20 @@ define @vfadd_vf_nxv32f16( %va, half %b ; ; ZVFHMIN-LABEL: vfadd_vf_nxv32f16: ; ZVFHMIN: # %bb.0: -; ZVFHMIN-NEXT: fcvt.s.h fa5, fa0 -; ZVFHMIN-NEXT: vsetvli a0, zero, e32, m8, ta, ma -; ZVFHMIN-NEXT: vfmv.v.f v16, fa5 -; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m4, ta, ma -; ZVFHMIN-NEXT: vfncvt.f.f.w v24, v16 -; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v8 -; ZVFHMIN-NEXT: vfwcvt.f.f.v v0, v24 +; ZVFHMIN-NEXT: fmv.x.h a0, fa0 +; ZVFHMIN-NEXT: vsetvli a1, zero, e16, m8, ta, ma +; ZVFHMIN-NEXT: vmv.v.x v16, a0 +; ZVFHMIN-NEXT: vsetvli a0, zero, e16, m4, ta, ma +; ZVFHMIN-NEXT: vfwcvt.f.f.v v24, v8 +; ZVFHMIN-NEXT: vfwcvt.f.f.v v0, v16 ; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma -; ZVFHMIN-NEXT: vfadd.vv v16, v16, v0 +; ZVFHMIN-NEXT: vfadd.vv v24, v24, v0 ; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m4, ta, ma -; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v16 -; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v24 -; ZVFHMIN-NEXT: vfwcvt.f.f.v v24, v12 +; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v24 +; ZVFHMIN-NEXT: vfwcvt.f.f.v v24, v20 +; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v12 ; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma -; ZVFHMIN-NEXT: vfadd.vv v16, v24, v16 +; ZVFHMIN-NEXT: vfadd.vv v16, v16, v24 ; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m4, ta, ma ; ZVFHMIN-NEXT: vfncvt.f.f.w v12, v16 ; ZVFHMIN-NEXT: ret diff --git a/llvm/test/CodeGen/RISCV/rvv/vfadd-sdnode.ll b/llvm/test/CodeGen/RISCV/rvv/vfadd-sdnode.ll index 4065b69e781ad4..8f21e326e68790 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vfadd-sdnode.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vfadd-sdnode.ll @@ -38,15 +38,13 @@ define @vfadd_vf_nxv1f16( %va, half %b) { ; ; ZVFHMIN-LABEL: vfadd_vf_nxv1f16: ; ZVFHMIN: # %bb.0: -; ZVFHMIN-NEXT: fcvt.s.h fa5, fa0 -; ZVFHMIN-NEXT: vsetvli a0, zero, e32, mf2, ta, ma -; ZVFHMIN-NEXT: vfmv.v.f v9, fa5 -; ZVFHMIN-NEXT: vsetvli zero, zero, e16, mf4, ta, ma -; ZVFHMIN-NEXT: vfncvt.f.f.w v10, v9 -; ZVFHMIN-NEXT: vfwcvt.f.f.v v9, v8 -; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v10 +; ZVFHMIN-NEXT: fmv.x.h a0, fa0 +; ZVFHMIN-NEXT: vsetvli a1, zero, e16, mf4, ta, ma +; ZVFHMIN-NEXT: vmv.v.x v9, a0 +; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v8 +; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v9 ; ZVFHMIN-NEXT: vsetvli zero, zero, e32, mf2, ta, ma -; ZVFHMIN-NEXT: vfadd.vv v9, v9, v8 +; ZVFHMIN-NEXT: vfadd.vv v9, v10, v8 ; ZVFHMIN-NEXT: vsetvli zero, zero, e16, mf4, ta, ma ; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v9 ; ZVFHMIN-NEXT: ret @@ -86,15 +84,13 @@ define @vfadd_vf_nxv2f16( %va, half %b) { ; ; ZVFHMIN-LABEL: vfadd_vf_nxv2f16: ; ZVFHMIN: # %bb.0: -; ZVFHMIN-NEXT: fcvt.s.h fa5, fa0 -; ZVFHMIN-NEXT: vsetvli a0, zero, e32, m1, ta, ma -; ZVFHMIN-NEXT: vfmv.v.f v9, fa5 -; ZVFHMIN-NEXT: vsetvli zero, zero, e16, mf2, ta, ma -; ZVFHMIN-NEXT: vfncvt.f.f.w v10, v9 -; ZVFHMIN-NEXT: vfwcvt.f.f.v v9, v8 -; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v10 +; ZVFHMIN-NEXT: fmv.x.h a0, fa0 +; ZVFHMIN-NEXT: vsetvli a1, zero, e16, mf2, ta, ma +; ZVFHMIN-NEXT: vmv.v.x v9, a0 +; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v8 +; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v9 ; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m1, ta, ma -; ZVFHMIN-NEXT: vfadd.vv v9, v9, v8 +; ZVFHMIN-NEXT: vfadd.vv v9, v10, v8 ; ZVFHMIN-NEXT: vsetvli zero, zero, e16, mf2, ta, ma ; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v9 ; ZVFHMIN-NEXT: ret @@ -134,11 +130,9 @@ define @vfadd_vf_nxv4f16( %va, half %b) { ; ; ZVFHMIN-LABEL: vfadd_vf_nxv4f16: ; ZVFHMIN: # %bb.0: -; ZVFHMIN-NEXT: fcvt.s.h fa5, fa0 -; ZVFHMIN-NEXT: vsetvli a0, zero, e32, m2, ta, ma -; ZVFHMIN-NEXT: vfmv.v.f v10, fa5 -; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m1, ta, ma -; ZVFHMIN-NEXT: vfncvt.f.f.w v9, v10 +; ZVFHMIN-NEXT: fmv.x.h a0, fa0 +; ZVFHMIN-NEXT: vsetvli a1, zero, e16, m1, ta, ma +; ZVFHMIN-NEXT: vmv.v.x v9, a0 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v8 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v9 ; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m2, ta, ma @@ -182,11 +176,9 @@ define @vfadd_vf_nxv8f16( %va, half %b) { ; ; ZVFHMIN-LABEL: vfadd_vf_nxv8f16: ; ZVFHMIN: # %bb.0: -; ZVFHMIN-NEXT: fcvt.s.h fa5, fa0 -; ZVFHMIN-NEXT: vsetvli a0, zero, e32, m4, ta, ma -; ZVFHMIN-NEXT: vfmv.v.f v12, fa5 -; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m2, ta, ma -; ZVFHMIN-NEXT: vfncvt.f.f.w v10, v12 +; ZVFHMIN-NEXT: fmv.x.h a0, fa0 +; ZVFHMIN-NEXT: vsetvli a1, zero, e16, m2, ta, ma +; ZVFHMIN-NEXT: vmv.v.x v10, a0 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v8 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v10 ; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m4, ta, ma @@ -209,11 +201,9 @@ define @vfadd_fv_nxv8f16( %va, half %b) { ; ; ZVFHMIN-LABEL: vfadd_fv_nxv8f16: ; ZVFHMIN: # %bb.0: -; ZVFHMIN-NEXT: fcvt.s.h fa5, fa0 -; ZVFHMIN-NEXT: vsetvli a0, zero, e32, m4, ta, ma -; ZVFHMIN-NEXT: vfmv.v.f v12, fa5 -; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m2, ta, ma -; ZVFHMIN-NEXT: vfncvt.f.f.w v10, v12 +; ZVFHMIN-NEXT: fmv.x.h a0, fa0 +; ZVFHMIN-NEXT: vsetvli a1, zero, e16, m2, ta, ma +; ZVFHMIN-NEXT: vmv.v.x v10, a0 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v8 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v10 ; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m4, ta, ma @@ -257,11 +247,9 @@ define @vfadd_vf_nxv16f16( %va, half %b ; ; ZVFHMIN-LABEL: vfadd_vf_nxv16f16: ; ZVFHMIN: # %bb.0: -; ZVFHMIN-NEXT: fcvt.s.h fa5, fa0 -; ZVFHMIN-NEXT: vsetvli a0, zero, e32, m8, ta, ma -; ZVFHMIN-NEXT: vfmv.v.f v16, fa5 -; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m4, ta, ma -; ZVFHMIN-NEXT: vfncvt.f.f.w v12, v16 +; ZVFHMIN-NEXT: fmv.x.h a0, fa0 +; ZVFHMIN-NEXT: vsetvli a1, zero, e16, m4, ta, ma +; ZVFHMIN-NEXT: vmv.v.x v12, a0 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v8 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v24, v12 ; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma @@ -311,20 +299,20 @@ define @vfadd_vf_nxv32f16( %va, half %b ; ; ZVFHMIN-LABEL: vfadd_vf_nxv32f16: ; ZVFHMIN: # %bb.0: -; ZVFHMIN-NEXT: fcvt.s.h fa5, fa0 -; ZVFHMIN-NEXT: vsetvli a0, zero, e32, m8, ta, ma -; ZVFHMIN-NEXT: vfmv.v.f v16, fa5 -; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m4, ta, ma -; ZVFHMIN-NEXT: vfncvt.f.f.w v24, v16 -; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v8 -; ZVFHMIN-NEXT: vfwcvt.f.f.v v0, v24 +; ZVFHMIN-NEXT: fmv.x.h a0, fa0 +; ZVFHMIN-NEXT: vsetvli a1, zero, e16, m8, ta, ma +; ZVFHMIN-NEXT: vmv.v.x v16, a0 +; ZVFHMIN-NEXT: vsetvli a0, zero, e16, m4, ta, ma +; ZVFHMIN-NEXT: vfwcvt.f.f.v v24, v8 +; ZVFHMIN-NEXT: vfwcvt.f.f.v v0, v16 ; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma -; ZVFHMIN-NEXT: vfadd.vv v16, v16, v0 +; ZVFHMIN-NEXT: vfadd.vv v24, v24, v0 ; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m4, ta, ma -; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v16 -; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v12 +; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v24 +; ZVFHMIN-NEXT: vfwcvt.f.f.v v24, v12 +; ZVFHMIN-NEXT: vfwcvt.f.f.v v0, v20 ; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma -; ZVFHMIN-NEXT: vfadd.vv v16, v16, v0 +; ZVFHMIN-NEXT: vfadd.vv v16, v24, v0 ; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m4, ta, ma ; ZVFHMIN-NEXT: vfncvt.f.f.w v12, v16 ; ZVFHMIN-NEXT: ret diff --git a/llvm/test/CodeGen/RISCV/rvv/vfadd-vp.ll b/llvm/test/CodeGen/RISCV/rvv/vfadd-vp.ll index ad7fb63fec2fcf..395f1a7c382bff 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vfadd-vp.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vfadd-vp.ll @@ -61,15 +61,13 @@ define @vfadd_vf_nxv1f16( %va, half %b, < ; ; ZVFHMIN-LABEL: vfadd_vf_nxv1f16: ; ZVFHMIN: # %bb.0: -; ZVFHMIN-NEXT: fcvt.s.h fa5, fa0 -; ZVFHMIN-NEXT: vsetvli a1, zero, e32, mf2, ta, ma -; ZVFHMIN-NEXT: vfmv.v.f v9, fa5 -; ZVFHMIN-NEXT: vsetvli zero, zero, e16, mf4, ta, ma -; ZVFHMIN-NEXT: vfncvt.f.f.w v10, v9 -; ZVFHMIN-NEXT: vfwcvt.f.f.v v9, v8 -; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v10 +; ZVFHMIN-NEXT: fmv.x.h a1, fa0 +; ZVFHMIN-NEXT: vsetvli a2, zero, e16, mf4, ta, ma +; ZVFHMIN-NEXT: vmv.v.x v9, a1 +; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v8 +; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v9 ; ZVFHMIN-NEXT: vsetvli zero, a0, e32, mf2, ta, ma -; ZVFHMIN-NEXT: vfadd.vv v9, v9, v8, v0.t +; ZVFHMIN-NEXT: vfadd.vv v9, v10, v8, v0.t ; ZVFHMIN-NEXT: vsetvli a0, zero, e16, mf4, ta, ma ; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v9 ; ZVFHMIN-NEXT: ret @@ -88,15 +86,13 @@ define @vfadd_vf_nxv1f16_commute( %va, ha ; ; ZVFHMIN-LABEL: vfadd_vf_nxv1f16_commute: ; ZVFHMIN: # %bb.0: -; ZVFHMIN-NEXT: fcvt.s.h fa5, fa0 -; ZVFHMIN-NEXT: vsetvli a1, zero, e32, mf2, ta, ma -; ZVFHMIN-NEXT: vfmv.v.f v9, fa5 -; ZVFHMIN-NEXT: vsetvli zero, zero, e16, mf4, ta, ma -; ZVFHMIN-NEXT: vfncvt.f.f.w v10, v9 -; ZVFHMIN-NEXT: vfwcvt.f.f.v v9, v8 -; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v10 +; ZVFHMIN-NEXT: fmv.x.h a1, fa0 +; ZVFHMIN-NEXT: vsetvli a2, zero, e16, mf4, ta, ma +; ZVFHMIN-NEXT: vmv.v.x v9, a1 +; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v8 +; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v9 ; ZVFHMIN-NEXT: vsetvli zero, a0, e32, mf2, ta, ma -; ZVFHMIN-NEXT: vfadd.vv v9, v8, v9, v0.t +; ZVFHMIN-NEXT: vfadd.vv v9, v8, v10, v0.t ; ZVFHMIN-NEXT: vsetvli a0, zero, e16, mf4, ta, ma ; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v9 ; ZVFHMIN-NEXT: ret @@ -115,15 +111,13 @@ define @vfadd_vf_nxv1f16_unmasked( %va, h ; ; ZVFHMIN-LABEL: vfadd_vf_nxv1f16_unmasked: ; ZVFHMIN: # %bb.0: -; ZVFHMIN-NEXT: fcvt.s.h fa5, fa0 -; ZVFHMIN-NEXT: vsetvli a1, zero, e32, mf2, ta, ma -; ZVFHMIN-NEXT: vfmv.v.f v9, fa5 -; ZVFHMIN-NEXT: vsetvli zero, zero, e16, mf4, ta, ma -; ZVFHMIN-NEXT: vfncvt.f.f.w v10, v9 -; ZVFHMIN-NEXT: vfwcvt.f.f.v v9, v8 -; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v10 +; ZVFHMIN-NEXT: fmv.x.h a1, fa0 +; ZVFHMIN-NEXT: vsetvli a2, zero, e16, mf4, ta, ma +; ZVFHMIN-NEXT: vmv.v.x v9, a1 +; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v8 +; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v9 ; ZVFHMIN-NEXT: vsetvli zero, a0, e32, mf2, ta, ma -; ZVFHMIN-NEXT: vfadd.vv v9, v9, v8 +; ZVFHMIN-NEXT: vfadd.vv v9, v10, v8 ; ZVFHMIN-NEXT: vsetvli a0, zero, e16, mf4, ta, ma ; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v9 ; ZVFHMIN-NEXT: ret @@ -142,15 +136,13 @@ define @vfadd_vf_nxv1f16_unmasked_commute( @vfadd_vf_nxv2f16( %va, half %b, < ; ; ZVFHMIN-LABEL: vfadd_vf_nxv2f16: ; ZVFHMIN: # %bb.0: -; ZVFHMIN-NEXT: fcvt.s.h fa5, fa0 -; ZVFHMIN-NEXT: vsetvli a1, zero, e32, m1, ta, ma -; ZVFHMIN-NEXT: vfmv.v.f v9, fa5 -; ZVFHMIN-NEXT: vsetvli zero, zero, e16, mf2, ta, ma -; ZVFHMIN-NEXT: vfncvt.f.f.w v10, v9 -; ZVFHMIN-NEXT: vfwcvt.f.f.v v9, v8 -; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v10 +; ZVFHMIN-NEXT: fmv.x.h a1, fa0 +; ZVFHMIN-NEXT: vsetvli a2, zero, e16, mf2, ta, ma +; ZVFHMIN-NEXT: vmv.v.x v9, a1 +; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v8 +; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v9 ; ZVFHMIN-NEXT: vsetvli zero, a0, e32, m1, ta, ma -; ZVFHMIN-NEXT: vfadd.vv v9, v9, v8, v0.t +; ZVFHMIN-NEXT: vfadd.vv v9, v10, v8, v0.t ; ZVFHMIN-NEXT: vsetvli a0, zero, e16, mf2, ta, ma ; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v9 ; ZVFHMIN-NEXT: ret @@ -240,15 +230,13 @@ define @vfadd_vf_nxv2f16_unmasked( %va, h ; ; ZVFHMIN-LABEL: vfadd_vf_nxv2f16_unmasked: ; ZVFHMIN: # %bb.0: -; ZVFHMIN-NEXT: fcvt.s.h fa5, fa0 -; ZVFHMIN-NEXT: vsetvli a1, zero, e32, m1, ta, ma -; ZVFHMIN-NEXT: vfmv.v.f v9, fa5 -; ZVFHMIN-NEXT: vsetvli zero, zero, e16, mf2, ta, ma -; ZVFHMIN-NEXT: vfncvt.f.f.w v10, v9 -; ZVFHMIN-NEXT: vfwcvt.f.f.v v9, v8 -; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v10 +; ZVFHMIN-NEXT: fmv.x.h a1, fa0 +; ZVFHMIN-NEXT: vsetvli a2, zero, e16, mf2, ta, ma +; ZVFHMIN-NEXT: vmv.v.x v9, a1 +; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v8 +; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v9 ; ZVFHMIN-NEXT: vsetvli zero, a0, e32, m1, ta, ma -; ZVFHMIN-NEXT: vfadd.vv v9, v9, v8 +; ZVFHMIN-NEXT: vfadd.vv v9, v10, v8 ; ZVFHMIN-NEXT: vsetvli a0, zero, e16, mf2, ta, ma ; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v9 ; ZVFHMIN-NEXT: ret @@ -311,11 +299,9 @@ define @vfadd_vf_nxv4f16( %va, half %b, < ; ; ZVFHMIN-LABEL: vfadd_vf_nxv4f16: ; ZVFHMIN: # %bb.0: -; ZVFHMIN-NEXT: fcvt.s.h fa5, fa0 -; ZVFHMIN-NEXT: vsetvli a1, zero, e32, m2, ta, ma -; ZVFHMIN-NEXT: vfmv.v.f v10, fa5 -; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m1, ta, ma -; ZVFHMIN-NEXT: vfncvt.f.f.w v9, v10 +; ZVFHMIN-NEXT: fmv.x.h a1, fa0 +; ZVFHMIN-NEXT: vsetvli a2, zero, e16, m1, ta, ma +; ZVFHMIN-NEXT: vmv.v.x v9, a1 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v8 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v9 ; ZVFHMIN-NEXT: vsetvli zero, a0, e32, m2, ta, ma @@ -338,11 +324,9 @@ define @vfadd_vf_nxv4f16_unmasked( %va, h ; ; ZVFHMIN-LABEL: vfadd_vf_nxv4f16_unmasked: ; ZVFHMIN: # %bb.0: -; ZVFHMIN-NEXT: fcvt.s.h fa5, fa0 -; ZVFHMIN-NEXT: vsetvli a1, zero, e32, m2, ta, ma -; ZVFHMIN-NEXT: vfmv.v.f v10, fa5 -; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m1, ta, ma -; ZVFHMIN-NEXT: vfncvt.f.f.w v9, v10 +; ZVFHMIN-NEXT: fmv.x.h a1, fa0 +; ZVFHMIN-NEXT: vsetvli a2, zero, e16, m1, ta, ma +; ZVFHMIN-NEXT: vmv.v.x v9, a1 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v8 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v9 ; ZVFHMIN-NEXT: vsetvli zero, a0, e32, m2, ta, ma @@ -409,11 +393,9 @@ define @vfadd_vf_nxv8f16( %va, half %b, < ; ; ZVFHMIN-LABEL: vfadd_vf_nxv8f16: ; ZVFHMIN: # %bb.0: -; ZVFHMIN-NEXT: fcvt.s.h fa5, fa0 -; ZVFHMIN-NEXT: vsetvli a1, zero, e32, m4, ta, ma -; ZVFHMIN-NEXT: vfmv.v.f v12, fa5 -; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m2, ta, ma -; ZVFHMIN-NEXT: vfncvt.f.f.w v10, v12 +; ZVFHMIN-NEXT: fmv.x.h a1, fa0 +; ZVFHMIN-NEXT: vsetvli a2, zero, e16, m2, ta, ma +; ZVFHMIN-NEXT: vmv.v.x v10, a1 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v8 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v10 ; ZVFHMIN-NEXT: vsetvli zero, a0, e32, m4, ta, ma @@ -436,11 +418,9 @@ define @vfadd_vf_nxv8f16_unmasked( %va, h ; ; ZVFHMIN-LABEL: vfadd_vf_nxv8f16_unmasked: ; ZVFHMIN: # %bb.0: -; ZVFHMIN-NEXT: fcvt.s.h fa5, fa0 -; ZVFHMIN-NEXT: vsetvli a1, zero, e32, m4, ta, ma -; ZVFHMIN-NEXT: vfmv.v.f v12, fa5 -; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m2, ta, ma -; ZVFHMIN-NEXT: vfncvt.f.f.w v10, v12 +; ZVFHMIN-NEXT: fmv.x.h a1, fa0 +; ZVFHMIN-NEXT: vsetvli a2, zero, e16, m2, ta, ma +; ZVFHMIN-NEXT: vmv.v.x v10, a1 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v8 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v10 ; ZVFHMIN-NEXT: vsetvli zero, a0, e32, m4, ta, ma @@ -507,11 +487,9 @@ define @vfadd_vf_nxv16f16( %va, half %b ; ; ZVFHMIN-LABEL: vfadd_vf_nxv16f16: ; ZVFHMIN: # %bb.0: -; ZVFHMIN-NEXT: fcvt.s.h fa5, fa0 -; ZVFHMIN-NEXT: vsetvli a1, zero, e32, m8, ta, ma -; ZVFHMIN-NEXT: vfmv.v.f v16, fa5 -; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m4, ta, ma -; ZVFHMIN-NEXT: vfncvt.f.f.w v12, v16 +; ZVFHMIN-NEXT: fmv.x.h a1, fa0 +; ZVFHMIN-NEXT: vsetvli a2, zero, e16, m4, ta, ma +; ZVFHMIN-NEXT: vmv.v.x v12, a1 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v8 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v24, v12 ; ZVFHMIN-NEXT: vsetvli zero, a0, e32, m8, ta, ma @@ -534,11 +512,9 @@ define @vfadd_vf_nxv16f16_unmasked( %va ; ; ZVFHMIN-LABEL: vfadd_vf_nxv16f16_unmasked: ; ZVFHMIN: # %bb.0: -; ZVFHMIN-NEXT: fcvt.s.h fa5, fa0 -; ZVFHMIN-NEXT: vsetvli a1, zero, e32, m8, ta, ma -; ZVFHMIN-NEXT: vfmv.v.f v16, fa5 -; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m4, ta, ma -; ZVFHMIN-NEXT: vfncvt.f.f.w v12, v16 +; ZVFHMIN-NEXT: fmv.x.h a1, fa0 +; ZVFHMIN-NEXT: vsetvli a2, zero, e16, m4, ta, ma +; ZVFHMIN-NEXT: vmv.v.x v12, a1 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v8 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v24, v12 ; ZVFHMIN-NEXT: vsetvli zero, a0, e32, m8, ta, ma @@ -678,17 +654,22 @@ define @vfadd_vf_nxv32f16( %va, half %b ; ZVFHMIN-NEXT: addi sp, sp, -16 ; ZVFHMIN-NEXT: .cfi_def_cfa_offset 16 ; ZVFHMIN-NEXT: csrr a1, vlenb -; ZVFHMIN-NEXT: slli a1, a1, 2 +; ZVFHMIN-NEXT: slli a1, a1, 1 +; ZVFHMIN-NEXT: mv a2, a1 +; ZVFHMIN-NEXT: slli a1, a1, 3 +; ZVFHMIN-NEXT: add a1, a1, a2 ; ZVFHMIN-NEXT: sub sp, sp, a1 -; ZVFHMIN-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x04, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 4 * vlenb -; ZVFHMIN-NEXT: vmv1r.v v7, v0 -; ZVFHMIN-NEXT: fcvt.s.h fa5, fa0 -; ZVFHMIN-NEXT: vsetvli a1, zero, e32, m8, ta, ma -; ZVFHMIN-NEXT: vfmv.v.f v24, fa5 -; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m4, ta, ma -; ZVFHMIN-NEXT: vfncvt.f.f.w v16, v24 -; ZVFHMIN-NEXT: addi a1, sp, 16 -; ZVFHMIN-NEXT: vs4r.v v16, (a1) # Unknown-size Folded Spill +; ZVFHMIN-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x12, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 18 * vlenb +; ZVFHMIN-NEXT: vmv8r.v v24, v8 +; ZVFHMIN-NEXT: fmv.x.h a1, fa0 +; ZVFHMIN-NEXT: vsetvli a2, zero, e16, m8, ta, ma +; ZVFHMIN-NEXT: vmv.v.x v16, a1 +; ZVFHMIN-NEXT: csrr a1, vlenb +; ZVFHMIN-NEXT: slli a2, a1, 3 +; ZVFHMIN-NEXT: add a1, a2, a1 +; ZVFHMIN-NEXT: add a1, sp, a1 +; ZVFHMIN-NEXT: addi a1, a1, 16 +; ZVFHMIN-NEXT: vs8r.v v16, (a1) # Unknown-size Folded Spill ; ZVFHMIN-NEXT: csrr a2, vlenb ; ZVFHMIN-NEXT: slli a1, a2, 1 ; ZVFHMIN-NEXT: sub a3, a0, a1 @@ -696,29 +677,56 @@ define @vfadd_vf_nxv32f16( %va, half %b ; ZVFHMIN-NEXT: addi a4, a4, -1 ; ZVFHMIN-NEXT: and a3, a4, a3 ; ZVFHMIN-NEXT: srli a2, a2, 2 +; ZVFHMIN-NEXT: csrr a4, vlenb +; ZVFHMIN-NEXT: slli a4, a4, 3 +; ZVFHMIN-NEXT: add a4, sp, a4 +; ZVFHMIN-NEXT: addi a4, a4, 16 +; ZVFHMIN-NEXT: vs1r.v v0, (a4) # Unknown-size Folded Spill ; ZVFHMIN-NEXT: vsetvli a4, zero, e8, mf2, ta, ma ; ZVFHMIN-NEXT: vslidedown.vx v0, v0, a2 -; ZVFHMIN-NEXT: vsetvli a2, zero, e16, m4, ta, ma -; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v12 ; ZVFHMIN-NEXT: addi a2, sp, 16 -; ZVFHMIN-NEXT: vl4r.v v12, (a2) # Unknown-size Folded Reload -; ZVFHMIN-NEXT: vfwcvt.f.f.v v24, v12 +; ZVFHMIN-NEXT: vs8r.v v8, (a2) # Unknown-size Folded Spill +; ZVFHMIN-NEXT: vsetvli a2, zero, e16, m4, ta, ma +; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v28 +; ZVFHMIN-NEXT: csrr a2, vlenb +; ZVFHMIN-NEXT: slli a4, a2, 3 +; ZVFHMIN-NEXT: add a2, a4, a2 +; ZVFHMIN-NEXT: add a2, sp, a2 +; ZVFHMIN-NEXT: addi a2, a2, 16 +; ZVFHMIN-NEXT: vl8r.v v24, (a2) # Unknown-size Folded Reload +; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v28 ; ZVFHMIN-NEXT: vsetvli zero, a3, e32, m8, ta, ma -; ZVFHMIN-NEXT: vfadd.vv v16, v16, v24, v0.t +; ZVFHMIN-NEXT: vfadd.vv v16, v8, v16, v0.t ; ZVFHMIN-NEXT: vsetvli a2, zero, e16, m4, ta, ma ; ZVFHMIN-NEXT: vfncvt.f.f.w v12, v16 ; ZVFHMIN-NEXT: bltu a0, a1, .LBB24_2 ; ZVFHMIN-NEXT: # %bb.1: ; ZVFHMIN-NEXT: mv a0, a1 ; ZVFHMIN-NEXT: .LBB24_2: -; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v8 -; ZVFHMIN-NEXT: vmv1r.v v0, v7 +; ZVFHMIN-NEXT: addi a1, sp, 16 +; ZVFHMIN-NEXT: vl8r.v v24, (a1) # Unknown-size Folded Reload +; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v24 +; ZVFHMIN-NEXT: csrr a1, vlenb +; ZVFHMIN-NEXT: slli a2, a1, 3 +; ZVFHMIN-NEXT: add a1, a2, a1 +; ZVFHMIN-NEXT: add a1, sp, a1 +; ZVFHMIN-NEXT: addi a1, a1, 16 +; ZVFHMIN-NEXT: vl8r.v v0, (a1) # Unknown-size Folded Reload +; ZVFHMIN-NEXT: vfwcvt.f.f.v v24, v0 +; ZVFHMIN-NEXT: csrr a1, vlenb +; ZVFHMIN-NEXT: slli a1, a1, 3 +; ZVFHMIN-NEXT: add a1, sp, a1 +; ZVFHMIN-NEXT: addi a1, a1, 16 +; ZVFHMIN-NEXT: vl1r.v v0, (a1) # Unknown-size Folded Reload ; ZVFHMIN-NEXT: vsetvli zero, a0, e32, m8, ta, ma ; ZVFHMIN-NEXT: vfadd.vv v16, v16, v24, v0.t ; ZVFHMIN-NEXT: vsetvli a0, zero, e16, m4, ta, ma ; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v16 ; ZVFHMIN-NEXT: csrr a0, vlenb -; ZVFHMIN-NEXT: slli a0, a0, 2 +; ZVFHMIN-NEXT: slli a0, a0, 1 +; ZVFHMIN-NEXT: mv a1, a0 +; ZVFHMIN-NEXT: slli a0, a0, 3 +; ZVFHMIN-NEXT: add a0, a0, a1 ; ZVFHMIN-NEXT: add sp, sp, a0 ; ZVFHMIN-NEXT: addi sp, sp, 16 ; ZVFHMIN-NEXT: ret @@ -737,11 +745,16 @@ define @vfadd_vf_nxv32f16_unmasked( %va ; ; ZVFHMIN-LABEL: vfadd_vf_nxv32f16_unmasked: ; ZVFHMIN: # %bb.0: -; ZVFHMIN-NEXT: fcvt.s.h fa5, fa0 -; ZVFHMIN-NEXT: vsetvli a1, zero, e32, m8, ta, ma -; ZVFHMIN-NEXT: vfmv.v.f v16, fa5 -; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m4, ta, ma -; ZVFHMIN-NEXT: vfncvt.f.f.w v4, v16 +; ZVFHMIN-NEXT: addi sp, sp, -16 +; ZVFHMIN-NEXT: .cfi_def_cfa_offset 16 +; ZVFHMIN-NEXT: csrr a1, vlenb +; ZVFHMIN-NEXT: slli a1, a1, 4 +; ZVFHMIN-NEXT: sub sp, sp, a1 +; ZVFHMIN-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x10, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 16 * vlenb +; ZVFHMIN-NEXT: vmv8r.v v16, v8 +; ZVFHMIN-NEXT: fmv.x.h a1, fa0 +; ZVFHMIN-NEXT: vsetvli a2, zero, e16, m8, ta, ma +; ZVFHMIN-NEXT: vmv.v.x v8, a1 ; ZVFHMIN-NEXT: csrr a2, vlenb ; ZVFHMIN-NEXT: slli a1, a2, 1 ; ZVFHMIN-NEXT: sub a3, a0, a1 @@ -749,26 +762,45 @@ define @vfadd_vf_nxv32f16_unmasked( %va ; ZVFHMIN-NEXT: addi a4, a4, -1 ; ZVFHMIN-NEXT: and a3, a4, a3 ; ZVFHMIN-NEXT: srli a2, a2, 2 -; ZVFHMIN-NEXT: vsetvli a4, zero, e8, m4, ta, ma -; ZVFHMIN-NEXT: vmset.m v16 +; ZVFHMIN-NEXT: vmset.m v24 ; ZVFHMIN-NEXT: vsetvli a4, zero, e8, mf2, ta, ma -; ZVFHMIN-NEXT: vslidedown.vx v0, v16, a2 +; ZVFHMIN-NEXT: vslidedown.vx v0, v24, a2 +; ZVFHMIN-NEXT: addi a2, sp, 16 +; ZVFHMIN-NEXT: vs8r.v v16, (a2) # Unknown-size Folded Spill ; ZVFHMIN-NEXT: vsetvli a2, zero, e16, m4, ta, ma -; ZVFHMIN-NEXT: vfwcvt.f.f.v v24, v12 -; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v4 +; ZVFHMIN-NEXT: vfwcvt.f.f.v v24, v20 +; ZVFHMIN-NEXT: vmv4r.v v16, v8 +; ZVFHMIN-NEXT: csrr a2, vlenb +; ZVFHMIN-NEXT: slli a2, a2, 3 +; ZVFHMIN-NEXT: add a2, sp, a2 +; ZVFHMIN-NEXT: addi a2, a2, 16 +; ZVFHMIN-NEXT: vs8r.v v16, (a2) # Unknown-size Folded Spill +; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v12 ; ZVFHMIN-NEXT: vsetvli zero, a3, e32, m8, ta, ma -; ZVFHMIN-NEXT: vfadd.vv v24, v24, v16, v0.t +; ZVFHMIN-NEXT: vfadd.vv v16, v24, v16, v0.t ; ZVFHMIN-NEXT: vsetvli a2, zero, e16, m4, ta, ma -; ZVFHMIN-NEXT: vfncvt.f.f.w v12, v24 +; ZVFHMIN-NEXT: vfncvt.f.f.w v12, v16 ; ZVFHMIN-NEXT: bltu a0, a1, .LBB25_2 ; ZVFHMIN-NEXT: # %bb.1: ; ZVFHMIN-NEXT: mv a0, a1 ; ZVFHMIN-NEXT: .LBB25_2: -; ZVFHMIN-NEXT: vfwcvt.f.f.v v24, v8 +; ZVFHMIN-NEXT: addi a1, sp, 16 +; ZVFHMIN-NEXT: vl8r.v v24, (a1) # Unknown-size Folded Reload +; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v24 +; ZVFHMIN-NEXT: csrr a1, vlenb +; ZVFHMIN-NEXT: slli a1, a1, 3 +; ZVFHMIN-NEXT: add a1, sp, a1 +; ZVFHMIN-NEXT: addi a1, a1, 16 +; ZVFHMIN-NEXT: vl8r.v v0, (a1) # Unknown-size Folded Reload +; ZVFHMIN-NEXT: vfwcvt.f.f.v v24, v0 ; ZVFHMIN-NEXT: vsetvli zero, a0, e32, m8, ta, ma -; ZVFHMIN-NEXT: vfadd.vv v16, v24, v16 +; ZVFHMIN-NEXT: vfadd.vv v16, v16, v24 ; ZVFHMIN-NEXT: vsetvli a0, zero, e16, m4, ta, ma ; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v16 +; ZVFHMIN-NEXT: csrr a0, vlenb +; ZVFHMIN-NEXT: slli a0, a0, 4 +; ZVFHMIN-NEXT: add sp, sp, a0 +; ZVFHMIN-NEXT: addi sp, sp, 16 ; ZVFHMIN-NEXT: ret %elt.head = insertelement poison, half %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer diff --git a/llvm/test/CodeGen/RISCV/rvv/vfcopysign-sdnode.ll b/llvm/test/CodeGen/RISCV/rvv/vfcopysign-sdnode.ll index c71c07488581a9..f37e593798efe5 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vfcopysign-sdnode.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vfcopysign-sdnode.ll @@ -39,15 +39,13 @@ define @vfcopysign_vf_nxv1f16( %vm, half ; ; ZVFHMIN-LABEL: vfcopysign_vf_nxv1f16: ; ZVFHMIN: # %bb.0: -; ZVFHMIN-NEXT: fcvt.s.h fa5, fa0 -; ZVFHMIN-NEXT: vsetvli a0, zero, e32, mf2, ta, ma -; ZVFHMIN-NEXT: vfmv.v.f v9, fa5 -; ZVFHMIN-NEXT: vsetvli zero, zero, e16, mf4, ta, ma -; ZVFHMIN-NEXT: vfncvt.f.f.w v10, v9 +; ZVFHMIN-NEXT: fmv.x.h a0, fa0 +; ZVFHMIN-NEXT: vsetvli a1, zero, e16, mf4, ta, ma +; ZVFHMIN-NEXT: vmv.v.x v9, a0 ; ZVFHMIN-NEXT: lui a0, 8 ; ZVFHMIN-NEXT: addi a1, a0, -1 ; ZVFHMIN-NEXT: vand.vx v8, v8, a1 -; ZVFHMIN-NEXT: vand.vx v9, v10, a0 +; ZVFHMIN-NEXT: vand.vx v9, v9, a0 ; ZVFHMIN-NEXT: vor.vv v8, v8, v9 ; ZVFHMIN-NEXT: ret %head = insertelement poison, half %s, i32 0 @@ -87,13 +85,11 @@ define @vfcopynsign_vf_nxv1f16( %vm, half ; ; ZVFHMIN-LABEL: vfcopynsign_vf_nxv1f16: ; ZVFHMIN: # %bb.0: -; ZVFHMIN-NEXT: fcvt.s.h fa5, fa0 -; ZVFHMIN-NEXT: vsetvli a0, zero, e32, mf2, ta, ma -; ZVFHMIN-NEXT: vfmv.v.f v9, fa5 -; ZVFHMIN-NEXT: vsetvli zero, zero, e16, mf4, ta, ma -; ZVFHMIN-NEXT: vfncvt.f.f.w v10, v9 +; ZVFHMIN-NEXT: fmv.x.h a0, fa0 +; ZVFHMIN-NEXT: vsetvli a1, zero, e16, mf4, ta, ma +; ZVFHMIN-NEXT: vmv.v.x v9, a0 ; ZVFHMIN-NEXT: lui a0, 8 -; ZVFHMIN-NEXT: vxor.vx v9, v10, a0 +; ZVFHMIN-NEXT: vxor.vx v9, v9, a0 ; ZVFHMIN-NEXT: addi a1, a0, -1 ; ZVFHMIN-NEXT: vand.vx v8, v8, a1 ; ZVFHMIN-NEXT: vand.vx v9, v9, a0 @@ -371,15 +367,13 @@ define @vfcopysign_vf_nxv2f16( %vm, half ; ; ZVFHMIN-LABEL: vfcopysign_vf_nxv2f16: ; ZVFHMIN: # %bb.0: -; ZVFHMIN-NEXT: fcvt.s.h fa5, fa0 -; ZVFHMIN-NEXT: vsetvli a0, zero, e32, m1, ta, ma -; ZVFHMIN-NEXT: vfmv.v.f v9, fa5 -; ZVFHMIN-NEXT: vsetvli zero, zero, e16, mf2, ta, ma -; ZVFHMIN-NEXT: vfncvt.f.f.w v10, v9 +; ZVFHMIN-NEXT: fmv.x.h a0, fa0 +; ZVFHMIN-NEXT: vsetvli a1, zero, e16, mf2, ta, ma +; ZVFHMIN-NEXT: vmv.v.x v9, a0 ; ZVFHMIN-NEXT: lui a0, 8 ; ZVFHMIN-NEXT: addi a1, a0, -1 ; ZVFHMIN-NEXT: vand.vx v8, v8, a1 -; ZVFHMIN-NEXT: vand.vx v9, v10, a0 +; ZVFHMIN-NEXT: vand.vx v9, v9, a0 ; ZVFHMIN-NEXT: vor.vv v8, v8, v9 ; ZVFHMIN-NEXT: ret %head = insertelement poison, half %s, i32 0 @@ -419,13 +413,11 @@ define @vfcopynsign_vf_nxv2f16( %vm, half ; ; ZVFHMIN-LABEL: vfcopynsign_vf_nxv2f16: ; ZVFHMIN: # %bb.0: -; ZVFHMIN-NEXT: fcvt.s.h fa5, fa0 -; ZVFHMIN-NEXT: vsetvli a0, zero, e32, m1, ta, ma -; ZVFHMIN-NEXT: vfmv.v.f v9, fa5 -; ZVFHMIN-NEXT: vsetvli zero, zero, e16, mf2, ta, ma -; ZVFHMIN-NEXT: vfncvt.f.f.w v10, v9 +; ZVFHMIN-NEXT: fmv.x.h a0, fa0 +; ZVFHMIN-NEXT: vsetvli a1, zero, e16, mf2, ta, ma +; ZVFHMIN-NEXT: vmv.v.x v9, a0 ; ZVFHMIN-NEXT: lui a0, 8 -; ZVFHMIN-NEXT: vxor.vx v9, v10, a0 +; ZVFHMIN-NEXT: vxor.vx v9, v9, a0 ; ZVFHMIN-NEXT: addi a1, a0, -1 ; ZVFHMIN-NEXT: vand.vx v8, v8, a1 ; ZVFHMIN-NEXT: vand.vx v9, v9, a0 @@ -469,11 +461,9 @@ define @vfcopysign_vf_nxv4f16( %vm, half ; ; ZVFHMIN-LABEL: vfcopysign_vf_nxv4f16: ; ZVFHMIN: # %bb.0: -; ZVFHMIN-NEXT: fcvt.s.h fa5, fa0 -; ZVFHMIN-NEXT: vsetvli a0, zero, e32, m2, ta, ma -; ZVFHMIN-NEXT: vfmv.v.f v10, fa5 -; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m1, ta, ma -; ZVFHMIN-NEXT: vfncvt.f.f.w v9, v10 +; ZVFHMIN-NEXT: fmv.x.h a0, fa0 +; ZVFHMIN-NEXT: vsetvli a1, zero, e16, m1, ta, ma +; ZVFHMIN-NEXT: vmv.v.x v9, a0 ; ZVFHMIN-NEXT: lui a0, 8 ; ZVFHMIN-NEXT: addi a1, a0, -1 ; ZVFHMIN-NEXT: vand.vx v8, v8, a1 @@ -517,11 +507,9 @@ define @vfcopynsign_vf_nxv4f16( %vm, half ; ; ZVFHMIN-LABEL: vfcopynsign_vf_nxv4f16: ; ZVFHMIN: # %bb.0: -; ZVFHMIN-NEXT: fcvt.s.h fa5, fa0 -; ZVFHMIN-NEXT: vsetvli a0, zero, e32, m2, ta, ma -; ZVFHMIN-NEXT: vfmv.v.f v10, fa5 -; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m1, ta, ma -; ZVFHMIN-NEXT: vfncvt.f.f.w v9, v10 +; ZVFHMIN-NEXT: fmv.x.h a0, fa0 +; ZVFHMIN-NEXT: vsetvli a1, zero, e16, m1, ta, ma +; ZVFHMIN-NEXT: vmv.v.x v9, a0 ; ZVFHMIN-NEXT: lui a0, 8 ; ZVFHMIN-NEXT: vxor.vx v9, v9, a0 ; ZVFHMIN-NEXT: addi a1, a0, -1 @@ -567,11 +555,9 @@ define @vfcopysign_vf_nxv8f16( %vm, half ; ; ZVFHMIN-LABEL: vfcopysign_vf_nxv8f16: ; ZVFHMIN: # %bb.0: -; ZVFHMIN-NEXT: fcvt.s.h fa5, fa0 -; ZVFHMIN-NEXT: vsetvli a0, zero, e32, m4, ta, ma -; ZVFHMIN-NEXT: vfmv.v.f v12, fa5 -; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m2, ta, ma -; ZVFHMIN-NEXT: vfncvt.f.f.w v10, v12 +; ZVFHMIN-NEXT: fmv.x.h a0, fa0 +; ZVFHMIN-NEXT: vsetvli a1, zero, e16, m2, ta, ma +; ZVFHMIN-NEXT: vmv.v.x v10, a0 ; ZVFHMIN-NEXT: lui a0, 8 ; ZVFHMIN-NEXT: addi a1, a0, -1 ; ZVFHMIN-NEXT: vand.vx v8, v8, a1 @@ -615,11 +601,9 @@ define @vfcopynsign_vf_nxv8f16( %vm, half ; ; ZVFHMIN-LABEL: vfcopynsign_vf_nxv8f16: ; ZVFHMIN: # %bb.0: -; ZVFHMIN-NEXT: fcvt.s.h fa5, fa0 -; ZVFHMIN-NEXT: vsetvli a0, zero, e32, m4, ta, ma -; ZVFHMIN-NEXT: vfmv.v.f v12, fa5 -; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m2, ta, ma -; ZVFHMIN-NEXT: vfncvt.f.f.w v10, v12 +; ZVFHMIN-NEXT: fmv.x.h a0, fa0 +; ZVFHMIN-NEXT: vsetvli a1, zero, e16, m2, ta, ma +; ZVFHMIN-NEXT: vmv.v.x v10, a0 ; ZVFHMIN-NEXT: lui a0, 8 ; ZVFHMIN-NEXT: vxor.vx v10, v10, a0 ; ZVFHMIN-NEXT: addi a1, a0, -1 @@ -899,11 +883,9 @@ define @vfcopysign_vf_nxv16f16( %vm, ha ; ; ZVFHMIN-LABEL: vfcopysign_vf_nxv16f16: ; ZVFHMIN: # %bb.0: -; ZVFHMIN-NEXT: fcvt.s.h fa5, fa0 -; ZVFHMIN-NEXT: vsetvli a0, zero, e32, m8, ta, ma -; ZVFHMIN-NEXT: vfmv.v.f v16, fa5 -; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m4, ta, ma -; ZVFHMIN-NEXT: vfncvt.f.f.w v12, v16 +; ZVFHMIN-NEXT: fmv.x.h a0, fa0 +; ZVFHMIN-NEXT: vsetvli a1, zero, e16, m4, ta, ma +; ZVFHMIN-NEXT: vmv.v.x v12, a0 ; ZVFHMIN-NEXT: lui a0, 8 ; ZVFHMIN-NEXT: addi a1, a0, -1 ; ZVFHMIN-NEXT: vand.vx v8, v8, a1 @@ -947,11 +929,9 @@ define @vfcopynsign_vf_nxv16f16( %vm, h ; ; ZVFHMIN-LABEL: vfcopynsign_vf_nxv16f16: ; ZVFHMIN: # %bb.0: -; ZVFHMIN-NEXT: fcvt.s.h fa5, fa0 -; ZVFHMIN-NEXT: vsetvli a0, zero, e32, m8, ta, ma -; ZVFHMIN-NEXT: vfmv.v.f v16, fa5 -; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m4, ta, ma -; ZVFHMIN-NEXT: vfncvt.f.f.w v12, v16 +; ZVFHMIN-NEXT: fmv.x.h a0, fa0 +; ZVFHMIN-NEXT: vsetvli a1, zero, e16, m4, ta, ma +; ZVFHMIN-NEXT: vmv.v.x v12, a0 ; ZVFHMIN-NEXT: lui a0, 8 ; ZVFHMIN-NEXT: vxor.vx v12, v12, a0 ; ZVFHMIN-NEXT: addi a1, a0, -1 @@ -997,17 +977,13 @@ define @vfcopysign_vf_nxv32f16( %vm, ha ; ; ZVFHMIN-LABEL: vfcopysign_vf_nxv32f16: ; ZVFHMIN: # %bb.0: -; ZVFHMIN-NEXT: fcvt.s.h fa5, fa0 -; ZVFHMIN-NEXT: vsetvli a0, zero, e32, m8, ta, ma -; ZVFHMIN-NEXT: vfmv.v.f v16, fa5 -; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m4, ta, ma -; ZVFHMIN-NEXT: vfncvt.f.f.w v24, v16 -; ZVFHMIN-NEXT: vmv.v.v v28, v24 +; ZVFHMIN-NEXT: fmv.x.h a0, fa0 +; ZVFHMIN-NEXT: vsetvli a1, zero, e16, m8, ta, ma +; ZVFHMIN-NEXT: vmv.v.x v16, a0 ; ZVFHMIN-NEXT: lui a0, 8 ; ZVFHMIN-NEXT: addi a1, a0, -1 -; ZVFHMIN-NEXT: vsetvli a2, zero, e16, m8, ta, ma ; ZVFHMIN-NEXT: vand.vx v8, v8, a1 -; ZVFHMIN-NEXT: vand.vx v16, v24, a0 +; ZVFHMIN-NEXT: vand.vx v16, v16, a0 ; ZVFHMIN-NEXT: vor.vv v8, v8, v16 ; ZVFHMIN-NEXT: ret %head = insertelement poison, half %s, i32 0 @@ -1047,15 +1023,11 @@ define @vfcopynsign_vf_nxv32f16( %vm, h ; ; ZVFHMIN-LABEL: vfcopynsign_vf_nxv32f16: ; ZVFHMIN: # %bb.0: -; ZVFHMIN-NEXT: fcvt.s.h fa5, fa0 -; ZVFHMIN-NEXT: vsetvli a0, zero, e32, m8, ta, ma -; ZVFHMIN-NEXT: vfmv.v.f v16, fa5 -; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m4, ta, ma -; ZVFHMIN-NEXT: vfncvt.f.f.w v24, v16 -; ZVFHMIN-NEXT: vmv.v.v v28, v24 -; ZVFHMIN-NEXT: lui a0, 8 +; ZVFHMIN-NEXT: fmv.x.h a0, fa0 ; ZVFHMIN-NEXT: vsetvli a1, zero, e16, m8, ta, ma -; ZVFHMIN-NEXT: vxor.vx v16, v24, a0 +; ZVFHMIN-NEXT: vmv.v.x v16, a0 +; ZVFHMIN-NEXT: lui a0, 8 +; ZVFHMIN-NEXT: vxor.vx v16, v16, a0 ; ZVFHMIN-NEXT: addi a1, a0, -1 ; ZVFHMIN-NEXT: vand.vx v8, v8, a1 ; ZVFHMIN-NEXT: vand.vx v16, v16, a0 diff --git a/llvm/test/CodeGen/RISCV/rvv/vfdiv-constrained-sdnode.ll b/llvm/test/CodeGen/RISCV/rvv/vfdiv-constrained-sdnode.ll index bd5f81341bf3d5..69095a0b21bb09 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vfdiv-constrained-sdnode.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vfdiv-constrained-sdnode.ll @@ -40,15 +40,13 @@ define @vfdiv_vf_nxv1f16( %va, half %b) s ; ; ZVFHMIN-LABEL: vfdiv_vf_nxv1f16: ; ZVFHMIN: # %bb.0: -; ZVFHMIN-NEXT: fcvt.s.h fa5, fa0 -; ZVFHMIN-NEXT: vsetvli a0, zero, e32, mf2, ta, ma -; ZVFHMIN-NEXT: vfmv.v.f v9, fa5 -; ZVFHMIN-NEXT: vsetvli zero, zero, e16, mf4, ta, ma -; ZVFHMIN-NEXT: vfncvt.f.f.w v10, v9 -; ZVFHMIN-NEXT: vfwcvt.f.f.v v9, v8 -; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v10 +; ZVFHMIN-NEXT: fmv.x.h a0, fa0 +; ZVFHMIN-NEXT: vsetvli a1, zero, e16, mf4, ta, ma +; ZVFHMIN-NEXT: vmv.v.x v9, a0 +; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v8 +; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v9 ; ZVFHMIN-NEXT: vsetvli zero, zero, e32, mf2, ta, ma -; ZVFHMIN-NEXT: vfdiv.vv v9, v9, v8 +; ZVFHMIN-NEXT: vfdiv.vv v9, v10, v8 ; ZVFHMIN-NEXT: vsetvli zero, zero, e16, mf4, ta, ma ; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v9 ; ZVFHMIN-NEXT: ret @@ -90,15 +88,13 @@ define @vfdiv_vf_nxv2f16( %va, half %b) s ; ; ZVFHMIN-LABEL: vfdiv_vf_nxv2f16: ; ZVFHMIN: # %bb.0: -; ZVFHMIN-NEXT: fcvt.s.h fa5, fa0 -; ZVFHMIN-NEXT: vsetvli a0, zero, e32, m1, ta, ma -; ZVFHMIN-NEXT: vfmv.v.f v9, fa5 -; ZVFHMIN-NEXT: vsetvli zero, zero, e16, mf2, ta, ma -; ZVFHMIN-NEXT: vfncvt.f.f.w v10, v9 -; ZVFHMIN-NEXT: vfwcvt.f.f.v v9, v8 -; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v10 +; ZVFHMIN-NEXT: fmv.x.h a0, fa0 +; ZVFHMIN-NEXT: vsetvli a1, zero, e16, mf2, ta, ma +; ZVFHMIN-NEXT: vmv.v.x v9, a0 +; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v8 +; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v9 ; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m1, ta, ma -; ZVFHMIN-NEXT: vfdiv.vv v9, v9, v8 +; ZVFHMIN-NEXT: vfdiv.vv v9, v10, v8 ; ZVFHMIN-NEXT: vsetvli zero, zero, e16, mf2, ta, ma ; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v9 ; ZVFHMIN-NEXT: ret @@ -140,11 +136,9 @@ define @vfdiv_vf_nxv4f16( %va, half %b) s ; ; ZVFHMIN-LABEL: vfdiv_vf_nxv4f16: ; ZVFHMIN: # %bb.0: -; ZVFHMIN-NEXT: fcvt.s.h fa5, fa0 -; ZVFHMIN-NEXT: vsetvli a0, zero, e32, m2, ta, ma -; ZVFHMIN-NEXT: vfmv.v.f v10, fa5 -; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m1, ta, ma -; ZVFHMIN-NEXT: vfncvt.f.f.w v9, v10 +; ZVFHMIN-NEXT: fmv.x.h a0, fa0 +; ZVFHMIN-NEXT: vsetvli a1, zero, e16, m1, ta, ma +; ZVFHMIN-NEXT: vmv.v.x v9, a0 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v8 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v9 ; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m2, ta, ma @@ -190,11 +184,9 @@ define @vfdiv_vf_nxv8f16( %va, half %b) s ; ; ZVFHMIN-LABEL: vfdiv_vf_nxv8f16: ; ZVFHMIN: # %bb.0: -; ZVFHMIN-NEXT: fcvt.s.h fa5, fa0 -; ZVFHMIN-NEXT: vsetvli a0, zero, e32, m4, ta, ma -; ZVFHMIN-NEXT: vfmv.v.f v12, fa5 -; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m2, ta, ma -; ZVFHMIN-NEXT: vfncvt.f.f.w v10, v12 +; ZVFHMIN-NEXT: fmv.x.h a0, fa0 +; ZVFHMIN-NEXT: vsetvli a1, zero, e16, m2, ta, ma +; ZVFHMIN-NEXT: vmv.v.x v10, a0 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v8 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v10 ; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m4, ta, ma @@ -217,11 +209,9 @@ define @vfdiv_fv_nxv8f16( %va, half %b) s ; ; ZVFHMIN-LABEL: vfdiv_fv_nxv8f16: ; ZVFHMIN: # %bb.0: -; ZVFHMIN-NEXT: fcvt.s.h fa5, fa0 -; ZVFHMIN-NEXT: vsetvli a0, zero, e32, m4, ta, ma -; ZVFHMIN-NEXT: vfmv.v.f v12, fa5 -; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m2, ta, ma -; ZVFHMIN-NEXT: vfncvt.f.f.w v10, v12 +; ZVFHMIN-NEXT: fmv.x.h a0, fa0 +; ZVFHMIN-NEXT: vsetvli a1, zero, e16, m2, ta, ma +; ZVFHMIN-NEXT: vmv.v.x v10, a0 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v8 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v10 ; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m4, ta, ma @@ -267,11 +257,9 @@ define @vfdiv_vf_nxv16f16( %va, half %b ; ; ZVFHMIN-LABEL: vfdiv_vf_nxv16f16: ; ZVFHMIN: # %bb.0: -; ZVFHMIN-NEXT: fcvt.s.h fa5, fa0 -; ZVFHMIN-NEXT: vsetvli a0, zero, e32, m8, ta, ma -; ZVFHMIN-NEXT: vfmv.v.f v16, fa5 -; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m4, ta, ma -; ZVFHMIN-NEXT: vfncvt.f.f.w v12, v16 +; ZVFHMIN-NEXT: fmv.x.h a0, fa0 +; ZVFHMIN-NEXT: vsetvli a1, zero, e16, m4, ta, ma +; ZVFHMIN-NEXT: vmv.v.x v12, a0 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v8 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v24, v12 ; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma @@ -323,21 +311,20 @@ define @vfdiv_vf_nxv32f16( %va, half %b ; ; ZVFHMIN-LABEL: vfdiv_vf_nxv32f16: ; ZVFHMIN: # %bb.0: -; ZVFHMIN-NEXT: fcvt.s.h fa5, fa0 -; ZVFHMIN-NEXT: vsetvli a0, zero, e32, m8, ta, ma -; ZVFHMIN-NEXT: vfmv.v.f v16, fa5 -; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m4, ta, ma -; ZVFHMIN-NEXT: vfncvt.f.f.w v24, v16 -; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v8 -; ZVFHMIN-NEXT: vfwcvt.f.f.v v0, v24 +; ZVFHMIN-NEXT: fmv.x.h a0, fa0 +; ZVFHMIN-NEXT: vsetvli a1, zero, e16, m8, ta, ma +; ZVFHMIN-NEXT: vmv.v.x v16, a0 +; ZVFHMIN-NEXT: vsetvli a0, zero, e16, m4, ta, ma +; ZVFHMIN-NEXT: vfwcvt.f.f.v v24, v8 +; ZVFHMIN-NEXT: vfwcvt.f.f.v v0, v16 ; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma -; ZVFHMIN-NEXT: vfdiv.vv v16, v16, v0 +; ZVFHMIN-NEXT: vfdiv.vv v24, v24, v0 ; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m4, ta, ma -; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v16 -; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v24 -; ZVFHMIN-NEXT: vfwcvt.f.f.v v24, v12 +; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v24 +; ZVFHMIN-NEXT: vfwcvt.f.f.v v24, v20 +; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v12 ; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma -; ZVFHMIN-NEXT: vfdiv.vv v16, v24, v16 +; ZVFHMIN-NEXT: vfdiv.vv v16, v16, v24 ; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m4, ta, ma ; ZVFHMIN-NEXT: vfncvt.f.f.w v12, v16 ; ZVFHMIN-NEXT: ret diff --git a/llvm/test/CodeGen/RISCV/rvv/vfdiv-sdnode.ll b/llvm/test/CodeGen/RISCV/rvv/vfdiv-sdnode.ll index 7d1d9ec1680c1a..9f5434dd34727d 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vfdiv-sdnode.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vfdiv-sdnode.ll @@ -38,15 +38,13 @@ define @vfdiv_vf_nxv1f16( %va, half %b) { ; ; ZVFHMIN-LABEL: vfdiv_vf_nxv1f16: ; ZVFHMIN: # %bb.0: -; ZVFHMIN-NEXT: fcvt.s.h fa5, fa0 -; ZVFHMIN-NEXT: vsetvli a0, zero, e32, mf2, ta, ma -; ZVFHMIN-NEXT: vfmv.v.f v9, fa5 -; ZVFHMIN-NEXT: vsetvli zero, zero, e16, mf4, ta, ma -; ZVFHMIN-NEXT: vfncvt.f.f.w v10, v9 -; ZVFHMIN-NEXT: vfwcvt.f.f.v v9, v8 -; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v10 +; ZVFHMIN-NEXT: fmv.x.h a0, fa0 +; ZVFHMIN-NEXT: vsetvli a1, zero, e16, mf4, ta, ma +; ZVFHMIN-NEXT: vmv.v.x v9, a0 +; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v8 +; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v9 ; ZVFHMIN-NEXT: vsetvli zero, zero, e32, mf2, ta, ma -; ZVFHMIN-NEXT: vfdiv.vv v9, v9, v8 +; ZVFHMIN-NEXT: vfdiv.vv v9, v10, v8 ; ZVFHMIN-NEXT: vsetvli zero, zero, e16, mf4, ta, ma ; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v9 ; ZVFHMIN-NEXT: ret @@ -86,15 +84,13 @@ define @vfdiv_vf_nxv2f16( %va, half %b) { ; ; ZVFHMIN-LABEL: vfdiv_vf_nxv2f16: ; ZVFHMIN: # %bb.0: -; ZVFHMIN-NEXT: fcvt.s.h fa5, fa0 -; ZVFHMIN-NEXT: vsetvli a0, zero, e32, m1, ta, ma -; ZVFHMIN-NEXT: vfmv.v.f v9, fa5 -; ZVFHMIN-NEXT: vsetvli zero, zero, e16, mf2, ta, ma -; ZVFHMIN-NEXT: vfncvt.f.f.w v10, v9 -; ZVFHMIN-NEXT: vfwcvt.f.f.v v9, v8 -; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v10 +; ZVFHMIN-NEXT: fmv.x.h a0, fa0 +; ZVFHMIN-NEXT: vsetvli a1, zero, e16, mf2, ta, ma +; ZVFHMIN-NEXT: vmv.v.x v9, a0 +; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v8 +; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v9 ; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m1, ta, ma -; ZVFHMIN-NEXT: vfdiv.vv v9, v9, v8 +; ZVFHMIN-NEXT: vfdiv.vv v9, v10, v8 ; ZVFHMIN-NEXT: vsetvli zero, zero, e16, mf2, ta, ma ; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v9 ; ZVFHMIN-NEXT: ret @@ -134,11 +130,9 @@ define @vfdiv_vf_nxv4f16( %va, half %b) { ; ; ZVFHMIN-LABEL: vfdiv_vf_nxv4f16: ; ZVFHMIN: # %bb.0: -; ZVFHMIN-NEXT: fcvt.s.h fa5, fa0 -; ZVFHMIN-NEXT: vsetvli a0, zero, e32, m2, ta, ma -; ZVFHMIN-NEXT: vfmv.v.f v10, fa5 -; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m1, ta, ma -; ZVFHMIN-NEXT: vfncvt.f.f.w v9, v10 +; ZVFHMIN-NEXT: fmv.x.h a0, fa0 +; ZVFHMIN-NEXT: vsetvli a1, zero, e16, m1, ta, ma +; ZVFHMIN-NEXT: vmv.v.x v9, a0 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v8 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v9 ; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m2, ta, ma @@ -182,11 +176,9 @@ define @vfdiv_vf_nxv8f16( %va, half %b) { ; ; ZVFHMIN-LABEL: vfdiv_vf_nxv8f16: ; ZVFHMIN: # %bb.0: -; ZVFHMIN-NEXT: fcvt.s.h fa5, fa0 -; ZVFHMIN-NEXT: vsetvli a0, zero, e32, m4, ta, ma -; ZVFHMIN-NEXT: vfmv.v.f v12, fa5 -; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m2, ta, ma -; ZVFHMIN-NEXT: vfncvt.f.f.w v10, v12 +; ZVFHMIN-NEXT: fmv.x.h a0, fa0 +; ZVFHMIN-NEXT: vsetvli a1, zero, e16, m2, ta, ma +; ZVFHMIN-NEXT: vmv.v.x v10, a0 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v8 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v10 ; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m4, ta, ma @@ -209,11 +201,9 @@ define @vfdiv_fv_nxv8f16( %va, half %b) { ; ; ZVFHMIN-LABEL: vfdiv_fv_nxv8f16: ; ZVFHMIN: # %bb.0: -; ZVFHMIN-NEXT: fcvt.s.h fa5, fa0 -; ZVFHMIN-NEXT: vsetvli a0, zero, e32, m4, ta, ma -; ZVFHMIN-NEXT: vfmv.v.f v12, fa5 -; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m2, ta, ma -; ZVFHMIN-NEXT: vfncvt.f.f.w v10, v12 +; ZVFHMIN-NEXT: fmv.x.h a0, fa0 +; ZVFHMIN-NEXT: vsetvli a1, zero, e16, m2, ta, ma +; ZVFHMIN-NEXT: vmv.v.x v10, a0 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v8 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v10 ; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m4, ta, ma @@ -257,11 +247,9 @@ define @vfdiv_vf_nxv16f16( %va, half %b ; ; ZVFHMIN-LABEL: vfdiv_vf_nxv16f16: ; ZVFHMIN: # %bb.0: -; ZVFHMIN-NEXT: fcvt.s.h fa5, fa0 -; ZVFHMIN-NEXT: vsetvli a0, zero, e32, m8, ta, ma -; ZVFHMIN-NEXT: vfmv.v.f v16, fa5 -; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m4, ta, ma -; ZVFHMIN-NEXT: vfncvt.f.f.w v12, v16 +; ZVFHMIN-NEXT: fmv.x.h a0, fa0 +; ZVFHMIN-NEXT: vsetvli a1, zero, e16, m4, ta, ma +; ZVFHMIN-NEXT: vmv.v.x v12, a0 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v8 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v24, v12 ; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma @@ -311,20 +299,20 @@ define @vfdiv_vf_nxv32f16( %va, half %b ; ; ZVFHMIN-LABEL: vfdiv_vf_nxv32f16: ; ZVFHMIN: # %bb.0: -; ZVFHMIN-NEXT: fcvt.s.h fa5, fa0 -; ZVFHMIN-NEXT: vsetvli a0, zero, e32, m8, ta, ma -; ZVFHMIN-NEXT: vfmv.v.f v16, fa5 -; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m4, ta, ma -; ZVFHMIN-NEXT: vfncvt.f.f.w v24, v16 -; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v8 -; ZVFHMIN-NEXT: vfwcvt.f.f.v v0, v24 +; ZVFHMIN-NEXT: fmv.x.h a0, fa0 +; ZVFHMIN-NEXT: vsetvli a1, zero, e16, m8, ta, ma +; ZVFHMIN-NEXT: vmv.v.x v16, a0 +; ZVFHMIN-NEXT: vsetvli a0, zero, e16, m4, ta, ma +; ZVFHMIN-NEXT: vfwcvt.f.f.v v24, v8 +; ZVFHMIN-NEXT: vfwcvt.f.f.v v0, v16 ; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma -; ZVFHMIN-NEXT: vfdiv.vv v16, v16, v0 +; ZVFHMIN-NEXT: vfdiv.vv v24, v24, v0 ; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m4, ta, ma -; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v16 -; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v12 +; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v24 +; ZVFHMIN-NEXT: vfwcvt.f.f.v v24, v12 +; ZVFHMIN-NEXT: vfwcvt.f.f.v v0, v20 ; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma -; ZVFHMIN-NEXT: vfdiv.vv v16, v16, v0 +; ZVFHMIN-NEXT: vfdiv.vv v16, v24, v0 ; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m4, ta, ma ; ZVFHMIN-NEXT: vfncvt.f.f.w v12, v16 ; ZVFHMIN-NEXT: ret diff --git a/llvm/test/CodeGen/RISCV/rvv/vfdiv-vp.ll b/llvm/test/CodeGen/RISCV/rvv/vfdiv-vp.ll index 81d844d1950ab2..52e2a9535ef603 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vfdiv-vp.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vfdiv-vp.ll @@ -61,15 +61,13 @@ define @vfdiv_vf_nxv1f16( %va, half %b, < ; ; ZVFHMIN-LABEL: vfdiv_vf_nxv1f16: ; ZVFHMIN: # %bb.0: -; ZVFHMIN-NEXT: fcvt.s.h fa5, fa0 -; ZVFHMIN-NEXT: vsetvli a1, zero, e32, mf2, ta, ma -; ZVFHMIN-NEXT: vfmv.v.f v9, fa5 -; ZVFHMIN-NEXT: vsetvli zero, zero, e16, mf4, ta, ma -; ZVFHMIN-NEXT: vfncvt.f.f.w v10, v9 -; ZVFHMIN-NEXT: vfwcvt.f.f.v v9, v8 -; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v10 +; ZVFHMIN-NEXT: fmv.x.h a1, fa0 +; ZVFHMIN-NEXT: vsetvli a2, zero, e16, mf4, ta, ma +; ZVFHMIN-NEXT: vmv.v.x v9, a1 +; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v8 +; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v9 ; ZVFHMIN-NEXT: vsetvli zero, a0, e32, mf2, ta, ma -; ZVFHMIN-NEXT: vfdiv.vv v9, v9, v8, v0.t +; ZVFHMIN-NEXT: vfdiv.vv v9, v10, v8, v0.t ; ZVFHMIN-NEXT: vsetvli a0, zero, e16, mf4, ta, ma ; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v9 ; ZVFHMIN-NEXT: ret @@ -88,15 +86,13 @@ define @vfdiv_vf_nxv1f16_unmasked( %va, h ; ; ZVFHMIN-LABEL: vfdiv_vf_nxv1f16_unmasked: ; ZVFHMIN: # %bb.0: -; ZVFHMIN-NEXT: fcvt.s.h fa5, fa0 -; ZVFHMIN-NEXT: vsetvli a1, zero, e32, mf2, ta, ma -; ZVFHMIN-NEXT: vfmv.v.f v9, fa5 -; ZVFHMIN-NEXT: vsetvli zero, zero, e16, mf4, ta, ma -; ZVFHMIN-NEXT: vfncvt.f.f.w v10, v9 -; ZVFHMIN-NEXT: vfwcvt.f.f.v v9, v8 -; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v10 +; ZVFHMIN-NEXT: fmv.x.h a1, fa0 +; ZVFHMIN-NEXT: vsetvli a2, zero, e16, mf4, ta, ma +; ZVFHMIN-NEXT: vmv.v.x v9, a1 +; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v8 +; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v9 ; ZVFHMIN-NEXT: vsetvli zero, a0, e32, mf2, ta, ma -; ZVFHMIN-NEXT: vfdiv.vv v9, v9, v8 +; ZVFHMIN-NEXT: vfdiv.vv v9, v10, v8 ; ZVFHMIN-NEXT: vsetvli a0, zero, e16, mf4, ta, ma ; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v9 ; ZVFHMIN-NEXT: ret @@ -159,15 +155,13 @@ define @vfdiv_vf_nxv2f16( %va, half %b, < ; ; ZVFHMIN-LABEL: vfdiv_vf_nxv2f16: ; ZVFHMIN: # %bb.0: -; ZVFHMIN-NEXT: fcvt.s.h fa5, fa0 -; ZVFHMIN-NEXT: vsetvli a1, zero, e32, m1, ta, ma -; ZVFHMIN-NEXT: vfmv.v.f v9, fa5 -; ZVFHMIN-NEXT: vsetvli zero, zero, e16, mf2, ta, ma -; ZVFHMIN-NEXT: vfncvt.f.f.w v10, v9 -; ZVFHMIN-NEXT: vfwcvt.f.f.v v9, v8 -; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v10 +; ZVFHMIN-NEXT: fmv.x.h a1, fa0 +; ZVFHMIN-NEXT: vsetvli a2, zero, e16, mf2, ta, ma +; ZVFHMIN-NEXT: vmv.v.x v9, a1 +; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v8 +; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v9 ; ZVFHMIN-NEXT: vsetvli zero, a0, e32, m1, ta, ma -; ZVFHMIN-NEXT: vfdiv.vv v9, v9, v8, v0.t +; ZVFHMIN-NEXT: vfdiv.vv v9, v10, v8, v0.t ; ZVFHMIN-NEXT: vsetvli a0, zero, e16, mf2, ta, ma ; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v9 ; ZVFHMIN-NEXT: ret @@ -186,15 +180,13 @@ define @vfdiv_vf_nxv2f16_unmasked( %va, h ; ; ZVFHMIN-LABEL: vfdiv_vf_nxv2f16_unmasked: ; ZVFHMIN: # %bb.0: -; ZVFHMIN-NEXT: fcvt.s.h fa5, fa0 -; ZVFHMIN-NEXT: vsetvli a1, zero, e32, m1, ta, ma -; ZVFHMIN-NEXT: vfmv.v.f v9, fa5 -; ZVFHMIN-NEXT: vsetvli zero, zero, e16, mf2, ta, ma -; ZVFHMIN-NEXT: vfncvt.f.f.w v10, v9 -; ZVFHMIN-NEXT: vfwcvt.f.f.v v9, v8 -; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v10 +; ZVFHMIN-NEXT: fmv.x.h a1, fa0 +; ZVFHMIN-NEXT: vsetvli a2, zero, e16, mf2, ta, ma +; ZVFHMIN-NEXT: vmv.v.x v9, a1 +; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v8 +; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v9 ; ZVFHMIN-NEXT: vsetvli zero, a0, e32, m1, ta, ma -; ZVFHMIN-NEXT: vfdiv.vv v9, v9, v8 +; ZVFHMIN-NEXT: vfdiv.vv v9, v10, v8 ; ZVFHMIN-NEXT: vsetvli a0, zero, e16, mf2, ta, ma ; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v9 ; ZVFHMIN-NEXT: ret @@ -257,11 +249,9 @@ define @vfdiv_vf_nxv4f16( %va, half %b, < ; ; ZVFHMIN-LABEL: vfdiv_vf_nxv4f16: ; ZVFHMIN: # %bb.0: -; ZVFHMIN-NEXT: fcvt.s.h fa5, fa0 -; ZVFHMIN-NEXT: vsetvli a1, zero, e32, m2, ta, ma -; ZVFHMIN-NEXT: vfmv.v.f v10, fa5 -; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m1, ta, ma -; ZVFHMIN-NEXT: vfncvt.f.f.w v9, v10 +; ZVFHMIN-NEXT: fmv.x.h a1, fa0 +; ZVFHMIN-NEXT: vsetvli a2, zero, e16, m1, ta, ma +; ZVFHMIN-NEXT: vmv.v.x v9, a1 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v8 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v9 ; ZVFHMIN-NEXT: vsetvli zero, a0, e32, m2, ta, ma @@ -284,11 +274,9 @@ define @vfdiv_vf_nxv4f16_unmasked( %va, h ; ; ZVFHMIN-LABEL: vfdiv_vf_nxv4f16_unmasked: ; ZVFHMIN: # %bb.0: -; ZVFHMIN-NEXT: fcvt.s.h fa5, fa0 -; ZVFHMIN-NEXT: vsetvli a1, zero, e32, m2, ta, ma -; ZVFHMIN-NEXT: vfmv.v.f v10, fa5 -; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m1, ta, ma -; ZVFHMIN-NEXT: vfncvt.f.f.w v9, v10 +; ZVFHMIN-NEXT: fmv.x.h a1, fa0 +; ZVFHMIN-NEXT: vsetvli a2, zero, e16, m1, ta, ma +; ZVFHMIN-NEXT: vmv.v.x v9, a1 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v8 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v9 ; ZVFHMIN-NEXT: vsetvli zero, a0, e32, m2, ta, ma @@ -355,11 +343,9 @@ define @vfdiv_vf_nxv8f16( %va, half %b, < ; ; ZVFHMIN-LABEL: vfdiv_vf_nxv8f16: ; ZVFHMIN: # %bb.0: -; ZVFHMIN-NEXT: fcvt.s.h fa5, fa0 -; ZVFHMIN-NEXT: vsetvli a1, zero, e32, m4, ta, ma -; ZVFHMIN-NEXT: vfmv.v.f v12, fa5 -; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m2, ta, ma -; ZVFHMIN-NEXT: vfncvt.f.f.w v10, v12 +; ZVFHMIN-NEXT: fmv.x.h a1, fa0 +; ZVFHMIN-NEXT: vsetvli a2, zero, e16, m2, ta, ma +; ZVFHMIN-NEXT: vmv.v.x v10, a1 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v8 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v10 ; ZVFHMIN-NEXT: vsetvli zero, a0, e32, m4, ta, ma @@ -382,11 +368,9 @@ define @vfdiv_vf_nxv8f16_unmasked( %va, h ; ; ZVFHMIN-LABEL: vfdiv_vf_nxv8f16_unmasked: ; ZVFHMIN: # %bb.0: -; ZVFHMIN-NEXT: fcvt.s.h fa5, fa0 -; ZVFHMIN-NEXT: vsetvli a1, zero, e32, m4, ta, ma -; ZVFHMIN-NEXT: vfmv.v.f v12, fa5 -; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m2, ta, ma -; ZVFHMIN-NEXT: vfncvt.f.f.w v10, v12 +; ZVFHMIN-NEXT: fmv.x.h a1, fa0 +; ZVFHMIN-NEXT: vsetvli a2, zero, e16, m2, ta, ma +; ZVFHMIN-NEXT: vmv.v.x v10, a1 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v8 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v10 ; ZVFHMIN-NEXT: vsetvli zero, a0, e32, m4, ta, ma @@ -453,11 +437,9 @@ define @vfdiv_vf_nxv16f16( %va, half %b ; ; ZVFHMIN-LABEL: vfdiv_vf_nxv16f16: ; ZVFHMIN: # %bb.0: -; ZVFHMIN-NEXT: fcvt.s.h fa5, fa0 -; ZVFHMIN-NEXT: vsetvli a1, zero, e32, m8, ta, ma -; ZVFHMIN-NEXT: vfmv.v.f v16, fa5 -; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m4, ta, ma -; ZVFHMIN-NEXT: vfncvt.f.f.w v12, v16 +; ZVFHMIN-NEXT: fmv.x.h a1, fa0 +; ZVFHMIN-NEXT: vsetvli a2, zero, e16, m4, ta, ma +; ZVFHMIN-NEXT: vmv.v.x v12, a1 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v8 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v24, v12 ; ZVFHMIN-NEXT: vsetvli zero, a0, e32, m8, ta, ma @@ -480,11 +462,9 @@ define @vfdiv_vf_nxv16f16_unmasked( %va ; ; ZVFHMIN-LABEL: vfdiv_vf_nxv16f16_unmasked: ; ZVFHMIN: # %bb.0: -; ZVFHMIN-NEXT: fcvt.s.h fa5, fa0 -; ZVFHMIN-NEXT: vsetvli a1, zero, e32, m8, ta, ma -; ZVFHMIN-NEXT: vfmv.v.f v16, fa5 -; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m4, ta, ma -; ZVFHMIN-NEXT: vfncvt.f.f.w v12, v16 +; ZVFHMIN-NEXT: fmv.x.h a1, fa0 +; ZVFHMIN-NEXT: vsetvli a2, zero, e16, m4, ta, ma +; ZVFHMIN-NEXT: vmv.v.x v12, a1 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v8 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v24, v12 ; ZVFHMIN-NEXT: vsetvli zero, a0, e32, m8, ta, ma @@ -624,17 +604,22 @@ define @vfdiv_vf_nxv32f16( %va, half %b ; ZVFHMIN-NEXT: addi sp, sp, -16 ; ZVFHMIN-NEXT: .cfi_def_cfa_offset 16 ; ZVFHMIN-NEXT: csrr a1, vlenb -; ZVFHMIN-NEXT: slli a1, a1, 2 +; ZVFHMIN-NEXT: slli a1, a1, 1 +; ZVFHMIN-NEXT: mv a2, a1 +; ZVFHMIN-NEXT: slli a1, a1, 3 +; ZVFHMIN-NEXT: add a1, a1, a2 ; ZVFHMIN-NEXT: sub sp, sp, a1 -; ZVFHMIN-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x04, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 4 * vlenb -; ZVFHMIN-NEXT: vmv1r.v v7, v0 -; ZVFHMIN-NEXT: fcvt.s.h fa5, fa0 -; ZVFHMIN-NEXT: vsetvli a1, zero, e32, m8, ta, ma -; ZVFHMIN-NEXT: vfmv.v.f v24, fa5 -; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m4, ta, ma -; ZVFHMIN-NEXT: vfncvt.f.f.w v16, v24 -; ZVFHMIN-NEXT: addi a1, sp, 16 -; ZVFHMIN-NEXT: vs4r.v v16, (a1) # Unknown-size Folded Spill +; ZVFHMIN-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x12, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 18 * vlenb +; ZVFHMIN-NEXT: vmv8r.v v24, v8 +; ZVFHMIN-NEXT: fmv.x.h a1, fa0 +; ZVFHMIN-NEXT: vsetvli a2, zero, e16, m8, ta, ma +; ZVFHMIN-NEXT: vmv.v.x v16, a1 +; ZVFHMIN-NEXT: csrr a1, vlenb +; ZVFHMIN-NEXT: slli a2, a1, 3 +; ZVFHMIN-NEXT: add a1, a2, a1 +; ZVFHMIN-NEXT: add a1, sp, a1 +; ZVFHMIN-NEXT: addi a1, a1, 16 +; ZVFHMIN-NEXT: vs8r.v v16, (a1) # Unknown-size Folded Spill ; ZVFHMIN-NEXT: csrr a2, vlenb ; ZVFHMIN-NEXT: slli a1, a2, 1 ; ZVFHMIN-NEXT: sub a3, a0, a1 @@ -642,29 +627,56 @@ define @vfdiv_vf_nxv32f16( %va, half %b ; ZVFHMIN-NEXT: addi a4, a4, -1 ; ZVFHMIN-NEXT: and a3, a4, a3 ; ZVFHMIN-NEXT: srli a2, a2, 2 +; ZVFHMIN-NEXT: csrr a4, vlenb +; ZVFHMIN-NEXT: slli a4, a4, 3 +; ZVFHMIN-NEXT: add a4, sp, a4 +; ZVFHMIN-NEXT: addi a4, a4, 16 +; ZVFHMIN-NEXT: vs1r.v v0, (a4) # Unknown-size Folded Spill ; ZVFHMIN-NEXT: vsetvli a4, zero, e8, mf2, ta, ma ; ZVFHMIN-NEXT: vslidedown.vx v0, v0, a2 -; ZVFHMIN-NEXT: vsetvli a2, zero, e16, m4, ta, ma -; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v12 ; ZVFHMIN-NEXT: addi a2, sp, 16 -; ZVFHMIN-NEXT: vl4r.v v12, (a2) # Unknown-size Folded Reload -; ZVFHMIN-NEXT: vfwcvt.f.f.v v24, v12 +; ZVFHMIN-NEXT: vs8r.v v8, (a2) # Unknown-size Folded Spill +; ZVFHMIN-NEXT: vsetvli a2, zero, e16, m4, ta, ma +; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v28 +; ZVFHMIN-NEXT: csrr a2, vlenb +; ZVFHMIN-NEXT: slli a4, a2, 3 +; ZVFHMIN-NEXT: add a2, a4, a2 +; ZVFHMIN-NEXT: add a2, sp, a2 +; ZVFHMIN-NEXT: addi a2, a2, 16 +; ZVFHMIN-NEXT: vl8r.v v24, (a2) # Unknown-size Folded Reload +; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v28 ; ZVFHMIN-NEXT: vsetvli zero, a3, e32, m8, ta, ma -; ZVFHMIN-NEXT: vfdiv.vv v16, v16, v24, v0.t +; ZVFHMIN-NEXT: vfdiv.vv v16, v8, v16, v0.t ; ZVFHMIN-NEXT: vsetvli a2, zero, e16, m4, ta, ma ; ZVFHMIN-NEXT: vfncvt.f.f.w v12, v16 ; ZVFHMIN-NEXT: bltu a0, a1, .LBB22_2 ; ZVFHMIN-NEXT: # %bb.1: ; ZVFHMIN-NEXT: mv a0, a1 ; ZVFHMIN-NEXT: .LBB22_2: -; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v8 -; ZVFHMIN-NEXT: vmv1r.v v0, v7 +; ZVFHMIN-NEXT: addi a1, sp, 16 +; ZVFHMIN-NEXT: vl8r.v v24, (a1) # Unknown-size Folded Reload +; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v24 +; ZVFHMIN-NEXT: csrr a1, vlenb +; ZVFHMIN-NEXT: slli a2, a1, 3 +; ZVFHMIN-NEXT: add a1, a2, a1 +; ZVFHMIN-NEXT: add a1, sp, a1 +; ZVFHMIN-NEXT: addi a1, a1, 16 +; ZVFHMIN-NEXT: vl8r.v v0, (a1) # Unknown-size Folded Reload +; ZVFHMIN-NEXT: vfwcvt.f.f.v v24, v0 +; ZVFHMIN-NEXT: csrr a1, vlenb +; ZVFHMIN-NEXT: slli a1, a1, 3 +; ZVFHMIN-NEXT: add a1, sp, a1 +; ZVFHMIN-NEXT: addi a1, a1, 16 +; ZVFHMIN-NEXT: vl1r.v v0, (a1) # Unknown-size Folded Reload ; ZVFHMIN-NEXT: vsetvli zero, a0, e32, m8, ta, ma ; ZVFHMIN-NEXT: vfdiv.vv v16, v16, v24, v0.t ; ZVFHMIN-NEXT: vsetvli a0, zero, e16, m4, ta, ma ; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v16 ; ZVFHMIN-NEXT: csrr a0, vlenb -; ZVFHMIN-NEXT: slli a0, a0, 2 +; ZVFHMIN-NEXT: slli a0, a0, 1 +; ZVFHMIN-NEXT: mv a1, a0 +; ZVFHMIN-NEXT: slli a0, a0, 3 +; ZVFHMIN-NEXT: add a0, a0, a1 ; ZVFHMIN-NEXT: add sp, sp, a0 ; ZVFHMIN-NEXT: addi sp, sp, 16 ; ZVFHMIN-NEXT: ret @@ -683,11 +695,16 @@ define @vfdiv_vf_nxv32f16_unmasked( %va ; ; ZVFHMIN-LABEL: vfdiv_vf_nxv32f16_unmasked: ; ZVFHMIN: # %bb.0: -; ZVFHMIN-NEXT: fcvt.s.h fa5, fa0 -; ZVFHMIN-NEXT: vsetvli a1, zero, e32, m8, ta, ma -; ZVFHMIN-NEXT: vfmv.v.f v16, fa5 -; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m4, ta, ma -; ZVFHMIN-NEXT: vfncvt.f.f.w v4, v16 +; ZVFHMIN-NEXT: addi sp, sp, -16 +; ZVFHMIN-NEXT: .cfi_def_cfa_offset 16 +; ZVFHMIN-NEXT: csrr a1, vlenb +; ZVFHMIN-NEXT: slli a1, a1, 4 +; ZVFHMIN-NEXT: sub sp, sp, a1 +; ZVFHMIN-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x10, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 16 * vlenb +; ZVFHMIN-NEXT: vmv8r.v v16, v8 +; ZVFHMIN-NEXT: fmv.x.h a1, fa0 +; ZVFHMIN-NEXT: vsetvli a2, zero, e16, m8, ta, ma +; ZVFHMIN-NEXT: vmv.v.x v8, a1 ; ZVFHMIN-NEXT: csrr a2, vlenb ; ZVFHMIN-NEXT: slli a1, a2, 1 ; ZVFHMIN-NEXT: sub a3, a0, a1 @@ -695,26 +712,45 @@ define @vfdiv_vf_nxv32f16_unmasked( %va ; ZVFHMIN-NEXT: addi a4, a4, -1 ; ZVFHMIN-NEXT: and a3, a4, a3 ; ZVFHMIN-NEXT: srli a2, a2, 2 -; ZVFHMIN-NEXT: vsetvli a4, zero, e8, m4, ta, ma -; ZVFHMIN-NEXT: vmset.m v16 +; ZVFHMIN-NEXT: vmset.m v24 ; ZVFHMIN-NEXT: vsetvli a4, zero, e8, mf2, ta, ma -; ZVFHMIN-NEXT: vslidedown.vx v0, v16, a2 +; ZVFHMIN-NEXT: vslidedown.vx v0, v24, a2 +; ZVFHMIN-NEXT: addi a2, sp, 16 +; ZVFHMIN-NEXT: vs8r.v v16, (a2) # Unknown-size Folded Spill ; ZVFHMIN-NEXT: vsetvli a2, zero, e16, m4, ta, ma -; ZVFHMIN-NEXT: vfwcvt.f.f.v v24, v12 -; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v4 +; ZVFHMIN-NEXT: vfwcvt.f.f.v v24, v20 +; ZVFHMIN-NEXT: vmv4r.v v16, v8 +; ZVFHMIN-NEXT: csrr a2, vlenb +; ZVFHMIN-NEXT: slli a2, a2, 3 +; ZVFHMIN-NEXT: add a2, sp, a2 +; ZVFHMIN-NEXT: addi a2, a2, 16 +; ZVFHMIN-NEXT: vs8r.v v16, (a2) # Unknown-size Folded Spill +; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v12 ; ZVFHMIN-NEXT: vsetvli zero, a3, e32, m8, ta, ma -; ZVFHMIN-NEXT: vfdiv.vv v24, v24, v16, v0.t +; ZVFHMIN-NEXT: vfdiv.vv v16, v24, v16, v0.t ; ZVFHMIN-NEXT: vsetvli a2, zero, e16, m4, ta, ma -; ZVFHMIN-NEXT: vfncvt.f.f.w v12, v24 +; ZVFHMIN-NEXT: vfncvt.f.f.w v12, v16 ; ZVFHMIN-NEXT: bltu a0, a1, .LBB23_2 ; ZVFHMIN-NEXT: # %bb.1: ; ZVFHMIN-NEXT: mv a0, a1 ; ZVFHMIN-NEXT: .LBB23_2: -; ZVFHMIN-NEXT: vfwcvt.f.f.v v24, v8 +; ZVFHMIN-NEXT: addi a1, sp, 16 +; ZVFHMIN-NEXT: vl8r.v v24, (a1) # Unknown-size Folded Reload +; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v24 +; ZVFHMIN-NEXT: csrr a1, vlenb +; ZVFHMIN-NEXT: slli a1, a1, 3 +; ZVFHMIN-NEXT: add a1, sp, a1 +; ZVFHMIN-NEXT: addi a1, a1, 16 +; ZVFHMIN-NEXT: vl8r.v v0, (a1) # Unknown-size Folded Reload +; ZVFHMIN-NEXT: vfwcvt.f.f.v v24, v0 ; ZVFHMIN-NEXT: vsetvli zero, a0, e32, m8, ta, ma -; ZVFHMIN-NEXT: vfdiv.vv v16, v24, v16 +; ZVFHMIN-NEXT: vfdiv.vv v16, v16, v24 ; ZVFHMIN-NEXT: vsetvli a0, zero, e16, m4, ta, ma ; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v16 +; ZVFHMIN-NEXT: csrr a0, vlenb +; ZVFHMIN-NEXT: slli a0, a0, 4 +; ZVFHMIN-NEXT: add sp, sp, a0 +; ZVFHMIN-NEXT: addi sp, sp, 16 ; ZVFHMIN-NEXT: ret %elt.head = insertelement poison, half %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer diff --git a/llvm/test/CodeGen/RISCV/rvv/vfmadd-constrained-sdnode.ll b/llvm/test/CodeGen/RISCV/rvv/vfmadd-constrained-sdnode.ll index c15b875e8f0c4e..52e438013fdbac 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vfmadd-constrained-sdnode.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vfmadd-constrained-sdnode.ll @@ -44,16 +44,14 @@ define @vfmadd_vf_nxv1f16( %va, @vfmadd_vf_nxv2f16( %va, @vfmadd_vf_nxv4f16( %va, @vfmadd_vf_nxv8f16( %va, @vfmadd_vf_nxv16f16( %va, @vfmadd_vf_nxv32f16( %va, @vfmadd_vf_nxv1f16( %va, @vfmadd_vf_nxv2f16( %va, @vfmadd_vf_nxv4f16( %va, @vfmadd_vf_nxv8f16( %va, @vfmadd_vf_nxv16f16( %va, @vfmadd_vf_nxv32f16( %va, @vfmax_nxv1f16_vf( %a, half %b) { ; ; ZVFHMIN-LABEL: vfmax_nxv1f16_vf: ; ZVFHMIN: # %bb.0: -; ZVFHMIN-NEXT: fcvt.s.h fa5, fa0 -; ZVFHMIN-NEXT: vsetvli a0, zero, e32, mf2, ta, ma -; ZVFHMIN-NEXT: vfmv.v.f v9, fa5 -; ZVFHMIN-NEXT: vsetvli zero, zero, e16, mf4, ta, ma -; ZVFHMIN-NEXT: vfncvt.f.f.w v10, v9 -; ZVFHMIN-NEXT: vfwcvt.f.f.v v9, v8 -; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v10 +; ZVFHMIN-NEXT: fmv.x.h a0, fa0 +; ZVFHMIN-NEXT: vsetvli a1, zero, e16, mf4, ta, ma +; ZVFHMIN-NEXT: vmv.v.x v9, a0 +; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v8 +; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v9 ; ZVFHMIN-NEXT: vsetvli zero, zero, e32, mf2, ta, ma -; ZVFHMIN-NEXT: vfmax.vv v9, v9, v8 +; ZVFHMIN-NEXT: vfmax.vv v9, v10, v8 ; ZVFHMIN-NEXT: vsetvli zero, zero, e16, mf4, ta, ma ; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v9 ; ZVFHMIN-NEXT: ret @@ -90,15 +88,13 @@ define @vfmax_nxv2f16_vf( %a, half %b) { ; ; ZVFHMIN-LABEL: vfmax_nxv2f16_vf: ; ZVFHMIN: # %bb.0: -; ZVFHMIN-NEXT: fcvt.s.h fa5, fa0 -; ZVFHMIN-NEXT: vsetvli a0, zero, e32, m1, ta, ma -; ZVFHMIN-NEXT: vfmv.v.f v9, fa5 -; ZVFHMIN-NEXT: vsetvli zero, zero, e16, mf2, ta, ma -; ZVFHMIN-NEXT: vfncvt.f.f.w v10, v9 -; ZVFHMIN-NEXT: vfwcvt.f.f.v v9, v8 -; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v10 +; ZVFHMIN-NEXT: fmv.x.h a0, fa0 +; ZVFHMIN-NEXT: vsetvli a1, zero, e16, mf2, ta, ma +; ZVFHMIN-NEXT: vmv.v.x v9, a0 +; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v8 +; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v9 ; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m1, ta, ma -; ZVFHMIN-NEXT: vfmax.vv v9, v9, v8 +; ZVFHMIN-NEXT: vfmax.vv v9, v10, v8 ; ZVFHMIN-NEXT: vsetvli zero, zero, e16, mf2, ta, ma ; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v9 ; ZVFHMIN-NEXT: ret @@ -140,11 +136,9 @@ define @vfmax_nxv4f16_vf( %a, half %b) { ; ; ZVFHMIN-LABEL: vfmax_nxv4f16_vf: ; ZVFHMIN: # %bb.0: -; ZVFHMIN-NEXT: fcvt.s.h fa5, fa0 -; ZVFHMIN-NEXT: vsetvli a0, zero, e32, m2, ta, ma -; ZVFHMIN-NEXT: vfmv.v.f v10, fa5 -; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m1, ta, ma -; ZVFHMIN-NEXT: vfncvt.f.f.w v9, v10 +; ZVFHMIN-NEXT: fmv.x.h a0, fa0 +; ZVFHMIN-NEXT: vsetvli a1, zero, e16, m1, ta, ma +; ZVFHMIN-NEXT: vmv.v.x v9, a0 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v8 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v9 ; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m2, ta, ma @@ -190,11 +184,9 @@ define @vfmax_nxv8f16_vf( %a, half %b) { ; ; ZVFHMIN-LABEL: vfmax_nxv8f16_vf: ; ZVFHMIN: # %bb.0: -; ZVFHMIN-NEXT: fcvt.s.h fa5, fa0 -; ZVFHMIN-NEXT: vsetvli a0, zero, e32, m4, ta, ma -; ZVFHMIN-NEXT: vfmv.v.f v12, fa5 -; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m2, ta, ma -; ZVFHMIN-NEXT: vfncvt.f.f.w v10, v12 +; ZVFHMIN-NEXT: fmv.x.h a0, fa0 +; ZVFHMIN-NEXT: vsetvli a1, zero, e16, m2, ta, ma +; ZVFHMIN-NEXT: vmv.v.x v10, a0 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v8 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v10 ; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m4, ta, ma @@ -240,11 +232,9 @@ define @vfmax_nxv16f16_vf( %a, half %b) ; ; ZVFHMIN-LABEL: vfmax_nxv16f16_vf: ; ZVFHMIN: # %bb.0: -; ZVFHMIN-NEXT: fcvt.s.h fa5, fa0 -; ZVFHMIN-NEXT: vsetvli a0, zero, e32, m8, ta, ma -; ZVFHMIN-NEXT: vfmv.v.f v16, fa5 -; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m4, ta, ma -; ZVFHMIN-NEXT: vfncvt.f.f.w v12, v16 +; ZVFHMIN-NEXT: fmv.x.h a0, fa0 +; ZVFHMIN-NEXT: vsetvli a1, zero, e16, m4, ta, ma +; ZVFHMIN-NEXT: vmv.v.x v12, a0 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v8 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v24, v12 ; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma @@ -296,20 +286,20 @@ define @vfmax_nxv32f16_vf( %a, half %b) ; ; ZVFHMIN-LABEL: vfmax_nxv32f16_vf: ; ZVFHMIN: # %bb.0: -; ZVFHMIN-NEXT: fcvt.s.h fa5, fa0 -; ZVFHMIN-NEXT: vsetvli a0, zero, e32, m8, ta, ma -; ZVFHMIN-NEXT: vfmv.v.f v16, fa5 -; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m4, ta, ma -; ZVFHMIN-NEXT: vfncvt.f.f.w v24, v16 -; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v8 -; ZVFHMIN-NEXT: vfwcvt.f.f.v v0, v24 +; ZVFHMIN-NEXT: fmv.x.h a0, fa0 +; ZVFHMIN-NEXT: vsetvli a1, zero, e16, m8, ta, ma +; ZVFHMIN-NEXT: vmv.v.x v16, a0 +; ZVFHMIN-NEXT: vsetvli a0, zero, e16, m4, ta, ma +; ZVFHMIN-NEXT: vfwcvt.f.f.v v24, v8 +; ZVFHMIN-NEXT: vfwcvt.f.f.v v0, v16 ; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma -; ZVFHMIN-NEXT: vfmax.vv v16, v16, v0 +; ZVFHMIN-NEXT: vfmax.vv v24, v24, v0 ; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m4, ta, ma -; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v16 -; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v12 +; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v24 +; ZVFHMIN-NEXT: vfwcvt.f.f.v v24, v12 +; ZVFHMIN-NEXT: vfwcvt.f.f.v v0, v20 ; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma -; ZVFHMIN-NEXT: vfmax.vv v16, v16, v0 +; ZVFHMIN-NEXT: vfmax.vv v16, v24, v0 ; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m4, ta, ma ; ZVFHMIN-NEXT: vfncvt.f.f.w v12, v16 ; ZVFHMIN-NEXT: ret diff --git a/llvm/test/CodeGen/RISCV/rvv/vfmin-sdnode.ll b/llvm/test/CodeGen/RISCV/rvv/vfmin-sdnode.ll index d8fd79dc3066fb..b47e14f4f26be6 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vfmin-sdnode.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vfmin-sdnode.ll @@ -40,15 +40,13 @@ define @vfmin_nxv1f16_vf( %a, half %b) { ; ; ZVFHMIN-LABEL: vfmin_nxv1f16_vf: ; ZVFHMIN: # %bb.0: -; ZVFHMIN-NEXT: fcvt.s.h fa5, fa0 -; ZVFHMIN-NEXT: vsetvli a0, zero, e32, mf2, ta, ma -; ZVFHMIN-NEXT: vfmv.v.f v9, fa5 -; ZVFHMIN-NEXT: vsetvli zero, zero, e16, mf4, ta, ma -; ZVFHMIN-NEXT: vfncvt.f.f.w v10, v9 -; ZVFHMIN-NEXT: vfwcvt.f.f.v v9, v8 -; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v10 +; ZVFHMIN-NEXT: fmv.x.h a0, fa0 +; ZVFHMIN-NEXT: vsetvli a1, zero, e16, mf4, ta, ma +; ZVFHMIN-NEXT: vmv.v.x v9, a0 +; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v8 +; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v9 ; ZVFHMIN-NEXT: vsetvli zero, zero, e32, mf2, ta, ma -; ZVFHMIN-NEXT: vfmin.vv v9, v9, v8 +; ZVFHMIN-NEXT: vfmin.vv v9, v10, v8 ; ZVFHMIN-NEXT: vsetvli zero, zero, e16, mf4, ta, ma ; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v9 ; ZVFHMIN-NEXT: ret @@ -90,15 +88,13 @@ define @vfmin_nxv2f16_vf( %a, half %b) { ; ; ZVFHMIN-LABEL: vfmin_nxv2f16_vf: ; ZVFHMIN: # %bb.0: -; ZVFHMIN-NEXT: fcvt.s.h fa5, fa0 -; ZVFHMIN-NEXT: vsetvli a0, zero, e32, m1, ta, ma -; ZVFHMIN-NEXT: vfmv.v.f v9, fa5 -; ZVFHMIN-NEXT: vsetvli zero, zero, e16, mf2, ta, ma -; ZVFHMIN-NEXT: vfncvt.f.f.w v10, v9 -; ZVFHMIN-NEXT: vfwcvt.f.f.v v9, v8 -; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v10 +; ZVFHMIN-NEXT: fmv.x.h a0, fa0 +; ZVFHMIN-NEXT: vsetvli a1, zero, e16, mf2, ta, ma +; ZVFHMIN-NEXT: vmv.v.x v9, a0 +; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v8 +; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v9 ; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m1, ta, ma -; ZVFHMIN-NEXT: vfmin.vv v9, v9, v8 +; ZVFHMIN-NEXT: vfmin.vv v9, v10, v8 ; ZVFHMIN-NEXT: vsetvli zero, zero, e16, mf2, ta, ma ; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v9 ; ZVFHMIN-NEXT: ret @@ -140,11 +136,9 @@ define @vfmin_nxv4f16_vf( %a, half %b) { ; ; ZVFHMIN-LABEL: vfmin_nxv4f16_vf: ; ZVFHMIN: # %bb.0: -; ZVFHMIN-NEXT: fcvt.s.h fa5, fa0 -; ZVFHMIN-NEXT: vsetvli a0, zero, e32, m2, ta, ma -; ZVFHMIN-NEXT: vfmv.v.f v10, fa5 -; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m1, ta, ma -; ZVFHMIN-NEXT: vfncvt.f.f.w v9, v10 +; ZVFHMIN-NEXT: fmv.x.h a0, fa0 +; ZVFHMIN-NEXT: vsetvli a1, zero, e16, m1, ta, ma +; ZVFHMIN-NEXT: vmv.v.x v9, a0 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v8 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v9 ; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m2, ta, ma @@ -190,11 +184,9 @@ define @vfmin_nxv8f16_vf( %a, half %b) { ; ; ZVFHMIN-LABEL: vfmin_nxv8f16_vf: ; ZVFHMIN: # %bb.0: -; ZVFHMIN-NEXT: fcvt.s.h fa5, fa0 -; ZVFHMIN-NEXT: vsetvli a0, zero, e32, m4, ta, ma -; ZVFHMIN-NEXT: vfmv.v.f v12, fa5 -; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m2, ta, ma -; ZVFHMIN-NEXT: vfncvt.f.f.w v10, v12 +; ZVFHMIN-NEXT: fmv.x.h a0, fa0 +; ZVFHMIN-NEXT: vsetvli a1, zero, e16, m2, ta, ma +; ZVFHMIN-NEXT: vmv.v.x v10, a0 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v8 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v10 ; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m4, ta, ma @@ -240,11 +232,9 @@ define @vfmin_nxv16f16_vf( %a, half %b) ; ; ZVFHMIN-LABEL: vfmin_nxv16f16_vf: ; ZVFHMIN: # %bb.0: -; ZVFHMIN-NEXT: fcvt.s.h fa5, fa0 -; ZVFHMIN-NEXT: vsetvli a0, zero, e32, m8, ta, ma -; ZVFHMIN-NEXT: vfmv.v.f v16, fa5 -; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m4, ta, ma -; ZVFHMIN-NEXT: vfncvt.f.f.w v12, v16 +; ZVFHMIN-NEXT: fmv.x.h a0, fa0 +; ZVFHMIN-NEXT: vsetvli a1, zero, e16, m4, ta, ma +; ZVFHMIN-NEXT: vmv.v.x v12, a0 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v8 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v24, v12 ; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma @@ -296,20 +286,20 @@ define @vfmin_nxv32f16_vf( %a, half %b) ; ; ZVFHMIN-LABEL: vfmin_nxv32f16_vf: ; ZVFHMIN: # %bb.0: -; ZVFHMIN-NEXT: fcvt.s.h fa5, fa0 -; ZVFHMIN-NEXT: vsetvli a0, zero, e32, m8, ta, ma -; ZVFHMIN-NEXT: vfmv.v.f v16, fa5 -; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m4, ta, ma -; ZVFHMIN-NEXT: vfncvt.f.f.w v24, v16 -; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v8 -; ZVFHMIN-NEXT: vfwcvt.f.f.v v0, v24 +; ZVFHMIN-NEXT: fmv.x.h a0, fa0 +; ZVFHMIN-NEXT: vsetvli a1, zero, e16, m8, ta, ma +; ZVFHMIN-NEXT: vmv.v.x v16, a0 +; ZVFHMIN-NEXT: vsetvli a0, zero, e16, m4, ta, ma +; ZVFHMIN-NEXT: vfwcvt.f.f.v v24, v8 +; ZVFHMIN-NEXT: vfwcvt.f.f.v v0, v16 ; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma -; ZVFHMIN-NEXT: vfmin.vv v16, v16, v0 +; ZVFHMIN-NEXT: vfmin.vv v24, v24, v0 ; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m4, ta, ma -; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v16 -; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v12 +; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v24 +; ZVFHMIN-NEXT: vfwcvt.f.f.v v24, v12 +; ZVFHMIN-NEXT: vfwcvt.f.f.v v0, v20 ; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma -; ZVFHMIN-NEXT: vfmin.vv v16, v16, v0 +; ZVFHMIN-NEXT: vfmin.vv v16, v24, v0 ; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m4, ta, ma ; ZVFHMIN-NEXT: vfncvt.f.f.w v12, v16 ; ZVFHMIN-NEXT: ret diff --git a/llvm/test/CodeGen/RISCV/rvv/vfmsub-constrained-sdnode.ll b/llvm/test/CodeGen/RISCV/rvv/vfmsub-constrained-sdnode.ll index 725ac14b0e7a7e..7ec241bf74247a 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vfmsub-constrained-sdnode.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vfmsub-constrained-sdnode.ll @@ -47,18 +47,16 @@ define @vfmsub_vf_nxv1f16( %va, @vfmsub_vf_nxv2f16( %va, @vfmsub_vf_nxv4f16( %va, @vfmsub_vf_nxv8f16( %va, @vfmsub_vf_nxv16f16( %va, poison, half %c, i32 0 %splat = shufflevector %head, poison, zeroinitializer @@ -412,85 +415,65 @@ define @vfmsub_vf_nxv32f16( %va, @vfmul_vf_nxv1f16( %va, half %b) s ; ; ZVFHMIN-LABEL: vfmul_vf_nxv1f16: ; ZVFHMIN: # %bb.0: -; ZVFHMIN-NEXT: fcvt.s.h fa5, fa0 -; ZVFHMIN-NEXT: vsetvli a0, zero, e32, mf2, ta, ma -; ZVFHMIN-NEXT: vfmv.v.f v9, fa5 -; ZVFHMIN-NEXT: vsetvli zero, zero, e16, mf4, ta, ma -; ZVFHMIN-NEXT: vfncvt.f.f.w v10, v9 -; ZVFHMIN-NEXT: vfwcvt.f.f.v v9, v8 -; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v10 +; ZVFHMIN-NEXT: fmv.x.h a0, fa0 +; ZVFHMIN-NEXT: vsetvli a1, zero, e16, mf4, ta, ma +; ZVFHMIN-NEXT: vmv.v.x v9, a0 +; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v8 +; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v9 ; ZVFHMIN-NEXT: vsetvli zero, zero, e32, mf2, ta, ma -; ZVFHMIN-NEXT: vfmul.vv v9, v9, v8 +; ZVFHMIN-NEXT: vfmul.vv v9, v10, v8 ; ZVFHMIN-NEXT: vsetvli zero, zero, e16, mf4, ta, ma ; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v9 ; ZVFHMIN-NEXT: ret @@ -90,15 +88,13 @@ define @vfmul_vf_nxv2f16( %va, half %b) s ; ; ZVFHMIN-LABEL: vfmul_vf_nxv2f16: ; ZVFHMIN: # %bb.0: -; ZVFHMIN-NEXT: fcvt.s.h fa5, fa0 -; ZVFHMIN-NEXT: vsetvli a0, zero, e32, m1, ta, ma -; ZVFHMIN-NEXT: vfmv.v.f v9, fa5 -; ZVFHMIN-NEXT: vsetvli zero, zero, e16, mf2, ta, ma -; ZVFHMIN-NEXT: vfncvt.f.f.w v10, v9 -; ZVFHMIN-NEXT: vfwcvt.f.f.v v9, v8 -; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v10 +; ZVFHMIN-NEXT: fmv.x.h a0, fa0 +; ZVFHMIN-NEXT: vsetvli a1, zero, e16, mf2, ta, ma +; ZVFHMIN-NEXT: vmv.v.x v9, a0 +; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v8 +; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v9 ; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m1, ta, ma -; ZVFHMIN-NEXT: vfmul.vv v9, v9, v8 +; ZVFHMIN-NEXT: vfmul.vv v9, v10, v8 ; ZVFHMIN-NEXT: vsetvli zero, zero, e16, mf2, ta, ma ; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v9 ; ZVFHMIN-NEXT: ret @@ -140,11 +136,9 @@ define @vfmul_vf_nxv4f16( %va, half %b) s ; ; ZVFHMIN-LABEL: vfmul_vf_nxv4f16: ; ZVFHMIN: # %bb.0: -; ZVFHMIN-NEXT: fcvt.s.h fa5, fa0 -; ZVFHMIN-NEXT: vsetvli a0, zero, e32, m2, ta, ma -; ZVFHMIN-NEXT: vfmv.v.f v10, fa5 -; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m1, ta, ma -; ZVFHMIN-NEXT: vfncvt.f.f.w v9, v10 +; ZVFHMIN-NEXT: fmv.x.h a0, fa0 +; ZVFHMIN-NEXT: vsetvli a1, zero, e16, m1, ta, ma +; ZVFHMIN-NEXT: vmv.v.x v9, a0 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v8 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v9 ; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m2, ta, ma @@ -190,11 +184,9 @@ define @vfmul_vf_nxv8f16( %va, half %b) s ; ; ZVFHMIN-LABEL: vfmul_vf_nxv8f16: ; ZVFHMIN: # %bb.0: -; ZVFHMIN-NEXT: fcvt.s.h fa5, fa0 -; ZVFHMIN-NEXT: vsetvli a0, zero, e32, m4, ta, ma -; ZVFHMIN-NEXT: vfmv.v.f v12, fa5 -; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m2, ta, ma -; ZVFHMIN-NEXT: vfncvt.f.f.w v10, v12 +; ZVFHMIN-NEXT: fmv.x.h a0, fa0 +; ZVFHMIN-NEXT: vsetvli a1, zero, e16, m2, ta, ma +; ZVFHMIN-NEXT: vmv.v.x v10, a0 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v8 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v10 ; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m4, ta, ma @@ -240,11 +232,9 @@ define @vfmul_vf_nxv16f16( %va, half %b ; ; ZVFHMIN-LABEL: vfmul_vf_nxv16f16: ; ZVFHMIN: # %bb.0: -; ZVFHMIN-NEXT: fcvt.s.h fa5, fa0 -; ZVFHMIN-NEXT: vsetvli a0, zero, e32, m8, ta, ma -; ZVFHMIN-NEXT: vfmv.v.f v16, fa5 -; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m4, ta, ma -; ZVFHMIN-NEXT: vfncvt.f.f.w v12, v16 +; ZVFHMIN-NEXT: fmv.x.h a0, fa0 +; ZVFHMIN-NEXT: vsetvli a1, zero, e16, m4, ta, ma +; ZVFHMIN-NEXT: vmv.v.x v12, a0 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v8 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v24, v12 ; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma @@ -296,21 +286,20 @@ define @vfmul_vf_nxv32f16( %va, half %b ; ; ZVFHMIN-LABEL: vfmul_vf_nxv32f16: ; ZVFHMIN: # %bb.0: -; ZVFHMIN-NEXT: fcvt.s.h fa5, fa0 -; ZVFHMIN-NEXT: vsetvli a0, zero, e32, m8, ta, ma -; ZVFHMIN-NEXT: vfmv.v.f v16, fa5 -; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m4, ta, ma -; ZVFHMIN-NEXT: vfncvt.f.f.w v24, v16 -; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v8 -; ZVFHMIN-NEXT: vfwcvt.f.f.v v0, v24 +; ZVFHMIN-NEXT: fmv.x.h a0, fa0 +; ZVFHMIN-NEXT: vsetvli a1, zero, e16, m8, ta, ma +; ZVFHMIN-NEXT: vmv.v.x v16, a0 +; ZVFHMIN-NEXT: vsetvli a0, zero, e16, m4, ta, ma +; ZVFHMIN-NEXT: vfwcvt.f.f.v v24, v8 +; ZVFHMIN-NEXT: vfwcvt.f.f.v v0, v16 ; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma -; ZVFHMIN-NEXT: vfmul.vv v16, v16, v0 +; ZVFHMIN-NEXT: vfmul.vv v24, v24, v0 ; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m4, ta, ma -; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v16 -; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v24 -; ZVFHMIN-NEXT: vfwcvt.f.f.v v24, v12 +; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v24 +; ZVFHMIN-NEXT: vfwcvt.f.f.v v24, v20 +; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v12 ; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma -; ZVFHMIN-NEXT: vfmul.vv v16, v24, v16 +; ZVFHMIN-NEXT: vfmul.vv v16, v16, v24 ; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m4, ta, ma ; ZVFHMIN-NEXT: vfncvt.f.f.w v12, v16 ; ZVFHMIN-NEXT: ret diff --git a/llvm/test/CodeGen/RISCV/rvv/vfmul-sdnode.ll b/llvm/test/CodeGen/RISCV/rvv/vfmul-sdnode.ll index f7f5e88bf8712f..70d664aa50ec4f 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vfmul-sdnode.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vfmul-sdnode.ll @@ -38,15 +38,13 @@ define @vfmul_vf_nxv1f16( %va, half %b) { ; ; ZVFHMIN-LABEL: vfmul_vf_nxv1f16: ; ZVFHMIN: # %bb.0: -; ZVFHMIN-NEXT: fcvt.s.h fa5, fa0 -; ZVFHMIN-NEXT: vsetvli a0, zero, e32, mf2, ta, ma -; ZVFHMIN-NEXT: vfmv.v.f v9, fa5 -; ZVFHMIN-NEXT: vsetvli zero, zero, e16, mf4, ta, ma -; ZVFHMIN-NEXT: vfncvt.f.f.w v10, v9 -; ZVFHMIN-NEXT: vfwcvt.f.f.v v9, v8 -; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v10 +; ZVFHMIN-NEXT: fmv.x.h a0, fa0 +; ZVFHMIN-NEXT: vsetvli a1, zero, e16, mf4, ta, ma +; ZVFHMIN-NEXT: vmv.v.x v9, a0 +; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v8 +; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v9 ; ZVFHMIN-NEXT: vsetvli zero, zero, e32, mf2, ta, ma -; ZVFHMIN-NEXT: vfmul.vv v9, v9, v8 +; ZVFHMIN-NEXT: vfmul.vv v9, v10, v8 ; ZVFHMIN-NEXT: vsetvli zero, zero, e16, mf4, ta, ma ; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v9 ; ZVFHMIN-NEXT: ret @@ -86,15 +84,13 @@ define @vfmul_vf_nxv2f16( %va, half %b) { ; ; ZVFHMIN-LABEL: vfmul_vf_nxv2f16: ; ZVFHMIN: # %bb.0: -; ZVFHMIN-NEXT: fcvt.s.h fa5, fa0 -; ZVFHMIN-NEXT: vsetvli a0, zero, e32, m1, ta, ma -; ZVFHMIN-NEXT: vfmv.v.f v9, fa5 -; ZVFHMIN-NEXT: vsetvli zero, zero, e16, mf2, ta, ma -; ZVFHMIN-NEXT: vfncvt.f.f.w v10, v9 -; ZVFHMIN-NEXT: vfwcvt.f.f.v v9, v8 -; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v10 +; ZVFHMIN-NEXT: fmv.x.h a0, fa0 +; ZVFHMIN-NEXT: vsetvli a1, zero, e16, mf2, ta, ma +; ZVFHMIN-NEXT: vmv.v.x v9, a0 +; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v8 +; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v9 ; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m1, ta, ma -; ZVFHMIN-NEXT: vfmul.vv v9, v9, v8 +; ZVFHMIN-NEXT: vfmul.vv v9, v10, v8 ; ZVFHMIN-NEXT: vsetvli zero, zero, e16, mf2, ta, ma ; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v9 ; ZVFHMIN-NEXT: ret @@ -134,11 +130,9 @@ define @vfmul_vf_nxv4f16( %va, half %b) { ; ; ZVFHMIN-LABEL: vfmul_vf_nxv4f16: ; ZVFHMIN: # %bb.0: -; ZVFHMIN-NEXT: fcvt.s.h fa5, fa0 -; ZVFHMIN-NEXT: vsetvli a0, zero, e32, m2, ta, ma -; ZVFHMIN-NEXT: vfmv.v.f v10, fa5 -; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m1, ta, ma -; ZVFHMIN-NEXT: vfncvt.f.f.w v9, v10 +; ZVFHMIN-NEXT: fmv.x.h a0, fa0 +; ZVFHMIN-NEXT: vsetvli a1, zero, e16, m1, ta, ma +; ZVFHMIN-NEXT: vmv.v.x v9, a0 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v8 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v9 ; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m2, ta, ma @@ -182,11 +176,9 @@ define @vfmul_vf_nxv8f16( %va, half %b) { ; ; ZVFHMIN-LABEL: vfmul_vf_nxv8f16: ; ZVFHMIN: # %bb.0: -; ZVFHMIN-NEXT: fcvt.s.h fa5, fa0 -; ZVFHMIN-NEXT: vsetvli a0, zero, e32, m4, ta, ma -; ZVFHMIN-NEXT: vfmv.v.f v12, fa5 -; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m2, ta, ma -; ZVFHMIN-NEXT: vfncvt.f.f.w v10, v12 +; ZVFHMIN-NEXT: fmv.x.h a0, fa0 +; ZVFHMIN-NEXT: vsetvli a1, zero, e16, m2, ta, ma +; ZVFHMIN-NEXT: vmv.v.x v10, a0 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v8 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v10 ; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m4, ta, ma @@ -209,11 +201,9 @@ define @vfmul_fv_nxv8f16( %va, half %b) { ; ; ZVFHMIN-LABEL: vfmul_fv_nxv8f16: ; ZVFHMIN: # %bb.0: -; ZVFHMIN-NEXT: fcvt.s.h fa5, fa0 -; ZVFHMIN-NEXT: vsetvli a0, zero, e32, m4, ta, ma -; ZVFHMIN-NEXT: vfmv.v.f v12, fa5 -; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m2, ta, ma -; ZVFHMIN-NEXT: vfncvt.f.f.w v10, v12 +; ZVFHMIN-NEXT: fmv.x.h a0, fa0 +; ZVFHMIN-NEXT: vsetvli a1, zero, e16, m2, ta, ma +; ZVFHMIN-NEXT: vmv.v.x v10, a0 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v8 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v10 ; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m4, ta, ma @@ -257,11 +247,9 @@ define @vfmul_vf_nxv16f16( %va, half %b ; ; ZVFHMIN-LABEL: vfmul_vf_nxv16f16: ; ZVFHMIN: # %bb.0: -; ZVFHMIN-NEXT: fcvt.s.h fa5, fa0 -; ZVFHMIN-NEXT: vsetvli a0, zero, e32, m8, ta, ma -; ZVFHMIN-NEXT: vfmv.v.f v16, fa5 -; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m4, ta, ma -; ZVFHMIN-NEXT: vfncvt.f.f.w v12, v16 +; ZVFHMIN-NEXT: fmv.x.h a0, fa0 +; ZVFHMIN-NEXT: vsetvli a1, zero, e16, m4, ta, ma +; ZVFHMIN-NEXT: vmv.v.x v12, a0 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v8 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v24, v12 ; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma @@ -311,20 +299,20 @@ define @vfmul_vf_nxv32f16( %va, half %b ; ; ZVFHMIN-LABEL: vfmul_vf_nxv32f16: ; ZVFHMIN: # %bb.0: -; ZVFHMIN-NEXT: fcvt.s.h fa5, fa0 -; ZVFHMIN-NEXT: vsetvli a0, zero, e32, m8, ta, ma -; ZVFHMIN-NEXT: vfmv.v.f v16, fa5 -; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m4, ta, ma -; ZVFHMIN-NEXT: vfncvt.f.f.w v24, v16 -; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v8 -; ZVFHMIN-NEXT: vfwcvt.f.f.v v0, v24 +; ZVFHMIN-NEXT: fmv.x.h a0, fa0 +; ZVFHMIN-NEXT: vsetvli a1, zero, e16, m8, ta, ma +; ZVFHMIN-NEXT: vmv.v.x v16, a0 +; ZVFHMIN-NEXT: vsetvli a0, zero, e16, m4, ta, ma +; ZVFHMIN-NEXT: vfwcvt.f.f.v v24, v8 +; ZVFHMIN-NEXT: vfwcvt.f.f.v v0, v16 ; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma -; ZVFHMIN-NEXT: vfmul.vv v16, v16, v0 +; ZVFHMIN-NEXT: vfmul.vv v24, v24, v0 ; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m4, ta, ma -; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v16 -; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v12 +; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v24 +; ZVFHMIN-NEXT: vfwcvt.f.f.v v24, v12 +; ZVFHMIN-NEXT: vfwcvt.f.f.v v0, v20 ; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma -; ZVFHMIN-NEXT: vfmul.vv v16, v16, v0 +; ZVFHMIN-NEXT: vfmul.vv v16, v24, v0 ; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m4, ta, ma ; ZVFHMIN-NEXT: vfncvt.f.f.w v12, v16 ; ZVFHMIN-NEXT: ret diff --git a/llvm/test/CodeGen/RISCV/rvv/vfmul-vp.ll b/llvm/test/CodeGen/RISCV/rvv/vfmul-vp.ll index 61f3e63f246c66..93160c1a13fbf2 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vfmul-vp.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vfmul-vp.ll @@ -61,15 +61,13 @@ define @vfmul_vf_nxv1f16( %va, half %b, < ; ; ZVFHMIN-LABEL: vfmul_vf_nxv1f16: ; ZVFHMIN: # %bb.0: -; ZVFHMIN-NEXT: fcvt.s.h fa5, fa0 -; ZVFHMIN-NEXT: vsetvli a1, zero, e32, mf2, ta, ma -; ZVFHMIN-NEXT: vfmv.v.f v9, fa5 -; ZVFHMIN-NEXT: vsetvli zero, zero, e16, mf4, ta, ma -; ZVFHMIN-NEXT: vfncvt.f.f.w v10, v9 -; ZVFHMIN-NEXT: vfwcvt.f.f.v v9, v8 -; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v10 +; ZVFHMIN-NEXT: fmv.x.h a1, fa0 +; ZVFHMIN-NEXT: vsetvli a2, zero, e16, mf4, ta, ma +; ZVFHMIN-NEXT: vmv.v.x v9, a1 +; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v8 +; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v9 ; ZVFHMIN-NEXT: vsetvli zero, a0, e32, mf2, ta, ma -; ZVFHMIN-NEXT: vfmul.vv v9, v9, v8, v0.t +; ZVFHMIN-NEXT: vfmul.vv v9, v10, v8, v0.t ; ZVFHMIN-NEXT: vsetvli a0, zero, e16, mf4, ta, ma ; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v9 ; ZVFHMIN-NEXT: ret @@ -88,15 +86,13 @@ define @vfmul_vf_nxv1f16_unmasked( %va, h ; ; ZVFHMIN-LABEL: vfmul_vf_nxv1f16_unmasked: ; ZVFHMIN: # %bb.0: -; ZVFHMIN-NEXT: fcvt.s.h fa5, fa0 -; ZVFHMIN-NEXT: vsetvli a1, zero, e32, mf2, ta, ma -; ZVFHMIN-NEXT: vfmv.v.f v9, fa5 -; ZVFHMIN-NEXT: vsetvli zero, zero, e16, mf4, ta, ma -; ZVFHMIN-NEXT: vfncvt.f.f.w v10, v9 -; ZVFHMIN-NEXT: vfwcvt.f.f.v v9, v8 -; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v10 +; ZVFHMIN-NEXT: fmv.x.h a1, fa0 +; ZVFHMIN-NEXT: vsetvli a2, zero, e16, mf4, ta, ma +; ZVFHMIN-NEXT: vmv.v.x v9, a1 +; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v8 +; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v9 ; ZVFHMIN-NEXT: vsetvli zero, a0, e32, mf2, ta, ma -; ZVFHMIN-NEXT: vfmul.vv v9, v9, v8 +; ZVFHMIN-NEXT: vfmul.vv v9, v10, v8 ; ZVFHMIN-NEXT: vsetvli a0, zero, e16, mf4, ta, ma ; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v9 ; ZVFHMIN-NEXT: ret @@ -159,15 +155,13 @@ define @vfmul_vf_nxv2f16( %va, half %b, < ; ; ZVFHMIN-LABEL: vfmul_vf_nxv2f16: ; ZVFHMIN: # %bb.0: -; ZVFHMIN-NEXT: fcvt.s.h fa5, fa0 -; ZVFHMIN-NEXT: vsetvli a1, zero, e32, m1, ta, ma -; ZVFHMIN-NEXT: vfmv.v.f v9, fa5 -; ZVFHMIN-NEXT: vsetvli zero, zero, e16, mf2, ta, ma -; ZVFHMIN-NEXT: vfncvt.f.f.w v10, v9 -; ZVFHMIN-NEXT: vfwcvt.f.f.v v9, v8 -; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v10 +; ZVFHMIN-NEXT: fmv.x.h a1, fa0 +; ZVFHMIN-NEXT: vsetvli a2, zero, e16, mf2, ta, ma +; ZVFHMIN-NEXT: vmv.v.x v9, a1 +; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v8 +; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v9 ; ZVFHMIN-NEXT: vsetvli zero, a0, e32, m1, ta, ma -; ZVFHMIN-NEXT: vfmul.vv v9, v9, v8, v0.t +; ZVFHMIN-NEXT: vfmul.vv v9, v10, v8, v0.t ; ZVFHMIN-NEXT: vsetvli a0, zero, e16, mf2, ta, ma ; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v9 ; ZVFHMIN-NEXT: ret @@ -186,15 +180,13 @@ define @vfmul_vf_nxv2f16_unmasked( %va, h ; ; ZVFHMIN-LABEL: vfmul_vf_nxv2f16_unmasked: ; ZVFHMIN: # %bb.0: -; ZVFHMIN-NEXT: fcvt.s.h fa5, fa0 -; ZVFHMIN-NEXT: vsetvli a1, zero, e32, m1, ta, ma -; ZVFHMIN-NEXT: vfmv.v.f v9, fa5 -; ZVFHMIN-NEXT: vsetvli zero, zero, e16, mf2, ta, ma -; ZVFHMIN-NEXT: vfncvt.f.f.w v10, v9 -; ZVFHMIN-NEXT: vfwcvt.f.f.v v9, v8 -; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v10 +; ZVFHMIN-NEXT: fmv.x.h a1, fa0 +; ZVFHMIN-NEXT: vsetvli a2, zero, e16, mf2, ta, ma +; ZVFHMIN-NEXT: vmv.v.x v9, a1 +; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v8 +; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v9 ; ZVFHMIN-NEXT: vsetvli zero, a0, e32, m1, ta, ma -; ZVFHMIN-NEXT: vfmul.vv v9, v9, v8 +; ZVFHMIN-NEXT: vfmul.vv v9, v10, v8 ; ZVFHMIN-NEXT: vsetvli a0, zero, e16, mf2, ta, ma ; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v9 ; ZVFHMIN-NEXT: ret @@ -257,11 +249,9 @@ define @vfmul_vf_nxv4f16( %va, half %b, < ; ; ZVFHMIN-LABEL: vfmul_vf_nxv4f16: ; ZVFHMIN: # %bb.0: -; ZVFHMIN-NEXT: fcvt.s.h fa5, fa0 -; ZVFHMIN-NEXT: vsetvli a1, zero, e32, m2, ta, ma -; ZVFHMIN-NEXT: vfmv.v.f v10, fa5 -; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m1, ta, ma -; ZVFHMIN-NEXT: vfncvt.f.f.w v9, v10 +; ZVFHMIN-NEXT: fmv.x.h a1, fa0 +; ZVFHMIN-NEXT: vsetvli a2, zero, e16, m1, ta, ma +; ZVFHMIN-NEXT: vmv.v.x v9, a1 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v8 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v9 ; ZVFHMIN-NEXT: vsetvli zero, a0, e32, m2, ta, ma @@ -284,11 +274,9 @@ define @vfmul_vf_nxv4f16_unmasked( %va, h ; ; ZVFHMIN-LABEL: vfmul_vf_nxv4f16_unmasked: ; ZVFHMIN: # %bb.0: -; ZVFHMIN-NEXT: fcvt.s.h fa5, fa0 -; ZVFHMIN-NEXT: vsetvli a1, zero, e32, m2, ta, ma -; ZVFHMIN-NEXT: vfmv.v.f v10, fa5 -; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m1, ta, ma -; ZVFHMIN-NEXT: vfncvt.f.f.w v9, v10 +; ZVFHMIN-NEXT: fmv.x.h a1, fa0 +; ZVFHMIN-NEXT: vsetvli a2, zero, e16, m1, ta, ma +; ZVFHMIN-NEXT: vmv.v.x v9, a1 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v8 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v9 ; ZVFHMIN-NEXT: vsetvli zero, a0, e32, m2, ta, ma @@ -355,11 +343,9 @@ define @vfmul_vf_nxv8f16( %va, half %b, < ; ; ZVFHMIN-LABEL: vfmul_vf_nxv8f16: ; ZVFHMIN: # %bb.0: -; ZVFHMIN-NEXT: fcvt.s.h fa5, fa0 -; ZVFHMIN-NEXT: vsetvli a1, zero, e32, m4, ta, ma -; ZVFHMIN-NEXT: vfmv.v.f v12, fa5 -; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m2, ta, ma -; ZVFHMIN-NEXT: vfncvt.f.f.w v10, v12 +; ZVFHMIN-NEXT: fmv.x.h a1, fa0 +; ZVFHMIN-NEXT: vsetvli a2, zero, e16, m2, ta, ma +; ZVFHMIN-NEXT: vmv.v.x v10, a1 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v8 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v10 ; ZVFHMIN-NEXT: vsetvli zero, a0, e32, m4, ta, ma @@ -382,11 +368,9 @@ define @vfmul_vf_nxv8f16_unmasked( %va, h ; ; ZVFHMIN-LABEL: vfmul_vf_nxv8f16_unmasked: ; ZVFHMIN: # %bb.0: -; ZVFHMIN-NEXT: fcvt.s.h fa5, fa0 -; ZVFHMIN-NEXT: vsetvli a1, zero, e32, m4, ta, ma -; ZVFHMIN-NEXT: vfmv.v.f v12, fa5 -; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m2, ta, ma -; ZVFHMIN-NEXT: vfncvt.f.f.w v10, v12 +; ZVFHMIN-NEXT: fmv.x.h a1, fa0 +; ZVFHMIN-NEXT: vsetvli a2, zero, e16, m2, ta, ma +; ZVFHMIN-NEXT: vmv.v.x v10, a1 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v8 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v10 ; ZVFHMIN-NEXT: vsetvli zero, a0, e32, m4, ta, ma @@ -453,11 +437,9 @@ define @vfmul_vf_nxv16f16( %va, half %b ; ; ZVFHMIN-LABEL: vfmul_vf_nxv16f16: ; ZVFHMIN: # %bb.0: -; ZVFHMIN-NEXT: fcvt.s.h fa5, fa0 -; ZVFHMIN-NEXT: vsetvli a1, zero, e32, m8, ta, ma -; ZVFHMIN-NEXT: vfmv.v.f v16, fa5 -; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m4, ta, ma -; ZVFHMIN-NEXT: vfncvt.f.f.w v12, v16 +; ZVFHMIN-NEXT: fmv.x.h a1, fa0 +; ZVFHMIN-NEXT: vsetvli a2, zero, e16, m4, ta, ma +; ZVFHMIN-NEXT: vmv.v.x v12, a1 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v8 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v24, v12 ; ZVFHMIN-NEXT: vsetvli zero, a0, e32, m8, ta, ma @@ -480,11 +462,9 @@ define @vfmul_vf_nxv16f16_unmasked( %va ; ; ZVFHMIN-LABEL: vfmul_vf_nxv16f16_unmasked: ; ZVFHMIN: # %bb.0: -; ZVFHMIN-NEXT: fcvt.s.h fa5, fa0 -; ZVFHMIN-NEXT: vsetvli a1, zero, e32, m8, ta, ma -; ZVFHMIN-NEXT: vfmv.v.f v16, fa5 -; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m4, ta, ma -; ZVFHMIN-NEXT: vfncvt.f.f.w v12, v16 +; ZVFHMIN-NEXT: fmv.x.h a1, fa0 +; ZVFHMIN-NEXT: vsetvli a2, zero, e16, m4, ta, ma +; ZVFHMIN-NEXT: vmv.v.x v12, a1 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v8 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v24, v12 ; ZVFHMIN-NEXT: vsetvli zero, a0, e32, m8, ta, ma @@ -624,17 +604,22 @@ define @vfmul_vf_nxv32f16( %va, half %b ; ZVFHMIN-NEXT: addi sp, sp, -16 ; ZVFHMIN-NEXT: .cfi_def_cfa_offset 16 ; ZVFHMIN-NEXT: csrr a1, vlenb -; ZVFHMIN-NEXT: slli a1, a1, 2 +; ZVFHMIN-NEXT: slli a1, a1, 1 +; ZVFHMIN-NEXT: mv a2, a1 +; ZVFHMIN-NEXT: slli a1, a1, 3 +; ZVFHMIN-NEXT: add a1, a1, a2 ; ZVFHMIN-NEXT: sub sp, sp, a1 -; ZVFHMIN-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x04, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 4 * vlenb -; ZVFHMIN-NEXT: vmv1r.v v7, v0 -; ZVFHMIN-NEXT: fcvt.s.h fa5, fa0 -; ZVFHMIN-NEXT: vsetvli a1, zero, e32, m8, ta, ma -; ZVFHMIN-NEXT: vfmv.v.f v24, fa5 -; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m4, ta, ma -; ZVFHMIN-NEXT: vfncvt.f.f.w v16, v24 -; ZVFHMIN-NEXT: addi a1, sp, 16 -; ZVFHMIN-NEXT: vs4r.v v16, (a1) # Unknown-size Folded Spill +; ZVFHMIN-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x12, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 18 * vlenb +; ZVFHMIN-NEXT: vmv8r.v v24, v8 +; ZVFHMIN-NEXT: fmv.x.h a1, fa0 +; ZVFHMIN-NEXT: vsetvli a2, zero, e16, m8, ta, ma +; ZVFHMIN-NEXT: vmv.v.x v16, a1 +; ZVFHMIN-NEXT: csrr a1, vlenb +; ZVFHMIN-NEXT: slli a2, a1, 3 +; ZVFHMIN-NEXT: add a1, a2, a1 +; ZVFHMIN-NEXT: add a1, sp, a1 +; ZVFHMIN-NEXT: addi a1, a1, 16 +; ZVFHMIN-NEXT: vs8r.v v16, (a1) # Unknown-size Folded Spill ; ZVFHMIN-NEXT: csrr a2, vlenb ; ZVFHMIN-NEXT: slli a1, a2, 1 ; ZVFHMIN-NEXT: sub a3, a0, a1 @@ -642,29 +627,56 @@ define @vfmul_vf_nxv32f16( %va, half %b ; ZVFHMIN-NEXT: addi a4, a4, -1 ; ZVFHMIN-NEXT: and a3, a4, a3 ; ZVFHMIN-NEXT: srli a2, a2, 2 +; ZVFHMIN-NEXT: csrr a4, vlenb +; ZVFHMIN-NEXT: slli a4, a4, 3 +; ZVFHMIN-NEXT: add a4, sp, a4 +; ZVFHMIN-NEXT: addi a4, a4, 16 +; ZVFHMIN-NEXT: vs1r.v v0, (a4) # Unknown-size Folded Spill ; ZVFHMIN-NEXT: vsetvli a4, zero, e8, mf2, ta, ma ; ZVFHMIN-NEXT: vslidedown.vx v0, v0, a2 -; ZVFHMIN-NEXT: vsetvli a2, zero, e16, m4, ta, ma -; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v12 ; ZVFHMIN-NEXT: addi a2, sp, 16 -; ZVFHMIN-NEXT: vl4r.v v12, (a2) # Unknown-size Folded Reload -; ZVFHMIN-NEXT: vfwcvt.f.f.v v24, v12 +; ZVFHMIN-NEXT: vs8r.v v8, (a2) # Unknown-size Folded Spill +; ZVFHMIN-NEXT: vsetvli a2, zero, e16, m4, ta, ma +; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v28 +; ZVFHMIN-NEXT: csrr a2, vlenb +; ZVFHMIN-NEXT: slli a4, a2, 3 +; ZVFHMIN-NEXT: add a2, a4, a2 +; ZVFHMIN-NEXT: add a2, sp, a2 +; ZVFHMIN-NEXT: addi a2, a2, 16 +; ZVFHMIN-NEXT: vl8r.v v24, (a2) # Unknown-size Folded Reload +; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v28 ; ZVFHMIN-NEXT: vsetvli zero, a3, e32, m8, ta, ma -; ZVFHMIN-NEXT: vfmul.vv v16, v16, v24, v0.t +; ZVFHMIN-NEXT: vfmul.vv v16, v8, v16, v0.t ; ZVFHMIN-NEXT: vsetvli a2, zero, e16, m4, ta, ma ; ZVFHMIN-NEXT: vfncvt.f.f.w v12, v16 ; ZVFHMIN-NEXT: bltu a0, a1, .LBB22_2 ; ZVFHMIN-NEXT: # %bb.1: ; ZVFHMIN-NEXT: mv a0, a1 ; ZVFHMIN-NEXT: .LBB22_2: -; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v8 -; ZVFHMIN-NEXT: vmv1r.v v0, v7 +; ZVFHMIN-NEXT: addi a1, sp, 16 +; ZVFHMIN-NEXT: vl8r.v v24, (a1) # Unknown-size Folded Reload +; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v24 +; ZVFHMIN-NEXT: csrr a1, vlenb +; ZVFHMIN-NEXT: slli a2, a1, 3 +; ZVFHMIN-NEXT: add a1, a2, a1 +; ZVFHMIN-NEXT: add a1, sp, a1 +; ZVFHMIN-NEXT: addi a1, a1, 16 +; ZVFHMIN-NEXT: vl8r.v v0, (a1) # Unknown-size Folded Reload +; ZVFHMIN-NEXT: vfwcvt.f.f.v v24, v0 +; ZVFHMIN-NEXT: csrr a1, vlenb +; ZVFHMIN-NEXT: slli a1, a1, 3 +; ZVFHMIN-NEXT: add a1, sp, a1 +; ZVFHMIN-NEXT: addi a1, a1, 16 +; ZVFHMIN-NEXT: vl1r.v v0, (a1) # Unknown-size Folded Reload ; ZVFHMIN-NEXT: vsetvli zero, a0, e32, m8, ta, ma ; ZVFHMIN-NEXT: vfmul.vv v16, v16, v24, v0.t ; ZVFHMIN-NEXT: vsetvli a0, zero, e16, m4, ta, ma ; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v16 ; ZVFHMIN-NEXT: csrr a0, vlenb -; ZVFHMIN-NEXT: slli a0, a0, 2 +; ZVFHMIN-NEXT: slli a0, a0, 1 +; ZVFHMIN-NEXT: mv a1, a0 +; ZVFHMIN-NEXT: slli a0, a0, 3 +; ZVFHMIN-NEXT: add a0, a0, a1 ; ZVFHMIN-NEXT: add sp, sp, a0 ; ZVFHMIN-NEXT: addi sp, sp, 16 ; ZVFHMIN-NEXT: ret @@ -683,11 +695,16 @@ define @vfmul_vf_nxv32f16_unmasked( %va ; ; ZVFHMIN-LABEL: vfmul_vf_nxv32f16_unmasked: ; ZVFHMIN: # %bb.0: -; ZVFHMIN-NEXT: fcvt.s.h fa5, fa0 -; ZVFHMIN-NEXT: vsetvli a1, zero, e32, m8, ta, ma -; ZVFHMIN-NEXT: vfmv.v.f v16, fa5 -; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m4, ta, ma -; ZVFHMIN-NEXT: vfncvt.f.f.w v4, v16 +; ZVFHMIN-NEXT: addi sp, sp, -16 +; ZVFHMIN-NEXT: .cfi_def_cfa_offset 16 +; ZVFHMIN-NEXT: csrr a1, vlenb +; ZVFHMIN-NEXT: slli a1, a1, 4 +; ZVFHMIN-NEXT: sub sp, sp, a1 +; ZVFHMIN-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x10, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 16 * vlenb +; ZVFHMIN-NEXT: vmv8r.v v16, v8 +; ZVFHMIN-NEXT: fmv.x.h a1, fa0 +; ZVFHMIN-NEXT: vsetvli a2, zero, e16, m8, ta, ma +; ZVFHMIN-NEXT: vmv.v.x v8, a1 ; ZVFHMIN-NEXT: csrr a2, vlenb ; ZVFHMIN-NEXT: slli a1, a2, 1 ; ZVFHMIN-NEXT: sub a3, a0, a1 @@ -695,26 +712,45 @@ define @vfmul_vf_nxv32f16_unmasked( %va ; ZVFHMIN-NEXT: addi a4, a4, -1 ; ZVFHMIN-NEXT: and a3, a4, a3 ; ZVFHMIN-NEXT: srli a2, a2, 2 -; ZVFHMIN-NEXT: vsetvli a4, zero, e8, m4, ta, ma -; ZVFHMIN-NEXT: vmset.m v16 +; ZVFHMIN-NEXT: vmset.m v24 ; ZVFHMIN-NEXT: vsetvli a4, zero, e8, mf2, ta, ma -; ZVFHMIN-NEXT: vslidedown.vx v0, v16, a2 +; ZVFHMIN-NEXT: vslidedown.vx v0, v24, a2 +; ZVFHMIN-NEXT: addi a2, sp, 16 +; ZVFHMIN-NEXT: vs8r.v v16, (a2) # Unknown-size Folded Spill ; ZVFHMIN-NEXT: vsetvli a2, zero, e16, m4, ta, ma -; ZVFHMIN-NEXT: vfwcvt.f.f.v v24, v12 -; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v4 +; ZVFHMIN-NEXT: vfwcvt.f.f.v v24, v20 +; ZVFHMIN-NEXT: vmv4r.v v16, v8 +; ZVFHMIN-NEXT: csrr a2, vlenb +; ZVFHMIN-NEXT: slli a2, a2, 3 +; ZVFHMIN-NEXT: add a2, sp, a2 +; ZVFHMIN-NEXT: addi a2, a2, 16 +; ZVFHMIN-NEXT: vs8r.v v16, (a2) # Unknown-size Folded Spill +; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v12 ; ZVFHMIN-NEXT: vsetvli zero, a3, e32, m8, ta, ma -; ZVFHMIN-NEXT: vfmul.vv v24, v24, v16, v0.t +; ZVFHMIN-NEXT: vfmul.vv v16, v24, v16, v0.t ; ZVFHMIN-NEXT: vsetvli a2, zero, e16, m4, ta, ma -; ZVFHMIN-NEXT: vfncvt.f.f.w v12, v24 +; ZVFHMIN-NEXT: vfncvt.f.f.w v12, v16 ; ZVFHMIN-NEXT: bltu a0, a1, .LBB23_2 ; ZVFHMIN-NEXT: # %bb.1: ; ZVFHMIN-NEXT: mv a0, a1 ; ZVFHMIN-NEXT: .LBB23_2: -; ZVFHMIN-NEXT: vfwcvt.f.f.v v24, v8 +; ZVFHMIN-NEXT: addi a1, sp, 16 +; ZVFHMIN-NEXT: vl8r.v v24, (a1) # Unknown-size Folded Reload +; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v24 +; ZVFHMIN-NEXT: csrr a1, vlenb +; ZVFHMIN-NEXT: slli a1, a1, 3 +; ZVFHMIN-NEXT: add a1, sp, a1 +; ZVFHMIN-NEXT: addi a1, a1, 16 +; ZVFHMIN-NEXT: vl8r.v v0, (a1) # Unknown-size Folded Reload +; ZVFHMIN-NEXT: vfwcvt.f.f.v v24, v0 ; ZVFHMIN-NEXT: vsetvli zero, a0, e32, m8, ta, ma -; ZVFHMIN-NEXT: vfmul.vv v16, v24, v16 +; ZVFHMIN-NEXT: vfmul.vv v16, v16, v24 ; ZVFHMIN-NEXT: vsetvli a0, zero, e16, m4, ta, ma ; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v16 +; ZVFHMIN-NEXT: csrr a0, vlenb +; ZVFHMIN-NEXT: slli a0, a0, 4 +; ZVFHMIN-NEXT: add sp, sp, a0 +; ZVFHMIN-NEXT: addi sp, sp, 16 ; ZVFHMIN-NEXT: ret %elt.head = insertelement poison, half %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer diff --git a/llvm/test/CodeGen/RISCV/rvv/vfnmadd-constrained-sdnode.ll b/llvm/test/CodeGen/RISCV/rvv/vfnmadd-constrained-sdnode.ll index 2f41b59d6b2253..5ec089a2dcac86 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vfnmadd-constrained-sdnode.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vfnmadd-constrained-sdnode.ll @@ -49,19 +49,17 @@ define @vfnmsub_vf_nxv1f16( %va, @vfnmsub_vf_nxv2f16( %va, @vfnmsub_vf_nxv4f16( %va, @vfnmsub_vf_nxv8f16( %va, @vfnmsub_vf_nxv16f16( %va, @vfnmsub_vf_nxv32f16( %va, @vfnmsub_vf_nxv32f16( %va, @vfnmsub_vf_nxv32f16( %va, @vfnmsub_vf_nxv1f16( %va, @vfnmsub_vf_nxv2f16( %va, @vfnmsub_vf_nxv4f16( %va, @vfnmsub_vf_nxv8f16( %va, @vfnmsub_vf_nxv16f16( %va, @vfnmsub_vf_nxv32f16( %va, @vfnmsub_vf_nxv32f16( %va, @vfsub_vf_nxv1f16( %va, half %b) s ; ; ZVFHMIN-LABEL: vfsub_vf_nxv1f16: ; ZVFHMIN: # %bb.0: -; ZVFHMIN-NEXT: fcvt.s.h fa5, fa0 -; ZVFHMIN-NEXT: vsetvli a0, zero, e32, mf2, ta, ma -; ZVFHMIN-NEXT: vfmv.v.f v9, fa5 -; ZVFHMIN-NEXT: vsetvli zero, zero, e16, mf4, ta, ma -; ZVFHMIN-NEXT: vfncvt.f.f.w v10, v9 -; ZVFHMIN-NEXT: vfwcvt.f.f.v v9, v8 -; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v10 +; ZVFHMIN-NEXT: fmv.x.h a0, fa0 +; ZVFHMIN-NEXT: vsetvli a1, zero, e16, mf4, ta, ma +; ZVFHMIN-NEXT: vmv.v.x v9, a0 +; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v8 +; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v9 ; ZVFHMIN-NEXT: vsetvli zero, zero, e32, mf2, ta, ma -; ZVFHMIN-NEXT: vfsub.vv v9, v9, v8 +; ZVFHMIN-NEXT: vfsub.vv v9, v10, v8 ; ZVFHMIN-NEXT: vsetvli zero, zero, e16, mf4, ta, ma ; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v9 ; ZVFHMIN-NEXT: ret @@ -90,15 +88,13 @@ define @vfsub_vf_nxv2f16( %va, half %b) s ; ; ZVFHMIN-LABEL: vfsub_vf_nxv2f16: ; ZVFHMIN: # %bb.0: -; ZVFHMIN-NEXT: fcvt.s.h fa5, fa0 -; ZVFHMIN-NEXT: vsetvli a0, zero, e32, m1, ta, ma -; ZVFHMIN-NEXT: vfmv.v.f v9, fa5 -; ZVFHMIN-NEXT: vsetvli zero, zero, e16, mf2, ta, ma -; ZVFHMIN-NEXT: vfncvt.f.f.w v10, v9 -; ZVFHMIN-NEXT: vfwcvt.f.f.v v9, v8 -; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v10 +; ZVFHMIN-NEXT: fmv.x.h a0, fa0 +; ZVFHMIN-NEXT: vsetvli a1, zero, e16, mf2, ta, ma +; ZVFHMIN-NEXT: vmv.v.x v9, a0 +; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v8 +; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v9 ; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m1, ta, ma -; ZVFHMIN-NEXT: vfsub.vv v9, v9, v8 +; ZVFHMIN-NEXT: vfsub.vv v9, v10, v8 ; ZVFHMIN-NEXT: vsetvli zero, zero, e16, mf2, ta, ma ; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v9 ; ZVFHMIN-NEXT: ret @@ -140,11 +136,9 @@ define @vfsub_vf_nxv4f16( %va, half %b) s ; ; ZVFHMIN-LABEL: vfsub_vf_nxv4f16: ; ZVFHMIN: # %bb.0: -; ZVFHMIN-NEXT: fcvt.s.h fa5, fa0 -; ZVFHMIN-NEXT: vsetvli a0, zero, e32, m2, ta, ma -; ZVFHMIN-NEXT: vfmv.v.f v10, fa5 -; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m1, ta, ma -; ZVFHMIN-NEXT: vfncvt.f.f.w v9, v10 +; ZVFHMIN-NEXT: fmv.x.h a0, fa0 +; ZVFHMIN-NEXT: vsetvli a1, zero, e16, m1, ta, ma +; ZVFHMIN-NEXT: vmv.v.x v9, a0 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v8 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v9 ; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m2, ta, ma @@ -190,11 +184,9 @@ define @vfsub_vf_nxv8f16( %va, half %b) s ; ; ZVFHMIN-LABEL: vfsub_vf_nxv8f16: ; ZVFHMIN: # %bb.0: -; ZVFHMIN-NEXT: fcvt.s.h fa5, fa0 -; ZVFHMIN-NEXT: vsetvli a0, zero, e32, m4, ta, ma -; ZVFHMIN-NEXT: vfmv.v.f v12, fa5 -; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m2, ta, ma -; ZVFHMIN-NEXT: vfncvt.f.f.w v10, v12 +; ZVFHMIN-NEXT: fmv.x.h a0, fa0 +; ZVFHMIN-NEXT: vsetvli a1, zero, e16, m2, ta, ma +; ZVFHMIN-NEXT: vmv.v.x v10, a0 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v8 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v10 ; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m4, ta, ma @@ -217,11 +209,9 @@ define @vfsub_fv_nxv8f16( %va, half %b) s ; ; ZVFHMIN-LABEL: vfsub_fv_nxv8f16: ; ZVFHMIN: # %bb.0: -; ZVFHMIN-NEXT: fcvt.s.h fa5, fa0 -; ZVFHMIN-NEXT: vsetvli a0, zero, e32, m4, ta, ma -; ZVFHMIN-NEXT: vfmv.v.f v12, fa5 -; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m2, ta, ma -; ZVFHMIN-NEXT: vfncvt.f.f.w v10, v12 +; ZVFHMIN-NEXT: fmv.x.h a0, fa0 +; ZVFHMIN-NEXT: vsetvli a1, zero, e16, m2, ta, ma +; ZVFHMIN-NEXT: vmv.v.x v10, a0 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v8 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v10 ; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m4, ta, ma @@ -267,11 +257,9 @@ define @vfsub_vf_nxv16f16( %va, half %b ; ; ZVFHMIN-LABEL: vfsub_vf_nxv16f16: ; ZVFHMIN: # %bb.0: -; ZVFHMIN-NEXT: fcvt.s.h fa5, fa0 -; ZVFHMIN-NEXT: vsetvli a0, zero, e32, m8, ta, ma -; ZVFHMIN-NEXT: vfmv.v.f v16, fa5 -; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m4, ta, ma -; ZVFHMIN-NEXT: vfncvt.f.f.w v12, v16 +; ZVFHMIN-NEXT: fmv.x.h a0, fa0 +; ZVFHMIN-NEXT: vsetvli a1, zero, e16, m4, ta, ma +; ZVFHMIN-NEXT: vmv.v.x v12, a0 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v8 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v24, v12 ; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma @@ -323,21 +311,20 @@ define @vfsub_vf_nxv32f16( %va, half %b ; ; ZVFHMIN-LABEL: vfsub_vf_nxv32f16: ; ZVFHMIN: # %bb.0: -; ZVFHMIN-NEXT: fcvt.s.h fa5, fa0 -; ZVFHMIN-NEXT: vsetvli a0, zero, e32, m8, ta, ma -; ZVFHMIN-NEXT: vfmv.v.f v16, fa5 -; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m4, ta, ma -; ZVFHMIN-NEXT: vfncvt.f.f.w v24, v16 -; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v8 -; ZVFHMIN-NEXT: vfwcvt.f.f.v v0, v24 +; ZVFHMIN-NEXT: fmv.x.h a0, fa0 +; ZVFHMIN-NEXT: vsetvli a1, zero, e16, m8, ta, ma +; ZVFHMIN-NEXT: vmv.v.x v16, a0 +; ZVFHMIN-NEXT: vsetvli a0, zero, e16, m4, ta, ma +; ZVFHMIN-NEXT: vfwcvt.f.f.v v24, v8 +; ZVFHMIN-NEXT: vfwcvt.f.f.v v0, v16 ; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma -; ZVFHMIN-NEXT: vfsub.vv v16, v16, v0 +; ZVFHMIN-NEXT: vfsub.vv v24, v24, v0 ; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m4, ta, ma -; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v16 -; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v24 -; ZVFHMIN-NEXT: vfwcvt.f.f.v v24, v12 +; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v24 +; ZVFHMIN-NEXT: vfwcvt.f.f.v v24, v20 +; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v12 ; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma -; ZVFHMIN-NEXT: vfsub.vv v16, v24, v16 +; ZVFHMIN-NEXT: vfsub.vv v16, v16, v24 ; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m4, ta, ma ; ZVFHMIN-NEXT: vfncvt.f.f.w v12, v16 ; ZVFHMIN-NEXT: ret diff --git a/llvm/test/CodeGen/RISCV/rvv/vfsub-sdnode.ll b/llvm/test/CodeGen/RISCV/rvv/vfsub-sdnode.ll index b7941c17dab5ca..bd73398fd04b56 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vfsub-sdnode.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vfsub-sdnode.ll @@ -38,15 +38,13 @@ define @vfsub_vf_nxv1f16( %va, half %b) { ; ; ZVFHMIN-LABEL: vfsub_vf_nxv1f16: ; ZVFHMIN: # %bb.0: -; ZVFHMIN-NEXT: fcvt.s.h fa5, fa0 -; ZVFHMIN-NEXT: vsetvli a0, zero, e32, mf2, ta, ma -; ZVFHMIN-NEXT: vfmv.v.f v9, fa5 -; ZVFHMIN-NEXT: vsetvli zero, zero, e16, mf4, ta, ma -; ZVFHMIN-NEXT: vfncvt.f.f.w v10, v9 -; ZVFHMIN-NEXT: vfwcvt.f.f.v v9, v8 -; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v10 +; ZVFHMIN-NEXT: fmv.x.h a0, fa0 +; ZVFHMIN-NEXT: vsetvli a1, zero, e16, mf4, ta, ma +; ZVFHMIN-NEXT: vmv.v.x v9, a0 +; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v8 +; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v9 ; ZVFHMIN-NEXT: vsetvli zero, zero, e32, mf2, ta, ma -; ZVFHMIN-NEXT: vfsub.vv v9, v9, v8 +; ZVFHMIN-NEXT: vfsub.vv v9, v10, v8 ; ZVFHMIN-NEXT: vsetvli zero, zero, e16, mf4, ta, ma ; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v9 ; ZVFHMIN-NEXT: ret @@ -86,15 +84,13 @@ define @vfsub_vf_nxv2f16( %va, half %b) { ; ; ZVFHMIN-LABEL: vfsub_vf_nxv2f16: ; ZVFHMIN: # %bb.0: -; ZVFHMIN-NEXT: fcvt.s.h fa5, fa0 -; ZVFHMIN-NEXT: vsetvli a0, zero, e32, m1, ta, ma -; ZVFHMIN-NEXT: vfmv.v.f v9, fa5 -; ZVFHMIN-NEXT: vsetvli zero, zero, e16, mf2, ta, ma -; ZVFHMIN-NEXT: vfncvt.f.f.w v10, v9 -; ZVFHMIN-NEXT: vfwcvt.f.f.v v9, v8 -; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v10 +; ZVFHMIN-NEXT: fmv.x.h a0, fa0 +; ZVFHMIN-NEXT: vsetvli a1, zero, e16, mf2, ta, ma +; ZVFHMIN-NEXT: vmv.v.x v9, a0 +; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v8 +; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v9 ; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m1, ta, ma -; ZVFHMIN-NEXT: vfsub.vv v9, v9, v8 +; ZVFHMIN-NEXT: vfsub.vv v9, v10, v8 ; ZVFHMIN-NEXT: vsetvli zero, zero, e16, mf2, ta, ma ; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v9 ; ZVFHMIN-NEXT: ret @@ -134,11 +130,9 @@ define @vfsub_vf_nxv4f16( %va, half %b) { ; ; ZVFHMIN-LABEL: vfsub_vf_nxv4f16: ; ZVFHMIN: # %bb.0: -; ZVFHMIN-NEXT: fcvt.s.h fa5, fa0 -; ZVFHMIN-NEXT: vsetvli a0, zero, e32, m2, ta, ma -; ZVFHMIN-NEXT: vfmv.v.f v10, fa5 -; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m1, ta, ma -; ZVFHMIN-NEXT: vfncvt.f.f.w v9, v10 +; ZVFHMIN-NEXT: fmv.x.h a0, fa0 +; ZVFHMIN-NEXT: vsetvli a1, zero, e16, m1, ta, ma +; ZVFHMIN-NEXT: vmv.v.x v9, a0 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v8 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v9 ; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m2, ta, ma @@ -182,11 +176,9 @@ define @vfsub_vf_nxv8f16( %va, half %b) { ; ; ZVFHMIN-LABEL: vfsub_vf_nxv8f16: ; ZVFHMIN: # %bb.0: -; ZVFHMIN-NEXT: fcvt.s.h fa5, fa0 -; ZVFHMIN-NEXT: vsetvli a0, zero, e32, m4, ta, ma -; ZVFHMIN-NEXT: vfmv.v.f v12, fa5 -; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m2, ta, ma -; ZVFHMIN-NEXT: vfncvt.f.f.w v10, v12 +; ZVFHMIN-NEXT: fmv.x.h a0, fa0 +; ZVFHMIN-NEXT: vsetvli a1, zero, e16, m2, ta, ma +; ZVFHMIN-NEXT: vmv.v.x v10, a0 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v8 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v10 ; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m4, ta, ma @@ -209,11 +201,9 @@ define @vfsub_fv_nxv8f16( %va, half %b) { ; ; ZVFHMIN-LABEL: vfsub_fv_nxv8f16: ; ZVFHMIN: # %bb.0: -; ZVFHMIN-NEXT: fcvt.s.h fa5, fa0 -; ZVFHMIN-NEXT: vsetvli a0, zero, e32, m4, ta, ma -; ZVFHMIN-NEXT: vfmv.v.f v12, fa5 -; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m2, ta, ma -; ZVFHMIN-NEXT: vfncvt.f.f.w v10, v12 +; ZVFHMIN-NEXT: fmv.x.h a0, fa0 +; ZVFHMIN-NEXT: vsetvli a1, zero, e16, m2, ta, ma +; ZVFHMIN-NEXT: vmv.v.x v10, a0 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v8 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v10 ; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m4, ta, ma @@ -257,11 +247,9 @@ define @vfsub_vf_nxv16f16( %va, half %b ; ; ZVFHMIN-LABEL: vfsub_vf_nxv16f16: ; ZVFHMIN: # %bb.0: -; ZVFHMIN-NEXT: fcvt.s.h fa5, fa0 -; ZVFHMIN-NEXT: vsetvli a0, zero, e32, m8, ta, ma -; ZVFHMIN-NEXT: vfmv.v.f v16, fa5 -; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m4, ta, ma -; ZVFHMIN-NEXT: vfncvt.f.f.w v12, v16 +; ZVFHMIN-NEXT: fmv.x.h a0, fa0 +; ZVFHMIN-NEXT: vsetvli a1, zero, e16, m4, ta, ma +; ZVFHMIN-NEXT: vmv.v.x v12, a0 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v8 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v24, v12 ; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma @@ -311,20 +299,20 @@ define @vfsub_vf_nxv32f16( %va, half %b ; ; ZVFHMIN-LABEL: vfsub_vf_nxv32f16: ; ZVFHMIN: # %bb.0: -; ZVFHMIN-NEXT: fcvt.s.h fa5, fa0 -; ZVFHMIN-NEXT: vsetvli a0, zero, e32, m8, ta, ma -; ZVFHMIN-NEXT: vfmv.v.f v16, fa5 -; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m4, ta, ma -; ZVFHMIN-NEXT: vfncvt.f.f.w v24, v16 -; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v8 -; ZVFHMIN-NEXT: vfwcvt.f.f.v v0, v24 +; ZVFHMIN-NEXT: fmv.x.h a0, fa0 +; ZVFHMIN-NEXT: vsetvli a1, zero, e16, m8, ta, ma +; ZVFHMIN-NEXT: vmv.v.x v16, a0 +; ZVFHMIN-NEXT: vsetvli a0, zero, e16, m4, ta, ma +; ZVFHMIN-NEXT: vfwcvt.f.f.v v24, v8 +; ZVFHMIN-NEXT: vfwcvt.f.f.v v0, v16 ; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma -; ZVFHMIN-NEXT: vfsub.vv v16, v16, v0 +; ZVFHMIN-NEXT: vfsub.vv v24, v24, v0 ; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m4, ta, ma -; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v16 -; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v12 +; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v24 +; ZVFHMIN-NEXT: vfwcvt.f.f.v v24, v12 +; ZVFHMIN-NEXT: vfwcvt.f.f.v v0, v20 ; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma -; ZVFHMIN-NEXT: vfsub.vv v16, v16, v0 +; ZVFHMIN-NEXT: vfsub.vv v16, v24, v0 ; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m4, ta, ma ; ZVFHMIN-NEXT: vfncvt.f.f.w v12, v16 ; ZVFHMIN-NEXT: ret diff --git a/llvm/test/CodeGen/RISCV/rvv/vfsub-vp.ll b/llvm/test/CodeGen/RISCV/rvv/vfsub-vp.ll index c833f8048fe32a..fda6d0c48d4a6e 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vfsub-vp.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vfsub-vp.ll @@ -61,15 +61,13 @@ define @vfsub_vf_nxv1f16( %va, half %b, < ; ; ZVFHMIN-LABEL: vfsub_vf_nxv1f16: ; ZVFHMIN: # %bb.0: -; ZVFHMIN-NEXT: fcvt.s.h fa5, fa0 -; ZVFHMIN-NEXT: vsetvli a1, zero, e32, mf2, ta, ma -; ZVFHMIN-NEXT: vfmv.v.f v9, fa5 -; ZVFHMIN-NEXT: vsetvli zero, zero, e16, mf4, ta, ma -; ZVFHMIN-NEXT: vfncvt.f.f.w v10, v9 -; ZVFHMIN-NEXT: vfwcvt.f.f.v v9, v8 -; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v10 +; ZVFHMIN-NEXT: fmv.x.h a1, fa0 +; ZVFHMIN-NEXT: vsetvli a2, zero, e16, mf4, ta, ma +; ZVFHMIN-NEXT: vmv.v.x v9, a1 +; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v8 +; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v9 ; ZVFHMIN-NEXT: vsetvli zero, a0, e32, mf2, ta, ma -; ZVFHMIN-NEXT: vfsub.vv v9, v9, v8, v0.t +; ZVFHMIN-NEXT: vfsub.vv v9, v10, v8, v0.t ; ZVFHMIN-NEXT: vsetvli a0, zero, e16, mf4, ta, ma ; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v9 ; ZVFHMIN-NEXT: ret @@ -88,15 +86,13 @@ define @vfsub_vf_nxv1f16_unmasked( %va, h ; ; ZVFHMIN-LABEL: vfsub_vf_nxv1f16_unmasked: ; ZVFHMIN: # %bb.0: -; ZVFHMIN-NEXT: fcvt.s.h fa5, fa0 -; ZVFHMIN-NEXT: vsetvli a1, zero, e32, mf2, ta, ma -; ZVFHMIN-NEXT: vfmv.v.f v9, fa5 -; ZVFHMIN-NEXT: vsetvli zero, zero, e16, mf4, ta, ma -; ZVFHMIN-NEXT: vfncvt.f.f.w v10, v9 -; ZVFHMIN-NEXT: vfwcvt.f.f.v v9, v8 -; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v10 +; ZVFHMIN-NEXT: fmv.x.h a1, fa0 +; ZVFHMIN-NEXT: vsetvli a2, zero, e16, mf4, ta, ma +; ZVFHMIN-NEXT: vmv.v.x v9, a1 +; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v8 +; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v9 ; ZVFHMIN-NEXT: vsetvli zero, a0, e32, mf2, ta, ma -; ZVFHMIN-NEXT: vfsub.vv v9, v9, v8 +; ZVFHMIN-NEXT: vfsub.vv v9, v10, v8 ; ZVFHMIN-NEXT: vsetvli a0, zero, e16, mf4, ta, ma ; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v9 ; ZVFHMIN-NEXT: ret @@ -159,15 +155,13 @@ define @vfsub_vf_nxv2f16( %va, half %b, < ; ; ZVFHMIN-LABEL: vfsub_vf_nxv2f16: ; ZVFHMIN: # %bb.0: -; ZVFHMIN-NEXT: fcvt.s.h fa5, fa0 -; ZVFHMIN-NEXT: vsetvli a1, zero, e32, m1, ta, ma -; ZVFHMIN-NEXT: vfmv.v.f v9, fa5 -; ZVFHMIN-NEXT: vsetvli zero, zero, e16, mf2, ta, ma -; ZVFHMIN-NEXT: vfncvt.f.f.w v10, v9 -; ZVFHMIN-NEXT: vfwcvt.f.f.v v9, v8 -; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v10 +; ZVFHMIN-NEXT: fmv.x.h a1, fa0 +; ZVFHMIN-NEXT: vsetvli a2, zero, e16, mf2, ta, ma +; ZVFHMIN-NEXT: vmv.v.x v9, a1 +; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v8 +; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v9 ; ZVFHMIN-NEXT: vsetvli zero, a0, e32, m1, ta, ma -; ZVFHMIN-NEXT: vfsub.vv v9, v9, v8, v0.t +; ZVFHMIN-NEXT: vfsub.vv v9, v10, v8, v0.t ; ZVFHMIN-NEXT: vsetvli a0, zero, e16, mf2, ta, ma ; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v9 ; ZVFHMIN-NEXT: ret @@ -186,15 +180,13 @@ define @vfsub_vf_nxv2f16_unmasked( %va, h ; ; ZVFHMIN-LABEL: vfsub_vf_nxv2f16_unmasked: ; ZVFHMIN: # %bb.0: -; ZVFHMIN-NEXT: fcvt.s.h fa5, fa0 -; ZVFHMIN-NEXT: vsetvli a1, zero, e32, m1, ta, ma -; ZVFHMIN-NEXT: vfmv.v.f v9, fa5 -; ZVFHMIN-NEXT: vsetvli zero, zero, e16, mf2, ta, ma -; ZVFHMIN-NEXT: vfncvt.f.f.w v10, v9 -; ZVFHMIN-NEXT: vfwcvt.f.f.v v9, v8 -; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v10 +; ZVFHMIN-NEXT: fmv.x.h a1, fa0 +; ZVFHMIN-NEXT: vsetvli a2, zero, e16, mf2, ta, ma +; ZVFHMIN-NEXT: vmv.v.x v9, a1 +; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v8 +; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v9 ; ZVFHMIN-NEXT: vsetvli zero, a0, e32, m1, ta, ma -; ZVFHMIN-NEXT: vfsub.vv v9, v9, v8 +; ZVFHMIN-NEXT: vfsub.vv v9, v10, v8 ; ZVFHMIN-NEXT: vsetvli a0, zero, e16, mf2, ta, ma ; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v9 ; ZVFHMIN-NEXT: ret @@ -257,11 +249,9 @@ define @vfsub_vf_nxv4f16( %va, half %b, < ; ; ZVFHMIN-LABEL: vfsub_vf_nxv4f16: ; ZVFHMIN: # %bb.0: -; ZVFHMIN-NEXT: fcvt.s.h fa5, fa0 -; ZVFHMIN-NEXT: vsetvli a1, zero, e32, m2, ta, ma -; ZVFHMIN-NEXT: vfmv.v.f v10, fa5 -; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m1, ta, ma -; ZVFHMIN-NEXT: vfncvt.f.f.w v9, v10 +; ZVFHMIN-NEXT: fmv.x.h a1, fa0 +; ZVFHMIN-NEXT: vsetvli a2, zero, e16, m1, ta, ma +; ZVFHMIN-NEXT: vmv.v.x v9, a1 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v8 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v9 ; ZVFHMIN-NEXT: vsetvli zero, a0, e32, m2, ta, ma @@ -284,11 +274,9 @@ define @vfsub_vf_nxv4f16_unmasked( %va, h ; ; ZVFHMIN-LABEL: vfsub_vf_nxv4f16_unmasked: ; ZVFHMIN: # %bb.0: -; ZVFHMIN-NEXT: fcvt.s.h fa5, fa0 -; ZVFHMIN-NEXT: vsetvli a1, zero, e32, m2, ta, ma -; ZVFHMIN-NEXT: vfmv.v.f v10, fa5 -; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m1, ta, ma -; ZVFHMIN-NEXT: vfncvt.f.f.w v9, v10 +; ZVFHMIN-NEXT: fmv.x.h a1, fa0 +; ZVFHMIN-NEXT: vsetvli a2, zero, e16, m1, ta, ma +; ZVFHMIN-NEXT: vmv.v.x v9, a1 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v8 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v9 ; ZVFHMIN-NEXT: vsetvli zero, a0, e32, m2, ta, ma @@ -355,11 +343,9 @@ define @vfsub_vf_nxv8f16( %va, half %b, < ; ; ZVFHMIN-LABEL: vfsub_vf_nxv8f16: ; ZVFHMIN: # %bb.0: -; ZVFHMIN-NEXT: fcvt.s.h fa5, fa0 -; ZVFHMIN-NEXT: vsetvli a1, zero, e32, m4, ta, ma -; ZVFHMIN-NEXT: vfmv.v.f v12, fa5 -; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m2, ta, ma -; ZVFHMIN-NEXT: vfncvt.f.f.w v10, v12 +; ZVFHMIN-NEXT: fmv.x.h a1, fa0 +; ZVFHMIN-NEXT: vsetvli a2, zero, e16, m2, ta, ma +; ZVFHMIN-NEXT: vmv.v.x v10, a1 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v8 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v10 ; ZVFHMIN-NEXT: vsetvli zero, a0, e32, m4, ta, ma @@ -382,11 +368,9 @@ define @vfsub_vf_nxv8f16_unmasked( %va, h ; ; ZVFHMIN-LABEL: vfsub_vf_nxv8f16_unmasked: ; ZVFHMIN: # %bb.0: -; ZVFHMIN-NEXT: fcvt.s.h fa5, fa0 -; ZVFHMIN-NEXT: vsetvli a1, zero, e32, m4, ta, ma -; ZVFHMIN-NEXT: vfmv.v.f v12, fa5 -; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m2, ta, ma -; ZVFHMIN-NEXT: vfncvt.f.f.w v10, v12 +; ZVFHMIN-NEXT: fmv.x.h a1, fa0 +; ZVFHMIN-NEXT: vsetvli a2, zero, e16, m2, ta, ma +; ZVFHMIN-NEXT: vmv.v.x v10, a1 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v8 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v10 ; ZVFHMIN-NEXT: vsetvli zero, a0, e32, m4, ta, ma @@ -453,11 +437,9 @@ define @vfsub_vf_nxv16f16( %va, half %b ; ; ZVFHMIN-LABEL: vfsub_vf_nxv16f16: ; ZVFHMIN: # %bb.0: -; ZVFHMIN-NEXT: fcvt.s.h fa5, fa0 -; ZVFHMIN-NEXT: vsetvli a1, zero, e32, m8, ta, ma -; ZVFHMIN-NEXT: vfmv.v.f v16, fa5 -; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m4, ta, ma -; ZVFHMIN-NEXT: vfncvt.f.f.w v12, v16 +; ZVFHMIN-NEXT: fmv.x.h a1, fa0 +; ZVFHMIN-NEXT: vsetvli a2, zero, e16, m4, ta, ma +; ZVFHMIN-NEXT: vmv.v.x v12, a1 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v8 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v24, v12 ; ZVFHMIN-NEXT: vsetvli zero, a0, e32, m8, ta, ma @@ -480,11 +462,9 @@ define @vfsub_vf_nxv16f16_unmasked( %va ; ; ZVFHMIN-LABEL: vfsub_vf_nxv16f16_unmasked: ; ZVFHMIN: # %bb.0: -; ZVFHMIN-NEXT: fcvt.s.h fa5, fa0 -; ZVFHMIN-NEXT: vsetvli a1, zero, e32, m8, ta, ma -; ZVFHMIN-NEXT: vfmv.v.f v16, fa5 -; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m4, ta, ma -; ZVFHMIN-NEXT: vfncvt.f.f.w v12, v16 +; ZVFHMIN-NEXT: fmv.x.h a1, fa0 +; ZVFHMIN-NEXT: vsetvli a2, zero, e16, m4, ta, ma +; ZVFHMIN-NEXT: vmv.v.x v12, a1 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v8 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v24, v12 ; ZVFHMIN-NEXT: vsetvli zero, a0, e32, m8, ta, ma @@ -624,17 +604,22 @@ define @vfsub_vf_nxv32f16( %va, half %b ; ZVFHMIN-NEXT: addi sp, sp, -16 ; ZVFHMIN-NEXT: .cfi_def_cfa_offset 16 ; ZVFHMIN-NEXT: csrr a1, vlenb -; ZVFHMIN-NEXT: slli a1, a1, 2 +; ZVFHMIN-NEXT: slli a1, a1, 1 +; ZVFHMIN-NEXT: mv a2, a1 +; ZVFHMIN-NEXT: slli a1, a1, 3 +; ZVFHMIN-NEXT: add a1, a1, a2 ; ZVFHMIN-NEXT: sub sp, sp, a1 -; ZVFHMIN-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x04, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 4 * vlenb -; ZVFHMIN-NEXT: vmv1r.v v7, v0 -; ZVFHMIN-NEXT: fcvt.s.h fa5, fa0 -; ZVFHMIN-NEXT: vsetvli a1, zero, e32, m8, ta, ma -; ZVFHMIN-NEXT: vfmv.v.f v24, fa5 -; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m4, ta, ma -; ZVFHMIN-NEXT: vfncvt.f.f.w v16, v24 -; ZVFHMIN-NEXT: addi a1, sp, 16 -; ZVFHMIN-NEXT: vs4r.v v16, (a1) # Unknown-size Folded Spill +; ZVFHMIN-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x12, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 18 * vlenb +; ZVFHMIN-NEXT: vmv8r.v v24, v8 +; ZVFHMIN-NEXT: fmv.x.h a1, fa0 +; ZVFHMIN-NEXT: vsetvli a2, zero, e16, m8, ta, ma +; ZVFHMIN-NEXT: vmv.v.x v16, a1 +; ZVFHMIN-NEXT: csrr a1, vlenb +; ZVFHMIN-NEXT: slli a2, a1, 3 +; ZVFHMIN-NEXT: add a1, a2, a1 +; ZVFHMIN-NEXT: add a1, sp, a1 +; ZVFHMIN-NEXT: addi a1, a1, 16 +; ZVFHMIN-NEXT: vs8r.v v16, (a1) # Unknown-size Folded Spill ; ZVFHMIN-NEXT: csrr a2, vlenb ; ZVFHMIN-NEXT: slli a1, a2, 1 ; ZVFHMIN-NEXT: sub a3, a0, a1 @@ -642,29 +627,56 @@ define @vfsub_vf_nxv32f16( %va, half %b ; ZVFHMIN-NEXT: addi a4, a4, -1 ; ZVFHMIN-NEXT: and a3, a4, a3 ; ZVFHMIN-NEXT: srli a2, a2, 2 +; ZVFHMIN-NEXT: csrr a4, vlenb +; ZVFHMIN-NEXT: slli a4, a4, 3 +; ZVFHMIN-NEXT: add a4, sp, a4 +; ZVFHMIN-NEXT: addi a4, a4, 16 +; ZVFHMIN-NEXT: vs1r.v v0, (a4) # Unknown-size Folded Spill ; ZVFHMIN-NEXT: vsetvli a4, zero, e8, mf2, ta, ma ; ZVFHMIN-NEXT: vslidedown.vx v0, v0, a2 -; ZVFHMIN-NEXT: vsetvli a2, zero, e16, m4, ta, ma -; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v12 ; ZVFHMIN-NEXT: addi a2, sp, 16 -; ZVFHMIN-NEXT: vl4r.v v12, (a2) # Unknown-size Folded Reload -; ZVFHMIN-NEXT: vfwcvt.f.f.v v24, v12 +; ZVFHMIN-NEXT: vs8r.v v8, (a2) # Unknown-size Folded Spill +; ZVFHMIN-NEXT: vsetvli a2, zero, e16, m4, ta, ma +; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v28 +; ZVFHMIN-NEXT: csrr a2, vlenb +; ZVFHMIN-NEXT: slli a4, a2, 3 +; ZVFHMIN-NEXT: add a2, a4, a2 +; ZVFHMIN-NEXT: add a2, sp, a2 +; ZVFHMIN-NEXT: addi a2, a2, 16 +; ZVFHMIN-NEXT: vl8r.v v24, (a2) # Unknown-size Folded Reload +; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v28 ; ZVFHMIN-NEXT: vsetvli zero, a3, e32, m8, ta, ma -; ZVFHMIN-NEXT: vfsub.vv v16, v16, v24, v0.t +; ZVFHMIN-NEXT: vfsub.vv v16, v8, v16, v0.t ; ZVFHMIN-NEXT: vsetvli a2, zero, e16, m4, ta, ma ; ZVFHMIN-NEXT: vfncvt.f.f.w v12, v16 ; ZVFHMIN-NEXT: bltu a0, a1, .LBB22_2 ; ZVFHMIN-NEXT: # %bb.1: ; ZVFHMIN-NEXT: mv a0, a1 ; ZVFHMIN-NEXT: .LBB22_2: -; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v8 -; ZVFHMIN-NEXT: vmv1r.v v0, v7 +; ZVFHMIN-NEXT: addi a1, sp, 16 +; ZVFHMIN-NEXT: vl8r.v v24, (a1) # Unknown-size Folded Reload +; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v24 +; ZVFHMIN-NEXT: csrr a1, vlenb +; ZVFHMIN-NEXT: slli a2, a1, 3 +; ZVFHMIN-NEXT: add a1, a2, a1 +; ZVFHMIN-NEXT: add a1, sp, a1 +; ZVFHMIN-NEXT: addi a1, a1, 16 +; ZVFHMIN-NEXT: vl8r.v v0, (a1) # Unknown-size Folded Reload +; ZVFHMIN-NEXT: vfwcvt.f.f.v v24, v0 +; ZVFHMIN-NEXT: csrr a1, vlenb +; ZVFHMIN-NEXT: slli a1, a1, 3 +; ZVFHMIN-NEXT: add a1, sp, a1 +; ZVFHMIN-NEXT: addi a1, a1, 16 +; ZVFHMIN-NEXT: vl1r.v v0, (a1) # Unknown-size Folded Reload ; ZVFHMIN-NEXT: vsetvli zero, a0, e32, m8, ta, ma ; ZVFHMIN-NEXT: vfsub.vv v16, v16, v24, v0.t ; ZVFHMIN-NEXT: vsetvli a0, zero, e16, m4, ta, ma ; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v16 ; ZVFHMIN-NEXT: csrr a0, vlenb -; ZVFHMIN-NEXT: slli a0, a0, 2 +; ZVFHMIN-NEXT: slli a0, a0, 1 +; ZVFHMIN-NEXT: mv a1, a0 +; ZVFHMIN-NEXT: slli a0, a0, 3 +; ZVFHMIN-NEXT: add a0, a0, a1 ; ZVFHMIN-NEXT: add sp, sp, a0 ; ZVFHMIN-NEXT: addi sp, sp, 16 ; ZVFHMIN-NEXT: ret @@ -683,11 +695,16 @@ define @vfsub_vf_nxv32f16_unmasked( %va ; ; ZVFHMIN-LABEL: vfsub_vf_nxv32f16_unmasked: ; ZVFHMIN: # %bb.0: -; ZVFHMIN-NEXT: fcvt.s.h fa5, fa0 -; ZVFHMIN-NEXT: vsetvli a1, zero, e32, m8, ta, ma -; ZVFHMIN-NEXT: vfmv.v.f v16, fa5 -; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m4, ta, ma -; ZVFHMIN-NEXT: vfncvt.f.f.w v4, v16 +; ZVFHMIN-NEXT: addi sp, sp, -16 +; ZVFHMIN-NEXT: .cfi_def_cfa_offset 16 +; ZVFHMIN-NEXT: csrr a1, vlenb +; ZVFHMIN-NEXT: slli a1, a1, 4 +; ZVFHMIN-NEXT: sub sp, sp, a1 +; ZVFHMIN-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x10, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 16 * vlenb +; ZVFHMIN-NEXT: vmv8r.v v16, v8 +; ZVFHMIN-NEXT: fmv.x.h a1, fa0 +; ZVFHMIN-NEXT: vsetvli a2, zero, e16, m8, ta, ma +; ZVFHMIN-NEXT: vmv.v.x v8, a1 ; ZVFHMIN-NEXT: csrr a2, vlenb ; ZVFHMIN-NEXT: slli a1, a2, 1 ; ZVFHMIN-NEXT: sub a3, a0, a1 @@ -695,26 +712,45 @@ define @vfsub_vf_nxv32f16_unmasked( %va ; ZVFHMIN-NEXT: addi a4, a4, -1 ; ZVFHMIN-NEXT: and a3, a4, a3 ; ZVFHMIN-NEXT: srli a2, a2, 2 -; ZVFHMIN-NEXT: vsetvli a4, zero, e8, m4, ta, ma -; ZVFHMIN-NEXT: vmset.m v16 +; ZVFHMIN-NEXT: vmset.m v24 ; ZVFHMIN-NEXT: vsetvli a4, zero, e8, mf2, ta, ma -; ZVFHMIN-NEXT: vslidedown.vx v0, v16, a2 +; ZVFHMIN-NEXT: vslidedown.vx v0, v24, a2 +; ZVFHMIN-NEXT: addi a2, sp, 16 +; ZVFHMIN-NEXT: vs8r.v v16, (a2) # Unknown-size Folded Spill ; ZVFHMIN-NEXT: vsetvli a2, zero, e16, m4, ta, ma -; ZVFHMIN-NEXT: vfwcvt.f.f.v v24, v12 -; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v4 +; ZVFHMIN-NEXT: vfwcvt.f.f.v v24, v20 +; ZVFHMIN-NEXT: vmv4r.v v16, v8 +; ZVFHMIN-NEXT: csrr a2, vlenb +; ZVFHMIN-NEXT: slli a2, a2, 3 +; ZVFHMIN-NEXT: add a2, sp, a2 +; ZVFHMIN-NEXT: addi a2, a2, 16 +; ZVFHMIN-NEXT: vs8r.v v16, (a2) # Unknown-size Folded Spill +; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v12 ; ZVFHMIN-NEXT: vsetvli zero, a3, e32, m8, ta, ma -; ZVFHMIN-NEXT: vfsub.vv v24, v24, v16, v0.t +; ZVFHMIN-NEXT: vfsub.vv v16, v24, v16, v0.t ; ZVFHMIN-NEXT: vsetvli a2, zero, e16, m4, ta, ma -; ZVFHMIN-NEXT: vfncvt.f.f.w v12, v24 +; ZVFHMIN-NEXT: vfncvt.f.f.w v12, v16 ; ZVFHMIN-NEXT: bltu a0, a1, .LBB23_2 ; ZVFHMIN-NEXT: # %bb.1: ; ZVFHMIN-NEXT: mv a0, a1 ; ZVFHMIN-NEXT: .LBB23_2: -; ZVFHMIN-NEXT: vfwcvt.f.f.v v24, v8 +; ZVFHMIN-NEXT: addi a1, sp, 16 +; ZVFHMIN-NEXT: vl8r.v v24, (a1) # Unknown-size Folded Reload +; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v24 +; ZVFHMIN-NEXT: csrr a1, vlenb +; ZVFHMIN-NEXT: slli a1, a1, 3 +; ZVFHMIN-NEXT: add a1, sp, a1 +; ZVFHMIN-NEXT: addi a1, a1, 16 +; ZVFHMIN-NEXT: vl8r.v v0, (a1) # Unknown-size Folded Reload +; ZVFHMIN-NEXT: vfwcvt.f.f.v v24, v0 ; ZVFHMIN-NEXT: vsetvli zero, a0, e32, m8, ta, ma -; ZVFHMIN-NEXT: vfsub.vv v16, v24, v16 +; ZVFHMIN-NEXT: vfsub.vv v16, v16, v24 ; ZVFHMIN-NEXT: vsetvli a0, zero, e16, m4, ta, ma ; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v16 +; ZVFHMIN-NEXT: csrr a0, vlenb +; ZVFHMIN-NEXT: slli a0, a0, 4 +; ZVFHMIN-NEXT: add sp, sp, a0 +; ZVFHMIN-NEXT: addi sp, sp, 16 ; ZVFHMIN-NEXT: ret %elt.head = insertelement poison, half %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer diff --git a/llvm/test/CodeGen/RISCV/rvv/vfwmacc-vp.ll b/llvm/test/CodeGen/RISCV/rvv/vfwmacc-vp.ll index f635b61fc3e5b9..80ada4670562d7 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vfwmacc-vp.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vfwmacc-vp.ll @@ -142,16 +142,14 @@ define @vfmacc_vf_nxv1f32( %va, half %b, ; ; ZVFHMIN-LABEL: vfmacc_vf_nxv1f32: ; ZVFHMIN: # %bb.0: -; ZVFHMIN-NEXT: fcvt.s.h fa5, fa0 -; ZVFHMIN-NEXT: vsetvli a1, zero, e32, mf2, ta, ma -; ZVFHMIN-NEXT: vfmv.v.f v10, fa5 -; ZVFHMIN-NEXT: vsetvli zero, zero, e16, mf4, ta, ma -; ZVFHMIN-NEXT: vfncvt.f.f.w v11, v10 +; ZVFHMIN-NEXT: fmv.x.h a1, fa0 +; ZVFHMIN-NEXT: vsetvli a2, zero, e16, mf4, ta, ma +; ZVFHMIN-NEXT: vmv.v.x v10, a1 ; ZVFHMIN-NEXT: vsetvli zero, a0, e16, mf4, ta, ma -; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v8, v0.t -; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v11, v0.t +; ZVFHMIN-NEXT: vfwcvt.f.f.v v11, v8, v0.t +; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v10, v0.t ; ZVFHMIN-NEXT: vsetvli zero, zero, e32, mf2, ta, ma -; ZVFHMIN-NEXT: vfmadd.vv v8, v10, v9, v0.t +; ZVFHMIN-NEXT: vfmadd.vv v8, v11, v9, v0.t ; ZVFHMIN-NEXT: ret %elt.head = insertelement poison, half %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer @@ -171,11 +169,9 @@ define @vfmacc_vf_nxv1f32_commute( %va, ; ; ZVFHMIN-LABEL: vfmacc_vf_nxv1f32_commute: ; ZVFHMIN: # %bb.0: -; ZVFHMIN-NEXT: fcvt.s.h fa5, fa0 -; ZVFHMIN-NEXT: vsetvli a1, zero, e32, mf2, ta, ma -; ZVFHMIN-NEXT: vfmv.v.f v10, fa5 -; ZVFHMIN-NEXT: vsetvli zero, zero, e16, mf4, ta, ma -; ZVFHMIN-NEXT: vfncvt.f.f.w v11, v10 +; ZVFHMIN-NEXT: fmv.x.h a1, fa0 +; ZVFHMIN-NEXT: vsetvli a2, zero, e16, mf4, ta, ma +; ZVFHMIN-NEXT: vmv.v.x v11, a1 ; ZVFHMIN-NEXT: vsetvli zero, a0, e16, mf4, ta, ma ; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v8, v0.t ; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v11, v0.t @@ -201,16 +197,14 @@ define @vfmacc_vf_nxv1f32_unmasked( %va, ; ; ZVFHMIN-LABEL: vfmacc_vf_nxv1f32_unmasked: ; ZVFHMIN: # %bb.0: -; ZVFHMIN-NEXT: fcvt.s.h fa5, fa0 -; ZVFHMIN-NEXT: vsetvli a1, zero, e32, mf2, ta, ma -; ZVFHMIN-NEXT: vfmv.v.f v10, fa5 -; ZVFHMIN-NEXT: vsetvli zero, zero, e16, mf4, ta, ma -; ZVFHMIN-NEXT: vfncvt.f.f.w v11, v10 +; ZVFHMIN-NEXT: fmv.x.h a1, fa0 +; ZVFHMIN-NEXT: vsetvli a2, zero, e16, mf4, ta, ma +; ZVFHMIN-NEXT: vmv.v.x v10, a1 ; ZVFHMIN-NEXT: vsetvli zero, a0, e16, mf4, ta, ma -; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v8 -; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v11 +; ZVFHMIN-NEXT: vfwcvt.f.f.v v11, v8 +; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v10 ; ZVFHMIN-NEXT: vsetvli zero, zero, e32, mf2, ta, ma -; ZVFHMIN-NEXT: vfmadd.vv v8, v10, v9 +; ZVFHMIN-NEXT: vfmadd.vv v8, v11, v9 ; ZVFHMIN-NEXT: ret %elt.head = insertelement poison, half %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer @@ -230,16 +224,14 @@ define @vfmacc_vf_nxv1f32_tu( %va, half ; ; ZVFHMIN-LABEL: vfmacc_vf_nxv1f32_tu: ; ZVFHMIN: # %bb.0: -; ZVFHMIN-NEXT: fcvt.s.h fa5, fa0 -; ZVFHMIN-NEXT: vsetvli a1, zero, e32, mf2, ta, ma -; ZVFHMIN-NEXT: vfmv.v.f v10, fa5 -; ZVFHMIN-NEXT: vsetvli zero, zero, e16, mf4, ta, ma -; ZVFHMIN-NEXT: vfncvt.f.f.w v11, v10 +; ZVFHMIN-NEXT: fmv.x.h a1, fa0 +; ZVFHMIN-NEXT: vsetvli a2, zero, e16, mf4, ta, ma +; ZVFHMIN-NEXT: vmv.v.x v10, a1 ; ZVFHMIN-NEXT: vsetvli zero, a0, e16, mf4, ta, ma -; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v8 -; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v11 +; ZVFHMIN-NEXT: vfwcvt.f.f.v v11, v8 +; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v10 ; ZVFHMIN-NEXT: vsetvli zero, zero, e32, mf2, tu, mu -; ZVFHMIN-NEXT: vfmacc.vv v9, v10, v8, v0.t +; ZVFHMIN-NEXT: vfmacc.vv v9, v11, v8, v0.t ; ZVFHMIN-NEXT: vmv1r.v v8, v9 ; ZVFHMIN-NEXT: ret %elt.head = insertelement poison, half %b, i32 0 @@ -261,16 +253,14 @@ define @vfmacc_vf_nxv1f32_commute_tu( %v ; ; ZVFHMIN-LABEL: vfmacc_vf_nxv1f32_commute_tu: ; ZVFHMIN: # %bb.0: -; ZVFHMIN-NEXT: fcvt.s.h fa5, fa0 -; ZVFHMIN-NEXT: vsetvli a1, zero, e32, mf2, ta, ma -; ZVFHMIN-NEXT: vfmv.v.f v10, fa5 -; ZVFHMIN-NEXT: vsetvli zero, zero, e16, mf4, ta, ma -; ZVFHMIN-NEXT: vfncvt.f.f.w v11, v10 +; ZVFHMIN-NEXT: fmv.x.h a1, fa0 +; ZVFHMIN-NEXT: vsetvli a2, zero, e16, mf4, ta, ma +; ZVFHMIN-NEXT: vmv.v.x v10, a1 ; ZVFHMIN-NEXT: vsetvli zero, a0, e16, mf4, ta, ma -; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v8 -; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v11 +; ZVFHMIN-NEXT: vfwcvt.f.f.v v11, v8 +; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v10 ; ZVFHMIN-NEXT: vsetvli zero, zero, e32, mf2, tu, mu -; ZVFHMIN-NEXT: vfmacc.vv v9, v8, v10, v0.t +; ZVFHMIN-NEXT: vfmacc.vv v9, v8, v11, v0.t ; ZVFHMIN-NEXT: vmv1r.v v8, v9 ; ZVFHMIN-NEXT: ret %elt.head = insertelement poison, half %b, i32 0 @@ -292,16 +282,14 @@ define @vfmacc_vf_nxv1f32_unmasked_tu( % ; ; ZVFHMIN-LABEL: vfmacc_vf_nxv1f32_unmasked_tu: ; ZVFHMIN: # %bb.0: -; ZVFHMIN-NEXT: fcvt.s.h fa5, fa0 -; ZVFHMIN-NEXT: vsetvli a1, zero, e32, mf2, ta, ma -; ZVFHMIN-NEXT: vfmv.v.f v10, fa5 -; ZVFHMIN-NEXT: vsetvli zero, zero, e16, mf4, ta, ma -; ZVFHMIN-NEXT: vfncvt.f.f.w v11, v10 +; ZVFHMIN-NEXT: fmv.x.h a1, fa0 +; ZVFHMIN-NEXT: vsetvli a2, zero, e16, mf4, ta, ma +; ZVFHMIN-NEXT: vmv.v.x v10, a1 ; ZVFHMIN-NEXT: vsetvli zero, a0, e16, mf4, ta, ma -; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v8 -; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v11 +; ZVFHMIN-NEXT: vfwcvt.f.f.v v11, v8 +; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v10 ; ZVFHMIN-NEXT: vsetvli zero, zero, e32, mf2, tu, ma -; ZVFHMIN-NEXT: vfmacc.vv v9, v10, v8 +; ZVFHMIN-NEXT: vfmacc.vv v9, v11, v8 ; ZVFHMIN-NEXT: vmv1r.v v8, v9 ; ZVFHMIN-NEXT: ret %elt.head = insertelement poison, half %b, i32 0 @@ -373,16 +361,14 @@ define @vfmacc_vf_nxv2f32( %va, half %b, ; ; ZVFHMIN-LABEL: vfmacc_vf_nxv2f32: ; ZVFHMIN: # %bb.0: -; ZVFHMIN-NEXT: fcvt.s.h fa5, fa0 -; ZVFHMIN-NEXT: vsetvli a1, zero, e32, m1, ta, ma -; ZVFHMIN-NEXT: vfmv.v.f v10, fa5 -; ZVFHMIN-NEXT: vsetvli zero, zero, e16, mf2, ta, ma -; ZVFHMIN-NEXT: vfncvt.f.f.w v11, v10 +; ZVFHMIN-NEXT: fmv.x.h a1, fa0 +; ZVFHMIN-NEXT: vsetvli a2, zero, e16, mf2, ta, ma +; ZVFHMIN-NEXT: vmv.v.x v10, a1 ; ZVFHMIN-NEXT: vsetvli zero, a0, e16, mf2, ta, ma -; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v8, v0.t -; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v11, v0.t +; ZVFHMIN-NEXT: vfwcvt.f.f.v v11, v8, v0.t +; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v10, v0.t ; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m1, ta, ma -; ZVFHMIN-NEXT: vfmadd.vv v8, v10, v9, v0.t +; ZVFHMIN-NEXT: vfmadd.vv v8, v11, v9, v0.t ; ZVFHMIN-NEXT: ret %elt.head = insertelement poison, half %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer @@ -402,16 +388,14 @@ define @vfmacc_vf_nxv2f32_unmasked( %va, ; ; ZVFHMIN-LABEL: vfmacc_vf_nxv2f32_unmasked: ; ZVFHMIN: # %bb.0: -; ZVFHMIN-NEXT: fcvt.s.h fa5, fa0 -; ZVFHMIN-NEXT: vsetvli a1, zero, e32, m1, ta, ma -; ZVFHMIN-NEXT: vfmv.v.f v10, fa5 -; ZVFHMIN-NEXT: vsetvli zero, zero, e16, mf2, ta, ma -; ZVFHMIN-NEXT: vfncvt.f.f.w v11, v10 +; ZVFHMIN-NEXT: fmv.x.h a1, fa0 +; ZVFHMIN-NEXT: vsetvli a2, zero, e16, mf2, ta, ma +; ZVFHMIN-NEXT: vmv.v.x v10, a1 ; ZVFHMIN-NEXT: vsetvli zero, a0, e16, mf2, ta, ma -; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v8 -; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v11 +; ZVFHMIN-NEXT: vfwcvt.f.f.v v11, v8 +; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v10 ; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m1, ta, ma -; ZVFHMIN-NEXT: vfmadd.vv v8, v10, v9 +; ZVFHMIN-NEXT: vfmadd.vv v8, v11, v9 ; ZVFHMIN-NEXT: ret %elt.head = insertelement poison, half %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer @@ -483,16 +467,14 @@ define @vfmacc_vf_nxv4f32( %va, half %b, ; ; ZVFHMIN-LABEL: vfmacc_vf_nxv4f32: ; ZVFHMIN: # %bb.0: -; ZVFHMIN-NEXT: fcvt.s.h fa5, fa0 -; ZVFHMIN-NEXT: vsetvli a1, zero, e32, m2, ta, ma -; ZVFHMIN-NEXT: vfmv.v.f v12, fa5 -; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m1, ta, ma -; ZVFHMIN-NEXT: vfncvt.f.f.w v14, v12 +; ZVFHMIN-NEXT: fmv.x.h a1, fa0 +; ZVFHMIN-NEXT: vsetvli a2, zero, e16, m1, ta, ma +; ZVFHMIN-NEXT: vmv.v.x v12, a1 ; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m1, ta, ma -; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v8, v0.t -; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v14, v0.t +; ZVFHMIN-NEXT: vfwcvt.f.f.v v14, v8, v0.t +; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v12, v0.t ; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m2, ta, ma -; ZVFHMIN-NEXT: vfmadd.vv v8, v12, v10, v0.t +; ZVFHMIN-NEXT: vfmadd.vv v8, v14, v10, v0.t ; ZVFHMIN-NEXT: ret %elt.head = insertelement poison, half %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer @@ -512,16 +494,14 @@ define @vfmacc_vf_nxv4f32_unmasked( %va, ; ; ZVFHMIN-LABEL: vfmacc_vf_nxv4f32_unmasked: ; ZVFHMIN: # %bb.0: -; ZVFHMIN-NEXT: fcvt.s.h fa5, fa0 -; ZVFHMIN-NEXT: vsetvli a1, zero, e32, m2, ta, ma -; ZVFHMIN-NEXT: vfmv.v.f v12, fa5 -; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m1, ta, ma -; ZVFHMIN-NEXT: vfncvt.f.f.w v14, v12 +; ZVFHMIN-NEXT: fmv.x.h a1, fa0 +; ZVFHMIN-NEXT: vsetvli a2, zero, e16, m1, ta, ma +; ZVFHMIN-NEXT: vmv.v.x v12, a1 ; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m1, ta, ma -; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v8 -; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v14 +; ZVFHMIN-NEXT: vfwcvt.f.f.v v14, v8 +; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v12 ; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m2, ta, ma -; ZVFHMIN-NEXT: vfmadd.vv v8, v12, v10 +; ZVFHMIN-NEXT: vfmadd.vv v8, v14, v10 ; ZVFHMIN-NEXT: ret %elt.head = insertelement poison, half %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer @@ -593,16 +573,14 @@ define @vfmacc_vf_nxv8f32( %va, half %b, ; ; ZVFHMIN-LABEL: vfmacc_vf_nxv8f32: ; ZVFHMIN: # %bb.0: -; ZVFHMIN-NEXT: fcvt.s.h fa5, fa0 -; ZVFHMIN-NEXT: vsetvli a1, zero, e32, m4, ta, ma -; ZVFHMIN-NEXT: vfmv.v.f v16, fa5 -; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m2, ta, ma -; ZVFHMIN-NEXT: vfncvt.f.f.w v20, v16 +; ZVFHMIN-NEXT: fmv.x.h a1, fa0 +; ZVFHMIN-NEXT: vsetvli a2, zero, e16, m2, ta, ma +; ZVFHMIN-NEXT: vmv.v.x v16, a1 ; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m2, ta, ma -; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v8, v0.t -; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v20, v0.t +; ZVFHMIN-NEXT: vfwcvt.f.f.v v20, v8, v0.t +; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v16, v0.t ; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m4, ta, ma -; ZVFHMIN-NEXT: vfmadd.vv v8, v16, v12, v0.t +; ZVFHMIN-NEXT: vfmadd.vv v8, v20, v12, v0.t ; ZVFHMIN-NEXT: ret %elt.head = insertelement poison, half %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer @@ -622,16 +600,14 @@ define @vfmacc_vf_nxv8f32_unmasked( %va, ; ; ZVFHMIN-LABEL: vfmacc_vf_nxv8f32_unmasked: ; ZVFHMIN: # %bb.0: -; ZVFHMIN-NEXT: fcvt.s.h fa5, fa0 -; ZVFHMIN-NEXT: vsetvli a1, zero, e32, m4, ta, ma -; ZVFHMIN-NEXT: vfmv.v.f v16, fa5 -; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m2, ta, ma -; ZVFHMIN-NEXT: vfncvt.f.f.w v20, v16 +; ZVFHMIN-NEXT: fmv.x.h a1, fa0 +; ZVFHMIN-NEXT: vsetvli a2, zero, e16, m2, ta, ma +; ZVFHMIN-NEXT: vmv.v.x v16, a1 ; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m2, ta, ma -; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v8 -; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v20 +; ZVFHMIN-NEXT: vfwcvt.f.f.v v20, v8 +; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v16 ; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m4, ta, ma -; ZVFHMIN-NEXT: vfmadd.vv v8, v16, v12 +; ZVFHMIN-NEXT: vfmadd.vv v8, v20, v12 ; ZVFHMIN-NEXT: ret %elt.head = insertelement poison, half %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer @@ -717,11 +693,9 @@ define @vfmacc_vf_nxv16f32( %va, half ; ; ZVFHMIN-LABEL: vfmacc_vf_nxv16f32: ; ZVFHMIN: # %bb.0: -; ZVFHMIN-NEXT: fcvt.s.h fa5, fa0 -; ZVFHMIN-NEXT: vsetvli a1, zero, e32, m8, ta, ma -; ZVFHMIN-NEXT: vfmv.v.f v24, fa5 -; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m4, ta, ma -; ZVFHMIN-NEXT: vfncvt.f.f.w v4, v24 +; ZVFHMIN-NEXT: fmv.x.h a1, fa0 +; ZVFHMIN-NEXT: vsetvli a2, zero, e16, m4, ta, ma +; ZVFHMIN-NEXT: vmv.v.x v4, a1 ; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m4, ta, ma ; ZVFHMIN-NEXT: vfwcvt.f.f.v v24, v8, v0.t ; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v4, v0.t @@ -746,16 +720,14 @@ define @vfmacc_vf_nxv16f32_unmasked( % ; ; ZVFHMIN-LABEL: vfmacc_vf_nxv16f32_unmasked: ; ZVFHMIN: # %bb.0: -; ZVFHMIN-NEXT: fcvt.s.h fa5, fa0 -; ZVFHMIN-NEXT: vsetvli a1, zero, e32, m8, ta, ma -; ZVFHMIN-NEXT: vfmv.v.f v24, fa5 -; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m4, ta, ma -; ZVFHMIN-NEXT: vfncvt.f.f.w v4, v24 +; ZVFHMIN-NEXT: fmv.x.h a1, fa0 +; ZVFHMIN-NEXT: vsetvli a2, zero, e16, m4, ta, ma +; ZVFHMIN-NEXT: vmv.v.x v24, a1 ; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m4, ta, ma -; ZVFHMIN-NEXT: vfwcvt.f.f.v v24, v8 -; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v4 +; ZVFHMIN-NEXT: vfwcvt.f.f.v v0, v8 +; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v24 ; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma -; ZVFHMIN-NEXT: vfmadd.vv v8, v24, v16 +; ZVFHMIN-NEXT: vfmadd.vv v8, v0, v16 ; ZVFHMIN-NEXT: ret %elt.head = insertelement poison, half %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer diff --git a/llvm/test/CodeGen/RISCV/rvv/vfwmsac-vp.ll b/llvm/test/CodeGen/RISCV/rvv/vfwmsac-vp.ll index 4cd9b8bc2cdede..c92a79e49c1642 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vfwmsac-vp.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vfwmsac-vp.ll @@ -119,16 +119,14 @@ define @vmfsac_vf_nxv1f32( %a, half %b, ; ; ZVFHMIN-LABEL: vmfsac_vf_nxv1f32: ; ZVFHMIN: # %bb.0: -; ZVFHMIN-NEXT: fcvt.s.h fa5, fa0 -; ZVFHMIN-NEXT: vsetvli a1, zero, e32, mf2, ta, ma -; ZVFHMIN-NEXT: vfmv.v.f v10, fa5 -; ZVFHMIN-NEXT: vsetvli zero, zero, e16, mf4, ta, ma -; ZVFHMIN-NEXT: vfncvt.f.f.w v11, v10 +; ZVFHMIN-NEXT: fmv.x.h a1, fa0 +; ZVFHMIN-NEXT: vsetvli a2, zero, e16, mf4, ta, ma +; ZVFHMIN-NEXT: vmv.v.x v10, a1 ; ZVFHMIN-NEXT: vsetvli zero, a0, e16, mf4, ta, ma -; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v8, v0.t -; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v11, v0.t +; ZVFHMIN-NEXT: vfwcvt.f.f.v v11, v8, v0.t +; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v10, v0.t ; ZVFHMIN-NEXT: vsetvli zero, zero, e32, mf2, ta, ma -; ZVFHMIN-NEXT: vfmsub.vv v8, v10, v9, v0.t +; ZVFHMIN-NEXT: vfmsub.vv v8, v11, v9, v0.t ; ZVFHMIN-NEXT: ret %elt.head = insertelement poison, half %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer @@ -149,11 +147,9 @@ define @vmfsac_vf_nxv1f32_commute( %a, h ; ; ZVFHMIN-LABEL: vmfsac_vf_nxv1f32_commute: ; ZVFHMIN: # %bb.0: -; ZVFHMIN-NEXT: fcvt.s.h fa5, fa0 -; ZVFHMIN-NEXT: vsetvli a1, zero, e32, mf2, ta, ma -; ZVFHMIN-NEXT: vfmv.v.f v10, fa5 -; ZVFHMIN-NEXT: vsetvli zero, zero, e16, mf4, ta, ma -; ZVFHMIN-NEXT: vfncvt.f.f.w v11, v10 +; ZVFHMIN-NEXT: fmv.x.h a1, fa0 +; ZVFHMIN-NEXT: vsetvli a2, zero, e16, mf4, ta, ma +; ZVFHMIN-NEXT: vmv.v.x v11, a1 ; ZVFHMIN-NEXT: vsetvli zero, a0, e16, mf4, ta, ma ; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v8, v0.t ; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v11, v0.t @@ -180,16 +176,14 @@ define @vmfsac_vf_nxv1f32_unmasked( %a, ; ; ZVFHMIN-LABEL: vmfsac_vf_nxv1f32_unmasked: ; ZVFHMIN: # %bb.0: -; ZVFHMIN-NEXT: fcvt.s.h fa5, fa0 -; ZVFHMIN-NEXT: vsetvli a1, zero, e32, mf2, ta, ma -; ZVFHMIN-NEXT: vfmv.v.f v10, fa5 -; ZVFHMIN-NEXT: vsetvli zero, zero, e16, mf4, ta, ma -; ZVFHMIN-NEXT: vfncvt.f.f.w v11, v10 +; ZVFHMIN-NEXT: fmv.x.h a1, fa0 +; ZVFHMIN-NEXT: vsetvli a2, zero, e16, mf4, ta, ma +; ZVFHMIN-NEXT: vmv.v.x v10, a1 ; ZVFHMIN-NEXT: vsetvli zero, a0, e16, mf4, ta, ma -; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v8 -; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v11 +; ZVFHMIN-NEXT: vfwcvt.f.f.v v11, v8 +; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v10 ; ZVFHMIN-NEXT: vsetvli zero, zero, e32, mf2, ta, ma -; ZVFHMIN-NEXT: vfmsub.vv v8, v10, v9 +; ZVFHMIN-NEXT: vfmsub.vv v8, v11, v9 ; ZVFHMIN-NEXT: ret %elt.head = insertelement poison, half %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer @@ -260,16 +254,14 @@ define @vmfsac_vf_nxv2f32( %a, half %b, ; ; ZVFHMIN-LABEL: vmfsac_vf_nxv2f32: ; ZVFHMIN: # %bb.0: -; ZVFHMIN-NEXT: fcvt.s.h fa5, fa0 -; ZVFHMIN-NEXT: vsetvli a1, zero, e32, m1, ta, ma -; ZVFHMIN-NEXT: vfmv.v.f v10, fa5 -; ZVFHMIN-NEXT: vsetvli zero, zero, e16, mf2, ta, ma -; ZVFHMIN-NEXT: vfncvt.f.f.w v11, v10 +; ZVFHMIN-NEXT: fmv.x.h a1, fa0 +; ZVFHMIN-NEXT: vsetvli a2, zero, e16, mf2, ta, ma +; ZVFHMIN-NEXT: vmv.v.x v10, a1 ; ZVFHMIN-NEXT: vsetvli zero, a0, e16, mf2, ta, ma -; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v8, v0.t -; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v11, v0.t +; ZVFHMIN-NEXT: vfwcvt.f.f.v v11, v8, v0.t +; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v10, v0.t ; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m1, ta, ma -; ZVFHMIN-NEXT: vfmsub.vv v8, v10, v9, v0.t +; ZVFHMIN-NEXT: vfmsub.vv v8, v11, v9, v0.t ; ZVFHMIN-NEXT: ret %elt.head = insertelement poison, half %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer @@ -290,11 +282,9 @@ define @vmfsac_vf_nxv2f32_commute( %a, h ; ; ZVFHMIN-LABEL: vmfsac_vf_nxv2f32_commute: ; ZVFHMIN: # %bb.0: -; ZVFHMIN-NEXT: fcvt.s.h fa5, fa0 -; ZVFHMIN-NEXT: vsetvli a1, zero, e32, m1, ta, ma -; ZVFHMIN-NEXT: vfmv.v.f v10, fa5 -; ZVFHMIN-NEXT: vsetvli zero, zero, e16, mf2, ta, ma -; ZVFHMIN-NEXT: vfncvt.f.f.w v11, v10 +; ZVFHMIN-NEXT: fmv.x.h a1, fa0 +; ZVFHMIN-NEXT: vsetvli a2, zero, e16, mf2, ta, ma +; ZVFHMIN-NEXT: vmv.v.x v11, a1 ; ZVFHMIN-NEXT: vsetvli zero, a0, e16, mf2, ta, ma ; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v8, v0.t ; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v11, v0.t @@ -321,16 +311,14 @@ define @vmfsac_vf_nxv2f32_unmasked( %a, ; ; ZVFHMIN-LABEL: vmfsac_vf_nxv2f32_unmasked: ; ZVFHMIN: # %bb.0: -; ZVFHMIN-NEXT: fcvt.s.h fa5, fa0 -; ZVFHMIN-NEXT: vsetvli a1, zero, e32, m1, ta, ma -; ZVFHMIN-NEXT: vfmv.v.f v10, fa5 -; ZVFHMIN-NEXT: vsetvli zero, zero, e16, mf2, ta, ma -; ZVFHMIN-NEXT: vfncvt.f.f.w v11, v10 +; ZVFHMIN-NEXT: fmv.x.h a1, fa0 +; ZVFHMIN-NEXT: vsetvli a2, zero, e16, mf2, ta, ma +; ZVFHMIN-NEXT: vmv.v.x v10, a1 ; ZVFHMIN-NEXT: vsetvli zero, a0, e16, mf2, ta, ma -; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v8 -; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v11 +; ZVFHMIN-NEXT: vfwcvt.f.f.v v11, v8 +; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v10 ; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m1, ta, ma -; ZVFHMIN-NEXT: vfmsub.vv v8, v10, v9 +; ZVFHMIN-NEXT: vfmsub.vv v8, v11, v9 ; ZVFHMIN-NEXT: ret %elt.head = insertelement poison, half %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer @@ -403,16 +391,14 @@ define @vmfsac_vf_nxv4f32( %a, half %b, ; ; ZVFHMIN-LABEL: vmfsac_vf_nxv4f32: ; ZVFHMIN: # %bb.0: -; ZVFHMIN-NEXT: fcvt.s.h fa5, fa0 -; ZVFHMIN-NEXT: vsetvli a1, zero, e32, m2, ta, ma -; ZVFHMIN-NEXT: vfmv.v.f v12, fa5 -; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m1, ta, ma -; ZVFHMIN-NEXT: vfncvt.f.f.w v14, v12 +; ZVFHMIN-NEXT: fmv.x.h a1, fa0 +; ZVFHMIN-NEXT: vsetvli a2, zero, e16, m1, ta, ma +; ZVFHMIN-NEXT: vmv.v.x v12, a1 ; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m1, ta, ma -; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v8, v0.t -; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v14, v0.t +; ZVFHMIN-NEXT: vfwcvt.f.f.v v14, v8, v0.t +; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v12, v0.t ; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m2, ta, ma -; ZVFHMIN-NEXT: vfmsub.vv v8, v12, v10, v0.t +; ZVFHMIN-NEXT: vfmsub.vv v8, v14, v10, v0.t ; ZVFHMIN-NEXT: ret %elt.head = insertelement poison, half %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer @@ -433,11 +419,9 @@ define @vmfsac_vf_nxv4f32_commute( %a, h ; ; ZVFHMIN-LABEL: vmfsac_vf_nxv4f32_commute: ; ZVFHMIN: # %bb.0: -; ZVFHMIN-NEXT: fcvt.s.h fa5, fa0 -; ZVFHMIN-NEXT: vsetvli a1, zero, e32, m2, ta, ma -; ZVFHMIN-NEXT: vfmv.v.f v12, fa5 -; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m1, ta, ma -; ZVFHMIN-NEXT: vfncvt.f.f.w v9, v12 +; ZVFHMIN-NEXT: fmv.x.h a1, fa0 +; ZVFHMIN-NEXT: vsetvli a2, zero, e16, m1, ta, ma +; ZVFHMIN-NEXT: vmv.v.x v9, a1 ; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m1, ta, ma ; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v8, v0.t ; ZVFHMIN-NEXT: vfwcvt.f.f.v v14, v9, v0.t @@ -464,16 +448,14 @@ define @vmfsac_vf_nxv4f32_unmasked( %a, ; ; ZVFHMIN-LABEL: vmfsac_vf_nxv4f32_unmasked: ; ZVFHMIN: # %bb.0: -; ZVFHMIN-NEXT: fcvt.s.h fa5, fa0 -; ZVFHMIN-NEXT: vsetvli a1, zero, e32, m2, ta, ma -; ZVFHMIN-NEXT: vfmv.v.f v12, fa5 -; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m1, ta, ma -; ZVFHMIN-NEXT: vfncvt.f.f.w v14, v12 +; ZVFHMIN-NEXT: fmv.x.h a1, fa0 +; ZVFHMIN-NEXT: vsetvli a2, zero, e16, m1, ta, ma +; ZVFHMIN-NEXT: vmv.v.x v12, a1 ; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m1, ta, ma -; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v8 -; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v14 +; ZVFHMIN-NEXT: vfwcvt.f.f.v v14, v8 +; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v12 ; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m2, ta, ma -; ZVFHMIN-NEXT: vfmsub.vv v8, v12, v10 +; ZVFHMIN-NEXT: vfmsub.vv v8, v14, v10 ; ZVFHMIN-NEXT: ret %elt.head = insertelement poison, half %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer @@ -546,16 +528,14 @@ define @vmfsac_vf_nxv8f32( %a, half %b, ; ; ZVFHMIN-LABEL: vmfsac_vf_nxv8f32: ; ZVFHMIN: # %bb.0: -; ZVFHMIN-NEXT: fcvt.s.h fa5, fa0 -; ZVFHMIN-NEXT: vsetvli a1, zero, e32, m4, ta, ma -; ZVFHMIN-NEXT: vfmv.v.f v16, fa5 -; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m2, ta, ma -; ZVFHMIN-NEXT: vfncvt.f.f.w v20, v16 +; ZVFHMIN-NEXT: fmv.x.h a1, fa0 +; ZVFHMIN-NEXT: vsetvli a2, zero, e16, m2, ta, ma +; ZVFHMIN-NEXT: vmv.v.x v16, a1 ; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m2, ta, ma -; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v8, v0.t -; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v20, v0.t +; ZVFHMIN-NEXT: vfwcvt.f.f.v v20, v8, v0.t +; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v16, v0.t ; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m4, ta, ma -; ZVFHMIN-NEXT: vfmsub.vv v8, v16, v12, v0.t +; ZVFHMIN-NEXT: vfmsub.vv v8, v20, v12, v0.t ; ZVFHMIN-NEXT: ret %elt.head = insertelement poison, half %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer @@ -576,11 +556,9 @@ define @vmfsac_vf_nxv8f32_commute( %a, h ; ; ZVFHMIN-LABEL: vmfsac_vf_nxv8f32_commute: ; ZVFHMIN: # %bb.0: -; ZVFHMIN-NEXT: fcvt.s.h fa5, fa0 -; ZVFHMIN-NEXT: vsetvli a1, zero, e32, m4, ta, ma -; ZVFHMIN-NEXT: vfmv.v.f v16, fa5 -; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m2, ta, ma -; ZVFHMIN-NEXT: vfncvt.f.f.w v10, v16 +; ZVFHMIN-NEXT: fmv.x.h a1, fa0 +; ZVFHMIN-NEXT: vsetvli a2, zero, e16, m2, ta, ma +; ZVFHMIN-NEXT: vmv.v.x v10, a1 ; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m2, ta, ma ; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v8, v0.t ; ZVFHMIN-NEXT: vfwcvt.f.f.v v20, v10, v0.t @@ -607,16 +585,14 @@ define @vmfsac_vf_nxv8f32_unmasked( %a, ; ; ZVFHMIN-LABEL: vmfsac_vf_nxv8f32_unmasked: ; ZVFHMIN: # %bb.0: -; ZVFHMIN-NEXT: fcvt.s.h fa5, fa0 -; ZVFHMIN-NEXT: vsetvli a1, zero, e32, m4, ta, ma -; ZVFHMIN-NEXT: vfmv.v.f v16, fa5 -; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m2, ta, ma -; ZVFHMIN-NEXT: vfncvt.f.f.w v20, v16 +; ZVFHMIN-NEXT: fmv.x.h a1, fa0 +; ZVFHMIN-NEXT: vsetvli a2, zero, e16, m2, ta, ma +; ZVFHMIN-NEXT: vmv.v.x v16, a1 ; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m2, ta, ma -; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v8 -; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v20 +; ZVFHMIN-NEXT: vfwcvt.f.f.v v20, v8 +; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v16 ; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m4, ta, ma -; ZVFHMIN-NEXT: vfmsub.vv v8, v16, v12 +; ZVFHMIN-NEXT: vfmsub.vv v8, v20, v12 ; ZVFHMIN-NEXT: ret %elt.head = insertelement poison, half %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer diff --git a/llvm/test/CodeGen/RISCV/rvv/vfwnmacc-vp.ll b/llvm/test/CodeGen/RISCV/rvv/vfwnmacc-vp.ll index c11867d55ba0cd..6ea58a4e768736 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vfwnmacc-vp.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vfwnmacc-vp.ll @@ -70,16 +70,14 @@ define @vfnmacc_vf_nxv1f32( %a, half %b, ; ; ZVFHMIN-LABEL: vfnmacc_vf_nxv1f32: ; ZVFHMIN: # %bb.0: -; ZVFHMIN-NEXT: fcvt.s.h fa5, fa0 -; ZVFHMIN-NEXT: vsetvli a1, zero, e32, mf2, ta, ma -; ZVFHMIN-NEXT: vfmv.v.f v10, fa5 -; ZVFHMIN-NEXT: vsetvli zero, zero, e16, mf4, ta, ma -; ZVFHMIN-NEXT: vfncvt.f.f.w v11, v10 +; ZVFHMIN-NEXT: fmv.x.h a1, fa0 +; ZVFHMIN-NEXT: vsetvli a2, zero, e16, mf4, ta, ma +; ZVFHMIN-NEXT: vmv.v.x v10, a1 ; ZVFHMIN-NEXT: vsetvli zero, a0, e16, mf4, ta, ma -; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v8, v0.t -; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v11, v0.t +; ZVFHMIN-NEXT: vfwcvt.f.f.v v11, v8, v0.t +; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v10, v0.t ; ZVFHMIN-NEXT: vsetvli zero, zero, e32, mf2, ta, ma -; ZVFHMIN-NEXT: vfnmadd.vv v8, v10, v9, v0.t +; ZVFHMIN-NEXT: vfnmadd.vv v8, v11, v9, v0.t ; ZVFHMIN-NEXT: ret %elt.head = insertelement poison, half %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer @@ -102,11 +100,9 @@ define @vfnmacc_vf_nxv1f32_commute( %a, ; ; ZVFHMIN-LABEL: vfnmacc_vf_nxv1f32_commute: ; ZVFHMIN: # %bb.0: -; ZVFHMIN-NEXT: fcvt.s.h fa5, fa0 -; ZVFHMIN-NEXT: vsetvli a1, zero, e32, mf2, ta, ma -; ZVFHMIN-NEXT: vfmv.v.f v10, fa5 -; ZVFHMIN-NEXT: vsetvli zero, zero, e16, mf4, ta, ma -; ZVFHMIN-NEXT: vfncvt.f.f.w v11, v10 +; ZVFHMIN-NEXT: fmv.x.h a1, fa0 +; ZVFHMIN-NEXT: vsetvli a2, zero, e16, mf4, ta, ma +; ZVFHMIN-NEXT: vmv.v.x v11, a1 ; ZVFHMIN-NEXT: vsetvli zero, a0, e16, mf4, ta, ma ; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v8, v0.t ; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v11, v0.t @@ -134,16 +130,14 @@ define @vfnmacc_vf_nxv1f32_unmasked( %a, ; ; ZVFHMIN-LABEL: vfnmacc_vf_nxv1f32_unmasked: ; ZVFHMIN: # %bb.0: -; ZVFHMIN-NEXT: fcvt.s.h fa5, fa0 -; ZVFHMIN-NEXT: vsetvli a1, zero, e32, mf2, ta, ma -; ZVFHMIN-NEXT: vfmv.v.f v10, fa5 -; ZVFHMIN-NEXT: vsetvli zero, zero, e16, mf4, ta, ma -; ZVFHMIN-NEXT: vfncvt.f.f.w v11, v10 +; ZVFHMIN-NEXT: fmv.x.h a1, fa0 +; ZVFHMIN-NEXT: vsetvli a2, zero, e16, mf4, ta, ma +; ZVFHMIN-NEXT: vmv.v.x v10, a1 ; ZVFHMIN-NEXT: vsetvli zero, a0, e16, mf4, ta, ma -; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v8 -; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v11 +; ZVFHMIN-NEXT: vfwcvt.f.f.v v11, v8 +; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v10 ; ZVFHMIN-NEXT: vsetvli zero, zero, e32, mf2, ta, ma -; ZVFHMIN-NEXT: vfnmadd.vv v8, v10, v9 +; ZVFHMIN-NEXT: vfnmadd.vv v8, v11, v9 ; ZVFHMIN-NEXT: ret %elt.head = insertelement poison, half %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer @@ -217,16 +211,14 @@ define @vfnmacc_vf_nxv2f32( %a, half %b, ; ; ZVFHMIN-LABEL: vfnmacc_vf_nxv2f32: ; ZVFHMIN: # %bb.0: -; ZVFHMIN-NEXT: fcvt.s.h fa5, fa0 -; ZVFHMIN-NEXT: vsetvli a1, zero, e32, m1, ta, ma -; ZVFHMIN-NEXT: vfmv.v.f v10, fa5 -; ZVFHMIN-NEXT: vsetvli zero, zero, e16, mf2, ta, ma -; ZVFHMIN-NEXT: vfncvt.f.f.w v11, v10 +; ZVFHMIN-NEXT: fmv.x.h a1, fa0 +; ZVFHMIN-NEXT: vsetvli a2, zero, e16, mf2, ta, ma +; ZVFHMIN-NEXT: vmv.v.x v10, a1 ; ZVFHMIN-NEXT: vsetvli zero, a0, e16, mf2, ta, ma -; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v8, v0.t -; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v11, v0.t +; ZVFHMIN-NEXT: vfwcvt.f.f.v v11, v8, v0.t +; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v10, v0.t ; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m1, ta, ma -; ZVFHMIN-NEXT: vfnmadd.vv v8, v10, v9, v0.t +; ZVFHMIN-NEXT: vfnmadd.vv v8, v11, v9, v0.t ; ZVFHMIN-NEXT: ret %elt.head = insertelement poison, half %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer @@ -249,11 +241,9 @@ define @vfnmacc_vf_nxv2f32_commute( %a, ; ; ZVFHMIN-LABEL: vfnmacc_vf_nxv2f32_commute: ; ZVFHMIN: # %bb.0: -; ZVFHMIN-NEXT: fcvt.s.h fa5, fa0 -; ZVFHMIN-NEXT: vsetvli a1, zero, e32, m1, ta, ma -; ZVFHMIN-NEXT: vfmv.v.f v10, fa5 -; ZVFHMIN-NEXT: vsetvli zero, zero, e16, mf2, ta, ma -; ZVFHMIN-NEXT: vfncvt.f.f.w v11, v10 +; ZVFHMIN-NEXT: fmv.x.h a1, fa0 +; ZVFHMIN-NEXT: vsetvli a2, zero, e16, mf2, ta, ma +; ZVFHMIN-NEXT: vmv.v.x v11, a1 ; ZVFHMIN-NEXT: vsetvli zero, a0, e16, mf2, ta, ma ; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v8, v0.t ; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v11, v0.t @@ -281,16 +271,14 @@ define @vfnmacc_vf_nxv2f32_unmasked( %a, ; ; ZVFHMIN-LABEL: vfnmacc_vf_nxv2f32_unmasked: ; ZVFHMIN: # %bb.0: -; ZVFHMIN-NEXT: fcvt.s.h fa5, fa0 -; ZVFHMIN-NEXT: vsetvli a1, zero, e32, m1, ta, ma -; ZVFHMIN-NEXT: vfmv.v.f v10, fa5 -; ZVFHMIN-NEXT: vsetvli zero, zero, e16, mf2, ta, ma -; ZVFHMIN-NEXT: vfncvt.f.f.w v11, v10 +; ZVFHMIN-NEXT: fmv.x.h a1, fa0 +; ZVFHMIN-NEXT: vsetvli a2, zero, e16, mf2, ta, ma +; ZVFHMIN-NEXT: vmv.v.x v10, a1 ; ZVFHMIN-NEXT: vsetvli zero, a0, e16, mf2, ta, ma -; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v8 -; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v11 +; ZVFHMIN-NEXT: vfwcvt.f.f.v v11, v8 +; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v10 ; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m1, ta, ma -; ZVFHMIN-NEXT: vfnmadd.vv v8, v10, v9 +; ZVFHMIN-NEXT: vfnmadd.vv v8, v11, v9 ; ZVFHMIN-NEXT: ret %elt.head = insertelement poison, half %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer @@ -366,16 +354,14 @@ define @vfnmacc_vf_nxv4f32( %a, half %b, ; ; ZVFHMIN-LABEL: vfnmacc_vf_nxv4f32: ; ZVFHMIN: # %bb.0: -; ZVFHMIN-NEXT: fcvt.s.h fa5, fa0 -; ZVFHMIN-NEXT: vsetvli a1, zero, e32, m2, ta, ma -; ZVFHMIN-NEXT: vfmv.v.f v12, fa5 -; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m1, ta, ma -; ZVFHMIN-NEXT: vfncvt.f.f.w v14, v12 +; ZVFHMIN-NEXT: fmv.x.h a1, fa0 +; ZVFHMIN-NEXT: vsetvli a2, zero, e16, m1, ta, ma +; ZVFHMIN-NEXT: vmv.v.x v12, a1 ; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m1, ta, ma -; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v8, v0.t -; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v14, v0.t +; ZVFHMIN-NEXT: vfwcvt.f.f.v v14, v8, v0.t +; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v12, v0.t ; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m2, ta, ma -; ZVFHMIN-NEXT: vfnmadd.vv v8, v12, v10, v0.t +; ZVFHMIN-NEXT: vfnmadd.vv v8, v14, v10, v0.t ; ZVFHMIN-NEXT: ret %elt.head = insertelement poison, half %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer @@ -398,11 +384,9 @@ define @vfnmacc_vf_nxv4f32_commute( %a, ; ; ZVFHMIN-LABEL: vfnmacc_vf_nxv4f32_commute: ; ZVFHMIN: # %bb.0: -; ZVFHMIN-NEXT: fcvt.s.h fa5, fa0 -; ZVFHMIN-NEXT: vsetvli a1, zero, e32, m2, ta, ma -; ZVFHMIN-NEXT: vfmv.v.f v12, fa5 -; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m1, ta, ma -; ZVFHMIN-NEXT: vfncvt.f.f.w v9, v12 +; ZVFHMIN-NEXT: fmv.x.h a1, fa0 +; ZVFHMIN-NEXT: vsetvli a2, zero, e16, m1, ta, ma +; ZVFHMIN-NEXT: vmv.v.x v9, a1 ; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m1, ta, ma ; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v8, v0.t ; ZVFHMIN-NEXT: vfwcvt.f.f.v v14, v9, v0.t @@ -430,16 +414,14 @@ define @vfnmacc_vf_nxv4f32_unmasked( %a, ; ; ZVFHMIN-LABEL: vfnmacc_vf_nxv4f32_unmasked: ; ZVFHMIN: # %bb.0: -; ZVFHMIN-NEXT: fcvt.s.h fa5, fa0 -; ZVFHMIN-NEXT: vsetvli a1, zero, e32, m2, ta, ma -; ZVFHMIN-NEXT: vfmv.v.f v12, fa5 -; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m1, ta, ma -; ZVFHMIN-NEXT: vfncvt.f.f.w v14, v12 +; ZVFHMIN-NEXT: fmv.x.h a1, fa0 +; ZVFHMIN-NEXT: vsetvli a2, zero, e16, m1, ta, ma +; ZVFHMIN-NEXT: vmv.v.x v12, a1 ; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m1, ta, ma -; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v8 -; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v14 +; ZVFHMIN-NEXT: vfwcvt.f.f.v v14, v8 +; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v12 ; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m2, ta, ma -; ZVFHMIN-NEXT: vfnmadd.vv v8, v12, v10 +; ZVFHMIN-NEXT: vfnmadd.vv v8, v14, v10 ; ZVFHMIN-NEXT: ret %elt.head = insertelement poison, half %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer @@ -515,16 +497,14 @@ define @vfnmacc_vf_nxv8f32( %a, half %b, ; ; ZVFHMIN-LABEL: vfnmacc_vf_nxv8f32: ; ZVFHMIN: # %bb.0: -; ZVFHMIN-NEXT: fcvt.s.h fa5, fa0 -; ZVFHMIN-NEXT: vsetvli a1, zero, e32, m4, ta, ma -; ZVFHMIN-NEXT: vfmv.v.f v16, fa5 -; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m2, ta, ma -; ZVFHMIN-NEXT: vfncvt.f.f.w v20, v16 +; ZVFHMIN-NEXT: fmv.x.h a1, fa0 +; ZVFHMIN-NEXT: vsetvli a2, zero, e16, m2, ta, ma +; ZVFHMIN-NEXT: vmv.v.x v16, a1 ; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m2, ta, ma -; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v8, v0.t -; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v20, v0.t +; ZVFHMIN-NEXT: vfwcvt.f.f.v v20, v8, v0.t +; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v16, v0.t ; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m4, ta, ma -; ZVFHMIN-NEXT: vfnmadd.vv v8, v16, v12, v0.t +; ZVFHMIN-NEXT: vfnmadd.vv v8, v20, v12, v0.t ; ZVFHMIN-NEXT: ret %elt.head = insertelement poison, half %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer @@ -547,11 +527,9 @@ define @vfnmacc_vf_nxv8f32_commute( %a, ; ; ZVFHMIN-LABEL: vfnmacc_vf_nxv8f32_commute: ; ZVFHMIN: # %bb.0: -; ZVFHMIN-NEXT: fcvt.s.h fa5, fa0 -; ZVFHMIN-NEXT: vsetvli a1, zero, e32, m4, ta, ma -; ZVFHMIN-NEXT: vfmv.v.f v16, fa5 -; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m2, ta, ma -; ZVFHMIN-NEXT: vfncvt.f.f.w v10, v16 +; ZVFHMIN-NEXT: fmv.x.h a1, fa0 +; ZVFHMIN-NEXT: vsetvli a2, zero, e16, m2, ta, ma +; ZVFHMIN-NEXT: vmv.v.x v10, a1 ; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m2, ta, ma ; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v8, v0.t ; ZVFHMIN-NEXT: vfwcvt.f.f.v v20, v10, v0.t @@ -579,16 +557,14 @@ define @vfnmacc_vf_nxv8f32_unmasked( %a, ; ; ZVFHMIN-LABEL: vfnmacc_vf_nxv8f32_unmasked: ; ZVFHMIN: # %bb.0: -; ZVFHMIN-NEXT: fcvt.s.h fa5, fa0 -; ZVFHMIN-NEXT: vsetvli a1, zero, e32, m4, ta, ma -; ZVFHMIN-NEXT: vfmv.v.f v16, fa5 -; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m2, ta, ma -; ZVFHMIN-NEXT: vfncvt.f.f.w v20, v16 +; ZVFHMIN-NEXT: fmv.x.h a1, fa0 +; ZVFHMIN-NEXT: vsetvli a2, zero, e16, m2, ta, ma +; ZVFHMIN-NEXT: vmv.v.x v16, a1 ; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m2, ta, ma -; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v8 -; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v20 +; ZVFHMIN-NEXT: vfwcvt.f.f.v v20, v8 +; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v16 ; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m4, ta, ma -; ZVFHMIN-NEXT: vfnmadd.vv v8, v16, v12 +; ZVFHMIN-NEXT: vfnmadd.vv v8, v20, v12 ; ZVFHMIN-NEXT: ret %elt.head = insertelement poison, half %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer @@ -678,11 +654,9 @@ define @vfnmacc_vf_nxv16f32( %a, half ; ; ZVFHMIN-LABEL: vfnmacc_vf_nxv16f32: ; ZVFHMIN: # %bb.0: -; ZVFHMIN-NEXT: fcvt.s.h fa5, fa0 -; ZVFHMIN-NEXT: vsetvli a1, zero, e32, m8, ta, ma -; ZVFHMIN-NEXT: vfmv.v.f v24, fa5 -; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m4, ta, ma -; ZVFHMIN-NEXT: vfncvt.f.f.w v4, v24 +; ZVFHMIN-NEXT: fmv.x.h a1, fa0 +; ZVFHMIN-NEXT: vsetvli a2, zero, e16, m4, ta, ma +; ZVFHMIN-NEXT: vmv.v.x v4, a1 ; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m4, ta, ma ; ZVFHMIN-NEXT: vfwcvt.f.f.v v24, v8, v0.t ; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v4, v0.t @@ -710,11 +684,9 @@ define @vfnmacc_vf_nxv16f32_commute( % ; ; ZVFHMIN-LABEL: vfnmacc_vf_nxv16f32_commute: ; ZVFHMIN: # %bb.0: -; ZVFHMIN-NEXT: fcvt.s.h fa5, fa0 -; ZVFHMIN-NEXT: vsetvli a1, zero, e32, m8, ta, ma -; ZVFHMIN-NEXT: vfmv.v.f v24, fa5 -; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m4, ta, ma -; ZVFHMIN-NEXT: vfncvt.f.f.w v4, v24 +; ZVFHMIN-NEXT: fmv.x.h a1, fa0 +; ZVFHMIN-NEXT: vsetvli a2, zero, e16, m4, ta, ma +; ZVFHMIN-NEXT: vmv.v.x v4, a1 ; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m4, ta, ma ; ZVFHMIN-NEXT: vfwcvt.f.f.v v24, v8, v0.t ; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v4, v0.t @@ -742,16 +714,14 @@ define @vfnmacc_vf_nxv16f32_unmasked( ; ; ZVFHMIN-LABEL: vfnmacc_vf_nxv16f32_unmasked: ; ZVFHMIN: # %bb.0: -; ZVFHMIN-NEXT: fcvt.s.h fa5, fa0 -; ZVFHMIN-NEXT: vsetvli a1, zero, e32, m8, ta, ma -; ZVFHMIN-NEXT: vfmv.v.f v24, fa5 -; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m4, ta, ma -; ZVFHMIN-NEXT: vfncvt.f.f.w v4, v24 +; ZVFHMIN-NEXT: fmv.x.h a1, fa0 +; ZVFHMIN-NEXT: vsetvli a2, zero, e16, m4, ta, ma +; ZVFHMIN-NEXT: vmv.v.x v24, a1 ; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m4, ta, ma -; ZVFHMIN-NEXT: vfwcvt.f.f.v v24, v8 -; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v4 +; ZVFHMIN-NEXT: vfwcvt.f.f.v v0, v8 +; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v24 ; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma -; ZVFHMIN-NEXT: vfnmadd.vv v8, v24, v16 +; ZVFHMIN-NEXT: vfnmadd.vv v8, v0, v16 ; ZVFHMIN-NEXT: ret %elt.head = insertelement poison, half %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer diff --git a/llvm/test/CodeGen/RISCV/rvv/vfwnmsac-vp.ll b/llvm/test/CodeGen/RISCV/rvv/vfwnmsac-vp.ll index 0ad7be47bcc8e3..0afbe58038c76f 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vfwnmsac-vp.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vfwnmsac-vp.ll @@ -68,16 +68,14 @@ define @vfnmsac_vf_nxv1f32( %a, half %b, ; ; ZVFHMIN-LABEL: vfnmsac_vf_nxv1f32: ; ZVFHMIN: # %bb.0: -; ZVFHMIN-NEXT: fcvt.s.h fa5, fa0 -; ZVFHMIN-NEXT: vsetvli a1, zero, e32, mf2, ta, ma -; ZVFHMIN-NEXT: vfmv.v.f v10, fa5 -; ZVFHMIN-NEXT: vsetvli zero, zero, e16, mf4, ta, ma -; ZVFHMIN-NEXT: vfncvt.f.f.w v11, v10 +; ZVFHMIN-NEXT: fmv.x.h a1, fa0 +; ZVFHMIN-NEXT: vsetvli a2, zero, e16, mf4, ta, ma +; ZVFHMIN-NEXT: vmv.v.x v10, a1 ; ZVFHMIN-NEXT: vsetvli zero, a0, e16, mf4, ta, ma -; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v8, v0.t -; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v11, v0.t +; ZVFHMIN-NEXT: vfwcvt.f.f.v v11, v8, v0.t +; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v10, v0.t ; ZVFHMIN-NEXT: vsetvli zero, zero, e32, mf2, ta, ma -; ZVFHMIN-NEXT: vfnmsub.vv v8, v10, v9, v0.t +; ZVFHMIN-NEXT: vfnmsub.vv v8, v11, v9, v0.t ; ZVFHMIN-NEXT: ret %elt.head = insertelement poison, half %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer @@ -98,11 +96,9 @@ define @vfnmsac_vf_nxv1f32_commute( %a, ; ; ZVFHMIN-LABEL: vfnmsac_vf_nxv1f32_commute: ; ZVFHMIN: # %bb.0: -; ZVFHMIN-NEXT: fcvt.s.h fa5, fa0 -; ZVFHMIN-NEXT: vsetvli a1, zero, e32, mf2, ta, ma -; ZVFHMIN-NEXT: vfmv.v.f v10, fa5 -; ZVFHMIN-NEXT: vsetvli zero, zero, e16, mf4, ta, ma -; ZVFHMIN-NEXT: vfncvt.f.f.w v11, v10 +; ZVFHMIN-NEXT: fmv.x.h a1, fa0 +; ZVFHMIN-NEXT: vsetvli a2, zero, e16, mf4, ta, ma +; ZVFHMIN-NEXT: vmv.v.x v11, a1 ; ZVFHMIN-NEXT: vsetvli zero, a0, e16, mf4, ta, ma ; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v8, v0.t ; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v11, v0.t @@ -129,16 +125,14 @@ define @vfnmsac_vf_nxv1f32_unmasked( %a, ; ; ZVFHMIN-LABEL: vfnmsac_vf_nxv1f32_unmasked: ; ZVFHMIN: # %bb.0: -; ZVFHMIN-NEXT: fcvt.s.h fa5, fa0 -; ZVFHMIN-NEXT: vsetvli a1, zero, e32, mf2, ta, ma -; ZVFHMIN-NEXT: vfmv.v.f v10, fa5 -; ZVFHMIN-NEXT: vsetvli zero, zero, e16, mf4, ta, ma -; ZVFHMIN-NEXT: vfncvt.f.f.w v11, v10 +; ZVFHMIN-NEXT: fmv.x.h a1, fa0 +; ZVFHMIN-NEXT: vsetvli a2, zero, e16, mf4, ta, ma +; ZVFHMIN-NEXT: vmv.v.x v10, a1 ; ZVFHMIN-NEXT: vsetvli zero, a0, e16, mf4, ta, ma -; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v8 -; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v11 +; ZVFHMIN-NEXT: vfwcvt.f.f.v v11, v8 +; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v10 ; ZVFHMIN-NEXT: vsetvli zero, zero, e32, mf2, ta, ma -; ZVFHMIN-NEXT: vfnmsub.vv v8, v10, v9 +; ZVFHMIN-NEXT: vfnmsub.vv v8, v11, v9 ; ZVFHMIN-NEXT: ret %elt.head = insertelement poison, half %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer @@ -209,16 +203,14 @@ define @vfnmsac_vf_nxv2f32( %a, half %b, ; ; ZVFHMIN-LABEL: vfnmsac_vf_nxv2f32: ; ZVFHMIN: # %bb.0: -; ZVFHMIN-NEXT: fcvt.s.h fa5, fa0 -; ZVFHMIN-NEXT: vsetvli a1, zero, e32, m1, ta, ma -; ZVFHMIN-NEXT: vfmv.v.f v10, fa5 -; ZVFHMIN-NEXT: vsetvli zero, zero, e16, mf2, ta, ma -; ZVFHMIN-NEXT: vfncvt.f.f.w v11, v10 +; ZVFHMIN-NEXT: fmv.x.h a1, fa0 +; ZVFHMIN-NEXT: vsetvli a2, zero, e16, mf2, ta, ma +; ZVFHMIN-NEXT: vmv.v.x v10, a1 ; ZVFHMIN-NEXT: vsetvli zero, a0, e16, mf2, ta, ma -; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v8, v0.t -; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v11, v0.t +; ZVFHMIN-NEXT: vfwcvt.f.f.v v11, v8, v0.t +; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v10, v0.t ; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m1, ta, ma -; ZVFHMIN-NEXT: vfnmsub.vv v8, v10, v9, v0.t +; ZVFHMIN-NEXT: vfnmsub.vv v8, v11, v9, v0.t ; ZVFHMIN-NEXT: ret %elt.head = insertelement poison, half %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer @@ -239,11 +231,9 @@ define @vfnmsac_vf_nxv2f32_commute( %a, ; ; ZVFHMIN-LABEL: vfnmsac_vf_nxv2f32_commute: ; ZVFHMIN: # %bb.0: -; ZVFHMIN-NEXT: fcvt.s.h fa5, fa0 -; ZVFHMIN-NEXT: vsetvli a1, zero, e32, m1, ta, ma -; ZVFHMIN-NEXT: vfmv.v.f v10, fa5 -; ZVFHMIN-NEXT: vsetvli zero, zero, e16, mf2, ta, ma -; ZVFHMIN-NEXT: vfncvt.f.f.w v11, v10 +; ZVFHMIN-NEXT: fmv.x.h a1, fa0 +; ZVFHMIN-NEXT: vsetvli a2, zero, e16, mf2, ta, ma +; ZVFHMIN-NEXT: vmv.v.x v11, a1 ; ZVFHMIN-NEXT: vsetvli zero, a0, e16, mf2, ta, ma ; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v8, v0.t ; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v11, v0.t @@ -270,16 +260,14 @@ define @vfnmsac_vf_nxv2f32_unmasked( %a, ; ; ZVFHMIN-LABEL: vfnmsac_vf_nxv2f32_unmasked: ; ZVFHMIN: # %bb.0: -; ZVFHMIN-NEXT: fcvt.s.h fa5, fa0 -; ZVFHMIN-NEXT: vsetvli a1, zero, e32, m1, ta, ma -; ZVFHMIN-NEXT: vfmv.v.f v10, fa5 -; ZVFHMIN-NEXT: vsetvli zero, zero, e16, mf2, ta, ma -; ZVFHMIN-NEXT: vfncvt.f.f.w v11, v10 +; ZVFHMIN-NEXT: fmv.x.h a1, fa0 +; ZVFHMIN-NEXT: vsetvli a2, zero, e16, mf2, ta, ma +; ZVFHMIN-NEXT: vmv.v.x v10, a1 ; ZVFHMIN-NEXT: vsetvli zero, a0, e16, mf2, ta, ma -; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v8 -; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v11 +; ZVFHMIN-NEXT: vfwcvt.f.f.v v11, v8 +; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v10 ; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m1, ta, ma -; ZVFHMIN-NEXT: vfnmsub.vv v8, v10, v9 +; ZVFHMIN-NEXT: vfnmsub.vv v8, v11, v9 ; ZVFHMIN-NEXT: ret %elt.head = insertelement poison, half %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer @@ -352,16 +340,14 @@ define @vfnmsac_vf_nxv4f32( %a, half %b, ; ; ZVFHMIN-LABEL: vfnmsac_vf_nxv4f32: ; ZVFHMIN: # %bb.0: -; ZVFHMIN-NEXT: fcvt.s.h fa5, fa0 -; ZVFHMIN-NEXT: vsetvli a1, zero, e32, m2, ta, ma -; ZVFHMIN-NEXT: vfmv.v.f v12, fa5 -; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m1, ta, ma -; ZVFHMIN-NEXT: vfncvt.f.f.w v14, v12 +; ZVFHMIN-NEXT: fmv.x.h a1, fa0 +; ZVFHMIN-NEXT: vsetvli a2, zero, e16, m1, ta, ma +; ZVFHMIN-NEXT: vmv.v.x v12, a1 ; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m1, ta, ma -; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v8, v0.t -; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v14, v0.t +; ZVFHMIN-NEXT: vfwcvt.f.f.v v14, v8, v0.t +; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v12, v0.t ; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m2, ta, ma -; ZVFHMIN-NEXT: vfnmsub.vv v8, v12, v10, v0.t +; ZVFHMIN-NEXT: vfnmsub.vv v8, v14, v10, v0.t ; ZVFHMIN-NEXT: ret %elt.head = insertelement poison, half %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer @@ -382,11 +368,9 @@ define @vfnmsac_vf_nxv4f32_commute( %a, ; ; ZVFHMIN-LABEL: vfnmsac_vf_nxv4f32_commute: ; ZVFHMIN: # %bb.0: -; ZVFHMIN-NEXT: fcvt.s.h fa5, fa0 -; ZVFHMIN-NEXT: vsetvli a1, zero, e32, m2, ta, ma -; ZVFHMIN-NEXT: vfmv.v.f v12, fa5 -; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m1, ta, ma -; ZVFHMIN-NEXT: vfncvt.f.f.w v9, v12 +; ZVFHMIN-NEXT: fmv.x.h a1, fa0 +; ZVFHMIN-NEXT: vsetvli a2, zero, e16, m1, ta, ma +; ZVFHMIN-NEXT: vmv.v.x v9, a1 ; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m1, ta, ma ; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v8, v0.t ; ZVFHMIN-NEXT: vfwcvt.f.f.v v14, v9, v0.t @@ -413,16 +397,14 @@ define @vfnmsac_vf_nxv4f32_unmasked( %a, ; ; ZVFHMIN-LABEL: vfnmsac_vf_nxv4f32_unmasked: ; ZVFHMIN: # %bb.0: -; ZVFHMIN-NEXT: fcvt.s.h fa5, fa0 -; ZVFHMIN-NEXT: vsetvli a1, zero, e32, m2, ta, ma -; ZVFHMIN-NEXT: vfmv.v.f v12, fa5 -; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m1, ta, ma -; ZVFHMIN-NEXT: vfncvt.f.f.w v14, v12 +; ZVFHMIN-NEXT: fmv.x.h a1, fa0 +; ZVFHMIN-NEXT: vsetvli a2, zero, e16, m1, ta, ma +; ZVFHMIN-NEXT: vmv.v.x v12, a1 ; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m1, ta, ma -; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v8 -; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v14 +; ZVFHMIN-NEXT: vfwcvt.f.f.v v14, v8 +; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v12 ; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m2, ta, ma -; ZVFHMIN-NEXT: vfnmsub.vv v8, v12, v10 +; ZVFHMIN-NEXT: vfnmsub.vv v8, v14, v10 ; ZVFHMIN-NEXT: ret %elt.head = insertelement poison, half %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer @@ -495,16 +477,14 @@ define @vfnmsac_vf_nxv8f32( %a, half %b, ; ; ZVFHMIN-LABEL: vfnmsac_vf_nxv8f32: ; ZVFHMIN: # %bb.0: -; ZVFHMIN-NEXT: fcvt.s.h fa5, fa0 -; ZVFHMIN-NEXT: vsetvli a1, zero, e32, m4, ta, ma -; ZVFHMIN-NEXT: vfmv.v.f v16, fa5 -; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m2, ta, ma -; ZVFHMIN-NEXT: vfncvt.f.f.w v20, v16 +; ZVFHMIN-NEXT: fmv.x.h a1, fa0 +; ZVFHMIN-NEXT: vsetvli a2, zero, e16, m2, ta, ma +; ZVFHMIN-NEXT: vmv.v.x v16, a1 ; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m2, ta, ma -; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v8, v0.t -; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v20, v0.t +; ZVFHMIN-NEXT: vfwcvt.f.f.v v20, v8, v0.t +; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v16, v0.t ; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m4, ta, ma -; ZVFHMIN-NEXT: vfnmsub.vv v8, v16, v12, v0.t +; ZVFHMIN-NEXT: vfnmsub.vv v8, v20, v12, v0.t ; ZVFHMIN-NEXT: ret %elt.head = insertelement poison, half %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer @@ -525,11 +505,9 @@ define @vfnmsac_vf_nxv8f32_commute( %a, ; ; ZVFHMIN-LABEL: vfnmsac_vf_nxv8f32_commute: ; ZVFHMIN: # %bb.0: -; ZVFHMIN-NEXT: fcvt.s.h fa5, fa0 -; ZVFHMIN-NEXT: vsetvli a1, zero, e32, m4, ta, ma -; ZVFHMIN-NEXT: vfmv.v.f v16, fa5 -; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m2, ta, ma -; ZVFHMIN-NEXT: vfncvt.f.f.w v10, v16 +; ZVFHMIN-NEXT: fmv.x.h a1, fa0 +; ZVFHMIN-NEXT: vsetvli a2, zero, e16, m2, ta, ma +; ZVFHMIN-NEXT: vmv.v.x v10, a1 ; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m2, ta, ma ; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v8, v0.t ; ZVFHMIN-NEXT: vfwcvt.f.f.v v20, v10, v0.t @@ -556,16 +534,14 @@ define @vfnmsac_vf_nxv8f32_unmasked( %a, ; ; ZVFHMIN-LABEL: vfnmsac_vf_nxv8f32_unmasked: ; ZVFHMIN: # %bb.0: -; ZVFHMIN-NEXT: fcvt.s.h fa5, fa0 -; ZVFHMIN-NEXT: vsetvli a1, zero, e32, m4, ta, ma -; ZVFHMIN-NEXT: vfmv.v.f v16, fa5 -; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m2, ta, ma -; ZVFHMIN-NEXT: vfncvt.f.f.w v20, v16 +; ZVFHMIN-NEXT: fmv.x.h a1, fa0 +; ZVFHMIN-NEXT: vsetvli a2, zero, e16, m2, ta, ma +; ZVFHMIN-NEXT: vmv.v.x v16, a1 ; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m2, ta, ma -; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v8 -; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v20 +; ZVFHMIN-NEXT: vfwcvt.f.f.v v20, v8 +; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v16 ; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m4, ta, ma -; ZVFHMIN-NEXT: vfnmsub.vv v8, v16, v12 +; ZVFHMIN-NEXT: vfnmsub.vv v8, v20, v12 ; ZVFHMIN-NEXT: ret %elt.head = insertelement poison, half %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer @@ -652,11 +628,9 @@ define @vfnmsac_vf_nxv16f32( %a, half ; ; ZVFHMIN-LABEL: vfnmsac_vf_nxv16f32: ; ZVFHMIN: # %bb.0: -; ZVFHMIN-NEXT: fcvt.s.h fa5, fa0 -; ZVFHMIN-NEXT: vsetvli a1, zero, e32, m8, ta, ma -; ZVFHMIN-NEXT: vfmv.v.f v24, fa5 -; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m4, ta, ma -; ZVFHMIN-NEXT: vfncvt.f.f.w v4, v24 +; ZVFHMIN-NEXT: fmv.x.h a1, fa0 +; ZVFHMIN-NEXT: vsetvli a2, zero, e16, m4, ta, ma +; ZVFHMIN-NEXT: vmv.v.x v4, a1 ; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m4, ta, ma ; ZVFHMIN-NEXT: vfwcvt.f.f.v v24, v8, v0.t ; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v4, v0.t @@ -682,11 +656,9 @@ define @vfnmsac_vf_nxv16f32_commute( % ; ; ZVFHMIN-LABEL: vfnmsac_vf_nxv16f32_commute: ; ZVFHMIN: # %bb.0: -; ZVFHMIN-NEXT: fcvt.s.h fa5, fa0 -; ZVFHMIN-NEXT: vsetvli a1, zero, e32, m8, ta, ma -; ZVFHMIN-NEXT: vfmv.v.f v24, fa5 -; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m4, ta, ma -; ZVFHMIN-NEXT: vfncvt.f.f.w v4, v24 +; ZVFHMIN-NEXT: fmv.x.h a1, fa0 +; ZVFHMIN-NEXT: vsetvli a2, zero, e16, m4, ta, ma +; ZVFHMIN-NEXT: vmv.v.x v4, a1 ; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m4, ta, ma ; ZVFHMIN-NEXT: vfwcvt.f.f.v v24, v8, v0.t ; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v4, v0.t @@ -713,16 +685,14 @@ define @vfnmsac_vf_nxv16f32_unmasked( ; ; ZVFHMIN-LABEL: vfnmsac_vf_nxv16f32_unmasked: ; ZVFHMIN: # %bb.0: -; ZVFHMIN-NEXT: fcvt.s.h fa5, fa0 -; ZVFHMIN-NEXT: vsetvli a1, zero, e32, m8, ta, ma -; ZVFHMIN-NEXT: vfmv.v.f v24, fa5 -; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m4, ta, ma -; ZVFHMIN-NEXT: vfncvt.f.f.w v4, v24 +; ZVFHMIN-NEXT: fmv.x.h a1, fa0 +; ZVFHMIN-NEXT: vsetvli a2, zero, e16, m4, ta, ma +; ZVFHMIN-NEXT: vmv.v.x v24, a1 ; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m4, ta, ma -; ZVFHMIN-NEXT: vfwcvt.f.f.v v24, v8 -; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v4 +; ZVFHMIN-NEXT: vfwcvt.f.f.v v0, v8 +; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v24 ; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma -; ZVFHMIN-NEXT: vfnmsub.vv v8, v24, v16 +; ZVFHMIN-NEXT: vfnmsub.vv v8, v0, v16 ; ZVFHMIN-NEXT: ret %elt.head = insertelement poison, half %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer diff --git a/llvm/test/CodeGen/RISCV/rvv/vpmerge-sdnode-bf16.ll b/llvm/test/CodeGen/RISCV/rvv/vpmerge-sdnode-bf16.ll index 66c4f79d50f7a1..16201da1a509a5 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vpmerge-sdnode-bf16.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vpmerge-sdnode-bf16.ll @@ -24,11 +24,11 @@ define @vpmerge_vv_nxv1bf16( %va, @vpmerge_vf_nxv1bf16(bfloat %a, %vb, %m, i32 zeroext %evl) { ; CHECK-LABEL: vpmerge_vf_nxv1bf16: ; CHECK: # %bb.0: -; CHECK-NEXT: fcvt.s.bf16 fa5, fa0 -; CHECK-NEXT: vsetvli a1, zero, e32, mf2, ta, ma -; CHECK-NEXT: vfmv.v.f v9, fa5 -; CHECK-NEXT: vsetvli zero, a0, e16, mf4, tu, mu -; CHECK-NEXT: vfncvtbf16.f.f.w v8, v9, v0.t +; CHECK-NEXT: fmv.x.h a1, fa0 +; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma +; CHECK-NEXT: vmv.v.x v9, a1 +; CHECK-NEXT: vsetvli zero, zero, e16, mf4, tu, ma +; CHECK-NEXT: vmerge.vvm v8, v8, v9, v0 ; CHECK-NEXT: ret %elt.head = insertelement poison, bfloat %a, i32 0 %va = shufflevector %elt.head, poison, zeroinitializer @@ -52,11 +52,11 @@ define @vpmerge_vv_nxv2bf16( %va, @vpmerge_vf_nxv2bf16(bfloat %a, %vb, %m, i32 zeroext %evl) { ; CHECK-LABEL: vpmerge_vf_nxv2bf16: ; CHECK: # %bb.0: -; CHECK-NEXT: fcvt.s.bf16 fa5, fa0 -; CHECK-NEXT: vsetvli a1, zero, e32, m1, ta, ma -; CHECK-NEXT: vfmv.v.f v9, fa5 -; CHECK-NEXT: vsetvli zero, a0, e16, mf2, tu, mu -; CHECK-NEXT: vfncvtbf16.f.f.w v8, v9, v0.t +; CHECK-NEXT: fmv.x.h a1, fa0 +; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, ma +; CHECK-NEXT: vmv.v.x v9, a1 +; CHECK-NEXT: vsetvli zero, zero, e16, mf2, tu, ma +; CHECK-NEXT: vmerge.vvm v8, v8, v9, v0 ; CHECK-NEXT: ret %elt.head = insertelement poison, bfloat %a, i32 0 %va = shufflevector %elt.head, poison, zeroinitializer @@ -80,11 +80,11 @@ define @vpmerge_vv_nxv4bf16( %va, @vpmerge_vf_nxv4bf16(bfloat %a, %vb, %m, i32 zeroext %evl) { ; CHECK-LABEL: vpmerge_vf_nxv4bf16: ; CHECK: # %bb.0: -; CHECK-NEXT: fcvt.s.bf16 fa5, fa0 -; CHECK-NEXT: vsetvli a1, zero, e32, m2, ta, ma -; CHECK-NEXT: vfmv.v.f v10, fa5 -; CHECK-NEXT: vsetvli zero, a0, e16, m1, tu, mu -; CHECK-NEXT: vfncvtbf16.f.f.w v8, v10, v0.t +; CHECK-NEXT: fmv.x.h a1, fa0 +; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, ma +; CHECK-NEXT: vmv.v.x v9, a1 +; CHECK-NEXT: vsetvli zero, zero, e16, m1, tu, ma +; CHECK-NEXT: vmerge.vvm v8, v8, v9, v0 ; CHECK-NEXT: ret %elt.head = insertelement poison, bfloat %a, i32 0 %va = shufflevector %elt.head, poison, zeroinitializer @@ -108,11 +108,11 @@ define @vpmerge_vv_nxv8bf16( %va, @vpmerge_vf_nxv8bf16(bfloat %a, %vb, %m, i32 zeroext %evl) { ; CHECK-LABEL: vpmerge_vf_nxv8bf16: ; CHECK: # %bb.0: -; CHECK-NEXT: fcvt.s.bf16 fa5, fa0 -; CHECK-NEXT: vsetvli a1, zero, e32, m4, ta, ma -; CHECK-NEXT: vfmv.v.f v12, fa5 -; CHECK-NEXT: vsetvli zero, a0, e16, m2, tu, mu -; CHECK-NEXT: vfncvtbf16.f.f.w v8, v12, v0.t +; CHECK-NEXT: fmv.x.h a1, fa0 +; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, ma +; CHECK-NEXT: vmv.v.x v10, a1 +; CHECK-NEXT: vsetvli zero, zero, e16, m2, tu, ma +; CHECK-NEXT: vmerge.vvm v8, v8, v10, v0 ; CHECK-NEXT: ret %elt.head = insertelement poison, bfloat %a, i32 0 %va = shufflevector %elt.head, poison, zeroinitializer @@ -136,11 +136,11 @@ define @vpmerge_vv_nxv16bf16( %va, define @vpmerge_vf_nxv16bf16(bfloat %a, %vb, %m, i32 zeroext %evl) { ; CHECK-LABEL: vpmerge_vf_nxv16bf16: ; CHECK: # %bb.0: -; CHECK-NEXT: fcvt.s.bf16 fa5, fa0 -; CHECK-NEXT: vsetvli a1, zero, e32, m8, ta, ma -; CHECK-NEXT: vfmv.v.f v16, fa5 -; CHECK-NEXT: vsetvli zero, a0, e16, m4, tu, mu -; CHECK-NEXT: vfncvtbf16.f.f.w v8, v16, v0.t +; CHECK-NEXT: fmv.x.h a1, fa0 +; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, ma +; CHECK-NEXT: vmv.v.x v12, a1 +; CHECK-NEXT: vsetvli zero, zero, e16, m4, tu, ma +; CHECK-NEXT: vmerge.vvm v8, v8, v12, v0 ; CHECK-NEXT: ret %elt.head = insertelement poison, bfloat %a, i32 0 %va = shufflevector %elt.head, poison, zeroinitializer @@ -164,13 +164,10 @@ define @vpmerge_vv_nxv32bf16( %va, define @vpmerge_vf_nxv32bf16(bfloat %a, %vb, %m, i32 zeroext %evl) { ; CHECK-LABEL: vpmerge_vf_nxv32bf16: ; CHECK: # %bb.0: -; CHECK-NEXT: fcvt.s.bf16 fa5, fa0 -; CHECK-NEXT: vsetvli a1, zero, e32, m8, ta, ma -; CHECK-NEXT: vfmv.v.f v24, fa5 -; CHECK-NEXT: vsetvli zero, zero, e16, m4, ta, ma -; CHECK-NEXT: vfncvtbf16.f.f.w v16, v24 -; CHECK-NEXT: vmv.v.v v20, v16 -; CHECK-NEXT: vsetvli zero, a0, e16, m8, tu, ma +; CHECK-NEXT: fmv.x.h a1, fa0 +; CHECK-NEXT: vsetvli zero, a0, e16, m8, ta, ma +; CHECK-NEXT: vmv.v.x v16, a1 +; CHECK-NEXT: vsetvli zero, zero, e16, m8, tu, ma ; CHECK-NEXT: vmerge.vvm v8, v8, v16, v0 ; CHECK-NEXT: ret %elt.head = insertelement poison, bfloat %a, i32 0 diff --git a/llvm/test/CodeGen/RISCV/rvv/vpmerge-sdnode.ll b/llvm/test/CodeGen/RISCV/rvv/vpmerge-sdnode.ll index 094e6c9cc754fa..86dfc74fdee37b 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vpmerge-sdnode.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vpmerge-sdnode.ll @@ -1051,20 +1051,20 @@ define @vpmerge_vf_nxv1f16(half %a, %vb, ; ; RV32ZVFHMIN-LABEL: vpmerge_vf_nxv1f16: ; RV32ZVFHMIN: # %bb.0: -; RV32ZVFHMIN-NEXT: fcvt.s.h fa5, fa0 -; RV32ZVFHMIN-NEXT: vsetvli a1, zero, e32, mf2, ta, ma -; RV32ZVFHMIN-NEXT: vfmv.v.f v9, fa5 -; RV32ZVFHMIN-NEXT: vsetvli zero, a0, e16, mf4, tu, mu -; RV32ZVFHMIN-NEXT: vfncvt.f.f.w v8, v9, v0.t +; RV32ZVFHMIN-NEXT: fmv.x.h a1, fa0 +; RV32ZVFHMIN-NEXT: vsetvli zero, a0, e16, mf4, ta, ma +; RV32ZVFHMIN-NEXT: vmv.v.x v9, a1 +; RV32ZVFHMIN-NEXT: vsetvli zero, zero, e16, mf4, tu, ma +; RV32ZVFHMIN-NEXT: vmerge.vvm v8, v8, v9, v0 ; RV32ZVFHMIN-NEXT: ret ; ; RV64ZVFHMIN-LABEL: vpmerge_vf_nxv1f16: ; RV64ZVFHMIN: # %bb.0: -; RV64ZVFHMIN-NEXT: fcvt.s.h fa5, fa0 -; RV64ZVFHMIN-NEXT: vsetvli a1, zero, e32, mf2, ta, ma -; RV64ZVFHMIN-NEXT: vfmv.v.f v9, fa5 -; RV64ZVFHMIN-NEXT: vsetvli zero, a0, e16, mf4, tu, mu -; RV64ZVFHMIN-NEXT: vfncvt.f.f.w v8, v9, v0.t +; RV64ZVFHMIN-NEXT: fmv.x.h a1, fa0 +; RV64ZVFHMIN-NEXT: vsetvli zero, a0, e16, mf4, ta, ma +; RV64ZVFHMIN-NEXT: vmv.v.x v9, a1 +; RV64ZVFHMIN-NEXT: vsetvli zero, zero, e16, mf4, tu, ma +; RV64ZVFHMIN-NEXT: vmerge.vvm v8, v8, v9, v0 ; RV64ZVFHMIN-NEXT: ret %elt.head = insertelement poison, half %a, i32 0 %va = shufflevector %elt.head, poison, zeroinitializer @@ -1100,20 +1100,20 @@ define @vpmerge_vf_nxv2f16(half %a, %vb, ; ; RV32ZVFHMIN-LABEL: vpmerge_vf_nxv2f16: ; RV32ZVFHMIN: # %bb.0: -; RV32ZVFHMIN-NEXT: fcvt.s.h fa5, fa0 -; RV32ZVFHMIN-NEXT: vsetvli a1, zero, e32, m1, ta, ma -; RV32ZVFHMIN-NEXT: vfmv.v.f v9, fa5 -; RV32ZVFHMIN-NEXT: vsetvli zero, a0, e16, mf2, tu, mu -; RV32ZVFHMIN-NEXT: vfncvt.f.f.w v8, v9, v0.t +; RV32ZVFHMIN-NEXT: fmv.x.h a1, fa0 +; RV32ZVFHMIN-NEXT: vsetvli zero, a0, e16, mf2, ta, ma +; RV32ZVFHMIN-NEXT: vmv.v.x v9, a1 +; RV32ZVFHMIN-NEXT: vsetvli zero, zero, e16, mf2, tu, ma +; RV32ZVFHMIN-NEXT: vmerge.vvm v8, v8, v9, v0 ; RV32ZVFHMIN-NEXT: ret ; ; RV64ZVFHMIN-LABEL: vpmerge_vf_nxv2f16: ; RV64ZVFHMIN: # %bb.0: -; RV64ZVFHMIN-NEXT: fcvt.s.h fa5, fa0 -; RV64ZVFHMIN-NEXT: vsetvli a1, zero, e32, m1, ta, ma -; RV64ZVFHMIN-NEXT: vfmv.v.f v9, fa5 -; RV64ZVFHMIN-NEXT: vsetvli zero, a0, e16, mf2, tu, mu -; RV64ZVFHMIN-NEXT: vfncvt.f.f.w v8, v9, v0.t +; RV64ZVFHMIN-NEXT: fmv.x.h a1, fa0 +; RV64ZVFHMIN-NEXT: vsetvli zero, a0, e16, mf2, ta, ma +; RV64ZVFHMIN-NEXT: vmv.v.x v9, a1 +; RV64ZVFHMIN-NEXT: vsetvli zero, zero, e16, mf2, tu, ma +; RV64ZVFHMIN-NEXT: vmerge.vvm v8, v8, v9, v0 ; RV64ZVFHMIN-NEXT: ret %elt.head = insertelement poison, half %a, i32 0 %va = shufflevector %elt.head, poison, zeroinitializer @@ -1149,20 +1149,20 @@ define @vpmerge_vf_nxv4f16(half %a, %vb, ; ; RV32ZVFHMIN-LABEL: vpmerge_vf_nxv4f16: ; RV32ZVFHMIN: # %bb.0: -; RV32ZVFHMIN-NEXT: fcvt.s.h fa5, fa0 -; RV32ZVFHMIN-NEXT: vsetvli a1, zero, e32, m2, ta, ma -; RV32ZVFHMIN-NEXT: vfmv.v.f v10, fa5 -; RV32ZVFHMIN-NEXT: vsetvli zero, a0, e16, m1, tu, mu -; RV32ZVFHMIN-NEXT: vfncvt.f.f.w v8, v10, v0.t +; RV32ZVFHMIN-NEXT: fmv.x.h a1, fa0 +; RV32ZVFHMIN-NEXT: vsetvli zero, a0, e16, m1, ta, ma +; RV32ZVFHMIN-NEXT: vmv.v.x v9, a1 +; RV32ZVFHMIN-NEXT: vsetvli zero, zero, e16, m1, tu, ma +; RV32ZVFHMIN-NEXT: vmerge.vvm v8, v8, v9, v0 ; RV32ZVFHMIN-NEXT: ret ; ; RV64ZVFHMIN-LABEL: vpmerge_vf_nxv4f16: ; RV64ZVFHMIN: # %bb.0: -; RV64ZVFHMIN-NEXT: fcvt.s.h fa5, fa0 -; RV64ZVFHMIN-NEXT: vsetvli a1, zero, e32, m2, ta, ma -; RV64ZVFHMIN-NEXT: vfmv.v.f v10, fa5 -; RV64ZVFHMIN-NEXT: vsetvli zero, a0, e16, m1, tu, mu -; RV64ZVFHMIN-NEXT: vfncvt.f.f.w v8, v10, v0.t +; RV64ZVFHMIN-NEXT: fmv.x.h a1, fa0 +; RV64ZVFHMIN-NEXT: vsetvli zero, a0, e16, m1, ta, ma +; RV64ZVFHMIN-NEXT: vmv.v.x v9, a1 +; RV64ZVFHMIN-NEXT: vsetvli zero, zero, e16, m1, tu, ma +; RV64ZVFHMIN-NEXT: vmerge.vvm v8, v8, v9, v0 ; RV64ZVFHMIN-NEXT: ret %elt.head = insertelement poison, half %a, i32 0 %va = shufflevector %elt.head, poison, zeroinitializer @@ -1198,20 +1198,20 @@ define @vpmerge_vf_nxv8f16(half %a, %vb, ; ; RV32ZVFHMIN-LABEL: vpmerge_vf_nxv8f16: ; RV32ZVFHMIN: # %bb.0: -; RV32ZVFHMIN-NEXT: fcvt.s.h fa5, fa0 -; RV32ZVFHMIN-NEXT: vsetvli a1, zero, e32, m4, ta, ma -; RV32ZVFHMIN-NEXT: vfmv.v.f v12, fa5 -; RV32ZVFHMIN-NEXT: vsetvli zero, a0, e16, m2, tu, mu -; RV32ZVFHMIN-NEXT: vfncvt.f.f.w v8, v12, v0.t +; RV32ZVFHMIN-NEXT: fmv.x.h a1, fa0 +; RV32ZVFHMIN-NEXT: vsetvli zero, a0, e16, m2, ta, ma +; RV32ZVFHMIN-NEXT: vmv.v.x v10, a1 +; RV32ZVFHMIN-NEXT: vsetvli zero, zero, e16, m2, tu, ma +; RV32ZVFHMIN-NEXT: vmerge.vvm v8, v8, v10, v0 ; RV32ZVFHMIN-NEXT: ret ; ; RV64ZVFHMIN-LABEL: vpmerge_vf_nxv8f16: ; RV64ZVFHMIN: # %bb.0: -; RV64ZVFHMIN-NEXT: fcvt.s.h fa5, fa0 -; RV64ZVFHMIN-NEXT: vsetvli a1, zero, e32, m4, ta, ma -; RV64ZVFHMIN-NEXT: vfmv.v.f v12, fa5 -; RV64ZVFHMIN-NEXT: vsetvli zero, a0, e16, m2, tu, mu -; RV64ZVFHMIN-NEXT: vfncvt.f.f.w v8, v12, v0.t +; RV64ZVFHMIN-NEXT: fmv.x.h a1, fa0 +; RV64ZVFHMIN-NEXT: vsetvli zero, a0, e16, m2, ta, ma +; RV64ZVFHMIN-NEXT: vmv.v.x v10, a1 +; RV64ZVFHMIN-NEXT: vsetvli zero, zero, e16, m2, tu, ma +; RV64ZVFHMIN-NEXT: vmerge.vvm v8, v8, v10, v0 ; RV64ZVFHMIN-NEXT: ret %elt.head = insertelement poison, half %a, i32 0 %va = shufflevector %elt.head, poison, zeroinitializer @@ -1247,20 +1247,20 @@ define @vpmerge_vf_nxv16f16(half %a, % ; ; RV32ZVFHMIN-LABEL: vpmerge_vf_nxv16f16: ; RV32ZVFHMIN: # %bb.0: -; RV32ZVFHMIN-NEXT: fcvt.s.h fa5, fa0 -; RV32ZVFHMIN-NEXT: vsetvli a1, zero, e32, m8, ta, ma -; RV32ZVFHMIN-NEXT: vfmv.v.f v16, fa5 -; RV32ZVFHMIN-NEXT: vsetvli zero, a0, e16, m4, tu, mu -; RV32ZVFHMIN-NEXT: vfncvt.f.f.w v8, v16, v0.t +; RV32ZVFHMIN-NEXT: fmv.x.h a1, fa0 +; RV32ZVFHMIN-NEXT: vsetvli zero, a0, e16, m4, ta, ma +; RV32ZVFHMIN-NEXT: vmv.v.x v12, a1 +; RV32ZVFHMIN-NEXT: vsetvli zero, zero, e16, m4, tu, ma +; RV32ZVFHMIN-NEXT: vmerge.vvm v8, v8, v12, v0 ; RV32ZVFHMIN-NEXT: ret ; ; RV64ZVFHMIN-LABEL: vpmerge_vf_nxv16f16: ; RV64ZVFHMIN: # %bb.0: -; RV64ZVFHMIN-NEXT: fcvt.s.h fa5, fa0 -; RV64ZVFHMIN-NEXT: vsetvli a1, zero, e32, m8, ta, ma -; RV64ZVFHMIN-NEXT: vfmv.v.f v16, fa5 -; RV64ZVFHMIN-NEXT: vsetvli zero, a0, e16, m4, tu, mu -; RV64ZVFHMIN-NEXT: vfncvt.f.f.w v8, v16, v0.t +; RV64ZVFHMIN-NEXT: fmv.x.h a1, fa0 +; RV64ZVFHMIN-NEXT: vsetvli zero, a0, e16, m4, ta, ma +; RV64ZVFHMIN-NEXT: vmv.v.x v12, a1 +; RV64ZVFHMIN-NEXT: vsetvli zero, zero, e16, m4, tu, ma +; RV64ZVFHMIN-NEXT: vmerge.vvm v8, v8, v12, v0 ; RV64ZVFHMIN-NEXT: ret %elt.head = insertelement poison, half %a, i32 0 %va = shufflevector %elt.head, poison, zeroinitializer @@ -1296,25 +1296,19 @@ define @vpmerge_vf_nxv32f16(half %a, % ; ; RV32ZVFHMIN-LABEL: vpmerge_vf_nxv32f16: ; RV32ZVFHMIN: # %bb.0: -; RV32ZVFHMIN-NEXT: fcvt.s.h fa5, fa0 -; RV32ZVFHMIN-NEXT: vsetvli a1, zero, e32, m8, ta, ma -; RV32ZVFHMIN-NEXT: vfmv.v.f v24, fa5 -; RV32ZVFHMIN-NEXT: vsetvli zero, zero, e16, m4, ta, ma -; RV32ZVFHMIN-NEXT: vfncvt.f.f.w v16, v24 -; RV32ZVFHMIN-NEXT: vmv.v.v v20, v16 -; RV32ZVFHMIN-NEXT: vsetvli zero, a0, e16, m8, tu, ma +; RV32ZVFHMIN-NEXT: fmv.x.h a1, fa0 +; RV32ZVFHMIN-NEXT: vsetvli zero, a0, e16, m8, ta, ma +; RV32ZVFHMIN-NEXT: vmv.v.x v16, a1 +; RV32ZVFHMIN-NEXT: vsetvli zero, zero, e16, m8, tu, ma ; RV32ZVFHMIN-NEXT: vmerge.vvm v8, v8, v16, v0 ; RV32ZVFHMIN-NEXT: ret ; ; RV64ZVFHMIN-LABEL: vpmerge_vf_nxv32f16: ; RV64ZVFHMIN: # %bb.0: -; RV64ZVFHMIN-NEXT: fcvt.s.h fa5, fa0 -; RV64ZVFHMIN-NEXT: vsetvli a1, zero, e32, m8, ta, ma -; RV64ZVFHMIN-NEXT: vfmv.v.f v24, fa5 -; RV64ZVFHMIN-NEXT: vsetvli zero, zero, e16, m4, ta, ma -; RV64ZVFHMIN-NEXT: vfncvt.f.f.w v16, v24 -; RV64ZVFHMIN-NEXT: vmv.v.v v20, v16 -; RV64ZVFHMIN-NEXT: vsetvli zero, a0, e16, m8, tu, ma +; RV64ZVFHMIN-NEXT: fmv.x.h a1, fa0 +; RV64ZVFHMIN-NEXT: vsetvli zero, a0, e16, m8, ta, ma +; RV64ZVFHMIN-NEXT: vmv.v.x v16, a1 +; RV64ZVFHMIN-NEXT: vsetvli zero, zero, e16, m8, tu, ma ; RV64ZVFHMIN-NEXT: vmerge.vvm v8, v8, v16, v0 ; RV64ZVFHMIN-NEXT: ret %elt.head = insertelement poison, half %a, i32 0 diff --git a/llvm/test/CodeGen/RISCV/rvv/vselect-bf16.ll b/llvm/test/CodeGen/RISCV/rvv/vselect-bf16.ll index ac4e417f0fe75c..a63d14e8b6c04e 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vselect-bf16.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vselect-bf16.ll @@ -21,11 +21,10 @@ define @vfmerge_vv_nxv1bf16( %va, @vfmerge_fv_nxv1bf16( %va, bfloat %b, %cond) { ; CHECK-LABEL: vfmerge_fv_nxv1bf16: ; CHECK: # %bb.0: -; CHECK-NEXT: fcvt.s.bf16 fa5, fa0 -; CHECK-NEXT: vsetvli a0, zero, e32, mf2, ta, ma -; CHECK-NEXT: vfmv.v.f v9, fa5 -; CHECK-NEXT: vsetvli zero, zero, e16, mf4, ta, mu -; CHECK-NEXT: vfncvtbf16.f.f.w v8, v9, v0.t +; CHECK-NEXT: fmv.x.h a0, fa0 +; CHECK-NEXT: vsetvli a1, zero, e16, mf4, ta, ma +; CHECK-NEXT: vmv.v.x v9, a0 +; CHECK-NEXT: vmerge.vvm v8, v8, v9, v0 ; CHECK-NEXT: ret %head = insertelement poison, bfloat %b, i32 0 %splat = shufflevector %head, poison, zeroinitializer @@ -46,11 +45,10 @@ define @vfmerge_vv_nxv2bf16( %va, @vfmerge_fv_nxv2bf16( %va, bfloat %b, %cond) { ; CHECK-LABEL: vfmerge_fv_nxv2bf16: ; CHECK: # %bb.0: -; CHECK-NEXT: fcvt.s.bf16 fa5, fa0 -; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, ma -; CHECK-NEXT: vfmv.v.f v9, fa5 -; CHECK-NEXT: vsetvli zero, zero, e16, mf2, ta, mu -; CHECK-NEXT: vfncvtbf16.f.f.w v8, v9, v0.t +; CHECK-NEXT: fmv.x.h a0, fa0 +; CHECK-NEXT: vsetvli a1, zero, e16, mf2, ta, ma +; CHECK-NEXT: vmv.v.x v9, a0 +; CHECK-NEXT: vmerge.vvm v8, v8, v9, v0 ; CHECK-NEXT: ret %head = insertelement poison, bfloat %b, i32 0 %splat = shufflevector %head, poison, zeroinitializer @@ -71,11 +69,10 @@ define @vfmerge_vv_nxv4bf16( %va, @vfmerge_fv_nxv4bf16( %va, bfloat %b, %cond) { ; CHECK-LABEL: vfmerge_fv_nxv4bf16: ; CHECK: # %bb.0: -; CHECK-NEXT: fcvt.s.bf16 fa5, fa0 -; CHECK-NEXT: vsetvli a0, zero, e32, m2, ta, ma -; CHECK-NEXT: vfmv.v.f v10, fa5 -; CHECK-NEXT: vsetvli zero, zero, e16, m1, ta, mu -; CHECK-NEXT: vfncvtbf16.f.f.w v8, v10, v0.t +; CHECK-NEXT: fmv.x.h a0, fa0 +; CHECK-NEXT: vsetvli a1, zero, e16, m1, ta, ma +; CHECK-NEXT: vmv.v.x v9, a0 +; CHECK-NEXT: vmerge.vvm v8, v8, v9, v0 ; CHECK-NEXT: ret %head = insertelement poison, bfloat %b, i32 0 %splat = shufflevector %head, poison, zeroinitializer @@ -96,11 +93,10 @@ define @vfmerge_vv_nxv8bf16( %va, @vfmerge_fv_nxv8bf16( %va, bfloat %b, %cond) { ; CHECK-LABEL: vfmerge_fv_nxv8bf16: ; CHECK: # %bb.0: -; CHECK-NEXT: fcvt.s.bf16 fa5, fa0 -; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, ma -; CHECK-NEXT: vfmv.v.f v12, fa5 -; CHECK-NEXT: vsetvli zero, zero, e16, m2, ta, mu -; CHECK-NEXT: vfncvtbf16.f.f.w v8, v12, v0.t +; CHECK-NEXT: fmv.x.h a0, fa0 +; CHECK-NEXT: vsetvli a1, zero, e16, m2, ta, ma +; CHECK-NEXT: vmv.v.x v10, a0 +; CHECK-NEXT: vmerge.vvm v8, v8, v10, v0 ; CHECK-NEXT: ret %head = insertelement poison, bfloat %b, i32 0 %splat = shufflevector %head, poison, zeroinitializer @@ -112,7 +108,8 @@ define @vfmerge_zv_nxv8bf16( %va, %cond, splat (bfloat zeroinitializer), %va ret %vc @@ -148,11 +145,10 @@ define @vfmerge_vv_nxv16bf16( %va, define @vfmerge_fv_nxv16bf16( %va, bfloat %b, %cond) { ; CHECK-LABEL: vfmerge_fv_nxv16bf16: ; CHECK: # %bb.0: -; CHECK-NEXT: fcvt.s.bf16 fa5, fa0 -; CHECK-NEXT: vsetvli a0, zero, e32, m8, ta, ma -; CHECK-NEXT: vfmv.v.f v16, fa5 -; CHECK-NEXT: vsetvli zero, zero, e16, m4, ta, mu -; CHECK-NEXT: vfncvtbf16.f.f.w v8, v16, v0.t +; CHECK-NEXT: fmv.x.h a0, fa0 +; CHECK-NEXT: vsetvli a1, zero, e16, m4, ta, ma +; CHECK-NEXT: vmv.v.x v12, a0 +; CHECK-NEXT: vmerge.vvm v8, v8, v12, v0 ; CHECK-NEXT: ret %head = insertelement poison, bfloat %b, i32 0 %splat = shufflevector %head, poison, zeroinitializer @@ -173,14 +169,10 @@ define @vfmerge_vv_nxv32bf16( %va, define @vfmerge_fv_nxv32bf16( %va, bfloat %b, %cond) { ; CHECK-LABEL: vfmerge_fv_nxv32bf16: ; CHECK: # %bb.0: -; CHECK-NEXT: fcvt.s.bf16 fa5, fa0 -; CHECK-NEXT: vsetvli a0, zero, e32, m8, ta, ma -; CHECK-NEXT: vfmv.v.f v16, fa5 -; CHECK-NEXT: vsetvli zero, zero, e16, m4, ta, ma -; CHECK-NEXT: vfncvtbf16.f.f.w v24, v16 -; CHECK-NEXT: vmv.v.v v28, v24 -; CHECK-NEXT: vsetvli a0, zero, e16, m8, ta, ma -; CHECK-NEXT: vmerge.vvm v8, v8, v24, v0 +; CHECK-NEXT: fmv.x.h a0, fa0 +; CHECK-NEXT: vsetvli a1, zero, e16, m8, ta, ma +; CHECK-NEXT: vmv.v.x v16, a0 +; CHECK-NEXT: vmerge.vvm v8, v8, v16, v0 ; CHECK-NEXT: ret %head = insertelement poison, bfloat %b, i32 0 %splat = shufflevector %head, poison, zeroinitializer diff --git a/llvm/test/CodeGen/RISCV/rvv/vselect-fp.ll b/llvm/test/CodeGen/RISCV/rvv/vselect-fp.ll index 2a3a3a3daae4c4..1f1a62f57664f3 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vselect-fp.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vselect-fp.ll @@ -27,11 +27,10 @@ define @vfmerge_fv_nxv1f16( %va, half %b, ; ; CHECK-ZVFHMIN-LABEL: vfmerge_fv_nxv1f16: ; CHECK-ZVFHMIN: # %bb.0: -; CHECK-ZVFHMIN-NEXT: fcvt.s.h fa5, fa0 -; CHECK-ZVFHMIN-NEXT: vsetvli a0, zero, e32, mf2, ta, ma -; CHECK-ZVFHMIN-NEXT: vfmv.v.f v9, fa5 -; CHECK-ZVFHMIN-NEXT: vsetvli zero, zero, e16, mf4, ta, mu -; CHECK-ZVFHMIN-NEXT: vfncvt.f.f.w v8, v9, v0.t +; CHECK-ZVFHMIN-NEXT: fmv.x.h a0, fa0 +; CHECK-ZVFHMIN-NEXT: vsetvli a1, zero, e16, mf4, ta, ma +; CHECK-ZVFHMIN-NEXT: vmv.v.x v9, a0 +; CHECK-ZVFHMIN-NEXT: vmerge.vvm v8, v8, v9, v0 ; CHECK-ZVFHMIN-NEXT: ret %head = insertelement poison, half %b, i32 0 %splat = shufflevector %head, poison, zeroinitializer @@ -58,11 +57,10 @@ define @vfmerge_fv_nxv2f16( %va, half %b, ; ; CHECK-ZVFHMIN-LABEL: vfmerge_fv_nxv2f16: ; CHECK-ZVFHMIN: # %bb.0: -; CHECK-ZVFHMIN-NEXT: fcvt.s.h fa5, fa0 -; CHECK-ZVFHMIN-NEXT: vsetvli a0, zero, e32, m1, ta, ma -; CHECK-ZVFHMIN-NEXT: vfmv.v.f v9, fa5 -; CHECK-ZVFHMIN-NEXT: vsetvli zero, zero, e16, mf2, ta, mu -; CHECK-ZVFHMIN-NEXT: vfncvt.f.f.w v8, v9, v0.t +; CHECK-ZVFHMIN-NEXT: fmv.x.h a0, fa0 +; CHECK-ZVFHMIN-NEXT: vsetvli a1, zero, e16, mf2, ta, ma +; CHECK-ZVFHMIN-NEXT: vmv.v.x v9, a0 +; CHECK-ZVFHMIN-NEXT: vmerge.vvm v8, v8, v9, v0 ; CHECK-ZVFHMIN-NEXT: ret %head = insertelement poison, half %b, i32 0 %splat = shufflevector %head, poison, zeroinitializer @@ -89,11 +87,10 @@ define @vfmerge_fv_nxv4f16( %va, half %b, ; ; CHECK-ZVFHMIN-LABEL: vfmerge_fv_nxv4f16: ; CHECK-ZVFHMIN: # %bb.0: -; CHECK-ZVFHMIN-NEXT: fcvt.s.h fa5, fa0 -; CHECK-ZVFHMIN-NEXT: vsetvli a0, zero, e32, m2, ta, ma -; CHECK-ZVFHMIN-NEXT: vfmv.v.f v10, fa5 -; CHECK-ZVFHMIN-NEXT: vsetvli zero, zero, e16, m1, ta, mu -; CHECK-ZVFHMIN-NEXT: vfncvt.f.f.w v8, v10, v0.t +; CHECK-ZVFHMIN-NEXT: fmv.x.h a0, fa0 +; CHECK-ZVFHMIN-NEXT: vsetvli a1, zero, e16, m1, ta, ma +; CHECK-ZVFHMIN-NEXT: vmv.v.x v9, a0 +; CHECK-ZVFHMIN-NEXT: vmerge.vvm v8, v8, v9, v0 ; CHECK-ZVFHMIN-NEXT: ret %head = insertelement poison, half %b, i32 0 %splat = shufflevector %head, poison, zeroinitializer @@ -120,11 +117,10 @@ define @vfmerge_fv_nxv8f16( %va, half %b, ; ; CHECK-ZVFHMIN-LABEL: vfmerge_fv_nxv8f16: ; CHECK-ZVFHMIN: # %bb.0: -; CHECK-ZVFHMIN-NEXT: fcvt.s.h fa5, fa0 -; CHECK-ZVFHMIN-NEXT: vsetvli a0, zero, e32, m4, ta, ma -; CHECK-ZVFHMIN-NEXT: vfmv.v.f v12, fa5 -; CHECK-ZVFHMIN-NEXT: vsetvli zero, zero, e16, m2, ta, mu -; CHECK-ZVFHMIN-NEXT: vfncvt.f.f.w v8, v12, v0.t +; CHECK-ZVFHMIN-NEXT: fmv.x.h a0, fa0 +; CHECK-ZVFHMIN-NEXT: vsetvli a1, zero, e16, m2, ta, ma +; CHECK-ZVFHMIN-NEXT: vmv.v.x v10, a0 +; CHECK-ZVFHMIN-NEXT: vmerge.vvm v8, v8, v10, v0 ; CHECK-ZVFHMIN-NEXT: ret %head = insertelement poison, half %b, i32 0 %splat = shufflevector %head, poison, zeroinitializer @@ -133,22 +129,37 @@ define @vfmerge_fv_nxv8f16( %va, half %b, } define @vfmerge_zv_nxv8f16( %va, %cond) { -; CHECK-LABEL: vfmerge_zv_nxv8f16: -; CHECK: # %bb.0: -; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, ma -; CHECK-NEXT: vmerge.vim v8, v8, 0, v0 -; CHECK-NEXT: ret +; CHECK-ZVFH-LABEL: vfmerge_zv_nxv8f16: +; CHECK-ZVFH: # %bb.0: +; CHECK-ZVFH-NEXT: vsetvli a0, zero, e16, m2, ta, ma +; CHECK-ZVFH-NEXT: vmerge.vim v8, v8, 0, v0 +; CHECK-ZVFH-NEXT: ret +; +; CHECK-ZVFHMIN-LABEL: vfmerge_zv_nxv8f16: +; CHECK-ZVFHMIN: # %bb.0: +; CHECK-ZVFHMIN-NEXT: vsetvli a0, zero, e16, m2, ta, ma +; CHECK-ZVFHMIN-NEXT: vmv.v.i v10, 0 +; CHECK-ZVFHMIN-NEXT: vmerge.vvm v8, v8, v10, v0 +; CHECK-ZVFHMIN-NEXT: ret %vc = select %cond, splat (half zeroinitializer), %va ret %vc } define @vfmerge_nzv_nxv8f16( %va, %cond) { -; CHECK-LABEL: vfmerge_nzv_nxv8f16: -; CHECK: # %bb.0: -; CHECK-NEXT: lui a0, 1048568 -; CHECK-NEXT: vsetvli a1, zero, e16, m2, ta, ma -; CHECK-NEXT: vmerge.vxm v8, v8, a0, v0 -; CHECK-NEXT: ret +; CHECK-ZVFH-LABEL: vfmerge_nzv_nxv8f16: +; CHECK-ZVFH: # %bb.0: +; CHECK-ZVFH-NEXT: lui a0, 1048568 +; CHECK-ZVFH-NEXT: vsetvli a1, zero, e16, m2, ta, ma +; CHECK-ZVFH-NEXT: vmerge.vxm v8, v8, a0, v0 +; CHECK-ZVFH-NEXT: ret +; +; CHECK-ZVFHMIN-LABEL: vfmerge_nzv_nxv8f16: +; CHECK-ZVFHMIN: # %bb.0: +; CHECK-ZVFHMIN-NEXT: lui a0, 1048568 +; CHECK-ZVFHMIN-NEXT: vsetvli a1, zero, e16, m2, ta, ma +; CHECK-ZVFHMIN-NEXT: vmv.v.x v10, a0 +; CHECK-ZVFHMIN-NEXT: vmerge.vvm v8, v8, v10, v0 +; CHECK-ZVFHMIN-NEXT: ret %vc = select %cond, splat (half -0.0), %va ret %vc } @@ -189,11 +200,10 @@ define @vfmerge_fv_nxv16f16( %va, half ; ; CHECK-ZVFHMIN-LABEL: vfmerge_fv_nxv16f16: ; CHECK-ZVFHMIN: # %bb.0: -; CHECK-ZVFHMIN-NEXT: fcvt.s.h fa5, fa0 -; CHECK-ZVFHMIN-NEXT: vsetvli a0, zero, e32, m8, ta, ma -; CHECK-ZVFHMIN-NEXT: vfmv.v.f v16, fa5 -; CHECK-ZVFHMIN-NEXT: vsetvli zero, zero, e16, m4, ta, mu -; CHECK-ZVFHMIN-NEXT: vfncvt.f.f.w v8, v16, v0.t +; CHECK-ZVFHMIN-NEXT: fmv.x.h a0, fa0 +; CHECK-ZVFHMIN-NEXT: vsetvli a1, zero, e16, m4, ta, ma +; CHECK-ZVFHMIN-NEXT: vmv.v.x v12, a0 +; CHECK-ZVFHMIN-NEXT: vmerge.vvm v8, v8, v12, v0 ; CHECK-ZVFHMIN-NEXT: ret %head = insertelement poison, half %b, i32 0 %splat = shufflevector %head, poison, zeroinitializer @@ -220,14 +230,10 @@ define @vfmerge_fv_nxv32f16( %va, half ; ; CHECK-ZVFHMIN-LABEL: vfmerge_fv_nxv32f16: ; CHECK-ZVFHMIN: # %bb.0: -; CHECK-ZVFHMIN-NEXT: fcvt.s.h fa5, fa0 -; CHECK-ZVFHMIN-NEXT: vsetvli a0, zero, e32, m8, ta, ma -; CHECK-ZVFHMIN-NEXT: vfmv.v.f v16, fa5 -; CHECK-ZVFHMIN-NEXT: vsetvli zero, zero, e16, m4, ta, ma -; CHECK-ZVFHMIN-NEXT: vfncvt.f.f.w v24, v16 -; CHECK-ZVFHMIN-NEXT: vmv.v.v v28, v24 -; CHECK-ZVFHMIN-NEXT: vsetvli a0, zero, e16, m8, ta, ma -; CHECK-ZVFHMIN-NEXT: vmerge.vvm v8, v8, v24, v0 +; CHECK-ZVFHMIN-NEXT: fmv.x.h a0, fa0 +; CHECK-ZVFHMIN-NEXT: vsetvli a1, zero, e16, m8, ta, ma +; CHECK-ZVFHMIN-NEXT: vmv.v.x v16, a0 +; CHECK-ZVFHMIN-NEXT: vmerge.vvm v8, v8, v16, v0 ; CHECK-ZVFHMIN-NEXT: ret %head = insertelement poison, half %b, i32 0 %splat = shufflevector %head, poison, zeroinitializer diff --git a/llvm/test/CodeGen/RISCV/rvv/vsplats-bf16.ll b/llvm/test/CodeGen/RISCV/rvv/vsplats-bf16.ll index ae57f6b054b120..af9881aca03bc5 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vsplats-bf16.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vsplats-bf16.ll @@ -3,22 +3,58 @@ ; RUN: | FileCheck %s ; RUN: llc -mtriple=riscv64 -mattr=+f,+d,+zfbfmin,+zvfbfmin,+v -target-abi lp64d -verify-machineinstrs < %s \ ; RUN: | FileCheck %s +; RUN: llc -mtriple=riscv32 -mattr=+f,+d,+zvfbfmin,+v -target-abi ilp32d -verify-machineinstrs < %s \ +; RUN: | FileCheck %s --check-prefixes=NOZFBFMIN +; RUN: llc -mtriple=riscv64 -mattr=+f,+d,+zvfbfmin,+v -target-abi lp64d -verify-machineinstrs < %s \ +; RUN: | FileCheck %s --check-prefixes=NOZFBFMIN -define @vsplat_zero_nxv8f16() { -; CHECK-LABEL: vsplat_zero_nxv8f16: +define @vsplat_nxv8bf16(bfloat %f) { +; CHECK-LABEL: vsplat_nxv8bf16: +; CHECK: # %bb.0: +; CHECK-NEXT: fmv.x.h a0, fa0 +; CHECK-NEXT: vsetvli a1, zero, e16, m2, ta, ma +; CHECK-NEXT: vmv.v.x v8, a0 +; CHECK-NEXT: ret +; +; NOZFBFMIN-LABEL: vsplat_nxv8bf16: +; NOZFBFMIN: # %bb.0: +; NOZFBFMIN-NEXT: fmv.x.w a0, fa0 +; NOZFBFMIN-NEXT: vsetvli a1, zero, e16, m2, ta, ma +; NOZFBFMIN-NEXT: vmv.v.x v8, a0 +; NOZFBFMIN-NEXT: ret + %head = insertelement poison, bfloat %f, i32 0 + %splat = shufflevector %head, poison, zeroinitializer + ret %splat +} + +define @vsplat_zero_nxv8bf16() { +; CHECK-LABEL: vsplat_zero_nxv8bf16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, ma ; CHECK-NEXT: vmv.v.i v8, 0 ; CHECK-NEXT: ret +; +; NOZFBFMIN-LABEL: vsplat_zero_nxv8bf16: +; NOZFBFMIN: # %bb.0: +; NOZFBFMIN-NEXT: vsetvli a0, zero, e16, m2, ta, ma +; NOZFBFMIN-NEXT: vmv.v.i v8, 0 +; NOZFBFMIN-NEXT: ret ret splat (bfloat zeroinitializer) } -define @vsplat_negzero_nxv8f16() { -; CHECK-LABEL: vsplat_negzero_nxv8f16: +define @vsplat_negzero_nxv8bf16() { +; CHECK-LABEL: vsplat_negzero_nxv8bf16: ; CHECK: # %bb.0: ; CHECK-NEXT: lui a0, 1048568 ; CHECK-NEXT: vsetvli a1, zero, e16, m2, ta, ma ; CHECK-NEXT: vmv.v.x v8, a0 ; CHECK-NEXT: ret +; +; NOZFBFMIN-LABEL: vsplat_negzero_nxv8bf16: +; NOZFBFMIN: # %bb.0: +; NOZFBFMIN-NEXT: lui a0, 1048568 +; NOZFBFMIN-NEXT: vsetvli a1, zero, e16, m2, ta, ma +; NOZFBFMIN-NEXT: vmv.v.x v8, a0 +; NOZFBFMIN-NEXT: ret ret splat (bfloat -0.0) } diff --git a/llvm/test/CodeGen/RISCV/rvv/vsplats-f16.ll b/llvm/test/CodeGen/RISCV/rvv/vsplats-f16.ll new file mode 100644 index 00000000000000..05a5e5bd32d4d5 --- /dev/null +++ b/llvm/test/CodeGen/RISCV/rvv/vsplats-f16.ll @@ -0,0 +1,20 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py +; RUN: llc -mtriple=riscv32 -mattr=+f,+d,+zvfhmin,+v -target-abi ilp32d -verify-machineinstrs < %s \ +; RUN: | FileCheck %s --check-prefixes=CHECK +; RUN: llc -mtriple=riscv64 -mattr=+f,+d,+zvfhmin,+v -target-abi lp64d -verify-machineinstrs < %s \ +; RUN: | FileCheck %s --check-prefixes=CHECK + +; Test that we don't crash when scalar f16 isn't legal. Other configurations +; are tested in vsplats-fp.ll + +define @vsplat_nxv8f16(half %f) { +; CHECK-LABEL: vsplat_nxv8f16: +; CHECK: # %bb.0: +; CHECK-NEXT: fmv.x.w a0, fa0 +; CHECK-NEXT: vsetvli a1, zero, e16, m2, ta, ma +; CHECK-NEXT: vmv.v.x v8, a0 +; CHECK-NEXT: ret + %head = insertelement poison, half %f, i32 0 + %splat = shufflevector %head, poison, zeroinitializer + ret %splat +} diff --git a/llvm/test/CodeGen/RISCV/rvv/vsplats-fp.ll b/llvm/test/CodeGen/RISCV/rvv/vsplats-fp.ll index 8a8c562bfb5fe3..8317690e3fd25d 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vsplats-fp.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vsplats-fp.ll @@ -25,11 +25,9 @@ define @vsplat_nxv8f16(half %f) { ; ; ZVFHMIN-LABEL: vsplat_nxv8f16: ; ZVFHMIN: # %bb.0: -; ZVFHMIN-NEXT: fcvt.s.h fa5, fa0 -; ZVFHMIN-NEXT: vsetvli a0, zero, e32, m4, ta, ma -; ZVFHMIN-NEXT: vfmv.v.f v12, fa5 -; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m2, ta, ma -; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v12 +; ZVFHMIN-NEXT: fmv.x.h a0, fa0 +; ZVFHMIN-NEXT: vsetvli a1, zero, e16, m2, ta, ma +; ZVFHMIN-NEXT: vmv.v.x v8, a0 ; ZVFHMIN-NEXT: ret %head = insertelement poison, half %f, i32 0 %splat = shufflevector %head, poison, zeroinitializer