diff --git a/clang/test/Driver/print-supported-extensions-riscv.c b/clang/test/Driver/print-supported-extensions-riscv.c index 91f12b8416b2a4..132422393170a9 100644 --- a/clang/test/Driver/print-supported-extensions-riscv.c +++ b/clang/test/Driver/print-supported-extensions-riscv.c @@ -172,6 +172,8 @@ // CHECK-NEXT: zicfiss 1.0 'Zicfiss' (Shadow stack) // CHECK-NEXT: zacas 1.0 'Zacas' (Atomic Compare-And-Swap Instructions) // CHECK-NEXT: zalasr 0.1 'Zalasr' (Load-Acquire and Store-Release Instructions) +// CHECK-NEXT: zvbc32e 0.7 'Zvbc32e' (Vector Carryless Multiplication with 32-bits elements) +// CHECK-NEXT: zvkgs 0.7 'Zvkgs' (Vector-Scalar GCM instructions for Cryptography) // CHECK-NEXT: smmpm 1.0 'Smmpm' (Machine-level Pointer Masking for M-mode) // CHECK-NEXT: smnpm 1.0 'Smnpm' (Machine-level Pointer Masking for next lower privilege mode) // CHECK-NEXT: ssnpm 1.0 'Ssnpm' (Supervisor-level Pointer Masking for next lower privilege mode) diff --git a/clang/test/Preprocessor/riscv-target-features.c b/clang/test/Preprocessor/riscv-target-features.c index 72131108cb5f6a..517702fab5b919 100644 --- a/clang/test/Preprocessor/riscv-target-features.c +++ b/clang/test/Preprocessor/riscv-target-features.c @@ -187,8 +187,10 @@ // CHECK-NOT: __riscv_zicfilp {{.*$}} // CHECK-NOT: __riscv_zicfiss {{.*$}} // CHECK-NOT: __riscv_ztso {{.*$}} +// CHECK-NOT: __riscv_zvbc32e {{.*$}} // CHECK-NOT: __riscv_zvfbfmin {{.*$}} // CHECK-NOT: __riscv_zvfbfwma {{.*$}} +// CHECK-NOT: __riscv_zvkgs {{.*$}} // RUN: %clang --target=riscv32-unknown-linux-gnu \ // RUN: -march=rv32ia -E -dM %s \ @@ -1658,6 +1660,14 @@ // RUN: -o - | FileCheck --check-prefix=CHECK-ZTSO-EXT %s // CHECK-ZTSO-EXT: __riscv_ztso 1000000{{$}} +// RUN: %clang --target=riscv32 -menable-experimental-extensions \ +// RUN: -march=rv32i_zve32x_zvbc32e0p7 -E -dM %s \ +// RUN: -o - | FileCheck --check-prefix=CHECK-ZVBC32E-EXT %s +// RUN: %clang --target=riscv64 -menable-experimental-extensions \ +// RUN: -march=rv64i_zve32x_zvbc32e0p7 -E -dM %s \ +// RUN: -o - | FileCheck --check-prefix=CHECK-ZVBC32E-EXT %s +// CHECK-ZVBC32E-EXT: __riscv_zvbc32e 7000{{$}} + // RUN: %clang --target=riscv32 -menable-experimental-extensions \ // RUN: -march=rv32ifzvfbfmin1p0 -E -dM %s \ // RUN: -o - | FileCheck --check-prefix=CHECK-ZVFBFMIN-EXT %s @@ -1674,6 +1684,14 @@ // RUN: -o - | FileCheck --check-prefix=CHECK-ZVFBFWMA-EXT %s // CHECK-ZVFBFWMA-EXT: __riscv_zvfbfwma 1000000{{$}} +// RUN: %clang --target=riscv32 -menable-experimental-extensions \ +// RUN: -march=rv32i_zve32x_zvkgs0p7 -E -dM %s \ +// RUN: -o - | FileCheck --check-prefix=CHECK-ZVKGS-EXT %s +// RUN: %clang --target=riscv64 -menable-experimental-extensions \ +// RUN: -march=rv64i_zve32x_zvkgs0p7 -E -dM %s \ +// RUN: -o - | FileCheck --check-prefix=CHECK-ZVKGS-EXT %s +// CHECK-ZVKGS-EXT: __riscv_zvkgs 7000{{$}} + // RUN: %clang -target riscv32 -menable-experimental-extensions \ // RUN: -march=rv32izicfiss1p0 -E -dM %s \ // RUN: -o - | FileCheck --check-prefix=CHECK-ZICFISS-EXT %s diff --git a/llvm/docs/RISCVUsage.rst b/llvm/docs/RISCVUsage.rst index b3c7b0e3883d01..3af1428138c021 100644 --- a/llvm/docs/RISCVUsage.rst +++ b/llvm/docs/RISCVUsage.rst @@ -302,6 +302,9 @@ The primary goal of experimental support is to assist in the process of ratifica ``experimental-zicfilp``, ``experimental-zicfiss`` LLVM implements the `1.0 release specification `__. +``experimental-zvbc32e``, ``experimental-zvkgs`` + LLVM implements the `0.7 release specification `__. + To use an experimental extension from `clang`, you must add `-menable-experimental-extensions` to the command line, and specify the exact version of the experimental extension you are using. To use an experimental extension with LLVM's internal developer tools (e.g. `llc`, `llvm-objdump`, `llvm-mc`), you must prefix the extension name with `experimental-`. Note that you don't need to specify the version with internal tools, and shouldn't include the `experimental-` prefix with `clang`. Vendor Extensions diff --git a/llvm/docs/ReleaseNotes.rst b/llvm/docs/ReleaseNotes.rst index 42c0ad976089f7..057bd5345fba28 100644 --- a/llvm/docs/ReleaseNotes.rst +++ b/llvm/docs/ReleaseNotes.rst @@ -111,6 +111,7 @@ Changes to the RISC-V Backend * Fixed length vector support using RVV instructions now requires VLEN>=64. This means Zve32x and Zve32f will also require Zvl64b. The prior support was largely untested. +* The ``Zvbc32e`` and ``Zvkgs`` extensions are now supported experimentally. Changes to the WebAssembly Backend ---------------------------------- diff --git a/llvm/lib/Target/RISCV/RISCVFeatures.td b/llvm/lib/Target/RISCV/RISCVFeatures.td index f2610ea7c9768e..a439e75a3d5af4 100644 --- a/llvm/lib/Target/RISCV/RISCVFeatures.td +++ b/llvm/lib/Target/RISCV/RISCVFeatures.td @@ -754,6 +754,14 @@ def HasStdExtZvbc : Predicate<"Subtarget->hasStdExtZvbc()">, AssemblerPredicate<(all_of FeatureStdExtZvbc), "'Zvbc' (Vector Carryless Multiplication)">; +def FeatureStdExtZvbc32e + : RISCVExperimentalExtension<"zvbc32e", 0, 7, + "'Zvbc32e' (Vector Carryless Multiplication with 32-bits elements)">; + +def HasStdExtZvbcOrZvbc32e : Predicate<"Subtarget->hasStdExtZvbc() || Subtarget->hasStdExtZvbc32e()">, + AssemblerPredicate<(any_of FeatureStdExtZvbc, FeatureStdExtZvbc32e), + "'Zvbc' or 'Zvbc32e' (Vector Carryless Multiplication)">; + def FeatureStdExtZvkg : RISCVExtension<"zvkg", 1, 0, "'Zvkg' (Vector GCM instructions for Cryptography)">, @@ -762,6 +770,14 @@ def HasStdExtZvkg : Predicate<"Subtarget->hasStdExtZvkg()">, AssemblerPredicate<(all_of FeatureStdExtZvkg), "'Zvkg' (Vector GCM instructions for Cryptography)">; +def FeatureStdExtZvkgs + : RISCVExperimentalExtension<"zvkgs", 0, 7, + "'Zvkgs' (Vector-Scalar GCM instructions for Cryptography)", + [FeatureStdExtZvkg]>; +def HasStdExtZvkgs : Predicate<"Subtarget->hasStdExtZvkgs()">, + AssemblerPredicate<(all_of FeatureStdExtZvkgs), + "'Zvkgs' (Vector-Scalar GCM instructions for Cryptography)">; + def FeatureStdExtZvkned : RISCVExtension<"zvkned", 1, 0, "'Zvkned' (Vector AES Encryption & Decryption (Single Round))">, diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoZvk.td b/llvm/lib/Target/RISCV/RISCVInstrInfoZvk.td index bf9caa9b30b674..cafd259031746d 100644 --- a/llvm/lib/Target/RISCV/RISCVInstrInfoZvk.td +++ b/llvm/lib/Target/RISCV/RISCVInstrInfoZvk.td @@ -127,10 +127,10 @@ let Predicates = [HasStdExtZvbb] in { defm VWSLL_V : VSHT_IV_V_X_I<"vwsll", 0b110101>; } // Predicates = [HasStdExtZvbb] -let Predicates = [HasStdExtZvbc] in { +let Predicates = [HasStdExtZvbcOrZvbc32e] in { defm VCLMUL_V : VCLMUL_MV_V_X<"vclmul", 0b001100>; defm VCLMULH_V : VCLMUL_MV_V_X<"vclmulh", 0b001101>; -} // Predicates = [HasStdExtZvbc] +} // Predicates = [HasStdExtZvbcOrZvbc32e] let Predicates = [HasStdExtZvkb] in { defm VANDN_V : VALU_IV_V_X<"vandn", 0b000001>; @@ -150,6 +150,14 @@ let Predicates = [HasStdExtZvkg], RVVConstraint = NoConstraint in { SchedBinaryMC<"WriteVGMULV", "ReadVGMULV", "ReadVGMULV">; } // Predicates = [HasStdExtZvkg] +let Predicates = [HasStdExtZvkgs], RVVConstraint = VS2Constraint in { + def VGHSH_VS : PALUVVNoVmTernary<0b100011, OPMVV, "vghsh.vs">, + SchedTernaryMC<"WriteVGHSHV", "ReadVGHSHV", "ReadVGHSHV", + "ReadVGHSHV">; + def VGMUL_VS : PALUVs2NoVmBinary<0b101001, 0b10001, OPMVV, "vgmul.vs">, + SchedBinaryMC<"WriteVGMULV", "ReadVGMULV", "ReadVGMULV">; +} // Predicates = [HasStdExtZvkgs] + let Predicates = [HasStdExtZvknhaOrZvknhb], RVVConstraint = Sha2Constraint in { def VSHA2CH_VV : PALUVVNoVmTernary<0b101110, OPMVV, "vsha2ch.vv">, SchedTernaryMC<"WriteVSHA2CHV", "ReadVSHA2CHV", "ReadVSHA2CHV", diff --git a/llvm/lib/TargetParser/RISCVISAInfo.cpp b/llvm/lib/TargetParser/RISCVISAInfo.cpp index 59df02daf63265..156ee0debab87b 100644 --- a/llvm/lib/TargetParser/RISCVISAInfo.cpp +++ b/llvm/lib/TargetParser/RISCVISAInfo.cpp @@ -750,8 +750,13 @@ Error RISCVISAInfo::checkDependency() { return getError( "'zvbc' requires 'v' or 'zve64*' extension to also be specified"); - if ((Exts.count("zvkb") || Exts.count("zvkg") || Exts.count("zvkned") || - Exts.count("zvknha") || Exts.count("zvksed") || Exts.count("zvksh")) && + if (Exts.count("zvbc32e") && !Exts.count("zve32x")) + return getError( + "'zvbc32e' requires 'v' or 'zve*' extension to also be specified"); + + if ((Exts.count("zvkb") || Exts.count("zvkg") || Exts.count("zvkgs") || + Exts.count("zvkned") || Exts.count("zvknha") || Exts.count("zvksed") || + Exts.count("zvksh")) && !HasVector) return getError( "'zvk*' requires 'v' or 'zve*' extension to also be specified"); diff --git a/llvm/test/CodeGen/RISCV/attributes.ll b/llvm/test/CodeGen/RISCV/attributes.ll index 4f841683a868c4..3aee484beeaa35 100644 --- a/llvm/test/CodeGen/RISCV/attributes.ll +++ b/llvm/test/CodeGen/RISCV/attributes.ll @@ -125,6 +125,8 @@ ; RUN: llc -mtriple=riscv32 -mattr=+zama16b %s -o - | FileCheck --check-prefixes=CHECK,RV32ZAMA16B %s ; RUN: llc -mtriple=riscv32 -mattr=+experimental-zicfilp %s -o - | FileCheck --check-prefix=RV32ZICFILP %s ; RUN: llc -mtriple=riscv32 -mattr=+a,+zabha %s -o - | FileCheck --check-prefix=RV32ZABHA %s +; RUN: llc -mtriple=riscv32 -mattr=+zve32x -mattr=+experimental-zvbc32e %s -o - | FileCheck --check-prefix=RV32ZVBC32E %s +; RUN: llc -mtriple=riscv32 -mattr=+zve32x -mattr=+experimental-zvkgs %s -o - | FileCheck --check-prefix=RV32ZVKGS %s ; RUN: llc -mtriple=riscv32 -mattr=+experimental-ssnpm %s -o - | FileCheck --check-prefix=RV32SSNPM %s ; RUN: llc -mtriple=riscv32 -mattr=+experimental-smnpm %s -o - | FileCheck --check-prefix=RV32SMNPM %s ; RUN: llc -mtriple=riscv32 -mattr=+experimental-smmpm %s -o - | FileCheck --check-prefix=RV32SMMPM %s @@ -263,6 +265,8 @@ ; RUN: llc -mtriple=riscv64 -mattr=+experimental-zalasr %s -o - | FileCheck --check-prefix=RV64ZALASR %s ; RUN: llc -mtriple=riscv64 -mattr=+experimental-zicfilp %s -o - | FileCheck --check-prefix=RV64ZICFILP %s ; RUN: llc -mtriple=riscv64 -mattr=+a,+zabha %s -o - | FileCheck --check-prefix=RV64ZABHA %s +; RUN: llc -mtriple=riscv64 -mattr=+zve32x -mattr=+experimental-zvbc32e %s -o - | FileCheck --check-prefix=RV64ZVBC32E %s +; RUN: llc -mtriple=riscv64 -mattr=+zve32x -mattr=+experimental-zvkgs %s -o - | FileCheck --check-prefix=RV64ZVKGS %s ; RUN: llc -mtriple=riscv64 -mattr=+experimental-ssnpm %s -o - | FileCheck --check-prefix=RV64SSNPM %s ; RUN: llc -mtriple=riscv64 -mattr=+experimental-smnpm %s -o - | FileCheck --check-prefix=RV64SMNPM %s ; RUN: llc -mtriple=riscv64 -mattr=+experimental-smmpm %s -o - | FileCheck --check-prefix=RV64SMMPM %s @@ -409,6 +413,8 @@ ; RV32ZAMA16B: .attribute 5, "rv32i2p1_zama16b1p0" ; RV32ZICFILP: .attribute 5, "rv32i2p1_zicfilp1p0_zicsr2p0" ; RV32ZABHA: .attribute 5, "rv32i2p1_a2p1_zabha1p0" +; RV32ZVBC32E: .attribute 5, "rv32i2p1_zicsr2p0_zvbc32e0p7_zve32x1p0_zvl32b1p0" +; RV32ZVKGS: .attribute 5, "rv32i2p1_zicsr2p0_zve32x1p0_zvkg1p0_zvkgs0p7_zvl32b1p0" ; RV32SSNPM: .attribute 5, "rv32i2p1_ssnpm1p0" ; RV32SMNPM: .attribute 5, "rv32i2p1_smnpm1p0" ; RV32SMMPM: .attribute 5, "rv32i2p1_smmpm1p0" @@ -545,6 +551,8 @@ ; RV64ZALASR: .attribute 5, "rv64i2p1_zalasr0p1" ; RV64ZICFILP: .attribute 5, "rv64i2p1_zicfilp1p0_zicsr2p0" ; RV64ZABHA: .attribute 5, "rv64i2p1_a2p1_zabha1p0" +; RV64ZVBC32E: .attribute 5, "rv64i2p1_zicsr2p0_zvbc32e0p7_zve32x1p0_zvl32b1p0" +; RV64ZVKGS: .attribute 5, "rv64i2p1_zicsr2p0_zve32x1p0_zvkg1p0_zvkgs0p7_zvl32b1p0" ; RV64SSNPM: .attribute 5, "rv64i2p1_ssnpm1p0" ; RV64SMNPM: .attribute 5, "rv64i2p1_smnpm1p0" ; RV64SMMPM: .attribute 5, "rv64i2p1_smmpm1p0" diff --git a/llvm/test/MC/RISCV/rvv/zvbc.s b/llvm/test/MC/RISCV/rvv/zvbc.s index 0eb02d153b79b6..324d6e04a308fe 100644 --- a/llvm/test/MC/RISCV/rvv/zvbc.s +++ b/llvm/test/MC/RISCV/rvv/zvbc.s @@ -7,27 +7,36 @@ # RUN: | FileCheck %s --check-prefix=CHECK-INST # RUN: llvm-mc -triple=riscv32 -filetype=obj --mattr=+zve64x --mattr=+zvbc %s \ # RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN +# RUN: llvm-mc -triple=riscv32 -show-encoding --mattr=+zve32x --mattr=+experimental-zvbc32e %s \ +# RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +# RUN: not llvm-mc -triple=riscv32 -show-encoding %s 2>&1 \ +# RUN: | FileCheck %s --check-prefix=CHECK-ERROR +# RUN: llvm-mc -triple=riscv32 -filetype=obj --mattr=+zve32x --mattr=+experimental-zvbc32e %s \ +# RUN: | llvm-objdump -d --mattr=+zve32x --mattr=+experimental-zvbc32e - \ +# RUN: | FileCheck %s --check-prefix=CHECK-INST +# RUN: llvm-mc -triple=riscv32 -filetype=obj --mattr=+zve32x --mattr=+experimental-zvbc32e %s \ +# RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN vclmul.vv v10, v9, v8 # CHECK-INST: vclmul.vv v10, v9, v8 # CHECK-ENCODING: [0x57,0x25,0x94,0x32] -# CHECK-ERROR: instruction requires the following: 'Zvbc' (Vector Carryless Multiplication){{$}} +# CHECK-ERROR: instruction requires the following: 'Zvbc' or 'Zvbc32e' (Vector Carryless Multiplication){{$}} # CHECK-UNKNOWN: 32942557 vclmul.vx v10, v9, a0 # CHECK-INST: vclmul.vx v10, v9, a0 # CHECK-ENCODING: [0x57,0x65,0x95,0x32] -# CHECK-ERROR: instruction requires the following: 'Zvbc' (Vector Carryless Multiplication){{$}} +# CHECK-ERROR: instruction requires the following: 'Zvbc' or 'Zvbc32e' (Vector Carryless Multiplication){{$}} # CHECK-UNKNOWN: 32956557 vclmulh.vv v10, v9, v8 # CHECK-INST: vclmulh.vv v10, v9, v8 # CHECK-ENCODING: [0x57,0x25,0x94,0x36] -# CHECK-ERROR: instruction requires the following: 'Zvbc' (Vector Carryless Multiplication){{$}} +# CHECK-ERROR: instruction requires the following: 'Zvbc' or 'Zvbc32e' (Vector Carryless Multiplication){{$}} # CHECK-UNKNOWN: 36942557 vclmulh.vx v10, v9, a0 # CHECK-INST: vclmulh.vx v10, v9, a0 # CHECK-ENCODING: [0x57,0x65,0x95,0x36] -# CHECK-ERROR: instruction requires the following: 'Zvbc' (Vector Carryless Multiplication){{$}} +# CHECK-ERROR: instruction requires the following: 'Zvbc' or 'Zvbc32e' (Vector Carryless Multiplication){{$}} # CHECK-UNKNOWN: 36956557 diff --git a/llvm/test/MC/RISCV/rvv/zvkgs.s b/llvm/test/MC/RISCV/rvv/zvkgs.s new file mode 100644 index 00000000000000..5af4e8bb49ccbb --- /dev/null +++ b/llvm/test/MC/RISCV/rvv/zvkgs.s @@ -0,0 +1,21 @@ +# RUN: llvm-mc -triple=riscv32 -show-encoding --mattr=+zve32x --mattr=+experimental-zvkgs %s \ +# RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +# RUN: not llvm-mc -triple=riscv32 -show-encoding %s 2>&1 \ +# RUN: | FileCheck %s --check-prefix=CHECK-ERROR +# RUN: llvm-mc -triple=riscv32 -filetype=obj --mattr=+zve32x --mattr=+experimental-zvkgs %s \ +# RUN: | llvm-objdump -d --mattr=+zve32x --mattr=+experimental-zvkgs - \ +# RUN: | FileCheck %s --check-prefix=CHECK-INST +# RUN: llvm-mc -triple=riscv32 -filetype=obj --mattr=+zve32x --mattr=+experimental-zvkgs %s \ +# RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN + +vghsh.vs v10, v9, v8 +# CHECK-INST: vghsh.vs v10, v9, v8 +# CHECK-ENCODING: [0x77,0x25,0x94,0x8e] +# CHECK-ERROR: instruction requires the following: 'Zvkgs' (Vector-Scalar GCM instructions for Cryptography){{$}} +# CHECK-UNKNOWN: 8e942577 + +vgmul.vs v10, v9 +# CHECK-INST: vgmul.vs v10, v9 +# CHECK-ENCODING: [0x77,0xa5,0x98,0xa6] +# CHECK-ERROR: instruction requires the following: 'Zvkgs' (Vector-Scalar GCM instructions for Cryptography){{$}} +# CHECK-UNKNOWN: a698a577 diff --git a/llvm/unittests/TargetParser/RISCVISAInfoTest.cpp b/llvm/unittests/TargetParser/RISCVISAInfoTest.cpp index bede4e64696c55..426dca50613511 100644 --- a/llvm/unittests/TargetParser/RISCVISAInfoTest.cpp +++ b/llvm/unittests/TargetParser/RISCVISAInfoTest.cpp @@ -1029,6 +1029,8 @@ Experimental extensions zicfiss 1.0 zacas 1.0 zalasr 0.1 + zvbc32e 0.7 + zvkgs 0.7 smmpm 1.0 smnpm 1.0 ssnpm 1.0