From 9f4a25e2a7cd176bd4f946dc651bc18c7a2e8c92 Mon Sep 17 00:00:00 2001 From: Dominik Steenken Date: Mon, 15 Jul 2024 10:39:23 +0200 Subject: [PATCH] Add extended mnemonics (#97571) This PR adds a number of thus-far missing extended mnemonics to the assembler and disassembler for SystemZ. The following mnemonics have been added and are supported for the assembler and disassembler: - `NOP(R)?` - `LFI` - `RISBG(N)?Z` The following mnemonics have been added and are supported for the assembler only: - `JC(TH)?` - `LLG(F|H)I` - `NOT(G)?R` --- lld/test/ELF/systemz-gotent-relax-und-dso.s | 4 +- lld/test/ELF/systemz-gotent-relax.s | 4 +- lld/test/ELF/systemz-init-padding.s | 2 +- lld/test/ELF/systemz-plt.s | 6 +-- .../lib/Target/SystemZ/SystemZInstrFormats.td | 51 +++++++++++++++++-- llvm/lib/Target/SystemZ/SystemZInstrInfo.td | 23 +++++++-- llvm/lib/Target/SystemZ/SystemZScheduleZ13.td | 8 ++- llvm/lib/Target/SystemZ/SystemZScheduleZ14.td | 8 ++- llvm/lib/Target/SystemZ/SystemZScheduleZ15.td | 8 ++- llvm/lib/Target/SystemZ/SystemZScheduleZ16.td | 8 ++- .../lib/Target/SystemZ/SystemZScheduleZ196.td | 7 ++- .../Target/SystemZ/SystemZScheduleZEC12.td | 7 ++- llvm/test/MC/Disassembler/SystemZ/insns.txt | 39 ++++++++------ llvm/test/MC/SystemZ/insn-good-z15.s | 4 ++ llvm/test/MC/SystemZ/insn-good-z196.s | 3 ++ llvm/test/MC/SystemZ/insn-good-zEC12.s | 14 ++++- llvm/test/MC/SystemZ/insn-good.s | 29 +++++++++-- 17 files changed, 181 insertions(+), 44 deletions(-) diff --git a/lld/test/ELF/systemz-gotent-relax-und-dso.s b/lld/test/ELF/systemz-gotent-relax-und-dso.s index fdbda701dad123..5a1bd7f949f897 100644 --- a/lld/test/ELF/systemz-gotent-relax-und-dso.s +++ b/lld/test/ELF/systemz-gotent-relax-und-dso.s @@ -14,9 +14,9 @@ # DISASM: Disassembly of section .text: # DISASM-EMPTY: # DISASM-NEXT: : -# DISASM-NEXT: bc 0, 0 +# DISASM-NEXT: nop 0 # DISASM: : -# DISASM-NEXT: bc 0, 0 +# DISASM-NEXT: nop 0 # DISASM: <_start>: # DISASM-NEXT: lgrl %r1, 0x2400 # DISASM-NEXT: lgrl %r1, 0x2400 diff --git a/lld/test/ELF/systemz-gotent-relax.s b/lld/test/ELF/systemz-gotent-relax.s index 7ff82b9a190006..e84fd8d4653e9c 100644 --- a/lld/test/ELF/systemz-gotent-relax.s +++ b/lld/test/ELF/systemz-gotent-relax.s @@ -30,9 +30,9 @@ # DISASM: Disassembly of section .text: # DISASM: 00000000010011e0 : -# DISASM-NEXT: bc 0, 0 +# DISASM-NEXT: nop 0 # DISASM: 00000000010011e4 : -# DISASM-NEXT: bc 0, 0 +# DISASM-NEXT: nop 0 # DISASM: 00000000010011e8 : # DISASM-NEXT: br %r14 # DISASM: 00000000010011ea <_start>: diff --git a/lld/test/ELF/systemz-init-padding.s b/lld/test/ELF/systemz-init-padding.s index c56b98d43f1b0e..c7d9e33c22b1b2 100644 --- a/lld/test/ELF/systemz-init-padding.s +++ b/lld/test/ELF/systemz-init-padding.s @@ -12,7 +12,7 @@ # CHECK: <.init>: # CHECK-NEXT: brasl %r14, -# CHECK-NEXT: bcr 0, %r7 +# CHECK-NEXT: nopr %r7 # CHECK-NEXT: lg %r4, 272(%r15) .text diff --git a/lld/test/ELF/systemz-plt.s b/lld/test/ELF/systemz-plt.s index 4669f01f588121..c7563cd18c2749 100644 --- a/lld/test/ELF/systemz-plt.s +++ b/lld/test/ELF/systemz-plt.s @@ -48,9 +48,9 @@ # DIS-NEXT: 100102c: d2 07 f0 30 10 08 mvc 48(8,%r15), 8(%r1) # DIS-NEXT: 1001032: e3 10 10 10 00 04 lg %r1, 16(%r1) # DIS-NEXT: 1001038: 07 f1 br %r1 -# DIS-NEXT: 100103a: 07 00 bcr 0, %r0 -# DIS-NEXT: 100103c: 07 00 bcr 0, %r0 -# DIS-NEXT: 100103e: 07 00 bcr 0, %r0 +# DIS-NEXT: 100103a: 07 00 nopr %r0 +# DIS-NEXT: 100103c: 07 00 nopr %r0 +# DIS-NEXT: 100103e: 07 00 nopr %r0 # DIS-NEXT: 1001040: c0 10 00 00 10 54 larl %r1, 0x10030e8 # DIS-NEXT: 1001046: e3 10 10 00 00 04 lg %r1, 0(%r1) # DIS-NEXT: 100104c: 07 f1 br %r1 diff --git a/llvm/lib/Target/SystemZ/SystemZInstrFormats.td b/llvm/lib/Target/SystemZ/SystemZInstrFormats.td index 3dba33b66bf4f4..9a12718db7cb95 100644 --- a/llvm/lib/Target/SystemZ/SystemZInstrFormats.td +++ b/llvm/lib/Target/SystemZ/SystemZInstrFormats.td @@ -363,7 +363,8 @@ class InstRIEe op, dag outs, dag ins, string asmstr, list pattern> let Inst{7-0} = op{7-0}; } -class InstRIEf op, dag outs, dag ins, string asmstr, list pattern> +class InstRIEf op, dag outs, dag ins, string asmstr, list pattern, + bits<8> I3Or = 0, bits<8> I4Or = 0> : InstSystemZ<6, outs, ins, asmstr, pattern> { field bits<48> Inst; field bits<48> SoftFail = 0; @@ -377,8 +378,22 @@ class InstRIEf op, dag outs, dag ins, string asmstr, list pattern> let Inst{47-40} = op{15-8}; let Inst{39-36} = R1; let Inst{35-32} = R2; - let Inst{31-24} = I3; - let Inst{23-16} = I4; + let Inst{31} = !if(I3Or{7}, 1, I3{7}); + let Inst{30} = !if(I3Or{6}, 1, I3{6}); + let Inst{29} = !if(I3Or{5}, 1, I3{5}); + let Inst{28} = !if(I3Or{4}, 1, I3{4}); + let Inst{27} = !if(I3Or{3}, 1, I3{3}); + let Inst{26} = !if(I3Or{2}, 1, I3{2}); + let Inst{25} = !if(I3Or{1}, 1, I3{1}); + let Inst{24} = !if(I3Or{0}, 1, I3{0}); + let Inst{23} = !if(I4Or{7}, 1, I4{7}); + let Inst{22} = !if(I4Or{6}, 1, I4{6}); + let Inst{21} = !if(I4Or{5}, 1, I4{5}); + let Inst{20} = !if(I4Or{4}, 1, I4{4}); + let Inst{19} = !if(I4Or{3}, 1, I4{3}); + let Inst{18} = !if(I4Or{2}, 1, I4{2}); + let Inst{17} = !if(I4Or{1}, 1, I4{1}); + let Inst{16} = !if(I4Or{0}, 1, I4{0}); let Inst{15-8} = I5; let Inst{7-0} = op{7-0}; } @@ -2349,6 +2364,12 @@ class AsmCondBranchRR opcode> : InstRR; +class NeverCondBranchRR opcode> + : InstRR { + let R1 = 0; +} + class FixedCondBranchRR opcode, SDPatternOperator operator = null_frag> : InstRR opcode> (ins imm32zx4:$M1, (bdxaddr12only $B2, $D2, $X2):$XBD2), mnemonic#"\t$M1, $XBD2", []>; +class NeverCondBranchRX opcode> + : InstRXb { + let M1 = 0; +} + class FixedCondBranchRX opcode> : InstRXb { @@ -3439,6 +3467,19 @@ class BinaryRRFa opcode, SDPatternOperator operator, let OpType = "reg"; } + +class UnaryRRFa opcode, SDPatternOperator operator, + RegisterOperand cls1, RegisterOperand cls2> + : InstRRFa { + let R3 = R2; + let M4 = 0; + let OpKey = mnemonic#cls1; + let OpType = "reg"; +} + + multiclass BinaryRRAndK opcode1, bits<16> opcode2, SDPatternOperator operator, RegisterOperand cls1, RegisterOperand cls2> { @@ -4999,11 +5040,11 @@ multiclass CmpSwapRSPair rsOpcode, bits<16> rsyOpcode, } class RotateSelectRIEf opcode, RegisterOperand cls1, - RegisterOperand cls2> + RegisterOperand cls2, bits<8> I3Or = 0, bits<8> I4Or = 0> : InstRIEf { + mnemonic#"\t$R1, $R2, $I3, $I4, $I5", [], I3Or, I4Or> { let Constraints = "$R1 = $R1src"; let DisableEncoding = "$R1src"; } diff --git a/llvm/lib/Target/SystemZ/SystemZInstrInfo.td b/llvm/lib/Target/SystemZ/SystemZInstrInfo.td index 7c6ab3f9b1ab5f..7ab0b366363045 100644 --- a/llvm/lib/Target/SystemZ/SystemZInstrInfo.td +++ b/llvm/lib/Target/SystemZ/SystemZInstrInfo.td @@ -111,11 +111,11 @@ let isBranch = 1, isTerminator = 1, isBarrier = 1 in { // NOPs. These are again variants of the conditional branches, with the // condition mask set to "never". NOP_bare can't be an InstAlias since it // would need R0D hard coded which is not part of ADDR64BitRegClass. -def NOP : InstAlias<"nop\t$XBD", (BCAsm 0, bdxaddr12only:$XBD), 0>; +def NOP : NeverCondBranchRX<"nop", 0x47>; let isAsmParserOnly = 1, hasNoSchedulingInfo = 1, M1 = 0, X2 = 0, B2 = 0, D2 = 0 in def NOP_bare : InstRXb<0x47,(outs), (ins), "nop", []>; -def NOPR : InstAlias<"nopr\t$R", (BCRAsm 0, GR64:$R), 0>; -def NOPR_bare : InstAlias<"nopr", (BCRAsm 0, R0D), 0>; +def NOPR : NeverCondBranchRR<"nopr", 0x07>; +def NOPR_bare : InstAlias<"nopr", (NOPR R0D), 0>; // An alias of BRC 0, label def JNOP : InstAlias<"jnop\t$RI2", (BRCAsm 0, brtarget16:$RI2), 0>; @@ -464,6 +464,8 @@ let isAsCheapAsAMove = 1, isMoveImm = 1, isReMaterializable = 1 in { def LLILF : UnaryRIL<"llilf", 0xC0F, bitconvert, GR64, imm64lf32>; def LLIHF : UnaryRIL<"llihf", 0xC0E, bitconvert, GR64, imm64hf32>; } +def LLGFI : InstAlias<"llgfi\t$R1, $RI1", (LLILF GR64:$R1, imm64lf32:$RI1)>; +def LLGHI : InstAlias<"llghi\t$R1, $RI1", (LLILL GR64:$R1, imm64ll16:$RI1)>; // Register loads. let canFoldAsLoad = 1, SimpleBDXLoad = 1, mayLoad = 1 in { @@ -973,6 +975,7 @@ let isAsCheapAsAMove = 1, isMoveImm = 1, isReMaterializable = 1 in { def IILF : UnaryRIL<"iilf", 0xC09, bitconvert, GR32, uimm32>; def IIHF : UnaryRIL<"iihf", 0xC08, bitconvert, GRH32, uimm32>; } +def LFI : InstAlias<"lfi\t$R1, $RI1", (IILF GR32:$R1, uimm32:$RI1)>; def IILF64 : BinaryAliasRIL; def IIHF64 : BinaryAliasRIL; @@ -1372,6 +1375,10 @@ let Predicates = [FeatureMiscellaneousExtensions3], let isCommutable = 1, CCValues = 0xC, CompareZeroCCMask = 0x8 in { def NORK : BinaryRRFa<"nork", 0xB976, nor, GR32, GR32, GR32>; def NOGRK : BinaryRRFa<"nogrk", 0xB966, nor, GR64, GR64, GR64>; + let isAsmParserOnly = 1 in { + def NOTR : UnaryRRFa<"notr", 0xB976, nor, GR32, GR32>; + def NOTGR : UnaryRRFa<"notgr", 0xB966, nor, GR64, GR64>; + } } // NXOR. @@ -1526,13 +1533,17 @@ def RLLG : BinaryRSY<"rllg", 0xEB1C, shiftop, GR64>; let Defs = [CC] in { let isCodeGenOnly = 1 in def RISBG32 : RotateSelectRIEf<"risbg", 0xEC55, GR32, GR32>; - let CCValues = 0xE, CompareZeroCCMask = 0xE in + let CCValues = 0xE, CompareZeroCCMask = 0xE in { def RISBG : RotateSelectRIEf<"risbg", 0xEC55, GR64, GR64>; + def RISBGZ : RotateSelectRIEf<"risbgz", 0xEC55, GR64, GR64, 0, 128>; + } } // On zEC12 we have a variant of RISBG that does not set CC. -let Predicates = [FeatureMiscellaneousExtensions] in +let Predicates = [FeatureMiscellaneousExtensions] in { def RISBGN : RotateSelectRIEf<"risbgn", 0xEC59, GR64, GR64>; + def RISBGNZ : RotateSelectRIEf<"risbgnz", 0xEC59, GR64, GR64, 0, 128>; +} // Forms of RISBG that only affect one word of the destination register. // They do not set CC. @@ -2330,6 +2341,8 @@ defm : BlockLoadStore; def JCT : MnemonicAlias<"jct", "brct">; def JCTG : MnemonicAlias<"jctg", "brctg">; +def JC : MnemonicAlias<"jc", "brc">; +def JCTH : MnemonicAlias<"jcth", "brcth">; def JAS : MnemonicAlias<"jas", "bras">; def JASL : MnemonicAlias<"jasl", "brasl">; def JXH : MnemonicAlias<"jxh", "brxh">; diff --git a/llvm/lib/Target/SystemZ/SystemZScheduleZ13.td b/llvm/lib/Target/SystemZ/SystemZScheduleZ13.td index 9ce1a0d06b5afd..d0fec02777875a 100644 --- a/llvm/lib/Target/SystemZ/SystemZScheduleZ13.td +++ b/llvm/lib/Target/SystemZ/SystemZScheduleZ13.td @@ -506,9 +506,9 @@ def : InstRW<[WLat5LSU, WLat5LSU, FXa4, LSU, GroupAlone2], def : InstRW<[WLat2LSU, FXa, LSU, NormalGr], (instregex "RLL(G)?$")>; // Rotate and insert -def : InstRW<[WLat1, FXa, NormalGr], (instregex "RISBG(N|32)?$")>; def : InstRW<[WLat1, FXa, NormalGr], (instregex "RISBH(G|H|L)$")>; def : InstRW<[WLat1, FXa, NormalGr], (instregex "RISBL(G|H|L)$")>; +def : InstRW<[WLat1, FXa, NormalGr], (instregex "RISBG(N|32)?(Z)?$")>; def : InstRW<[WLat1, FXa, NormalGr], (instregex "RISBMux$")>; // Rotate and Select @@ -1553,5 +1553,11 @@ def : InstRW<[WLat30, MCD], (instregex "STC(PS|RW)$")>; def : InstRW<[WLat30, MCD], (instregex "TPI$")>; def : InstRW<[WLat30, MCD], (instregex "SAL$")>; +//===----------------------------------------------------------------------===// +// NOPs +//===----------------------------------------------------------------------===// + +def : InstRW<[WLat1, FXb, NormalGr], (instregex "NOP(R)?$")>; + } diff --git a/llvm/lib/Target/SystemZ/SystemZScheduleZ14.td b/llvm/lib/Target/SystemZ/SystemZScheduleZ14.td index 120d4a457ee396..a6d89ce9443c5a 100644 --- a/llvm/lib/Target/SystemZ/SystemZScheduleZ14.td +++ b/llvm/lib/Target/SystemZ/SystemZScheduleZ14.td @@ -516,9 +516,9 @@ def : InstRW<[WLat5LSU, WLat5LSU, FXa4, LSU, GroupAlone2], def : InstRW<[WLat2LSU, FXa, LSU, NormalGr], (instregex "RLL(G)?$")>; // Rotate and insert -def : InstRW<[WLat1, FXa, NormalGr], (instregex "RISBG(N|32)?$")>; def : InstRW<[WLat1, FXa, NormalGr], (instregex "RISBH(G|H|L)$")>; def : InstRW<[WLat1, FXa, NormalGr], (instregex "RISBL(G|H|L)$")>; +def : InstRW<[WLat1, FXa, NormalGr], (instregex "RISBG(N|32)?(Z)?$")>; def : InstRW<[WLat1, FXa, NormalGr], (instregex "RISBMux$")>; // Rotate and Select @@ -1643,5 +1643,11 @@ def : InstRW<[WLat30, MCD], (instregex "STC(PS|RW)$")>; def : InstRW<[WLat30, MCD], (instregex "TPE?I$")>; def : InstRW<[WLat30, MCD], (instregex "SAL$")>; +//===----------------------------------------------------------------------===// +// NOPs +//===----------------------------------------------------------------------===// + +def : InstRW<[WLat1, FXb, NormalGr], (instregex "NOP(R)?$")>; + } diff --git a/llvm/lib/Target/SystemZ/SystemZScheduleZ15.td b/llvm/lib/Target/SystemZ/SystemZScheduleZ15.td index acba3a1fd9919e..455354e283ad8e 100644 --- a/llvm/lib/Target/SystemZ/SystemZScheduleZ15.td +++ b/llvm/lib/Target/SystemZ/SystemZScheduleZ15.td @@ -471,6 +471,7 @@ def : InstRW<[WLat1, FXa, NormalGr], (instregex "NC(G)?RK$")>; def : InstRW<[WLat1, FXa, NormalGr], (instregex "OC(G)?RK$")>; def : InstRW<[WLat1, FXa, NormalGr], (instregex "NN(G)?RK$")>; def : InstRW<[WLat1, FXa, NormalGr], (instregex "NO(G)?RK$")>; +def : InstRW<[WLat1, FXa, NormalGr], (instregex "NOT(G)?R$")>; def : InstRW<[WLat1, FXa, NormalGr], (instregex "NX(G)?RK$")>; //===----------------------------------------------------------------------===// @@ -530,9 +531,9 @@ def : InstRW<[WLat5LSU, WLat5LSU, FXa4, LSU, GroupAlone2], def : InstRW<[WLat2LSU, FXa, LSU, NormalGr], (instregex "RLL(G)?$")>; // Rotate and insert -def : InstRW<[WLat1, FXa, NormalGr], (instregex "RISBG(N|32)?$")>; def : InstRW<[WLat1, FXa, NormalGr], (instregex "RISBH(G|H|L)$")>; def : InstRW<[WLat1, FXa, NormalGr], (instregex "RISBL(G|H|L)$")>; +def : InstRW<[WLat1, FXa, NormalGr], (instregex "RISBG(N|32)?(Z)?$")>; def : InstRW<[WLat1, FXa, NormalGr], (instregex "RISBMux$")>; // Rotate and Select @@ -1689,5 +1690,10 @@ def : InstRW<[WLat30, MCD], (instregex "STC(PS|RW)$")>; def : InstRW<[WLat30, MCD], (instregex "TPE?I$")>; def : InstRW<[WLat30, MCD], (instregex "SAL$")>; +//===----------------------------------------------------------------------===// +// NOPs +//===----------------------------------------------------------------------===// + +def : InstRW<[WLat1, FXb, NormalGr], (instregex "NOP(R)?$")>; } diff --git a/llvm/lib/Target/SystemZ/SystemZScheduleZ16.td b/llvm/lib/Target/SystemZ/SystemZScheduleZ16.td index dd82b2b9b71e75..92abf0ba4022cc 100644 --- a/llvm/lib/Target/SystemZ/SystemZScheduleZ16.td +++ b/llvm/lib/Target/SystemZ/SystemZScheduleZ16.td @@ -471,6 +471,7 @@ def : InstRW<[WLat1, FXa, NormalGr], (instregex "NC(G)?RK$")>; def : InstRW<[WLat1, FXa, NormalGr], (instregex "OC(G)?RK$")>; def : InstRW<[WLat1, FXa, NormalGr], (instregex "NN(G)?RK$")>; def : InstRW<[WLat1, FXa, NormalGr], (instregex "NO(G)?RK$")>; +def : InstRW<[WLat1, FXa, NormalGr], (instregex "NOT(G)?R$")>; def : InstRW<[WLat1, FXa, NormalGr], (instregex "NX(G)?RK$")>; //===----------------------------------------------------------------------===// @@ -530,9 +531,9 @@ def : InstRW<[WLat5LSU, WLat5LSU, FXa4, LSU, GroupAlone2], def : InstRW<[WLat2LSU, FXa, LSU, NormalGr], (instregex "RLL(G)?$")>; // Rotate and insert -def : InstRW<[WLat1, FXa, NormalGr], (instregex "RISBG(N|32)?$")>; def : InstRW<[WLat1, FXa, NormalGr], (instregex "RISBH(G|H|L)$")>; def : InstRW<[WLat1, FXa, NormalGr], (instregex "RISBL(G|H|L)$")>; +def : InstRW<[WLat1, FXa, NormalGr], (instregex "RISBG(N|32)?(Z)?$")>; def : InstRW<[WLat1, FXa, NormalGr], (instregex "RISBMux$")>; // Rotate and Select @@ -1722,5 +1723,10 @@ def : InstRW<[WLat30, MCD], (instregex "STC(PS|RW)$")>; def : InstRW<[WLat30, MCD], (instregex "TPE?I$")>; def : InstRW<[WLat30, MCD], (instregex "SAL$")>; +//===----------------------------------------------------------------------===// +// NOPs +//===----------------------------------------------------------------------===// + +def : InstRW<[WLat1, FXb, NormalGr], (instregex "NOP(R)?$")>; } diff --git a/llvm/lib/Target/SystemZ/SystemZScheduleZ196.td b/llvm/lib/Target/SystemZ/SystemZScheduleZ196.td index 226db9d4272f9b..99d0d674bbbb2f 100644 --- a/llvm/lib/Target/SystemZ/SystemZScheduleZ196.td +++ b/llvm/lib/Target/SystemZ/SystemZScheduleZ196.td @@ -469,9 +469,9 @@ def : InstRW<[WLat5LSU, WLat5LSU, FXU4, LSU, GroupAlone2], def : InstRW<[WLat2LSU, FXU, LSU, NormalGr], (instregex "RLL(G)?$")>; // Rotate and insert -def : InstRW<[WLat1, FXU, NormalGr], (instregex "RISBG(32)?$")>; def : InstRW<[WLat1, FXU, NormalGr], (instregex "RISBH(G|H|L)$")>; def : InstRW<[WLat1, FXU, NormalGr], (instregex "RISBL(G|H|L)$")>; +def : InstRW<[WLat1, FXU, NormalGr], (instregex "RISBG(32)?(Z)?$")>; def : InstRW<[WLat1, FXU, NormalGr], (instregex "RISBMux$")>; // Rotate and Select @@ -1235,5 +1235,10 @@ def : InstRW<[WLat30, MCD], (instregex "STC(PS|RW)$")>; def : InstRW<[WLat30, MCD], (instregex "TPI$")>; def : InstRW<[WLat30, MCD], (instregex "SAL$")>; +//===----------------------------------------------------------------------===// +// NOPs +//===----------------------------------------------------------------------===// + +def : InstRW<[WLat1, LSU, EndGroup], (instregex "NOP(R)?$")>; } diff --git a/llvm/lib/Target/SystemZ/SystemZScheduleZEC12.td b/llvm/lib/Target/SystemZ/SystemZScheduleZEC12.td index f5ecdb1f438009..5b334da2bac342 100644 --- a/llvm/lib/Target/SystemZ/SystemZScheduleZEC12.td +++ b/llvm/lib/Target/SystemZ/SystemZScheduleZEC12.td @@ -480,9 +480,9 @@ def : InstRW<[WLat5LSU, WLat5LSU, FXU4, LSU, GroupAlone2], def : InstRW<[WLat2LSU, FXU, LSU, NormalGr], (instregex "RLL(G)?$")>; // Rotate and insert -def : InstRW<[WLat1, FXU, NormalGr], (instregex "RISBG(N|32)?$")>; def : InstRW<[WLat1, FXU, NormalGr], (instregex "RISBH(G|H|L)$")>; def : InstRW<[WLat1, FXU, NormalGr], (instregex "RISBL(G|H|L)$")>; +def : InstRW<[WLat1, FXU, NormalGr], (instregex "RISBG(N|32)?(Z)?$")>; def : InstRW<[WLat1, FXU, NormalGr], (instregex "RISBMux$")>; // Rotate and Select @@ -1280,5 +1280,10 @@ def : InstRW<[WLat30, MCD], (instregex "STC(PS|RW)$")>; def : InstRW<[WLat30, MCD], (instregex "TPI$")>; def : InstRW<[WLat30, MCD], (instregex "SAL$")>; +//===----------------------------------------------------------------------===// +// NOPs +//===----------------------------------------------------------------------===// + +def : InstRW<[WLat1, LSU, NormalGr], (instregex "NOP(R)?$")>; } diff --git a/llvm/test/MC/Disassembler/SystemZ/insns.txt b/llvm/test/MC/Disassembler/SystemZ/insns.txt index 23714dfc3a8e6e..392993d4e2a36a 100644 --- a/llvm/test/MC/Disassembler/SystemZ/insns.txt +++ b/llvm/test/MC/Disassembler/SystemZ/insns.txt @@ -1315,22 +1315,22 @@ # CHECK: bassm %r15, %r1 0x0c 0xf1 -# CHECK: bc 0, 0 +# CHECK: nop 0 0x47 0x00 0x00 0x00 -# CHECK: bc 0, 4095 +# CHECK: nop 4095 0x47 0x00 0x0f 0xff -# CHECK: bc 0, 0(%r1) +# CHECK: nop 0(%r1) 0x47 0x00 0x10 0x00 -# CHECK: bc 0, 0(%r15) +# CHECK: nop 0(%r15) 0x47 0x00 0xf0 0x00 -# CHECK: bc 0, 4095(%r1,%r15) +# CHECK: nop 4095(%r1,%r15) 0x47 0x01 0xff 0xff -# CHECK: bc 0, 4095(%r15,%r1) +# CHECK: nop 4095(%r15,%r1) 0x47 0x0f 0x1f 0xff # CHECK: bo 0(%r13) @@ -1375,9 +1375,12 @@ # CHECK: bno 0 0x47 0xe0 0x00 0x00 -# CHECK: bcr 0, %r14 +# CHECK: nopr %r14 0x07 0x0e +# CHECK: nopr %r7 +0x07 0x07 + # CHECK: bor %r13 0x07 0x1d @@ -13968,11 +13971,11 @@ # CHECK: risbg %r0, %r0, 0, 0, 0 0xec 0x00 0x00 0x00 0x00 0x55 -# CHECK: risbg %r0, %r0, 0, 0, 63 -0xec 0x00 0x00 0x00 0x3f 0x55 +# CHECK: risbg %r0, %r0, 0, 0, 255 +0xec 0x00 0x00 0x00 0xff 0x55 -# CHECK: risbg %r0, %r0, 0, 255, 0 -0xec 0x00 0x00 0xff 0x00 0x55 +# CHECK: risbg %r0, %r0, 0, 127, 0 +0xec 0x00 0x00 0x7f 0x00 0x55 # CHECK: risbg %r0, %r0, 255, 0, 0 0xec 0x00 0xff 0x00 0x00 0x55 @@ -13986,14 +13989,17 @@ # CHECK: risbg %r4, %r5, 6, 7, 8 0xec 0x45 0x06 0x07 0x08 0x55 +# CHECK: risbgz %r4, %r5, 6, 7, 8 +0xec 0x45 0x06 0x87 0x08 0x55 + # CHECK: risbgn %r0, %r0, 0, 0, 0 0xec 0x00 0x00 0x00 0x00 0x59 -# CHECK: risbgn %r0, %r0, 0, 0, 63 -0xec 0x00 0x00 0x00 0x3f 0x59 +# CHECK: risbgn %r0, %r0, 0, 0, 255 +0xec 0x00 0x00 0x00 0xff 0x59 -# CHECK: risbgn %r0, %r0, 0, 255, 0 -0xec 0x00 0x00 0xff 0x00 0x59 +# CHECK: risbgn %r0, %r0, 0, 127, 0 +0xec 0x00 0x00 0x7f 0x00 0x59 # CHECK: risbgn %r0, %r0, 255, 0, 0 0xec 0x00 0xff 0x00 0x00 0x59 @@ -14007,6 +14013,9 @@ # CHECK: risbgn %r4, %r5, 6, 7, 8 0xec 0x45 0x06 0x07 0x08 0x59 +# CHECK: risbgnz %r4, %r5, 6, 7, 8 +0xec 0x45 0x06 0x87 0x08 0x59 + # CHECK: risbhg %r0, %r0, 0, 0, 0 0xec 0x00 0x00 0x00 0x00 0x5d diff --git a/llvm/test/MC/SystemZ/insn-good-z15.s b/llvm/test/MC/SystemZ/insn-good-z15.s index 36476161ea46de..108f8421162313 100644 --- a/llvm/test/MC/SystemZ/insn-good-z15.s +++ b/llvm/test/MC/SystemZ/insn-good-z15.s @@ -146,24 +146,28 @@ #CHECK: nogrk %r0, %r15, %r0 # encoding: [0xb9,0x66,0x00,0x0f] #CHECK: nogrk %r15, %r0, %r0 # encoding: [0xb9,0x66,0x00,0xf0] #CHECK: nogrk %r7, %r8, %r9 # encoding: [0xb9,0x66,0x90,0x78] +#CHECK: notgr %r7, %r8 # encoding: [0xb9,0x66,0x80,0x78] nogrk %r0,%r0,%r0 nogrk %r0,%r0,%r15 nogrk %r0,%r15,%r0 nogrk %r15,%r0,%r0 nogrk %r7,%r8,%r9 + notgr %r7,%r8 #CHECK: nork %r0, %r0, %r0 # encoding: [0xb9,0x76,0x00,0x00] #CHECK: nork %r0, %r0, %r15 # encoding: [0xb9,0x76,0xf0,0x00] #CHECK: nork %r0, %r15, %r0 # encoding: [0xb9,0x76,0x00,0x0f] #CHECK: nork %r15, %r0, %r0 # encoding: [0xb9,0x76,0x00,0xf0] #CHECK: nork %r7, %r8, %r9 # encoding: [0xb9,0x76,0x90,0x78] +#CHECK: notr %r7, %r8 # encoding: [0xb9,0x76,0x80,0x78] nork %r0,%r0,%r0 nork %r0,%r0,%r15 nork %r0,%r15,%r0 nork %r15,%r0,%r0 nork %r7,%r8,%r9 + notr %r7,%r8 #CHECK: nxgrk %r0, %r0, %r0 # encoding: [0xb9,0x67,0x00,0x00] #CHECK: nxgrk %r0, %r0, %r15 # encoding: [0xb9,0x67,0xf0,0x00] diff --git a/llvm/test/MC/SystemZ/insn-good-z196.s b/llvm/test/MC/SystemZ/insn-good-z196.s index fc90b18e66d8f1..d2a7724d3a9a25 100644 --- a/llvm/test/MC/SystemZ/insn-good-z196.s +++ b/llvm/test/MC/SystemZ/insn-good-z196.s @@ -276,10 +276,13 @@ #CHECK: brcth %r7, frob@PLT # encoding: [0xcc,0x76,A,A,A,A] # fixup A - offset: 2, value: frob@PLT+2, kind: FK_390_PC32DBL #CHECK: brcth %r8, frob@PLT # encoding: [0xcc,0x86,A,A,A,A] +# fixup A - offset: 2, value: frob@PLT+2, kind: FK_390_PC32DBL +#CHECK: brcth %r8, frob@PLT # encoding: [0xcc,0x86,A,A,A,A] # fixup A - offset: 2, value: frob@PLT+2, kind: FK_390_PC32DBL brcth %r7,frob@PLT brcth %r8,frob@PLT + jcth %r8,frob@PLT #CHECK: cdfbra %f0, 0, %r0, 0 # encoding: [0xb3,0x95,0x00,0x00] #CHECK: cdfbra %f0, 0, %r0, 15 # encoding: [0xb3,0x95,0x0f,0x00] diff --git a/llvm/test/MC/SystemZ/insn-good-zEC12.s b/llvm/test/MC/SystemZ/insn-good-zEC12.s index db37d28686e9bb..a564491c6c36fa 100644 --- a/llvm/test/MC/SystemZ/insn-good-zEC12.s +++ b/llvm/test/MC/SystemZ/insn-good-zEC12.s @@ -462,21 +462,33 @@ #CHECK: risbgn %r0, %r0, 0, 0, 63 # encoding: [0xec,0x00,0x00,0x00,0x3f,0x59] #CHECK: risbgn %r0, %r0, 0, 0, 64 # encoding: [0xec,0x00,0x00,0x00,0x40,0x59] #CHECK: risbgn %r0, %r0, 0, 0, 255 # encoding: [0xec,0x00,0x00,0x00,0xff,0x59] -#CHECK: risbgn %r0, %r0, 0, 255, 0 # encoding: [0xec,0x00,0x00,0xff,0x00,0x59] +#CHECK: risbgnz %r0, %r0, 0, 255, 0 # encoding: [0xec,0x00,0x00,0xff,0x00,0x59] +#CHECK: risbgn %r0, %r0, 0, 255, 0 # encoding: [0xec,0x00,0x00,0xff,0x00,0x59] #CHECK: risbgn %r0, %r0, 255, 0, 0 # encoding: [0xec,0x00,0xff,0x00,0x00,0x59] +#CHECK: risbgn %r0, %r0, 0, 0, 127 # encoding: [0xec,0x00,0x00,0x00,0x7f,0x59] +#CHECK: risbgnz %r0, %r0, 0, 127, 0 # encoding: [0xec,0x00,0x00,0xff,0x00,0x59] +#CHECK: risbgn %r0, %r0, 0, 127, 0 # encoding: [0xec,0x00,0x00,0x7f,0x00,0x59] +#CHECK: risbgn %r0, %r0, 127, 0, 0 # encoding: [0xec,0x00,0x7f,0x00,0x00,0x59] #CHECK: risbgn %r0, %r15, 0, 0, 0 # encoding: [0xec,0x0f,0x00,0x00,0x00,0x59] #CHECK: risbgn %r15, %r0, 0, 0, 0 # encoding: [0xec,0xf0,0x00,0x00,0x00,0x59] #CHECK: risbgn %r4, %r5, 6, 7, 8 # encoding: [0xec,0x45,0x06,0x07,0x08,0x59] +#CHECK: risbgnz %r4, %r5, 6, 7, 8 # encoding: [0xec,0x45,0x06,0x87,0x08,0x59] risbgn %r0,%r0,0,0,0 risbgn %r0,%r0,0,0,63 risbgn %r0,%r0,0,0,64 risbgn %r0,%r0,0,0,255 + risbgnz %r0,%r0,0,255,0 risbgn %r0,%r0,0,255,0 risbgn %r0,%r0,255,0,0 + risbgn %r0,%r0,0,0,127 + risbgnz %r0,%r0,0,127,0 + risbgn %r0,%r0,0,127,0 + risbgn %r0,%r0,127,0,0 risbgn %r0,%r15,0,0,0 risbgn %r15,%r0,0,0,0 risbgn %r4,%r5,6,7,8 + risbgnz %r4,%r5,6,7,8 #CHECK: tabort 0 # encoding: [0xb2,0xfc,0x00,0x00] #CHECK: tabort 0(%r1) # encoding: [0xb2,0xfc,0x10,0x00] diff --git a/llvm/test/MC/SystemZ/insn-good.s b/llvm/test/MC/SystemZ/insn-good.s index 2add4a108319e6..9fcb8a42cd73c8 100644 --- a/llvm/test/MC/SystemZ/insn-good.s +++ b/llvm/test/MC/SystemZ/insn-good.s @@ -1441,6 +1441,8 @@ jo foo bro foo +#CHECK: brc 2, foo # encoding: [0xa7,0x24,A,A] +#CHECK: fixup A - offset: 2, value: foo+2, kind: FK_390_PC16DBL #CHECK: brc 2, foo # encoding: [0xa7,0x24,A,A] #CHECK: fixup A - offset: 2, value: foo+2, kind: FK_390_PC16DBL #CHECK: jh foo # encoding: [0xa7,0x24,A,A] @@ -1452,6 +1454,7 @@ #CHECK: jp foo # encoding: [0xa7,0x24,A,A] #CHECK: fixup A - offset: 2, value: foo+2, kind: FK_390_PC16DBL brc 2, foo + jc 2, foo jh foo jp foo brh foo @@ -8694,11 +8697,13 @@ #CHECK: iilf %r0, 0 # encoding: [0xc0,0x09,0x00,0x00,0x00,0x00] #CHECK: iilf %r0, 4294967295 # encoding: [0xc0,0x09,0xff,0xff,0xff,0xff] +#CHECK: iilf %r15, 0 # encoding: [0xc0,0xf9,0x00,0x00,0x00,0x00] #CHECK: iilf %r15, 0 # encoding: [0xc0,0xf9,0x00,0x00,0x00,0x00] iilf %r0, 0 iilf %r0, 0xffffffff iilf %r15, 0 + lfi %r15, 0 #CHECK: iilh %r0, 0 # encoding: [0xa5,0x02,0x00,0x00] #CHECK: iilh %r0, 32768 # encoding: [0xa5,0x02,0x80,0x00] @@ -10335,11 +10340,13 @@ #CHECK: llilf %r0, 0 # encoding: [0xc0,0x0f,0x00,0x00,0x00,0x00] #CHECK: llilf %r0, 4294967295 # encoding: [0xc0,0x0f,0xff,0xff,0xff,0xff] +#CHECK: llilf %r15, 0 # encoding: [0xc0,0xff,0x00,0x00,0x00,0x00] #CHECK: llilf %r15, 0 # encoding: [0xc0,0xff,0x00,0x00,0x00,0x00] llilf %r0, 0 llilf %r0, 0xffffffff llilf %r15, 0 + llgfi %r15, 0 #CHECK: llilh %r0, 0 # encoding: [0xa5,0x0e,0x00,0x00] #CHECK: llilh %r0, 32768 # encoding: [0xa5,0x0e,0x80,0x00] @@ -10354,12 +10361,14 @@ #CHECK: llill %r0, 0 # encoding: [0xa5,0x0f,0x00,0x00] #CHECK: llill %r0, 32768 # encoding: [0xa5,0x0f,0x80,0x00] #CHECK: llill %r0, 65535 # encoding: [0xa5,0x0f,0xff,0xff] +#CHECK: llill %r15, 0 # encoding: [0xa5,0xff,0x00,0x00] #CHECK: llill %r15, 0 # encoding: [0xa5,0xff,0x00,0x00] llill %r0, 0 llill %r0, 0x8000 llill %r0, 0xffff llill %r15, 0 + llghi %r15, 0 #CHECK: lm %r0, %r0, 0 # encoding: [0x98,0x00,0x00,0x00] #CHECK: lm %r0, %r15, 0 # encoding: [0x98,0x0f,0x00,0x00] @@ -13122,10 +13131,10 @@ niy 524287(%r1), 42 niy 524287(%r15), 42 -#CHECK: bc 0, 0 # encoding: [0x47,0x00,0x00,0x00] +#CHECK: nop 0 # encoding: [0x47,0x00,0x00,0x00] #CHECK: nop # encoding: [0x47,0x00,0x00,0x00] -#CHECK: bcr 0, %r7 # encoding: [0x07,0x07] -#CHECK: bcr 0, %r0 # encoding: [0x07,0x00] +#CHECK: nopr %r7 # encoding: [0x07,0x07] +#CHECK: nopr %r0 # encoding: [0x07,0x00] nop 0 nop @@ -13680,21 +13689,33 @@ #CHECK: risbg %r0, %r0, 0, 0, 63 # encoding: [0xec,0x00,0x00,0x00,0x3f,0x55] #CHECK: risbg %r0, %r0, 0, 0, 64 # encoding: [0xec,0x00,0x00,0x00,0x40,0x55] #CHECK: risbg %r0, %r0, 0, 0, 255 # encoding: [0xec,0x00,0x00,0x00,0xff,0x55] -#CHECK: risbg %r0, %r0, 0, 255, 0 # encoding: [0xec,0x00,0x00,0xff,0x00,0x55] +#CHECK: risbgz %r0, %r0, 0, 255, 0 # encoding: [0xec,0x00,0x00,0xff,0x00,0x55] +#CHECK: risbg %r0, %r0, 0, 255, 0 # encoding: [0xec,0x00,0x00,0xff,0x00,0x55] #CHECK: risbg %r0, %r0, 255, 0, 0 # encoding: [0xec,0x00,0xff,0x00,0x00,0x55] +#CHECK: risbg %r0, %r0, 0, 0, 127 # encoding: [0xec,0x00,0x00,0x00,0x7f,0x55] +#CHECK: risbgz %r0, %r0, 0, 127, 0 # encoding: [0xec,0x00,0x00,0xff,0x00,0x55] +#CHECK: risbg %r0, %r0, 0, 127, 0 # encoding: [0xec,0x00,0x00,0x7f,0x00,0x55] +#CHECK: risbg %r0, %r0, 127, 0, 0 # encoding: [0xec,0x00,0x7f,0x00,0x00,0x55] #CHECK: risbg %r0, %r15, 0, 0, 0 # encoding: [0xec,0x0f,0x00,0x00,0x00,0x55] #CHECK: risbg %r15, %r0, 0, 0, 0 # encoding: [0xec,0xf0,0x00,0x00,0x00,0x55] #CHECK: risbg %r4, %r5, 6, 7, 8 # encoding: [0xec,0x45,0x06,0x07,0x08,0x55] +#CHECK: risbgz %r4, %r5, 6, 7, 8 # encoding: [0xec,0x45,0x06,0x87,0x08,0x55] risbg %r0,%r0,0,0,0 risbg %r0,%r0,0,0,63 risbg %r0,%r0,0,0,64 risbg %r0,%r0,0,0,255 + risbgz %r0,%r0,0,255,0 risbg %r0,%r0,0,255,0 risbg %r0,%r0,255,0,0 + risbg %r0,%r0,0,0,127 + risbgz %r0,%r0,0,127,0 + risbg %r0,%r0,0,127,0 + risbg %r0,%r0,127,0,0 risbg %r0,%r15,0,0,0 risbg %r15,%r0,0,0,0 risbg %r4,%r5,6,7,8 + risbgz %r4,%r5,6,7,8 #CHECK: rll %r0, %r0, 0 # encoding: [0xeb,0x00,0x00,0x00,0x00,0x1d] #CHECK: rll %r15, %r1, 0 # encoding: [0xeb,0xf1,0x00,0x00,0x00,0x1d]