From 03b54bc3f239d85ac25c5854373c7fe7bae4dcdb Mon Sep 17 00:00:00 2001
From: Tim Gymnich <tgymnich@icloud.com>
Date: Sun, 14 Jul 2024 15:47:11 +0200
Subject: [PATCH] add test

---
 .../InstCombine/select-of-sym-selects.ll           | 14 ++++++++++++++
 1 file changed, 14 insertions(+)
 create mode 100644 llvm/test/Transforms/InstCombine/select-of-sym-selects.ll

diff --git a/llvm/test/Transforms/InstCombine/select-of-sym-selects.ll b/llvm/test/Transforms/InstCombine/select-of-sym-selects.ll
new file mode 100644
index 00000000000000..afac5c0164aff4
--- /dev/null
+++ b/llvm/test/Transforms/InstCombine/select-of-sym-selects.ll
@@ -0,0 +1,14 @@
+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
+; RUN: opt < %s -passes=instcombine -S | FileCheck %s
+
+define i32 @src(i32 %a, i32 %b, i1 %c1, i1 %c2) {
+; CHECK-LABEL: @src(
+; CHECK-NEXT:    [[TMP1:%.*]] = xor i1 [[C1:%.*]], [[C2:%.*]]
+; CHECK-NEXT:    [[RET:%.*]] = select i1 [[TMP1]], i32 [[B:%.*]], i32 [[A:%.*]]
+; CHECK-NEXT:    ret i32 [[RET]]
+;
+  %sel1 = select i1 %c1, i32 %a, i32 %b
+  %sel2 = select i1 %c1, i32 %b, i32 %a
+  %ret = select i1 %c2, i32 %sel1, i32 %sel2
+  ret i32 %ret
+}