Potential validator false error

[Kyrhe]

Description

When wide port is sectioned to multiple logical bus interfaces, validator gives error ('Range not within ref port width in mapped logical port in initiator bus interface ). Verilog generates to correct code, and component context menu does not give show errors prompt. No warning comes when saving the component, either.

Hence I believe this is false warning.

my port is 128 bits wide and I section it to 4 32-bit interfaces. Interface definition does not have width defined, and I map it to have logical width of 32 bits matching bit select of 32 bits of the ports (for each interface separate indexes).

kactus2 Version

3.13.1

Os

win10

ipxact standard

2022