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waveform.vcd
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waveform.vcd
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$version Generated by VerilatedVcd $end
$timescale 1ps $end
$scope module TOP $end
$var wire 1 V clk $end
$var wire 1 W reset $end
$scope module hmmm $end
$var wire 32 - alu_op [31:0] $end
$var wire 1 , alu_src_a $end
$var wire 2 ' alu_src_b [1:0] $end
$var wire 1 V clk $end
$var wire 16 # instruction [15:0] $end
$var wire 32 . instruction_type [31:0] $end
$var wire 2 & mem_adr_src [1:0] $end
$var wire 1 + mem_data_src $end
$var wire 1 ( mem_write $end
$var wire 2 % pc_src [1:0] $end
$var wire 1 W reset $end
$var wire 2 $ rf_src_x [1:0] $end
$var wire 1 ) rf_write_en_x $end
$var wire 1 * rf_write_en_y $end
$scope module controller $end
$var wire 32 - alu_op [31:0] $end
$var wire 1 , alu_src_a $end
$var wire 2 ' alu_src_b [1:0] $end
$var wire 16 # instruction [15:0] $end
$var wire 32 . instruction_type [31:0] $end
$var wire 2 & mem_adr_src [1:0] $end
$var wire 1 + mem_data_src $end
$var wire 1 ( mem_write $end
$var wire 2 % pc_src [1:0] $end
$var wire 2 $ rf_src_x [1:0] $end
$var wire 1 ) rf_write_en_x $end
$var wire 1 * rf_write_en_y $end
$upscope $end
$scope module datapath $end
$var wire 16 5 alu_input_a [15:0] $end
$var wire 16 6 alu_input_b [15:0] $end
$var wire 32 - alu_op [31:0] $end
$var wire 16 4 alu_result [15:0] $end
$var wire 1 , alu_src_a $end
$var wire 2 ' alu_src_b [1:0] $end
$var wire 1 V clk $end
$var wire 16 C imm_ext [15:0] $end
$var wire 8 2 immediate [7:0] $end
$var wire 16 # instruction [15:0] $end
$var wire 32 . instruction_type [31:0] $end
$var wire 2 & mem_adr_src [1:0] $end
$var wire 8 3 mem_data_address [7:0] $end
$var wire 1 + mem_data_src $end
$var wire 16 ; mem_read_data [15:0] $end
$var wire 1 ( mem_write $end
$var wire 16 < mem_write_data [15:0] $end
$var wire 8 / pc [7:0] $end
$var wire 8 X pc_next [7:0] $end
$var wire 8 0 pc_plus_2 [7:0] $end
$var wire 2 % pc_src [1:0] $end
$var wire 8 1 pc_target [7:0] $end
$var wire 1 W reset $end
$var wire 16 Y result [15:0] $end
$var wire 4 = rf_adr_x [3:0] $end
$var wire 4 > rf_adr_y [3:0] $end
$var wire 4 ? rf_adr_z [3:0] $end
$var wire 16 7 rf_read_data_x [15:0] $end
$var wire 16 8 rf_read_data_y [15:0] $end
$var wire 16 9 rf_read_data_z [15:0] $end
$var wire 2 $ rf_src_x [1:0] $end
$var wire 16 : rf_write_data_x [15:0] $end
$var wire 16 4 rf_write_data_y [15:0] $end
$var wire 1 ) rf_write_en_x $end
$var wire 1 * rf_write_en_y $end
$var wire 1 A sign $end
$var wire 1 B take_jump $end
$var wire 1 @ zero $end
$scope module alu $end
$var wire 16 5 alu_input_a [15:0] $end
$var wire 16 6 alu_input_b [15:0] $end
$var wire 32 - alu_op [31:0] $end
$var wire 16 4 alu_result [15:0] $end
$upscope $end
$scope module mem $end
$var wire 1 V clk $end
$var wire 16 # instruction [15:0] $end
$var wire 8 3 mem_data_address [7:0] $end
$var wire 16 ; mem_read_data [15:0] $end
$var wire 16 < mem_write_data [15:0] $end
$var wire 1 ( mem_write_en $end
$var wire 8 / pc [7:0] $end
$upscope $end
$scope module rf $end
$var wire 1 V clk $end
$var wire 16 D registers[0] [15:0] $end
$var wire 16 N registers[10] [15:0] $end
$var wire 16 O registers[11] [15:0] $end
$var wire 16 P registers[12] [15:0] $end
$var wire 16 Q registers[13] [15:0] $end
$var wire 16 R registers[14] [15:0] $end
$var wire 16 S registers[15] [15:0] $end
$var wire 16 E registers[1] [15:0] $end
$var wire 16 F registers[2] [15:0] $end
$var wire 16 G registers[3] [15:0] $end
$var wire 16 H registers[4] [15:0] $end
$var wire 16 I registers[5] [15:0] $end
$var wire 16 J registers[6] [15:0] $end
$var wire 16 K registers[7] [15:0] $end
$var wire 16 L registers[8] [15:0] $end
$var wire 16 M registers[9] [15:0] $end
$var wire 4 = rf_adr_x [3:0] $end
$var wire 4 > rf_adr_y [3:0] $end
$var wire 4 ? rf_adr_z [3:0] $end
$var wire 16 7 rf_read_data_x [15:0] $end
$var wire 16 8 rf_read_data_y [15:0] $end
$var wire 16 9 rf_read_data_z [15:0] $end
$var wire 16 : rf_write_data_x [15:0] $end
$var wire 16 4 rf_write_data_y [15:0] $end
$var wire 1 ) rf_write_en_x $end
$var wire 1 * rf_write_en_y $end
$upscope $end
$scope module unnamedblk1 $end
$var wire 32 T i [31:0] $end
$upscope $end
$scope module unnamedblk2 $end
$var wire 32 U i [31:0] $end
$upscope $end
$upscope $end
$upscope $end
$upscope $end
$enddefinitions $end
#0
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b0000000000000001 :
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b1111 =
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b0000000000000001 C
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#4
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#8
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b0001000100000001 #
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b00000000000000000000000000000100 .
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#11
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#12
b1101000100001010 #
b10 %
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b00000000000000000000000000010110 .
b00010000 /
b00010010 0
b00010100 1
b00001010 2
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b0000000000000001 7
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#14
b0001000111111111 #
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b00000000000000000000000000000100 .
b00010100 /
b00010110 0
b11111110 1
b11111111 2
b11111111 3
b0000000000000010 4
b0000000000000001 5
b0000000000000001 6
b0000000000000001 8
b0000000000000001 9
b1111111111111111 :
b0000000000000000 ;
b0000000000000010 <
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b1111 ?
b1111111111111111 C
1V
b00010110 X
#15
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#16
b1101000100001100 #
b10 %
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b00000000000000000000000000010110 .
b00010110 /
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b00011000 1
b00001100 2
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b0000000000000000 4
b0000000000000000 5
b0000000000000000 6
b1111111111111111 7
b0000000000000000 8
b0000000000000000 9
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b0000111000000010 ;
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b0000 >
b1100 ?
1A
b0000000000001100 C
b1111111111111111 E
1V
b00011000 X
#17
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#18
b0000111000000010 #
b00 %
b00000000000000000000000000000011 .
b00011000 /
b00011010 0
b00000100 1
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b0000000000000010 :
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b1110 =
b0010 ?
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#19
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#20
b0001000100000001 #
1)
b00000000000000000000000000000100 .
b00011010 /
b00011100 0
b00000010 1
b00000001 2
b00000001 3
b1111111111111111 4
b1111111111111111 6
b1111111111111111 7
b1111111111111111 9
b0000000000000001 :
b0001111100000001 ;
b1111111111111111 <
b0001 =
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#21
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#22
b1100000100000011 #
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b00000000000000000000000000010101 .
b00011100 /
b00011110 0
b00000110 1
b00000011 2
b00000011 3
b0000000000000000 4
b0000000000000000 6
b0000000000000001 7
b0000000000000000 9
b0000000000000011 :
b0000111100000010 ;
b0000000000000000 <
b0011 ?
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b0000000000000011 C
b0000000000000001 E
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#23
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#24
b0001000111111111 #
b00 %
1)
b00000000000000000000000000000100 .
b00011110 /
b00100000 0
b11111110 1
b11111111 2
b11111111 3
b0000000000000010 4
b0000000000000001 5
b0000000000000001 6
b0000000000000001 8
b0000000000000001 9
b1111111111111111 :
b0000000000000000 ;
b0000000000000010 <
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b1111 ?
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b1111111111111111 C
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b00100000 X
#25
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#26
b1100000100000011 #
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b00100000 /
b00100010 0
b00000110 1
b00000011 2
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b0000000000000000 4
b0000000000000000 5
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b0000000000000000 8
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#27
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#28
b0001000100000000 #
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b00000000000000000000000000000100 .
b00100010 /
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b00000000 1
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b0000000000000000 :
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b0000 ?
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#30
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b00000000000000000000000000010101 .
b00100100 /
b00100110 0
b00101000 1
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1@
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1V
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#31
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#32
b0000111000000010 #
b00 %
b00000000000000000000000000000011 .
b00101000 /
b00101010 0
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b0000000000000010 :
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b1110 =
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b0010 ?
b0000000000000010 C
1V
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#33
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#34
b0001000111111111 #
1)
b00000000000000000000000000000100 .
b00101010 /
b00101100 0
b11111110 1
b11111111 2
b11111111 3
b0000000000000010 4
b0000000000000001 5
b0000000000000001 6
b0000000000000001 8
b0000000000000001 9
b1111111111111111 :
b0000000000000000 ;
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#35
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#36
b1110000100000011 #
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#40
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#44
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b0000000000000001 7
b0000000000000001 8
b0000000000011100 :
b0000111000000010 ;
b0000000000000001 <
b0001 >
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0@
b0000000000011100 C
b0000000000000001 E
1V
b00111000 X
#45
0V
#46
b0000111000000010 #
b00 %
b00000000000000000000000000000011 .
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b0000000000000000 5
b0000000000000000 7
b0000000000000000 8
b0000000000000010 :
b1011000000000101 ;
b0000000000000000 <
b1110 =
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1@
b0000000000000010 C
1V
b00111010 X
#47
0V
#48
b0001000100000001 #
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b00000000000000000000000000000100 .
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b00000001 3
b0000000000000001 4
b0000000000000001 6
b0000000000000001 7
b0000000000000001 9
b0000000000000001 :
b0001111100000001 ;
b0000000000000001 <
b0001 =
b0001 ?
0@
b0000000000000001 C
1V
b00111100 X
#49
0V
#50
b1111000100000011 #
b10 %
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b00000000000000000000000000011000 .
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b00000011 2
b00000011 3
b0000000000000000 4
b0000000000000000 6
b0000000000000000 9
b0000000000000011 :
b0000111100000010 ;
b0000000000000000 <
b0011 ?
0B
b0000000000000011 C
1V
b00111110 X
#51
0V
#52
b0001000100000000 #
b00 %
1)
b00000000000000000000000000000100 .
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1B
b0000000000000000 C
1V
b01000000 X
#53
0V
#54
b1111000100000011 #
b10 %
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b00000000000000000000000000011000 .
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b0000000000000000 7
b0000000000000011 :
b0000111100000010 ;
b0011 ?
1@
0B
b0000000000000011 C
b0000000000000000 E
1V
b01000010 X
#55
0V
#56
b0001000111111111 #
b00 %
1)
b00000000000000000000000000000100 .
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b01000100 0
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b11111111 3
b0000000000000010 4
b0000000000000001 5
b0000000000000001 6
b0000000000000001 8
b0000000000000001 9
b1111111111111111 :
b0000000000000000 ;
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b1111 ?
1B
b1111111111111111 C
1V
b01000100 X
#57
0V
#58
b1111000100100100 #
b10 %
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b00000000000000000000000000011000 .
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b0000000000000000 6
b1111111111111111 7
b0000000000000000 8
b0000000000000000 9
b0000000000100100 :
b0000111000000010 ;
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b0010 >
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0@
1A
b0000000000100100 C
b1111111111111111 E
1V
b01001000 X
#59
0V
#60
b0000111000000010 #
b00 %
b00000000000000000000000000000011 .
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b01001010 0
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1@
0A
b0000000000000010 C
1V
b01001010 X
#61
0V
#62
b0001000111111111 #
1)
b00000000000000000000000000000100 .
b01001010 /
b01001100 0
b11111110 1
b11111111 2
b11111111 3
b0000000000000010 4
b0000000000000001 5
b0000000000000001 6
b1111111111111111 7
b0000000000000001 8
b0000000000000001 9
b1111111111111111 :
b0000000000000000 ;
b0000000000000010 <
b0001 =
b1111 >
b1111 ?
0@
1A
b1111111111111111 C
1V
b01001100 X
#63
0V
#64
b1011001000101000 #
b10 $
b10 %
b00000000000000000000000000011001 .
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b01001110 0
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b0000000000000000 6
b0000000000000000 7
b0000000000000000 8
b0000000000000000 9
b0000000001001110 :
b1011000000101011 ;
b0000000000000000 <
b0010 =
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1@
0A
b0000000000101000 C
1V
b01010000 X
#65
0V
#66
b1011000000101011 #
b00 $
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b00000000000000000000000000010100 .
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b01010110 1
b00101011 2
b00101011 3
b0000000001001110 4
b0000000001001110 5
b0000000001001110 8
b0000000000101011 :
b0000111000000010 ;
b0000000001001110 <
b0000 =
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b0000000000101011 C
b0000000001001110 F
1V
b01010110 X
#67
0V
#68
b0000111000000010 #
b00 %
b00000000000000000000000000000011 .
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b01011000 0
b00000100 1
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b00000010 3
b0000000000000000 5
b0000000001001110 6
b0000000000000000 8
b0000000001001110 9
b0000000000000010 :
b1011000000000101 ;
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b0000000000000010 C
1V
b01011000 X
#69
0V
#70
b0000000000000000 #
b00000000000000000000000000000000 .
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b0000 =
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1V
b01011010 X
#71