diff --git a/.settings/language.settings.xml b/.settings/language.settings.xml index 9d2f0d7..e2ee4c9 100644 --- a/.settings/language.settings.xml +++ b/.settings/language.settings.xml @@ -4,7 +4,7 @@ - + @@ -14,7 +14,7 @@ - + @@ -24,7 +24,7 @@ - + @@ -34,7 +34,7 @@ - + @@ -44,7 +44,7 @@ - + diff --git a/bsp/E21/multizone.cfg b/bsp/E21/multizone.cfg index 89327cf..af6b95d 100644 --- a/bsp/E21/multizone.cfg +++ b/bsp/E21/multizone.cfg @@ -11,7 +11,7 @@ Zone = 1 clic = 159 # UART base = 0x40408000; size = 32K; rwx = rx # FLASH base = 0x80003000; size = 4K; rwx = rw # RAM - base = 0x20000000; size = 0x100; rwx = rw # UART + base = 0x20000000; size = 0x100; rwx = rw # UART base = 0x02800000; size =0x1000; rwx = r # CLIC (ro) Zone = 2 diff --git a/bsp/E21/newlib/crt0.S b/bsp/E21/newlib/crt0.S index 7e77142..15e7d3d 100644 --- a/bsp/E21/newlib/crt0.S +++ b/bsp/E21/newlib/crt0.S @@ -7,6 +7,12 @@ _start: .cfi_startproc .cfi_undefined ra + + /* setup trap vector - CLIC vectored mode */ + la a0, _mtvec + csrw mtvec, a0 + csrs mtvec, 0b11 + .option push .option norelax la gp, __global_pointer$ @@ -64,3 +70,5 @@ _init: ret .type _fini, @function _fini: ret .size _fini, .-_fini + + .include "mtvec.s" diff --git a/bsp/E21/newlib/mtvec.s b/bsp/E21/newlib/mtvec.s new file mode 100644 index 0000000..805b55d --- /dev/null +++ b/bsp/E21/newlib/mtvec.s @@ -0,0 +1,62 @@ +/* Copyright(C) 2020 Hex Five Security, Inc. - All Rights Reserved */ + + .align 2 + +_mtvec: + +irq0: .word trp_isr +irq1: .word 1f +irq2: .word 1f +irq3: .word msi_isr +irq4: .word 1f +irq5: .word 1f +irq6: .word 1f +irq7: .word tmr_isr +irq8: .word 1f +irq9: .word 1f +irq10: .word 1f +irq11: .word 1f +irq12: .word 1f +irq13: .word 1f +irq14: .word 1f +irq15: .word 1f +irq16: .word 1f +irq17: .word 1f +irq18: .word 1f +irq19: .word dma_isr +irq20: .word btn0_isr +irq21: .word btn1_isr +irq22: .word btn2_isr +irq23: .word 1f +irq24: .word 1f +irq25: .word 1f +irq26: .word 1f +irq27: .word 1f +irq28: .word 1f +irq29: .word 1f +irq30: .word 1f +irq31: .word 1f + +.macro FILL from, to +.word 1f +.if \to-\from +FILL "(\from+1)",\to +.endif +.endm + +FILL 32, 99 +FILL 100, 158 + +irq159: .word uart_isr + + .weak trp_isr, msi_isr, tmr_isr, dma_isr, uart_isr, btn0_isr, btn1_isr, btn2_isr + +trp_isr: +msi_isr: +tmr_isr: +dma_isr: +uart_isr: +btn0_isr: +btn1_isr: +btn2_isr: +1: j . diff --git a/bsp/E21/newlib/newlib.mk b/bsp/E21/newlib/newlib.mk index 1188ad2..22b7867 100644 --- a/bsp/E21/newlib/newlib.mk +++ b/bsp/E21/newlib/newlib.mk @@ -6,6 +6,7 @@ all: $(TARGET) ASM_SRCS += $(NEWLIB_DIR)/crt0.S C_SRCS += $(NEWLIB_DIR)/newlib.c +INCLUDES += -I$(NEWLIB_DIR) INCLUDES += -I$(PLATFORM_DIR) LDFLAGS += -T $(PLATFORM_DIR)/memory.lds diff --git a/bsp/E21/platform.h b/bsp/E21/platform.h index 3f34499..7246b14 100644 --- a/bsp/E21/platform.h +++ b/bsp/E21/platform.h @@ -104,9 +104,9 @@ #define BTN2 6 #define BTN3 7 -#define BTN0_IRQ 16+4 -#define BTN1_IRQ 16+5 -#define BTN2_IRQ 16+6 +#define BTN0_IRQ 20 +#define BTN1_IRQ 21 +#define BTN2_IRQ 22 // ----------------------------------------------------------------------------- // LED0 (GPIO) @@ -140,7 +140,7 @@ #define _REG64(base, offset) (*(volatile uint64_t *)((base) + (offset))) #define _REG32(base, offset) (*(volatile uint32_t *)((base) + (offset))) -#define CLIC_REG(offset) _REG64(CLIC_BASE, offset) +#define CLIC_REG(offset) _REG32(CLIC_BASE, offset) #define GPIO_REG(offset) _REG32(GPIO_BASE, offset) #define PWM_REG(offset) _REG32(PWM_BASE, offset) #define UART_REG(offset) _REG32(UART_BASE, offset) diff --git a/bsp/E31/newlib/crt0.S b/bsp/E31/newlib/crt0.S index 97b61f2..43e5fa2 100644 --- a/bsp/E31/newlib/crt0.S +++ b/bsp/E31/newlib/crt0.S @@ -7,6 +7,12 @@ _start: .cfi_startproc .cfi_undefined ra + + /* setup trap vector */ + la a0, _mtvec + csrw mtvec, a0 + csrs mtvec, 1 + .option push .option norelax la gp, __global_pointer$ @@ -36,7 +42,6 @@ _start: bltu a0, a1, 1b 2: - /* Call global constructors */ la a0, __libc_fini_array call atexit @@ -65,3 +70,5 @@ _init: ret .type _fini, @function _fini: ret .size _fini, .-_fini + + .include "mtvec.s" diff --git a/bsp/E31/newlib/mtvec.s b/bsp/E31/newlib/mtvec.s new file mode 100644 index 0000000..95352de --- /dev/null +++ b/bsp/E31/newlib/mtvec.s @@ -0,0 +1,55 @@ +/* Copyright(C) 2020 Hex Five Security, Inc. - All Rights Reserved */ + + .align 2 + +_mtvec: + + .option push + .option norvc + +irq0: j trp_isr +irq1: j . +irq2: j . +irq3: j msi_isr +irq4: j . +irq5: j . +irq6: j . +irq7: j tmr_isr +irq8: j . +irq9: j . +irq10: j . +irq11: j uart_isr +irq12: j . +irq13: j . +irq14: j . +irq15: j . +irq16: j . +irq17: j . +irq18: j . +irq19: j dma_isr +irq20: j btn0_isr +irq21: j btn1_isr +irq22: j btn2_isr +irq23: j . +irq24: j . +irq25: j . +irq26: j . +irq27: j . +irq28: j . +irq29: j . +irq30: j . +irq31: j . + + .option pop + + .weak trp_isr, msi_isr, tmr_isr, dma_isr, uart_isr, btn0_isr, btn1_isr, btn2_isr + +trp_isr: +msi_isr: +tmr_isr: +dma_isr: +uart_isr: +btn0_isr: +btn1_isr: +btn2_isr: + j . diff --git a/bsp/E31/newlib/newlib.mk b/bsp/E31/newlib/newlib.mk index 1188ad2..22b7867 100644 --- a/bsp/E31/newlib/newlib.mk +++ b/bsp/E31/newlib/newlib.mk @@ -6,6 +6,7 @@ all: $(TARGET) ASM_SRCS += $(NEWLIB_DIR)/crt0.S C_SRCS += $(NEWLIB_DIR)/newlib.c +INCLUDES += -I$(NEWLIB_DIR) INCLUDES += -I$(PLATFORM_DIR) LDFLAGS += -T $(PLATFORM_DIR)/memory.lds diff --git a/bsp/FE310/mtvec.s b/bsp/FE310/mtvec.s new file mode 100644 index 0000000..84d1da2 --- /dev/null +++ b/bsp/FE310/mtvec.s @@ -0,0 +1,55 @@ +/* Copyright(C) 2020 Hex Five Security, Inc. - All Rights Reserved */ + + .align 2 + +_mtvec: + + .option push + .option norvc + +irq0: j trp_isr +irq1: j . +irq2: j . +irq3: j msi_isr +irq4: j . +irq5: j . +irq6: j . +irq7: j tmr_isr +irq8: j . +irq9: j . +irq10: j . +irq11: j uart_isr +irq12: j . +irq13: j . +irq14: j . +irq15: j . +irq16: j . +irq17: j . +irq18: j . +irq19: j dma_isr +irq20: j . +irq21: j . +irq22: j . +irq23: j . +irq24: j . +irq25: j . +irq26: j . +irq27: j . +irq28: j . +irq29: j . +irq30: j . +irq31: j . + + .option pop + + .weak trp_isr, msi_isr, tmr_isr, dma_isr, uart_isr, btn0_isr, btn1_isr, btn2_isr + +trp_isr: +msi_isr: +tmr_isr: +dma_isr: +uart_isr: +btn0_isr: +btn1_isr: +btn2_isr: + j . diff --git a/bsp/FE310/newlib/crt0.S b/bsp/FE310/newlib/crt0.S index 97b61f2..10d2d8d 100644 --- a/bsp/FE310/newlib/crt0.S +++ b/bsp/FE310/newlib/crt0.S @@ -7,6 +7,12 @@ _start: .cfi_startproc .cfi_undefined ra + + /* setup trap vector */ + la a0, _mtvec + csrw mtvec, a0 + csrs mtvec, 1 + .option push .option norelax la gp, __global_pointer$ @@ -36,7 +42,6 @@ _start: bltu a0, a1, 1b 2: - /* Call global constructors */ la a0, __libc_fini_array call atexit @@ -65,3 +70,5 @@ _init: ret .type _fini, @function _fini: ret .size _fini, .-_fini + + .include "mtvec.s" diff --git a/bsp/FE310/newlib/newlib.mk b/bsp/FE310/newlib/newlib.mk index 1188ad2..22b7867 100644 --- a/bsp/FE310/newlib/newlib.mk +++ b/bsp/FE310/newlib/newlib.mk @@ -6,6 +6,7 @@ all: $(TARGET) ASM_SRCS += $(NEWLIB_DIR)/crt0.S C_SRCS += $(NEWLIB_DIR)/newlib.c +INCLUDES += -I$(NEWLIB_DIR) INCLUDES += -I$(PLATFORM_DIR) LDFLAGS += -T $(PLATFORM_DIR)/memory.lds diff --git a/bsp/S51/newlib/crt0.S b/bsp/S51/newlib/crt0.S index 97b61f2..9145e3d 100644 --- a/bsp/S51/newlib/crt0.S +++ b/bsp/S51/newlib/crt0.S @@ -7,6 +7,12 @@ _start: .cfi_startproc .cfi_undefined ra + + /* setup trap vector */ + la a0, _mtvec + csrw mtvec, a0 + csrs mtvec, 1 + .option push .option norelax la gp, __global_pointer$ @@ -36,7 +42,6 @@ _start: bltu a0, a1, 1b 2: - /* Call global constructors */ la a0, __libc_fini_array call atexit @@ -65,3 +70,5 @@ _init: ret .type _fini, @function _fini: ret .size _fini, .-_fini + + .include "mtvec.s" diff --git a/bsp/S51/newlib/mtvec.s b/bsp/S51/newlib/mtvec.s new file mode 100644 index 0000000..95352de --- /dev/null +++ b/bsp/S51/newlib/mtvec.s @@ -0,0 +1,55 @@ +/* Copyright(C) 2020 Hex Five Security, Inc. - All Rights Reserved */ + + .align 2 + +_mtvec: + + .option push + .option norvc + +irq0: j trp_isr +irq1: j . +irq2: j . +irq3: j msi_isr +irq4: j . +irq5: j . +irq6: j . +irq7: j tmr_isr +irq8: j . +irq9: j . +irq10: j . +irq11: j uart_isr +irq12: j . +irq13: j . +irq14: j . +irq15: j . +irq16: j . +irq17: j . +irq18: j . +irq19: j dma_isr +irq20: j btn0_isr +irq21: j btn1_isr +irq22: j btn2_isr +irq23: j . +irq24: j . +irq25: j . +irq26: j . +irq27: j . +irq28: j . +irq29: j . +irq30: j . +irq31: j . + + .option pop + + .weak trp_isr, msi_isr, tmr_isr, dma_isr, uart_isr, btn0_isr, btn1_isr, btn2_isr + +trp_isr: +msi_isr: +tmr_isr: +dma_isr: +uart_isr: +btn0_isr: +btn1_isr: +btn2_isr: + j . diff --git a/bsp/S51/newlib/newlib.mk b/bsp/S51/newlib/newlib.mk index 6689ffd..9abf1ca 100644 --- a/bsp/S51/newlib/newlib.mk +++ b/bsp/S51/newlib/newlib.mk @@ -6,6 +6,7 @@ all: $(TARGET) ASM_SRCS += $(NEWLIB_DIR)/crt0.S C_SRCS += $(NEWLIB_DIR)/newlib.c +INCLUDES += -I$(NEWLIB_DIR) INCLUDES += -I$(PLATFORM_DIR) LDFLAGS += -T $(PLATFORM_DIR)/memory.lds diff --git a/bsp/X300/newlib/crt0.S b/bsp/X300/newlib/crt0.S index 97b61f2..ae3b2c4 100644 --- a/bsp/X300/newlib/crt0.S +++ b/bsp/X300/newlib/crt0.S @@ -7,10 +7,16 @@ _start: .cfi_startproc .cfi_undefined ra -.option push -.option norelax + + /* setup trap vector */ + la a0, _mtvec + csrw mtvec, a0 + csrs mtvec, 1 + + .option push + .option norelax la gp, __global_pointer$ -.option pop + .option pop la sp, _sp /* Load data section */ @@ -36,7 +42,6 @@ _start: bltu a0, a1, 1b 2: - /* Call global constructors */ la a0, __libc_fini_array call atexit @@ -65,3 +70,5 @@ _init: ret .type _fini, @function _fini: ret .size _fini, .-_fini + + .include "mtvec.s" diff --git a/bsp/X300/newlib/mtvec.s b/bsp/X300/newlib/mtvec.s new file mode 100644 index 0000000..3d83a53 --- /dev/null +++ b/bsp/X300/newlib/mtvec.s @@ -0,0 +1,55 @@ +/* Copyright(C) 2020 Hex Five Security, Inc. - All Rights Reserved */ + + .align 2 + +_mtvec: + + .option push + .option norvc + +irq0: j trp_isr +irq1: j . +irq2: j . +irq3: j msi_isr +irq4: j . +irq5: j . +irq6: j . +irq7: j tmr_isr +irq8: j . +irq9: j . +irq10: j . +irq11: j uart_isr +irq12: j . +irq13: j . +irq14: j . +irq15: j . +irq16: j btn0_isr +irq17: j btn1_isr +irq18: j btn2_isr +irq19: j dma_isr +irq20: j . +irq21: j . +irq22: j . +irq23: j . +irq24: j . +irq25: j . +irq26: j . +irq27: j . +irq28: j . +irq29: j . +irq30: j . +irq31: j . + + .option pop + + .weak trp_isr, msi_isr, tmr_isr, dma_isr, uart_isr, btn0_isr, btn1_isr, btn2_isr + +trp_isr: +msi_isr: +tmr_isr: +dma_isr: +uart_isr: +btn0_isr: +btn1_isr: +btn2_isr: + j . diff --git a/bsp/X300/newlib/newlib.mk b/bsp/X300/newlib/newlib.mk index eece7c1..637d3ad 100644 --- a/bsp/X300/newlib/newlib.mk +++ b/bsp/X300/newlib/newlib.mk @@ -6,6 +6,7 @@ all: $(TARGET) ASM_SRCS += $(NEWLIB_DIR)/crt0.S C_SRCS += $(NEWLIB_DIR)/newlib.c +INCLUDES += -I$(NEWLIB_DIR) INCLUDES += -I$(PLATFORM_DIR) LDFLAGS += -T $(PLATFORM_DIR)/memory.lds diff --git a/multizone-sdk-FE310.launch b/multizone-sdk-FE310.launch index fcd2713..39c1cee 100644 --- a/multizone-sdk-FE310.launch +++ b/multizone-sdk-FE310.launch @@ -34,7 +34,7 @@ - + @@ -68,12 +68,15 @@ + + + diff --git a/multizone-sdk.launch b/multizone-sdk.launch index d6981f9..5a9cdf1 100644 --- a/multizone-sdk.launch +++ b/multizone-sdk.launch @@ -33,8 +33,8 @@ - - + + @@ -50,6 +50,7 @@ + @@ -57,10 +58,10 @@ - + - + diff --git a/multizone.jar b/multizone.jar index 87623f6..e973989 100644 Binary files a/multizone.jar and b/multizone.jar differ diff --git a/zone1/main.c b/zone1/main.c index c1019b0..5348d0c 100644 --- a/zone1/main.c +++ b/zone1/main.c @@ -12,36 +12,27 @@ #define MIN(a,b) (((a)<(b))?(a):(b)) -typedef enum {zone1=1, zone2, zone3, zone4} Zone; - #define BUFFER_SIZE 32 static volatile struct{ - char data[BUFFER_SIZE]; - int r; // read - int w; // write + char data[BUFFER_SIZE]; + int r; // read + int w; // write } buffer; int buffer_empty(void){ - return (buffer.w==0); + return (buffer.w==0); } +typedef enum {zone1=1, zone2, zone3, zone4} Zone; + static char inputline[BUFFER_SIZE+1]=""; static volatile char inbox[4][16] = { {'\0'}, {'\0'}, {'\0'}, {'\0'} }; -int inbox_empty(void){ - return (inbox[0][0]=='\0' && inbox[1][0]=='\0' && inbox[2][0]=='\0' && inbox[3][0]=='\0'); -} -// ------------------------------------------------------------------------ -#ifdef E21 - static void (*trap_vect[173])(void) = {}; -#else - static void (*trap_vect[__riscv_xlen])(void) = {}; -#endif __attribute__((interrupt())) void trp_isr(void) { // nmi traps (0) - const unsigned long mcause = MZONE_CSRR(CSR_MCAUSE); - const unsigned long mepc = MZONE_CSRR(CSR_MEPC); - const unsigned long mtval = MZONE_CSRR(CSR_MTVAL); + const unsigned long mcause = MZONE_CSRR(CSR_MCAUSE); + const unsigned long mepc = MZONE_CSRR(CSR_MEPC); + const unsigned long mtval = MZONE_CSRR(CSR_MTVAL); switch(mcause){ @@ -91,6 +82,7 @@ __attribute__((interrupt())) void trp_isr(void) { // nmi traps (0) asm ("j _start"); } + __attribute__((interrupt())) void msi_isr(void) { // msip/inbox (3) for (Zone zone = zone1; zone <= zone4; zone++) { @@ -100,19 +92,21 @@ __attribute__((interrupt())) void msi_isr(void) { // msip/inbox (3) } } + __attribute__((interrupt())) void tmr_isr(void) { // timer (7) const unsigned long mcause = MZONE_CSRR(CSR_MCAUSE); const unsigned long mepc = MZONE_CSRR(CSR_MEPC); const unsigned long mtval = MZONE_CSRR(CSR_MTVAL); - write(1, "\e7\e[2K", 6); // save curs pos & clear entire line + write(1, "\e7\e[2K", 6); // save curs pos & clear entire line printf("\rTimer interrupt : 0x%08x 0x%08x 0x%08x \n", mcause, mepc, mtval); write(1, "\nZ1 > %s", 6); write(1, inputline, strlen(inputline)); - write(1, "\e8\e[2B", 6); // restore curs pos & curs down +2 lines - CSRC(mie, 1<<7); // disable one-shot timer + write(1, "\e8\e[2B", 6); // restore curs pos & curs down +2 lines + CSRC(mie, 1<<7); // disable one-shot timer } + __attribute__((interrupt())) void uart_isr(void) { // uart #ifdef PLIC_BASE @@ -130,6 +124,7 @@ __attribute__((interrupt())) void uart_isr(void) { // uart #endif } + __attribute__((interrupt())) void dma_isr(void) { // dma #ifdef DMA_BASE @@ -146,9 +141,119 @@ __attribute__((interrupt())) void dma_isr(void) { // dma } -// ------------------------------------------------------------------------ +int inbox_empty(void){ + return (inbox[0][0]=='\0' && inbox[1][0]=='\0' && inbox[2][0]=='\0' && inbox[3][0]=='\0'); +} + +int readline() { + + static size_t p=0; + static int esc=0; + static char history[8][sizeof(inputline)]={"","","","","","","",""}; static int h=-1; + + int eol = 0; // end of line + + while ( !eol && buffer.w > buffer.r ) { + + CSRC(mstatus, 1<<3); // CSRC(mie, 1<<11); // PLIC_REG(PLIC_EN) &= ~(1 << PLIC_SRC_UART); + const char c = buffer.data[buffer.r++]; + if (buffer.r >= buffer.w) {buffer.r = 0; buffer.w = 0;} + CSRS(mstatus, 1<<3); // CSRS(mie, 1<<11); //PLIC_REG(PLIC_EN) |= 1 << PLIC_SRC_UART; + + if (c=='\e'){ + esc=1; + + } else if (esc==1 && c=='['){ + esc=2; + + } else if (esc==2 && c=='3'){ + esc=3; + + } else if (esc==3 && c=='~'){ // del key + for (size_t i=p; i0){ + p--; + write(1, "\e[D", 3); + } + + } else if (esc==2 && c=='A'){ // up arrow (history) + esc=0; + if (h<8-1 && strlen(history[h+1])>0){ + h++; + strcpy(inputline, history[h]); + write(1, "\e[2K", 4); // 2K clear entire line - cur pos dosn't change + write(1, "\rZ1 > ", 6); + write(1, inputline, strlen(inputline)); + p=strlen(inputline); + + } + + } else if (esc==2 && c=='B'){ // down arrow (history) + esc=0; + if (h>0 && strlen(history[h-1])>0){ + h--; + strcpy(inputline, history[h]); + write(1, "\e[2K", 4); // 2K clear entire line - cur pos dosn't change + write(1, "\rZ1 > ", 6); + write(1, inputline, strlen(inputline)); + p=strlen(inputline); + } + + } else if ((c=='\b' || c=='\x7f') && p>0 && esc==0){ // backspace + p--; + for (size_t i=p; i=' ' && c<='~' && p < sizeof(inputline)-1 && esc==0){ + for (size_t i = sizeof(inputline)-1-1; i > p; i--) inputline[i]=inputline[i-1]; // make room for 1 ch + inputline[p]=c; + write(1, "\e7", 2); // save curs pos + write(1, "\e[K", 3); // clear line from curs pos + write(1, &inputline[p], strlen(inputline)-p); p++; + write(1, "\e8", 2); // restore curs pos + write(1, "\e[C", 3); // move curs right 1 pos + + } else if (c=='\r') { + p=0; esc=0; eol = 1; + // trim + while (inputline[strlen(inputline)-1]==' ') inputline[strlen(inputline)-1]='\0'; + while (inputline[0]==' ') for (size_t i = 0; i < strlen(inputline); i++) inputline[i]=inputline[i+1]; + // save line to history + if (strlen(inputline)>0 && strcmp(inputline, history[0])!=0){ + for (int i = 8-1; i > 0; i--) strcpy(history[i], history[i-1]); + strcpy(history[0], inputline); + } h = -1; + write(1, "\n", 1); + + } else + esc=0; + + } + + return eol; + +} + void print_sys_info(void) { -// ------------------------------------------------------------------------ // misa unsigned long misa; asm volatile ("csrr %0, misa" : "=r"(misa) : ); @@ -218,7 +323,6 @@ void print_sys_info(void) { } -// ------------------------------------------------------------------------ int cmpfunc(const void* a, const void* b){ const int ai = *(const int* )a; @@ -226,7 +330,6 @@ int cmpfunc(const void* a, const void* b){ return ai < bi ? -1 : ai > bi ? 1 : 0; } -// ------------------------------------------------------------------------ void print_stats(void){ #define MHZ (CPU_FREQ/1000000) @@ -292,9 +395,7 @@ void print_stats(void){ } -// ------------------------------------------------------------------------ void print_pmp(void){ -// ------------------------------------------------------------------------ #define TOR 0b00001000 #define NA4 0b00010000 @@ -364,7 +465,6 @@ void print_pmp(void){ } -// ------------------------------------------------------------------------ void msg_handler() { CSRC(mie, 1 << 3); @@ -396,7 +496,6 @@ void msg_handler() { } -// ------------------------------------------------------------------------ void cmd_handler(){ char * tk[9]; tk[0] = strtok(inputline, " "); for (int i=1; i<9; i++) tk[i] = strtok(NULL, " "); @@ -530,122 +629,22 @@ void cmd_handler(){ } -// ------------------------------------------------------------------------ -int readline() { -// ------------------------------------------------------------------------ - - static size_t p=0; - static int esc=0; - static char history[8][sizeof(inputline)]={"","","","","","","",""}; static int h=-1; - - int eol = 0; // end of line - - while ( !eol && buffer.w > buffer.r ) { - - CSRC(mstatus, 1<<3); // CSRC(mie, 1<<11); // PLIC_REG(PLIC_EN) &= ~(1 << PLIC_SRC_UART); - const char c = buffer.data[buffer.r++]; - if (buffer.r >= buffer.w) {buffer.r = 0; buffer.w = 0;} - CSRS(mstatus, 1<<3); // CSRS(mie, 1<<11); //PLIC_REG(PLIC_EN) |= 1 << PLIC_SRC_UART; - - if (c=='\e'){ - esc=1; - - } else if (esc==1 && c=='['){ - esc=2; - - } else if (esc==2 && c=='3'){ - esc=3; - - } else if (esc==3 && c=='~'){ // del key - for (size_t i=p; i0){ - p--; - write(1, "\e[D", 3); - } - - } else if (esc==2 && c=='A'){ // up arrow (history) - esc=0; - if (h<8-1 && strlen(history[h+1])>0){ - h++; - strcpy(inputline, history[h]); - write(1, "\e[2K", 4); // 2K clear entire line - cur pos dosn't change - write(1, "\rZ1 > ", 6); - write(1, inputline, strlen(inputline)); - p=strlen(inputline); - - } - - } else if (esc==2 && c=='B'){ // down arrow (history) - esc=0; - if (h>0 && strlen(history[h-1])>0){ - h--; - strcpy(inputline, history[h]); - write(1, "\e[2K", 4); // 2K clear entire line - cur pos dosn't change - write(1, "\rZ1 > ", 6); - write(1, inputline, strlen(inputline)); - p=strlen(inputline); - } - - } else if ((c=='\b' || c=='\x7f') && p>0 && esc==0){ // backspace - p--; - for (size_t i=p; i=' ' && c<='~' && p < sizeof(inputline)-1 && esc==0){ - for (size_t i = sizeof(inputline)-1-1; i > p; i--) inputline[i]=inputline[i-1]; // make room for 1 ch - inputline[p]=c; - write(1, "\e7", 2); // save curs pos - write(1, "\e[K", 3); // clear line from curs pos - write(1, &inputline[p], strlen(inputline)-p); p++; - write(1, "\e8", 2); // restore curs pos - write(1, "\e[C", 3); // move curs right 1 pos - - } else if (c=='\r') { - p=0; esc=0; eol = 1; - // trim - while (inputline[strlen(inputline)-1]==' ') inputline[strlen(inputline)-1]='\0'; - while (inputline[0]==' ') for (size_t i = 0; i < strlen(inputline); i++) inputline[i]=inputline[i+1]; - // save line to history - if (strlen(inputline)>0 && strcmp(inputline, history[0])!=0){ - for (int i = 8-1; i > 0; i--) strcpy(history[i], history[i-1]); - strcpy(history[0], inputline); - } h = -1; - write(1, "\n", 1); - - } else - esc=0; - - } - - return eol; - -} - -// ------------------------------------------------------------------------ int main (void) { - //while(1) MZONE_WFI(); - //while(1) MZONE_YIELD(); - //while(1); + // enable interrupts + CSRS(mie, 1<<3); +#ifdef PLIC_BASE + CSRS(mie, 1L< ", 7); while(1){ @@ -711,5 +685,3 @@ int main (void) { } } - - diff --git a/zone2/main.c b/zone2/main.c index 84f2e8c..d140192 100644 --- a/zone2/main.c +++ b/zone2/main.c @@ -15,13 +15,8 @@ static volatile char inbox[16] = ""; -// ------------------------------------------------------------------------ -#ifdef E21 - static void (*trap_vect[173])(void) = {}; -#else - static void (*trap_vect[__riscv_xlen])(void) = {}; -#endif -__attribute__((interrupt())) void trp_handler(void) { // trap handler (0) +__attribute__((interrupt())) void trp_isr + (void) { // trap handler (0) const unsigned long mcause = MZONE_CSRR(CSR_MCAUSE); @@ -39,12 +34,14 @@ __attribute__((interrupt())) void trp_handler(void) { // trap handler (0) for(;;); } -__attribute__((interrupt())) void msi_handler(void) { // machine software interrupt (3) + +__attribute__((interrupt())) void msi_isr(void) { // machine software interrupt (3) MZONE_RECV(1, inbox); } -__attribute__((interrupt())) void tmr_handler(void) { // machine timer interrupt (7) + +__attribute__((interrupt())) void tmr_isr(void) { // machine timer interrupt (7) static uint16_t r=0x3F; static uint16_t g=0; @@ -68,7 +65,8 @@ __attribute__((interrupt())) void tmr_handler(void) { // machine timer interrup MZONE_ADTIMECMP((uint64_t)5*RTC_FREQ/1000); } -__attribute__((interrupt())) void btn0_handler(void) { + +__attribute__((interrupt())) void btn0_isr(void) { static uint64_t debounce = 0; const uint64_t T = MZONE_RDTIME(); @@ -81,7 +79,8 @@ __attribute__((interrupt())) void btn0_handler(void) { BITSET(GPIO_BASE+GPIO_HIGH_IP, 1< #include "multizone.h" -__attribute__(( interrupt())) void trap_handler(void){ +__attribute__(( interrupt())) void trap_isr(void){ for( ;; ); @@ -11,13 +11,9 @@ __attribute__(( interrupt())) void trap_handler(void){ int main (void){ - //while(1) MZONE_WFI(); - //while(1) MZONE_YIELD(); - //while(1); - - CSRW(mtvec, trap_handler); // register trap handler - CSRS(mie, 1<<3); // wake up on msip/inbox - CSRC(mstatus, 1<<3); // disable global interrupts - no irq taken + CSRW(mtvec, trap_isr); // register trap handler + CSRS(mie, 1<<3); // wake up on msip/inbox + CSRC(mstatus, 1<<3); // disable global interrupts - no irq taken while (1) {