Skip to content
New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

[herd] Write a label to LR (X30) when it is possible #776

Merged
merged 2 commits into from
Apr 9, 2024

Conversation

relokin
Copy link
Member

@relokin relokin commented Jan 31, 2024

In sequences where the label is know, rather than setting the LR with an internal address we use the label. This means that in certain cases (-variant=ifetch) we can use it to address the instruction in that label.

}
P0 | P0.F ;
L0: | STR X2,[X3] ;
LDR W0,[X1] | DSB ISHST ;
Copy link
Member

@maranget maranget Apr 2, 2024

Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

Isn't a final ERET instruction missing here?

Suggested change
LDR W0,[X1] | DSB ISHST ;
LDR W0,[X1] | DSB ISHST ;
| ERET ;

And is the DSB ISHR instruction necessary?

Copy link
Member Author

Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

Yes indeed the ERET is missing, my bad. I'll fix it now.

Yes, without ETS2, I think we need a DSB to make sure that the LDR won't fault again. Or am I missing something?

@maranget
Copy link
Member

maranget commented Apr 2, 2024

Hi @relokin, this PR looks good to me. I have only one question about the vmsa test.

Copy link
Member Author

@relokin relokin left a comment

Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

Thanks for the review @maranget !

}
P0 | P0.F ;
L0: | STR X2,[X3] ;
LDR W0,[X1] | DSB ISHST ;
Copy link
Member Author

Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

Yes indeed the ERET is missing, my bad. I'll fix it now.

Yes, without ETS2, I think we need a DSB to make sure that the LDR won't fault again. Or am I missing something?

In sequences where the label is know, rather than setting the LR with
an internal address we use the label. This means that in certain cases
(-variant=ifetch) we can use it to address the instruction in that
label.

Signed-off-by: Nikos Nikoleris <[email protected]>
This change enables herd to handle tests like:

AArch64 LDRv0+I2V-dsb.ishst
{
 [PTE(x)]=(oa:PA(x),valid:0);
 x=1;

 0:X1=x;
 0:X3=PTE(x);
 0:X2=(oa:PA(x),valid:1);
}
 P0            | P0.F           ;
L0:            | STR X2,[X3]    ;
 LDR W0,[X1]   | DSB ISHST      ;
               | ERET           ;
locations[0:ELR_EL1;]
forall(0:X0=1)

Note that in the above test ELR_EL1 is automatically set to
P0:L0. However this wouldn't be the case if the faulting instruction
didn't have a label. In which case herd7 would warn that the target of
ERET is unknown.

Signed-off-by: Nikos Nikoleris <[email protected]>
@relokin
Copy link
Member Author

relokin commented Apr 8, 2024

@maranget are you happy with this PR?

@maranget
Copy link
Member

maranget commented Apr 9, 2024

I am happy, please feel free to merge.

@relokin
Copy link
Member Author

relokin commented Apr 9, 2024

I am happy, please feel free to merge.

Thanks @maranget !

@relokin relokin merged commit 5b5abd6 into herd:master Apr 9, 2024
3 checks passed
Sign up for free to join this conversation on GitHub. Already have an account? Sign in to comment
Labels
None yet
Projects
None yet
Development

Successfully merging this pull request may close these issues.

2 participants