From bdda66ae7faafdb1f448122752af889f06370186 Mon Sep 17 00:00:00 2001
From: crvdgc <ubikium@gmail.com>
Date: Thu, 19 Sep 2024 09:54:35 +0100
Subject: [PATCH] [herd,SVE] Fix store predicated base iico_data dependency

---
 herd/AArch64Sem.ml | 62 ++++++++++++++++++++++++++++------------------
 1 file changed, 38 insertions(+), 24 deletions(-)

diff --git a/herd/AArch64Sem.ml b/herd/AArch64Sem.ml
index 494b87b41..391380042 100644
--- a/herd/AArch64Sem.ml
+++ b/herd/AArch64Sem.ml
@@ -2906,26 +2906,40 @@ module Make
         let psize = predicate_psize r in
         let esize = scalable_esize r in
         let nregs = List.length rlist in
-        let>= pred = read_reg_predicate false p ii
-        and* base = ma
-        in
-        let ops i r =
-          let op idx =
-            let store =
-              let>= v = read_reg_scalable true r ii in
-              let offset = (idx * nregs + i) * MachSize.nbytes sz in
-              let>= addr = M.op1 (Op.AddK offset) base
-              and* v = scalable_getlane v idx esize >>= demote
+        let>= results =
+          let<>= base = ma
+          and* pred = read_reg_predicate false p ii
+          in
+          let ops i r =
+            let op idx =
+              let store =
+                let>= v = read_reg_scalable true r ii in
+                let offset = (idx * nregs + i) * MachSize.nbytes sz in
+                let>= addr = M.op1 (Op.AddK offset) base
+                and* v = scalable_getlane v idx esize >>= demote
+                in
+                M.unitT (Some (addr, v))
+                (* write_mem sz aexp Access.VIR addr v ii *)
               in
-              write_mem sz aexp Access.VIR addr v ii
+              is_active_element p pred psize idx ii store (M.unitT None)
             in
-            is_active_element p pred psize idx ii store (M.unitT ())
+            let ops = List.map op (Misc.interval 0 nelem) in
+            List.fold_right ( >>:: ) ops (M.unitT [])
+            (* List.fold_right M.seq_mem_list ops (M.unitT [()]) *)
           in
-          let ops = List.map op (Misc.interval 0 nelem) in
-          List.fold_right M.seq_mem_list ops (M.unitT [()])
+          let ops = List.mapi ops rlist in
+          List.fold_right ( >>:: ) ops (M.unitT [])
         in
-        let ops = List.mapi ops rlist in
-        List.fold_right M.seq_mem_list ops (M.unitT [[()]])
+        let f avs macc =
+          let avs = List.filter_map Fun.id avs in
+          let g (addr, v) macc =
+            M.seq_mem_list
+              (write_mem sz aexp Access.VIR addr v ii)
+              macc
+          in
+          List.fold_right g avs macc
+        in
+        List.fold_right f results (M.unitT [()])
 
       let load_gather_predicated_elem_or_zero sz p ma mo rs e k ii =
         let r = List.hd rs in
@@ -3634,19 +3648,19 @@ module Make
         | I_ST3SP(var,rs,p,rA,MemExt.Imm (k,Idx))
         | I_ST4SP(var,rs,p,rA,MemExt.Imm (k,Idx)) ->
           check_sve inst;
-          !!!!(let sz = tr_simd_variant var in
-               let ma = get_ea_idx rA k ii in
-                store_predicated_elem_or_merge_m sz p ma rs ii >>|
-                M.unitT ())
+          !!!(let sz = tr_simd_variant var in
+              let ma = get_ea_idx rA k ii in
+               store_predicated_elem_or_merge_m sz p ma rs ii >>|
+               M.unitT ())
         | I_ST1SP(var,rs,p,rA,MemExt.Reg (V64,rM,MemExt.LSL,s))
         | I_ST2SP(var,rs,p,rA,MemExt.Reg (V64,rM,MemExt.LSL,s))
         | I_ST3SP(var,rs,p,rA,MemExt.Reg (V64,rM,MemExt.LSL,s))
         | I_ST4SP(var,rs,p,rA,MemExt.Reg (V64,rM,MemExt.LSL,s)) ->
           check_sve inst;
-          !!!!(let sz = tr_simd_variant var in
-               let ma = get_ea_reg rA V64 rM MemExt.LSL s ii in
-                store_predicated_elem_or_merge_m sz p ma rs ii >>|
-                M.unitT ())
+          !!!(let sz = tr_simd_variant var in
+              let ma = get_ea_reg rA V64 rM MemExt.LSL s ii in
+               store_predicated_elem_or_merge_m sz p ma rs ii >>|
+               M.unitT ())
         | I_ST1SP (var,rs,p,rA,MemExt.ZReg (rM,sext,s)) ->
           check_sve inst;
           !!!(let sz = tr_simd_variant var in