From 39967df72daad186679a20262e60a0d91d46f4e8 Mon Sep 17 00:00:00 2001 From: Vladimir Murzin Date: Tue, 2 Jan 2024 15:45:05 +0000 Subject: [PATCH] [gen]: Generate basic SVE loads and stores SVE pseudo-relaxation are grouped under `Sv` suffix: - `SvV` command a SVE gather load and scatter store - `Sv{1,2,3,4}` command a SVE interleave loads and stores' Generated tests set predicates in such way that single access won't exceed 128 bit (which is minimal allowed vector length) which allow them tolerate difference in implemented vector length when run on the target. Also it aligns with herd's implementation choice of 128 bit vector length. Please note that predicate register require another allocator which implemented via newly introduced `special2` allocator Signed-off-by: Vladimir Murzin --- gen/AArch64Arch_gen.ml | 46 +++++--- gen/AArch64Compile_gen.ml | 231 ++++++++++++++++++++++++++++++++++++++ gen/X86_64Arch_gen.ml | 1 + gen/archExtra_gen.ml | 8 ++ gen/cycle.ml | 7 +- gen/noSpecial.ml | 1 + gen/noSpecial.mli | 1 + gen/variant_gen.ml | 4 + gen/variant_gen.mli | 2 + 9 files changed, 285 insertions(+), 16 deletions(-) diff --git a/gen/AArch64Arch_gen.ml b/gen/AArch64Arch_gen.ml index 0f5fab7e5d..c1dc9f6123 100644 --- a/gen/AArch64Arch_gen.ml +++ b/gen/AArch64Arch_gen.ml @@ -35,6 +35,7 @@ let do_morello = C.variant Variant_gen.Morello let do_fullkvm = C.variant Variant_gen.FullKVM let do_kvm = do_fullkvm || C.variant Variant_gen.KVM let do_neon = C.variant Variant_gen.Neon +let do_sve = C.variant Variant_gen.SVE let do_mixed = Variant_gen.is_mixed C.variant let do_cu = C.variant Variant_gen.ConstrainedUnpredictable @@ -60,7 +61,7 @@ module Mixed = let bellatom = false module SIMD = struct - type atom = NeP|NeAcqPc|NeRel|Ne1|Ne2|Ne3|Ne4|Ne2i|Ne3i|Ne4i|NePa|NePaN + type atom = SvV|Sv1|Sv2i|Sv3i|Sv4i|NeP|NeAcqPc|NeRel|Ne1|Ne2|Ne3|Ne4|Ne2i|Ne3i|Ne4i|NePa|NePaN let fold_neon f r = r |> f NeAcqPc |> f NeRel |> @@ -69,19 +70,25 @@ module SIMD = struct f Ne1 |> f Ne2 |> f Ne3 |> f Ne4 |> f Ne2i |> f Ne3i |> f Ne4i + let fold_sve f r = r |> + f SvV |> f Sv1 |> + f Sv2i |> f Sv3i |> f Sv4i + let nregs = function - | Ne1 -> 1 - | Ne2 | Ne2i -> 2 - | Ne3 | Ne3i -> 3 - | Ne4 | Ne4i -> 4 + | SvV | Sv1 | Ne1 -> 1 + | Sv2i | Ne2 | Ne2i -> 2 + | Sv3i | Ne3 | Ne3i -> 3 + | Sv4i | Ne4 | Ne4i -> 4 | _ -> 1 let nelements = function + | SvV|Sv1|Sv2i|Sv3i|Sv4i | Ne1|Ne2|Ne2i|Ne3|Ne3i|Ne4|Ne4i -> 4 | NePa|NePaN -> 2 | NeP | NeAcqPc | NeRel -> 1 let pp_opt = function + | Sv2i | Sv3i | Sv4i | Ne2i | Ne3i | Ne4i -> "i" | _ -> "" @@ -89,6 +96,9 @@ module SIMD = struct match n with | Ne1 | Ne2 | Ne3 | Ne4 | Ne2i | Ne3i | Ne4i -> Printf.sprintf "Ne%i%s" (nregs n) (pp_opt n) + | Sv1 | Sv2i | Sv3i | Sv4i -> + Printf.sprintf "Sv%i%s" (nregs n) (pp_opt n) + | SvV -> "SvV" | NePa -> "NePa" | NePaN -> "NePaN" | NeP -> "NeP" @@ -107,9 +117,10 @@ module SIMD = struct for k = 0 to sz-1 do for i=0 to el-1 do let j = match n with - | Ne2i | Ne3i | Ne4i -> k+i*sz + | Sv2i | Sv3i | Sv4i | Ne2i | Ne3i | Ne4i -> k+i*sz | NeP | NeAcqPc | NeRel | NePa | NePaN - | Ne1 | Ne2 | Ne3 | Ne4 -> i+k*el + | Ne1 | Ne2 | Ne3 | Ne4 + | SvV | Sv1 -> i+k*el in v.(j) <- start+k done @@ -120,9 +131,10 @@ module SIMD = struct let el = nelements n in let sz = nregs n in let access r k = match n with - | Ne2i | Ne3i | Ne4i -> sz*k + r + | Sv2i | Sv3i | Sv4i | Ne2i | Ne3i | Ne4i -> sz*k + r | NeP | NeAcqPc | NeRel | NePa | NePaN - | Ne1 | Ne2 | Ne3 | Ne4 -> el*r + k + | Ne1 | Ne2 | Ne3 | Ne4 + | SvV | Sv1 -> el*r + k in let rec reg r k = if k >= el then [] @@ -335,6 +347,12 @@ let is_ifetch a = match a with else fun _ r -> r + let fold_sve = + if do_sve then + fun f -> SIMD.fold_sve (fun n -> f (Neon n)) + else + fun _ r -> r + let fold_pair f r = if do_mixed then r else @@ -357,6 +375,7 @@ let is_ifetch a = match a with let r = fold_morello f r in let r = fold_tag f r in let r = fold_neon f r in + let r = fold_sve f r in let r = fold_pair f r in let r = fold_acc_opt None f r in let r = @@ -456,10 +475,10 @@ let is_ifetch a = match a with function | NeP | NeAcqPc | NeRel -> 1 | NePa | NePaN -> 2 - | Ne1 -> 4 - | Ne2 | Ne2i -> 8 - | Ne3 | Ne3i -> 12 - | Ne4 | Ne4i -> 16 + | SvV | Sv1 | Ne1 -> 4 + | Sv2i | Ne2 | Ne2i -> 8 + | Sv3i | Ne3 | Ne3i -> 12 + | Sv4i | Ne4 | Ne4i -> 16 let atom_to_bank = function | Tag,None -> Code.Tag @@ -866,6 +885,7 @@ include type special = reg let specials = vregs + let specials2 = pregs end) end diff --git a/gen/AArch64Compile_gen.ml b/gen/AArch64Compile_gen.ml index 87fb37669b..559f5b4cf5 100644 --- a/gen/AArch64Compile_gen.ml +++ b/gen/AArch64Compile_gen.ml @@ -60,11 +60,26 @@ module Make(Cfg:Config) : XXXCompile_gen.S = | Vreg (r,(_,64)) -> A64.SIMDreg r | _ -> assert false (* ? *) + let to_scalable_vec r = match r with + | Vreg (r,(_,s)) -> A64.Zreg (r,s) + | _ -> assert false (* ? *) + let next_vreg x = A64.alloc_special x let next_scalar_reg x = let r,x = next_vreg x in to_scalar r,x + let next_zreg x = + let r,x = next_vreg x in + to_scalable_vec r,x + + let next_preg x = A64.alloc_special2 x + + let with_mode m r = match r with + | Preg (r,_) -> PMreg(r,m) + | PMreg (r,_) -> PMreg(r,m) + | _ -> assert false + let pseudo = List.map (fun i -> Instruction i) let tempo1 st = A.alloc_trashed_reg "T1" st (* May be used for address *) @@ -85,6 +100,25 @@ module Make(Cfg:Config) : XXXCompile_gen.S = | Ne2 | Ne2i -> call_rec Ne1 st | Ne3 | Ne3i -> call_rec Ne2 st | Ne4 | Ne4i -> call_rec Ne3 st + | _ -> assert false + in + fun n st -> + let (r,rs),st = get_reg_list n st in + (r,rs),A.set_friends r rs st + + let emit_zregs = + let rec call_rec n st = + let r1,st = next_zreg st in + let (r2,rs),st = get_reg_list n st in + (r1,(r2::rs)),st + and get_reg_list n st = + let open SIMD in + match n with + | Sv1 -> let r,st = next_zreg st in (r,[]),st + | Sv2i -> call_rec Sv1 st + | Sv3i -> call_rec Sv2i st + | Sv4i -> call_rec Sv3i st + | _ -> assert false in fun n st -> let (r,rs),st = get_reg_list n st in @@ -238,6 +272,15 @@ module Make(Cfg:Config) : XXXCompile_gen.S = | Ne4i -> I_LD4M (rs,rt,K 0) | _ -> assert false + let ldnsv n rs pg rn idx= + let open SIMD in + match n with + | Sv1 -> I_LD1SP (VSIMD32,rs,with_mode Zero pg,rn,idx) + | Sv2i -> I_LD2SP (VSIMD32,rs,with_mode Zero pg,rn,idx) + | Sv3i -> I_LD3SP (VSIMD32,rs,with_mode Zero pg,rn,idx) + | Sv4i -> I_LD4SP (VSIMD32,rs,with_mode Zero pg,rn,idx) + | _ -> assert false + let ldr_mixed_idx v r1 r2 idx sz = let idx = MemExt.v2idx_reg v idx in let open MachSize in @@ -278,6 +321,15 @@ module Make(Cfg:Config) : XXXCompile_gen.S = | Ne4i -> I_ST4M (rs,rt,K 0) | _ -> assert false + let stnsv n rs pg rn idx = + let open SIMD in + match n with + | Sv1 -> I_ST1SP (VSIMD32,rs,pg,rn,idx) + | Sv2i -> I_ST2SP (VSIMD32,rs,pg,rn,idx) + | Sv3i -> I_ST3SP (VSIMD32,rs,pg,rn,idx) + | Sv4i -> I_ST4SP (VSIMD32,rs,pg,rn,idx) + | _ -> assert false + let stxr_sz t sz r1 r2 r3 = let open MachSize in match sz with @@ -638,6 +690,77 @@ module Make(Cfg:Config) : XXXCompile_gen.S = r,init,pseudo csA@cs,st end + module LDNW = struct + + let emit_load_reg n st init rA idx = + let start,st = ZR,st in + let finish,st = next_reg st in + let pred,st = next_preg st in + let acc,st = next_vreg st in + let whilelt = [I_WHILELT (pred,V32,start,finish)] in + let setup = [do_movi V32 finish (SIMD.nelements n)]@whilelt in + let (r,rs),st = emit_zregs n st in + let load = [ldnsv n (r::rs) pred rA idx] in + let reduce = (List.map (fun v -> I_ADD_SV (r,r,v)) rs)@[I_UADDV (VSIMD64,to_scalar acc,pred,r)] in + let rX,st = next_reg st in + let fmov = [I_FMOV_TG(V32,rX,VSIMD32,to_scalar acc)] in + rX,init,lift_code (setup@load@reduce@fmov),st + + let emit_load n st p init loc = + let open MemExt in + let idx = Imm(0,Idx) in + let rA,init,st = U.next_init st p init loc in + emit_load_reg n st init rA idx + + let emit_load_idx n v st p init loc ridx = + let open MemExt in + let rA,init,st = U.next_init st p init loc in + let rI,csI,st = match v with + | V32 -> + let r,st = next_reg st in + r,[sxtw r ridx],st + | _ -> ridx,[],st + in + let idx = Reg(V64,rI,LSL,2) in + let r,init,cs,st = emit_load_reg n st init rA idx in + r,init,pseudo csI@cs,st + end + + module LD1G = struct + + let emit_load_reg n st init rA idx = + let start,st = ZR,st in + let finish,st = next_reg st in + let pred,st = next_preg st in + let acc,st = next_vreg st in + let whilelt = [I_WHILELT (pred,V32,start,finish)] in + let setup = [do_movi V32 finish (SIMD.nelements n)]@whilelt in + let r,st = next_zreg st in + let load = [I_LD1SP (VSIMD32,[r],with_mode Zero pred,rA,idx)] in + let reduce = [I_UADDV (VSIMD64,to_scalar acc,pred,r)] in + let rX,st = next_reg st in + let fmov = [I_FMOV_TG(V32,rX,VSIMD32,to_scalar acc)] in + rX,init,lift_code (setup@load@reduce@fmov),st + + let emit_load n st p init loc = + let open MemExt in + let rA,init,st = U.next_init st p init loc in + let rI,st = next_zreg st in + let csI = [I_INDEX_II (rI,0,1)] in + let idx = ZReg(rI,UXTW,2) in + let r,init,cs,st = emit_load_reg n st init rA idx in + r,init,pseudo csI@cs,st + + let emit_load_idx n v st p init loc ridx = + let open MemExt in + let rA,init,st = U.next_init st p init loc in + let rI,st = next_zreg st in + let csI = [I_INDEX_SI (rI,v,ridx,1)] in + let idx = ZReg(rI,UXTW,2) in + let r,init,cs,st = emit_load_reg n st init rA idx in + r,init,pseudo csI@cs,st + end + module LDG = struct let emit_load st p init x = let rA,st = next_reg st in @@ -912,6 +1035,102 @@ module Make(Cfg:Config) : XXXCompile_gen.S = init,lift_code(dup@movi@adds@stlur),st end + module STNW = struct + let emit_store_reg n st init rA v idx = + let start,st = ZR,st in + let finish,st = next_reg st in + let pred,st = next_preg st in + let whilelt = [I_WHILELT (pred,V32,start,finish)] in + let (r,rs),st = emit_zregs n st in + let mov_sv = List.mapi (fun i r -> I_MOV_SV (r,(v+i),S_NOEXT)) (r::rs) in + let setup = [do_movi V32 finish (SIMD.nelements n)]@mov_sv@whilelt in + let store = [stnsv n (r::rs) pred rA idx] in + init,lift_code (setup@store),st + + let emit_store n st p init loc v = + let open MemExt in + let idx = Imm(0,Idx) in + let rA,init,st = U.next_init st p init loc in + emit_store_reg n st init rA v idx + + let emit_store_idx n vdep st p init loc ridx v = + let open MemExt in + let rA,init,st = U.next_init st p init loc in + let rI,csI,st = match vdep with + | V32 -> + let r,st = next_reg st in + r,[sxtw r ridx],st + | _ -> ridx,[],st + in + let idx = Reg(V64,rI,LSL,2) in + let init,cs,st = emit_store_reg n st init rA v idx in + init,pseudo csI@cs,st + + let emit_store_dep n vdep st init rA v = + let open MemExt in + let idx = Imm(0,Idx) in + let rB,st = next_zreg st in + let dup_sv = [I_DUP_SV (rB,V32,vdep)] in + let (r,rs),st = emit_zregs n st in + let mov_sv = List.mapi (fun i r -> I_MOV_SV (r,(v+i),S_NOEXT)) (r::rs) in + let add_sv = List.map (fun v -> I_ADD_SV(v,v,rB)) (r::rs) in + let start,st = ZR,st in + let finish,st = next_reg st in + let pred,st = next_preg st in + let whilelt = [I_WHILELT (pred,V32,start,finish)] in + let setup = dup_sv@mov_sv@add_sv@[do_movi V32 finish (SIMD.nelements n)]@whilelt in + let store = [stnsv n (r::rs) pred rA idx] in + init,lift_code (setup@store),st + end + + module ST1S = struct + let emit_store_reg n st init rA v idx= + let start,st = ZR,st in + let finish,st = next_reg st in + let pred,st = next_preg st in + let whilelt = [I_WHILELT (pred,V32,start,finish)] in + let r,st = next_zreg st in + let mov_sv = [I_MOV_SV (r,v,S_NOEXT)] in + let setup = [do_movi V32 finish (SIMD.nelements n)]@mov_sv@whilelt in + let store = [I_ST1SP (VSIMD32,[r],pred,rA,idx)] in + init,lift_code (setup@store),st + + let emit_store n st p init loc v = + let open MemExt in + let rA,init,st = U.next_init st p init loc in + let rI,st = next_zreg st in + let csI = [I_INDEX_II (rI,0,1)] in + let idx = ZReg(rI,UXTW,2) in + let init,cs,st = emit_store_reg n st init rA v idx in + init,pseudo csI@cs,st + + let emit_store_idx n vdep st p init loc ridx v = + let open MemExt in + let rA,init,st = U.next_init st p init loc in + let rI,st = next_zreg st in + let csI = [I_INDEX_SI (rI,vdep,ridx,1)] in + let idx = ZReg(rI,UXTW,2) in + let init,cs,st = emit_store_reg n st init rA v idx in + init,pseudo csI@cs,st + + let emit_store_dep n vdep st init rA v = + let open MemExt in + let rB,st = next_zreg st in + let dup_sv = [I_DUP_SV (rB,V32,vdep)] in + let r,st = next_zreg st in + let mov_sv = [I_MOV_SV (r,v,S_NOEXT)] in + let add_sv = [I_ADD_SV (r,r,rB)] in + let start,st = ZR,st in + let finish,st = next_reg st in + let pred,st = next_preg st in + let rI,st = next_zreg st in + let whilelt = [I_WHILELT (pred,V32,start,finish)] in + let index = [I_INDEX_II (rI,0,1)] in + let setup = dup_sv@mov_sv@add_sv@[do_movi V32 finish (SIMD.nelements n)]@whilelt in + let store = [I_ST1SP (VSIMD32,[r],pred,rA,ZReg(rI,UXTW,2))] in + init,lift_code (index@setup@store),st + end + module STG = struct let emit_store_reg st p init x rA = @@ -1353,6 +1572,8 @@ module Make(Cfg:Config) : XXXCompile_gen.S = | SIMD.NeP -> LDUR.emit_load | SIMD.NePa -> LDP.emit_load A64.TT | SIMD.NePaN -> LDP.emit_load A64.NT + | SIMD.Sv1 | SIMD.Sv2i | SIMD.Sv3i | SIMD.Sv4i-> LDNW.emit_load n + | SIMD.SvV -> LD1G.emit_load n | _ -> LDN.emit_load n in emit_load @@ -1473,6 +1694,8 @@ module Make(Cfg:Config) : XXXCompile_gen.S = | SIMD.NeP -> LDUR.emit_load | SIMD.NePa -> LDP.emit_load A64.TT | SIMD.NePaN -> LDP.emit_load A64.NT + | SIMD.Sv1 | SIMD.Sv2i | SIMD.Sv3i | SIMD.Sv4i -> LDNW.emit_load n + | SIMD.SvV -> LD1G.emit_load n | _ -> LDN.emit_load n in let r,init,cs,st = emit_load st p init loc in @@ -1566,6 +1789,8 @@ module Make(Cfg:Config) : XXXCompile_gen.S = | SIMD.NeP -> STUR.emit_store | SIMD.NePa -> STP.emit_store A64.TT | SIMD.NePaN -> STP.emit_store A64.NT + | SIMD.Sv1 | SIMD.Sv2i | SIMD.Sv3i | SIMD.Sv4i-> STNW.emit_store n + | SIMD.SvV -> ST1S.emit_store n | _ -> STN.emit_store n in let init,cs,st = emit_store st p init loc e.C.v in @@ -1925,6 +2150,8 @@ module Make(Cfg:Config) : XXXCompile_gen.S = | SIMD.NeP -> LDUR.emit_load_idx | SIMD.NePa -> LDP.emit_load_idx A64.TT | SIMD.NePaN -> LDP.emit_load_idx A64.NT + | SIMD.Sv1 | SIMD.Sv2i | SIMD.Sv3i | SIMD.Sv4i -> LDNW.emit_load_idx n + | SIMD.SvV -> LD1G.emit_load_idx n | _ -> LDN.emit_load_idx n in let rB,init,cs,st = emit_load_idx vdep st p init loc r2 in @@ -2064,6 +2291,8 @@ module Make(Cfg:Config) : XXXCompile_gen.S = | SIMD.NeP -> STUR.emit_store_idx | SIMD.NePa -> STP.emit_store_idx A64.TT | SIMD.NePaN -> STP.emit_store_idx A64.NT + | SIMD.Sv1 | SIMD.Sv2i | SIMD.Sv3i | SIMD.Sv4i -> STNW.emit_store_idx n + | SIMD.SvV -> ST1S.emit_store_idx n | _ -> STN.emit_store_idx n in let init,cs,st = emit_store_idx vdep st p init loc r2 e.C.v in @@ -2266,6 +2495,8 @@ module Make(Cfg:Config) : XXXCompile_gen.S = | SIMD.NeP -> STUR.emit_store_dep | SIMD.NePa -> STP.emit_store_dep A64.TT | SIMD.NePaN -> STP.emit_store_dep A64.NT + | SIMD.Sv1 | SIMD.Sv2i | SIMD.Sv3i | SIMD.Sv4i -> STNW.emit_store_dep n + | SIMD.SvV -> ST1S.emit_store_dep n | _ -> STN.emit_store_dep n in let init,cs,st = emit_store_dep r2 st init rA e.C.v in diff --git a/gen/X86_64Arch_gen.ml b/gen/X86_64Arch_gen.ml index 14cc435956..48cb9085b8 100644 --- a/gen/X86_64Arch_gen.ml +++ b/gen/X86_64Arch_gen.ml @@ -255,5 +255,6 @@ module Make let free_registers = allowed_for_symb type special = xmm let specials = xmms + let specials2 = [] end) end diff --git a/gen/archExtra_gen.ml b/gen/archExtra_gen.ml index fa57953657..20c5078618 100644 --- a/gen/archExtra_gen.ml +++ b/gen/archExtra_gen.ml @@ -25,6 +25,7 @@ module type I = sig type special val specials : special list + val specials2 : special list val pp_i : int -> string end @@ -74,6 +75,7 @@ module type S = sig type special val alloc_special : st -> special * st + val alloc_special2 : st -> special * st val set_friends : arch_reg -> arch_reg list -> st -> st val get_friends : st -> arch_reg -> arch_reg list @@ -219,6 +221,7 @@ with type arch_reg = I.arch_reg and type special = I.special { regs : arch_reg list ; map : arch_reg StringMap.t ; specials : I.special list ; + specials2 : I.special list ; noks : int ; env : TypBase.t LocMap.t ; (* Record types *) (* Group special registers together *) @@ -235,6 +238,7 @@ with type arch_reg = I.arch_reg and type special = I.special { regs = I.free_registers; map = StringMap.empty; specials = I.specials; + specials2 = I.specials2; noks = 0; env = LocMap.empty; friends = RegMap.empty; @@ -267,6 +271,10 @@ with type arch_reg = I.arch_reg and type special = I.special | [] -> Warn.fatal "No more special registers" | r::rs -> r,{ st with specials = rs; } + let alloc_special2 st = match st.specials2 with + | [] -> Warn.fatal "No more special registers" + | r::rs -> r,{ st with specials2 = rs; } + let set_friends r rs st = let friends = RegMap.add r rs st.friends in { st with friends; } diff --git a/gen/cycle.ml b/gen/cycle.ml index f2ece8675b..c46b76d107 100644 --- a/gen/cycle.ml +++ b/gen/cycle.ml @@ -136,6 +136,7 @@ module Make (O:Config) (E:Edge.S) : let do_morello = O.variant Variant_gen.Morello let do_kvm = Variant_gen.is_kvm O.variant let do_neon = O.variant Variant_gen.Neon + let do_sve = O.variant Variant_gen.SVE type fence = E.fence type edge = E.edge @@ -207,8 +208,8 @@ module Make (O:Config) (E:Edge.S) : sprintf " (ord=%i) (ctag=%i) (cseal=%i) (dep=%i)" e.ord e.ctag e.cseal e.dep else fun _ -> "" - let debug_neon = - if do_neon then + let debug_vector = + if do_neon || do_sve then let pp_one = Code.add_vector O.hexa in fun e -> sprintf " (vecreg={%s})" @@ -231,7 +232,7 @@ module Make (O:Config) (E:Edge.S) : (Code.pp_loc e.loc) (match debug_vec e.cell with | "" -> "" | s -> "cell=[" ^ s ^"] ") - pp_v (debug_tag e) (debug_morello e) (debug_neon e) + pp_v (debug_tag e) (debug_morello e) (debug_vector e) let debug_edge = E.pp_edge diff --git a/gen/noSpecial.ml b/gen/noSpecial.ml index 50cec2f900..44044be20b 100644 --- a/gen/noSpecial.ml +++ b/gen/noSpecial.ml @@ -18,3 +18,4 @@ type special let specials = [] +let specials2 = [] diff --git a/gen/noSpecial.mli b/gen/noSpecial.mli index a574699208..2a6c60e7da 100644 --- a/gen/noSpecial.mli +++ b/gen/noSpecial.mli @@ -18,3 +18,4 @@ type special val specials : special list +val specials2 : special list diff --git a/gen/variant_gen.ml b/gen/variant_gen.ml index efc531cc68..1494c5e022 100644 --- a/gen/variant_gen.ml +++ b/gen/variant_gen.ml @@ -38,6 +38,8 @@ type t = | KVM | FullKVM | NoFault (* Neon AArch64 extension *) | Neon +(* Scalable Vector extension (AArch64) *) + | SVE (* Constrained Unpredictable *) | ConstrainedUnpredictable @@ -63,6 +65,7 @@ let parse tag = match Misc.lowercase tag with | "fullkvm" -> Some FullKVM | "nofault" -> Some NoFault | "neon" -> Some Neon +| "sve" -> Some SVE | "constrainedunpredictable"|"cu" -> Some ConstrainedUnpredictable | _ -> None @@ -81,6 +84,7 @@ let pp = function | FullKVM -> "FullKvm" | NoFault -> "NoFault" | Neon -> "Neon" + | SVE -> "sve" | ConstrainedUnpredictable -> "ConstrainedUnpredictable" let is_mixed v = v Mixed || v FullMixed diff --git a/gen/variant_gen.mli b/gen/variant_gen.mli index b5898cc527..7df51d79c8 100644 --- a/gen/variant_gen.mli +++ b/gen/variant_gen.mli @@ -40,6 +40,8 @@ type t = | NoFault (* Neon AArch64 extension *) | Neon +(* SVE AArch64 extension *) + | SVE (* Constrained Unpredictable, ie generate tests thar may exhibit such behaviours. Typically LDXR / STXR of different size or address. *) | ConstrainedUnpredictable