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plasma_atomic.h
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plasma_atomic.h
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/*
* plasma_atomic - portable macros for processor-specific atomic operations
*
* inline assembly and compiler intrinsics for atomic operations
*
*
* Copyright (c) 2012, Glue Logic LLC. All rights reserved. code()gluelogic.com
*
* This file is part of plasma.
*
* plasma is free software: you can redistribute it and/or modify it under
* the terms of the GNU Lesser General Public License as published by
* the Free Software Foundation, either version 2.1 of the License, or
* (at your option) any later version.
*
* plasma is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU Lesser General Public License for more details.
*
* You should have received a copy of the GNU Lesser General Public License
* along with plasma. If not, see <http://www.gnu.org/licenses/>.
*/
#ifndef INCLUDED_PLASMA_ATOMIC_H
#define INCLUDED_PLASMA_ATOMIC_H
#ifndef PLASMA_ATOMIC_C99INLINE
#define PLASMA_ATOMIC_C99INLINE C99INLINE
#endif
#ifndef NO_C99INLINE
#ifndef PLASMA_ATOMIC_C99INLINE_FUNCS
#define PLASMA_ATOMIC_C99INLINE_FUNCS
#endif
#endif
#include "plasma_feature.h"
#include "plasma_attr.h"
#include "plasma_membar.h"
#include "plasma_stdtypes.h"
PLASMA_ATTR_Pragma_once
/*
* plasma_atomic_CAS_ptr - atomic pointer compare-and-swap (CAS)
* plasma_atomic_CAS_64 - atomic 64-bit compare-and-swap (CAS)
* plasma_atomic_CAS_32 - atomic 32-bit compare-and-swap (CAS)
*
* NB: Intended use is with regular, cacheable memory
* Intended use is on naturally aligned integral types
* Not appropriate for float or double types
* Not appropriate for MMIO, SSE, or drivers
* Futher information can be found in plasma_membar.h
*
* NB: please be aware how these building blocks are used
* platforms with CAS instruction are vulnerable to A-B-A race
* when swapping ptrs to structs and modifying the values in the structs
* (e.g. next ptr in struct) -- caller must take appropriate precautions
* (CAS == compare-and-swap)
* platforms with LL/SC instructions avoid A-B-A race
* (LL/SC == load linked, store conditional)
*
* NB: Input must be properly aligned for atomics to function properly
* 64-bit must be at least 8-byte aligned
* 32-bit must be at least 4-byte aligned
*
* NB: Use plasma_atomic_CAS_ptr() instead of plasma_atomic_CAS_ptr_impl()
* Use plasma_atomic_CAS_64() instead of plasma_atomic_CAS_64_impl()
* Use plasma_atomic_CAS_32() instead of plasma_atomic_CAS_32_impl()
*
* plasma_atomic_CAS_*_impl() is intended to be used in inline functions
* which comply with the following restrictions: cmpval must be a variable
* on the stack (and not a constant), must be re-initialized each time
* before these macros are called, and must not have side effects of
* evaluation. This is so that when these macros are used in reentrant
* code, there is not a race condition accessing cmpval more than once.
* There would be a race if cmpval were accessed through a pointer that
* another thread might modify. Additionally, implementations might modify
* cmpval, another reason cmpval must be re-initialized before each use,
* and why cmpval must be a variable and not a constant. Typical usage
* of these macros is in a loop, and cmpval should already need to be
* re-initialized before each use for many scenarios using these macros.
* To avoid compiler warnings, casts are used, so type-safety is discarded.
*
* NB: Note: 64-bit ops might not be available when code is compiled 32-bits.
* (depends on the platform and compiler intrinsic support)
* On AIX, 32-bit compilation should specify arch, e.g. -q32 -qarch=pwr5
* or other 64-bit hardware -qarch, or else ld errors may look similar to:
* ld: 0711-317 ERROR: Undefined symbol: .plasma_atomic_fetch_add_u64
* ld: 0711-317 ERROR: Undefined symbol: .plasma_atomic_fetch_sub_u64
* ld: 0711-317 ERROR: Undefined symbol: .plasma_atomic_fetch_or_u64
* ld: 0711-317 ERROR: Undefined symbol: .plasma_atomic_fetch_and_u64
* ld: 0711-317 ERROR: Undefined symbol: .plasma_atomic_fetch_xor_u64
* ld: 0711-317 ERROR: Undefined symbol: .plasma_atomic_exchange_n_64
* ld: 0711-317 ERROR: Undefined symbol: .plasma_atomic_compare_exchange_n_64
*
* NB: in contrast to C11 pattern where atomic_xxx() implies sequential
* consistency and atomic_xxx_explicit() specifies memory_order,
* plasma_atomic_xxx_T(), where T is type, implies memory_order_relaxed
* (i.e. no barrier), and plasma_atomic_xxx_T_mmm species memory_order.
*
* FUTURE: Current plasma_atomic implementation is done w/ compiler intrinsics.
* Intrinsics might provide stronger (slower) memory barriers than
* required. Might provide assembly code implementations with more
* precise barriers and to support additional compilers on each platform
*
* known current limitations:
* - not implemented: 64-bit ops on 32-bit CPU w/o help from compiler intrinsics
* - suboptimal: HP-UX on Itanium plasma implementation (should avoid volatile)
* - assumption: native 64-bit load or store is atomic even in 32-bit compile
* (given natural alignment of load target and store target)
*/
#if defined(_MSC_VER)
#include <intrin.h>
#pragma intrinsic(_InterlockedCompareExchange)
#pragma intrinsic(_InterlockedCompareExchange64)
#pragma intrinsic(_InterlockedCompareExchangePointer)
#pragma intrinsic(_InterlockedExchange)
#pragma intrinsic(_InterlockedExchange64)
#pragma intrinsic(_InterlockedExchangePointer)
#define plasma_atomic_CAS_ptr_impl(ptr, cmpval, newval) \
(_InterlockedCompareExchangePointer((ptr),(newval),(cmpval)) \
== (cmpval))
#define plasma_atomic_CAS_64_impl(ptr, cmpval, newval) \
(_InterlockedCompareExchange64((ptr),(newval),(cmpval)) == (cmpval))
#define plasma_atomic_CAS_32_impl(ptr, cmpval, newval) \
(_InterlockedCompareExchange((ptr),(newval),(cmpval)) == (cmpval))
#define plasma_atomic_CAS_ptr_val_impl(ptr, cmpval, newval) \
_InterlockedCompareExchangePointer((ptr),(newval),(cmpval))
#define plasma_atomic_CAS_64_val_impl(ptr, cmpval, newval) \
_InterlockedCompareExchange64((ptr),(newval),(cmpval))
#define plasma_atomic_CAS_32_val_impl(ptr, cmpval, newval) \
_InterlockedCompareExchange((ptr),(newval),(cmpval))
#define plasma_atomic_xchg_ptr_impl(ptr, newval) \
_InterlockedExchangePointer((ptr),(newval))
#define plasma_atomic_xchg_64_impl(ptr, newval) \
_InterlockedExchange64((ptr),(newval))
#define plasma_atomic_xchg_32_impl(ptr, newval) \
_InterlockedExchange((ptr),(newval))
#elif defined(__APPLE__) && defined(__MACH__)
#include <libkern/OSAtomic.h>
#if ( (defined(MAC_OS_X_VERSION_MIN_REQUIRED) \
&& MAC_OS_X_VERSION_MIN_REQUIRED-0 >= 1050) \
|| (defined(__IPHONE_OS_VERSION_MIN_REQUIRED) \
&& __IPHONE_OS_VERSION_MIN_REQUIRED-0 >= 20000) )
#define plasma_atomic_CAS_ptr_impl(ptr, cmpval, newval) \
(OSAtomicCompareAndSwapPtr((cmpval),(newval),(ptr)))
#endif
#define plasma_atomic_CAS_64_impl(ptr, cmpval, newval) \
(OSAtomicCompareAndSwap64((int64_t)(cmpval),(int64_t)(newval), \
(int64_t *)(ptr)))
#define plasma_atomic_CAS_32_impl(ptr, cmpval, newval) \
(OSAtomicCompareAndSwap32((int32_t)(cmpval),(int32_t)(newval), \
(int32_t *)(ptr)))
#elif defined(__sun) && defined(__SVR4)
/* Solaris 10 provides library functions to perform many atomic operations.
* Doing so encapsulates the implementation, allowing for an optimal set of
* instructions depending on the underlying hardware, at the minor cost of
* the overhead of a shared library function call.
* Sun Studio 12.1 adds support for extended inline asm and so inline assembly
* could now be provided, replacing .il inline function templates were the
* prior assembly inlining mechanism on Solaris. However, coding inline
* assembly must be done very carefully to ensure correctness.
* https://blogs.oracle.com/wesolows/entry/gcc_inline_assembly_part_2
*/
#include <atomic.h>
#define plasma_atomic_CAS_ptr_impl(ptr, cmpval, newval) \
(atomic_cas_ptr((ptr),(cmpval),(newval)) == (cmpval))
#define plasma_atomic_CAS_64_impl(ptr, cmpval, newval) \
(atomic_cas_64((ptr),(cmpval),(newval)) == (cmpval))
#define plasma_atomic_CAS_32_impl(ptr, cmpval, newval) \
(atomic_cas_32((ptr),(cmpval),(newval)) == (cmpval))
#define plasma_atomic_CAS_ptr_val_impl(ptr, cmpval, newval) \
atomic_cas_ptr((ptr),(cmpval),(newval))
#define plasma_atomic_CAS_64_val_impl(ptr, cmpval, newval) \
atomic_cas_64((ptr),(cmpval),(newval))
#define plasma_atomic_CAS_32_val_impl(ptr, cmpval, newval) \
atomic_cas_32((ptr),(cmpval),(newval))
#define plasma_atomic_xchg_ptr_impl(ptr, newval) \
(atomic_swap_ptr((ptr),(newval)))
#define plasma_atomic_xchg_64_impl(ptr, newval) \
(atomic_swap_64((ptr),(newval)))
#define plasma_atomic_xchg_32_impl(ptr, newval) \
(atomic_swap_32((ptr),(newval)))
#elif defined(__ppc__) || defined(_ARCH_PPC) || \
defined(_ARCH_PWR) || defined(_ARCH_PWR2) || defined(_POWER)
/* AIX xlC compiler intrinsics __compare_and_swap() and __compare_and_swaplp()
* require pointer to cmpval and the original contents in ptr is always
* copied into cmpval, whether or not the swap occurred. Further, &(cmpval)
* is (incorrectly) rejected as an invalid lvalue, so (&cmpval) is used,
* which is less safe for macro encapsulation (callers must be more careful
* what is passed). Also, be sure to save/reset cmpval if used in loop.
* AIX xlC compiler intrinsics __check_lock_mp() and __check_lockd_mp() do not
* require a pointer to cmpval, but note that the return value is the inverse
* to the return value of __compare_and_swap()
* AIX xlC compiler intrinsics __clear_lock_mp() and __clear_lockd_mp() add a
* full 'sync' barrier */
#if defined(__IBMC__) || defined(__IBMCPP__)
#ifdef __cplusplus
#include <builtins.h>
#endif
typedef struct plasma_atomic_words
{uint32_t hi; uint32_t lo;} __attribute_aligned__(8)
__attribute_may_alias__
plasma_atomic_words;
#define plasma_atomic_CAS_32_impl(ptr, cmpval, newval) \
__compare_and_swap((int *)(ptr),(int *)(&cmpval),(int)(newval))
/* !__check_lock_mp((int *)(ptr),(int)(cmpval),(int)(newval)) */
#define plasma_atomic_CAS_32_val_impl(ptr, cmpval, newval) \
(__compare_and_swap((int *)(ptr), \
(int *)(&cmpval),(int)(newval)), (cmpval))
#define plasma_atomic_xchg_32_impl(ptr, newval) \
__fetch_and_swap((int *)(ptr),(int)(newval))
#if defined(_LP64) || defined(__LP64__)
#define plasma_atomic_CAS_64_impl(ptr, cmpval, newval) \
__compare_and_swaplp((long *)(ptr), \
(long *)(&cmpval),(long)(newval))
/*!__check_lockd_mp((long *)(ptr),(long)(cmpval),(long)(newval))*/
#define plasma_atomic_CAS_64_val_impl(ptr, cmpval, newval) \
(__compare_and_swaplp((long *)(ptr), \
(long *)(&cmpval),(long)(newval)), (cmpval))
#define plasma_atomic_xchg_64_impl(ptr, newval) \
__fetch_and_swaplp((long *)(ptr),(long)(newval))
#elif defined(_ARCH_PPC64)
/* AIX 64-bit intrinsics not available for 32-bit compile.
* xlC sets _ARCH_PPC64 when compiler arch target is 64-bit architecture,
* even if compilation is 32-bit (xlc -q32)
* (could avoid a couple extra instructions including a branch if each use
* of plasma_atomic_stdcx() in a loop were implemented completely in
* assembly so loop could branch off condition code from stdcx. instead
* of moving result from CR0 to a register (previously initialized 0),
* followed by a cmp and branch) */
#define plasma_atomic_ldarx(ptr) \
__extension__ ({ \
plasma_atomic_words plasma_atomic_tmpw; \
__asm__ volatile ("\t ldarx %0, %2, %3 \n" \
"\t srdi %1, %0, 32 \n" \
:"=r"(plasma_atomic_tmpw.lo), \
"=r"(plasma_atomic_tmpw.hi) \
:"i"(0),"r"(ptr),"m"(*(ptr)) \
:"cr0"); \
*(uint64_t *)&plasma_atomic_tmpw; \
})
#define plasma_atomic_stdcx(ptr, newval) \
__extension__ ({ \
plasma_atomic_words plasma_atomic_tmpw; \
int plasma_atomic_tmp = 0; \
*(__typeof__(*(ptr)) *)&plasma_atomic_tmpw = (newval); \
__asm__ volatile ("\t rldimi %2, %3, 32, 64 \n" \
"\t stdcx. %2, 0, %4 \n" \
"\t mfocrf %0, 0x80 \n" \
:"=r"(plasma_atomic_tmp), "=m"(*(ptr)) \
:"r"(plasma_atomic_tmpw.lo), \
"r"(plasma_atomic_tmpw.hi), "r"(ptr) \
:"cr0"); \
plasma_atomic_tmp; \
})
#define plasma_atomic_CAS_64_impl(ptr, cmpval, newval) \
__extension__ ({ \
bool plasma_atomic_tmp_rv; \
do { \
plasma_atomic_tmp_rv = \
((cmpval) == plasma_atomic_ldarx((uint64_t *)(ptr))); \
} while (__builtin_expect( plasma_atomic_tmp_rv, 1) \
&& __builtin_expect( \
!plasma_atomic_stdcx((uint64_t *)(ptr), \
(uint64_t)(newval)), 0)); \
plasma_atomic_tmp_rv; \
})
#define plasma_atomic_CAS_64_val_impl(ptr, cmpval, newval) \
__extension__ ({ \
uint64_t plasma_atomic_tmp_cas; \
do { \
plasma_atomic_tmp_cas = \
plasma_atomic_ldarx((uint64_t *)(ptr)); \
} while (__builtin_expect( \
((cmpval) == plasma_atomic_tmp_cas), 1) \
&& __builtin_expect( \
!plasma_atomic_stdcx((uint64_t *)(ptr), \
(uint64_t)(newval)), 0)); \
plasma_atomic_tmp_cas; \
})
#define plasma_atomic_xchg_64_impl(ptr, newval) \
__extension__ ({ \
uint64_t plasma_atomic_tmp_xchg; \
do { \
plasma_atomic_tmp_xchg = \
plasma_atomic_ldarx((uint64_t *)(ptr)); \
} while (__builtin_expect( \
!plasma_atomic_stdcx((uint64_t *)(ptr), \
(uint64_t)(newval)), 0)); \
plasma_atomic_tmp_xchg; \
})
#else
/* (32-bit compile targetting 32-bit CPU)
* (not implemented, but could fall back to mutex implementation) */
#define plasma_atomic_not_implemented_64
#endif
#elif !defined(__GNUC__)/*avoid extra includes; gcc intrinsics further below*/
#ifndef _ALL_SOURCE
#ifndef _H_TYPES
#include <sys/types.h>
#endif
typedef uchar_t uchar;
typedef ushort_t ushort;
typedef uint_t uint;
typedef ulong_t ulong;
#endif/*(IBM should fix sys/atomic_op.h to avoid using non-standard types)*/
#include <sys/atomic_op.h>
#define plasma_atomic_CAS_64_impl(ptr, cmpval, newval) \
compare_and_swaplp((ptr),&(cmpval),(newval))
#define plasma_atomic_CAS_32_impl(ptr, cmpval, newval) \
compare_and_swap((ptr),&(cmpval),(newval))
/* !_check_lock((ptr),(cmpval),(newval)) */
#define plasma_atomic_CAS_64_val_impl(ptr, cmpval, newval) \
(compare_and_swaplp((ptr),&(cmpval),(newval)), (cmpval))
#define plasma_atomic_CAS_32_val_impl(ptr, cmpval, newval) \
(compare_and_swap((ptr),&(cmpval),(newval)), (cmpval))
#endif
#elif defined(__ia64__) \
&& (defined(__HP_cc__) || defined(__HP_aCC__))
#include <machine/sys/inline.h>
/* Implementing Spinlocks on Itanium and PA-RISC
* Section 3.3.1 Compare-and-Exchange */
#define plasma_atomic_ia64_relaxed_fence \
(_Asm_fence) ( _UP_CALL_FENCE | _UP_SYS_FENCE | \
_DOWN_CALL_FENCE | _DOWN_SYS_FENCE )
#define plasma_atomic_CAS_64_impl(ptr, cmpval, newval) \
(_Asm_mov_to_ar(_AREG_CCV,(cmpval),plasma_atomic_ia64_relaxed_fence),\
_Asm_cmpxchg(_SZ_D,_SEM_ACQ,(ptr),(newval),_LDHINT_NONE) == (cmpval))
#define plasma_atomic_CAS_32_impl(ptr, cmpval, newval) \
(_Asm_mov_to_ar(_AREG_CCV,(cmpval),plasma_atomic_ia64_relaxed_fence),\
_Asm_cmpxchg(_SZ_W,_SEM_ACQ,(ptr),(newval),_LDHINT_NONE) == (cmpval))
#define plasma_atomic_CAS_64__val_impl(ptr, cmpval, newval) \
(_Asm_mov_to_ar(_AREG_CCV,(cmpval),plasma_atomic_ia64_relaxed_fence),\
_Asm_cmpxchg(_SZ_D,_SEM_ACQ,(ptr),(newval),_LDHINT_NONE))
#define plasma_atomic_CAS_32_val_impl(ptr, cmpval, newval) \
(_Asm_mov_to_ar(_AREG_CCV,(cmpval),plasma_atomic_ia64_relaxed_fence),\
_Asm_cmpxchg(_SZ_W,_SEM_ACQ,(ptr),(newval),_LDHINT_NONE))
/* Microsoft has stopped supporting Windows on Itanium and
* RedHat has stopped supporting Linux on Itanium, so even though Linux on
* Itanium is still viable, further support is omitted here, at least for now.
* Intrinsics are available for Intel icc compiler, but not implemented here*/
#elif defined(__GNUC__) || defined(__clang__) || defined(__INTEL_COMPILER)
/* see next preprocessor block below;
* preference given to intrinsics over OS system library functions */
#elif !defined(PLASMA_ATOMIC_MUTEX_FALLBACK)
/* (mutex-based fallback implementation enabled by preprocessor define) */
#error "plasma atomics not implemented for platform+compiler; suggestions?"
#endif
/* prefer compiler intrinsics, if present, over OS system library functions */
#if defined(__GNUC__) || defined(__clang__) || defined(__INTEL_COMPILER)
/* (note: __sync_* builtins provide compiler optimization fence) */
/* Linux kernel user helper functions on ARM
* https://github.com/torvalds/linux/blob/master/Documentation/arm/kernel_user_helpers.txt
* and (likely) used by compiler intrinsics
* http://gcc.gnu.org/wiki/Atomic
* (see Built-in atomic support by architecture) */
#undef plasma_atomic_CAS_ptr_impl
#undef plasma_atomic_CAS_ptr_val_impl
#define plasma_atomic_CAS_ptr_impl(ptr, cmpval, newval) \
__sync_bool_compare_and_swap((ptr), (cmpval), (newval))
#define plasma_atomic_CAS_ptr_val_impl(ptr, cmpval, newval) \
__sync_val_compare_and_swap((ptr), (cmpval), (newval))
#if !defined(__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8) && !defined(INTEL_COMPILER) \
&& !(defined(__APPLE__) && defined(__MACH__))
#ifndef plasma_atomic_CAS_64_impl
#define plasma_atomic_not_implemented_64
#endif
#else
#undef plasma_atomic_CAS_64_impl
#undef plasma_atomic_CAS_64_val_impl
#define plasma_atomic_CAS_64_impl(ptr, cmpval, newval) \
__sync_bool_compare_and_swap((ptr), (cmpval), (newval))
#define plasma_atomic_CAS_64_val_impl(ptr, cmpval, newval) \
__sync_val_compare_and_swap((ptr), (cmpval), (newval))
#endif
#undef plasma_atomic_CAS_32_impl
#undef plasma_atomic_CAS_32_val_impl
#define plasma_atomic_CAS_32_impl(ptr, cmpval, newval) \
__sync_bool_compare_and_swap((ptr), (cmpval), (newval))
#define plasma_atomic_CAS_32_val_impl(ptr, cmpval, newval) \
__sync_val_compare_and_swap((ptr), (cmpval), (newval))
#endif
/* default plasma_atomic_CAS_ptr_impl() (if not previously defined) */
#ifndef plasma_atomic_CAS_ptr_impl
#if defined(_LP64) || defined(__LP64__) || defined(_WIN64) /* 64-bit */
#define plasma_atomic_CAS_ptr_impl(ptr, cmpval, newval) \
plasma_atomic_CAS_64_impl((uint64_t *)(ptr), \
(uint64_t)(cmpval),(uint64_t)(newval))
#else
#define plasma_atomic_CAS_ptr_impl(ptr, cmpval, newval) \
plasma_atomic_CAS_32_impl((uint32_t *)(ptr), \
(uint32_t)(cmpval),(uint32_t)(newval))
#endif
#endif
#ifndef plasma_atomic_CAS_ptr_val_impl
#if defined(_LP64) || defined(__LP64__) || defined(_WIN64) /* 64-bit */
#define plasma_atomic_CAS_ptr_val_impl(ptr, cmpval, newval) \
((__typeof__(*(ptr))) \
plasma_atomic_CAS_64_val_impl((uint64_t *)(ptr), \
(uint64_t)(cmpval), \
(uint64_t)(newval)))
#else
#define plasma_atomic_CAS_ptr_val_impl(ptr, cmpval, newval) \
((__typeof__(*(ptr))) \
plasma_atomic_CAS_32_val_impl((uint32_t *)(ptr), \
(uint32_t)(cmpval), \
(uint32_t)(newval)))
#endif
#endif
#ifdef __cplusplus
extern "C" {
#endif
/* op sequences/combinations which provide barriers
* (each macro is not necessarily defined for each platforms) */
/*
* plasma_atomic_ld_nopt - load value from ptr, avoiding compiler optimization
* (intended for internal use; prefer plasma_atomic_load_explicit())
*
* http://software.intel.com/en-us/blogs/2007/11/30/volatile-almost-useless-for-multi-threaded-programming/
* intended replacement when ptr is known to be an _Atomic type:
* atomic_load_explicit(ptr, memmodel)
* Note: 32-bit processors, like 32-bit ARM, require special instructions
* for 64-bit atomic load (not implemented here).
* (xlC compiler gets additional xlC intrinsic __fence() since it appears
* that xlC does not honor 'volatile' as compiler fence)
*/
#if defined(__IBMC__) || defined(__IBMCPP__)
#define plasma_atomic_ld_nopt(ptr) (*(volatile __typeof__(ptr))(ptr)); __fence()
#define plasma_atomic_ld_nopt_T(T,ptr) (*(volatile T)(ptr)); __fence()
#elif defined(__ppc__) || defined(_ARCH_PPC) || \
defined(_ARCH_PWR) || defined(_ARCH_PWR2) || defined(_POWER)
#define plasma_atomic_ld_nopt(ptr) \
(*(volatile __typeof__(ptr))(ptr)); plasma_membar_ccfence()
#define plasma_atomic_ld_nopt_T(T,ptr) \
(*(volatile T)(ptr)); plasma_membar_ccfence()
#else
#define plasma_atomic_ld_nopt(ptr) (*(volatile __typeof__(ptr))(ptr))
#define plasma_atomic_ld_nopt_T(T,ptr) (*(volatile T)(ptr))
#endif
#define plasma_atomic_ld_nopt_into(lval,ptr) \
do { (lval) = plasma_atomic_ld_nopt(ptr); } while (0)
#define plasma_atomic_ld_nopt_T_into(lval,T,ptr) \
do { (lval) = plasma_atomic_ld_nopt(T,(ptr)); } while (0)
/*
* plasma_atomic_st_nopt - store value to ptr, avoiding compiler optimization
* (intended for internal use; prefer plasma_atomic_store_explicit())
*
* http://software.intel.com/en-us/blogs/2007/11/30/volatile-almost-useless-for-multi-threaded-programming/
* intended replacement when ptr is known to be an _Atomic type:
* atomic_store_explicit(ptr, val, memmodel)
* Note: 32-bit processors, like 32-bit ARM, require special instructions
* for 64-bit atomic store (not implemented here).
* (xlC compiler gets additional xlC intrinsic __fence() since it appears
* that xlC does not honor 'volatile' as compiler fence)
*/
#if defined(__IBMC__) || defined(__IBMCPP__)
#define plasma_atomic_st_nopt(ptr,val) \
do { ((*(volatile __typeof__(ptr))(ptr)) = (val)); __fence(); } while(0)
#define plasma_atomic_st_nopt_T(T,ptr,val) \
do { ((*(volatile T)(ptr)) = (val)); __fence(); } while (0)
#elif defined(__ppc__) || defined(_ARCH_PPC) || \
defined(_ARCH_PWR) || defined(_ARCH_PWR2) || defined(_POWER)
#define plasma_atomic_st_nopt(ptr,val) \
do { ((*(volatile __typeof__(ptr))(ptr)) = (val)); \
plasma_membar_ccfence(); \
} while(0)
#define plasma_atomic_st_nopt_T(T,ptr,val) \
do { ((*(volatile T)(ptr)) = (val)); \
plasma_membar_ccfence(); \
} while(0)
#else
#define plasma_atomic_st_nopt(ptr,val) \
((*(volatile __typeof__(ptr))(ptr)) = (val))
#define plasma_atomic_st_nopt_T(T,ptr,val) \
((*(volatile T)(ptr)) = (val))
#endif
/* plasma_atomic_xchg_ptr,64,32_acquire_impl() */
#if defined (_MSC_VER)
#if defined(_M_IA64)
#pragma intrinsic(_InterlockedExchange_acq)
#pragma intrinsic(_InterlockedExchange64_acq)
#pragma intrinsic(_InterlockedExchangePointer_acq)
#define plasma_atomic_xchg_ptr_acquire_impl(ptr, newval) \
_InterlockedExchangePointer_acq((ptr),(newval))
#define plasma_atomic_xchg_64_acquire_impl(ptr, newval) \
_InterlockedExchange64_acq((ptr),(newval))
#define plasma_atomic_xchg_32_acquire_impl(ptr, newval) \
_InterlockedExchange_acq((ptr),(newval))
#elif defined(_M_AMD64) || defined(_M_IX86)
/* (LOCK implied on xchg on x86 and results in full memory barrier) */
#define plasma_atomic_xchg_ptr_acquire_impl(ptr, newval) \
_InterlockedExchangePointer((ptr),(newval))
#define plasma_atomic_xchg_64_acquire_impl(ptr, newval) \
_InterlockedExchange64((ptr),(newval))
#define plasma_atomic_xchg_32_acquire_impl(ptr, newval) \
_InterlockedExchange((ptr),(newval))
#endif
#elif defined(__sun) && defined(__SVR4)
/* TSO (total store order) on SPARC, so acquire barrier is implicit */
#define plasma_atomic_xchg_ptr_acquire_impl(ptr, newval) \
plasma_atomic_xchg_ptr_impl((ptr),(newval))
#define plasma_atomic_xchg_64_acquire_impl(ptr, newval) \
plasma_atomic_xchg_64_impl((ptr),(newval))
#define plasma_atomic_xchg_32_acquire_impl(ptr, newval) \
plasma_atomic_xchg_32_impl((ptr),(newval))
#elif defined(__ia64__) \
&& (defined(__HP_cc__) || defined(__HP_aCC__))
/* 'xchg' instruction has 'acquire' semantics on Itanium */
#define plasma_atomic_xchg_64_acquire_impl(ptr,newval) \
_Asm_xchg(_SZ_D, (ptr), (newval), _LDHINT_NONE)
#define plasma_atomic_xchg_32_acquire_impl(ptr,newval) \
_Asm_xchg(_SZ_W, (ptr), (newval), _LDHINT_NONE)
#if defined(_LP64) || defined(__LP64__) /* 64-bit */
#define plasma_atomic_xchg_ptr_acquire_impl(ptr,newval) \
plasma_atomic_xchg_64_acquire_impl((ptr),(newval))
#else
#define plasma_atomic_xchg_ptr_acquire_impl(ptr,newval) \
plasma_atomic_xchg_32_acquire_impl((ptr),(newval))
#endif
#endif
#if defined(__GNUC__) || defined(__clang__) || defined(__INTEL_COMPILER)
/* Note: gcc __sync_lock_test_and_set() limitation documented at
* http://gcc.gnu.org/onlinedocs/gcc/_005f_005fsync-Builtins.html
* "Many targets have only minimal support for such locks, and do not support
* a full exchange operation. In this case, a target may support reduced
* functionality here by which the only valid value to store is the immediate
* constant 1. The exact value actually stored in *ptr is implementation
* defined."
* An example is ldstub (load-store-unsigned-byte) assembly instruction on
* SPARC which stores 0xFF in unsigned char. XXX: Not handled here are any
* cases where a similar limitation applies to 32- or 64-bit exchange.
* Note: gcc __sync_lock_release adds mfence on x86, and is not used in
* plasma_atomic.h since mfence barrier is stronger than needed for release
* barrier provided by plasma_atomic_lock_release() for cacheable memory */
#undef plasma_atomic_xchg_ptr_acquire_impl
#undef plasma_atomic_xchg_64_acquire_impl
#undef plasma_atomic_xchg_32_acquire_impl
#define plasma_atomic_xchg_ptr_acquire_impl(ptr, newval) \
__sync_lock_test_and_set((ptr), (newval))
#define plasma_atomic_xchg_64_acquire_impl(ptr, newval) \
__sync_lock_test_and_set((ptr), (newval))
#define plasma_atomic_xchg_32_acquire_impl(ptr, newval) \
__sync_lock_test_and_set((ptr), (newval))
#endif
/* default plasma_atomic_xchg_ptr,64,32_impl() (if not previously defined) */
#if !defined(plasma_atomic_xchg_64_impl) \
&& defined(plasma_atomic_xchg_64_acquire_impl)
#define plasma_atomic_xchg_64_impl(ptr,newval) \
plasma_atomic_xchg_64_acquire_impl((ptr),(newval))
#endif
#if !defined(plasma_atomic_xchg_32_impl) \
&& defined(plasma_atomic_xchg_32_acquire_impl)
#define plasma_atomic_xchg_32_impl(ptr,newval) \
plasma_atomic_xchg_32_acquire_impl((ptr),(newval))
#endif
#ifndef plasma_atomic_xchg_ptr_impl
#if defined(_LP64) || defined(__LP64__) || defined(_WIN64) /* 64-bit */
#ifdef plasma_atomic_xchg_64_impl
#define plasma_atomic_xchg_ptr_impl(ptr, newval) \
plasma_atomic_xchg_64_impl((uint64_t *)(ptr),(uint64_t)(newval))
#endif
#else
#ifdef plasma_atomic_xchg_32_impl
#define plasma_atomic_xchg_ptr_impl(ptr, newval) \
plasma_atomic_xchg_32_impl((uint32_t *)(ptr),(uint32_t)(newval))
#endif
#endif
#endif
#if defined(PLASMA_ATOMIC_MUTEX_FALLBACK)
/* mutex-based fallback implementation, enabled by preprocessor define */
bool
plasma_atomic_CAS_64_impl (uint64_t * const ptr,
uint64_t cmpval, const uint64_t newval);
bool
plasma_atomic_CAS_32_impl (uint32_t * const ptr,
uint32_t cmpval, const uint32_t newval);
uint64_t
plasma_atomic_CAS_64_val_impl (uint64_t * const ptr,
uint64_t cmpval, const uint64_t newval);
uint32_t
plasma_atomic_CAS_32_val_impl (uint32_t * const ptr,
uint32_t cmpval, const uint32_t newval);
#if defined(_LP64) || defined(__LP64__) || defined(_WIN64) /* 64-bit */
#define plasma_atomic_CAS_ptr_impl(ptr, cmpval, newval) \
plasma_atomic_CAS_64_impl((ptr),(cmpval),(newval))
#define plasma_atomic_CAS_ptr_val_impl(ptr, cmpval, newval) \
plasma_atomic_CAS_64_val_impl((ptr),(cmpval),(newval))
#else
#define plasma_atomic_CAS_ptr_impl(ptr, cmpval, newval) \
plasma_atomic_CAS_32_impl((ptr),(cmpval),(newval))
#define plasma_atomic_CAS_ptr_val_impl(ptr, cmpval, newval) \
plasma_atomic_CAS_32_val_impl((ptr),(cmpval),(newval))
#endif
#endif
/* create inline routines to encapsulate
* - avoid multiple use of macro param cmpval
* - coerce values into registers or at least variables (instead of constants),
* (address of var and/or integer promotion required for some intrinsics) */
__attribute_nonnull__((1))
__attribute_regparm__((3))
PLASMA_ATOMIC_C99INLINE
bool
plasma_atomic_CAS_ptr (void ** const ptr, void *cmpval, void * const newval);
#ifdef PLASMA_ATOMIC_C99INLINE_FUNCS
__attribute_regparm__((3))
PLASMA_ATOMIC_C99INLINE
bool
plasma_atomic_CAS_ptr (void ** const ptr, void *cmpval, void * const newval)
{
#if defined(__IBMC__) || defined(__IBMCPP__)
/* AIX xlC compiler intrinsics __compare_and_swap(), __compare_and_swaplp()
* have some limitations. See plasma_atomic_CAS_64_impl() macro for AIX */
#if defined(_LP64) || defined(__LP64__) /* 64-bit */
return plasma_atomic_CAS_64_impl(ptr, cmpval, newval);
#else
return plasma_atomic_CAS_32_impl(ptr, cmpval, newval);
#endif
#else
return plasma_atomic_CAS_ptr_impl(ptr, cmpval, newval);
#endif
}
#endif
#ifndef plasma_atomic_not_implemented_64
__attribute_nonnull__()
__attribute_regparm__((3))
PLASMA_ATOMIC_C99INLINE
bool
plasma_atomic_CAS_64 (uint64_t * const ptr,
uint64_t cmpval, const uint64_t newval);
#ifdef PLASMA_ATOMIC_C99INLINE_FUNCS
__attribute_regparm__((3))
PLASMA_ATOMIC_C99INLINE
bool
plasma_atomic_CAS_64 (uint64_t * const ptr,
uint64_t cmpval, const uint64_t newval)
{
return plasma_atomic_CAS_64_impl(ptr, cmpval, newval);
}
#endif
#endif
__attribute_nonnull__()
__attribute_regparm__((3))
PLASMA_ATOMIC_C99INLINE
bool
plasma_atomic_CAS_32 (uint32_t * const ptr,
uint32_t cmpval, const uint32_t newval);
#ifdef PLASMA_ATOMIC_C99INLINE_FUNCS
__attribute_regparm__((3))
PLASMA_ATOMIC_C99INLINE
bool
plasma_atomic_CAS_32 (uint32_t * const ptr,
uint32_t cmpval, const uint32_t newval)
{
return plasma_atomic_CAS_32_impl(ptr, cmpval, newval);
}
#endif
__attribute_nonnull__((1))
__attribute_regparm__((3))
PLASMA_ATOMIC_C99INLINE
void *
plasma_atomic_CAS_ptr_val (void ** const ptr, void *cmpval,void * const newval);
#ifdef PLASMA_ATOMIC_C99INLINE_FUNCS
__attribute_regparm__((3))
PLASMA_ATOMIC_C99INLINE
void *
plasma_atomic_CAS_ptr_val (void ** const ptr, void *cmpval,void * const newval)
{
#if defined(__IBMC__) || defined(__IBMCPP__)
/* AIX xlC compiler intrinsics __compare_and_swap(), __compare_and_swaplp()
* have some limitations. See plasma_atomic_CAS_64_impl() macro for AIX */
#if defined(_LP64) || defined(__LP64__) /* 64-bit */
return plasma_atomic_CAS_64_val_impl(ptr, cmpval, newval);
#else
return plasma_atomic_CAS_32_val_impl(ptr, cmpval, newval);
#endif
#else
return plasma_atomic_CAS_ptr_val_impl(ptr, cmpval, newval);
#endif
}
#endif
#ifndef plasma_atomic_not_implemented_64
__attribute_nonnull__()
__attribute_regparm__((3))
PLASMA_ATOMIC_C99INLINE
uint64_t
plasma_atomic_CAS_64_val (uint64_t * const ptr,
uint64_t cmpval, const uint64_t newval);
#ifdef PLASMA_ATOMIC_C99INLINE_FUNCS
__attribute_regparm__((3))
PLASMA_ATOMIC_C99INLINE
uint64_t
plasma_atomic_CAS_64_val (uint64_t * const ptr,
uint64_t cmpval, const uint64_t newval)
{
return plasma_atomic_CAS_64_val_impl(ptr, cmpval, newval);
}
#endif
#endif
__attribute_nonnull__()
__attribute_regparm__((3))
PLASMA_ATOMIC_C99INLINE
uint32_t
plasma_atomic_CAS_32_val (uint32_t * const ptr,
uint32_t cmpval, const uint32_t newval);
#ifdef PLASMA_ATOMIC_C99INLINE_FUNCS
__attribute_regparm__((3))
PLASMA_ATOMIC_C99INLINE
uint32_t
plasma_atomic_CAS_32_val (uint32_t * const ptr,
uint32_t cmpval, const uint32_t newval)
{
return plasma_atomic_CAS_32_val_impl(ptr, cmpval, newval);
}
#endif
/*(convenience to avoid compiler warnings about signed vs unsigned conversion)*/
#define plasma_atomic_CAS_vptr(ptr,cmpval,newval) \
((__typeof__(*(ptr))) \
plasma_atomic_CAS_ptr((void **)(ptr), \
(void *)(cmpval),(void *)(newval)))
#define plasma_atomic_CAS_u64(ptr,cmpval,newval) \
plasma_atomic_CAS_64((uint64_t *)(ptr), \
(uint64_t)(cmpval),(uint64_t)(newval))
#define plasma_atomic_CAS_u32(ptr,cmpval,newval) \
plasma_atomic_CAS_32((uint32_t *)(ptr), \
(uint32_t)(cmpval),(uint32_t)(newval))
#define plasma_atomic_CAS_vptr_val(ptr,cmpval,newval) \
((__typeof__(*(ptr))) \
plasma_atomic_CAS_ptr_val((void **)(ptr), \
(void *)(cmpval),(void *)(newval)))
#define plasma_atomic_CAS_u64_val(ptr,cmpval,newval) \
plasma_atomic_CAS_64_val((uint64_t *)(ptr), \
(uint64_t)(cmpval),(uint64_t)(newval))
#define plasma_atomic_CAS_u32_val(ptr,cmpval,newval) \
plasma_atomic_CAS_32_val((uint32_t *)(ptr), \
(uint32_t)(cmpval),(uint32_t)(newval))
#define plasma_atomic_CAS_ptr_vcast \
plasma_atomic_CAS_vptr
#define plasma_atomic_CAS_64_ucast \
plasma_atomic_CAS_u64
#define plasma_atomic_CAS_32_ucast \
plasma_atomic_CAS_u32
/*
* plasma_atomic_fetch_{add,sub,or,and,xor} - atomic <op>, memory_order_seq_cst
* plasma_atomic_fetch_*_explicit - atomic <op> specifying memory order
*
* (limited support: at least 64-bit and 32-bit sizes, and maybe others)
*/
#if __has_builtin(__atomic_fetch_add) || __GNUC_PREREQ(4,7)
/* clang 3.3 supports GNUC __atomic_*()
* (check for __atomic_fetch_add() above is sufficient) */
#define plasma_atomic_fetch_add_ptr(ptr, val, memmodel) \
__atomic_fetch_add((ptr), (val), (memmodel))
#define plasma_atomic_fetch_add_u64(ptr, val, memmodel) \
__atomic_fetch_add((ptr), (val), (memmodel))
#define plasma_atomic_fetch_add_u32(ptr, val, memmodel) \
__atomic_fetch_add((ptr), (val), (memmodel))
#define plasma_atomic_fetch_sub_ptr(ptr, val, memmodel) \
__atomic_fetch_sub((ptr), (val), (memmodel))
#define plasma_atomic_fetch_sub_u64(ptr, val, memmodel) \
__atomic_fetch_sub((ptr), (val), (memmodel))
#define plasma_atomic_fetch_sub_u32(ptr, val, memmodel) \
__atomic_fetch_sub((ptr), (val), (memmodel))
#define plasma_atomic_fetch_or_ptr(ptr, val, memmodel) \
__atomic_fetch_or((ptr), (val), (memmodel))
#define plasma_atomic_fetch_or_u64(ptr, val, memmodel) \
__atomic_fetch_or((ptr), (val), (memmodel))
#define plasma_atomic_fetch_or_u32(ptr, val, memmodel) \
__atomic_fetch_or((ptr), (val), (memmodel))
#define plasma_atomic_fetch_and_ptr(ptr, val, memmodel) \
__atomic_fetch_and((ptr), (val), (memmodel))
#define plasma_atomic_fetch_and_u64(ptr, val, memmodel) \
__atomic_fetch_and((ptr), (val), (memmodel))
#define plasma_atomic_fetch_and_u32(ptr, val, memmodel) \
__atomic_fetch_and((ptr), (val), (memmodel))
#define plasma_atomic_fetch_xor_ptr(ptr, val, memmodel) \
__atomic_fetch_xor((ptr), (val), (memmodel))
#define plasma_atomic_fetch_xor_u64(ptr, val, memmodel) \
__atomic_fetch_xor((ptr), (val), (memmodel))
#define plasma_atomic_fetch_xor_u32(ptr, val, memmodel) \
__atomic_fetch_xor((ptr), (val), (memmodel))
#define plasma_atomic_fetch_add_explicit(ptr, val, memmodel) \
__atomic_fetch_add((ptr), (val), (memmodel))
#define plasma_atomic_fetch_add(ptr, val) \
plasma_atomic_fetch_add_explicit((ptr), (val), memory_order_seq_cst)
#define plasma_atomic_fetch_sub_explicit(ptr, val, memmodel) \
__atomic_fetch_sub((ptr), (val), (memmodel))
#define plasma_atomic_fetch_sub(ptr, val) \
plasma_atomic_fetch_sub_explicit((ptr), (val), memory_order_seq_cst)
#define plasma_atomic_fetch_or_explicit(ptr, val, memmodel) \
__atomic_fetch_or((ptr), (val), (memmodel))
#define plasma_atomic_fetch_or(ptr, val) \
plasma_atomic_fetch_or_explicit((ptr), (val), memory_order_seq_cst)
#define plasma_atomic_fetch_and_explicit(ptr, val, memmodel) \
__atomic_fetch_and((ptr), (val), (memmodel))
#define plasma_atomic_fetch_and(ptr, val) \
plasma_atomic_fetch_and_explicit((ptr), (val), memory_order_seq_cst)
#define plasma_atomic_fetch_xor_explicit(ptr, val, memmodel) \
__atomic_fetch_xor((ptr), (val), (memmodel))
#define plasma_atomic_fetch_xor(ptr, val) \
plasma_atomic_fetch_xor_explicit((ptr), (val), memory_order_seq_cst)
#else /* plasma_atomic_fetch_*() */
/*
* plasma_atomic_fetch_add_* - atomic fetch and add specialized implementations
*
* (*_nb_* is short for "no barrier" building block)
*/
#if defined (_MSC_VER)
/* NB: untested with signed types; might not wrap around at INT_MAX, INT_MIN
* (Microsoft provides prototypes that take signed values)
* (result might need to be cast back to original type)
* (MS Windows is LLP64 ABI, so 'long' is 32-bits even when compiler 64-bit)*/
#pragma intrinsic(_InterlockedExchangeAdd)
#pragma intrinsic(_InterlockedExchangeAdd64)
#define plasma_atomic_fetch_add_u64_nb_impl(ptr, addval) \
_InterlockedExchangeAdd64((__int64 *)(ptr),(__int64)(addval))
#define plasma_atomic_fetch_add_u32_nb_impl(ptr, addval) \
_InterlockedExchangeAdd((long *)(ptr),(long)(addval))
#elif defined(__sun) && defined(__SVR4)
#define plasma_atomic_fetch_add_ptr_nb_impl(ptr,addval) ((void *) \
((char *)atomic_add_ptr_nv((ptr),(ssize_t)(addval)) \
- ((ssize_t)(addval))))
#define plasma_atomic_fetch_add_u64_nb_impl(ptr,addval) \
(atomic_add_64_nv((uint64_t *)(ptr),(int64_t)(addval)) \
- ((int64_t)(addval)))
#define plasma_atomic_fetch_add_u32_nb_impl(ptr,addval) \
(atomic_add_32_nv((uint32_t *)(ptr),(int32_t)(addval)) \
- ((int32_t)(addval)))
#elif defined(__APPLE__) && defined(__MACH__)
/* Prefer above macros for __clang__ on MacOSX/iOS instead of these
* NB: untested with signed types; might not wrap around at INT_MAX, INT_MIN
* (Apple provides prototypes that take signed values)
* (result might need to be cast back to original type)
* NB: subtract addval from result in order to return the original value;
* OSAtomicAdd*() returns the resulting value, not the original value */
#define plasma_atomic_fetch_add_u64_nb_impl(ptr, addval) \
(OSAtomicAdd64((int64_t)(addval),(int64_t *)(ptr))-(int64_t)(addval))
#define plasma_atomic_fetch_add_u32_nb_impl(ptr, addval) \
(OSAtomicAdd32((int32_t)(addval),(int32_t *)(ptr))-(int32_t)(addval))
#elif defined(__ia64__) \
&& (defined(__HP_cc__) || defined(__HP_aCC__))
/* NB: _Asm_fetchadd supports only -16, -8, -4, -1, 1, 4, 8, 16 !!!
* and must be an immediate value, not a variable.
* If HP compiler supported something akin to GNU __builtin_constant_p(),
* then a macro could expand and check if addval is constant and legal,
* or else could fallback to call a routine which implemented the atomic
* add via compare and swap. ** Not implemented here **
* http://www.memoryhole.net/kyle/2007/05/atomic_incrementing.html
* _Asm_fetchadd supports optional _Asm_fence arg for .acq or .rel modifiers
* (not used here) */
/*
* #define plasma_atomic_fetch_add_u64_nb_impl(ptr, addval) \
* _Asm_fetchadd(_FASZ_D,_SEM_REL,(ptr),(addval),_LDHINT_NONE)
* #define plasma_atomic_fetch_add_u32_nb_impl(ptr, addval) \
* _Asm_fetchadd(_FASZ_W,_SEM_REL,(ptr),(addval),_LDHINT_NONE)
*/
/* FUTURE: if creating _acquire versions of these macros for use in locks
* instead of xchg or CAS, _Asm_sem should be _SEM_ACQ instead of _SEM_REL and
* additional (optional) _Asm_fence argument might be needed to cause the .acq
* assembly instruction modifier to be emitted. */
/* implement with CAS for portability
* use plasma_atomic_ld_nopt_T() to avoid compiler optimization
* (would prefer atomic_load_explicit() to get ld8.acq or ld4.acq)
* FUTURE: might implement more optimal code than provided by generic macros*/
/* (fall back to inline funcs using generic CAS or LL/SC macros) */
#elif (defined(__ppc__) || defined(_ARCH_PPC) || \
defined(_ARCH_PWR) || defined(_ARCH_PWR2) || defined(_POWER)) \
&& (defined(__IBMC__) || defined(__IBMCPP__))
/* (fall back to inline funcs using generic CAS or LL/SC macros) */
#endif
#if defined(__GNUC__) || defined(__clang__) || defined(__INTEL_COMPILER)
#undef plasma_atomic_fetch_add_ptr_nb_impl
#undef plasma_atomic_fetch_add_u64_nb_impl
#undef plasma_atomic_fetch_add_u32_nb_impl
#define plasma_atomic_fetch_add_ptr_nb_impl(ptr,addval) \
__sync_fetch_and_add((ptr),(addval))
#define plasma_atomic_fetch_add_u64_nb_impl(ptr,addval) \
__sync_fetch_and_add((ptr),(addval))
#define plasma_atomic_fetch_add_u32_nb_impl(ptr,addval) \
__sync_fetch_and_add((ptr),(addval))
#endif
/*
* plasma_atomic_fetch_sub_* - atomic fetch and sub specialized implementations
*
* (leverage plasma_atomic_fetch_add_*() if compiler builtin is not available)
*/
#if defined(__GNUC__) || defined(__clang__) || defined(__INTEL_COMPILER)
#define plasma_atomic_fetch_sub_ptr_nb_impl(ptr,subval) \
__sync_fetch_and_sub((ptr),(subval))
#define plasma_atomic_fetch_sub_u64_nb_impl(ptr,subval) \
__sync_fetch_and_sub((ptr),(subval))
#define plasma_atomic_fetch_sub_u32_nb_impl(ptr,subval) \
__sync_fetch_and_sub((ptr),(subval))
#endif
/*
* plasma_atomic_fetch_or_* - atomic fetch and or specialized implementations
*/
#if defined (_MSC_VER)
/* (MS Windows is LLP64 ABI, so 'long' is 32-bits even when compiler 64-bit)*/
#pragma intrinsic(_InterlockedOr)
#pragma intrinsic(_InterlockedOr64)
#define plasma_atomic_fetch_or_u64_nb_impl(ptr, orval) \
_InterlockedOr64((__int64 *)(ptr),(__int64)(orval))
#define plasma_atomic_fetch_or_u32_nb_impl(ptr, orval) \
_InterlockedOr((long *)(ptr),(long)(orval))
#elif defined(__sun) && defined(__SVR4)