Ability to use PeekPokeTester similar to InterpretiveTester

[wachag]

It is a bit complex to phrase what I want, but I'll try it nonetheless
PeekPokeTester requires that every test should be in the tester class, like:

class GCDPeekPokeTester(c: RealGCD2) extends PeekPokeTester(c) {
poke(c.io.in.bits.a, 1)
}

With InterpretiveTester one has more degree of freedom:

val tester = new InterpretiveTester(s)
tester.poke("io_a", i)

Note: in case of the InterpretiveTester one can create a class, which instantiates an InterpretiveTester, and has a poke() and a peek() method, thus allowing more freedom. This use case can happen in complex verification environments, for example when you want to mimic UVM. An example could be this one (this could be done inside a PeekPokeTester class, but when the sequencers get more complex or you want to do distributed simulation it could be not):

class DUTTester {
def poke(...)=...
def peek(...)=...
... initialization...
}

object Verif extends App{
val seq=new Sequencer()
val dut=new DutTester()
...
dut.poke(seq.next())
...
}

In most cases InterpretiveTester could do the job, however in some cases one wants to use the Verilator backend to test on Verilog level.

[wachag]

One can hack some in a non intended way to have an instance of the PeekPokeTester class, and could to this:
var testerClass: Tester[T] = null
Driver.execute(gen, options) { c: T => {
testerClass = new TesterT
testerClass
}
}
Where Tester extends PeekPokeTester. Then one can use testerClass.peek() and testerClass.poke(). However this one fails to do the intented (but of course not supported) behavior because
https://github.com/freechipsproject/chisel-testers/blob/master/src/main/scala/chisel3/iotesters/Driver.scala#L62
When the constructor of a PeekPokeTester finishes, it automatically stops the simulation.

[chick]

I'm not quite sure what the question is here but I have a feeling that the following test construction example may be relevant. Take a look at /ChiselPokeSpec.scala, it separates out the tester from the DUT creation in a different way and should be runnable with verilog. Let me know if I am not on the right track here.