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Supporting Ultrascale+ is in plan? #2620

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the-centry opened this issue Apr 29, 2022 · 3 comments
Open

Supporting Ultrascale+ is in plan? #2620

the-centry opened this issue Apr 29, 2022 · 3 comments
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@the-centry
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If there is a plan to support u+ device?
Thanks so much!

@mithro
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mithro commented Apr 29, 2022

See https://github.com/f4pga/prjuray - #1651

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Documenting the Xilinx Ultrascale, Ultrascale+ and UltraScale MPSoC series bit-stream format. - GitHub - f4pga/prjuray: Documenting the Xilinx Ultrascale, Ultrascale+ and UltraScale MPSoC series bi...

@mithro
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mithro commented Apr 29, 2022

Support for Ultrascale and Ultrascale+ will most likely end up happening through the FPGA Interchange Format rather than this architecture definitions approach.

You can see some initial xczu7ev support in that method -> https://chipsalliance.github.io/fpga-interchange-tests/#xczu7ev

@mithro mithro changed the title Suporting u+ is in plan? Supporting Ultrascale+ is in plan? Apr 29, 2022
@the-centry
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the-centry commented Apr 30, 2022

Support for Ultrascale and Ultrascale+ will most likely end up happening through the FPGA Interchange Format rather than this architecture definitions approach.

You can see some initial xczu7ev support in that method -> https://chipsalliance.github.io/fpga-interchange-tests/#xczu7ev

FPGA interchange tests — fpga-interchange-tests 0.1 documentation

Ok,thanks so much!
This project fpga-interchange seems like that next-pnr generate *bba through rapidwright,and the use next-pnr place and route! It may meet problem while device's data over the limit of capnp!
It means that the work generating vpr's device data through rapidwright for Ultrascale+ is in plan?

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