diff --git a/esp-hal/src/dma/mod.rs b/esp-hal/src/dma/mod.rs
index 447f605142..542648a5f2 100644
--- a/esp-hal/src/dma/mod.rs
+++ b/esp-hal/src/dma/mod.rs
@@ -1707,7 +1707,7 @@ where
         peri: DmaPeripheral,
         chain: &DescriptorChain,
     ) -> Result<(), DmaError> {
-        // TODO: based on the ESP32-S3 TRM teh alignment check is not needed for TX!
+        // TODO: based on the ESP32-S3 TRM the alignment check is not needed for TX!
         // for esp32s3 we check each descriptor buffer that points to psram for
         // alignment and writeback the cache for that buffer
         #[cfg(esp32s3)]
@@ -2032,7 +2032,6 @@ pub enum DmaBufError {
 }
 
 /// DMA buffer allignments
-#[cfg(all(esp32s3, psram))]
 #[derive(Debug, Clone, Copy, PartialEq)]
 #[cfg_attr(feature = "defmt", derive(defmt::Format))]
 pub enum DmaBufBlkSize {
diff --git a/examples/src/bin/spi_loopback_dma_psram.rs b/examples/src/bin/spi_loopback_dma_psram.rs
index 3c31349ed6..cb5aca8125 100644
--- a/examples/src/bin/spi_loopback_dma_psram.rs
+++ b/examples/src/bin/spi_loopback_dma_psram.rs
@@ -12,6 +12,9 @@
 //! This example transfers data via SPI.
 //! Connect MISO and MOSI pins to see the outgoing data is read as incoming
 //! data.
+//!
+//! If your module is quad PSRAM then you need to change the `psram` feature in the
+//! in the features line below to `psram-2m`.
 
 //% FEATURES: esp-hal/log opsram-2m
 //% CHIPS: esp32s3