This page serves as the landing spot for all hardware development within the OpenTitan project.
We start off by providing links to the results of various tool-flows run on all of our Comportable IPs.
This includes DV simulations, FPV and lint, all of which are run with the dvsim tool which serves as the common frontend.
The Comportable IPs following it provides links to their design specifications and DV documents, and tracks their current stage of development. See the Hardware Development Stages for description of the hardware stages and how they are determined.
Next, we focus on all available processor cores and provide links to their design specifications, DV documents and the DV simulation results.
Finally, we provide the same set of information for all available top level designs.
- DV simulation summary results, with coverage (nightly)
- FPV sec_cm results (weekly)
- FPV ip results (weekly)
- FPV prim results (weekly)
- AscentLint summary results (nightly)
- Verilator lint summary results (nightly)
- Style lint summary results (nightly)
- DV Style lint summary results (nightly)
- FPV Style lint summary results (nightly)
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core_ibex- User manual
- DV document
- DV simulation results, with coverage (nightly) (TBD)
- Datasheet
- Specification
- DV Document
- DV simulation results, with coverage (nightly)
- Connectivity results (nightly)
- AscentLint results (nightly)
- Verilator lint results (nightly)
- Style lint results (nightly)
- DV Style lint results (nightly)
- CDC results (nightly)
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