diff --git a/edk2-rockchip/Platform/Ameridroid/IndiedroidNova/Library/RockchipPlatformLib/RockchipPlatformLib.c b/edk2-rockchip/Platform/Ameridroid/IndiedroidNova/Library/RockchipPlatformLib/RockchipPlatformLib.c
index 22719bbdf..dd6922ed9 100644
--- a/edk2-rockchip/Platform/Ameridroid/IndiedroidNova/Library/RockchipPlatformLib/RockchipPlatformLib.c
+++ b/edk2-rockchip/Platform/Ameridroid/IndiedroidNova/Library/RockchipPlatformLib/RockchipPlatformLib.c
@@ -119,7 +119,7 @@ NorFspiIomux (
 VOID
 EFIAPI
 GmacIomux (
-   UINT32 id
+  IN UINT32 Id
   )
 {
   /* No GMAC here */
diff --git a/edk2-rockchip/Platform/Firefly/ROC-RK3588S-PC/AcpiTables/Dsdt.asl b/edk2-rockchip/Platform/Firefly/ROC-RK3588S-PC/AcpiTables/Dsdt.asl
index 658ed7b31..045ee2516 100644
--- a/edk2-rockchip/Platform/Firefly/ROC-RK3588S-PC/AcpiTables/Dsdt.asl
+++ b/edk2-rockchip/Platform/Firefly/ROC-RK3588S-PC/AcpiTables/Dsdt.asl
@@ -21,7 +21,7 @@ DefinitionBlock ("Dsdt.aml", "DSDT", 2, "RPIFDN", "RPI", 2)
 
     include ("Emmc.asl")
     include ("Sdhc.asl")
-    // include ("Gmac.asl")
+    include ("Gmac1.asl")
     // include ("Gpio.asl")
     // include ("I2c.asl")
     include ("Uart.asl")
diff --git a/edk2-rockchip/Platform/Firefly/ROC-RK3588S-PC/Library/RockchipPlatformLib/RockchipPlatformLib.c b/edk2-rockchip/Platform/Firefly/ROC-RK3588S-PC/Library/RockchipPlatformLib/RockchipPlatformLib.c
index 35404fe90..72cf76615 100644
--- a/edk2-rockchip/Platform/Firefly/ROC-RK3588S-PC/Library/RockchipPlatformLib/RockchipPlatformLib.c
+++ b/edk2-rockchip/Platform/Firefly/ROC-RK3588S-PC/Library/RockchipPlatformLib/RockchipPlatformLib.c
@@ -140,24 +140,40 @@ NorFspiIomux (
 VOID
 EFIAPI
 GmacIomux (
-   UINT32 id
+  IN UINT32 Id
   )
 {
-  switch (id) {
-  case 0:
-    /* gmac0 iomux */
-    BUS_IOC->GPIO2A_IOMUX_SEL_H = (0xFF00UL << 16) | 0x1100;
-    BUS_IOC->GPIO2B_IOMUX_SEL_L = (0xFFFFUL << 16) | 0x1111;
-    BUS_IOC->GPIO2B_IOMUX_SEL_H = (0xFF00UL << 16) | 0x1100;
-    BUS_IOC->GPIO2C_IOMUX_SEL_L = (0xFFFFUL << 16) | 0x1111;
-    BUS_IOC->GPIO4C_IOMUX_SEL_L = (0x0F00UL << 16) | 0x0100;
-    BUS_IOC->GPIO4C_IOMUX_SEL_H = (0x00FFUL << 16) | 0x0011;
-    break;
-  case 1:
-    /* gmac1 iomux */
-    break;
-  default:
-    break;
+  switch (Id) {
+    case 1:
+      /* gmac1 iomux */
+      BUS_IOC->GPIO3B_IOMUX_SEL_H = (0x0FFFUL << 16) | 0x0111;
+      BUS_IOC->GPIO3A_IOMUX_SEL_L = (0xFFFFUL << 16) | 0x1111;
+      BUS_IOC->GPIO3B_IOMUX_SEL_L = (0xF0FFUL << 16) | 0x1011;
+      BUS_IOC->GPIO3A_IOMUX_SEL_H = (0xF0FFUL << 16) | 0x1011;
+      BUS_IOC->GPIO3C_IOMUX_SEL_L = (0xFF00UL << 16) | 0x1100;
+
+      /* phy1 reset */
+      GpioPinSetDirection (0, GPIO_PIN_PD3, GPIO_PIN_OUTPUT);
+      break;
+    default:
+      break;
+  }
+}
+
+VOID
+EFIAPI
+GmacIoPhyReset (
+  UINT32   Id,
+  BOOLEAN  Enable
+  )
+{
+  switch (Id) {
+    case 1:
+      /* phy1 reset */
+      GpioPinWrite (0, GPIO_PIN_PD3, !Enable);
+      break;
+    default:
+      break;
   }
 }
 
diff --git a/edk2-rockchip/Platform/Firefly/ROC-RK3588S-PC/ROC-RK3588S-PC.dsc.inc b/edk2-rockchip/Platform/Firefly/ROC-RK3588S-PC/ROC-RK3588S-PC.dsc.inc
index 9cf9e3af6..4ef5144d5 100644
--- a/edk2-rockchip/Platform/Firefly/ROC-RK3588S-PC/ROC-RK3588S-PC.dsc.inc
+++ b/edk2-rockchip/Platform/Firefly/ROC-RK3588S-PC/ROC-RK3588S-PC.dsc.inc
@@ -78,6 +78,12 @@
   gRK3588TokenSpaceGuid.PcdUsbDpPhy0Supported|TRUE
   gRK3588TokenSpaceGuid.PcdDp0LaneMux|{ 0x2, 0x3 }
 
+  #
+  # GMAC
+  #
+  gRK3588TokenSpaceGuid.PcdGmac1Supported|TRUE
+  gRK3588TokenSpaceGuid.PcdGmac1TxDelay|0x43
+
 ################################################################################
 #
 # Components Section - list of all EDK II Modules needed by this Platform.
diff --git a/edk2-rockchip/Platform/FriendlyElec/NanoPC-T6/Library/RockchipPlatformLib/RockchipPlatformLib.c b/edk2-rockchip/Platform/FriendlyElec/NanoPC-T6/Library/RockchipPlatformLib/RockchipPlatformLib.c
index 35547d474..70f247295 100644
--- a/edk2-rockchip/Platform/FriendlyElec/NanoPC-T6/Library/RockchipPlatformLib/RockchipPlatformLib.c
+++ b/edk2-rockchip/Platform/FriendlyElec/NanoPC-T6/Library/RockchipPlatformLib/RockchipPlatformLib.c
@@ -139,7 +139,7 @@ NorFspiIomux (
 VOID
 EFIAPI
 GmacIomux (
-   UINT32 id
+  IN UINT32 Id
   )
 {
   /* No GMAC here */
diff --git a/edk2-rockchip/Platform/FriendlyElec/NanoPi-R6C/AcpiTables/Dsdt.asl b/edk2-rockchip/Platform/FriendlyElec/NanoPi-R6C/AcpiTables/Dsdt.asl
index 75fc81a60..bde7e0036 100644
--- a/edk2-rockchip/Platform/FriendlyElec/NanoPi-R6C/AcpiTables/Dsdt.asl
+++ b/edk2-rockchip/Platform/FriendlyElec/NanoPi-R6C/AcpiTables/Dsdt.asl
@@ -21,7 +21,7 @@ DefinitionBlock ("Dsdt.aml", "DSDT", 2, "RKCP  ", "RK3588S", 2)
 
     include ("Emmc.asl")
     include ("Sdhc.asl")
-    // include ("Gmac.asl")
+    include ("Gmac1.asl")
     //include ("Gpio.asl")
     //include ("I2c.asl")
     include ("Uart.asl")
diff --git a/edk2-rockchip/Platform/FriendlyElec/NanoPi-R6C/Library/RockchipPlatformLib/RockchipPlatformLib.c b/edk2-rockchip/Platform/FriendlyElec/NanoPi-R6C/Library/RockchipPlatformLib/RockchipPlatformLib.c
index 4bd55ba78..936251d0d 100644
--- a/edk2-rockchip/Platform/FriendlyElec/NanoPi-R6C/Library/RockchipPlatformLib/RockchipPlatformLib.c
+++ b/edk2-rockchip/Platform/FriendlyElec/NanoPi-R6C/Library/RockchipPlatformLib/RockchipPlatformLib.c
@@ -120,26 +120,40 @@ NorFspiIomux (
 VOID
 EFIAPI
 GmacIomux (
-   UINT32 id
+  IN UINT32 Id
   )
 {
-  switch (id) {
-  case 0:
-    /* gmac0 iomux from Radxa Rock-5A */
-#if 0
-    BUS_IOC->GPIO2A_IOMUX_SEL_H = (0xFF00UL << 16) | 0x1100;
-    BUS_IOC->GPIO2B_IOMUX_SEL_L = (0xFFFFUL << 16) | 0x1111;
-    BUS_IOC->GPIO2B_IOMUX_SEL_H = (0xFF00UL << 16) | 0x1100;
-    BUS_IOC->GPIO2C_IOMUX_SEL_L = (0xFFFFUL << 16) | 0x1111;
-    BUS_IOC->GPIO4C_IOMUX_SEL_L = (0x0F00UL << 16) | 0x0100;
-    BUS_IOC->GPIO4C_IOMUX_SEL_H = (0x00FFUL << 16) | 0x0011;
-#endif
-    break;
-  case 1:
-    /* gmac1 iomux */
-    break;
-  default:
-    break;
+  switch (Id) {
+    case 1:
+      /* gmac1 iomux */
+      BUS_IOC->GPIO3B_IOMUX_SEL_H = (0x0FFFUL << 16) | 0x0111;
+      BUS_IOC->GPIO3A_IOMUX_SEL_L = (0xFFFFUL << 16) | 0x1111;
+      BUS_IOC->GPIO3B_IOMUX_SEL_L = (0xF0FFUL << 16) | 0x1011;
+      BUS_IOC->GPIO3A_IOMUX_SEL_H = (0xF0FFUL << 16) | 0x1011;
+      BUS_IOC->GPIO3C_IOMUX_SEL_L = (0xFF00UL << 16) | 0x1100;
+
+      /* phy1 reset */
+      GpioPinSetDirection (3, GPIO_PIN_PB7, GPIO_PIN_OUTPUT);
+      break;
+    default:
+      break;
+  }
+}
+
+VOID
+EFIAPI
+GmacIoPhyReset (
+  UINT32   Id,
+  BOOLEAN  Enable
+  )
+{
+  switch (Id) {
+    case 1:
+      /* phy1 reset */
+      GpioPinWrite (3, GPIO_PIN_PB7, !Enable);
+      break;
+    default:
+      break;
   }
 }
 
diff --git a/edk2-rockchip/Platform/FriendlyElec/NanoPi-R6C/NanoPi-R6C.dsc b/edk2-rockchip/Platform/FriendlyElec/NanoPi-R6C/NanoPi-R6C.dsc
index 1bfa13f6f..0070b09d8 100644
--- a/edk2-rockchip/Platform/FriendlyElec/NanoPi-R6C/NanoPi-R6C.dsc
+++ b/edk2-rockchip/Platform/FriendlyElec/NanoPi-R6C/NanoPi-R6C.dsc
@@ -93,6 +93,12 @@
   gRK3588TokenSpaceGuid.PcdUsbDpPhy0Supported|TRUE
   gRK3588TokenSpaceGuid.PcdDp0LaneMux|{ 0x2, 0x3 }
 
+  #
+  # GMAC
+  #
+  gRK3588TokenSpaceGuid.PcdGmac1Supported|TRUE
+  gRK3588TokenSpaceGuid.PcdGmac1TxDelay|0x42
+
 ################################################################################
 #
 # Components Section - list of all EDK II Modules needed by this Platform.
diff --git a/edk2-rockchip/Platform/FriendlyElec/NanoPi-R6S/AcpiTables/Dsdt.asl b/edk2-rockchip/Platform/FriendlyElec/NanoPi-R6S/AcpiTables/Dsdt.asl
index 658ed7b31..045ee2516 100755
--- a/edk2-rockchip/Platform/FriendlyElec/NanoPi-R6S/AcpiTables/Dsdt.asl
+++ b/edk2-rockchip/Platform/FriendlyElec/NanoPi-R6S/AcpiTables/Dsdt.asl
@@ -21,7 +21,7 @@ DefinitionBlock ("Dsdt.aml", "DSDT", 2, "RPIFDN", "RPI", 2)
 
     include ("Emmc.asl")
     include ("Sdhc.asl")
-    // include ("Gmac.asl")
+    include ("Gmac1.asl")
     // include ("Gpio.asl")
     // include ("I2c.asl")
     include ("Uart.asl")
diff --git a/edk2-rockchip/Platform/FriendlyElec/NanoPi-R6S/Library/RockchipPlatformLib/RockchipPlatformLib.c b/edk2-rockchip/Platform/FriendlyElec/NanoPi-R6S/Library/RockchipPlatformLib/RockchipPlatformLib.c
index fe20c4c63..a8f8457ee 100644
--- a/edk2-rockchip/Platform/FriendlyElec/NanoPi-R6S/Library/RockchipPlatformLib/RockchipPlatformLib.c
+++ b/edk2-rockchip/Platform/FriendlyElec/NanoPi-R6S/Library/RockchipPlatformLib/RockchipPlatformLib.c
@@ -118,24 +118,40 @@ NorFspiIomux (
 VOID
 EFIAPI
 GmacIomux (
-   UINT32 id
+  IN UINT32 Id
   )
 {
-  switch (id) {
-  case 0:
-    /* gmac0 iomux */
-    BUS_IOC->GPIO2A_IOMUX_SEL_H = (0xFF00UL << 16) | 0x1100;
-    BUS_IOC->GPIO2B_IOMUX_SEL_L = (0xFFFFUL << 16) | 0x1111;
-    BUS_IOC->GPIO2B_IOMUX_SEL_H = (0xFF00UL << 16) | 0x1100;
-    BUS_IOC->GPIO2C_IOMUX_SEL_L = (0xFFFFUL << 16) | 0x1111;
-    BUS_IOC->GPIO4C_IOMUX_SEL_L = (0x0F00UL << 16) | 0x0100;
-    BUS_IOC->GPIO4C_IOMUX_SEL_H = (0x00FFUL << 16) | 0x0011;
-    break;
-  case 1:
-    /* gmac1 iomux */
-    break;
-  default:
-    break;
+  switch (Id) {
+    case 1:
+      /* gmac1 iomux */
+      BUS_IOC->GPIO3B_IOMUX_SEL_H = (0x0FFFUL << 16) | 0x0111;
+      BUS_IOC->GPIO3A_IOMUX_SEL_L = (0xFFFFUL << 16) | 0x1111;
+      BUS_IOC->GPIO3B_IOMUX_SEL_L = (0xF0FFUL << 16) | 0x1011;
+      BUS_IOC->GPIO3A_IOMUX_SEL_H = (0xF0FFUL << 16) | 0x1011;
+      BUS_IOC->GPIO3C_IOMUX_SEL_L = (0xFF00UL << 16) | 0x1100;
+
+      /* phy1 reset */
+      GpioPinSetDirection (3, GPIO_PIN_PB7, GPIO_PIN_OUTPUT);
+      break;
+    default:
+      break;
+  }
+}
+
+VOID
+EFIAPI
+GmacIoPhyReset (
+  UINT32   Id,
+  BOOLEAN  Enable
+  )
+{
+  switch (Id) {
+    case 1:
+      /* phy1 reset */
+      GpioPinWrite (3, GPIO_PIN_PB7, !Enable);
+      break;
+    default:
+      break;
   }
 }
 
diff --git a/edk2-rockchip/Platform/FriendlyElec/NanoPi-R6S/NanoPi-R6S.dsc b/edk2-rockchip/Platform/FriendlyElec/NanoPi-R6S/NanoPi-R6S.dsc
index f772fdb06..120313752 100644
--- a/edk2-rockchip/Platform/FriendlyElec/NanoPi-R6S/NanoPi-R6S.dsc
+++ b/edk2-rockchip/Platform/FriendlyElec/NanoPi-R6S/NanoPi-R6S.dsc
@@ -92,6 +92,12 @@
   gRK3588TokenSpaceGuid.PcdUsbDpPhy0Supported|TRUE
   gRK3588TokenSpaceGuid.PcdDp0LaneMux|{ 0x2, 0x3 }
 
+  #
+  # GMAC
+  #
+  gRK3588TokenSpaceGuid.PcdGmac1Supported|TRUE
+  gRK3588TokenSpaceGuid.PcdGmac1TxDelay|0x42
+
 ################################################################################
 #
 # Components Section - list of all EDK II Modules needed by this Platform.
diff --git a/edk2-rockchip/Platform/Hinlink/H88K/AcpiTables/Dsdt.asl b/edk2-rockchip/Platform/Hinlink/H88K/AcpiTables/Dsdt.asl
index 5071e698c..2e8fbfc0d 100755
--- a/edk2-rockchip/Platform/Hinlink/H88K/AcpiTables/Dsdt.asl
+++ b/edk2-rockchip/Platform/Hinlink/H88K/AcpiTables/Dsdt.asl
@@ -21,7 +21,7 @@ DefinitionBlock ("Dsdt.aml", "DSDT", 2, "RPIFDN", "RPI", 2)
 
     include ("Emmc.asl")
     include ("Sdhc.asl")
-    // include ("Gmac.asl")
+    include ("Gmac0.asl")
     // include ("Gpio.asl")
     // include ("I2c.asl")
     include ("Uart.asl")
diff --git a/edk2-rockchip/Platform/Hinlink/H88K/H88K.dsc b/edk2-rockchip/Platform/Hinlink/H88K/H88K.dsc
index 7f5c0eda0..5f4855468 100644
--- a/edk2-rockchip/Platform/Hinlink/H88K/H88K.dsc
+++ b/edk2-rockchip/Platform/Hinlink/H88K/H88K.dsc
@@ -96,6 +96,12 @@
   gRK3588TokenSpaceGuid.PcdDp0LaneMux|{ 0x2, 0x3 }
   gRK3588TokenSpaceGuid.PcdDp1LaneMux|{ 0x0 }
 
+  #
+  # GMAC
+  #
+  gRK3588TokenSpaceGuid.PcdGmac0Supported|TRUE
+  gRK3588TokenSpaceGuid.PcdGmac0TxDelay|0x44
+
 ################################################################################
 #
 # Components Section - list of all EDK II Modules needed by this Platform.
diff --git a/edk2-rockchip/Platform/Hinlink/H88K/Library/RockchipPlatformLib/RockchipPlatformLib.c b/edk2-rockchip/Platform/Hinlink/H88K/Library/RockchipPlatformLib/RockchipPlatformLib.c
index 3222bcf75..4c0df4fd8 100644
--- a/edk2-rockchip/Platform/Hinlink/H88K/Library/RockchipPlatformLib/RockchipPlatformLib.c
+++ b/edk2-rockchip/Platform/Hinlink/H88K/Library/RockchipPlatformLib/RockchipPlatformLib.c
@@ -140,10 +140,42 @@ NorFspiIomux (
 VOID
 EFIAPI
 GmacIomux (
-   UINT32 id
+  IN UINT32 Id
+  )
+{
+  switch (Id) {
+    case 0:
+      /* gmac0 iomux */
+      BUS_IOC->GPIO2A_IOMUX_SEL_H = (0xFF00UL << 16) | 0x1100;
+      BUS_IOC->GPIO2B_IOMUX_SEL_L = (0xFFFFUL << 16) | 0x1111;
+      BUS_IOC->GPIO2B_IOMUX_SEL_H = (0xFF00UL << 16) | 0x1100;
+      BUS_IOC->GPIO2C_IOMUX_SEL_L = (0x0FFFUL << 16) | 0x0111;
+      BUS_IOC->GPIO4C_IOMUX_SEL_L = (0xFF00UL << 16) | 0x1100;
+      BUS_IOC->GPIO4C_IOMUX_SEL_H = (0x00FFUL << 16) | 0x0011;
+
+      /* phy0 reset */
+      GpioPinSetDirection (4, GPIO_PIN_PB3, GPIO_PIN_OUTPUT);
+      break;
+    default:
+      break;
+  }
+}
+
+VOID
+EFIAPI
+GmacIoPhyReset (
+  UINT32   Id,
+  BOOLEAN  Enable
   )
 {
-  /* No GMAC here */
+  switch (Id) {
+    case 0:
+      /* phy0 reset */
+      GpioPinWrite (4, GPIO_PIN_PB3, !Enable);
+      break;
+    default:
+      break;
+  }
 }
 
 VOID
diff --git a/edk2-rockchip/Platform/Khadas/Edge2/Library/RockchipPlatformLib/RockchipPlatformLib.c b/edk2-rockchip/Platform/Khadas/Edge2/Library/RockchipPlatformLib/RockchipPlatformLib.c
index 6ea07dec3..079a76de9 100644
--- a/edk2-rockchip/Platform/Khadas/Edge2/Library/RockchipPlatformLib/RockchipPlatformLib.c
+++ b/edk2-rockchip/Platform/Khadas/Edge2/Library/RockchipPlatformLib/RockchipPlatformLib.c
@@ -139,7 +139,7 @@ NorFspiIomux (
 VOID
 EFIAPI
 GmacIomux (
-   UINT32 id
+  IN UINT32 Id
   )
 {
   /* No GMAC here */
diff --git a/edk2-rockchip/Platform/Mekotronics/R58-Mini/AcpiTables/Dsdt.asl b/edk2-rockchip/Platform/Mekotronics/R58-Mini/AcpiTables/Dsdt.asl
index 5071e698c..2e8fbfc0d 100644
--- a/edk2-rockchip/Platform/Mekotronics/R58-Mini/AcpiTables/Dsdt.asl
+++ b/edk2-rockchip/Platform/Mekotronics/R58-Mini/AcpiTables/Dsdt.asl
@@ -21,7 +21,7 @@ DefinitionBlock ("Dsdt.aml", "DSDT", 2, "RPIFDN", "RPI", 2)
 
     include ("Emmc.asl")
     include ("Sdhc.asl")
-    // include ("Gmac.asl")
+    include ("Gmac0.asl")
     // include ("Gpio.asl")
     // include ("I2c.asl")
     include ("Uart.asl")
diff --git a/edk2-rockchip/Platform/Mekotronics/R58-Mini/Library/RockchipPlatformLib/RockchipPlatformLib.c b/edk2-rockchip/Platform/Mekotronics/R58-Mini/Library/RockchipPlatformLib/RockchipPlatformLib.c
index b815b40f6..681ff7ed9 100644
--- a/edk2-rockchip/Platform/Mekotronics/R58-Mini/Library/RockchipPlatformLib/RockchipPlatformLib.c
+++ b/edk2-rockchip/Platform/Mekotronics/R58-Mini/Library/RockchipPlatformLib/RockchipPlatformLib.c
@@ -139,24 +139,41 @@ NorFspiIomux (
 VOID
 EFIAPI
 GmacIomux (
-   UINT32 id
+  IN UINT32 Id
   )
 {
-  switch (id) {
-  case 0:
-    /* gmac0 iomux */
-    BUS_IOC->GPIO2A_IOMUX_SEL_H = (0xFF00UL << 16) | 0x1100;
-    BUS_IOC->GPIO2B_IOMUX_SEL_L = (0xFFFFUL << 16) | 0x1111;
-    BUS_IOC->GPIO2B_IOMUX_SEL_H = (0xFF00UL << 16) | 0x1100;
-    BUS_IOC->GPIO2C_IOMUX_SEL_L = (0xFFFFUL << 16) | 0x1111;
-    BUS_IOC->GPIO4C_IOMUX_SEL_L = (0x0F00UL << 16) | 0x0100;
-    BUS_IOC->GPIO4C_IOMUX_SEL_H = (0x00FFUL << 16) | 0x0011;
-    break;
-  case 1:
-    /* gmac1 iomux */
-    break;
-  default:
-    break;
+  switch (Id) {
+    case 0:
+      /* gmac0 iomux */
+      BUS_IOC->GPIO2A_IOMUX_SEL_H = (0xFF00UL << 16) | 0x1100;
+      BUS_IOC->GPIO2B_IOMUX_SEL_L = (0xFFFFUL << 16) | 0x1111;
+      BUS_IOC->GPIO2B_IOMUX_SEL_H = (0xFF00UL << 16) | 0x1100;
+      BUS_IOC->GPIO2C_IOMUX_SEL_L = (0x0FFFUL << 16) | 0x0111;
+      BUS_IOC->GPIO4C_IOMUX_SEL_L = (0xFF00UL << 16) | 0x1100;
+      BUS_IOC->GPIO4C_IOMUX_SEL_H = (0x00FFUL << 16) | 0x0011;
+
+      /* phy0 reset */
+      GpioPinSetDirection (4, GPIO_PIN_PB3, GPIO_PIN_OUTPUT);
+      break;
+    default:
+      break;
+  }
+}
+
+VOID
+EFIAPI
+GmacIoPhyReset (
+  UINT32   Id,
+  BOOLEAN  Enable
+  )
+{
+  switch (Id) {
+    case 0:
+      /* phy0 reset */
+      GpioPinWrite (4, GPIO_PIN_PB3, !Enable);
+      break;
+    default:
+      break;
   }
 }
 
diff --git a/edk2-rockchip/Platform/Mekotronics/R58-Mini/R58-Mini.dsc b/edk2-rockchip/Platform/Mekotronics/R58-Mini/R58-Mini.dsc
index fa45d623e..287fee1bf 100644
--- a/edk2-rockchip/Platform/Mekotronics/R58-Mini/R58-Mini.dsc
+++ b/edk2-rockchip/Platform/Mekotronics/R58-Mini/R58-Mini.dsc
@@ -104,6 +104,12 @@
   gRK3588TokenSpaceGuid.PcdDp0LaneMux|{ 0x2, 0x3 }
   gRK3588TokenSpaceGuid.PcdDp1LaneMux|{ 0x0, 0x1, 0x2, 0x3 }
 
+  #
+  # GMAC
+  #
+  gRK3588TokenSpaceGuid.PcdGmac0Supported|TRUE
+  gRK3588TokenSpaceGuid.PcdGmac0TxDelay|0x44
+
 ################################################################################
 #
 # Components Section - list of all EDK II Modules needed by this Platform.
diff --git a/edk2-rockchip/Platform/Mekotronics/R58X/AcpiTables/Dsdt.asl b/edk2-rockchip/Platform/Mekotronics/R58X/AcpiTables/Dsdt.asl
index 5071e698c..5cfd220a1 100644
--- a/edk2-rockchip/Platform/Mekotronics/R58X/AcpiTables/Dsdt.asl
+++ b/edk2-rockchip/Platform/Mekotronics/R58X/AcpiTables/Dsdt.asl
@@ -21,7 +21,8 @@ DefinitionBlock ("Dsdt.aml", "DSDT", 2, "RPIFDN", "RPI", 2)
 
     include ("Emmc.asl")
     include ("Sdhc.asl")
-    // include ("Gmac.asl")
+    include ("Gmac0.asl")
+    include ("Gmac1.asl")
     // include ("Gpio.asl")
     // include ("I2c.asl")
     include ("Uart.asl")
diff --git a/edk2-rockchip/Platform/Mekotronics/R58X/Library/RockchipPlatformLib/RockchipPlatformLib.c b/edk2-rockchip/Platform/Mekotronics/R58X/Library/RockchipPlatformLib/RockchipPlatformLib.c
index 038129e09..3244467e7 100644
--- a/edk2-rockchip/Platform/Mekotronics/R58X/Library/RockchipPlatformLib/RockchipPlatformLib.c
+++ b/edk2-rockchip/Platform/Mekotronics/R58X/Library/RockchipPlatformLib/RockchipPlatformLib.c
@@ -139,24 +139,56 @@ NorFspiIomux (
 VOID
 EFIAPI
 GmacIomux (
-   UINT32 id
+  IN UINT32 Id
   )
 {
-  switch (id) {
-  case 0:
-    /* gmac0 iomux */
-    BUS_IOC->GPIO2A_IOMUX_SEL_H = (0xFF00UL << 16) | 0x1100;
-    BUS_IOC->GPIO2B_IOMUX_SEL_L = (0xFFFFUL << 16) | 0x1111;
-    BUS_IOC->GPIO2B_IOMUX_SEL_H = (0xFF00UL << 16) | 0x1100;
-    BUS_IOC->GPIO2C_IOMUX_SEL_L = (0xFFFFUL << 16) | 0x1111;
-    BUS_IOC->GPIO4C_IOMUX_SEL_L = (0x0F00UL << 16) | 0x0100;
-    BUS_IOC->GPIO4C_IOMUX_SEL_H = (0x00FFUL << 16) | 0x0011;
-    break;
-  case 1:
-    /* gmac1 iomux */
-    break;
-  default:
-    break;
+  switch (Id) {
+    case 0:
+      /* gmac0 iomux */
+      BUS_IOC->GPIO2A_IOMUX_SEL_H = (0xFF00UL << 16) | 0x1100;
+      BUS_IOC->GPIO2B_IOMUX_SEL_L = (0xFFFFUL << 16) | 0x1111;
+      BUS_IOC->GPIO2B_IOMUX_SEL_H = (0xFF00UL << 16) | 0x1100;
+      BUS_IOC->GPIO2C_IOMUX_SEL_L = (0x0FFFUL << 16) | 0x0111;
+      BUS_IOC->GPIO4C_IOMUX_SEL_L = (0xFF00UL << 16) | 0x1100;
+      BUS_IOC->GPIO4C_IOMUX_SEL_H = (0x00FFUL << 16) | 0x0011;
+
+      /* phy0 reset */
+      GpioPinSetDirection (4, GPIO_PIN_PB3, GPIO_PIN_OUTPUT);
+      break;
+    case 1:
+      /* gmac1 iomux */
+      BUS_IOC->GPIO3B_IOMUX_SEL_H = (0x0FFFUL << 16) | 0x0111;
+      BUS_IOC->GPIO3A_IOMUX_SEL_L = (0xFFFFUL << 16) | 0x1111;
+      BUS_IOC->GPIO3B_IOMUX_SEL_L = (0xF0FFUL << 16) | 0x1011;
+      BUS_IOC->GPIO3A_IOMUX_SEL_H = (0xF0FFUL << 16) | 0x1011;
+      BUS_IOC->GPIO3C_IOMUX_SEL_L = (0xFF00UL << 16) | 0x1100;
+
+      /* phy1 reset */
+      GpioPinSetDirection (4, GPIO_PIN_PA2, GPIO_PIN_OUTPUT);
+      break;
+    default:
+      break;
+  }
+}
+
+VOID
+EFIAPI
+GmacIoPhyReset (
+  UINT32   Id,
+  BOOLEAN  Enable
+  )
+{
+  switch (Id) {
+    case 0:
+      /* phy0 reset */
+      GpioPinWrite (4, GPIO_PIN_PB3, !Enable);
+      break;
+    case 1:
+      /* phy1 reset */
+      GpioPinWrite (4, GPIO_PIN_PA2, !Enable);
+      break;
+    default:
+      break;
   }
 }
 
diff --git a/edk2-rockchip/Platform/Mekotronics/R58X/R58X.dsc b/edk2-rockchip/Platform/Mekotronics/R58X/R58X.dsc
index b4662b3db..be06c655d 100644
--- a/edk2-rockchip/Platform/Mekotronics/R58X/R58X.dsc
+++ b/edk2-rockchip/Platform/Mekotronics/R58X/R58X.dsc
@@ -99,6 +99,14 @@
   gRK3588TokenSpaceGuid.PcdDp0LaneMux|{ 0x2, 0x3 }
   gRK3588TokenSpaceGuid.PcdDp1LaneMux|{ 0x0, 0x1, 0x2, 0x3 }
 
+  #
+  # GMAC
+  #
+  gRK3588TokenSpaceGuid.PcdGmac0Supported|TRUE
+  gRK3588TokenSpaceGuid.PcdGmac1Supported|TRUE
+  gRK3588TokenSpaceGuid.PcdGmac0TxDelay|0x44
+  gRK3588TokenSpaceGuid.PcdGmac1TxDelay|0x42
+
 ################################################################################
 #
 # Components Section - list of all EDK II Modules needed by this Platform.
diff --git a/edk2-rockchip/Platform/Mixtile/Blade3/Library/RockchipPlatformLib/RockchipPlatformLib.c b/edk2-rockchip/Platform/Mixtile/Blade3/Library/RockchipPlatformLib/RockchipPlatformLib.c
index c0049286e..92e98fcf7 100644
--- a/edk2-rockchip/Platform/Mixtile/Blade3/Library/RockchipPlatformLib/RockchipPlatformLib.c
+++ b/edk2-rockchip/Platform/Mixtile/Blade3/Library/RockchipPlatformLib/RockchipPlatformLib.c
@@ -139,7 +139,7 @@ NorFspiIomux (
 VOID
 EFIAPI
 GmacIomux (
-   UINT32 id
+  IN UINT32 Id
   )
 {
   /* No GMAC here */
diff --git a/edk2-rockchip/Platform/OrangePi/OrangePi5/AcpiTables/Dsdt.asl b/edk2-rockchip/Platform/OrangePi/OrangePi5/AcpiTables/Dsdt.asl
index 6edf9c0a7..0c64eabc7 100755
--- a/edk2-rockchip/Platform/OrangePi/OrangePi5/AcpiTables/Dsdt.asl
+++ b/edk2-rockchip/Platform/OrangePi/OrangePi5/AcpiTables/Dsdt.asl
@@ -21,7 +21,7 @@ DefinitionBlock ("Dsdt.aml", "DSDT", 2, "RPIFDN", "RPI", 2)
 
     // include ("Emmc.asl")
     include ("Sdhc.asl")
-    // include ("Gmac.asl")
+    include ("Gmac1.asl")
     // include ("Gpio.asl")
     // include ("I2c.asl")
     include ("Uart.asl")
diff --git a/edk2-rockchip/Platform/OrangePi/OrangePi5/Library/RockchipPlatformLib/RockchipPlatformLib.c b/edk2-rockchip/Platform/OrangePi/OrangePi5/Library/RockchipPlatformLib/RockchipPlatformLib.c
index ba5c98538..ad6b13b0e 100644
--- a/edk2-rockchip/Platform/OrangePi/OrangePi5/Library/RockchipPlatformLib/RockchipPlatformLib.c
+++ b/edk2-rockchip/Platform/OrangePi/OrangePi5/Library/RockchipPlatformLib/RockchipPlatformLib.c
@@ -120,24 +120,40 @@ NorFspiIomux (
 VOID
 EFIAPI
 GmacIomux (
-   UINT32 id
+  IN UINT32 Id
   )
 {
-  switch (id) {
-  case 0:
-    /* gmac0 iomux */
-    BUS_IOC->GPIO2A_IOMUX_SEL_H = (0xFF00UL << 16) | 0x1100;
-    BUS_IOC->GPIO2B_IOMUX_SEL_L = (0xFFFFUL << 16) | 0x1111;
-    BUS_IOC->GPIO2B_IOMUX_SEL_H = (0xFF00UL << 16) | 0x1100;
-    BUS_IOC->GPIO2C_IOMUX_SEL_L = (0xFFFFUL << 16) | 0x1111;
-    BUS_IOC->GPIO4C_IOMUX_SEL_L = (0x0F00UL << 16) | 0x0100;
-    BUS_IOC->GPIO4C_IOMUX_SEL_H = (0x00FFUL << 16) | 0x0011;
-    break;
-  case 1:
-    /* gmac1 iomux */
-    break;
-  default:
-    break;
+  switch (Id) {
+    case 1:
+      /* gmac1 iomux */
+      BUS_IOC->GPIO3B_IOMUX_SEL_H = (0x0FFFUL << 16) | 0x0111;
+      BUS_IOC->GPIO3A_IOMUX_SEL_L = (0xFFFFUL << 16) | 0x1111;
+      BUS_IOC->GPIO3B_IOMUX_SEL_L = (0xF0FFUL << 16) | 0x1011;
+      BUS_IOC->GPIO3A_IOMUX_SEL_H = (0xF0FFUL << 16) | 0x1011;
+      BUS_IOC->GPIO3C_IOMUX_SEL_L = (0xFF00UL << 16) | 0x1100;
+
+      /* phy1 reset */
+      GpioPinSetDirection (3, GPIO_PIN_PB2, GPIO_PIN_OUTPUT);
+      break;
+    default:
+      break;
+  }
+}
+
+VOID
+EFIAPI
+GmacIoPhyReset (
+  UINT32   Id,
+  BOOLEAN  Enable
+  )
+{
+  switch (Id) {
+    case 1:
+      /* phy1 reset */
+      GpioPinWrite (3, GPIO_PIN_PB2, !Enable);
+      break;
+    default:
+      break;
   }
 }
 
@@ -200,8 +216,8 @@ UsbPortPowerEnable (
 {
   DEBUG((DEBUG_INFO, "UsbPortPowerEnable called\n"));
   /* Set GPIO3 PC0 (TYPEC_EN) output high to power Type-C/USB2.0 ports */
-  GpioPinWrite (3, GPIO_PIN_PC0, TRUE);
-  GpioPinSetDirection (3, GPIO_PIN_PC0, GPIO_PIN_OUTPUT);
+  //GpioPinWrite (3, GPIO_PIN_PC0, TRUE);
+  //GpioPinSetDirection (3, GPIO_PIN_PC0, GPIO_PIN_OUTPUT);
 
   // DEBUG((DEBUG_INFO, "Trying to enable green led\n"));
   // GpioPinWrite (1, GPIO_PIN_PA2, TRUE);
diff --git a/edk2-rockchip/Platform/OrangePi/OrangePi5/OrangePi5.dsc b/edk2-rockchip/Platform/OrangePi/OrangePi5/OrangePi5.dsc
index c0e75965e..a43421cea 100644
--- a/edk2-rockchip/Platform/OrangePi/OrangePi5/OrangePi5.dsc
+++ b/edk2-rockchip/Platform/OrangePi/OrangePi5/OrangePi5.dsc
@@ -92,6 +92,12 @@
   gRK3588TokenSpaceGuid.PcdUsbDpPhy0Supported|TRUE
   gRK3588TokenSpaceGuid.PcdDp0LaneMux|{ 0x2, 0x3 }
 
+  #
+  # GMAC
+  #
+  gRK3588TokenSpaceGuid.PcdGmac1Supported|TRUE
+  gRK3588TokenSpaceGuid.PcdGmac1TxDelay|0x42
+
 ################################################################################
 #
 # Components Section - list of all EDK II Modules needed by this Platform.
diff --git a/edk2-rockchip/Platform/OrangePi/OrangePi5Plus/Library/RockchipPlatformLib/RockchipPlatformLib.c b/edk2-rockchip/Platform/OrangePi/OrangePi5Plus/Library/RockchipPlatformLib/RockchipPlatformLib.c
index 51f9431db..21912fe38 100644
--- a/edk2-rockchip/Platform/OrangePi/OrangePi5Plus/Library/RockchipPlatformLib/RockchipPlatformLib.c
+++ b/edk2-rockchip/Platform/OrangePi/OrangePi5Plus/Library/RockchipPlatformLib/RockchipPlatformLib.c
@@ -139,7 +139,7 @@ NorFspiIomux (
 VOID
 EFIAPI
 GmacIomux (
-   UINT32 id
+  IN UINT32 Id
   )
 {
   /* No GMAC here */
diff --git a/edk2-rockchip/Platform/Radxa/ROCK5A/AcpiTables/Dsdt.asl b/edk2-rockchip/Platform/Radxa/ROCK5A/AcpiTables/Dsdt.asl
index 658ed7b31..045ee2516 100755
--- a/edk2-rockchip/Platform/Radxa/ROCK5A/AcpiTables/Dsdt.asl
+++ b/edk2-rockchip/Platform/Radxa/ROCK5A/AcpiTables/Dsdt.asl
@@ -21,7 +21,7 @@ DefinitionBlock ("Dsdt.aml", "DSDT", 2, "RPIFDN", "RPI", 2)
 
     include ("Emmc.asl")
     include ("Sdhc.asl")
-    // include ("Gmac.asl")
+    include ("Gmac1.asl")
     // include ("Gpio.asl")
     // include ("I2c.asl")
     include ("Uart.asl")
diff --git a/edk2-rockchip/Platform/Radxa/ROCK5A/Library/RockchipPlatformLib/RockchipPlatformLib.c b/edk2-rockchip/Platform/Radxa/ROCK5A/Library/RockchipPlatformLib/RockchipPlatformLib.c
index b70019349..1b35aded4 100644
--- a/edk2-rockchip/Platform/Radxa/ROCK5A/Library/RockchipPlatformLib/RockchipPlatformLib.c
+++ b/edk2-rockchip/Platform/Radxa/ROCK5A/Library/RockchipPlatformLib/RockchipPlatformLib.c
@@ -119,24 +119,40 @@ NorFspiIomux (
 VOID
 EFIAPI
 GmacIomux (
-   UINT32 id
+  IN UINT32 Id
   )
 {
-  switch (id) {
-  case 0:
-    /* gmac0 iomux */
-    BUS_IOC->GPIO2A_IOMUX_SEL_H = (0xFF00UL << 16) | 0x1100;
-    BUS_IOC->GPIO2B_IOMUX_SEL_L = (0xFFFFUL << 16) | 0x1111;
-    BUS_IOC->GPIO2B_IOMUX_SEL_H = (0xFF00UL << 16) | 0x1100;
-    BUS_IOC->GPIO2C_IOMUX_SEL_L = (0xFFFFUL << 16) | 0x1111;
-    BUS_IOC->GPIO4C_IOMUX_SEL_L = (0x0F00UL << 16) | 0x0100;
-    BUS_IOC->GPIO4C_IOMUX_SEL_H = (0x00FFUL << 16) | 0x0011;
-    break;
-  case 1:
-    /* gmac1 iomux */
-    break;
-  default:
-    break;
+  switch (Id) {
+    case 1:
+      /* gmac1 iomux */
+      BUS_IOC->GPIO3B_IOMUX_SEL_H = (0x0FFFUL << 16) | 0x0111;
+      BUS_IOC->GPIO3A_IOMUX_SEL_L = (0xFFFFUL << 16) | 0x1111;
+      BUS_IOC->GPIO3B_IOMUX_SEL_L = (0xF0FFUL << 16) | 0x1011;
+      BUS_IOC->GPIO3A_IOMUX_SEL_H = (0xF0FFUL << 16) | 0x1011;
+      BUS_IOC->GPIO3C_IOMUX_SEL_L = (0xFF00UL << 16) | 0x1100;
+
+      /* phy1 reset */
+      GpioPinSetDirection (3, GPIO_PIN_PB7, GPIO_PIN_OUTPUT);
+      break;
+    default:
+      break;
+  }
+}
+
+VOID
+EFIAPI
+GmacIoPhyReset (
+  UINT32   Id,
+  BOOLEAN  Enable
+  )
+{
+  switch (Id) {
+    case 1:
+      /* phy1 reset */
+      GpioPinWrite (3, GPIO_PIN_PB7, !Enable);
+      break;
+    default:
+      break;
   }
 }
 
@@ -291,5 +307,5 @@ PlatformEarlyInit (
   )
 {
   // Configure various things specific to this platform
-  
+
 }
diff --git a/edk2-rockchip/Platform/Radxa/ROCK5A/ROCK5A.dsc b/edk2-rockchip/Platform/Radxa/ROCK5A/ROCK5A.dsc
index d10db4aff..3383a19bc 100644
--- a/edk2-rockchip/Platform/Radxa/ROCK5A/ROCK5A.dsc
+++ b/edk2-rockchip/Platform/Radxa/ROCK5A/ROCK5A.dsc
@@ -84,6 +84,13 @@
   gRK3588TokenSpaceGuid.PcdUsbDpPhy0Supported|TRUE
   gRK3588TokenSpaceGuid.PcdDp0LaneMux|{ 0x2, 0x3 }
 
+  #
+  # GMAC
+  #
+  gRK3588TokenSpaceGuid.PcdGmac1Supported|TRUE
+  gRK3588TokenSpaceGuid.PcdGmac1TxDelay|0x3a
+  gRK3588TokenSpaceGuid.PcdGmac1RxDelay|0x3e
+
   #
   # On-Board fan output
   #
diff --git a/edk2-rockchip/Platform/Radxa/ROCK5B/Library/RockchipPlatformLib/RockchipPlatformLib.c b/edk2-rockchip/Platform/Radxa/ROCK5B/Library/RockchipPlatformLib/RockchipPlatformLib.c
index 45be5fdad..8185217cf 100644
--- a/edk2-rockchip/Platform/Radxa/ROCK5B/Library/RockchipPlatformLib/RockchipPlatformLib.c
+++ b/edk2-rockchip/Platform/Radxa/ROCK5B/Library/RockchipPlatformLib/RockchipPlatformLib.c
@@ -140,7 +140,7 @@ NorFspiIomux (
 VOID
 EFIAPI
 GmacIomux (
-   UINT32 id
+  IN UINT32 Id
   )
 {
   /* No GMAC here */
diff --git a/edk2-rockchip/Silicon/Rockchip/Include/Library/RockchipPlatformLib.h b/edk2-rockchip/Silicon/Rockchip/Include/Library/RockchipPlatformLib.h
index c472e8b74..e086375b1 100644
--- a/edk2-rockchip/Silicon/Rockchip/Include/Library/RockchipPlatformLib.h
+++ b/edk2-rockchip/Silicon/Rockchip/Include/Library/RockchipPlatformLib.h
@@ -44,7 +44,14 @@ EnablePWM (
 VOID
 EFIAPI
 GmacIomux (
-  UINT32 id
+  IN UINT32 Id
+  );
+
+VOID
+EFIAPI
+GmacIoPhyReset (
+  IN UINT32   Id,
+  IN BOOLEAN  Enable
   );
 
 VOID
diff --git a/edk2-rockchip/Silicon/Rockchip/RK3588/AcpiTables/Gmac.asl b/edk2-rockchip/Silicon/Rockchip/RK3588/AcpiTables/Gmac.asl
deleted file mode 100644
index a2a5ab6ab..000000000
--- a/edk2-rockchip/Silicon/Rockchip/RK3588/AcpiTables/Gmac.asl
+++ /dev/null
@@ -1,214 +0,0 @@
-/** @file
- *
- *  Copyright (c) 2021, ARM Limited. All rights reserved.
- *
- *  SPDX-License-Identifier: BSD-2-Clause-Patent
- *
- **/
-#include "AcpiTables.h"
-
-  Device (MAC0) {
-    Name (_HID, "PRP0001")
-    Name (_UID, 0)
-    Name (_CCA, 0)
-
-    Method (_CRS, 0x0, Serialized) {
-      Name (RBUF, ResourceTemplate() {
-        Memory32Fixed (ReadWrite, 0xfe1b0000, 0x10000)
-        Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive) { 259, 258 }
-      })
-      Return (RBUF)
-    }
-    Name (_DSD, Package () {
-      ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
-      Package () {
-        Package (2) { "interrupt-names", Package () { "macirq", "eth_wake_irq" }, },
-        Package (2) { "tx_delay", 67 },
-        Package (2) { "compatible", package () { "rockchip,rk3588-gmac", "snps,dwmac-4.20a" }, },
-        Package (2) { "phy-mode", "rgmii-rxid" },
-        Package (2) { "clock_in_out", "output" },
-        Package (2) { "csr-freq", 150000000 },
-        Package (2) { "snps,reset-delays-us", package () { 0, 20000, 100000 } },
-        Package (2) { "phy-handle", \_SB.MAC0.MDIO.PHY0 },
-        Package (2) { "snps,axi-config", \_SB.MAC0.AST0 },
-        Package (2) { "snps,mtl-rx-config", \_SB.MAC0.MRX0 },
-        Package (2) { "snps,mtl-tx-config", \_SB.MAC0.MTX0 },
-        Package () { "snps,mixed-burst", " " },
-        Package () { "snps,tso", " " },
-        Package () { "snps,reset-active-low", " " },
-      }
-    })
-
-    Method(PRST, 0, Serialized) {
-      OperationRegion(CTRL, SystemMemory, 0xfec50000, 0x10)
-      Field(CTRL, DWordAcc,Lock, Preserve) {
-        DRL, 32,
-        DRH, 32,
-        DDRL, 32,
-        DDRH, 32,
-      }
-
-      Store(0x08000800, DDRL)
-      sleep(20)
-      Store(0x08000000, DRL)
-      sleep(200)
-      Store(0x08000800, DRL)
-      sleep(1000)
-    }
-
-    Method(RGMI, 2, Serialized) {
-      OperationRegion(PGRF, SystemMemory, 0xfd5b0008, 0x70)
-      Field(PGRF, DWordAcc,Lock, Preserve) {
-        CON0, 32,
-        Offset(0x68),
-        CLK1, 32,
-      }
-
-      OperationRegion(SGRF, SystemMemory, 0xfd58c31c, 0x8)
-      Field(SGRF, DWordAcc,Lock, Preserve) {
-        CON7, 32,
-        CON8, 32,
-      }
-
-      Store(0x00380008, CON0)
-      Store(0x00010000, CLK1)
-
-      if (LGreater(ToInteger(Arg0), 0)) {
-        Store(0x00040004, CON7)
-        local0 = Arg0 & 0xff
-        local0 = local0 | 0x00ff0000
-        Store(local0, CON8)
-      }
-
-      if (LGreater(ToInteger(Arg1), 0)) {
-        Store(0x00080008, CON7)
-        local1 = Arg1 & 0x00
-        local1 = local1 << 8
-        local1 = local1 | 0xff000000
-        Store(local1, CON8)
-      }
-    }
-
-    Method(RMII, 0, Serialized) {
-      OperationRegion(PGRF, SystemMemory, 0xfd5b0008, 0x70)
-      Field(PGRF, DWordAcc,Lock, Preserve) {
-        CON0, 32,
-        Offset(0x68),
-        CLK1, 32,
-      }
-
-      Store(0x00380020, CON0)
-      Store(0x00010001, CLK1)
-    }
-
-    Method(SPED, 1, Serialized) {
-      OperationRegion(PGRF, SystemMemory, 0xfd5b0070, 0x4)
-      Field(PGRF, DWordAcc,Lock, Preserve) {
-        CLK1, 32,
-      }
-
-      if (LEqual(Arg0, 1000)) {
-        Store(0x000c0000, CLK1)
-      }
-
-      if (LEqual(Arg0, 100)) {
-        Store(0x000c000c, CLK1)
-      }
-
-      if (LEqual(Arg0, 10)) {
-        Store(0x000c0008, CLK1)
-      }
-    }
-
-    Method(CLKS, 2, Serialized) {
-      OperationRegion(PGRF, SystemMemory, 0xfd5b0070, 0x4)
-      Field(PGRF, DWordAcc,Lock, Preserve) {
-        CLK1, 32,
-      }
-
-      if (LEqual(Arg0, 0)) {
-        Store(0x00100010, CLK1)
-      }
-
-      if (LEqual(Arg1, 1)) {
-        Store(0x00020000, CLK1)
-      }
-    }
-
-    Device (AST0)
-    {
-      Name (_DSD, Package() {
-        ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
-        Package () {
-          Package () { "snps,wr_osr_lmt", 4 },
-          Package () { "snps,rd_osr_lmt", 8 },
-          Package () { "snps,blen", package () { 0, 0, 0, 0, 16, 8, 4 }, },
-        }
-      })
-    }
-
-    Device (MRX0)
-    {
-      Name (_DSD, Package() {
-        ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
-        Package () {
-          Package () { "snps,rx-queues-to-use", 2 },
-        }
-      })
-
-      Device (rxq0) {
-        Name (_ADR, 0)
-      }
-
-      Device (rxq1) {
-        Name (_ADR, 1)
-      }
-    }
-
-    Device (MTX0)
-    {
-      Name (_DSD, Package() {
-        ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
-        Package () {
-          Package () { "snps,tx-queues-to-use", 2 },
-        }
-      })
-
-      Device (txq0) {
-        Name (_ADR, 0)
-      }
-
-      Device (txq1) {
-        Name (_ADR, 1)
-      }
-    }
-
-    Device (MDIO)
-    {
-      Name (_HID, "PRP0001")
-      Name (_UID, 0)
-
-      Name (_DSD, Package () {
-        ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
-        Package () {
-          Package () { "compatible", "snps,dwmac-mdio" },
-          Package () { "#address-cells", 1},
-        }
-      })
-
-      Device (PHY0)
-      {
-        Name (_HID, "PRP0001")
-        Name (_UID, 0)
-        Name (_ADR, 1)
-
-        Name (_DSD, Package () {
-          ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
-          Package () {
-            Package () { "compatible", "ethernet-phy-ieee802.3-c22" },
-            Package () { "reg", 1},
-          }
-        })
-      }
-    }
-  }
diff --git a/edk2-rockchip/Silicon/Rockchip/RK3588/AcpiTables/Gmac0.asl b/edk2-rockchip/Silicon/Rockchip/RK3588/AcpiTables/Gmac0.asl
new file mode 100644
index 000000000..8b3ad0e26
--- /dev/null
+++ b/edk2-rockchip/Silicon/Rockchip/RK3588/AcpiTables/Gmac0.asl
@@ -0,0 +1,46 @@
+/** @file
+ *
+ *  Copyright (c) 2022, Jared McNeill <jmcneill@invisible.ca>
+ *  Copyright (c) 2023, Mario Bălănică <mariobalanica02@gmail.com>
+ *
+ *  SPDX-License-Identifier: BSD-2-Clause-Patent
+ *
+ **/
+
+#include "AcpiTables.h"
+
+// Gigabit Media Access Controller (GMAC0)
+Device (MAC0) {
+  Name (_HID, "PRP0001")
+  Name (_UID, 0)
+  Name (_CCA, 0)
+  Name (_STA, 0xF)
+
+  Method (_CRS, 0x0, Serialized) {
+    Name (RBUF, ResourceTemplate() {
+      Memory32Fixed (ReadWrite, 0xfe1b0000, 0x10000)
+      Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive) { 259, 258 }
+    })
+    Return (RBUF)
+  }
+
+  Name (_DSD, Package () {
+    ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
+    Package () {
+      Package () { "compatible", Package () { "snps,dwmac-4.20a", "snps,dwmac" } },
+      Package () { "interrupt-names", Package () { "macirq", "eth_wake_irq" } },
+      Package () { "snps,mixed-burst", 1 },
+      Package () { "snps,tso", 1 },
+      Package () { "snps,axi-config", "AXIC" },
+    }
+  })
+
+  Name (AXIC, Package () {
+    ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
+    Package () {
+      Package () { "snps,wr_osr_lmt", 4 },
+      Package () { "snps,rd_osr_lmt", 8 },
+      Package () { "snps,blen", Package () { 0, 0, 0, 0, 16, 8, 4 } },
+    }
+  })
+}
diff --git a/edk2-rockchip/Silicon/Rockchip/RK3588/AcpiTables/Gmac1.asl b/edk2-rockchip/Silicon/Rockchip/RK3588/AcpiTables/Gmac1.asl
new file mode 100644
index 000000000..12bf67755
--- /dev/null
+++ b/edk2-rockchip/Silicon/Rockchip/RK3588/AcpiTables/Gmac1.asl
@@ -0,0 +1,46 @@
+/** @file
+ *
+ *  Copyright (c) 2022, Jared McNeill <jmcneill@invisible.ca>
+ *  Copyright (c) 2023, Mario Bălănică <mariobalanica02@gmail.com>
+ *
+ *  SPDX-License-Identifier: BSD-2-Clause-Patent
+ *
+ **/
+
+#include "AcpiTables.h"
+
+// Gigabit Media Access Controller (GMAC1)
+Device (MAC1) {
+  Name (_HID, "PRP0001")
+  Name (_UID, 1)
+  Name (_CCA, 0)
+  Name (_STA, 0xF)
+
+  Method (_CRS, 0x0, Serialized) {
+    Name (RBUF, ResourceTemplate() {
+      Memory32Fixed (ReadWrite, 0xfe1c0000, 0x10000)
+      Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive) { 266, 265 }
+    })
+    Return (RBUF)
+  }
+
+  Name (_DSD, Package () {
+    ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
+    Package () {
+      Package () { "compatible", Package () { "snps,dwmac-4.20a", "snps,dwmac" } },
+      Package () { "interrupt-names", Package () { "macirq", "eth_wake_irq" } },
+      Package () { "snps,mixed-burst", 1 },
+      Package () { "snps,tso", 1 },
+      Package () { "snps,axi-config", "AXIC" },
+    }
+  })
+
+  Name (AXIC, Package () {
+    ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
+    Package () {
+      Package () { "snps,wr_osr_lmt", 4 },
+      Package () { "snps,rd_osr_lmt", 8 },
+      Package () { "snps,blen", Package () { 0, 0, 0, 0, 16, 8, 4 } },
+    }
+  })
+}
diff --git a/edk2-rockchip/Silicon/Rockchip/RK3588/Drivers/GmacPlatformDxe/EthernetPhy.h b/edk2-rockchip/Silicon/Rockchip/RK3588/Drivers/GmacPlatformDxe/EthernetPhy.h
new file mode 100644
index 000000000..367b10520
--- /dev/null
+++ b/edk2-rockchip/Silicon/Rockchip/RK3588/Drivers/GmacPlatformDxe/EthernetPhy.h
@@ -0,0 +1,50 @@
+/** @file
+ *
+ *  Copyright (c) 2022, Jared McNeill <jmcneill@invisible.ca>
+ *  Copyright (c) 2023, Mario Bălănică <mariobalanica02@gmail.com>
+ *
+ *  SPDX-License-Identifier: BSD-2-Clause-Patent
+ *
+ **/
+
+#ifndef ETHERNETPHY_H__
+#define ETHERNETPHY_H__
+
+typedef
+EFI_STATUS
+(EFIAPI *ETHERNET_PHY_INIT) (
+  IN EFI_PHYSICAL_ADDRESS   GmacBase,
+  IN UINT32                 PhyId
+  );
+
+VOID
+PhyRead (
+  IN  EFI_PHYSICAL_ADDRESS   GmacBase,
+  IN  UINT8                  Phy,
+  IN  UINT16                 Reg,
+  OUT UINT16                 *Value
+  );
+
+VOID
+PhyWrite (
+  IN EFI_PHYSICAL_ADDRESS   GmacBase,
+  IN UINT8                  Phy,
+  IN UINT16                 Reg,
+  IN UINT16                 Value
+  );
+
+EFI_STATUS
+EFIAPI
+RealtekPhyInit (
+  IN EFI_PHYSICAL_ADDRESS  GmacBase,
+  IN UINT32                PhyId
+  );
+
+EFI_STATUS
+EFIAPI
+MotorcommPhyInit (
+  IN EFI_PHYSICAL_ADDRESS  GmacBase,
+  IN UINT32                PhyId
+  );
+
+#endif /* ETHERNETPHY_H__ */
diff --git a/edk2-rockchip/Silicon/Rockchip/RK3588/Drivers/GmacPlatformDxe/GmacPlatformDxe.c b/edk2-rockchip/Silicon/Rockchip/RK3588/Drivers/GmacPlatformDxe/GmacPlatformDxe.c
new file mode 100644
index 000000000..a3f2307dc
--- /dev/null
+++ b/edk2-rockchip/Silicon/Rockchip/RK3588/Drivers/GmacPlatformDxe/GmacPlatformDxe.c
@@ -0,0 +1,309 @@
+/** @file
+ *
+ *  RK3588 GMAC initializer
+ *
+ *  Copyright (c) 2021-2022, Jared McNeill <jmcneill@invisible.ca>
+ *  Copyright (c) 2023, Mario Bălănică <mariobalanica02@gmail.com>
+ *
+ *  SPDX-License-Identifier: BSD-2-Clause-Patent
+ *
+ **/
+
+#include <Library/DebugLib.h>
+#include <Library/IoLib.h>
+#include <Library/TimerLib.h>
+#include <Library/BaseCryptLib.h>
+#include <Library/OtpLib.h>
+#include <Library/RockchipPlatformLib.h>
+#include <Soc.h>
+
+#include <EthernetPhy.h>
+
+#define CRU_SOFTRST_CON32       (CRU_BASE + 0x0A80)
+
+#define PHP_GRF_BASE            0xFD5B0000
+#define PHP_GRF_CLK_CON1        (PHP_GRF_BASE + 0x0070)
+#define PHP_GRF_GMAC_CON0       (PHP_GRF_BASE + 0x0008)
+
+#define SYS_GRF_BASE            0xFD58C000
+#define SYS_GRF_SOC_CON7        (SYS_GRF_BASE + 0x031C)
+#define SYS_GRF_SOC_CON8        (SYS_GRF_BASE + 0x0320)
+#define SYS_GRF_SOC_CON9        (SYS_GRF_BASE + 0x0324)
+#define  CLK_RX_DL_CFG_SHIFT    8
+#define  CLK_TX_DL_CFG_SHIFT    0
+
+#define TX_DELAY_GMAC0          FixedPcdGet8 (PcdGmac0TxDelay)
+#define RX_DELAY_GMAC0          FixedPcdGet8 (PcdGmac0RxDelay)
+#define TX_DELAY_GMAC1          FixedPcdGet8 (PcdGmac1TxDelay)
+#define RX_DELAY_GMAC1          FixedPcdGet8 (PcdGmac1RxDelay)
+
+#define GMAC0_BASE                         0xfe1b0000
+#define GMAC1_BASE                         0xfe1c0000
+
+/* GMAC registers */
+#define  GMAC_MAC_MDIO_ADDRESS               0x0200
+#define   GMAC_MAC_MDIO_ADDRESS_PA_SHIFT     21
+#define   GMAC_MAC_MDIO_ADDRESS_RDA_SHIFT    16
+#define   GMAC_MAC_MDIO_ADDRESS_CR_SHIFT     8
+#define   GMAC_MAC_MDIO_ADDRESS_CR_100_150   (1U << GMAC_MAC_MDIO_ADDRESS_CR_SHIFT)
+#define   GMAC_MAC_MDIO_ADDRESS_GOC_SHIFT    2
+#define   GMAC_MAC_MDIO_ADDRESS_GOC_READ     (3U << GMAC_MAC_MDIO_ADDRESS_GOC_SHIFT)
+#define   GMAC_MAC_MDIO_ADDRESS_GOC_WRITE    (1U << GMAC_MAC_MDIO_ADDRESS_GOC_SHIFT)
+#define   GMAC_MAC_MDIO_ADDRESS_GB           BIT0
+#define  GMAC_MAC_MDIO_DATA                  0x0204
+
+#define GMAC_MAC_ADDRESS0_LOW               0x0304
+#define GMAC_MAC_ADDRESS0_HIGH              0x0300
+
+/* MII registers */
+#define MII_PHYIDR1                         0x02
+#define MII_PHYIDR2                         0x03
+
+STATIC ETHERNET_PHY_INIT mPhyInitList[] = {
+  RealtekPhyInit,
+  MotorcommPhyInit
+};
+
+VOID
+PhyRead (
+  IN  EFI_PHYSICAL_ADDRESS  GmacBase,
+  IN  UINT8                 Phy,
+  IN  UINT16                Reg,
+  OUT UINT16                *Value
+  )
+{
+  UINT32 Addr;
+  UINTN Retry;
+
+  Addr = GMAC_MAC_MDIO_ADDRESS_CR_100_150 |
+          (Phy << GMAC_MAC_MDIO_ADDRESS_PA_SHIFT) |
+          (Reg << GMAC_MAC_MDIO_ADDRESS_RDA_SHIFT) |
+          GMAC_MAC_MDIO_ADDRESS_GOC_READ |
+          GMAC_MAC_MDIO_ADDRESS_GB;
+  MmioWrite32 (GmacBase + GMAC_MAC_MDIO_ADDRESS, Addr);
+
+  MicroSecondDelay (10000);
+
+  for (Retry = 1000; Retry > 0; Retry--) {
+    Addr = MmioRead32 (GmacBase + GMAC_MAC_MDIO_ADDRESS);
+    if ((Addr & GMAC_MAC_MDIO_ADDRESS_GB) == 0) {
+      *Value = MmioRead32 (GmacBase + GMAC_MAC_MDIO_DATA) & 0xFFFFu;
+      break;
+    }
+    MicroSecondDelay (10);
+  }
+  if (Retry == 0) {
+    DEBUG ((DEBUG_WARN, "MDIO: PHY read timeout!\n"));
+    *Value = 0xFFFFU;
+    ASSERT (FALSE);
+  }
+}
+
+VOID
+PhyWrite (
+  IN EFI_PHYSICAL_ADDRESS   GmacBase,
+  IN UINT8                  Phy,
+  IN UINT16                 Reg,
+  IN UINT16                 Value
+  )
+{
+  UINT32 Addr;
+  UINTN Retry;
+
+  MmioWrite32 (GmacBase + GMAC_MAC_MDIO_DATA, Value);
+
+  Addr = GMAC_MAC_MDIO_ADDRESS_CR_100_150 |
+          (Phy << GMAC_MAC_MDIO_ADDRESS_PA_SHIFT) |
+          (Reg << GMAC_MAC_MDIO_ADDRESS_RDA_SHIFT) |
+          GMAC_MAC_MDIO_ADDRESS_GOC_WRITE |
+          GMAC_MAC_MDIO_ADDRESS_GB;
+  MmioWrite32 (GmacBase + GMAC_MAC_MDIO_ADDRESS, Addr);
+
+  MicroSecondDelay (10000);
+
+  for (Retry = 1000; Retry > 0; Retry--) {
+    Addr = MmioRead32 (GmacBase + GMAC_MAC_MDIO_ADDRESS);
+    if ((Addr & GMAC_MAC_MDIO_ADDRESS_GB) == 0) {
+      break;
+    }
+    MicroSecondDelay (10);
+  }
+  if (Retry == 0) {
+    DEBUG ((DEBUG_WARN, "MDIO: PHY write timeout!\n"));
+    ASSERT (FALSE);
+  }
+}
+
+STATIC
+VOID
+EFIAPI
+PhyInit (
+  IN EFI_PHYSICAL_ADDRESS GmacBase
+  )
+{
+  EFI_STATUS Status;
+  UINT16 PhyIdReg;
+  UINT32 PhyId;
+  UINT32 Index;
+
+  PhyRead (GmacBase, 0, MII_PHYIDR1, &PhyIdReg);
+  PhyId = PhyIdReg << 16;
+  PhyRead (GmacBase, 0, MII_PHYIDR2, &PhyIdReg);
+  PhyId |= PhyIdReg;
+
+  for (Index = 0; Index < ARRAY_SIZE (mPhyInitList); Index++) {
+    Status = mPhyInitList[Index] (GmacBase, PhyId);
+    if (Status == EFI_UNSUPPORTED) {
+      continue;
+    } else if (EFI_ERROR (Status)) {
+      DEBUG ((DEBUG_ERROR, "%a: mPhyInitList[%d]() failed: %r\n", __func__, Index, Status));
+    }
+    return;
+  }
+
+  DEBUG ((DEBUG_ERROR, "%a: Unknown PHY ID %08X\n", __func__, PhyId));
+}
+
+STATIC
+VOID
+EFIAPI
+InitGmac0 (
+  VOID
+  )
+{
+  /* Assert reset */
+  MmioWrite32 (CRU_SOFTRST_CON32, 0x04000400); // aresetn_gmac0 = 1
+
+  /* Configure pins */
+  GmacIomux (0);
+
+  /* Setup clocks */
+  MmioWrite32 (PHP_GRF_CLK_CON1, 0x001d0000);  // io_clksel_gmac0 = io
+                                               // mii_tx_clk_sel_gamc0 = 125 MHz
+                                               // rmii_mode_gmac0 = RGMII mode
+
+  MmioWrite32 (PHP_GRF_GMAC_CON0, 0x00380008);  // gmac0_phy_intf_sel = RGMII
+
+  /* Setup DLLs */
+  if (TX_DELAY_GMAC0) {
+    MmioWrite32 (SYS_GRF_SOC_CON7, 0x00040004); // gmac0_txclk_dly_ena = 1
+    MmioWrite32 (SYS_GRF_SOC_CON8, 0x007F0000U |
+                  (TX_DELAY_GMAC0 << CLK_TX_DL_CFG_SHIFT));
+  }
+
+  if (RX_DELAY_GMAC0) {
+    MmioWrite32 (SYS_GRF_SOC_CON7, 0x00080008); // gmac0_rxclk_dly_ena = 1
+    MmioWrite32 (SYS_GRF_SOC_CON8, 0x7F000000U |
+                  (RX_DELAY_GMAC0 << CLK_RX_DL_CFG_SHIFT));
+  }
+
+  /* Reset PHY */
+  GmacIoPhyReset (0, TRUE);
+  MicroSecondDelay (20000);
+  GmacIoPhyReset (0, FALSE);
+  MicroSecondDelay (200000);
+
+  /* Deassert reset */
+  MmioWrite32 (CRU_SOFTRST_CON32, 0x04000000); // aresetn_gmac0 = 0
+
+  PhyInit (GMAC0_BASE);
+}
+
+STATIC
+VOID
+EFIAPI
+InitGmac1 (
+  VOID
+  )
+{
+  /* Assert reset */
+  MmioWrite32 (CRU_SOFTRST_CON32, 0x08000800); // aresetn_gmac1 = 1
+
+  /* Configure pins */
+  GmacIomux (1);
+
+  /* Setup clocks */
+  MmioWrite32 (PHP_GRF_CLK_CON1, 0x03a00000);  // io_clksel_gmac1 = io
+                                               // mii_tx_clk_sel_gamc1 = 125 MHz
+                                               // rmii_mode_gmac1 = RGMII mode
+
+  MmioWrite32 (PHP_GRF_GMAC_CON0, 0x0e000200);  // gmac1_phy_intf_sel = RGMII
+
+  /* Setup DLLs */
+  if (TX_DELAY_GMAC1) {
+    MmioWrite32 (SYS_GRF_SOC_CON7, 0x00100010); // gmac1_txclk_dly_ena = 1
+    MmioWrite32 (SYS_GRF_SOC_CON9, 0x007F0000U |
+                  (TX_DELAY_GMAC1 << CLK_TX_DL_CFG_SHIFT));
+  }
+
+  if (RX_DELAY_GMAC1) {
+    MmioWrite32 (SYS_GRF_SOC_CON7, 0x00200020); // gmac1_rxclk_dly_ena = 1
+    MmioWrite32 (SYS_GRF_SOC_CON9, 0x7F000000U |
+                  (RX_DELAY_GMAC1 << CLK_RX_DL_CFG_SHIFT));
+  }
+
+  /* Reset PHY */
+  GmacIoPhyReset (1, TRUE);
+  MicroSecondDelay (20000);
+  GmacIoPhyReset (1, FALSE);
+  MicroSecondDelay (200000);
+
+  /* Deassert reset */
+  MmioWrite32 (CRU_SOFTRST_CON32, 0x08000000); // aresetn_gmac1 = 0
+
+  PhyInit (GMAC1_BASE);
+}
+
+EFI_STATUS
+EFIAPI
+GmacPlatformDxeInitialize (
+  IN EFI_HANDLE          ImageHandle,
+  IN EFI_SYSTEM_TABLE    *SystemTable
+  )
+{
+  UINT8 OtpData[32];
+  UINT8 Hash[SHA256_DIGEST_SIZE];
+  UINT32 MacLo, MacHi;
+
+  if (!FixedPcdGetBool (PcdGmac0Supported)
+      && !FixedPcdGetBool (PcdGmac1Supported)) {
+    return EFI_SUCCESS;
+  }
+
+  /* Generate MAC addresses from the first 32 bytes in the OTP and write it to GMAC0 and GMAC1 */
+  /* Use sequential MAC addresses. Last byte is even for GMAC0, and odd for GMAC1. */
+  OtpRead (0x00, sizeof (OtpData), OtpData);
+  Sha256HashAll (OtpData, sizeof (OtpData), Hash);
+  Hash[0] &= 0xFE;
+  Hash[0] |= 0x02;
+
+  if (FixedPcdGetBool (PcdGmac0Supported)) {
+    InitGmac0 ();
+
+    Hash[5] &= ~1;
+    DEBUG ((DEBUG_INFO, "%a: GMAC0 MAC address: %02X:%02X:%02X:%02X:%02X:%02X\n",
+            __func__,
+            Hash[0], Hash[1], Hash[2],
+            Hash[3], Hash[4], Hash[5]));
+    MacLo = Hash[3] | (Hash[2] << 8) | (Hash[1] << 16) | (Hash[0] << 24);
+    MacHi = Hash[5] | (Hash[4] << 8);
+    MmioWrite32 (GMAC0_BASE + GMAC_MAC_ADDRESS0_LOW, MacLo);
+    MmioWrite32 (GMAC0_BASE + GMAC_MAC_ADDRESS0_HIGH, MacHi);
+  }
+
+  if (FixedPcdGetBool (PcdGmac1Supported)) {
+    InitGmac1 ();
+
+    Hash[5] |= 1;
+    DEBUG ((DEBUG_INFO, "%a: GMAC1 MAC address: %02X:%02X:%02X:%02X:%02X:%02X\n",
+            __func__,
+            Hash[0], Hash[1], Hash[2],
+            Hash[3], Hash[4], Hash[5]));
+    MacLo = Hash[3] | (Hash[2] << 8) | (Hash[1] << 16) | (Hash[0] << 24);
+    MacHi = Hash[5] | (Hash[4] << 8);
+    MmioWrite32 (GMAC1_BASE + GMAC_MAC_ADDRESS0_LOW, MacLo);
+    MmioWrite32 (GMAC1_BASE + GMAC_MAC_ADDRESS0_HIGH, MacHi);
+  }
+
+  return EFI_SUCCESS;
+}
diff --git a/edk2-rockchip/Silicon/Rockchip/RK3588/Drivers/GmacPlatformDxe/GmacPlatformDxe.inf b/edk2-rockchip/Silicon/Rockchip/RK3588/Drivers/GmacPlatformDxe/GmacPlatformDxe.inf
new file mode 100644
index 000000000..808e3e157
--- /dev/null
+++ b/edk2-rockchip/Silicon/Rockchip/RK3588/Drivers/GmacPlatformDxe/GmacPlatformDxe.inf
@@ -0,0 +1,51 @@
+#/** @file
+#
+#  RK3588 GMAC initializer
+#
+#  Copyright (c) 2023, Mario Bălănică <mariobalanica02@gmail.com>
+#
+#  SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+#**/
+
+[Defines]
+  INF_VERSION                    = 0x00010019
+  BASE_NAME                      = GmacPlatformDxe
+  FILE_GUID                      = e08592c7-55f6-4f90-be56-327356aa1462
+  MODULE_TYPE                    = DXE_DRIVER
+  VERSION_STRING                 = 1.0
+  ENTRY_POINT                    = GmacPlatformDxeInitialize
+
+[Sources.common]
+  GmacPlatformDxe.c
+  RealtekPhy.c
+  MotorcommPhy.c
+
+[Packages]
+  MdePkg/MdePkg.dec
+  MdeModulePkg/MdeModulePkg.dec
+  CryptoPkg/CryptoPkg.dec
+  Silicon/Rockchip/RockchipPkg.dec
+  Silicon/Rockchip/RK3588/RK3588.dec
+
+[LibraryClasses]
+  UefiDriverEntryPoint
+  DebugLib
+  IoLib
+  TimerLib
+  BaseCryptLib
+  OtpLib
+  RockchipPlatformLib
+
+[Protocols]
+
+[Pcd]
+  gRK3588TokenSpaceGuid.PcdGmac0Supported
+  gRK3588TokenSpaceGuid.PcdGmac1Supported
+  gRK3588TokenSpaceGuid.PcdGmac0TxDelay
+  gRK3588TokenSpaceGuid.PcdGmac0RxDelay
+  gRK3588TokenSpaceGuid.PcdGmac1TxDelay
+  gRK3588TokenSpaceGuid.PcdGmac1RxDelay
+
+[Depex]
+  TRUE
diff --git a/edk2-rockchip/Silicon/Rockchip/RK3588/Drivers/GmacPlatformDxe/MotorcommPhy.c b/edk2-rockchip/Silicon/Rockchip/RK3588/Drivers/GmacPlatformDxe/MotorcommPhy.c
new file mode 100644
index 000000000..cbb5ab0e6
--- /dev/null
+++ b/edk2-rockchip/Silicon/Rockchip/RK3588/Drivers/GmacPlatformDxe/MotorcommPhy.c
@@ -0,0 +1,97 @@
+/** @file
+ *
+ *  Copyright (c) 2022, Jared McNeill <jmcneill@invisible.ca>
+ *  Copyright (c) 2023, Mario Bălănică <mariobalanica02@gmail.com>
+ *
+ *  SPDX-License-Identifier: BSD-2-Clause-Patent
+ *
+ **/
+
+#include <Base.h>
+#include <Library/DebugLib.h>
+#include <Library/TimerLib.h>
+
+#include "EthernetPhy.h"
+
+/* Motorcomm PHY registers */
+#define EXT_REG_ADDR                  0x1E
+#define EXT_REG_DATA                  0x1F
+#define PHY_CLOCK_GATING_REG          0x0C
+#define  RX_CLK_EN                    BIT12
+#define  TX_CLK_DELAY_SEL_SHIFT       4
+#define  TX_CLK_DELAY_SEL             (0xFU << TX_CLK_DELAY_SEL_SHIFT)
+#define  CLK_25M_SEL_SHIFT            1
+#define  CLK_25M_SEL_MASK             (0x3U << CLK_25M_SEL_SHIFT)
+#define  CLK_25M_SEL_125M             (3U << CLK_25M_SEL_SHIFT)
+#define  RX_CLK_DELAY_EN              BIT0
+#define PHY_SLEEP_CONTROL1_REG        0x27
+#define  SLEEP_SW                     BIT15
+#define  PLLON_IN_SLP                 BIT14
+
+#define YTPHY_SYNCE_CFG_REG                 0xA012
+#define  YT8531_SCR_SYNCE_ENABLE            BIT6
+#define  YT8531_SCR_CLK_FRE_SEL_125M        BIT4
+#define  YT8531_SCR_CLK_SRC_SEL_SHIFT       1
+#define  YT8531_SCR_CLK_SRC_SEL_PLL_125M    (0 << YT8531_SCR_CLK_SRC_SEL_SHIFT)
+
+#define LED1_CFG_REG            0xA00D
+#define LED2_CFG_REG            0xA00E
+#define LED_BLINK_CFG_REG       0xA00F
+
+STATIC
+VOID
+YT8531PhyInit (
+  IN EFI_PHYSICAL_ADDRESS GmacBase
+  )
+{
+  UINT16 OldAddr;
+  UINT16 Data;
+
+  PhyRead (GmacBase, 0, EXT_REG_ADDR, &OldAddr);
+
+  PhyWrite (GmacBase, 0, EXT_REG_ADDR, YTPHY_SYNCE_CFG_REG);
+  PhyWrite (GmacBase, 0, EXT_REG_DATA, YT8531_SCR_SYNCE_ENABLE |
+                                       YT8531_SCR_CLK_FRE_SEL_125M |
+                                       YT8531_SCR_CLK_SRC_SEL_PLL_125M);
+
+  PhyWrite (GmacBase, 0, EXT_REG_ADDR, PHY_CLOCK_GATING_REG);
+  PhyRead (GmacBase, 0, EXT_REG_DATA, &Data);
+  Data &= ~RX_CLK_EN;
+  Data &= ~CLK_25M_SEL_MASK;
+  Data |= CLK_25M_SEL_125M;
+  PhyWrite (GmacBase, 0, EXT_REG_DATA, Data);
+
+  PhyWrite (GmacBase, 0, EXT_REG_ADDR, PHY_SLEEP_CONTROL1_REG);
+  PhyRead (GmacBase, 0, EXT_REG_DATA, &Data);
+  Data &= ~SLEEP_SW;
+  PhyWrite (GmacBase, 0, EXT_REG_DATA, Data);
+
+  PhyWrite (GmacBase, 0, EXT_REG_ADDR, LED1_CFG_REG);
+  PhyWrite (GmacBase, 0, EXT_REG_DATA, 0x0670);
+
+  PhyWrite (GmacBase, 0, EXT_REG_ADDR, LED2_CFG_REG);
+  PhyWrite (GmacBase, 0, EXT_REG_DATA, 0x2070);
+
+  PhyWrite (GmacBase, 0, EXT_REG_ADDR, LED_BLINK_CFG_REG);
+  PhyWrite (GmacBase, 0, EXT_REG_DATA, 0x007e);
+
+  PhyWrite (GmacBase, 0, EXT_REG_ADDR, OldAddr);
+}
+
+EFI_STATUS
+EFIAPI
+MotorcommPhyInit (
+  IN EFI_PHYSICAL_ADDRESS  GmacBase,
+  IN UINT32                PhyId
+  )
+{
+  switch (PhyId) {
+    case 0x4F51E91B:
+      DEBUG ((DEBUG_INFO, "%a: Found Motorcomm YT8531 GbE PHY\n", __func__));
+      YT8531PhyInit (GmacBase);
+      break;
+    default:
+      return EFI_UNSUPPORTED;
+  }
+  return EFI_SUCCESS;
+}
diff --git a/edk2-rockchip/Silicon/Rockchip/RK3588/Drivers/GmacPlatformDxe/RealtekPhy.c b/edk2-rockchip/Silicon/Rockchip/RK3588/Drivers/GmacPlatformDxe/RealtekPhy.c
new file mode 100644
index 000000000..5581112c3
--- /dev/null
+++ b/edk2-rockchip/Silicon/Rockchip/RK3588/Drivers/GmacPlatformDxe/RealtekPhy.c
@@ -0,0 +1,53 @@
+/** @file
+ *
+ *  Copyright (c) 2022, Jared McNeill <jmcneill@invisible.ca>
+ *  Copyright (c) 2023, Mario Bălănică <mariobalanica02@gmail.com>
+ *
+ *  SPDX-License-Identifier: BSD-2-Clause-Patent
+ *
+ **/
+
+#include <Base.h>
+#include <Library/DebugLib.h>
+#include <Library/TimerLib.h>
+
+#include "EthernetPhy.h"
+
+/* Realtek RTL8211F PHY registers */
+#define PAGSR               0x1F
+#define LCR                 0x10
+#define LCR_VALUE           0x6940
+
+STATIC
+VOID
+RTL8211FPhyInit (
+  IN EFI_PHYSICAL_ADDRESS GmacBase
+  )
+{
+  PhyWrite (GmacBase, 0, PAGSR, 0xD04);
+  MicroSecondDelay (10000);
+  PhyWrite (GmacBase, 0, LCR, LCR_VALUE);
+  MicroSecondDelay (10000);
+  PhyWrite (GmacBase, 0, PAGSR, 0);
+}
+
+EFI_STATUS
+EFIAPI
+RealtekPhyInit (
+  IN EFI_PHYSICAL_ADDRESS  GmacBase,
+  IN UINT32                PhyId
+  )
+{
+  switch (PhyId) {
+    case 0x001CC916:
+      DEBUG ((DEBUG_INFO, "%a: Found Realtek RTL8211F GbE PHY\n", __func__));
+      RTL8211FPhyInit (GmacBase);
+      break;
+    case 0x001CC878:
+      DEBUG ((DEBUG_INFO, "%a: Found Realtek RTL8211F-VD GbE PHY\n", __func__));
+      RTL8211FPhyInit (GmacBase);
+    default:
+      return EFI_UNSUPPORTED;
+  }
+  return EFI_SUCCESS;
+}
diff --git a/edk2-rockchip/Silicon/Rockchip/RK3588/Drivers/RK3588Dxe/RK3588Dxe.c b/edk2-rockchip/Silicon/Rockchip/RK3588/Drivers/RK3588Dxe/RK3588Dxe.c
index c1ee31096..95059d4c6 100644
--- a/edk2-rockchip/Silicon/Rockchip/RK3588/Drivers/RK3588Dxe/RK3588Dxe.c
+++ b/edk2-rockchip/Silicon/Rockchip/RK3588/Drivers/RK3588Dxe/RK3588Dxe.c
@@ -258,16 +258,6 @@ MtcmosInit (
   //} while ((Data & PW_EN0_G3D) == 0);
 }
 
-STATIC
-VOID
-GmacIomuxInit (
-  IN VOID
-  )
-{
-  DEBUG((DEBUG_INIT, "RK3588InitPeripherals: GmacIomuxInit()\n"));
-  GmacIomux(0);
-}
-
 EFI_STATUS
 RK3588InitPeripherals (
   IN VOID
@@ -292,8 +282,6 @@ RK3588InitPeripherals (
 
   Rk806Configure();
 
-  GmacIomuxInit();
-
   return EFI_SUCCESS;
 }
 
diff --git a/edk2-rockchip/Silicon/Rockchip/RK3588/RK3588.dec b/edk2-rockchip/Silicon/Rockchip/RK3588/RK3588.dec
index eacd020d8..9b130b135 100644
--- a/edk2-rockchip/Silicon/Rockchip/RK3588/RK3588.dec
+++ b/edk2-rockchip/Silicon/Rockchip/RK3588/RK3588.dec
@@ -52,6 +52,13 @@
   gRK3588TokenSpaceGuid.PcdDp0LaneMux|{ 0x0 }|VOID*|0x00010503
   gRK3588TokenSpaceGuid.PcdDp1LaneMux|{ 0x0 }|VOID*|0x00010504
 
+  gRK3588TokenSpaceGuid.PcdGmac0Supported|FALSE|BOOLEAN|0x00010601
+  gRK3588TokenSpaceGuid.PcdGmac1Supported|FALSE|BOOLEAN|0x00010602
+  gRK3588TokenSpaceGuid.PcdGmac0TxDelay|0|UINT8|0x00010603
+  gRK3588TokenSpaceGuid.PcdGmac0RxDelay|0|UINT8|0x00010604
+  gRK3588TokenSpaceGuid.PcdGmac1TxDelay|0|UINT8|0x00010605
+  gRK3588TokenSpaceGuid.PcdGmac1RxDelay|0|UINT8|0x00010606
+
 [PcdsFixedAtBuild, PcdsPatchableInModule, PcdsDynamic, PcdsDynamicEx]
   gRK3588TokenSpaceGuid.PcdCPULClusterClockPreset|0|UINT32|0x00000001
   gRK3588TokenSpaceGuid.PcdCPULClusterClockCustom|0|UINT32|0x00000002
diff --git a/edk2-rockchip/Silicon/Rockchip/RK3588/RK3588.fdf b/edk2-rockchip/Silicon/Rockchip/RK3588/RK3588.fdf
index f367d68dc..28d193325 100644
--- a/edk2-rockchip/Silicon/Rockchip/RK3588/RK3588.fdf
+++ b/edk2-rockchip/Silicon/Rockchip/RK3588/RK3588.fdf
@@ -126,6 +126,11 @@ READ_LOCK_STATUS   = TRUE
   #
   INF Silicon/Rockchip/RK3588/Drivers/UsbDpPhyDxe/UsbDpPhyDxe.inf
 
+  #
+  # GMAC Init Driver
+  #
+  INF Silicon/Rockchip/RK3588/Drivers/GmacPlatformDxe/GmacPlatformDxe.inf
+
   #
   # Custom platform components
   #
diff --git a/edk2-rockchip/Silicon/Rockchip/RK3588/RK3588Base.dsc.inc b/edk2-rockchip/Silicon/Rockchip/RK3588/RK3588Base.dsc.inc
index b2935892a..045001190 100644
--- a/edk2-rockchip/Silicon/Rockchip/RK3588/RK3588Base.dsc.inc
+++ b/edk2-rockchip/Silicon/Rockchip/RK3588/RK3588Base.dsc.inc
@@ -334,3 +334,8 @@
   # USB/DP PHY Driver
   #
   Silicon/Rockchip/RK3588/Drivers/UsbDpPhyDxe/UsbDpPhyDxe.inf
+
+  #
+  # GMAC Init Driver
+  #
+  Silicon/Rockchip/RK3588/Drivers/GmacPlatformDxe/GmacPlatformDxe.inf