diff --git a/configs/h88k.conf b/configs/h88k.conf
new file mode 100644
index 000000000..cb71fdc4c
--- /dev/null
+++ b/configs/h88k.conf
@@ -0,0 +1,3 @@
+DSC_FILE=edk2-rockchip/Platform/Hinlink/H88K/H88K.dsc
+PLATFORM_NAME=H88K
+SOC=RK3588
diff --git a/edk2-rockchip/Platform/Hinlink/Drivers/LogoDxe/Logo.bmp b/edk2-rockchip/Platform/Hinlink/Drivers/LogoDxe/Logo.bmp
new file mode 100644
index 000000000..9c393fd5d
Binary files /dev/null and b/edk2-rockchip/Platform/Hinlink/Drivers/LogoDxe/Logo.bmp differ
diff --git a/edk2-rockchip/Platform/Hinlink/Drivers/LogoDxe/Logo.c b/edk2-rockchip/Platform/Hinlink/Drivers/LogoDxe/Logo.c
new file mode 100644
index 000000000..2255b11ea
--- /dev/null
+++ b/edk2-rockchip/Platform/Hinlink/Drivers/LogoDxe/Logo.c
@@ -0,0 +1,144 @@
+/** @file
+ Logo DXE Driver, install Edkii Platform Logo protocol.
+
+ Copyright (c) 2016 - 2017, Intel Corporation. All rights reserved.
+ Copyright (c) 2018, Linaro, Ltd. All rights reserved.
+ Copyright (c) 2022 Rockchip Electronics Co. Ltd.
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+typedef struct {
+ EFI_IMAGE_ID ImageId;
+ EDKII_PLATFORM_LOGO_DISPLAY_ATTRIBUTE Attribute;
+ INTN OffsetX;
+ INTN OffsetY;
+} LOGO_ENTRY;
+
+STATIC EFI_HII_IMAGE_EX_PROTOCOL *mHiiImageEx;
+STATIC EFI_HII_HANDLE mHiiHandle;
+STATIC LOGO_ENTRY mLogos[] = {
+ {
+ IMAGE_TOKEN (IMG_LOGO),
+ EdkiiPlatformLogoDisplayAttributeCenter,
+ 0,
+ 0
+ }
+};
+
+/**
+ Load a platform logo image and return its data and attributes.
+
+ @param This The pointer to this protocol instance.
+ @param Instance The visible image instance is found.
+ @param Image Points to the image.
+ @param Attribute The display attributes of the image returned.
+ @param OffsetX The X offset of the image regarding the Attribute.
+ @param OffsetY The Y offset of the image regarding the Attribute.
+
+ @retval EFI_SUCCESS The image was fetched successfully.
+ @retval EFI_NOT_FOUND The specified image could not be found.
+**/
+STATIC
+EFI_STATUS
+EFIAPI
+GetImage (
+ IN EDKII_PLATFORM_LOGO_PROTOCOL *This,
+ IN OUT UINT32 *Instance,
+ OUT EFI_IMAGE_INPUT *Image,
+ OUT EDKII_PLATFORM_LOGO_DISPLAY_ATTRIBUTE *Attribute,
+ OUT INTN *OffsetX,
+ OUT INTN *OffsetY
+ )
+{
+ UINT32 Current;
+
+ if (Instance == NULL || Image == NULL ||
+ Attribute == NULL || OffsetX == NULL || OffsetY == NULL) {
+ return EFI_INVALID_PARAMETER;
+ }
+
+ Current = *Instance;
+ if (Current >= ARRAY_SIZE (mLogos)) {
+ return EFI_NOT_FOUND;
+ }
+
+ (*Instance)++;
+ *Attribute = mLogos[Current].Attribute;
+ *OffsetX = mLogos[Current].OffsetX;
+ *OffsetY = mLogos[Current].OffsetY;
+
+ return mHiiImageEx->GetImageEx (mHiiImageEx, mHiiHandle,
+ mLogos[Current].ImageId, Image);
+}
+
+STATIC EDKII_PLATFORM_LOGO_PROTOCOL mPlatformLogo = {
+ GetImage
+};
+
+/**
+ Entrypoint of this module.
+
+ This function is the entrypoint of this module. It installs the Edkii
+ Platform Logo protocol.
+
+ @param ImageHandle The firmware allocated handle for the EFI image.
+ @param SystemTable A pointer to the EFI System Table.
+
+ @retval EFI_SUCCESS The entry point is executed successfully.
+
+**/
+EFI_STATUS
+EFIAPI
+InitializeLogo (
+ IN EFI_HANDLE ImageHandle,
+ IN EFI_SYSTEM_TABLE *SystemTable
+ )
+{
+ EFI_STATUS Status;
+ EFI_HII_PACKAGE_LIST_HEADER *PackageList;
+ EFI_HII_DATABASE_PROTOCOL *HiiDatabase;
+ EFI_HANDLE Handle;
+
+ Status = gBS->LocateProtocol (&gEfiHiiDatabaseProtocolGuid, NULL,
+ (VOID **) &HiiDatabase);
+ ASSERT_EFI_ERROR (Status);
+
+ Status = gBS->LocateProtocol (&gEfiHiiImageExProtocolGuid, NULL,
+ (VOID **) &mHiiImageEx);
+ ASSERT_EFI_ERROR (Status);
+
+ //
+ // Retrieve HII package list from ImageHandle
+ //
+ Status = gBS->OpenProtocol (ImageHandle, &gEfiHiiPackageListProtocolGuid,
+ (VOID **) &PackageList, ImageHandle, NULL,
+ EFI_OPEN_PROTOCOL_GET_PROTOCOL);
+ if (EFI_ERROR (Status)) {
+ DEBUG ((DEBUG_ERROR,
+ "HII Image Package with logo not found in PE/COFF resource section\n"));
+ return Status;
+ }
+
+ //
+ // Publish HII package list to HII Database.
+ //
+ Status = HiiDatabase->NewPackageList (HiiDatabase, PackageList, NULL,
+ &mHiiHandle);
+ if (!EFI_ERROR (Status)) {
+ Handle = NULL;
+ Status = gBS->InstallMultipleProtocolInterfaces (&Handle,
+ &gEdkiiPlatformLogoProtocolGuid, &mPlatformLogo, NULL);
+ }
+ return Status;
+}
diff --git a/edk2-rockchip/Platform/Hinlink/Drivers/LogoDxe/Logo.idf b/edk2-rockchip/Platform/Hinlink/Drivers/LogoDxe/Logo.idf
new file mode 100644
index 000000000..c2d909624
--- /dev/null
+++ b/edk2-rockchip/Platform/Hinlink/Drivers/LogoDxe/Logo.idf
@@ -0,0 +1,10 @@
+// @file
+// Platform Logo image definition file.
+//
+// Copyright (c) 2018, Linaro, Ltd. All rights reserved.
+// Copyright (c) 2022 Rockchip Electronics Co. Ltd.
+//
+// SPDX-License-Identifier: BSD-2-Clause-Patent
+//
+
+#image IMG_LOGO Logo.bmp
diff --git a/edk2-rockchip/Platform/Hinlink/Drivers/LogoDxe/LogoDxe.inf b/edk2-rockchip/Platform/Hinlink/Drivers/LogoDxe/LogoDxe.inf
new file mode 100644
index 000000000..e7a35de10
--- /dev/null
+++ b/edk2-rockchip/Platform/Hinlink/Drivers/LogoDxe/LogoDxe.inf
@@ -0,0 +1,48 @@
+## @file
+# The default logo bitmap picture shown on setup screen.
+#
+# Copyright (c) 2016 - 2017, Intel Corporation. All rights reserved.
+# Copyright (c) 2018, Linaro, Ltd. All rights reserved.
+# Copyright (c) 2022 Rockchip Electronics Co. Ltd.
+#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+#
+##
+
+[Defines]
+ INF_VERSION = 0x0001001A
+ BASE_NAME = LogoDxe
+ FILE_GUID = 4b55f0bc-8b1a-11ec-bd4b-f42a7dcb925d
+ MODULE_TYPE = DXE_DRIVER
+ VERSION_STRING = 1.0
+
+ ENTRY_POINT = InitializeLogo
+#
+# This flag specifies whether HII resource section is generated into PE image.
+#
+ UEFI_HII_RESOURCE_SECTION = TRUE
+
+[Sources]
+ Logo.bmp
+ Logo.c
+ Logo.idf
+
+[Packages]
+ MdeModulePkg/MdeModulePkg.dec
+ MdePkg/MdePkg.dec
+
+[LibraryClasses]
+ UefiBootServicesTableLib
+ UefiDriverEntryPoint
+ DebugLib
+
+[Protocols]
+ gEfiHiiDatabaseProtocolGuid ## CONSUMES
+ gEfiHiiImageExProtocolGuid ## CONSUMES
+ gEfiHiiPackageListProtocolGuid ## PRODUCES CONSUMES
+ gEdkiiPlatformLogoProtocolGuid ## PRODUCES
+
+[Depex]
+ gEfiHiiDatabaseProtocolGuid AND
+ gEfiHiiImageExProtocolGuid
diff --git a/edk2-rockchip/Platform/Hinlink/H88K/AcpiTables/AcpiTables.inf b/edk2-rockchip/Platform/Hinlink/H88K/AcpiTables/AcpiTables.inf
new file mode 100644
index 000000000..e95eb7e1c
--- /dev/null
+++ b/edk2-rockchip/Platform/Hinlink/H88K/AcpiTables/AcpiTables.inf
@@ -0,0 +1,71 @@
+#/** @file
+#
+# ACPI table data and ASL sources required to boot the platform.
+#
+# Copyright (c) 2019-2021, ARM Limited. All rights reserved.
+# Copyright (c) Microsoft Corporation. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+#**/
+
+[Defines]
+ INF_VERSION = 0x0001001A
+ BASE_NAME = AcpiTables
+ FILE_GUID = 7E374E25-8E01-4FEE-87F2-390C23C606CD
+ MODULE_TYPE = USER_DEFINED
+ VERSION_STRING = 1.0
+ RK_COMMON_ACPI_DIR = Silicon/Rockchip/RK3588/AcpiTables
+
+#
+# The following information is for reference only and not required by the build tools.
+#
+# VALID_ARCHITECTURES = AARCH64
+#
+
+[Sources]
+ Dsdt.asl
+ $(RK_COMMON_ACPI_DIR)/Madt.aslc
+ $(RK_COMMON_ACPI_DIR)/Fadt.aslc
+ $(RK_COMMON_ACPI_DIR)/Gtdt.aslc
+ $(RK_COMMON_ACPI_DIR)/Spcr.aslc
+ $(RK_COMMON_ACPI_DIR)/Mcfg.aslc
+ $(RK_COMMON_ACPI_DIR)/Dbg2.aslc
+ $(RK_COMMON_ACPI_DIR)/Pcie3x4.asl
+ $(RK_COMMON_ACPI_DIR)/Pcie3x2.asl
+ $(RK_COMMON_ACPI_DIR)/Pcie2x1l0.asl
+ $(RK_COMMON_ACPI_DIR)/Pcie2x1l1.asl
+ $(RK_COMMON_ACPI_DIR)/Pcie2x1l2.asl
+ $(RK_COMMON_ACPI_DIR)/Sata0.asl
+ $(RK_COMMON_ACPI_DIR)/Sata1.asl
+ $(RK_COMMON_ACPI_DIR)/Sata2.asl
+
+[Packages]
+ ArmPkg/ArmPkg.dec
+ ArmPlatformPkg/ArmPlatformPkg.dec
+ EmbeddedPkg/EmbeddedPkg.dec
+ MdeModulePkg/MdeModulePkg.dec
+ MdePkg/MdePkg.dec
+ Silicon/Rockchip/RockchipPkg.dec
+ Platform/Rockchip/RK3588/RK3588.dec
+
+[FixedPcd]
+ gArmTokenSpaceGuid.PcdArmArchTimerIntrNum
+ gArmTokenSpaceGuid.PcdArmArchTimerHypIntrNum
+ gArmTokenSpaceGuid.PcdArmArchTimerSecIntrNum
+ gArmTokenSpaceGuid.PcdArmArchTimerVirtIntrNum
+ gArmTokenSpaceGuid.PcdGicInterruptInterfaceBase
+ gArmTokenSpaceGuid.PcdGicDistributorBase
+ gArmTokenSpaceGuid.PcdGicRedistributorsBase
+ gRockchipTokenSpaceGuid.PcdPcieRootPort3x4CfgBaseAddress
+ gRockchipTokenSpaceGuid.PcdPcieRootPort3x4ApbBaseAddress
+ gRockchipTokenSpaceGuid.PcdPcieRootPort3x4DbiBaseAddress
+ gRockchipTokenSpaceGuid.PcdPcieRootPort3x4CfgBaseAddress
+ gRockchipTokenSpaceGuid.PcdPcieRootPort3x4CfgSize
+ gRockchipTokenSpaceGuid.PcdPcieRootPort3x4IoBaseAddress
+ gRockchipTokenSpaceGuid.PcdPcieRootPort3x4IoSize
+ gRockchipTokenSpaceGuid.PcdPcieRootPort3x4MemBaseAddress
+ gRockchipTokenSpaceGuid.PcdPcieRootPort3x4MemSize
+ gRockchipTokenSpaceGuid.PcdPcieRootPort3x4MemBaseAddress64
+ gRockchipTokenSpaceGuid.PcdPcieRootPort3x4MemSize64
+ gEfiMdeModulePkgTokenSpaceGuid.PcdSerialRegisterBase
diff --git a/edk2-rockchip/Platform/Hinlink/H88K/AcpiTables/Dsdt.asl b/edk2-rockchip/Platform/Hinlink/H88K/AcpiTables/Dsdt.asl
new file mode 100755
index 000000000..a48463eff
--- /dev/null
+++ b/edk2-rockchip/Platform/Hinlink/H88K/AcpiTables/Dsdt.asl
@@ -0,0 +1,37 @@
+/** @file
+ *
+ * Differentiated System Definition Table (DSDT)
+ *
+ * Copyright (c) 2020, Pete Batard
+ * Copyright (c) 2018-2020, Andrey Warkentin
+ * Copyright (c) Microsoft Corporation. All rights reserved.
+ * Copyright (c) 2021, ARM Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-2-Clause-Patent
+ *
+ **/
+
+#include "AcpiTables.h"
+
+DefinitionBlock ("Dsdt.aml", "DSDT", 2, "RPIFDN", "RPI", 2)
+{
+ Scope (\_SB_)
+ {
+ include ("Cpu.asl")
+
+ include ("Emmc.asl")
+ include ("Sdhc.asl")
+ // include ("Gmac.asl")
+ // include ("Gpio.asl")
+ // include ("I2c.asl")
+ include ("Uart.asl")
+ // include ("Spi.asl")
+
+ // won't work on Windows, will trigger bugcheck by usbehci
+ // include ("Usb2.asl")
+
+ include ("Usb3Host0.asl")
+ include ("Usb3Host1.asl")
+ include ("Usb3Host2.asl")
+ }
+}
diff --git a/edk2-rockchip/Platform/Hinlink/H88K/H88K.Modules.fdf.inc b/edk2-rockchip/Platform/Hinlink/H88K/H88K.Modules.fdf.inc
new file mode 100644
index 000000000..c61608d63
--- /dev/null
+++ b/edk2-rockchip/Platform/Hinlink/H88K/H88K.Modules.fdf.inc
@@ -0,0 +1,13 @@
+## @file
+#
+# Copyright (c) 2023, Mario Bălănică
+#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+##
+
+ # ACPI Support
+ INF RuleOverride = ACPITABLE $(PLATFORM_DIRECTORY)/AcpiTables/AcpiTables.inf
+
+ # Splash screen logo
+ INF $(VENDOR_DIRECTORY)/Drivers/LogoDxe/LogoDxe.inf
diff --git a/edk2-rockchip/Platform/Hinlink/H88K/H88K.dsc b/edk2-rockchip/Platform/Hinlink/H88K/H88K.dsc
new file mode 100644
index 000000000..2d9405c6d
--- /dev/null
+++ b/edk2-rockchip/Platform/Hinlink/H88K/H88K.dsc
@@ -0,0 +1,85 @@
+## @file
+#
+# Copyright (c) 2014-2018, Linaro Limited. All rights reserved.
+# Copyright (c) 2022, Xilin Wu
+# Copyright (c) 2023, Jianfeng Liu
+#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+##
+
+################################################################################
+#
+# Defines Section - statements that will be processed to create a Makefile.
+#
+################################################################################
+[Defines]
+ PLATFORM_NAME = H88K
+ PLATFORM_VENDOR = Hinlink
+ PLATFORM_GUID = 5ecd3024-77d5-47a2-8293-a963ac878d48
+ PLATFORM_VERSION = 0.2
+ DSC_SPECIFICATION = 0x00010019
+ OUTPUT_DIRECTORY = Build/$(PLATFORM_NAME)
+ VENDOR_DIRECTORY = Platform/$(PLATFORM_VENDOR)
+ PLATFORM_DIRECTORY = $(VENDOR_DIRECTORY)/$(PLATFORM_NAME)
+ SUPPORTED_ARCHITECTURES = AARCH64
+ BUILD_TARGETS = DEBUG|RELEASE
+ SKUID_IDENTIFIER = DEFAULT
+ FLASH_DEFINITION = Silicon/Rockchip/RK3588/RK3588.fdf
+ RK_PLATFORM_FVMAIN_MODULES = $(PLATFORM_DIRECTORY)/$(PLATFORM_NAME).Modules.fdf.inc
+
+ #
+ # RK3588-based platform
+ #
+!include Silicon/Rockchip/RK3588/RK3588Platform.dsc.inc
+
+################################################################################
+#
+# Library Class section - list of all Library Classes needed by this Platform.
+#
+################################################################################
+
+[LibraryClasses.common]
+ RockchipPlatformLib|$(PLATFORM_DIRECTORY)/Library/RockchipPlatformLib/RockchipPlatformLib.inf
+
+################################################################################
+#
+# Pcd Section - list of all EDK II PCD Entries defined by this Platform.
+#
+################################################################################
+
+[PcdsFixedAtBuild.common]
+ # SMBIOS platform config
+ gRockchipTokenSpaceGuid.PcdPlatformName|"H88K"
+ gRockchipTokenSpaceGuid.PcdPlatformVendorName|"Hinlink"
+ gRockchipTokenSpaceGuid.PcdFamilyName|"H88K"
+ gRockchipTokenSpaceGuid.PcdProductUrl|"http://www.hinlink.com/"
+
+ #
+ # CPU Performance default values
+ #
+ gRK3588TokenSpaceGuid.PcdCPULClusterClockPresetDefault|$(CPU_PERF_CLUSTER_CLOCK_PRESET_BOOTDEFAULT)
+ gRK3588TokenSpaceGuid.PcdCPUB01ClusterClockPresetDefault|$(CPU_PERF_CLUSTER_CLOCK_PRESET_BOOTDEFAULT)
+ gRK3588TokenSpaceGuid.PcdCPUB23ClusterClockPresetDefault|$(CPU_PERF_CLUSTER_CLOCK_PRESET_BOOTDEFAULT)
+
+ #
+ # PCIe/SATA/USB Combo PIPE PHY support flags and default values
+ #
+ gRK3588TokenSpaceGuid.PcdComboPhy0Switchable|TRUE
+ gRK3588TokenSpaceGuid.PcdComboPhy1Switchable|FALSE
+ gRK3588TokenSpaceGuid.PcdComboPhy2Switchable|FALSE
+ gRK3588TokenSpaceGuid.PcdComboPhy0ModeDefault|$(COMBO_PHY_MODE_PCIE)
+ gRK3588TokenSpaceGuid.PcdComboPhy1ModeDefault|$(COMBO_PHY_MODE_PCIE)
+ gRK3588TokenSpaceGuid.PcdComboPhy2ModeDefault|$(COMBO_PHY_MODE_PCIE)
+
+################################################################################
+#
+# Components Section - list of all EDK II Modules needed by this Platform.
+#
+################################################################################
+[Components.common]
+ # ACPI Support
+ $(PLATFORM_DIRECTORY)/AcpiTables/AcpiTables.inf
+
+ # Splash screen logo
+ $(VENDOR_DIRECTORY)/Drivers/LogoDxe/LogoDxe.inf
diff --git a/edk2-rockchip/Platform/Hinlink/H88K/Library/RockchipPlatformLib/RockchipPlatformLib.c b/edk2-rockchip/Platform/Hinlink/H88K/Library/RockchipPlatformLib/RockchipPlatformLib.c
new file mode 100644
index 000000000..051450a60
--- /dev/null
+++ b/edk2-rockchip/Platform/Hinlink/H88K/Library/RockchipPlatformLib/RockchipPlatformLib.c
@@ -0,0 +1,317 @@
+/** @file
+*
+* Copyright (c) 2021, Rockchip Limited. All rights reserved.
+*
+* SPDX-License-Identifier: BSD-2-Clause-Patent
+*
+**/
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+static struct regulator_init_data rk806_init_data[] = {
+ /* Master PMIC */
+ RK8XX_VOLTAGE_INIT(MASTER_BUCK1, 750000),
+ RK8XX_VOLTAGE_INIT(MASTER_BUCK3, 750000),
+ RK8XX_VOLTAGE_INIT(MASTER_BUCK4, 750000),
+ RK8XX_VOLTAGE_INIT(MASTER_BUCK5, 850000),
+ //RK8XX_VOLTAGE_INIT(MASTER_BUCK6, 750000),
+ RK8XX_VOLTAGE_INIT(MASTER_BUCK7, 2000000),
+ RK8XX_VOLTAGE_INIT(MASTER_BUCK8, 3300000),
+ RK8XX_VOLTAGE_INIT(MASTER_BUCK10, 1800000),
+
+ RK8XX_VOLTAGE_INIT(MASTER_NLDO1, 750000),
+ RK8XX_VOLTAGE_INIT(MASTER_NLDO2, 850000),
+ RK8XX_VOLTAGE_INIT(MASTER_NLDO3, 750000),
+ RK8XX_VOLTAGE_INIT(MASTER_NLDO4, 850000),
+ RK8XX_VOLTAGE_INIT(MASTER_NLDO5, 750000),
+
+ RK8XX_VOLTAGE_INIT(MASTER_PLDO1, 1800000),
+ RK8XX_VOLTAGE_INIT(MASTER_PLDO2, 1800000),
+ RK8XX_VOLTAGE_INIT(MASTER_PLDO3, 1200000),
+ RK8XX_VOLTAGE_INIT(MASTER_PLDO4, 3300000),
+ RK8XX_VOLTAGE_INIT(MASTER_PLDO5, 3300000),
+ RK8XX_VOLTAGE_INIT(MASTER_PLDO6, 1800000),
+
+ /* No dual PMICs on this platform */
+};
+
+VOID
+EFIAPI
+DwEmmcDxeIoMux (
+ VOID
+ )
+{
+ /* sdmmc0 iomux (microSD socket) */
+ BUS_IOC->GPIO4D_IOMUX_SEL_L = (0xFFFFUL << 16) | (0x1111); //SDMMC_D0,SDMMC_D1,SDMMC_D2,SDMMC_D3
+ BUS_IOC->GPIO4D_IOMUX_SEL_H = (0x00FFUL << 16) | (0x0011); //SDMMC_CLK,SDMMC_CMD
+ PMU1_IOC->GPIO0A_IOMUX_SEL_H = (0x000FUL << 16) | (0x0001); //SDMMC_DET
+}
+
+VOID
+EFIAPI
+SdhciEmmcDxeIoMux (
+ VOID
+ )
+{
+ /* sdhci0 iomux (eMMC socket) */
+ BUS_IOC->GPIO2A_IOMUX_SEL_L = (0xFFFFUL << 16) | (0x1111); //EMMC_CMD,EMMC_CLKOUT,EMMC_DATASTROBE,EMMC_RSTN
+ BUS_IOC->GPIO2D_IOMUX_SEL_L = (0xFFFFUL << 16) | (0x1111); //EMMC_D0,EMMC_D1,EMMC_D2,EMMC_D3
+ BUS_IOC->GPIO2D_IOMUX_SEL_H = (0xFFFFUL << 16) | (0x1111); //EMMC_D4,EMMC_D5,EMMC_D6,EMMC_D7
+}
+
+#define NS_CRU_BASE 0xFD7C0000
+#define CRU_CLKSEL_CON59 0x03EC
+#define CRU_CLKSEL_CON78 0x0438
+
+VOID
+EFIAPI
+Rk806SpiIomux (
+ VOID
+ )
+{
+ /* io mux */
+ //BUS_IOC->GPIO1A_IOMUX_SEL_H = (0xFFFFUL << 16) | 0x8888;
+ //BUS_IOC->GPIO1B_IOMUX_SEL_L = (0x000FUL << 16) | 0x0008;
+ PMU1_IOC->GPIO0A_IOMUX_SEL_H = (0x0FF0UL << 16) | 0x0110;
+ PMU1_IOC->GPIO0B_IOMUX_SEL_L = (0xF0FFUL << 16) | 0x1011;
+ MmioWrite32(NS_CRU_BASE + CRU_CLKSEL_CON59, (0x00C0UL << 16) | 0x0080);
+}
+
+VOID
+EFIAPI
+Rk806Configure (
+ VOID
+ )
+{
+ UINTN RegCfgIndex;
+
+ RK806Init();
+
+ for (RegCfgIndex = 0; RegCfgIndex < ARRAY_SIZE(rk806_init_data); RegCfgIndex++)
+ RK806RegulatorInit(rk806_init_data[RegCfgIndex]);
+}
+
+VOID
+EFIAPI
+SetCPULittleVoltage (
+ IN UINT32 Microvolts
+ )
+{
+ struct regulator_init_data Rk806CpuLittleSupply =
+ RK8XX_VOLTAGE_INIT(MASTER_BUCK2, Microvolts);
+
+ RK806RegulatorInit(Rk806CpuLittleSupply);
+}
+
+VOID
+EFIAPI
+NorFspiIomux (
+ VOID
+ )
+{
+ /* io mux */
+ MmioWrite32(NS_CRU_BASE + CRU_CLKSEL_CON78,
+ (((0x3 << 12) | (0x3f << 6)) << 16) | (0x0 << 12) | (0x3f << 6));
+#define FSPI_M1
+#if defined(FSPI_M0)
+ /*FSPI M0*/
+ BUS_IOC->GPIO2A_IOMUX_SEL_L = ((0xF << 0) << 16) | (2 << 0); //FSPI_CLK_M0
+ BUS_IOC->GPIO2D_IOMUX_SEL_L = (0xFFFFUL << 16) | (0x2222); //FSPI_D0_M0,FSPI_D1_M0,FSPI_D2_M0,FSPI_D3_M0
+ BUS_IOC->GPIO2D_IOMUX_SEL_H = ((0xF << 8) << 16) | (0x2 << 8); //FSPI_CS0N_M0
+#elif defined(FSPI_M1)
+ /*FSPI M1*/
+ BUS_IOC->GPIO2A_IOMUX_SEL_H = (0xFF00UL << 16) | (0x3300); //FSPI_D0_M1,FSPI_D1_M1
+ BUS_IOC->GPIO2B_IOMUX_SEL_L = (0xF0FFUL << 16) | (0x3033); //FSPI_D2_M1,FSPI_D3_M1,FSPI_CLK_M1
+ BUS_IOC->GPIO2B_IOMUX_SEL_H = (0xF << 16) | (0x3); //FSPI_CS0N_M1
+#else
+ /*FSPI M2*/
+ BUS_IOC->GPIO3A_IOMUX_SEL_L = (0xFFFFUL << 16) | (0x5555); //[FSPI_D0_M2-FSPI_D3_M2]
+ BUS_IOC->GPIO3A_IOMUX_SEL_H = (0xF0UL << 16) | (0x50); //FSPI_CLK_M2
+ BUS_IOC->GPIO3C_IOMUX_SEL_H = (0xF << 16) | (0x2); //FSPI_CS0_M2
+#endif
+}
+
+VOID
+EFIAPI
+GmacIomux (
+ UINT32 id
+ )
+{
+ /* No GMAC here */
+}
+
+VOID
+EFIAPI
+NorFspiEnableClock (
+ UINT32 *CruBase
+ )
+{
+ UINTN BaseAddr = (UINTN) CruBase;
+
+ MmioWrite32(BaseAddr + 0x087C, 0x0E000000);
+}
+
+VOID
+EFIAPI
+I2cIomux (
+ UINT32 id
+ )
+{
+ switch (id) {
+ case 0:
+ /* io mux M2 */
+ PMU2_IOC->GPIO0D_IOMUX_SEL_L = (0x0F00UL << 16) | 0x0300;
+ PMU2_IOC->GPIO0D_IOMUX_SEL_L = (0x00F0UL << 16) | 0x0030;
+ break;
+ case 1:
+ /* io mux */
+ //BUS_IOC->GPIO0B_IOMUX_SEL_H = (0x0FF0UL << 16) | 0x0990;
+ //PMU2_IOC->GPIO0B_IOMUX_SEL_H = (0x0FF0UL << 16) | 0x0880;
+ break;
+ case 2:
+ /* io mux */
+ BUS_IOC->GPIO0B_IOMUX_SEL_H = (0xF000UL << 16) | 0x9000;
+ BUS_IOC->GPIO0C_IOMUX_SEL_L = (0x000FUL << 16) | 0x0009;
+ PMU2_IOC->GPIO0B_IOMUX_SEL_H = (0xF000UL << 16) | 0x8000;
+ PMU2_IOC->GPIO0C_IOMUX_SEL_L = (0x000FUL << 16) | 0x0008;
+ break;
+ case 3:
+ break;
+ case 4:
+ break;
+ case 5:
+ break;
+ default:
+ break;
+ }
+}
+
+VOID
+EFIAPI
+UsbPortPowerEnable (
+ VOID
+ )
+{
+ DEBUG((EFI_D_WARN, "UsbPortPowerEnable called\n"));
+ /* Set GPIO4 PB0 (USB_HOST_PWREN) output high to power USB ports */
+ GpioPinSetDirection (4, GPIO_PIN_PB0, GPIO_PIN_OUTPUT);
+ GpioPinWrite (4, GPIO_PIN_PB0, TRUE);
+}
+
+VOID
+EFIAPI
+Usb2PhyResume (
+ VOID
+ )
+{
+ MmioWrite32(0xfd5d0008, 0x20000000);
+ MmioWrite32(0xfd5d4008, 0x20000000);
+ MmioWrite32(0xfd5d8008, 0x20000000);
+ MmioWrite32(0xfd5dc008, 0x20000000);
+ MmioWrite32(0xfd7f0a10, 0x07000700);
+ MmioWrite32(0xfd7f0a10, 0x07000000);
+}
+
+VOID
+EFIAPI
+UsbDpPhyEnable (
+ VOID
+ )
+{
+ /* enable rx_lfps_en & usbdp_low_pwrn */
+ MmioWrite32(0xfd5c8004, 0x60006000);
+ MmioWrite32(0xfd5cc004, 0x60006000);
+
+ /* remove rx-termination, we don't support SS yet */
+ MmioWrite32 (0xfd5c800c, 0x00030001);
+ MmioWrite32 (0xfd5cc00c, 0x00030001);
+}
+
+VOID
+EFIAPI
+PcieIoInit (
+ UINT32 Segment
+ )
+{
+ /* Set reset and power IO to gpio output mode */
+ switch(Segment) {
+ case PCIE_SEGMENT_PCIE30X4:
+ GpioPinSetDirection (4, GPIO_PIN_PB6, GPIO_PIN_OUTPUT);
+ GpioPinSetDirection (3, GPIO_PIN_PD5, GPIO_PIN_OUTPUT);
+ break;
+ case PCIE_SEGMENT_PCIE20L0:
+ GpioPinSetDirection (0, GPIO_PIN_PB0, GPIO_PIN_OUTPUT);
+ break;
+ case PCIE_SEGMENT_PCIE20L1:
+ GpioPinSetDirection (4, GPIO_PIN_PA2, GPIO_PIN_OUTPUT);
+ break;
+ case PCIE_SEGMENT_PCIE20L2:
+ GpioPinSetDirection (4, GPIO_PIN_PA5, GPIO_PIN_OUTPUT);
+ break;
+ default:
+ break;
+ }
+}
+
+VOID
+EFIAPI
+PciePowerEn (
+ UINT32 Segment,
+ BOOLEAN Enable
+ )
+{
+ /* output high to enable power */
+
+ switch(Segment) {
+ case PCIE_SEGMENT_PCIE30X4:
+ GpioPinWrite (3, GPIO_PIN_PD5, Enable);
+ break;
+ case PCIE_SEGMENT_PCIE20L0:
+ break;
+ case PCIE_SEGMENT_PCIE20L1:
+ break;
+ case PCIE_SEGMENT_PCIE20L2:
+ break;
+ default:
+ break;
+ }
+}
+
+VOID
+EFIAPI
+PciePeReset (
+ UINT32 Segment,
+ BOOLEAN Enable
+ )
+{
+ switch(Segment) {
+ case PCIE_SEGMENT_PCIE30X4:
+ GpioPinWrite (4, GPIO_PIN_PB6, !Enable);
+ break;
+ case PCIE_SEGMENT_PCIE20L0:
+ GpioPinWrite (0, GPIO_PIN_PB0, !Enable);
+ break;
+ case PCIE_SEGMENT_PCIE20L1:
+ GpioPinWrite (4, GPIO_PIN_PA2, !Enable);
+ break;
+ case PCIE_SEGMENT_PCIE20L2:
+ GpioPinWrite (4, GPIO_PIN_PA5, !Enable);
+ break;
+ default:
+ break;
+ }
+}
+
+VOID
+EFIAPI
+PlatformEarlyInit (
+ VOID
+ )
+{
+ // Configure various things specific to this platform
+}
diff --git a/edk2-rockchip/Platform/Hinlink/H88K/Library/RockchipPlatformLib/RockchipPlatformLib.inf b/edk2-rockchip/Platform/Hinlink/H88K/Library/RockchipPlatformLib/RockchipPlatformLib.inf
new file mode 100644
index 000000000..57a153f51
--- /dev/null
+++ b/edk2-rockchip/Platform/Hinlink/H88K/Library/RockchipPlatformLib/RockchipPlatformLib.inf
@@ -0,0 +1,41 @@
+#
+# Copyright (c) 2021, Rockchip Limited. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+
+[Defines]
+ INF_VERSION = 0x00010019
+ BASE_NAME = RockchipPlatformLib
+ FILE_GUID = 5178fa86-2fec-11ec-95b4-f42a7dcb925d
+ MODULE_TYPE = BASE
+ VERSION_STRING = 1.0
+ LIBRARY_CLASS = RockchipPlatformLib
+ RKPLATLIB_COMMON_DIR = Silicon/Rockchip/RK3588/Library/RockchipPlatformLibCommon
+
+[Packages]
+ EmbeddedPkg/EmbeddedPkg.dec
+ MdePkg/MdePkg.dec
+ MdeModulePkg/MdeModulePkg.dec
+ Platform/Rockchip/RK3588/RK3588.dec
+ Silicon/Rockchip/RK3588/RK3588.dec
+ Silicon/Rockchip/RockchipPkg.dec
+
+[LibraryClasses]
+ ArmLib
+ HobLib
+ IoLib
+ MemoryAllocationLib
+ SerialPortLib
+ CruLib
+ GpioLib
+
+[Sources.common]
+ RockchipPlatformLib.c
+ $(RKPLATLIB_COMMON_DIR)/RK3588CruLib.c
+
+[Sources.AARCH64]
+
+[Pcd]
+ gRockchipTokenSpaceGuid.PcdI2cBusCount
+