Feasibility of Chaining transport usage in a serial communication implementation #4623
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Hi @Syamkamalnadhc, Chaining transports is a feature that allows for injecting code in between the RTPS layer and the actual underlying transport (UDP/TCP/SHM) so it is possible to perform manipulations on the transport payload itself (in this case RTPS datagrams), the set of destinations and so on. That being said, the data always ends up the real transports, you by using this feature you could for instance wrap the RTPS datagram however you wanted, but the payload will always end up in all the participant's transports. For you case, that would mean that you could use a chaining transport to do all the PCIe logic you wanted, but no matter what you do, the data will always end up in the UDP transport. Unfortunately we do not have any example that we can provide at the moment. |
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We are currently exploring the capabilities of Fast-DDS, as part of a project that involves a custom serial protocol implemented over PCIe.
After going through the documentation and source code related to ChainingTransport, We understand that ChainingTransport allows for the manipulation of data before sending or after receiving from another transport. This feature seems useful for our use case, where we aim to adapt the send and receive functionalities to work with PCIe logic, without the need to extensively modify or create new transport descriptors, interface classes, and channel resource classes specifically for PCIe.
Before proceeding, We would like to seek your advice and clarification on a few points:
Feasibility: Is it feasible to use ChainingTransport to implement a custom protocol over PCIe by modifying the send and receive functions to incorporate PCIe logic? If so, could you provide any guidance or examples on how to approach this adaptation?
Avoiding Extensive Customization: The objective is to minimize the effort in creating dedicated transport descriptors, interface classes, and channel resource classes for PCIe. Can ChainingTransport be utilized in such a way that it uses the existing transport mechanisms while introducing PCIe-specific logic?
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