PostDoc at EPFL and Director of Eng. in the OpenHW Group. He received his Ph.D. from ETH Zurich.
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EPFL, OpenHW Group
- Geneva
- @DavideSchiavo10
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esl-epfl/x-heep
esl-epfl/x-heep PubliceXtendable Heterogeneous Energy-Efficient Platform based on RISC-V
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openhwgroup/cv32e40p
openhwgroup/cv32e40p PublicCV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform
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lowRISC/ibex
lowRISC/ibex PublicIbex is a small 32 bit RISC-V CPU core, previously known as zero-riscy.
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