-
Notifications
You must be signed in to change notification settings - Fork 0
/
timing.txt
3088 lines (2829 loc) · 207 KB
/
timing.txt
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353
354
355
356
357
358
359
360
361
362
363
364
365
366
367
368
369
370
371
372
373
374
375
376
377
378
379
380
381
382
383
384
385
386
387
388
389
390
391
392
393
394
395
396
397
398
399
400
401
402
403
404
405
406
407
408
409
410
411
412
413
414
415
416
417
418
419
420
421
422
423
424
425
426
427
428
429
430
431
432
433
434
435
436
437
438
439
440
441
442
443
444
445
446
447
448
449
450
451
452
453
454
455
456
457
458
459
460
461
462
463
464
465
466
467
468
469
470
471
472
473
474
475
476
477
478
479
480
481
482
483
484
485
486
487
488
489
490
491
492
493
494
495
496
497
498
499
500
501
502
503
504
505
506
507
508
509
510
511
512
513
514
515
516
517
518
519
520
521
522
523
524
525
526
527
528
529
530
531
532
533
534
535
536
537
538
539
540
541
542
543
544
545
546
547
548
549
550
551
552
553
554
555
556
557
558
559
560
561
562
563
564
565
566
567
568
569
570
571
572
573
574
575
576
577
578
579
580
581
582
583
584
585
586
587
588
589
590
591
592
593
594
595
596
597
598
599
600
601
602
603
604
605
606
607
608
609
610
611
612
613
614
615
616
617
618
619
620
621
622
623
624
625
626
627
628
629
630
631
632
633
634
635
636
637
638
639
640
641
642
643
644
645
646
647
648
649
650
651
652
653
654
655
656
657
658
659
660
661
662
663
664
665
666
667
668
669
670
671
672
673
674
675
676
677
678
679
680
681
682
683
684
685
686
687
688
689
690
691
692
693
694
695
696
697
698
699
700
701
702
703
704
705
706
707
708
709
710
711
712
713
714
715
716
717
718
719
720
721
722
723
724
725
726
727
728
729
730
731
732
733
734
735
736
737
738
739
740
741
742
743
744
745
746
747
748
749
750
751
752
753
754
755
756
757
758
759
760
761
762
763
764
765
766
767
768
769
770
771
772
773
774
775
776
777
778
779
780
781
782
783
784
785
786
787
788
789
790
791
792
793
794
795
796
797
798
799
800
801
802
803
804
805
806
807
808
809
810
811
812
813
814
815
816
817
818
819
820
821
822
823
824
825
826
827
828
829
830
831
832
833
834
835
836
837
838
839
840
841
842
843
844
845
846
847
848
849
850
851
852
853
854
855
856
857
858
859
860
861
862
863
864
865
866
867
868
869
870
871
872
873
874
875
876
877
878
879
880
881
882
883
884
885
886
887
888
889
890
891
892
893
894
895
896
897
898
899
900
901
902
903
904
905
906
907
908
909
910
911
912
913
914
915
916
917
918
919
920
921
922
923
924
925
926
927
928
929
930
931
932
933
934
935
936
937
938
939
940
941
942
943
944
945
946
947
948
949
950
951
952
953
954
955
956
957
958
959
960
961
962
963
964
965
966
967
968
969
970
971
972
973
974
975
976
977
978
979
980
981
982
983
984
985
986
987
988
989
990
991
992
993
994
995
996
997
998
999
1000
Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
| Tool Version : Vivado v.2022.1 (lin64) Build 3526262 Mon Apr 18 15:47:01 MDT 2022
| Date : Thu Nov 2 13:55:19 2023
| Host : ubuntu2004 running 64-bit Ubuntu 20.04.4 LTS
| Command : report_timing_summary -delay_type min_max -report_unconstrained -check_timing_verbose -max_paths 10 -input_pins -routable_nets -name timing_1 -file /home/ubuntu/Desktop/timing.txt
| Design : user_proj_example
| Device : 7z020-clg400
| Speed File : -1 PRODUCTION 1.12 2019-11-22
-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
Timing Summary Report
------------------------------------------------------------------------------------------------
| Timer Settings
| --------------
------------------------------------------------------------------------------------------------
Enable Multi Corner Analysis : Yes
Enable Pessimism Removal : Yes
Pessimism Removal Resolution : Nearest Common Node
Enable Input Delay Default Clock : No
Enable Preset / Clear Arcs : No
Disable Flight Delays : No
Ignore I/O Paths : No
Timing Early Launch at Borrowing Latches : No
Borrow Time for Max Delay Exceptions : Yes
Merge Timing Exceptions : Yes
Corner Analyze Analyze
Name Max Paths Min Paths
------ --------- ---------
Slow Yes Yes
Fast Yes Yes
------------------------------------------------------------------------------------------------
| Report Methodology
| ------------------
------------------------------------------------------------------------------------------------
No report available as report_methodology has not been run prior. Run report_methodology on the current design for the summary of methodology violations.
check_timing report
Table of Contents
-----------------
1. checking no_clock (0)
2. checking constant_clock (0)
3. checking pulse_width_clock (0)
4. checking unconstrained_internal_endpoints (0)
5. checking no_input_delay (60)
6. checking no_output_delay (33)
7. checking multiple_clock (0)
8. checking generated_clocks (0)
9. checking loops (0)
10. checking partial_input_delay (0)
11. checking partial_output_delay (0)
12. checking latch_loops (0)
1. checking no_clock (0)
------------------------
There are 0 register/latch pins with no clock.
2. checking constant_clock (0)
------------------------------
There are 0 register/latch pins with constant_clock.
3. checking pulse_width_clock (0)
---------------------------------
There are 0 register/latch pins which need pulse_width check
4. checking unconstrained_internal_endpoints (0)
------------------------------------------------
There are 0 pins that are not constrained for maximum delay.
There are 0 pins that are not constrained for maximum delay due to constant clock.
5. checking no_input_delay (60)
-------------------------------
There are 60 input ports with no input delay specified. (HIGH)
wb_rst_i
wbs_adr_i[0]
wbs_adr_i[10]
wbs_adr_i[11]
wbs_adr_i[1]
wbs_adr_i[24]
wbs_adr_i[25]
wbs_adr_i[26]
wbs_adr_i[27]
wbs_adr_i[28]
wbs_adr_i[29]
wbs_adr_i[2]
wbs_adr_i[30]
wbs_adr_i[31]
wbs_adr_i[3]
wbs_adr_i[4]
wbs_adr_i[5]
wbs_adr_i[6]
wbs_adr_i[7]
wbs_adr_i[8]
wbs_adr_i[9]
wbs_cyc_i
wbs_dat_i[0]
wbs_dat_i[10]
wbs_dat_i[11]
wbs_dat_i[12]
wbs_dat_i[13]
wbs_dat_i[14]
wbs_dat_i[15]
wbs_dat_i[16]
wbs_dat_i[17]
wbs_dat_i[18]
wbs_dat_i[19]
wbs_dat_i[1]
wbs_dat_i[20]
wbs_dat_i[21]
wbs_dat_i[22]
wbs_dat_i[23]
wbs_dat_i[24]
wbs_dat_i[25]
wbs_dat_i[26]
wbs_dat_i[27]
wbs_dat_i[28]
wbs_dat_i[29]
wbs_dat_i[2]
wbs_dat_i[30]
wbs_dat_i[31]
wbs_dat_i[3]
wbs_dat_i[4]
wbs_dat_i[5]
wbs_dat_i[6]
wbs_dat_i[7]
wbs_dat_i[8]
wbs_dat_i[9]
wbs_sel_i[0]
wbs_sel_i[1]
wbs_sel_i[2]
wbs_sel_i[3]
wbs_stb_i
wbs_we_i
There are 0 input ports with no input delay but user has a false path constraint.
6. checking no_output_delay (33)
--------------------------------
There are 33 ports with no output delay specified. (HIGH)
wbs_ack_o
wbs_dat_o[0]
wbs_dat_o[10]
wbs_dat_o[11]
wbs_dat_o[12]
wbs_dat_o[13]
wbs_dat_o[14]
wbs_dat_o[15]
wbs_dat_o[16]
wbs_dat_o[17]
wbs_dat_o[18]
wbs_dat_o[19]
wbs_dat_o[1]
wbs_dat_o[20]
wbs_dat_o[21]
wbs_dat_o[22]
wbs_dat_o[23]
wbs_dat_o[24]
wbs_dat_o[25]
wbs_dat_o[26]
wbs_dat_o[27]
wbs_dat_o[28]
wbs_dat_o[29]
wbs_dat_o[2]
wbs_dat_o[30]
wbs_dat_o[31]
wbs_dat_o[3]
wbs_dat_o[4]
wbs_dat_o[5]
wbs_dat_o[6]
wbs_dat_o[7]
wbs_dat_o[8]
wbs_dat_o[9]
There are 0 ports with no output delay but user has a false path constraint
There are 0 ports with no output delay but with a timing clock defined on it or propagating through it
7. checking multiple_clock (0)
------------------------------
There are 0 register/latch pins with multiple clocks.
8. checking generated_clocks (0)
--------------------------------
There are 0 generated clocks that are not connected to a clock source.
9. checking loops (0)
---------------------
There are 0 combinational loops in the design.
10. checking partial_input_delay (0)
------------------------------------
There are 0 input ports with partial input delay specified.
11. checking partial_output_delay (0)
-------------------------------------
There are 0 ports with partial output delay specified.
12. checking latch_loops (0)
----------------------------
There are 0 combinational latch loops in the design through latch input
------------------------------------------------------------------------------------------------
| Design Timing Summary
| ---------------------
------------------------------------------------------------------------------------------------
WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints WPWS(ns) TPWS(ns) TPWS Failing Endpoints TPWS Total Endpoints
------- ------- --------------------- ------------------- ------- ------- --------------------- ------------------- -------- -------- ---------------------- --------------------
7.365 0.000 0 9 0.146 0.000 0 9 4.500 0.000 0 14
All user specified timing constraints are met.
------------------------------------------------------------------------------------------------
| Clock Summary
| -------------
------------------------------------------------------------------------------------------------
Clock Waveform(ns) Period(ns) Frequency(MHz)
----- ------------ ---------- --------------
wb_clk_i {0.000 5.000} 10.000 100.000
------------------------------------------------------------------------------------------------
| Intra Clock Table
| -----------------
------------------------------------------------------------------------------------------------
Clock WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints WPWS(ns) TPWS(ns) TPWS Failing Endpoints TPWS Total Endpoints
----- ------- ------- --------------------- ------------------- ------- ------- --------------------- ------------------- -------- -------- ---------------------- --------------------
wb_clk_i 7.365 0.000 0 9 0.146 0.000 0 9 4.500 0.000 0 14
------------------------------------------------------------------------------------------------
| Inter Clock Table
| -----------------
------------------------------------------------------------------------------------------------
From Clock To Clock WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints
---------- -------- ------- ------- --------------------- ------------------- ------- ------- --------------------- -------------------
------------------------------------------------------------------------------------------------
| Other Path Groups Table
| -----------------------
------------------------------------------------------------------------------------------------
Path Group From Clock To Clock WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints
---------- ---------- -------- ------- ------- --------------------- ------------------- ------- ------- --------------------- -------------------
------------------------------------------------------------------------------------------------
| User Ignored Path Table
| -----------------------
------------------------------------------------------------------------------------------------
Path Group From Clock To Clock
---------- ---------- --------
------------------------------------------------------------------------------------------------
| Unconstrained Path Table
| ------------------------
------------------------------------------------------------------------------------------------
Path Group From Clock To Clock
---------- ---------- --------
(none) wb_clk_i
(none) wb_clk_i
------------------------------------------------------------------------------------------------
| Timing Details
| --------------
------------------------------------------------------------------------------------------------
---------------------------------------------------------------------------------------------------
From Clock: wb_clk_i
To Clock: wb_clk_i
Setup : 0 Failing Endpoints, Worst Slack 7.365ns, Total Violation 0.000ns
Hold : 0 Failing Endpoints, Worst Slack 0.146ns, Total Violation 0.000ns
PW : 0 Failing Endpoints, Worst Slack 4.500ns, Total Violation 0.000ns
---------------------------------------------------------------------------------------------------
Max Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) : 7.365ns (required time - arrival time)
Source: ack_reg/C
(rising edge-triggered cell FDRE clocked by wb_clk_i {[email protected] [email protected] period=10.000ns})
Destination: delay_cnt_reg[0]/CE
(rising edge-triggered cell FDRE clocked by wb_clk_i {[email protected] [email protected] period=10.000ns})
Path Group: wb_clk_i
Path Type: Setup (Max at Slow Process Corner)
Requirement: 10.000ns (wb_clk_i [email protected] - wb_clk_i [email protected])
Data Path Delay: 2.253ns (logic 0.773ns (34.310%) route 1.480ns (65.690%))
Logic Levels: 1 (LUT6=1)
Clock Path Skew: -0.145ns (DCD - SCD + CPR)
Destination Clock Delay (DCD): 2.128ns = ( 12.128 - 10.000 )
Source Clock Delay (SCD): 2.456ns
Clock Pessimism Removal (CPR): 0.184ns
Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
Total System Jitter (TSJ): 0.071ns
Total Input Jitter (TIJ): 0.000ns
Discrete Jitter (DJ): 0.000ns
Phase Error (PE): 0.000ns
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
------------------------------------------------------------------- -------------------
(clock wb_clk_i rise edge)
0.000 0.000 r
0.000 0.000 r wb_clk_i (IN)
net (fo=0) 0.000 0.000 wb_clk_i
r wb_clk_i_IBUF_inst/I
IBUF (Prop_ibuf_I_O) 0.972 0.972 r wb_clk_i_IBUF_inst/O
net (fo=1, unplaced) 0.800 1.771 wb_clk_i_IBUF
r wb_clk_i_IBUF_BUFG_inst/I
BUFG (Prop_bufg_I_O) 0.101 1.872 r wb_clk_i_IBUF_BUFG_inst/O
net (fo=13, unplaced) 0.584 2.456 wb_clk_i_IBUF_BUFG
FDRE r ack_reg/C
------------------------------------------------------------------- -------------------
FDRE (Prop_fdre_C_Q) 0.478 2.934 f ack_reg/Q
net (fo=3, unplaced) 0.983 3.917 wbs_ack_o_OBUF
f delay_cnt[3]_i_1/I1
LUT6 (Prop_lut6_I1_O) 0.295 4.212 r delay_cnt[3]_i_1/O
net (fo=4, unplaced) 0.497 4.709 delay_cnt
FDRE r delay_cnt_reg[0]/CE
------------------------------------------------------------------- -------------------
(clock wb_clk_i rise edge)
10.000 10.000 r
0.000 10.000 r wb_clk_i (IN)
net (fo=0) 0.000 10.000 wb_clk_i
r wb_clk_i_IBUF_inst/I
IBUF (Prop_ibuf_I_O) 0.838 10.838 r wb_clk_i_IBUF_inst/O
net (fo=1, unplaced) 0.760 11.598 wb_clk_i_IBUF
r wb_clk_i_IBUF_BUFG_inst/I
BUFG (Prop_bufg_I_O) 0.091 11.689 r wb_clk_i_IBUF_BUFG_inst/O
net (fo=13, unplaced) 0.439 12.128 wb_clk_i_IBUF_BUFG
FDRE r delay_cnt_reg[0]/C
clock pessimism 0.184 12.311
clock uncertainty -0.035 12.276
FDRE (Setup_fdre_C_CE) -0.202 12.074 delay_cnt_reg[0]
-------------------------------------------------------------------
required time 12.074
arrival time -4.709
-------------------------------------------------------------------
slack 7.365
Slack (MET) : 7.365ns (required time - arrival time)
Source: ack_reg/C
(rising edge-triggered cell FDRE clocked by wb_clk_i {[email protected] [email protected] period=10.000ns})
Destination: delay_cnt_reg[1]/CE
(rising edge-triggered cell FDRE clocked by wb_clk_i {[email protected] [email protected] period=10.000ns})
Path Group: wb_clk_i
Path Type: Setup (Max at Slow Process Corner)
Requirement: 10.000ns (wb_clk_i [email protected] - wb_clk_i [email protected])
Data Path Delay: 2.253ns (logic 0.773ns (34.310%) route 1.480ns (65.690%))
Logic Levels: 1 (LUT6=1)
Clock Path Skew: -0.145ns (DCD - SCD + CPR)
Destination Clock Delay (DCD): 2.128ns = ( 12.128 - 10.000 )
Source Clock Delay (SCD): 2.456ns
Clock Pessimism Removal (CPR): 0.184ns
Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
Total System Jitter (TSJ): 0.071ns
Total Input Jitter (TIJ): 0.000ns
Discrete Jitter (DJ): 0.000ns
Phase Error (PE): 0.000ns
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
------------------------------------------------------------------- -------------------
(clock wb_clk_i rise edge)
0.000 0.000 r
0.000 0.000 r wb_clk_i (IN)
net (fo=0) 0.000 0.000 wb_clk_i
r wb_clk_i_IBUF_inst/I
IBUF (Prop_ibuf_I_O) 0.972 0.972 r wb_clk_i_IBUF_inst/O
net (fo=1, unplaced) 0.800 1.771 wb_clk_i_IBUF
r wb_clk_i_IBUF_BUFG_inst/I
BUFG (Prop_bufg_I_O) 0.101 1.872 r wb_clk_i_IBUF_BUFG_inst/O
net (fo=13, unplaced) 0.584 2.456 wb_clk_i_IBUF_BUFG
FDRE r ack_reg/C
------------------------------------------------------------------- -------------------
FDRE (Prop_fdre_C_Q) 0.478 2.934 f ack_reg/Q
net (fo=3, unplaced) 0.983 3.917 wbs_ack_o_OBUF
f delay_cnt[3]_i_1/I1
LUT6 (Prop_lut6_I1_O) 0.295 4.212 r delay_cnt[3]_i_1/O
net (fo=4, unplaced) 0.497 4.709 delay_cnt
FDRE r delay_cnt_reg[1]/CE
------------------------------------------------------------------- -------------------
(clock wb_clk_i rise edge)
10.000 10.000 r
0.000 10.000 r wb_clk_i (IN)
net (fo=0) 0.000 10.000 wb_clk_i
r wb_clk_i_IBUF_inst/I
IBUF (Prop_ibuf_I_O) 0.838 10.838 r wb_clk_i_IBUF_inst/O
net (fo=1, unplaced) 0.760 11.598 wb_clk_i_IBUF
r wb_clk_i_IBUF_BUFG_inst/I
BUFG (Prop_bufg_I_O) 0.091 11.689 r wb_clk_i_IBUF_BUFG_inst/O
net (fo=13, unplaced) 0.439 12.128 wb_clk_i_IBUF_BUFG
FDRE r delay_cnt_reg[1]/C
clock pessimism 0.184 12.311
clock uncertainty -0.035 12.276
FDRE (Setup_fdre_C_CE) -0.202 12.074 delay_cnt_reg[1]
-------------------------------------------------------------------
required time 12.074
arrival time -4.709
-------------------------------------------------------------------
slack 7.365
Slack (MET) : 7.365ns (required time - arrival time)
Source: ack_reg/C
(rising edge-triggered cell FDRE clocked by wb_clk_i {[email protected] [email protected] period=10.000ns})
Destination: delay_cnt_reg[2]/CE
(rising edge-triggered cell FDRE clocked by wb_clk_i {[email protected] [email protected] period=10.000ns})
Path Group: wb_clk_i
Path Type: Setup (Max at Slow Process Corner)
Requirement: 10.000ns (wb_clk_i [email protected] - wb_clk_i [email protected])
Data Path Delay: 2.253ns (logic 0.773ns (34.310%) route 1.480ns (65.690%))
Logic Levels: 1 (LUT6=1)
Clock Path Skew: -0.145ns (DCD - SCD + CPR)
Destination Clock Delay (DCD): 2.128ns = ( 12.128 - 10.000 )
Source Clock Delay (SCD): 2.456ns
Clock Pessimism Removal (CPR): 0.184ns
Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
Total System Jitter (TSJ): 0.071ns
Total Input Jitter (TIJ): 0.000ns
Discrete Jitter (DJ): 0.000ns
Phase Error (PE): 0.000ns
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
------------------------------------------------------------------- -------------------
(clock wb_clk_i rise edge)
0.000 0.000 r
0.000 0.000 r wb_clk_i (IN)
net (fo=0) 0.000 0.000 wb_clk_i
r wb_clk_i_IBUF_inst/I
IBUF (Prop_ibuf_I_O) 0.972 0.972 r wb_clk_i_IBUF_inst/O
net (fo=1, unplaced) 0.800 1.771 wb_clk_i_IBUF
r wb_clk_i_IBUF_BUFG_inst/I
BUFG (Prop_bufg_I_O) 0.101 1.872 r wb_clk_i_IBUF_BUFG_inst/O
net (fo=13, unplaced) 0.584 2.456 wb_clk_i_IBUF_BUFG
FDRE r ack_reg/C
------------------------------------------------------------------- -------------------
FDRE (Prop_fdre_C_Q) 0.478 2.934 f ack_reg/Q
net (fo=3, unplaced) 0.983 3.917 wbs_ack_o_OBUF
f delay_cnt[3]_i_1/I1
LUT6 (Prop_lut6_I1_O) 0.295 4.212 r delay_cnt[3]_i_1/O
net (fo=4, unplaced) 0.497 4.709 delay_cnt
FDRE r delay_cnt_reg[2]/CE
------------------------------------------------------------------- -------------------
(clock wb_clk_i rise edge)
10.000 10.000 r
0.000 10.000 r wb_clk_i (IN)
net (fo=0) 0.000 10.000 wb_clk_i
r wb_clk_i_IBUF_inst/I
IBUF (Prop_ibuf_I_O) 0.838 10.838 r wb_clk_i_IBUF_inst/O
net (fo=1, unplaced) 0.760 11.598 wb_clk_i_IBUF
r wb_clk_i_IBUF_BUFG_inst/I
BUFG (Prop_bufg_I_O) 0.091 11.689 r wb_clk_i_IBUF_BUFG_inst/O
net (fo=13, unplaced) 0.439 12.128 wb_clk_i_IBUF_BUFG
FDRE r delay_cnt_reg[2]/C
clock pessimism 0.184 12.311
clock uncertainty -0.035 12.276
FDRE (Setup_fdre_C_CE) -0.202 12.074 delay_cnt_reg[2]
-------------------------------------------------------------------
required time 12.074
arrival time -4.709
-------------------------------------------------------------------
slack 7.365
Slack (MET) : 7.365ns (required time - arrival time)
Source: ack_reg/C
(rising edge-triggered cell FDRE clocked by wb_clk_i {[email protected] [email protected] period=10.000ns})
Destination: delay_cnt_reg[3]/CE
(rising edge-triggered cell FDRE clocked by wb_clk_i {[email protected] [email protected] period=10.000ns})
Path Group: wb_clk_i
Path Type: Setup (Max at Slow Process Corner)
Requirement: 10.000ns (wb_clk_i [email protected] - wb_clk_i [email protected])
Data Path Delay: 2.253ns (logic 0.773ns (34.310%) route 1.480ns (65.690%))
Logic Levels: 1 (LUT6=1)
Clock Path Skew: -0.145ns (DCD - SCD + CPR)
Destination Clock Delay (DCD): 2.128ns = ( 12.128 - 10.000 )
Source Clock Delay (SCD): 2.456ns
Clock Pessimism Removal (CPR): 0.184ns
Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
Total System Jitter (TSJ): 0.071ns
Total Input Jitter (TIJ): 0.000ns
Discrete Jitter (DJ): 0.000ns
Phase Error (PE): 0.000ns
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
------------------------------------------------------------------- -------------------
(clock wb_clk_i rise edge)
0.000 0.000 r
0.000 0.000 r wb_clk_i (IN)
net (fo=0) 0.000 0.000 wb_clk_i
r wb_clk_i_IBUF_inst/I
IBUF (Prop_ibuf_I_O) 0.972 0.972 r wb_clk_i_IBUF_inst/O
net (fo=1, unplaced) 0.800 1.771 wb_clk_i_IBUF
r wb_clk_i_IBUF_BUFG_inst/I
BUFG (Prop_bufg_I_O) 0.101 1.872 r wb_clk_i_IBUF_BUFG_inst/O
net (fo=13, unplaced) 0.584 2.456 wb_clk_i_IBUF_BUFG
FDRE r ack_reg/C
------------------------------------------------------------------- -------------------
FDRE (Prop_fdre_C_Q) 0.478 2.934 f ack_reg/Q
net (fo=3, unplaced) 0.983 3.917 wbs_ack_o_OBUF
f delay_cnt[3]_i_1/I1
LUT6 (Prop_lut6_I1_O) 0.295 4.212 r delay_cnt[3]_i_1/O
net (fo=4, unplaced) 0.497 4.709 delay_cnt
FDRE r delay_cnt_reg[3]/CE
------------------------------------------------------------------- -------------------
(clock wb_clk_i rise edge)
10.000 10.000 r
0.000 10.000 r wb_clk_i (IN)
net (fo=0) 0.000 10.000 wb_clk_i
r wb_clk_i_IBUF_inst/I
IBUF (Prop_ibuf_I_O) 0.838 10.838 r wb_clk_i_IBUF_inst/O
net (fo=1, unplaced) 0.760 11.598 wb_clk_i_IBUF
r wb_clk_i_IBUF_BUFG_inst/I
BUFG (Prop_bufg_I_O) 0.091 11.689 r wb_clk_i_IBUF_BUFG_inst/O
net (fo=13, unplaced) 0.439 12.128 wb_clk_i_IBUF_BUFG
FDRE r delay_cnt_reg[3]/C
clock pessimism 0.184 12.311
clock uncertainty -0.035 12.276
FDRE (Setup_fdre_C_CE) -0.202 12.074 delay_cnt_reg[3]
-------------------------------------------------------------------
required time 12.074
arrival time -4.709
-------------------------------------------------------------------
slack 7.365
Slack (MET) : 7.775ns (required time - arrival time)
Source: delay_cnt_reg[0]/C
(rising edge-triggered cell FDRE clocked by wb_clk_i {[email protected] [email protected] period=10.000ns})
Destination: ack_reg/D
(rising edge-triggered cell FDRE clocked by wb_clk_i {[email protected] [email protected] period=10.000ns})
Path Group: wb_clk_i
Path Type: Setup (Max at Slow Process Corner)
Requirement: 10.000ns (wb_clk_i [email protected] - wb_clk_i [email protected])
Data Path Delay: 2.089ns (logic 0.897ns (42.939%) route 1.192ns (57.061%))
Logic Levels: 2 (LUT4=2)
Clock Path Skew: -0.145ns (DCD - SCD + CPR)
Destination Clock Delay (DCD): 2.128ns = ( 12.128 - 10.000 )
Source Clock Delay (SCD): 2.456ns
Clock Pessimism Removal (CPR): 0.184ns
Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
Total System Jitter (TSJ): 0.071ns
Total Input Jitter (TIJ): 0.000ns
Discrete Jitter (DJ): 0.000ns
Phase Error (PE): 0.000ns
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
------------------------------------------------------------------- -------------------
(clock wb_clk_i rise edge)
0.000 0.000 r
0.000 0.000 r wb_clk_i (IN)
net (fo=0) 0.000 0.000 wb_clk_i
r wb_clk_i_IBUF_inst/I
IBUF (Prop_ibuf_I_O) 0.972 0.972 r wb_clk_i_IBUF_inst/O
net (fo=1, unplaced) 0.800 1.771 wb_clk_i_IBUF
r wb_clk_i_IBUF_BUFG_inst/I
BUFG (Prop_bufg_I_O) 0.101 1.872 r wb_clk_i_IBUF_BUFG_inst/O
net (fo=13, unplaced) 0.584 2.456 wb_clk_i_IBUF_BUFG
FDRE r delay_cnt_reg[0]/C
------------------------------------------------------------------- -------------------
FDRE (Prop_fdre_C_Q) 0.478 2.934 f delay_cnt_reg[0]/Q
net (fo=6, unplaced) 0.773 3.707 delay_cnt_reg_n_0_[0]
f ack_i_2/I1
LUT4 (Prop_lut4_I1_O) 0.295 4.002 r ack_i_2/O
net (fo=1, unplaced) 0.419 4.421 ack2_in
r ack_i_1/I1
LUT4 (Prop_lut4_I1_O) 0.124 4.545 r ack_i_1/O
net (fo=1, unplaced) 0.000 4.545 ack_i_1_n_0
FDRE r ack_reg/D
------------------------------------------------------------------- -------------------
(clock wb_clk_i rise edge)
10.000 10.000 r
0.000 10.000 r wb_clk_i (IN)
net (fo=0) 0.000 10.000 wb_clk_i
r wb_clk_i_IBUF_inst/I
IBUF (Prop_ibuf_I_O) 0.838 10.838 r wb_clk_i_IBUF_inst/O
net (fo=1, unplaced) 0.760 11.598 wb_clk_i_IBUF
r wb_clk_i_IBUF_BUFG_inst/I
BUFG (Prop_bufg_I_O) 0.091 11.689 r wb_clk_i_IBUF_BUFG_inst/O
net (fo=13, unplaced) 0.439 12.128 wb_clk_i_IBUF_BUFG
FDRE r ack_reg/C
clock pessimism 0.184 12.311
clock uncertainty -0.035 12.276
FDRE (Setup_fdre_C_D) 0.044 12.320 ack_reg
-------------------------------------------------------------------
required time 12.320
arrival time -4.545
-------------------------------------------------------------------
slack 7.775
Slack (MET) : 8.298ns (required time - arrival time)
Source: delay_cnt_reg[3]/C
(rising edge-triggered cell FDRE clocked by wb_clk_i {[email protected] [email protected] period=10.000ns})
Destination: delay_cnt_reg[0]/D
(rising edge-triggered cell FDRE clocked by wb_clk_i {[email protected] [email protected] period=10.000ns})
Path Group: wb_clk_i
Path Type: Setup (Max at Slow Process Corner)
Requirement: 10.000ns (wb_clk_i [email protected] - wb_clk_i [email protected])
Data Path Delay: 1.566ns (logic 0.797ns (50.894%) route 0.769ns (49.106%))
Logic Levels: 1 (LUT4=1)
Clock Path Skew: -0.145ns (DCD - SCD + CPR)
Destination Clock Delay (DCD): 2.128ns = ( 12.128 - 10.000 )
Source Clock Delay (SCD): 2.456ns
Clock Pessimism Removal (CPR): 0.184ns
Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
Total System Jitter (TSJ): 0.071ns
Total Input Jitter (TIJ): 0.000ns
Discrete Jitter (DJ): 0.000ns
Phase Error (PE): 0.000ns
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
------------------------------------------------------------------- -------------------
(clock wb_clk_i rise edge)
0.000 0.000 r
0.000 0.000 r wb_clk_i (IN)
net (fo=0) 0.000 0.000 wb_clk_i
r wb_clk_i_IBUF_inst/I
IBUF (Prop_ibuf_I_O) 0.972 0.972 r wb_clk_i_IBUF_inst/O
net (fo=1, unplaced) 0.800 1.771 wb_clk_i_IBUF
r wb_clk_i_IBUF_BUFG_inst/I
BUFG (Prop_bufg_I_O) 0.101 1.872 r wb_clk_i_IBUF_BUFG_inst/O
net (fo=13, unplaced) 0.584 2.456 wb_clk_i_IBUF_BUFG
FDRE r delay_cnt_reg[3]/C
------------------------------------------------------------------- -------------------
FDRE (Prop_fdre_C_Q) 0.478 2.934 f delay_cnt_reg[3]/Q
net (fo=5, unplaced) 0.769 3.703 delay_cnt_reg_n_0_[3]
f delay_cnt[0]_i_1/I1
LUT4 (Prop_lut4_I1_O) 0.319 4.022 r delay_cnt[0]_i_1/O
net (fo=1, unplaced) 0.000 4.022 delay_cnt[0]_i_1_n_0
FDRE r delay_cnt_reg[0]/D
------------------------------------------------------------------- -------------------
(clock wb_clk_i rise edge)
10.000 10.000 r
0.000 10.000 r wb_clk_i (IN)
net (fo=0) 0.000 10.000 wb_clk_i
r wb_clk_i_IBUF_inst/I
IBUF (Prop_ibuf_I_O) 0.838 10.838 r wb_clk_i_IBUF_inst/O
net (fo=1, unplaced) 0.760 11.598 wb_clk_i_IBUF
r wb_clk_i_IBUF_BUFG_inst/I
BUFG (Prop_bufg_I_O) 0.091 11.689 r wb_clk_i_IBUF_BUFG_inst/O
net (fo=13, unplaced) 0.439 12.128 wb_clk_i_IBUF_BUFG
FDRE r delay_cnt_reg[0]/C
clock pessimism 0.184 12.311
clock uncertainty -0.035 12.276
FDRE (Setup_fdre_C_D) 0.044 12.320 delay_cnt_reg[0]
-------------------------------------------------------------------
required time 12.320
arrival time -4.022
-------------------------------------------------------------------
slack 8.298
Slack (MET) : 8.298ns (required time - arrival time)
Source: delay_cnt_reg[3]/C
(rising edge-triggered cell FDRE clocked by wb_clk_i {[email protected] [email protected] period=10.000ns})
Destination: delay_cnt_reg[3]/D
(rising edge-triggered cell FDRE clocked by wb_clk_i {[email protected] [email protected] period=10.000ns})
Path Group: wb_clk_i
Path Type: Setup (Max at Slow Process Corner)
Requirement: 10.000ns (wb_clk_i [email protected] - wb_clk_i [email protected])
Data Path Delay: 1.566ns (logic 0.797ns (50.894%) route 0.769ns (49.106%))
Logic Levels: 1 (LUT4=1)
Clock Path Skew: -0.145ns (DCD - SCD + CPR)
Destination Clock Delay (DCD): 2.128ns = ( 12.128 - 10.000 )
Source Clock Delay (SCD): 2.456ns
Clock Pessimism Removal (CPR): 0.184ns
Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
Total System Jitter (TSJ): 0.071ns
Total Input Jitter (TIJ): 0.000ns
Discrete Jitter (DJ): 0.000ns
Phase Error (PE): 0.000ns
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
------------------------------------------------------------------- -------------------
(clock wb_clk_i rise edge)
0.000 0.000 r
0.000 0.000 r wb_clk_i (IN)
net (fo=0) 0.000 0.000 wb_clk_i
r wb_clk_i_IBUF_inst/I
IBUF (Prop_ibuf_I_O) 0.972 0.972 r wb_clk_i_IBUF_inst/O
net (fo=1, unplaced) 0.800 1.771 wb_clk_i_IBUF
r wb_clk_i_IBUF_BUFG_inst/I
BUFG (Prop_bufg_I_O) 0.101 1.872 r wb_clk_i_IBUF_BUFG_inst/O
net (fo=13, unplaced) 0.584 2.456 wb_clk_i_IBUF_BUFG
FDRE r delay_cnt_reg[3]/C
------------------------------------------------------------------- -------------------
FDRE (Prop_fdre_C_Q) 0.478 2.934 r delay_cnt_reg[3]/Q
net (fo=5, unplaced) 0.769 3.703 delay_cnt_reg_n_0_[3]
r delay_cnt[3]_i_2/I1
LUT4 (Prop_lut4_I1_O) 0.319 4.022 r delay_cnt[3]_i_2/O
net (fo=1, unplaced) 0.000 4.022 delay_cnt[3]_i_2_n_0
FDRE r delay_cnt_reg[3]/D
------------------------------------------------------------------- -------------------
(clock wb_clk_i rise edge)
10.000 10.000 r
0.000 10.000 r wb_clk_i (IN)
net (fo=0) 0.000 10.000 wb_clk_i
r wb_clk_i_IBUF_inst/I
IBUF (Prop_ibuf_I_O) 0.838 10.838 r wb_clk_i_IBUF_inst/O
net (fo=1, unplaced) 0.760 11.598 wb_clk_i_IBUF
r wb_clk_i_IBUF_BUFG_inst/I
BUFG (Prop_bufg_I_O) 0.091 11.689 r wb_clk_i_IBUF_BUFG_inst/O
net (fo=13, unplaced) 0.439 12.128 wb_clk_i_IBUF_BUFG
FDRE r delay_cnt_reg[3]/C
clock pessimism 0.184 12.311
clock uncertainty -0.035 12.276
FDRE (Setup_fdre_C_D) 0.044 12.320 delay_cnt_reg[3]
-------------------------------------------------------------------
required time 12.320
arrival time -4.022
-------------------------------------------------------------------
slack 8.298
Slack (MET) : 8.318ns (required time - arrival time)
Source: delay_cnt_reg[1]/C
(rising edge-triggered cell FDRE clocked by wb_clk_i {[email protected] [email protected] period=10.000ns})
Destination: delay_cnt_reg[2]/D
(rising edge-triggered cell FDRE clocked by wb_clk_i {[email protected] [email protected] period=10.000ns})
Path Group: wb_clk_i
Path Type: Setup (Max at Slow Process Corner)
Requirement: 10.000ns (wb_clk_i [email protected] - wb_clk_i [email protected])
Data Path Delay: 1.546ns (logic 0.773ns (50.000%) route 0.773ns (50.000%))
Logic Levels: 1 (LUT3=1)
Clock Path Skew: -0.145ns (DCD - SCD + CPR)
Destination Clock Delay (DCD): 2.128ns = ( 12.128 - 10.000 )
Source Clock Delay (SCD): 2.456ns
Clock Pessimism Removal (CPR): 0.184ns
Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
Total System Jitter (TSJ): 0.071ns
Total Input Jitter (TIJ): 0.000ns
Discrete Jitter (DJ): 0.000ns
Phase Error (PE): 0.000ns
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
------------------------------------------------------------------- -------------------
(clock wb_clk_i rise edge)
0.000 0.000 r
0.000 0.000 r wb_clk_i (IN)
net (fo=0) 0.000 0.000 wb_clk_i
r wb_clk_i_IBUF_inst/I
IBUF (Prop_ibuf_I_O) 0.972 0.972 r wb_clk_i_IBUF_inst/O
net (fo=1, unplaced) 0.800 1.771 wb_clk_i_IBUF
r wb_clk_i_IBUF_BUFG_inst/I
BUFG (Prop_bufg_I_O) 0.101 1.872 r wb_clk_i_IBUF_BUFG_inst/O
net (fo=13, unplaced) 0.584 2.456 wb_clk_i_IBUF_BUFG
FDRE r delay_cnt_reg[1]/C
------------------------------------------------------------------- -------------------
FDRE (Prop_fdre_C_Q) 0.478 2.934 r delay_cnt_reg[1]/Q
net (fo=6, unplaced) 0.773 3.707 delay_cnt_reg_n_0_[1]
r delay_cnt[2]_i_1/I0
LUT3 (Prop_lut3_I0_O) 0.295 4.002 r delay_cnt[2]_i_1/O
net (fo=1, unplaced) 0.000 4.002 delay_cnt[2]_i_1_n_0
FDRE r delay_cnt_reg[2]/D
------------------------------------------------------------------- -------------------
(clock wb_clk_i rise edge)
10.000 10.000 r
0.000 10.000 r wb_clk_i (IN)
net (fo=0) 0.000 10.000 wb_clk_i
r wb_clk_i_IBUF_inst/I
IBUF (Prop_ibuf_I_O) 0.838 10.838 r wb_clk_i_IBUF_inst/O
net (fo=1, unplaced) 0.760 11.598 wb_clk_i_IBUF
r wb_clk_i_IBUF_BUFG_inst/I
BUFG (Prop_bufg_I_O) 0.091 11.689 r wb_clk_i_IBUF_BUFG_inst/O
net (fo=13, unplaced) 0.439 12.128 wb_clk_i_IBUF_BUFG
FDRE r delay_cnt_reg[2]/C
clock pessimism 0.184 12.311
clock uncertainty -0.035 12.276
FDRE (Setup_fdre_C_D) 0.044 12.320 delay_cnt_reg[2]
-------------------------------------------------------------------
required time 12.320
arrival time -4.002
-------------------------------------------------------------------
slack 8.318
Slack (MET) : 8.322ns (required time - arrival time)
Source: delay_cnt_reg[3]/C
(rising edge-triggered cell FDRE clocked by wb_clk_i {[email protected] [email protected] period=10.000ns})
Destination: delay_cnt_reg[1]/D
(rising edge-triggered cell FDRE clocked by wb_clk_i {[email protected] [email protected] period=10.000ns})
Path Group: wb_clk_i
Path Type: Setup (Max at Slow Process Corner)
Requirement: 10.000ns (wb_clk_i [email protected] - wb_clk_i [email protected])
Data Path Delay: 1.542ns (logic 0.773ns (50.130%) route 0.769ns (49.870%))
Logic Levels: 1 (LUT4=1)
Clock Path Skew: -0.145ns (DCD - SCD + CPR)
Destination Clock Delay (DCD): 2.128ns = ( 12.128 - 10.000 )
Source Clock Delay (SCD): 2.456ns
Clock Pessimism Removal (CPR): 0.184ns
Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
Total System Jitter (TSJ): 0.071ns
Total Input Jitter (TIJ): 0.000ns
Discrete Jitter (DJ): 0.000ns
Phase Error (PE): 0.000ns
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
------------------------------------------------------------------- -------------------
(clock wb_clk_i rise edge)
0.000 0.000 r
0.000 0.000 r wb_clk_i (IN)
net (fo=0) 0.000 0.000 wb_clk_i
r wb_clk_i_IBUF_inst/I
IBUF (Prop_ibuf_I_O) 0.972 0.972 r wb_clk_i_IBUF_inst/O
net (fo=1, unplaced) 0.800 1.771 wb_clk_i_IBUF
r wb_clk_i_IBUF_BUFG_inst/I
BUFG (Prop_bufg_I_O) 0.101 1.872 r wb_clk_i_IBUF_BUFG_inst/O
net (fo=13, unplaced) 0.584 2.456 wb_clk_i_IBUF_BUFG
FDRE r delay_cnt_reg[3]/C
------------------------------------------------------------------- -------------------
FDRE (Prop_fdre_C_Q) 0.478 2.934 f delay_cnt_reg[3]/Q
net (fo=5, unplaced) 0.769 3.703 delay_cnt_reg_n_0_[3]
f delay_cnt[1]_i_1/I1
LUT4 (Prop_lut4_I1_O) 0.295 3.998 r delay_cnt[1]_i_1/O
net (fo=1, unplaced) 0.000 3.998 delay_cnt[1]_i_1_n_0
FDRE r delay_cnt_reg[1]/D
------------------------------------------------------------------- -------------------
(clock wb_clk_i rise edge)
10.000 10.000 r
0.000 10.000 r wb_clk_i (IN)
net (fo=0) 0.000 10.000 wb_clk_i
r wb_clk_i_IBUF_inst/I
IBUF (Prop_ibuf_I_O) 0.838 10.838 r wb_clk_i_IBUF_inst/O
net (fo=1, unplaced) 0.760 11.598 wb_clk_i_IBUF
r wb_clk_i_IBUF_BUFG_inst/I
BUFG (Prop_bufg_I_O) 0.091 11.689 r wb_clk_i_IBUF_BUFG_inst/O
net (fo=13, unplaced) 0.439 12.128 wb_clk_i_IBUF_BUFG
FDRE r delay_cnt_reg[1]/C
clock pessimism 0.184 12.311
clock uncertainty -0.035 12.276
FDRE (Setup_fdre_C_D) 0.044 12.320 delay_cnt_reg[1]
-------------------------------------------------------------------
required time 12.320
arrival time -3.998
-------------------------------------------------------------------
slack 8.322
Min Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) : 0.146ns (arrival time - required time)
Source: delay_cnt_reg[2]/C
(rising edge-triggered cell FDRE clocked by wb_clk_i {[email protected] [email protected] period=10.000ns})
Destination: delay_cnt_reg[1]/D
(rising edge-triggered cell FDRE clocked by wb_clk_i {[email protected] [email protected] period=10.000ns})
Path Group: wb_clk_i
Path Type: Hold (Min at Fast Process Corner)
Requirement: 0.000ns (wb_clk_i [email protected] - wb_clk_i [email protected])
Data Path Delay: 0.390ns (logic 0.245ns (62.888%) route 0.145ns (37.112%))
Logic Levels: 1 (LUT4=1)
Clock Path Skew: 0.145ns (DCD - SCD - CPR)
Destination Clock Delay (DCD): 1.032ns
Source Clock Delay (SCD): 0.678ns
Clock Pessimism Removal (CPR): 0.210ns
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
------------------------------------------------------------------- -------------------
(clock wb_clk_i rise edge)
0.000 0.000 r
0.000 0.000 r wb_clk_i (IN)
net (fo=0) 0.000 0.000 wb_clk_i
r wb_clk_i_IBUF_inst/I
IBUF (Prop_ibuf_I_O) 0.200 0.200 r wb_clk_i_IBUF_inst/O
net (fo=1, unplaced) 0.337 0.538 wb_clk_i_IBUF
r wb_clk_i_IBUF_BUFG_inst/I
BUFG (Prop_bufg_I_O) 0.026 0.564 r wb_clk_i_IBUF_BUFG_inst/O
net (fo=13, unplaced) 0.114 0.678 wb_clk_i_IBUF_BUFG
FDRE r delay_cnt_reg[2]/C
------------------------------------------------------------------- -------------------
FDRE (Prop_fdre_C_Q) 0.147 0.825 r delay_cnt_reg[2]/Q
net (fo=6, unplaced) 0.145 0.969 delay_cnt_reg_n_0_[2]
r delay_cnt[1]_i_1/I3
LUT4 (Prop_lut4_I3_O) 0.098 1.067 r delay_cnt[1]_i_1/O
net (fo=1, unplaced) 0.000 1.067 delay_cnt[1]_i_1_n_0
FDRE r delay_cnt_reg[1]/D
------------------------------------------------------------------- -------------------
(clock wb_clk_i rise edge)
0.000 0.000 r
0.000 0.000 r wb_clk_i (IN)
net (fo=0) 0.000 0.000 wb_clk_i
r wb_clk_i_IBUF_inst/I
IBUF (Prop_ibuf_I_O) 0.389 0.389 r wb_clk_i_IBUF_inst/O
net (fo=1, unplaced) 0.355 0.744 wb_clk_i_IBUF
r wb_clk_i_IBUF_BUFG_inst/I
BUFG (Prop_bufg_I_O) 0.029 0.773 r wb_clk_i_IBUF_BUFG_inst/O
net (fo=13, unplaced) 0.259 1.032 wb_clk_i_IBUF_BUFG
FDRE r delay_cnt_reg[1]/C
clock pessimism -0.210 0.823
FDRE (Hold_fdre_C_D) 0.099 0.922 delay_cnt_reg[1]
-------------------------------------------------------------------
required time -0.922
arrival time 1.067
-------------------------------------------------------------------
slack 0.146
Slack (MET) : 0.146ns (arrival time - required time)
Source: delay_cnt_reg[2]/C
(rising edge-triggered cell FDRE clocked by wb_clk_i {[email protected] [email protected] period=10.000ns})
Destination: delay_cnt_reg[2]/D
(rising edge-triggered cell FDRE clocked by wb_clk_i {[email protected] [email protected] period=10.000ns})
Path Group: wb_clk_i
Path Type: Hold (Min at Fast Process Corner)
Requirement: 0.000ns (wb_clk_i [email protected] - wb_clk_i [email protected])
Data Path Delay: 0.390ns (logic 0.245ns (62.888%) route 0.145ns (37.112%))
Logic Levels: 1 (LUT3=1)
Clock Path Skew: 0.145ns (DCD - SCD - CPR)
Destination Clock Delay (DCD): 1.032ns
Source Clock Delay (SCD): 0.678ns
Clock Pessimism Removal (CPR): 0.210ns
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
------------------------------------------------------------------- -------------------
(clock wb_clk_i rise edge)
0.000 0.000 r
0.000 0.000 r wb_clk_i (IN)
net (fo=0) 0.000 0.000 wb_clk_i
r wb_clk_i_IBUF_inst/I
IBUF (Prop_ibuf_I_O) 0.200 0.200 r wb_clk_i_IBUF_inst/O
net (fo=1, unplaced) 0.337 0.538 wb_clk_i_IBUF
r wb_clk_i_IBUF_BUFG_inst/I
BUFG (Prop_bufg_I_O) 0.026 0.564 r wb_clk_i_IBUF_BUFG_inst/O
net (fo=13, unplaced) 0.114 0.678 wb_clk_i_IBUF_BUFG
FDRE r delay_cnt_reg[2]/C
------------------------------------------------------------------- -------------------
FDRE (Prop_fdre_C_Q) 0.147 0.825 r delay_cnt_reg[2]/Q
net (fo=6, unplaced) 0.145 0.969 delay_cnt_reg_n_0_[2]
r delay_cnt[2]_i_1/I2
LUT3 (Prop_lut3_I2_O) 0.098 1.067 r delay_cnt[2]_i_1/O
net (fo=1, unplaced) 0.000 1.067 delay_cnt[2]_i_1_n_0
FDRE r delay_cnt_reg[2]/D
------------------------------------------------------------------- -------------------
(clock wb_clk_i rise edge)
0.000 0.000 r
0.000 0.000 r wb_clk_i (IN)
net (fo=0) 0.000 0.000 wb_clk_i
r wb_clk_i_IBUF_inst/I
IBUF (Prop_ibuf_I_O) 0.389 0.389 r wb_clk_i_IBUF_inst/O
net (fo=1, unplaced) 0.355 0.744 wb_clk_i_IBUF
r wb_clk_i_IBUF_BUFG_inst/I
BUFG (Prop_bufg_I_O) 0.029 0.773 r wb_clk_i_IBUF_BUFG_inst/O
net (fo=13, unplaced) 0.259 1.032 wb_clk_i_IBUF_BUFG
FDRE r delay_cnt_reg[2]/C
clock pessimism -0.210 0.823
FDRE (Hold_fdre_C_D) 0.099 0.922 delay_cnt_reg[2]
-------------------------------------------------------------------
required time -0.922
arrival time 1.067
-------------------------------------------------------------------
slack 0.146
Slack (MET) : 0.149ns (arrival time - required time)
Source: delay_cnt_reg[2]/C
(rising edge-triggered cell FDRE clocked by wb_clk_i {[email protected] [email protected] period=10.000ns})
Destination: delay_cnt_reg[0]/D
(rising edge-triggered cell FDRE clocked by wb_clk_i {[email protected] [email protected] period=10.000ns})
Path Group: wb_clk_i