{"payload":{"feedbackUrl":"https://github.com/orgs/community/discussions/53140","repo":{"id":289094803,"defaultBranch":"master","name":"verilog-ethernet","ownerLogin":"corundum","currentUserCanPush":false,"isFork":true,"isEmpty":false,"createdAt":"2020-08-20T19:38:35.000Z","ownerAvatar":"https://avatars.githubusercontent.com/u/69613510?v=4","public":true,"private":false,"isOrgOwned":true},"refInfo":{"name":"","listCacheKey":"v0:1613540690.052453","currentOid":""},"activityList":{"items":[{"before":"84004c720dd1a873db96632c9c766badf1de59be","after":"77adf30dad1883e1603cf99fe036339a25b79007","ref":"refs/heads/master","pushedAt":"2023-06-26T02:03:57.817Z","pushType":"push","commitsCount":67,"pusher":{"login":"alexforencich","name":"Alex Forencich","path":"/alexforencich","primaryAvatarUrl":"https://avatars.githubusercontent.com/u/508807?s=80&v=4"},"commit":{"message":"Add missing serdes_rx_reset_req output to 10G MAC+PHY modules\n\nSigned-off-by: Alex Forencich ","shortMessageHtmlLink":"Add missing serdes_rx_reset_req output to 10G MAC+PHY modules"}},{"before":"84004c720dd1a873db96632c9c766badf1de59be","after":"77adf30dad1883e1603cf99fe036339a25b79007","ref":"refs/heads/master","pushedAt":"2023-06-26T02:03:57.754Z","pushType":"push","commitsCount":67,"pusher":{"login":"alexforencich","name":"Alex Forencich","path":"/alexforencich","primaryAvatarUrl":"https://avatars.githubusercontent.com/u/508807?s=80&v=4"},"commit":{"message":"Add missing serdes_rx_reset_req output to 10G MAC+PHY modules\n\nSigned-off-by: Alex Forencich ","shortMessageHtmlLink":"Add missing serdes_rx_reset_req output to 10G MAC+PHY modules"}}],"hasNextPage":false,"hasPreviousPage":false,"activityType":"all","actor":null,"timePeriod":"all","sort":"DESC","perPage":30,"startCursor":"Y3Vyc29yOnYyOpK7MjAyMy0wNi0yNlQwMjowMzo1Ny44MTc3NTRazwAAAANItZX1","endCursor":"Y3Vyc29yOnYyOpK7MjAyMy0wNi0yNlQwMjowMzo1Ny43NTQ0NDlazwAAAANItZX8"}},"title":"Activity ยท corundum/verilog-ethernet"}