diff --git a/riscv-test-suite/env/encoding.h b/riscv-test-suite/env/encoding.h
index 1ee1285be..6c889e0b0 100755
--- a/riscv-test-suite/env/encoding.h
+++ b/riscv-test-suite/env/encoding.h
@@ -131,6 +131,42 @@
 #define SIP_SSIP MIP_SSIP
 #define SIP_STIP MIP_STIP
 
+#define MENVCFG_FIOM  0x00000001
+#define MENVCFG_CBIE  0x00000030
+#define MENVCFG_CBCFE 0x00000040
+#define MENVCFG_CBZE  0x00000080
+#define MENVCFG_DTSO  0x00000100
+#define MENVCFG_ADUE  0x2000000000000000
+#define MENVCFG_PBMTE 0x4000000000000000
+#define MENVCFG_STCE  0x8000000000000000
+
+#define MENVCFGH_ADUE  0x20000000
+#define MENVCFGH_PBMTE 0x40000000
+#define MENVCFGH_STCE  0x80000000
+
+#define MSTATEEN0_HENVCFG  0x4000000000000000
+#define MSTATEEN0H_HENVCFG  0x40000000
+#define HENVCFG_FIOM  0x00000001
+#define HENVCFG_CBIE  0x00000030
+#define HENVCFG_CBCFE 0x00000040
+#define HENVCFG_CBZE  0x00000080
+#define HENVCFG_DTSO  0x00000100
+#define HENVCFG_ADUE  0x2000000000000000
+#define HENVCFG_PBMTE 0x4000000000000000
+#define HENVCFG_STCE  0x8000000000000000
+
+#define HENVCFGH_ADUE  0x20000000
+#define HENVCFGH_PBMTE 0x40000000
+#define HENVCFGH_STCE  0x80000000
+
+#define HSTATEEN0_SENVCFG  0x4000000000000000
+#define HSTATEEN0H_SENVCFG  0x40000000
+#define SENVCFG_FIOM  0x00000001
+#define SENVCFG_CBIE  0x00000030
+#define SENVCFG_CBCFE 0x00000040
+#define SENVCFG_CBZE  0x00000080
+#define SENVCFG_DTSO  0x00000100
+
 #define PRV_U 0
 #define PRV_S 1
 #define PRV_H 2
@@ -813,6 +849,7 @@
 #define CSR_SIE 0x104
 #define CSR_STVEC 0x105
 #define CSR_SCOUNTEREN 0x106
+#define CSR_SENVCFG 0x10a
 #define CSR_SSCRATCH 0x140
 #define CSR_SEPC 0x141
 #define CSR_SCAUSE 0x142
@@ -820,6 +857,7 @@
 #define CSR_SIP 0x144
 #define CSR_SATP 0x180
 #define CSR_SEDELEG 0x102
+#define CSR_HENVCFG 0x60a
 #define CSR_MSTATUS 0x300
 #define CSR_MSTATUSH 0x310
 #define CSR_MISA 0x301
@@ -828,6 +866,7 @@
 #define CSR_MIE 0x304
 #define CSR_MTVEC 0x305
 #define CSR_MCOUNTEREN 0x306
+#define CSR_MENVCFG 0x30a
 #define CSR_MSCRATCH 0x340
 #define CSR_MEPC 0x341
 #define CSR_MCAUSE 0x342
@@ -924,6 +963,7 @@
 #define CSR_MARCHID 0xf12
 #define CSR_MIMPID 0xf13
 #define CSR_MHARTID 0xf14
+#define CSR_HENVCFGH 0x61a
 #define CSR_CYCLEH 0xc80
 #define CSR_TIMEH 0xc81
 #define CSR_INSTRETH 0xc82
@@ -956,6 +996,7 @@
 #define CSR_HPMCOUNTER29H 0xc9d
 #define CSR_HPMCOUNTER30H 0xc9e
 #define CSR_HPMCOUNTER31H 0xc9f
+#define CSR_MENVCFGH 0x31a
 #define CSR_MCYCLEH 0xb80
 #define CSR_MINSTRETH 0xb82
 #define CSR_MHPMCOUNTER3H 0xb83
@@ -1309,12 +1350,14 @@ DECLARE_CSR(sstatus, CSR_SSTATUS)
 DECLARE_CSR(sie, CSR_SIE)
 DECLARE_CSR(stvec, CSR_STVEC)
 DECLARE_CSR(scounteren, CSR_SCOUNTEREN)
+DECLARE_CSR(senvcfg, CSR_SENVCFG)
 DECLARE_CSR(sscratch, CSR_SSCRATCH)
 DECLARE_CSR(sepc, CSR_SEPC)
 DECLARE_CSR(scause, CSR_SCAUSE)
 DECLARE_CSR(stval, CSR_STVAL)
 DECLARE_CSR(sip, CSR_SIP)
 DECLARE_CSR(satp, CSR_SATP)
+DECLARE_CSR(henvcfg, CSR_HENVCFG)
 DECLARE_CSR(mstatus, CSR_MSTATUS)
 DECLARE_CSR(mstatush, CSR_MSTATUSH)
 DECLARE_CSR(hstatus, CSR_HSTATUS)
@@ -1324,6 +1367,7 @@ DECLARE_CSR(mideleg, CSR_MIDELEG)
 DECLARE_CSR(mie, CSR_MIE)
 DECLARE_CSR(mtvec, CSR_MTVEC)
 DECLARE_CSR(mcounteren, CSR_MCOUNTEREN)
+DECLARE_CSR(menvcfg, CSR_MENVCFG)
 DECLARE_CSR(mscratch, CSR_MSCRATCH)
 DECLARE_CSR(mepc, CSR_MEPC)
 DECLARE_CSR(mcause, CSR_MCAUSE)
@@ -1420,6 +1464,7 @@ DECLARE_CSR(mvendorid, CSR_MVENDORID)
 DECLARE_CSR(marchid, CSR_MARCHID)
 DECLARE_CSR(mimpid, CSR_MIMPID)
 DECLARE_CSR(mhartid, CSR_MHARTID)
+DECLARE_CSR(henvcfgh, CSR_HENVCFGH)
 DECLARE_CSR(cycleh, CSR_CYCLEH)
 DECLARE_CSR(timeh, CSR_TIMEH)
 DECLARE_CSR(instreth, CSR_INSTRETH)
@@ -1452,6 +1497,7 @@ DECLARE_CSR(hpmcounter28h, CSR_HPMCOUNTER28H)
 DECLARE_CSR(hpmcounter29h, CSR_HPMCOUNTER29H)
 DECLARE_CSR(hpmcounter30h, CSR_HPMCOUNTER30H)
 DECLARE_CSR(hpmcounter31h, CSR_HPMCOUNTER31H)
+DECLARE_CSR(menvcfgh, CSR_MENVCFGH)
 DECLARE_CSR(mcycleh, CSR_MCYCLEH)
 DECLARE_CSR(minstreth, CSR_MINSTRETH)
 DECLARE_CSR(mhpmcounter3h, CSR_MHPMCOUNTER3H)
diff --git a/riscv-test-suite/rv32i_m/privilege/src/menvcfg.S b/riscv-test-suite/rv32i_m/privilege/src/menvcfg.S
new file mode 100644
index 000000000..3f67b0368
--- /dev/null
+++ b/riscv-test-suite/rv32i_m/privilege/src/menvcfg.S
@@ -0,0 +1,106 @@
+// -----------
+// Copyright (c) 2023. RISC-V International. All rights reserved.
+// SPDX-License-Identifier: BSD-3-Clause
+// -----------
+//
+// This assembly file tests the menvcfg CSR access.
+// 
+
+#include "model_test.h"
+#include "arch_test.h"
+
+RVTEST_ISA("RV32I_Zicbom_Zicboz_Zicsr_Ssdtso_Sstc")
+
+# Test code region
+.section .text.init
+.globl rvtest_entry_point
+rvtest_entry_point:
+RVMODEL_BOOT
+RVTEST_CODE_BEGIN
+
+RVTEST_SIGBASE(a1,signature_a1_m)
+
+#define VAL_POS(VALUE, POSITION) ((VALUE) << (POSITION))
+#define CSR_SET_BIT(CSR, TMP1, TMP2, BIT) \
+    csrr    TMP1, CSR \
+    LI(BIT
+
+#ifdef TEST_CASE_1
+
+RVTEST_CASE(0,"//check ISA:=regex(.*I.*Zicbom.*Zicboz.*Zicsr.*Ssdtso.*Sstc); def rvtest_mtrap_routine=True; def TEST_CASE_1=True",menvcfg)
+
+inst_0:
+// Simple read of the CSR's original value
+csrr  t2, CSR_MENVCFG
+RVTEST_SIGUPD(a1, t2)
+
+inst_1:
+ori  t1, t2, MENVCFG_FIOM
+csrw  CSR_MENVCFG, t1
+csrr  t0, CSR_MENVCFG
+RVTEST_SIGUPD(a1, t0)
+
+inst_2:
+ori  t1, t2, MENVCFG_CBIE
+csrw  CSR_MENVCFG, t1
+csrr  t0, CSR_MENVCFG
+RVTEST_SIGUPD(a1, t0)
+
+inst_3:
+ori  t1, t2, MENVCFG_CBCFE
+csrw  CSR_MENVCFG, t1
+csrr  t0, CSR_MENVCFG
+RVTEST_SIGUPD(a1, t0)
+
+inst4:
+ori  t1, t2, MENVCFG_CBZE
+csrw  CSR_MENVCFG, t1
+csrr  t0, CSR_MENVCFG
+RVTEST_SIGUPD(a1, t0)
+
+inst5:
+ori  t1, t2, MENVCFG_DTSO
+csrw  CSR_MENVCFG, t1
+csrr  t0, CSR_MENVCFG
+RVTEST_SIGUPD(a1, t0)
+
+instLAST:
+// Restore the CSR's original value
+csrw  CSR_MENVCFG, t2
+csrr  t0, CSR_MENVCFG
+RVTEST_SIGUPD(a1, t0)
+
+
+#endif
+
+
+RVTEST_CODE_END
+RVMODEL_HALT
+
+RVTEST_DATA_BEGIN
+# Input data section.
+    .data
+    .align 4
+RVTEST_DATA_END
+
+# Output data section.
+RVMODEL_DATA_BEGIN
+rvtest_sig_begin:
+signature_a1_m:
+    .fill 32*(XLEN/32),4,0xdeadbeef
+
+sig_begin_canary:
+CANARY;
+
+mtrap_sigptr:
+  .fill 4, 4, 0xdeadbeef
+
+#ifdef rvtest_gpr_save
+gpr_save:
+  .fill 32*(XLEN/32), 4, 0xdeadbeef
+#endif
+
+sig_end_canary:
+CANARY;
+rvtest_sig_end:
+RVMODEL_DATA_END