From a5216a1104bafd27354b969a391af80d10ea784c Mon Sep 17 00:00:00 2001 From: Jan Bylicki Date: Fri, 5 May 2023 11:15:17 +0200 Subject: [PATCH] formatter_test: Added end-to-end always_wrap_module_instantiations tests Signed-off-by: Jan Bylicki --- verilog/formatting/formatter_test.cc | 37 ++++++++++++++++++++++++++++ 1 file changed, 37 insertions(+) diff --git a/verilog/formatting/formatter_test.cc b/verilog/formatting/formatter_test.cc index 89883077c..83b636fa6 100644 --- a/verilog/formatting/formatter_test.cc +++ b/verilog/formatting/formatter_test.cc @@ -15438,6 +15438,43 @@ TEST(FormatterEndToEndTest, VerilogFormatTest) { } } +TEST(FormatterEndToEndTest, AlwaysWrapModuleInstantiation) { + static constexpr FormatterTestCase kTestCases[] = { + {" module foo ; bar bq();endmodule\n", + "module foo;\n" + " bar bq ();\n" // single instance + "endmodule\n"}, + {" module foo ; bar bq(), bq2( );endmodule\n", + "module foo;\n" + " bar bq (), bq2 ();\n" // multiple empty instances, still fitting on + // one line + "endmodule\n"}, + {"module foo; bar #(.N(N)) bq (.bus(bus));endmodule\n", + // instance parameter and port fits on line + "module foo;\n" + " bar #(\n .N(N)\n ) bq (\n .bus(bus)\n );\n" + "endmodule\n"}, + {"module foo; bar bq (.bus(bus));endmodule\n", + "module foo;\n" + " bar bq (\n .bus(bus)\n );\n" + "endmodule\n"}, + }; + FormatStyle style; + style.column_limit = 40; + style.indentation_spaces = 2; + style.wrap_spaces = 4; + style.always_wrap_module_instantiations = true; + for (const auto& test_case : kTestCases) { + VLOG(1) << "code-to-format:\n" << test_case.input << ""; + std::ostringstream stream; + const auto status = + FormatVerilog(test_case.input, "", style, stream); + // Require these test cases to be valid. + EXPECT_OK(status) << status.message(); + EXPECT_EQ(stream.str(), test_case.expected) << "code:\n" << test_case.input; + } +} + TEST(FormatterEndToEndTest, AutoInferAlignment) { static constexpr FormatterTestCase kTestCases[] = { {"", ""},