From ce4da50a0afa95994742c625d912fa43f5f66745 Mon Sep 17 00:00:00 2001 From: Takehana Date: Thu, 13 Jul 2023 14:43:18 +0800 Subject: [PATCH] migrate TLBroadcast to chisel3 --- src/main/scala/tilelink/Broadcast.scala | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/src/main/scala/tilelink/Broadcast.scala b/src/main/scala/tilelink/Broadcast.scala index f28bb4c9e88..2e95d1e54be 100644 --- a/src/main/scala/tilelink/Broadcast.scala +++ b/src/main/scala/tilelink/Broadcast.scala @@ -118,7 +118,7 @@ class TLBroadcast(params: TLBroadcastParams)(implicit p: Parameters) extends Laz val d_what = out.d.bits.source(d_high+1, d_high) val d_drop = d_what === DROP val d_hasData = edgeOut.hasData(out.d.bits) - val d_normal = Wire(in.d) + val d_normal = Wire(chiselTypeOf(in.d)) val (d_first, d_last, _) = edgeIn.firstlast(d_normal) val d_trackerOH = VecInit(trackers.map { t => t.need_d && t.source === d_normal.bits.source }).asUInt holdUnless d_first @@ -178,8 +178,8 @@ class TLBroadcast(params: TLBroadcastParams)(implicit p: Parameters) extends Laz in.c.bits.param === TLPermissions.BtoB) } - val releaseack = Wire(in.d) - val putfull = Wire(out.a) + val releaseack = Wire(chiselTypeOf(in.d)) + val putfull = Wire(chiselTypeOf(out.a)) in.c.ready := c_probeack || Mux(c_release, releaseack.ready, putfull.ready)