From 4732a9166d9ef725b03319dca4b0bfbde2d6f360 Mon Sep 17 00:00:00 2001 From: Jerry Zhao Date: Fri, 18 Aug 2023 22:07:35 -0700 Subject: [PATCH 1/8] Various fixes for new chisel --- src/main/scala/groundtest/DummyPTW.scala | 2 +- src/main/scala/groundtest/Tile.scala | 2 ++ src/main/scala/rocket/NBDcache.scala | 7 ++++++- src/main/scala/util/LatencyPipe.scala | 2 +- 4 files changed, 10 insertions(+), 3 deletions(-) diff --git a/src/main/scala/groundtest/DummyPTW.scala b/src/main/scala/groundtest/DummyPTW.scala index 8870f522a11..ce95b826d83 100644 --- a/src/main/scala/groundtest/DummyPTW.scala +++ b/src/main/scala/groundtest/DummyPTW.scala @@ -15,7 +15,7 @@ class DummyPTW(n: Int)(implicit p: Parameters) extends CoreModule()(p) { val io = IO(new Bundle { val requestors = Flipped(Vec(n, new TLBPTWIO)) }) - + io.requestors := DontCare val req_arb = Module(new RRArbiter(Valid(new PTWReq), n)) req_arb.io.in <> io.requestors.map(_.req) req_arb.io.out.ready := true.B diff --git a/src/main/scala/groundtest/Tile.scala b/src/main/scala/groundtest/Tile.scala index d559dd5c54e..912016f8ea4 100644 --- a/src/main/scala/groundtest/Tile.scala +++ b/src/main/scala/groundtest/Tile.scala @@ -45,6 +45,7 @@ abstract class GroundTestTile( InModuleBody { m.module match { case module: DCacheModule => module.tlb_port := DontCare + case other => other } } } @@ -58,6 +59,7 @@ class GroundTestTileModuleImp(outer: GroundTestTile) extends BaseTileModuleImp(o outer.dcacheOpt foreach { dcache => val ptw = Module(new DummyPTW(1)) + ptw.io.requestors := DontCare ptw.io.requestors.head <> dcache.module.io.ptw } } diff --git a/src/main/scala/rocket/NBDcache.scala b/src/main/scala/rocket/NBDcache.scala index 50c7400f29a..f9161dd5d51 100644 --- a/src/main/scala/rocket/NBDcache.scala +++ b/src/main/scala/rocket/NBDcache.scala @@ -449,7 +449,9 @@ class MSHRFile(implicit edge: TLEdgeOut, p: Parameters) extends L1HellaCacheModu val free_sdq = io.replay.fire && isWrite(io.replay.bits.cmd) io.replay.bits.data := sdq(RegEnable(replay_arb.io.out.bits.sdq_id, free_sdq)) io.replay.bits.mask := 0.U - io.replay <> replay_arb.io.out + io.replay.valid := replay_arb.io.out.valid + replay_arb.io.out.ready := io.replay.ready + io.replay.bits.viewAsSupertype(new HellaCacheReqInternal) <> replay_arb.io.out.bits.viewAsSupertype(new HellaCacheReqInternal) when (io.replay.valid || sdq_enq) { sdq_val := sdq_val & ~(UIntToOH(replay_arb.io.out.bits.sdq_id) & Fill(cfg.nSDQ, free_sdq)) | @@ -707,6 +709,9 @@ class NonBlockingDCacheModule(outer: NonBlockingDCache) extends HellaCacheModule require(cacheParams.tagCode.isInstanceOf[IdentityCode]) val dECC = cacheParams.dataCode + io.cpu := DontCare + io.errors := DontCare + val wb = Module(new WritebackUnit) val prober = Module(new ProbeUnit) val mshrs = Module(new MSHRFile) diff --git a/src/main/scala/util/LatencyPipe.scala b/src/main/scala/util/LatencyPipe.scala index a90dcf2a316..f11b2c9f2ed 100644 --- a/src/main/scala/util/LatencyPipe.scala +++ b/src/main/scala/util/LatencyPipe.scala @@ -19,7 +19,7 @@ class LatencyPipe[T <: Data](typ: T, latency: Int) extends Module { object LatencyPipe { def apply[T <: Data](in: DecoupledIO[T], latency: Int): DecoupledIO[T] = { - val pipe = Module(new LatencyPipe(in.bits, latency)) + val pipe = Module(new LatencyPipe(chiselTypeOf(in.bits), latency)) pipe.io.in <> in pipe.io.out } From 086b5dc254b3dd5bba12879ab112a17cd3232683 Mon Sep 17 00:00:00 2001 From: Jerry Zhao Date: Sat, 19 Aug 2023 11:01:25 -0700 Subject: [PATCH 2/8] Fix HellaCache match error --- src/main/scala/rocket/HellaCache.scala | 1 + 1 file changed, 1 insertion(+) diff --git a/src/main/scala/rocket/HellaCache.scala b/src/main/scala/rocket/HellaCache.scala index 5114367db73..7360ab89fc0 100644 --- a/src/main/scala/rocket/HellaCache.scala +++ b/src/main/scala/rocket/HellaCache.scala @@ -274,6 +274,7 @@ trait HasHellaCache { this: BaseTile => InModuleBody { dcache.module match { case module: DCacheModule => module.tlb_port := DontCare + case other => other } } } From fa0f88ec3c64c96c95bd91d3ae607c6500d84ef9 Mon Sep 17 00:00:00 2001 From: Jerry Zhao Date: Sat, 19 Aug 2023 14:59:12 -0700 Subject: [PATCH 3/8] Fix unconnected wire in ICache --- src/main/scala/rocket/ICache.scala | 1 + 1 file changed, 1 insertion(+) diff --git a/src/main/scala/rocket/ICache.scala b/src/main/scala/rocket/ICache.scala index 97b776e5c4f..3090ca4f99d 100644 --- a/src/main/scala/rocket/ICache.scala +++ b/src/main/scala/rocket/ICache.scala @@ -636,6 +636,7 @@ class ICacheModule(outer: ICache) extends LazyModuleImp(outer) io.resp.bits.data := Mux1H(s1_tag_hit, s1_dout) io.resp.bits.ae := s1_tl_error.asUInt.orR io.resp.valid := s1_valid && s1_hit + io.resp.bits.replay := false.B // if I$ latency is 2, can have ITIM and ECC. case 2 => From 9aaac40fe630487c9d8774370fa918a562301d5f Mon Sep 17 00:00:00 2001 From: Jerry Zhao Date: Sat, 19 Aug 2023 22:37:56 -0700 Subject: [PATCH 4/8] Fix AXI4 xbar chisel3 connectable --- src/main/scala/amba/axi4/Xbar.scala | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/main/scala/amba/axi4/Xbar.scala b/src/main/scala/amba/axi4/Xbar.scala index 2f2d066aaf6..a3aa4ab63a7 100644 --- a/src/main/scala/amba/axi4/Xbar.scala +++ b/src/main/scala/amba/axi4/Xbar.scala @@ -85,7 +85,7 @@ class AXI4Xbar( // Transform input bundles val in = Wire(Vec(io_in.size, new AXI4Bundle(wide_bundle))) for (i <- 0 until in.size) { - in(i) :<>= io_in(i) + in(i).squeezeAll :<>= io_in(i).squeezeAll // Handle size = 1 gracefully (Chisel3 empty range is broken) def trim(id: UInt, size: Int) = if (size <= 1) 0.U else id(log2Ceil(size)-1, 0) From 13fe404387cfd70988240a3f5c03d31e25d7ca87 Mon Sep 17 00:00:00 2001 From: Jerry Zhao Date: Sat, 19 Aug 2023 23:29:16 -0700 Subject: [PATCH 5/8] More fixes to amba components --- src/main/scala/amba/ahb/Xbar.scala | 2 +- src/main/scala/amba/apb/Xbar.scala | 2 +- src/main/scala/amba/axi4/RegisterRouter.scala | 8 ++++---- src/main/scala/amba/axi4/Xbar.scala | 2 +- 4 files changed, 7 insertions(+), 7 deletions(-) diff --git a/src/main/scala/amba/ahb/Xbar.scala b/src/main/scala/amba/ahb/Xbar.scala index 8922c838dcd..2db7d5cd187 100644 --- a/src/main/scala/amba/ahb/Xbar.scala +++ b/src/main/scala/amba/ahb/Xbar.scala @@ -46,7 +46,7 @@ class AHBFanout()(implicit p: Parameters) extends LazyModule { when (in.hready) { d_sel := a_sel } (a_sel zip io_out) foreach { case (sel, out) => - out :<>= in + out.squeezeAll :<>= in.squeezeAll out.hsel := in.hsel && sel out.hmaster.map { _ := 0.U } } diff --git a/src/main/scala/amba/apb/Xbar.scala b/src/main/scala/amba/apb/Xbar.scala index de82ae15b13..849edaa5f19 100644 --- a/src/main/scala/amba/apb/Xbar.scala +++ b/src/main/scala/amba/apb/Xbar.scala @@ -43,7 +43,7 @@ class APBFanout()(implicit p: Parameters) extends LazyModule { val sel = VecInit(route_addrs.map(seq => seq.map(_.contains(in.paddr)).reduce(_ || _))) (sel zip io_out) foreach { case (sel, out) => - out :<>= in + out.squeezeAll :<>= in.squeezeAll out.psel := sel && in.psel out.penable := sel && in.penable } diff --git a/src/main/scala/amba/axi4/RegisterRouter.scala b/src/main/scala/amba/axi4/RegisterRouter.scala index 5a7f9e916b2..827c64e4952 100644 --- a/src/main/scala/amba/axi4/RegisterRouter.scala +++ b/src/main/scala/amba/axi4/RegisterRouter.scala @@ -48,8 +48,8 @@ case class AXI4RegisterNode(address: AddressSet, concurrency: Int = 0, beatBytes aw.ready := in.ready && !ar.valid && w .valid w .ready := in.ready && !ar.valid && aw.valid - ar_extra :<= ar.bits.echo - aw_extra :<= aw.bits.echo + ar_extra.waiveAll :<= ar.bits.echo + aw_extra.waiveAll :<= aw.bits.echo ar_extra(AXI4RRId) := ar.bits.id aw_extra(AXI4RRId) := aw.bits.id val addr = Mux(ar.valid, ar.bits.addr, aw.bits.addr) @@ -75,11 +75,11 @@ case class AXI4RegisterNode(address: AddressSet, concurrency: Int = 0, beatBytes r.bits.data := out.bits.data r.bits.last := true.B r.bits.resp := AXI4Parameters.RESP_OKAY - r.bits.echo :<= out.bits.extra + r.bits.echo :<= out.bits.extra.waiveAll b.bits.id := out.bits.extra(AXI4RRId) b.bits.resp := AXI4Parameters.RESP_OKAY - b.bits.echo :<= out.bits.extra + b.bits.echo :<= out.bits.extra.waiveAll } } diff --git a/src/main/scala/amba/axi4/Xbar.scala b/src/main/scala/amba/axi4/Xbar.scala index a3aa4ab63a7..be65db13834 100644 --- a/src/main/scala/amba/axi4/Xbar.scala +++ b/src/main/scala/amba/axi4/Xbar.scala @@ -168,7 +168,7 @@ class AXI4Xbar( // Transform output bundles val out = Wire(Vec(io_out.size, new AXI4Bundle(wide_bundle))) for (i <- 0 until out.size) { - io_out(i) :<>= out(i) + io_out(i).squeezeAll :<>= out(i).squeezeAll if (io_in.size > 1) { // Block AW if we cannot record the W source From ecacc48460578f6977fbc0221effcdd37beff218 Mon Sep 17 00:00:00 2001 From: Jerry Zhao Date: Sun, 20 Aug 2023 09:39:31 -0700 Subject: [PATCH 6/8] Fix default connection in BroadcastFilter --- src/main/scala/tilelink/Broadcast.scala | 1 + 1 file changed, 1 insertion(+) diff --git a/src/main/scala/tilelink/Broadcast.scala b/src/main/scala/tilelink/Broadcast.scala index 2e95d1e54be..0e69bd5d60f 100644 --- a/src/main/scala/tilelink/Broadcast.scala +++ b/src/main/scala/tilelink/Broadcast.scala @@ -367,6 +367,7 @@ class BroadcastFilter(params: ProbeFilterParams) extends ProbeFilter(params) { io.response.bits.needT := io.request.bits.needT io.response.bits.allocOH := io.request.bits.allocOH io.response.bits.gaveT := true.B + io.response.bits.cacheOH := DontCare if (params.caches > 0) io.response.bits.cacheOH := ~0.U(params.caches.W) From d71cfe41f08fc6ade4cc9d0d663bb010c3780376 Mon Sep 17 00:00:00 2001 From: Jerry Zhao Date: Mon, 21 Aug 2023 10:22:55 -0700 Subject: [PATCH 7/8] Use .waiveAll when constructing BundleMap subsets --- src/main/scala/util/BundleMap.scala | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/main/scala/util/BundleMap.scala b/src/main/scala/util/BundleMap.scala index 57dd5153043..2b8dc0a1911 100644 --- a/src/main/scala/util/BundleMap.scala +++ b/src/main/scala/util/BundleMap.scala @@ -112,7 +112,7 @@ class BundleMap(val fields: Seq[BundleFieldBase]) extends Record { // Create a new BundleMap with only the selected Keys retained def subset(fn: BundleKeyBase => Boolean): BundleMap = { val out = Wire(BundleMap(fields.filter(x => fn(x.key)))) - out :<= this + out :<= this.waiveAll out } } From c563f74a54e60745969a5ad6b55a8207074f7509 Mon Sep 17 00:00:00 2001 From: Jerry Zhao Date: Mon, 21 Aug 2023 10:23:20 -0700 Subject: [PATCH 8/8] Fix Fragmenter with user fields --- src/main/scala/tilelink/Fragmenter.scala | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/main/scala/tilelink/Fragmenter.scala b/src/main/scala/tilelink/Fragmenter.scala index c38554d0fb8..0aace162b46 100644 --- a/src/main/scala/tilelink/Fragmenter.scala +++ b/src/main/scala/tilelink/Fragmenter.scala @@ -313,7 +313,7 @@ class TLFragmenter(val minSize: Int, val maxSize: Int, val alwaysMin: Boolean = val fullMask = ((BigInt(1) << beatBytes) - 1).U assert (!repeater.io.full || in_a.bits.mask === fullMask) out.a.bits.mask := Mux(repeater.io.full, fullMask, in.a.bits.mask) - out.a.bits.user :<= in.a.bits.user.subset(_.isData) + out.a.bits.user.waiveAll :<= in.a.bits.user.subset(_.isData) // Tie off unused channels in.b.valid := false.B