From 7774cd099252a644972a1e5b51b3948303c05b6a Mon Sep 17 00:00:00 2001 From: kanataso Date: Mon, 17 Jul 2023 15:17:53 +0900 Subject: [PATCH] Change the condition of mul/div illegal instruction trap Signed-off-by: kanataso --- src/main/scala/rocket/RocketCore.scala | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/main/scala/rocket/RocketCore.scala b/src/main/scala/rocket/RocketCore.scala index a7e0374521c..b8486c581a7 100644 --- a/src/main/scala/rocket/RocketCore.scala +++ b/src/main/scala/rocket/RocketCore.scala @@ -328,7 +328,7 @@ class Rocket(tile: RocketTile)(implicit p: Parameters) extends CoreModule()(p) } val id_illegal_rnum = if (usingCryptoNIST) (id_ctrl.zkn && aluFn.isKs1(id_ctrl.alu_fn) && id_inst(0)(23,20) > 0xA.U(4.W)) else false.B val id_illegal_insn = !id_ctrl.legal || - (id_ctrl.mul || id_ctrl.div) && !csr.io.status.isa('m'-'a') || + id_ctrl.div && !csr.io.status.isa('m'-'a') || id_ctrl.amo && !csr.io.status.isa('a'-'a') || id_ctrl.fp && (csr.io.decode(0).fp_illegal || io.fpu.illegal_rm) || id_ctrl.dp && !csr.io.status.isa('d'-'a') ||