From 71108282153a15091f4d39e09aa3704946d437cc Mon Sep 17 00:00:00 2001 From: Jiuyang Liu Date: Thu, 27 Jul 2023 14:47:01 +0800 Subject: [PATCH 1/6] remove CompileOption in Plic --- src/main/scala/devices/tilelink/Plic.scala | 1 - 1 file changed, 1 deletion(-) diff --git a/src/main/scala/devices/tilelink/Plic.scala b/src/main/scala/devices/tilelink/Plic.scala index e18b344c67c..500a620c24c 100644 --- a/src/main/scala/devices/tilelink/Plic.scala +++ b/src/main/scala/devices/tilelink/Plic.scala @@ -4,7 +4,6 @@ package freechips.rocketchip.devices.tilelink import chisel3._ import chisel3.util._ -import freechips.rocketchip.util.CompileOptions.NotStrictInferReset import org.chipsalliance.cde.config.{Field, Parameters} import freechips.rocketchip.subsystem._ import freechips.rocketchip.diplomacy._ From a18bcf02280f8101020ffd2aa5444497105ec40e Mon Sep 17 00:00:00 2001 From: Jiuyang Liu Date: Thu, 27 Jul 2023 14:53:23 +0800 Subject: [PATCH 2/6] remove CompileOption in tilelink Atomics --- src/main/scala/tilelink/Atomics.scala | 2 -- 1 file changed, 2 deletions(-) diff --git a/src/main/scala/tilelink/Atomics.scala b/src/main/scala/tilelink/Atomics.scala index 9066c83e001..eeba7737f4c 100644 --- a/src/main/scala/tilelink/Atomics.scala +++ b/src/main/scala/tilelink/Atomics.scala @@ -4,8 +4,6 @@ package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ -import freechips.rocketchip.util.CompileOptions.NotStrictInferReset - class Atomics(params: TLBundleParameters) extends Module { From 07d1b5735a94827d2131a61ee392af667c2aab88 Mon Sep 17 00:00:00 2001 From: Jiuyang Liu Date: Thu, 27 Jul 2023 14:54:25 +0800 Subject: [PATCH 3/6] remove CompileOption in tilelink Broadcast --- src/main/scala/tilelink/Broadcast.scala | 7 +++---- 1 file changed, 3 insertions(+), 4 deletions(-) diff --git a/src/main/scala/tilelink/Broadcast.scala b/src/main/scala/tilelink/Broadcast.scala index 5d33ea8bca5..2e95d1e54be 100644 --- a/src/main/scala/tilelink/Broadcast.scala +++ b/src/main/scala/tilelink/Broadcast.scala @@ -4,7 +4,6 @@ package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ -import freechips.rocketchip.util.CompileOptions.NotStrictInferReset import org.chipsalliance.cde.config.Parameters import freechips.rocketchip.diplomacy._ import freechips.rocketchip.regmapper._ @@ -119,7 +118,7 @@ class TLBroadcast(params: TLBroadcastParams)(implicit p: Parameters) extends Laz val d_what = out.d.bits.source(d_high+1, d_high) val d_drop = d_what === DROP val d_hasData = edgeOut.hasData(out.d.bits) - val d_normal = Wire(in.d) + val d_normal = Wire(chiselTypeOf(in.d)) val (d_first, d_last, _) = edgeIn.firstlast(d_normal) val d_trackerOH = VecInit(trackers.map { t => t.need_d && t.source === d_normal.bits.source }).asUInt holdUnless d_first @@ -179,8 +178,8 @@ class TLBroadcast(params: TLBroadcastParams)(implicit p: Parameters) extends Laz in.c.bits.param === TLPermissions.BtoB) } - val releaseack = Wire(in.d) - val putfull = Wire(out.a) + val releaseack = Wire(chiselTypeOf(in.d)) + val putfull = Wire(chiselTypeOf(out.a)) in.c.ready := c_probeack || Mux(c_release, releaseack.ready, putfull.ready) From 81f38753c32726ffff1528d1eee6c3b53cf00587 Mon Sep 17 00:00:00 2001 From: Jiuyang Liu Date: Thu, 27 Jul 2023 14:55:52 +0800 Subject: [PATCH 4/6] remove CompileOption in AsyncResetReg --- src/main/scala/util/AsyncResetReg.scala | 2 -- 1 file changed, 2 deletions(-) diff --git a/src/main/scala/util/AsyncResetReg.scala b/src/main/scala/util/AsyncResetReg.scala index bca6f2b7d81..a687115d157 100644 --- a/src/main/scala/util/AsyncResetReg.scala +++ b/src/main/scala/util/AsyncResetReg.scala @@ -2,8 +2,6 @@ package freechips.rocketchip.util -import freechips.rocketchip.util.CompileOptions.NotStrictInferReset - import chisel3._ /** This black-boxes an Async Reset From ba86e0a957000a63713f7fed1ab140f6cc07e617 Mon Sep 17 00:00:00 2001 From: Jiuyang Liu Date: Thu, 27 Jul 2023 14:45:59 +0800 Subject: [PATCH 5/6] remove CompileOption in UserYanker --- src/main/scala/amba/axi4/UserYanker.scala | 17 ++++++++++++----- 1 file changed, 12 insertions(+), 5 deletions(-) diff --git a/src/main/scala/amba/axi4/UserYanker.scala b/src/main/scala/amba/axi4/UserYanker.scala index 0e209cecd46..a332f5399d3 100644 --- a/src/main/scala/amba/axi4/UserYanker.scala +++ b/src/main/scala/amba/axi4/UserYanker.scala @@ -4,7 +4,6 @@ package freechips.rocketchip.amba.axi4 import chisel3._ import chisel3.util._ -import freechips.rocketchip.util.CompileOptions.NotStrictInferReset import org.chipsalliance.cde.config.Parameters import freechips.rocketchip.diplomacy._ import freechips.rocketchip.util._ @@ -74,8 +73,12 @@ class AXI4UserYanker(capMaxFlight: Option[Int] = None)(implicit p: Parameters) e val rsel = UIntToOH(rid, edgeIn.master.endId).asBools (rqueues zip (arsel zip rsel)) foreach { case (q, (ar, r)) => q.deq.ready := out.r .valid && in .r .ready && r && out.r.bits.last + q.deq.valid := DontCare + q.deq.bits := DontCare q.enq.valid := in .ar.valid && out.ar.ready && ar - q.enq.bits :<= in.ar.bits.echo + q.enq.ready := DontCare + q.enq.bits :<>= in.ar.bits.echo + q.count := DontCare } val awid = in.aw.bits.id @@ -83,7 +86,7 @@ class AXI4UserYanker(capMaxFlight: Option[Int] = None)(implicit p: Parameters) e in .aw.ready := out.aw.ready && aw_ready out.aw.valid := in .aw.valid && aw_ready Connectable.waiveUnmatched(out.aw.bits, in.aw.bits) match { - case (lhs, rhs) => lhs :<= rhs + case (lhs, rhs) => lhs :<>= rhs } val bid = out.b.bits.id @@ -93,14 +96,18 @@ class AXI4UserYanker(capMaxFlight: Option[Int] = None)(implicit p: Parameters) e Connectable.waiveUnmatched(in.b, out.b) match { case (lhs, rhs) => lhs :<>= rhs } - in.b.bits.echo :<= b_bits + in.b.bits.echo :<>= b_bits val awsel = UIntToOH(awid, edgeIn.master.endId).asBools val bsel = UIntToOH(bid, edgeIn.master.endId).asBools (wqueues zip (awsel zip bsel)) foreach { case (q, (aw, b)) => q.deq.ready := out.b .valid && in .b .ready && b + q.deq.valid := DontCare + q.deq.bits := DontCare q.enq.valid := in .aw.valid && out.aw.ready && aw - q.enq.bits :<= in.aw.bits.echo + q.enq.ready := DontCare + q.enq.bits :<>= in.aw.bits.echo + q.count := DontCare } out.w :<>= in.w From 18bb9b3a144b22d24b8164e221be7466be91dc5a Mon Sep 17 00:00:00 2001 From: Jiuyang Liu Date: Thu, 27 Jul 2023 14:51:50 +0800 Subject: [PATCH 6/6] remove CompileOption in FPU --- src/main/scala/tile/FPU.scala | 11 +++++++---- 1 file changed, 7 insertions(+), 4 deletions(-) diff --git a/src/main/scala/tile/FPU.scala b/src/main/scala/tile/FPU.scala index 0ebeb0a9275..174cd38c7de 100644 --- a/src/main/scala/tile/FPU.scala +++ b/src/main/scala/tile/FPU.scala @@ -5,9 +5,9 @@ package freechips.rocketchip.tile import chisel3._ import chisel3.util._ -import freechips.rocketchip.util.CompileOptions.NotStrictInferReset import chisel3.{DontCare, WireInit, withClock, withReset} import chisel3.experimental.SourceInfo +import chisel3.experimental.dataview._ import org.chipsalliance.cde.config.Parameters import freechips.rocketchip.rocket._ import freechips.rocketchip.rocket.Instructions._ @@ -768,9 +768,10 @@ class FPU(cfg: FPUParams)(implicit p: Parameters) extends FPUModule()(p) { val wb_reg_valid = RegNext(mem_reg_valid && (!killm || mem_cp_valid), false.B) val cp_ctrl = Wire(new FPUCtrlSigs) - cp_ctrl <> io.cp_req.bits + cp_ctrl :<>= io.cp_req.bits.viewAsSupertype(new FPUCtrlSigs) io.cp_resp.valid := false.B io.cp_resp.bits.data := 0.U + io.cp_resp.bits.exc := DontCare val ex_ctrl = Mux(ex_cp_valid, cp_ctrl, ex_reg_ctrl) val mem_ctrl = RegEnable(ex_ctrl, req_valid) @@ -822,7 +823,7 @@ class FPU(cfg: FPUParams)(implicit p: Parameters) extends FPUModule()(p) { def fuInput(minT: Option[FType]): FPInput = { val req = Wire(new FPInput) val tag = ex_ctrl.typeTagIn - req := ex_ctrl + req.viewAsSupertype(new Bundle with HasFPUCtrlSigs) :#= ex_ctrl.viewAsSupertype(new Bundle with HasFPUCtrlSigs) req.rm := ex_rm req.in1 := unbox(ex_rs(0), tag, minT) req.in2 := unbox(ex_rs(1), tag, minT) @@ -870,7 +871,9 @@ class FPU(cfg: FPUParams)(implicit p: Parameters) extends FPUModule()(p) { val divSqrt_typeTag = Wire(UInt(log2Up(floatTypes.size).W)) val divSqrt_wdata = Wire(UInt((fLen+1).W)) val divSqrt_flags = Wire(UInt(FPConstants.FLAGS_SZ.W)) - + divSqrt_typeTag := DontCare + divSqrt_wdata := DontCare + divSqrt_flags := DontCare // writeback arbitration case class Pipe(p: Module, lat: Int, cond: (FPUCtrlSigs) => Bool, res: FPResult) val pipes = List(