From 445b5da319ac4a83bb199c6c577fb276dc1b4e95 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?David=20Lanzend=C3=B6rfer?= Date: Mon, 19 Aug 2024 04:43:39 +0100 Subject: [PATCH] Adding support for Litex There is a naming conflict of the ALU module which prevents a successful synthesis with Yosys. This patch fixes this conflict. In addition, this patch introduces the configurations expected by Litex when generating an SoC This patch also adds a generator for System Verilog which works with Yosys --- build.sc | 64 ++++++- src/main/scala/rocket/ALU.scala | 2 + src/main/scala/rocket/BitManipCrypto.scala | 0 src/main/scala/rocket/CryptoNIST.scala | 0 src/main/scala/subsystem/Litex.scala | 53 ++++++ src/main/scala/system/Litex.scala | 209 +++++++++++++++++++++ 6 files changed, 327 insertions(+), 1 deletion(-) delete mode 100644 src/main/scala/rocket/BitManipCrypto.scala delete mode 100644 src/main/scala/rocket/CryptoNIST.scala create mode 100644 src/main/scala/subsystem/Litex.scala create mode 100644 src/main/scala/system/Litex.scala diff --git a/build.sc b/build.sc index b63c6ae7900..cf602b2a8ab 100644 --- a/build.sc +++ b/build.sc @@ -185,6 +185,35 @@ trait Emulator extends Cross.Module2[String, String] { } } + object litexgenerate extends Module { + def compile = T { + os.proc("firtool", + generator.chirrtl().path, + s"--annotation-file=${generator.chiselAnno().path}", + "--disable-annotation-unknown", + "-dedup", + "-O=debug", + "--split-verilog", + "--preserve-values=named", + "--output-annotation-file=mfc.anno.json", + "--lowering-options=disallowLocalVariables", + s"-o=${T.dest}" + ).call(T.dest) + PathRef(T.dest) + } + + def rtls = T { + os.read(compile().path / "filelist.f").split("\n").map(str => + try { + os.Path(str) + } catch { + case e: IllegalArgumentException if e.getMessage.contains("is not an absolute path") => + compile().path / str.stripPrefix("./") + } + ).filter(p => p.ext == "v" || p.ext == "sv").map(PathRef(_)).toSeq + } + } + object mfccompiler extends Module { def compile = T { os.proc("firtool", @@ -233,7 +262,7 @@ trait Emulator extends Cross.Module2[String, String] { "debug_rob.cc", "emulator.cc", "remote_bitbang.cc", - ).map(c => PathRef(csrcDir().path / c)) + ).map(c => PathRef(csrcDir().path / c)) } def CMakeListsString = T { @@ -347,6 +376,39 @@ object emulator extends Cross[Emulator]( ("freechips.rocketchip.system.TestHarness", "freechips.rocketchip.system.DefaultBConfig"), ("freechips.rocketchip.system.TestHarness", "freechips.rocketchip.system.DefaultRV32BConfig"), + // Litex + ("freechips.rocketchip.system.TestHarness", "freechips.rocketchip.system.LitexConfigSmall1x1"), + ("freechips.rocketchip.system.TestHarness", "freechips.rocketchip.system.LitexConfigSmall1x2"), + ("freechips.rocketchip.system.TestHarness", "freechips.rocketchip.system.LitexConfigSmall1x4"), + ("freechips.rocketchip.system.TestHarness", "freechips.rocketchip.system.LitexConfigSmall1x8"), + ("freechips.rocketchip.system.TestHarness", "freechips.rocketchip.system.LitexConfigSmall2x1"), + ("freechips.rocketchip.system.TestHarness", "freechips.rocketchip.system.LitexConfigSmall2x2"), + ("freechips.rocketchip.system.TestHarness", "freechips.rocketchip.system.LitexConfigSmall2x4"), + ("freechips.rocketchip.system.TestHarness", "freechips.rocketchip.system.LitexConfigSmall2x8"), + ("freechips.rocketchip.system.TestHarness", "freechips.rocketchip.system.LitexConfigSmall4x1"), + ("freechips.rocketchip.system.TestHarness", "freechips.rocketchip.system.LitexConfigSmall4x2"), + ("freechips.rocketchip.system.TestHarness", "freechips.rocketchip.system.LitexConfigSmall4x4"), + ("freechips.rocketchip.system.TestHarness", "freechips.rocketchip.system.LitexConfigSmall4x8"), + ("freechips.rocketchip.system.TestHarness", "freechips.rocketchip.system.LitexConfigSmall8x1"), + ("freechips.rocketchip.system.TestHarness", "freechips.rocketchip.system.LitexConfigSmall8x2"), + ("freechips.rocketchip.system.TestHarness", "freechips.rocketchip.system.LitexConfigSmall8x4"), + ("freechips.rocketchip.system.TestHarness", "freechips.rocketchip.system.LitexConfigSmall8x8"), + ("freechips.rocketchip.system.TestHarness", "freechips.rocketchip.system.LitexConfigBig1x1"), + ("freechips.rocketchip.system.TestHarness", "freechips.rocketchip.system.LitexConfigBig1x2"), + ("freechips.rocketchip.system.TestHarness", "freechips.rocketchip.system.LitexConfigBig1x4"), + ("freechips.rocketchip.system.TestHarness", "freechips.rocketchip.system.LitexConfigBig1x8"), + ("freechips.rocketchip.system.TestHarness", "freechips.rocketchip.system.LitexConfigBig2x1"), + ("freechips.rocketchip.system.TestHarness", "freechips.rocketchip.system.LitexConfigBig2x2"), + ("freechips.rocketchip.system.TestHarness", "freechips.rocketchip.system.LitexConfigBig2x4"), + ("freechips.rocketchip.system.TestHarness", "freechips.rocketchip.system.LitexConfigBig2x8"), + ("freechips.rocketchip.system.TestHarness", "freechips.rocketchip.system.LitexConfigBig4x1"), + ("freechips.rocketchip.system.TestHarness", "freechips.rocketchip.system.LitexConfigBig4x2"), + ("freechips.rocketchip.system.TestHarness", "freechips.rocketchip.system.LitexConfigBig4x4"), + ("freechips.rocketchip.system.TestHarness", "freechips.rocketchip.system.LitexConfigBig4x8"), + ("freechips.rocketchip.system.TestHarness", "freechips.rocketchip.system.LitexConfigBig8x1"), + ("freechips.rocketchip.system.TestHarness", "freechips.rocketchip.system.LitexConfigBig8x2"), + ("freechips.rocketchip.system.TestHarness", "freechips.rocketchip.system.LitexConfigBig8x4"), + ("freechips.rocketchip.system.TestHarness", "freechips.rocketchip.system.LitexConfigBig8x8"), ) object `runnable-riscv-test` extends mill.Cross[RiscvTest]( diff --git a/src/main/scala/rocket/ALU.scala b/src/main/scala/rocket/ALU.scala index 96cbc98aa58..ca8a11067b1 100644 --- a/src/main/scala/rocket/ALU.scala +++ b/src/main/scala/rocket/ALU.scala @@ -81,6 +81,8 @@ abstract class AbstractALU(implicit p: Parameters) extends CoreModule()(p) { } class ALU(implicit p: Parameters) extends AbstractALU()(p) { + override def desiredName = "RocketALU" + // ADD, SUB val in2_inv = Mux(isSub(io.fn), ~io.in2, io.in2) val in1_xor_in2 = io.in1 ^ in2_inv diff --git a/src/main/scala/rocket/BitManipCrypto.scala b/src/main/scala/rocket/BitManipCrypto.scala deleted file mode 100644 index e69de29bb2d..00000000000 diff --git a/src/main/scala/rocket/CryptoNIST.scala b/src/main/scala/rocket/CryptoNIST.scala deleted file mode 100644 index e69de29bb2d..00000000000 diff --git a/src/main/scala/subsystem/Litex.scala b/src/main/scala/subsystem/Litex.scala new file mode 100644 index 00000000000..7e8e1888d94 --- /dev/null +++ b/src/main/scala/subsystem/Litex.scala @@ -0,0 +1,53 @@ +// See LICENSE.SiFive for license details. +// See LICENSE.Berkeley for license details. + +package freechips.rocketchip.subsystem + +import chisel3.util._ + +import org.chipsalliance.cde.config._ +import org.chipsalliance.diplomacy.lazymodule._ + +import freechips.rocketchip.devices.debug.{DebugModuleKey, DefaultDebugModuleParams, ExportDebug, JTAG, APB} +import freechips.rocketchip.devices.tilelink.{ + BuiltInErrorDeviceParams, BootROMLocated, BootROMParams, CLINTKey, DevNullDevice, CLINTParams, PLICKey, PLICParams, DevNullParams +} +import freechips.rocketchip.prci.{SynchronousCrossing, AsynchronousCrossing, RationalCrossing, ClockCrossingType} +import freechips.rocketchip.diplomacy.{ + AddressSet, MonitorsEnabled, +} +import freechips.rocketchip.resources.{ + DTSModel, DTSCompat, DTSTimebase, BigIntHexContext +} +import freechips.rocketchip.tile.{ + MaxHartIdBits, RocketTileParams, BuildRoCC, AccumulatorExample, OpcodeSet, TranslatorExample, CharacterCountExample, BlackBoxExample +} +import freechips.rocketchip.util.ClockGateModelFile +import scala.reflect.ClassTag + +class WithLitexMemPort extends Config((site, here, up) => { + case ExtMem => Some(MemoryPortParams(MasterPortParams( + base = x"8000_0000", + size = x"8000_0000", + beatBytes = site(MemoryBusKey).beatBytes, + idBits = 4), 1)) +}) + +class WithLitexMMIOPort extends Config((site, here, up) => { + case ExtBus => Some(MasterPortParams( + base = x"1000_0000", + size = x"7000_0000", + beatBytes = site(SystemBusKey).beatBytes, + idBits = 4)) +}) + +class WithLitexSlavePort extends Config((site, here, up) => { + case ExtIn => Some(SlavePortParams( + beatBytes = site(SystemBusKey).beatBytes, + idBits = 8, + sourceBits = 4)) +}) + +class WithNBitMemoryBus(dataBits: Int) extends Config((site, here, up) => { + case MemoryBusKey => up(MemoryBusKey, site).copy(beatBytes = dataBits/8) +}) diff --git a/src/main/scala/system/Litex.scala b/src/main/scala/system/Litex.scala new file mode 100644 index 00000000000..4ffad24fe27 --- /dev/null +++ b/src/main/scala/system/Litex.scala @@ -0,0 +1,209 @@ +// See LICENSE.SiFive for license details. +// See LICENSE.Berkeley for license details. + +package freechips.rocketchip.system + +import org.chipsalliance.cde.config.Config +import freechips.rocketchip.subsystem._ +import freechips.rocketchip.rocket.{WithNBigCores, WithNMedCores, WithNSmallCores, WithRV32, WithFP16, WithHypervisor, With1TinyCore, WithScratchpadsOnly, WithCloneRocketTiles, WithB} + +class BaseLitexConfig extends Config( + new WithLitexMemPort() ++ + new WithLitexMMIOPort() ++ + new WithLitexSlavePort ++ + new WithNExtTopInterrupts(8) ++ + new WithCoherentBusTopology ++ + new BaseConfig +) + +class LitexConfigSmall1x1 extends Config( + new WithNSmallCores(1) ++ + new WithNBitMemoryBus(64) ++ + new BaseLitexConfig +) + +class LitexConfigSmall1x2 extends Config( + new WithNSmallCores(1) ++ + new WithNBitMemoryBus(128) ++ + new BaseLitexConfig +) + +class LitexConfigSmall1x4 extends Config( + new WithNSmallCores(1) ++ + new WithNBitMemoryBus(256) ++ + new BaseLitexConfig +) + +class LitexConfigSmall1x8 extends Config( + new WithNSmallCores(1) ++ + new WithNBitMemoryBus(512) ++ + new BaseLitexConfig +) + +class LitexConfigSmall2x1 extends Config( + new WithNSmallCores(2) ++ + new WithNBitMemoryBus(64) ++ + new BaseLitexConfig +) + +class LitexConfigSmall2x2 extends Config( + new WithNSmallCores(2) ++ + new WithNBitMemoryBus(128) ++ + new BaseLitexConfig +) + +class LitexConfigSmall2x4 extends Config( + new WithNSmallCores(2) ++ + new WithNBitMemoryBus(256) ++ + new BaseLitexConfig +) + +class LitexConfigSmall2x8 extends Config( + new WithNSmallCores(2) ++ + new WithNBitMemoryBus(512) ++ + new BaseLitexConfig +) + +class LitexConfigSmall4x1 extends Config( + new WithNSmallCores(4) ++ + new WithNBitMemoryBus(64) ++ + new BaseLitexConfig +) + +class LitexConfigSmall4x2 extends Config( + new WithNSmallCores(4) ++ + new WithNBitMemoryBus(128) ++ + new BaseLitexConfig +) + +class LitexConfigSmall4x4 extends Config( + new WithNSmallCores(4) ++ + new WithNBitMemoryBus(256) ++ + new BaseLitexConfig +) + +class LitexConfigSmall4x8 extends Config( + new WithNSmallCores(4) ++ + new WithNBitMemoryBus(512) ++ + new BaseLitexConfig +) + +class LitexConfigSmall8x1 extends Config( + new WithNSmallCores(8) ++ + new WithNBitMemoryBus(64) ++ + new BaseLitexConfig +) + +class LitexConfigSmall8x2 extends Config( + new WithNSmallCores(8) ++ + new WithNBitMemoryBus(128) ++ + new BaseLitexConfig +) + +class LitexConfigSmall8x4 extends Config( + new WithNSmallCores(8) ++ + new WithNBitMemoryBus(256) ++ + new BaseLitexConfig +) + +class LitexConfigSmall8x8 extends Config( + new WithNSmallCores(8) ++ + new WithNBitMemoryBus(512) ++ + new BaseLitexConfig +) + +class LitexConfigBig1x1 extends Config( + new WithNBigCores(1) ++ + new WithNBitMemoryBus(64) ++ + new BaseLitexConfig +) + +class LitexConfigBig1x2 extends Config( + new WithNBigCores(1) ++ + new WithNBitMemoryBus(128) ++ + new BaseLitexConfig +) + +class LitexConfigBig1x4 extends Config( + new WithNBigCores(1) ++ + new WithNBitMemoryBus(256) ++ + new BaseLitexConfig +) + +class LitexConfigBig1x8 extends Config( + new WithNBigCores(1) ++ + new WithNBitMemoryBus(512) ++ + new BaseLitexConfig +) + +class LitexConfigBig2x1 extends Config( + new WithNBigCores(2) ++ + new WithNBitMemoryBus(64) ++ + new BaseLitexConfig +) + +class LitexConfigBig2x2 extends Config( + new WithNBigCores(2) ++ + new WithNBitMemoryBus(128) ++ + new BaseLitexConfig +) + +class LitexConfigBig2x4 extends Config( + new WithNBigCores(2) ++ + new WithNBitMemoryBus(256) ++ + new BaseLitexConfig +) + +class LitexConfigBig2x8 extends Config( + new WithNBigCores(2) ++ + new WithNBitMemoryBus(512) ++ + new BaseLitexConfig +) + +class LitexConfigBig4x1 extends Config( + new WithNBigCores(4) ++ + new WithNBitMemoryBus(64) ++ + new BaseLitexConfig +) + +class LitexConfigBig4x2 extends Config( + new WithNBigCores(4) ++ + new WithNBitMemoryBus(128) ++ + new BaseLitexConfig +) + +class LitexConfigBig4x4 extends Config( + new WithNBigCores(4) ++ + new WithNBitMemoryBus(256) ++ + new BaseLitexConfig +) + +class LitexConfigBig4x8 extends Config( + new WithNBigCores(4) ++ + new WithNBitMemoryBus(512) ++ + new BaseLitexConfig +) + +class LitexConfigBig8x1 extends Config( + new WithNBigCores(8) ++ + new WithNBitMemoryBus(64) ++ + new BaseLitexConfig +) + +class LitexConfigBig8x2 extends Config( + new WithNBigCores(8) ++ + new WithNBitMemoryBus(128) ++ + new BaseLitexConfig +) + +class LitexConfigBig8x4 extends Config( + new WithNBigCores(8) ++ + new WithNBitMemoryBus(256) ++ + new BaseLitexConfig +) + +class LitexConfigBig8x8 extends Config( + new WithNBigCores(8) ++ + new WithNBitMemoryBus(512) ++ + new BaseLitexConfig +)