From 3f925674ac9137b44b4709da73b156db37e10d88 Mon Sep 17 00:00:00 2001 From: Jerry Zhao Date: Tue, 9 May 2023 16:09:32 -0700 Subject: [PATCH] Support removing the nonstandard CEASE from rocket (cherry picked from commit 956a1ff8bd13e310bb805672b969f5c7e4abf8a7) --- src/main/scala/rocket/IDecode.scala | 8 +++++++- src/main/scala/rocket/RocketCore.scala | 6 ++++-- src/main/scala/subsystem/Configs.scala | 8 ++++++++ 3 files changed, 19 insertions(+), 3 deletions(-) diff --git a/src/main/scala/rocket/IDecode.scala b/src/main/scala/rocket/IDecode.scala index 7428b0e4661..d75be986481 100644 --- a/src/main/scala/rocket/IDecode.scala +++ b/src/main/scala/rocket/IDecode.scala @@ -118,7 +118,6 @@ class IDecode(aluFn: ALUFN = ALUFN())(implicit val p: Parameters) extends Decode EBREAK-> List(Y,N,N,N,N,N,N,X,N,N,N,N,A2_X, A1_X, IMM_X, DW_X, aluFn.FN_X, N,M_X, N,N,N,N,N,N,N,CSR.I,N,N,N,N), MRET-> List(Y,N,N,N,N,N,N,X,N,N,N,N,A2_X, A1_X, IMM_X, DW_X, aluFn.FN_X, N,M_X, N,N,N,N,N,N,N,CSR.I,N,N,N,N), WFI-> List(Y,N,N,N,N,N,N,X,N,N,N,N,A2_X, A1_X, IMM_X, DW_X, aluFn.FN_X, N,M_X, N,N,N,N,N,N,N,CSR.I,N,N,N,N), - CEASE-> List(Y,N,N,N,N,N,N,X,N,N,N,N,A2_X, A1_X, IMM_X, DW_X, aluFn.FN_X, N,M_X, N,N,N,N,N,N,N,CSR.I,N,N,N,N), CSRRW-> List(Y,N,N,N,N,N,N,Y,N,N,N,N,A2_ZERO,A1_RS1, IMM_X, DW_XPR,aluFn.FN_ADD, N,M_X, N,N,N,N,N,N,Y,CSR.W,N,N,N,N), CSRRS-> List(Y,N,N,N,N,N,N,Y,N,N,N,N,A2_ZERO,A1_RS1, IMM_X, DW_XPR,aluFn.FN_ADD, N,M_X, N,N,N,N,N,N,Y,CSR.S,N,N,N,N), CSRRC-> List(Y,N,N,N,N,N,N,Y,N,N,N,N,A2_ZERO,A1_RS1, IMM_X, DW_XPR,aluFn.FN_ADD, N,M_X, N,N,N,N,N,N,Y,CSR.C,N,N,N,N), @@ -127,6 +126,13 @@ class IDecode(aluFn: ALUFN = ALUFN())(implicit val p: Parameters) extends Decode CSRRCI-> List(Y,N,N,N,N,N,N,N,N,N,N,N,A2_IMM, A1_ZERO,IMM_Z, DW_XPR,aluFn.FN_ADD, N,M_X, N,N,N,N,N,N,Y,CSR.C,N,N,N,N)) } +class CeaseDecode(aluFn: ALUFN = ALUFN())(implicit val p: Parameters) extends DecodeConstants +{ + val table: Array[(BitPat, List[BitPat])] = Array( + CEASE-> List(Y,N,N,N,N,N,N,X,N,N,N,N,A2_X, A1_X, IMM_X, DW_X, aluFn.FN_X, N,M_X, N,N,N,N,N,N,N,CSR.I,N,N,N,N)) +} + + class FenceIDecode(flushDCache: Boolean, aluFn: ALUFN = ALUFN())(implicit val p: Parameters) extends DecodeConstants { private val (v, cmd) = if (flushDCache) (Y, BitPat(M_FLUSH_ALL)) else (N, M_X) diff --git a/src/main/scala/rocket/RocketCore.scala b/src/main/scala/rocket/RocketCore.scala index 6c01985aab3..632b8c12746 100644 --- a/src/main/scala/rocket/RocketCore.scala +++ b/src/main/scala/rocket/RocketCore.scala @@ -53,7 +53,8 @@ case class RocketCoreParams( mvendorid: Int = 0, // 0 means non-commercial implementation mimpid: Int = 0x20181004, // release date in BCD mulDiv: Option[MulDivParams] = Some(MulDivParams()), - fpu: Option[FPUParams] = Some(FPUParams()) + fpu: Option[FPUParams] = Some(FPUParams()), + haveCease: Boolean = true // non-standard CEASE instruction ) extends CoreParams { val lgPauseCycles = 5 val haveFSDirty = false @@ -65,7 +66,7 @@ case class RocketCoreParams( val instBits: Int = if (useCompressed) 16 else 32 val lrscCycles: Int = 80 // worst case is 14 mispredicted branches + slop val traceHasWdata: Boolean = false // ooo wb, so no wdata in trace - override val customIsaExt = Some("xrocket") // CEASE instruction + override val customIsaExt = Option.when(haveCease)("xrocket") // CEASE instruction override def minFLen: Int = fpu.map(_.minFLen).getOrElse(32) override def customCSRs(implicit p: Parameters) = new RocketCustomCSRs } @@ -207,6 +208,7 @@ class Rocket(tile: RocketTile)(implicit p: Parameters) extends CoreModule()(p) (usingConditionalZero.option(new ConditionalZeroDecode(aluFn))) ++: Seq(new FenceIDecode(tile.dcache.flushOnFenceI, aluFn)) ++: coreParams.haveCFlush.option(new CFlushDecode(tile.dcache.canSupportCFlushLine, aluFn)) ++: + rocketParams.haveCease.option(new CeaseDecode(aluFn)) ++: Seq(new IDecode(aluFn)) } flatMap(_.table) diff --git a/src/main/scala/subsystem/Configs.scala b/src/main/scala/subsystem/Configs.scala index 215ae26b0a6..4f903c2c6b6 100644 --- a/src/main/scala/subsystem/Configs.scala +++ b/src/main/scala/subsystem/Configs.scala @@ -430,6 +430,14 @@ class WithCryptoSM extends Config((site, here, up) => { } }) +class WithRocketCease(enable: Boolean = true) extends Config((site, here, up) => { + case TilesLocated(InSubsystem) => up(TilesLocated(InSubsystem), site) map { + case tp: RocketTileAttachParams => tp.copy(tileParams = tp.tileParams.copy( + core = tp.tileParams.core.copy(haveCease = enable) + )) + } +}) + class WithBootROMFile(bootROMFile: String) extends Config((site, here, up) => { case BootROMLocated(x) => up(BootROMLocated(x), site).map(_.copy(contentFileName = bootROMFile)) })