From 00d9e02c1901d0285f22eefec7c25073fb90e4f1 Mon Sep 17 00:00:00 2001
From: John Ingalls <43973001+ingallsj@users.noreply.github.com>
Date: Tue, 15 Dec 2020 13:36:18 -0800
Subject: [PATCH] chisel3.experimental.chiselName is no longer necessary with
 chisel3._ (#2762)

---
 src/main/scala/devices/debug/Debug.scala          | 3 ---
 src/main/scala/devices/debug/DebugTransport.scala | 3 ---
 src/main/scala/tile/LazyRoCC.scala                | 4 ----
 src/main/scala/tilelink/Monitor.scala             | 2 --
 src/main/scala/util/ReadyValidCancel.scala        | 2 --
 5 files changed, 14 deletions(-)

diff --git a/src/main/scala/devices/debug/Debug.scala b/src/main/scala/devices/debug/Debug.scala
index 52377f09490..8ab84fc6390 100755
--- a/src/main/scala/devices/debug/Debug.scala
+++ b/src/main/scala/devices/debug/Debug.scala
@@ -4,7 +4,6 @@ package freechips.rocketchip.devices.debug
 
 
 import chisel3._
-import chisel3.experimental.chiselName
 import chisel3.util._
 import freechips.rocketchip.config._
 import freechips.rocketchip.diplomacy._
@@ -283,7 +282,6 @@ object WNotifyVal {
   }
 }
 
-@chiselName
 class TLDebugModuleOuter(device: Device)(implicit p: Parameters) extends LazyModule {
 
   // For Shorter Register Names
@@ -691,7 +689,6 @@ class TLDebugModuleOuterAsync(device: Device)(implicit p: Parameters) extends La
   }
 }
 
-@chiselName
 class TLDebugModuleInner(device: Device, getNComponents: () => Int, beatBytes: Int)(implicit p: Parameters) extends LazyModule
 {
 
diff --git a/src/main/scala/devices/debug/DebugTransport.scala b/src/main/scala/devices/debug/DebugTransport.scala
index 5b28567f973..02659b4f949 100644
--- a/src/main/scala/devices/debug/DebugTransport.scala
+++ b/src/main/scala/devices/debug/DebugTransport.scala
@@ -4,8 +4,6 @@ package freechips.rocketchip.devices.debug
 
 import chisel3._
 import chisel3.util._
-import chisel3.experimental.chiselName
-
 
 import freechips.rocketchip.config._
 import freechips.rocketchip.jtag._
@@ -74,7 +72,6 @@ class SystemJTAGIO extends Bundle {
 }
 
 // Use the Chisel Name macro due to the bulk of this being inside a withClockAndReset block
-@chiselName
 class DebugTransportModuleJTAG(debugAddrBits: Int, c: JtagDTMConfig)
   (implicit val p: Parameters) extends RawModule  {
 
diff --git a/src/main/scala/tile/LazyRoCC.scala b/src/main/scala/tile/LazyRoCC.scala
index 5c7c484a395..d58b1f003ad 100644
--- a/src/main/scala/tile/LazyRoCC.scala
+++ b/src/main/scala/tile/LazyRoCC.scala
@@ -7,7 +7,6 @@ import chisel3._
 import chisel3.util._
 import chisel3.util.HasBlackBoxResource
 import chisel3.experimental.IntParam
-import chisel3.experimental.chiselName
 import freechips.rocketchip.config._
 import freechips.rocketchip.diplomacy._
 import freechips.rocketchip.rocket._
@@ -122,7 +121,6 @@ class AccumulatorExample(opcodes: OpcodeSet, val n: Int = 4)(implicit p: Paramet
   override lazy val module = new AccumulatorExampleModuleImp(this)
 }
 
-@chiselName
 class AccumulatorExampleModuleImp(outer: AccumulatorExample)(implicit p: Parameters) extends LazyRoCCModuleImp(outer)
     with HasCoreParameters {
   val regfile = Mem(outer.n, UInt(xLen.W))
@@ -193,7 +191,6 @@ class  TranslatorExample(opcodes: OpcodeSet)(implicit p: Parameters) extends Laz
   override lazy val module = new TranslatorExampleModuleImp(this)
 }
 
-@chiselName
 class TranslatorExampleModuleImp(outer: TranslatorExample)(implicit p: Parameters) extends LazyRoCCModuleImp(outer)
     with HasCoreParameters {
   val req_addr = Reg(UInt(coreMaxAddrBits.W))
@@ -242,7 +239,6 @@ class  CharacterCountExample(opcodes: OpcodeSet)(implicit p: Parameters) extends
   override val atlNode = TLClientNode(Seq(TLMasterPortParameters.v1(Seq(TLMasterParameters.v1("CharacterCountRoCC")))))
 }
 
-@chiselName
 class CharacterCountExampleModuleImp(outer: CharacterCountExample)(implicit p: Parameters) extends LazyRoCCModuleImp(outer)
   with HasCoreParameters
   with HasL1CacheParameters {
diff --git a/src/main/scala/tilelink/Monitor.scala b/src/main/scala/tilelink/Monitor.scala
index 075642441a7..75bd6e2a4fc 100644
--- a/src/main/scala/tilelink/Monitor.scala
+++ b/src/main/scala/tilelink/Monitor.scala
@@ -5,7 +5,6 @@ package freechips.rocketchip.tilelink
 import chisel3._
 import chisel3.util._
 import chisel3.internal.sourceinfo.SourceLine
-import chisel3.experimental.chiselName
 import freechips.rocketchip.config.Parameters
 import freechips.rocketchip.diplomacy._
 import freechips.rocketchip.util.PlusArg
@@ -31,7 +30,6 @@ object TLMonitor {
   }
 }
 
-@chiselName
 class TLMonitor(args: TLMonitorArgs, monitorDir: MonitorDirection = MonitorDirection.Monitor) extends TLMonitorBase(args)
 {
   require (args.edge.params(TLMonitorStrictMode) || (! args.edge.params(TestplanTestType).formal))
diff --git a/src/main/scala/util/ReadyValidCancel.scala b/src/main/scala/util/ReadyValidCancel.scala
index 80646c1f7e1..afb000c2a48 100644
--- a/src/main/scala/util/ReadyValidCancel.scala
+++ b/src/main/scala/util/ReadyValidCancel.scala
@@ -4,7 +4,6 @@ package freechips.rocketchip.util
 
 import chisel3._
 import chisel3.util._
-import chisel3.experimental.chiselName
 
 /** A [[Bundle]] that adds `earlyValid` and `lateCancel` bits to some data.
   * This indicates that the user expects a "ValidCancel" interface between a producer and a consumer.
@@ -95,7 +94,6 @@ object ReadyValidCancel {
   * consumer.io.in <> arb.io.out
   * }}}
   */
-@chiselName
 class ReadyValidCancelRRArbiter[T <: Data](gen: T, n: Int, rr: Boolean) extends Module {
   val io = IO(new Bundle{
     val in  = Flipped(Vec(n, ReadyValidCancel(gen)))