CdM-16/e incorrectly reacts to exception request

[Intelix8996]

CdM-16/e architecture has an important invariant - when conditions for an exception are met, processor must not change its external state, as it can potentially affect these conditions.

Currently, this invariant is broken. When fetching an instruction, exception request via EXC pin alters processor's external state.

This happens because exception request triggers latch_int signal, that, combined with fetch, activates inhibit_microcode, which sets all external pins to some default state.

Proposed solution: Gate latch_int & fetch branch with exc_triggered signal so that it activates only when processor fetches an interrupt virtual instruction.