From 941f4cd10f05c141222e397071c3ce937322d8d1 Mon Sep 17 00:00:00 2001 From: billow Date: Thu, 27 Jun 2024 15:09:58 +0800 Subject: [PATCH] [skip ci]Xtensa+autosync: fix AddCSDetail --- .../src/autosync/cpptranslator/patches/AddCSDetail.py | 3 +++ 1 file changed, 3 insertions(+) diff --git a/suite/auto-sync/src/autosync/cpptranslator/patches/AddCSDetail.py b/suite/auto-sync/src/autosync/cpptranslator/patches/AddCSDetail.py index 45bccbc6f6..c1013b32af 100644 --- a/suite/auto-sync/src/autosync/cpptranslator/patches/AddCSDetail.py +++ b/suite/auto-sync/src/autosync/cpptranslator/patches/AddCSDetail.py @@ -34,6 +34,8 @@ class AddCSDetail(Patch): b"(SStream*O,ARM_AM::ShiftOpcShOpc,unsignedShImm,boolgetUseMarkup())", # ARM - printRegImmShift b"(MCInst*MI,unsignedOpNo,SStream*O,constchar*Modifier)", # PPC - printPredicateOperand b"(MCInst*MI,uint64_tAddress,unsignedOpNo,SStream*O)", # PPC - printBranchOperand + b"(MCInst*MI,intOpNum,SStream*O)", # Xtensa printOperand parameters. + b"(MCInst*MI,intOpNum,SStream*OS)", # Xtensa printOperand parameters. ] def __init__(self, priority: int, arch: str): @@ -45,6 +47,7 @@ def __init__(self, priority: int, arch: str): "PPCInstPrinter.cpp", "AArch64InstPrinter.cpp", "LoongArchInstPrinter.cpp", + "XtensaInstPrinter.cpp", ], "archs": list(), }