diff --git a/tests/cs_details/issue.cs b/tests/cs_details/issue.cs
index a4cd5cbd6d..6dff0033c8 100644
--- a/tests/cs_details/issue.cs
+++ b/tests/cs_details/issue.cs
@@ -204,3 +204,14 @@
 !# CS_ARCH_ARM, CS_MODE_ARM, CS_OPT_DETAIL
 0xef,0xf3,0x11,0x85 == ldrhi pc, [r1, #-0x3ef] ; op_count: 2 ; operands[0].type: REG = r15 ; operands[0].access: WRITE ; operands[1].type: MEM ; operands[1].mem.base: REG = r1 ; operands[1].mem.disp: 0x3ef ; operands[1].access: READ ; Code condition: 8 ; Registers read: cpsr r1 ; Registers modified: r15 ; Groups: IsARM jump
 
+!# issue 0 AArch64 operands
+!# CS_ARCH_AARCH64, CS_MODE_ARM, CS_OPT_DETAIL
+0xc0,0x08,0x9f,0xe0 == ld1w {za0h.s[w12, 0]}, p2/z, [x6] ; op_count: 3 ; operands[0].type: SME_MATRIX ; operands[0].sme.type: 2 ; operands[0].sme.mx.tile: za0.s ; operands[0].sme.mx.slice_reg: w12 ; operands[0].sme.mx.slice_offset: 0 ; operands[0].sme.mx.is_vertical: false ; operands[0].access: WRITE ; Vector Arrangement Specifier: 0x20 ; operands[1].type: SME_PRED ; operands[1].sme.pred.reg: p2 ; operands[1].access: READ ; operands[2].type: MEM ; operands[2].mem.base: REG = x6 ; operands[2].access: READ ; Registers read: za0.s w12 p2 x6 ; Groups: HasSME
+
+!# issue 0 AArch64 operands
+!# CS_ARCH_AARCH64, CS_MODE_ARM, CS_OPT_DETAIL
+0x41,0x31,0xa2,0xe0 == st1w {za0h.s[w13, 1]}, p4, [x10, x2, lsl #2] ; op_count: 3 ; operands[0].type: SME_MATRIX ; operands[0].sme.type: 2 ; operands[0].sme.mx.tile: za0.s ; operands[0].sme.mx.slice_reg: w13 ; operands[0].sme.mx.slice_offset: 1 ; operands[0].sme.mx.is_vertical: false ; operands[0].access: READ ; Vector Arrangement Specifier: 0x20 ; operands[1].type: SME_PRED ; operands[1].sme.pred.reg: p4 ; operands[1].access: READ ; operands[2].type: MEM ; operands[2].mem.base: REG = x10 ; operands[2].mem.index: REG = x2 ; operands[2].access: WRITE ; Shift: type = 1, value = 2 ; Registers read: za0.s w13 p4 x10 x2 ; Groups: HasSME
+
+!# issue 0 AArch64 operands
+!# CS_ARCH_AARCH64, CS_MODE_ARM, CS_OPT_DETAIL
+0x67,0x44,0x71,0x25 == psel p7, p1, p3.s[w13, 1] ; op_count: 3 ; operands[0].type: SME_PRED ; operands[0].sme.pred.reg: p7 ; operands[0].access: WRITE ; operands[1].type: SME_PRED ; operands[1].sme.pred.reg: p1 ; operands[1].access: READ ; operands[2].type: SME_PRED ; operands[2].sme.pred.reg: p3 ; operands[2].sme.pred.vec_select: w13 ; operands[2].sme.pred.index: 1 ; operands[2].access: READ ; Vector Arrangement Specifier: 0x20 ; Registers read: p7 p1 p3 w13 ; Groups: HasSVE2p1_or_HasSME