diff --git a/arch/AArch64/AArch64Disassembler.c b/arch/AArch64/AArch64Disassembler.c
index 1f5ff17a4b..31248c1ef8 100644
--- a/arch/AArch64/AArch64Disassembler.c
+++ b/arch/AArch64/AArch64Disassembler.c
@@ -1871,9 +1871,9 @@ static DecodeStatus DecodeUnconditionalBranch(MCInst *Inst, uint32_t insn,
 
 static bool isInvalidPState(uint64_t Op1, uint64_t Op2)
 {
-	return Op1 == 0b000 && (Op2 == 0b000 || // CFINV
-							Op2 == 0b001 || // XAFlag
-							Op2 == 0b010);	// AXFlag
+	return Op1 == 0 && (Op2 == 0 || // CFINV
+							Op2 == 1 || // XAFlag
+							Op2 == 2);  // AXFlag
 }
 
 static DecodeStatus DecodeSystemPStateImm0_15Instruction(MCInst *Inst,
@@ -1988,7 +1988,7 @@ static DecodeStatus DecodeSyspXzrInstruction(MCInst *Inst, uint32_t insn,
 	unsigned CRm = fieldFromInstruction_4(insn, 8, 4);
 	unsigned op2 = fieldFromInstruction_4(insn, 5, 3);
 	unsigned Rt = fieldFromInstruction_4(insn, 0, 5);
-	if (Rt != 0b11111)
+	if (Rt != 0x1f)
 		return Fail;
 
 	MCOperand_CreateImm0(Inst, (op1));
diff --git a/arch/PowerPC/PPCMapping.c b/arch/PowerPC/PPCMapping.c
index f3e4503f73..2d11674389 100644
--- a/arch/PowerPC/PPCMapping.c
+++ b/arch/PowerPC/PPCMapping.c
@@ -171,18 +171,18 @@ static void PPC_add_branch_predicates(MCInst *MI, const uint8_t *Bytes,
 	switch (bh) {
 	default:
 		assert(0 && "Invalid BH value.");
-	case 0b00:
+	case 0:
 		PPC_get_detail(MI)->bc.bh = cond ? PPC_BH_NO_SUBROUTINE_RET :
 						   PPC_BH_SUBROUTINE_RET;
 		break;
-	case 0b01:
+	case 1:
 		PPC_get_detail(MI)->bc.bh = cond ? PPC_BH_RESERVED :
 						   PPC_BH_NO_SUBROUTINE_RET;
 		break;
-	case 0b10:
+	case 2:
 		PPC_get_detail(MI)->bc.bh = PPC_BH_RESERVED;
 		break;
-	case 0b11:
+	case 3:
 		PPC_get_detail(MI)->bc.bh = PPC_BH_NOT_PREDICTABLE;
 		break;
 	}
diff --git a/bindings/python/capstone/arm_const.py b/bindings/python/capstone/arm_const.py
index df4f119e97..3e9d868566 100644
--- a/bindings/python/capstone/arm_const.py
+++ b/bindings/python/capstone/arm_const.py
@@ -21,21 +21,21 @@
 ARMVCC_None = 0
 ARMVCC_Then = 1
 ARMVCC_Else = 2
-ARM_T = 0b1000
-ARM_TT = 0b0100
-ARM_TE = 0b1100
-ARM_TTT = 0b0010
-ARM_TTE = 0b0110
-ARM_TEE = 0b1110
-ARM_TET = 0b1010
-ARM_TTTT = 0b0001
-ARM_TTTE = 0b0011
-ARM_TTEE = 0b0111
-ARM_TTET = 0b0101
-ARM_TEEE = 0b1111
-ARM_TEET = 0b1101
-ARM_TETT = 0b1001
-ARM_TETE = 0b1011
+ARM_T = 0x8
+ARM_TT = 0x4
+ARM_TE = 0xc
+ARM_TTT = 0x2
+ARM_TTE = 0x6
+ARM_TEE = 0xe
+ARM_TET = 0xa
+ARM_TTTT = 0x1
+ARM_TTTE = 0x3
+ARM_TTEE = 0x7
+ARM_TTET = 0x5
+ARM_TEEE = 0xf
+ARM_TEET = 0xd
+ARM_TETT = 0x9
+ARM_TETE = 0xb
 
 ARM_SFT_INVALID = 0
 ARM_SFT_ASR = 1
diff --git a/bindings/python/capstone/ppc_const.py b/bindings/python/capstone/ppc_const.py
index f74a693e44..48676de4e2 100644
--- a/bindings/python/capstone/ppc_const.py
+++ b/bindings/python/capstone/ppc_const.py
@@ -52,16 +52,16 @@
 PPC_BI_Z = 2
 PPC_BI_SO = 3
 PPC_BI_INVALID = 0xff
-PPC_BO_TEST_CR = 0b10000
-PPC_BO_CR_CMP = 0b01000
-PPC_BO_DECR_CTR = 0b00100
-PPC_BO_CTR_CMP = 0b00010
-PPC_BO_T = 0b00001
-PPC_BR_NOT_GIVEN = 0b00
-PPC_BR_RESERVED = 0b01
-PPC_BR_NOT_TAKEN = 0b10
-PPC_BR_TAKEN = 0b11
-PPC_BR_HINT_MASK = 0b11
+PPC_BO_TEST_CR = (1<<4)
+PPC_BO_CR_CMP = (1<<3)
+PPC_BO_DECR_CTR = (1<<2)
+PPC_BO_CTR_CMP = (1<<1)
+PPC_BO_T = 1
+PPC_BR_NOT_GIVEN = 0x0
+PPC_BR_RESERVED = 0x1
+PPC_BR_NOT_TAKEN = 0x2
+PPC_BR_TAKEN = 0x3
+PPC_BR_HINT_MASK = 0x3
 
 PPC_BH_INVALID = 0
 PPC_BH_SUBROUTINE_RET = 1
diff --git a/include/capstone/arm.h b/include/capstone/arm.h
index dfc69944cf..1fc608eb0b 100644
--- a/include/capstone/arm.h
+++ b/include/capstone/arm.h
@@ -125,21 +125,21 @@ typedef enum VPTCodes {
 ///   Txy = xy10
 ///   Txyz = xyz1
 typedef enum PredBlockMask {
-  ARM_T = 0b1000,
-  ARM_TT = 0b0100,
-  ARM_TE = 0b1100,
-  ARM_TTT = 0b0010,
-  ARM_TTE = 0b0110,
-  ARM_TEE = 0b1110,
-  ARM_TET = 0b1010,
-  ARM_TTTT = 0b0001,
-  ARM_TTTE = 0b0011,
-  ARM_TTEE = 0b0111,
-  ARM_TTET = 0b0101,
-  ARM_TEEE = 0b1111,
-  ARM_TEET = 0b1101,
-  ARM_TETT = 0b1001,
-  ARM_TETE = 0b1011
+  ARM_T = 0x8, // 0b1000
+  ARM_TT = 0x4, // 0b0100
+  ARM_TE = 0xc, // 0b1100
+  ARM_TTT = 0x2, // 0b0010
+  ARM_TTE = 0x6, // 0b0110
+  ARM_TEE = 0xe, // 0b1110
+  ARM_TET = 0xa, // 0b1010
+  ARM_TTTT = 0x1, // 0b0001
+  ARM_TTTE = 0x3, // 0b0011
+  ARM_TTEE = 0x7, // 0b0111
+  ARM_TTET = 0x5, // 0b0101
+  ARM_TEEE = 0xf, // 0b1111
+  ARM_TEET = 0xd, // 0b1101
+  ARM_TETT = 0x9, // 0b1001
+  ARM_TETE = 0xb, // 0b1011
 } ARM_PredBlockMask;
 
 // Expands a PredBlockMask by adding an E or a T at the end, depending on Kind.
diff --git a/include/capstone/ppc.h b/include/capstone/ppc.h
index b38c4eee97..820dc06a1a 100644
--- a/include/capstone/ppc.h
+++ b/include/capstone/ppc.h
@@ -124,11 +124,11 @@ typedef enum {
 
 /// Masks of flags in the BO field.
 typedef enum {
-	PPC_BO_TEST_CR = 0b10000,  ///< Flag mask: Test CR bit.
-	PPC_BO_CR_CMP = 0b01000,   ///< Flag mask: Compare CR bit to 0 or 1.
-	PPC_BO_DECR_CTR = 0b00100, ///< Flag mask: Decrement counter.
-	PPC_BO_CTR_CMP = 0b00010,  ///< Flag mask: Compare CTR to 0 or 1.
-	PPC_BO_T = 0b00001,	   ///< Either ignored (z) or hint bit t
+	PPC_BO_TEST_CR = (1 << 4),  ///< Flag mask: Test CR bit.
+	PPC_BO_CR_CMP = (1 << 3),   ///< Flag mask: Compare CR bit to 0 or 1.
+	PPC_BO_DECR_CTR = (1 << 2), ///< Flag mask: Decrement counter.
+	PPC_BO_CTR_CMP = (1 << 1),  ///< Flag mask: Compare CTR to 0 or 1.
+	PPC_BO_T = 1,               ///< Either ignored (z) or hint bit t
 } ppc_bo_mask;
 
 /// Bit for branch taken (plus) or not-taken (minus) hint
@@ -136,11 +136,11 @@ typedef enum {
 /// Bit:  | 0 | 1 |
 /// Name: | a | t |
 typedef enum {
-	PPC_BR_NOT_GIVEN = 0b00,
-	PPC_BR_RESERVED = 0b01,
-	PPC_BR_NOT_TAKEN = 0b10, ///< Minus
-	PPC_BR_TAKEN = 0b11,	 ///< Plus
-	PPC_BR_HINT_MASK = 0b11,
+	PPC_BR_NOT_GIVEN = 0x0,
+	PPC_BR_RESERVED = 0x1,
+	PPC_BR_NOT_TAKEN = 0x2, ///< Minus
+	PPC_BR_TAKEN = 0x3,     ///< Plus
+	PPC_BR_HINT_MASK = 0x3,
 } ppc_br_hint;
 
 /// Encodes the different meanings of the BH field.