diff --git a/arch/Xtensa/XtensaMapping.c b/arch/Xtensa/XtensaMapping.c
index 68774918e0..2b676279f0 100644
--- a/arch/Xtensa/XtensaMapping.c
+++ b/arch/Xtensa/XtensaMapping.c
@@ -66,7 +66,7 @@ static void set_instr_map_data(MCInst *MI)
 		operand->type = op->type;
 		MCOperand *mc = MCInst_getOperand(MI, i);
 
-#define check(_k) if ((op->type & _k) == _k)
+#define check(_k) if ((op->type & (_k)) == (_k))
 		check(CS_OP_IMM)
 		{
 			operand->imm = (int32_t)mc->ImmVal;
@@ -75,8 +75,22 @@ static void set_instr_map_data(MCInst *MI)
 		{
 			operand->reg = (uint8_t)mc->RegVal;
 		}
-		check(CS_OP_MEM)
+		check(CS_OP_MEM_REG)
 		{
+			operand->mem.base = mc->RegVal;
+		}
+		check(CS_OP_MEM_IMM)
+		{
+			if (i > 0) {
+				cs_xtensa_op *prev = (operand - 1);
+				if (prev->type == CS_OP_MEM_REG &&
+				    prev->access == op->access) {
+					prev->type = Xtensa_OP_MEM;
+					prev->mem.disp = mc->ImmVal;
+					continue;
+				}
+			}
+			operand->mem.disp = mc->ImmVal;
 		}
 
 		detail->op_count++;
@@ -168,11 +182,6 @@ void Xtensa_reg_access(const cs_insn *insn, cs_regs regs_read,
 				regs_read[read_count] = (uint16_t)op->mem.base;
 				read_count++;
 			}
-			if ((op->mem.index != Xtensa_REG_INVALID) &&
-			    !arr_exist(regs_read, read_count, op->mem.index)) {
-				regs_read[read_count] = (uint16_t)op->mem.index;
-				read_count++;
-			}
 			if ((insn->detail->writeback) &&
 			    (op->mem.base != Xtensa_REG_INVALID) &&
 			    !arr_exist(regs_write, write_count, op->mem.base)) {
diff --git a/cstool/cstool_xtensa.c b/cstool/cstool_xtensa.c
index 4fa10b9f21..b5d3332149 100644
--- a/cstool/cstool_xtensa.c
+++ b/cstool/cstool_xtensa.c
@@ -32,7 +32,7 @@ void print_insn_detail_xtensa(csh handle, cs_insn *ins, Stream *steam)
 			       "\t\t\t.mem.base: REG = %s\n"
 			       "\t\t\t.mem.disp: 0x%" PRIx8 "\n",
 			       i, cs_reg_name(handle, op->mem.base),
-			       op->mem.index);
+			       op->mem.disp);
 		check_access(CS_AC_READ) printf("\t\t\t.access: READ\n");
 		else check_access(CS_AC_WRITE) printf("\t\t\t.access: WRITE\n");
 		else check_access(CS_AC_READ | CS_AC_WRITE)
diff --git a/include/capstone/xtensa.h b/include/capstone/xtensa.h
index 7d9703ad9e..c374b64b00 100644
--- a/include/capstone/xtensa.h
+++ b/include/capstone/xtensa.h
@@ -143,15 +143,17 @@ Xtensa_FEATURE_HasDensity = 128,
 } xtensa_feature;
 
 typedef enum cs_xtensa_op_type {
-	Xtensa_OP_INVALID = CS_OP_INVALID, ///< = CS_OP_INVALID (Uninitialized).
-	Xtensa_OP_REG = CS_OP_REG,	   ///< = CS_OP_REG (Register operand).
-	Xtensa_OP_IMM = CS_OP_IMM,	   ///< = CS_OP_IMM (Immediate operand).
-	Xtensa_OP_MEM = CS_OP_MEM,	   ///< = CS_OP_MEM (Memory operand).
+	Xtensa_OP_INVALID = CS_OP_INVALID, ///< = (Uninitialized).
+	Xtensa_OP_REG = CS_OP_REG,	   ///< = (Register operand).
+	Xtensa_OP_IMM = CS_OP_IMM,	   ///< = (Immediate operand).
+	Xtensa_OP_MEM = CS_OP_MEM,	   ///< = (Memory operand).
+	Xtensa_OP_MEM_REG = CS_OP_MEM_REG, ///< = (Memory Register operand).
+	Xtensa_OP_MEM_IMM = CS_OP_MEM_IMM, ///< = (Memory Immediate operand).
 } cs_xtensa_op_type;
 
 typedef struct cs_xtensa_op_mem {
 	uint8_t base;
-	uint8_t index;
+	uint8_t disp;
 } cs_xtensa_op_mem;
 
 typedef struct cs_xtensa_operand {