diff --git a/CHANGELOG.md b/CHANGELOG.md
index 202e0626d4..fa9d91ee8a 100644
--- a/CHANGELOG.md
+++ b/CHANGELOG.md
@@ -1,9 +1,8 @@
-## 0.5.0
+## Unreleased
 - Don't require `@clk` and `@reset` ports in `comb` components
 - `inline` pass supports inlining `ref` cells
 - `comb-prop`: disable rewrite from `wire.in = port` when the output of a wire is read.
 - BREAKING: Remove `PortDef::into()` because it makes it easy to miss copying attributes.
-- Remove the `futil` binary.
 - The `calyx` binary ships all the primitives and therefore self-contained now.
     - Add the `calyx-stdlib` package
     - Add a new build script that installs primitives when the package is installed.
diff --git a/Cargo.lock b/Cargo.lock
index ddb4982bb6..92dbe4d51b 100644
--- a/Cargo.lock
+++ b/Cargo.lock
@@ -184,7 +184,7 @@ checksum = "14c189c53d098945499cdfa7ecc63567cf3886b3332b312a5b4585d8d3a6a610"
 
 [[package]]
 name = "calyx"
-version = "0.5.0"
+version = "0.4.0"
 dependencies = [
  "argh",
  "atty",
@@ -207,7 +207,7 @@ dependencies = [
 
 [[package]]
 name = "calyx-frontend"
-version = "0.5.0"
+version = "0.4.0"
 dependencies = [
  "atty",
  "calyx-utils",
@@ -227,7 +227,7 @@ dependencies = [
 
 [[package]]
 name = "calyx-ir"
-version = "0.5.0"
+version = "0.4.0"
 dependencies = [
  "calyx-frontend",
  "calyx-utils",
@@ -243,7 +243,7 @@ dependencies = [
 
 [[package]]
 name = "calyx-opt"
-version = "0.5.0"
+version = "0.4.0"
 dependencies = [
  "boolean_expression",
  "calyx-ir",
@@ -260,11 +260,11 @@ dependencies = [
 
 [[package]]
 name = "calyx-stdlib"
-version = "0.5.0"
+version = "0.4.0"
 
 [[package]]
 name = "calyx-utils"
-version = "0.5.0"
+version = "0.4.0"
 dependencies = [
  "atty",
  "itertools 0.10.5",
diff --git a/Cargo.toml b/Cargo.toml
index 7f6eafdbbd..247ea4832b 100644
--- a/Cargo.toml
+++ b/Cargo.toml
@@ -23,7 +23,7 @@ description = "Compiler Infrastructure for Hardware Accelerator Generation"
 categories = ["compilers"]
 homepage = "https://calyxir.org"
 edition = "2021"
-version = "0.5.0"
+version = "0.4.0"
 rust-version = "1.66"
 
 [workspace.dependencies]
@@ -41,10 +41,10 @@ pest = "2.0"
 pest_derive = "2"
 pest_consume = "1"
 argh = "0.1"
-calyx-utils = { path = "calyx-utils", version = "0.5.0" }
-calyx-ir = { path = "calyx-ir", version = "0.5.0" }
-calyx-frontend = { path = "calyx-frontend", version = "0.5.0" }
-calyx-opt = { path = "calyx-opt", version = "0.5.0" }
+calyx-utils = { path = "calyx-utils", version = "0.4.0" }
+calyx-ir = { path = "calyx-ir", version = "0.4.0" }
+calyx-frontend = { path = "calyx-frontend", version = "0.4.0" }
+calyx-opt = { path = "calyx-opt", version = "0.4.0" }
 
 [workspace.dependencies.petgraph]
 version = "0.6"
@@ -73,6 +73,10 @@ build = "src/build.rs"
 name = "calyx"
 path = "src/main.rs"
 
+[[bin]]
+name = "futil"
+path = "src/futil.rs"
+
 [features]
 default = []
 serialize = [
@@ -83,7 +87,8 @@ serialize = [
 ]
 
 [build-dependencies]
-calyx-stdlib = { path = "calyx-stdlib", version = "0.5.0" }
+calyx-stdlib = { path = "calyx-stdlib", version = "0.4.0" }
+
 
 [dependencies]
 atty.workspace = true
diff --git a/calyx-py/calyx/builder.py b/calyx-py/calyx/builder.py
index 94a6860373..f59012d776 100644
--- a/calyx-py/calyx/builder.py
+++ b/calyx-py/calyx/builder.py
@@ -346,10 +346,6 @@ def le(self, size: int, name: str = None, signed: bool = False) -> CellBuilder:
         """Generate a StdLe cell."""
         return self.binary("le", size, name, signed)
 
-    def rsh(self, size: int, name: str = None, signed: bool = False) -> CellBuilder:
-        """Generate a StdRsh cell."""
-        return self.binary("rsh", size, name, signed)
-
     def logic(self, operation, size: int, name: str = None) -> CellBuilder:
         """Generate a logical operator cell, of the flavor specified in `operation`."""
         name = name or self.generate_name(operation)
@@ -358,12 +354,10 @@ def logic(self, operation, size: int, name: str = None) -> CellBuilder:
 
     def and_(self, size: int, name: str = None) -> CellBuilder:
         """Generate a StdAnd cell."""
-        name = name or self.generate_name("and")
         return self.logic("and", size, name)
 
     def not_(self, size: int, name: str = None) -> CellBuilder:
         """Generate a StdNot cell."""
-        name = name or self.generate_name("not")
         return self.logic("not", size, name)
 
     def pipelined_mult(self, name: str) -> CellBuilder:
@@ -428,7 +422,7 @@ def binary_use(self, left, right, cell, groupname=None):
             cell.right = right
         return CellAndGroup(cell, comb_group)
 
-    def eq_use(self, left, right, width=None, signed=False, cellname=None):
+    def eq_use(self, left, right, width=None, cellname=None):
         """Inserts wiring into `self` to check if `left` == `right`."""
         width = width or self.infer_width(left) or self.infer_width(right)
         if not width:
@@ -436,35 +430,35 @@ def eq_use(self, left, right, width=None, signed=False, cellname=None):
                 "Cannot infer widths from `left` or `right` to create an eq cell. "
                 "Consider providing width as an argument."
             )
-        return self.binary_use(left, right, self.eq(width, cellname, signed))
+        return self.binary_use(left, right, self.eq(width, cellname))
 
-    def neq_use(self, left, right, width, signed=False, cellname=None):
+    def neq_use(self, left, right, width, cellname=None):
         """Inserts wiring into `self` to check if `left` != `right`."""
-        return self.binary_use(left, right, self.neq(width, cellname, signed))
+        return self.binary_use(left, right, self.neq(width, cellname))
 
-    def lt_use(self, left, right, width, signed=False, cellname=None):
+    def lt_use(self, left, right, width, cellname=None):
         """Inserts wiring into `self` to check if `left` < `right`."""
-        return self.binary_use(left, right, self.lt(width, cellname, signed))
+        return self.binary_use(left, right, self.lt(width, cellname))
 
-    def le_use(self, left, right, width, signed=False, cellname=None):
+    def le_use(self, left, right, width, cellname=None):
         """Inserts wiring into `self` to check if `left` <= `right`."""
-        return self.binary_use(left, right, self.le(width, cellname, signed))
+        return self.binary_use(left, right, self.le(width, cellname))
 
-    def ge_use(self, left, right, width, signed=False, cellname=None):
+    def ge_use(self, left, right, width, cellname=None):
         """Inserts wiring into `self` to check if `left` >= `right`."""
-        return self.binary_use(left, right, self.ge(width, cellname, signed))
+        return self.binary_use(left, right, self.ge(width, cellname))
 
-    def gt_use(self, left, right, width, signed=False, cellname=None):
+    def gt_use(self, left, right, width, cellname=None):
         """Inserts wiring into `self` to check if `left` > `right`."""
-        return self.binary_use(left, right, self.gt(width, cellname, signed))
+        return self.binary_use(left, right, self.gt(width, cellname))
 
-    def add_use(self, left, right, width, signed=False, cellname=None):
+    def add_use(self, left, right, width, cellname=None):
         """Inserts wiring into `self` to compute `left` + `right`."""
-        return self.binary_use(left, right, self.add(width, cellname, signed))
+        return self.binary_use(left, right, self.add(width, cellname))
 
-    def sub_use(self, left, right, width, signed=False, cellname=None):
+    def sub_use(self, left, right, width, cellname=None):
         """Inserts wiring into `self` to compute `left` - `right`."""
-        return self.binary_use(left, right, self.sub(width, cellname, signed))
+        return self.binary_use(left, right, self.sub(width, cellname))
 
     def bitwise_flip_reg(self, reg, cellname=None):
         """Inserts wiring into `self` to bitwise-flip the contents of `reg`
@@ -480,11 +474,11 @@ def bitwise_flip_reg(self, reg, cellname=None):
             not_group.done = reg.done
         return not_group
 
-    def incr(self, reg, val=1, signed=False, cellname=None):
+    def incr(self, reg, val=1, cellname=None):
         """Inserts wiring into `self` to perform `reg := reg + val`."""
         cellname = cellname or f"{reg.name}_incr"
         width = reg.infer_width("in")
-        add_cell = self.add(width, cellname, signed)
+        add_cell = self.add(width, cellname)
         with self.group(f"{cellname}_group") as incr_group:
             add_cell.left = reg.out
             add_cell.right = val
@@ -493,11 +487,11 @@ def incr(self, reg, val=1, signed=False, cellname=None):
             incr_group.done = reg.done
         return incr_group
 
-    def decr(self, reg, val=1, signed=False, cellname=None):
+    def decr(self, reg, val=1, cellname=None):
         """Inserts wiring into `self` to perform `reg := reg - val`."""
         cellname = cellname or f"{reg.name}_decr"
         width = reg.infer_width("in")
-        sub_cell = self.sub(width, cellname, signed)
+        sub_cell = self.sub(width, cellname)
         with self.group(f"{cellname}_group") as decr_group:
             sub_cell.left = reg.out
             sub_cell.right = val
@@ -592,48 +586,67 @@ def mem_load_to_mem(self, mem, i, ans, j, groupname=None):
             load_grp.done = ans.done
         return load_grp
 
-    def op_store_in_reg(self, op_cell, left, right, cellname, width, ans_reg=None):
-        """Inserts wiring into `self` to perform `reg := left op right`,
-        where `op_cell`, a Cell that performs some `op`, is provided.
-        """
+    def add_store_in_reg(self, left, right, cellname, width, ans_reg=None):
+        """Inserts wiring into `self` to perform `reg := left + right`."""
+        add_cell = self.add(width, cellname)
         ans_reg = ans_reg or self.reg(f"reg_{cellname}", width)
-        with self.group(f"{cellname}_group") as op_group:
-            op_cell.left = left
-            op_cell.right = right
+        with self.group(f"{cellname}_group") as adder_group:
+            add_cell.left = left
+            add_cell.right = right
             ans_reg.write_en = 1
-            ans_reg.in_ = op_cell.out
-            op_group.done = ans_reg.done
-        return op_group, ans_reg
-
-    def add_store_in_reg(
-        self, left, right, cellname, width, ans_reg=None, signed=False
-    ):
-        """Inserts wiring into `self` to perform `reg := left + right`."""
-        return self.op_store_in_reg(
-            self.add(width, cellname, signed), left, right, cellname, width, ans_reg
-        )
+            ans_reg.in_ = add_cell.out
+            adder_group.done = ans_reg.done
+        return adder_group, ans_reg
 
-    def sub_store_in_reg(
-        self, left, right, cellname, width, ans_reg=None, signed=False
-    ):
+    def sub_store_in_reg(self, left, right, cellname, width, ans_reg=None):
         """Inserts wiring into `self` to perform `reg := left - right`."""
-        return self.op_store_in_reg(
-            self.sub(width, cellname, signed), left, right, cellname, width, ans_reg
-        )
-
-    def eq_store_in_reg(self, left, right, cellname, width, ans_reg=None, signed=False):
-        """Adds wiring into `self to perform `reg := left == right`."""
-        return self.op_store_in_reg(
-            self.eq(width, cellname, signed), left, right, cellname, 1, ans_reg
-        )
-
-    def neq_store_in_reg(
-        self, left, right, cellname, width, ans_reg=None, signed=False
-    ):
-        """Adds wiring into `self to perform `reg := left != right`."""
-        return self.op_store_in_reg(
-            self.neq(width, cellname, signed), left, right, cellname, 1, ans_reg
-        )
+        sub_cell = self.sub(width, cellname)
+        ans_reg = ans_reg or self.reg(f"reg_{cellname}", width)
+        with self.group(f"{cellname}_group") as sub_group:
+            sub_cell.left = left
+            sub_cell.right = right
+            ans_reg.write_en = 1
+            ans_reg.in_ = sub_cell.out
+            sub_group.done = ans_reg.done
+        return sub_group, ans_reg
+
+    def eq_store_in_reg(self, left, right, cellname, width, ans_reg=None):
+        """Adds wiring into component `self` to compute `left` == `right`
+        and store it in `ans_reg`.
+        1. Within component `self`, creates a group called `cellname`_group.
+        2. Within `group`, create a cell `cellname` that computes equality.
+        3. Puts the values of `left` and `right` into `cell`.
+        4. Then puts the answer of the computation into `ans_reg`.
+        4. Returns the equality group and the register.
+        """
+        eq_cell = self.eq(width, cellname)
+        ans_reg = ans_reg or self.reg(f"reg_{cellname}", 1)
+        with self.group(f"{cellname}_group") as eq_group:
+            eq_cell.left = left
+            eq_cell.right = right
+            ans_reg.write_en = 1
+            ans_reg.in_ = eq_cell.out
+            eq_group.done = ans_reg.done
+        return eq_group, ans_reg
+
+    def neq_store_in_reg(self, left, right, cellname, width, ans_reg=None):
+        """Adds wiring into component `self` to compute `left` != `right`
+        and store it in `ans_reg`.
+        1. Within component `self`, creates a group called `cellname`_group.
+        2. Within `group`, create a cell `cellname` that computes inequality.
+        3. Puts the values of `left` and `right` into `cell`.
+        4. Then puts the answer of the computation into `ans_reg`.
+        4. Returns the inequality group and the register.
+        """
+        neq_cell = self.neq(width, cellname)
+        ans_reg = ans_reg or self.reg(f"reg_{cellname}", 1)
+        with self.group(f"{cellname}_group") as neq_group:
+            neq_cell.left = left
+            neq_cell.right = right
+            ans_reg.write_en = 1
+            ans_reg.in_ = neq_cell.out
+            neq_group.done = ans_reg.done
+        return neq_group, ans_reg
 
     def infer_width(self, expr) -> int:
         """Infer the width of an expression.
diff --git a/calyx-py/calyx/gen_exp.py b/calyx-py/calyx/gen_exp.py
index 9a74122824..df389290aa 100644
--- a/calyx-py/calyx/gen_exp.py
+++ b/calyx-py/calyx/gen_exp.py
@@ -49,6 +49,8 @@ def generate_fp_pow_component(
             "mult_pipe", width, int_width, frac_width, signed=is_signed
         ),
     )
+    lt = comp.cell("lt", Stdlib.op("lt", width, signed=is_signed))
+    incr = comp.cell("incr", Stdlib.op("add", width, signed=is_signed))
 
     # groups
     with comp.group("init") as init:
@@ -68,14 +70,27 @@ def generate_fp_pow_component(
         pow.in_ = mul.out
         execute_mul.done = pow.done
 
-    incr_count = comp.incr(count, width, 1, is_signed)
+    with comp.group("incr_count") as incr_count:
+        incr.left = const(width, 1)
+        incr.right = count.out
+        count.in_ = incr.out
+        count.write_en = 1
+        incr_count.done = count.done
 
-    cond = comp.lt_use(count.out, comp.this().integer_exp, width, is_signed)
+    with comp.comb_group("cond") as cond:
+        lt.left = count.out
+        lt.right = comp.this().integer_exp
 
     with comp.continuous:
         comp.this().out = pow.out
 
-    comp.control += [init, while_with(cond, par(execute_mul, incr_count))]
+    comp.control += [
+        init,
+        while_with(
+            CellAndGroup(lt, cond),
+            par(execute_mul, incr_count),
+        ),
+    ]
 
     return comp.component
 
@@ -90,12 +105,11 @@ def generate_cells(
     comp.reg("int_x", width)
     comp.reg("frac_x", width)
     comp.reg("m", width)
-
-    comp.and_(width, "and0")
-    comp.and_(width, "and1")
-    comp.rsh(width, "rsh")
+    comp.cell("and0", Stdlib.op("and", width, signed=False))
+    comp.cell("and1", Stdlib.op("and", width, signed=False))
+    comp.cell("rsh", Stdlib.op("rsh", width, signed=False))
     if is_signed:
-        comp.lt(width, "lt", is_signed)
+        comp.cell("lt", Stdlib.op("lt", width, signed=is_signed))
 
     # constants
     for i in range(2, degree + 1):
@@ -527,6 +541,21 @@ def gen_reverse_sign(
         group.done = base_cell.done
 
 
+def gen_comb_lt(
+    comp: ComponentBuilder,
+    name: str,
+    lhs: ExprBuilder,
+    lt: CellBuilder,
+    const_cell: CellBuilder,
+):
+    """
+    Generates lhs < const_cell
+    """
+    with comp.comb_group(name):
+        lt.left = lhs
+        lt.right = const_cell.out
+
+
 # This appears to be unused. Brilliant.
 # TODO (griffin): Double check that this is unused and, if so, remove it.
 def gen_constant_cell(
@@ -561,8 +590,7 @@ def generate_fp_pow_full(
     comp.input("base", width)
     comp.input("exp_value", width)
     comp.output("out", width)
-    lt = comp.lt(width, "lt", is_signed)
-
+    lt = comp.cell("lt", Stdlib.op("lt", width, is_signed))
     div = comp.cell(
         "div",
         Stdlib.fixed_point_op(
@@ -604,13 +632,7 @@ def generate_fp_pow_full(
         )
         gen_reverse_sign(comp, "rev_base_sign", new_base_reg, mult, const_neg_one),
         gen_reverse_sign(comp, "rev_res_sign", res, mult, const_neg_one),
-
-        base_lt_zero = comp.lt_use(
-            comp.this().base,
-            const_zero.out,
-            width,
-            is_signed,
-        )
+        gen_comb_lt(comp, "base_lt_zero", comp.this().base, lt, const_zero),
 
     new_exp_val = comp.reg("new_exp_val", width)
     e = comp.comp_instance("e", "exp", check_undeclared=False)
@@ -627,29 +649,48 @@ def generate_fp_pow_full(
     with comp.continuous:
         comp.this().out = res.out
 
-    write_to_base_reg = comp.reg_store(
-        new_base_reg, comp.this().base, "write_to_base_reg"
-    )
-    store_old_reg_val = comp.reg_store(
-        stored_base_reg, new_base_reg.out, "store_old_reg_val"
-    )
-    write_e_to_res = comp.reg_store(res, e.out, "write_e_to_res")
+    with comp.group("write_to_base_reg") as write_to_base_reg:
+        new_base_reg.write_en = 1
+        new_base_reg.in_ = comp.this().base
+        write_to_base_reg.done = new_base_reg.done
+
+    with comp.group("store_old_reg_val") as store_old_reg_val:
+        stored_base_reg.write_en = 1
+        stored_base_reg.in_ = new_base_reg.out
+        store_old_reg_val.done = stored_base_reg.done
+
+    with comp.group("write_e_to_res") as write_e_to_res:
+        res.write_en = 1
+        res.in_ = e.out
+        write_e_to_res.done = res.done
 
     gen_reciprocal(comp, "set_base_reciprocal", new_base_reg, div, const_one)
     gen_reciprocal(comp, "set_res_reciprocal", res, div, const_one),
-    base_lt_one = comp.lt_use(stored_base_reg.out, const_one.out, width, is_signed)
+    gen_comb_lt(
+        comp,
+        "base_lt_one",
+        stored_base_reg.out,
+        lt,
+        const_one,
+    )
 
-    base_reciprocal = if_with(base_lt_one, comp.get_group("set_base_reciprocal"))
+    base_reciprocal = if_with(
+        CellAndGroup(lt, comp.get_group("base_lt_one")),
+        comp.get_group("set_base_reciprocal"),
+    )
 
-    res_reciprocal = if_with(base_lt_one, comp.get_group("set_res_reciprocal"))
+    res_reciprocal = if_with(
+        CellAndGroup(lt, comp.get_group("base_lt_one")),
+        comp.get_group("set_res_reciprocal"),
+    )
 
     if is_signed:
         base_rev = if_with(
-            base_lt_zero,
+            CellAndGroup(lt, comp.get_group("base_lt_zero")),
             comp.get_group("rev_base_sign"),
         )
         res_rev = if_with(
-            base_lt_zero,
+            CellAndGroup(lt, comp.get_group("base_lt_zero")),
             comp.get_group("rev_res_sign"),
         )
         pre_process = [base_rev, store_old_reg_val, base_reciprocal]
@@ -700,9 +741,23 @@ def build_base_not_e(degree, width, int_width, is_signed) -> Program:
     ret = main.mem_d1("ret", width, 1, 1, is_external=True)
     f = main.comp_instance("f", "fp_pow_full")
 
-    read_base = main.mem_load_std_d1(b, 0, base_reg, "read_base")
-    read_exp = main.mem_load_std_d1(x, 0, exp_reg, "read_exp")
-    write_to_memory = main.mem_store_std_d1(ret, 0, f.out, "write_to_memory")
+    with main.group("read_base") as read_base:
+        b.addr0 = 0
+        base_reg.in_ = b.read_data
+        base_reg.write_en = 1
+        read_base.done = base_reg.done
+
+    with main.group("read_exp") as read_exp:
+        x.addr0 = 0
+        exp_reg.in_ = x.read_data
+        exp_reg.write_en = 1
+        read_exp.done = exp_reg.done
+
+    with main.group("write_to_memory") as write_to_memory:
+        ret.addr0 = 0
+        ret.write_en = 1
+        ret.write_data = f.out
+        write_to_memory.done = ret.done
 
     main.control += [
         read_base,
@@ -741,7 +796,11 @@ def build_base_is_e(degree, width, int_width, is_signed) -> Program:
         t.write_en = 1
         init.done = t.done
 
-    write_to_memory = main.mem_store_std_d1(ret, 0, e.out, "write_to_memory")
+    with main.group("write_to_memory") as write_to_memory:
+        ret.addr0 = 0
+        ret.write_en = 1
+        ret.write_data = e.out
+        write_to_memory.done = ret.done
 
     main.control += [
         init,
diff --git a/docs/compiler-as-library.md b/docs/compiler-as-library.md
index 473c0ba47a..b4336f32c0 100644
--- a/docs/compiler-as-library.md
+++ b/docs/compiler-as-library.md
@@ -13,7 +13,7 @@ The [`calyx` binary][calyx-crate] is published using Rust's crates.io repository
 
 1. The [`calyx-stdlib`][calyx-stdlib] package pulls in the sources of all the primitives using the Rust `include_str!` macro.
 2. The `calyx` binary defines a build script that depends on `calyx-stdlib` as a build dependency.
-3. During build time, the script loads the string representation of all the primitives files and writes them to `$CALYX_PRIMITIVE_DIR/primitives`. If the variable is not set, the location defaults to `$HOME/.calyx`.
+3. During build time, the script loads the string representation of all the primitives files and writes them to `$OUT_DIR/primitives`. The `OUT_DIR` environment variable is defined by `cargo`.
 4. If (3) succeeds, the build scripts defines the `CALYX_PRIMITIVES_LIB` environment variable which is used when compiling the `calyx` crate.
 5. During compilation, `calyx` embeds the value of this environment variable as the default argument to the `-l` flag. If the variable is not defined, the default value of the `-l` flag is `.`.
 
diff --git a/src/build.rs b/src/build.rs
index a66c4f445d..3a916d1f66 100644
--- a/src/build.rs
+++ b/src/build.rs
@@ -1,80 +1,23 @@
-use std::{env, fs, io::Result, path};
+use std::fs;
+use std::io::Result;
+use std::path;
 
-/// Location to install the primitives library
-const PRIM_DIR: &str = "CALYX_PRIMITIVES_DIR";
-
-struct PrimState {
-    base: path::PathBuf,
-    old_prims: Option<path::PathBuf>,
-    new_prims: path::PathBuf,
-}
-
-/// Move the old primitives directory to a different location if present and create a new one.
-fn move_primitives() -> Result<PrimState> {
-    let base: path::PathBuf = match env::var_os(PRIM_DIR) {
-        Some(v) => path::PathBuf::from(v),
-        None => {
-            let mut path: path::PathBuf = env::var_os("HOME").unwrap().into();
-            path.push(".calyx");
-            path
-        }
-    };
+fn write_primitive() -> Result<path::PathBuf> {
+    // Get the OUT_DIR environment variable from Cargo.
+    let base: path::PathBuf = std::env::var("OUT_DIR").unwrap().into();
     let mut prims = base.clone();
     prims.push("primitives");
-    let old_prims = if prims.exists() {
-        let mut old_prims = base.clone();
-        old_prims.push("old_primitives");
-        fs::rename(&prims, &old_prims)?;
-        Some(old_prims)
-    } else {
-        None
-    };
-
-    // Create the directory again
     fs::create_dir_all(&prims)?;
-    Ok(PrimState {
-        base,
-        old_prims,
-        new_prims: prims,
-    })
-}
-
-fn write_primitive(prims: &path::Path) -> Result<()> {
-    // Get the OUT_DIR environment variable from Cargo.
     // Write the compile primitives
     for (loc, src) in calyx_stdlib::KNOWN_LIBS
         .into_iter()
         .flat_map(|(_, info)| info)
         .chain(Some(calyx_stdlib::COMPILE_LIB))
     {
-        let mut path = prims.to_owned().clone();
+        let mut path = prims.clone();
         path.push(loc);
         fs::write(path, src)?;
     }
-    Ok(())
-}
-
-fn create_primitives() -> Result<path::PathBuf> {
-    let PrimState {
-        base,
-        old_prims,
-        new_prims: prims,
-    } = move_primitives()?;
-    match write_primitive(prims.as_path()) {
-        Ok(_) => {
-            if let Some(old) = old_prims {
-                fs::remove_dir_all(old)?;
-            }
-        }
-        Err(e) => {
-            // Move the old primitives back
-            println!("cargo:warning=Failed to write primitives directory. Restoring old directory");
-            if let Some(old) = old_prims {
-                fs::rename(old, &prims)?;
-            }
-            return Err(e);
-        }
-    }
     Ok(base)
 }
 
@@ -82,11 +25,14 @@ fn create_primitives() -> Result<path::PathBuf> {
 fn main() {
     println!("cargo:rerun-if-changed=src/build.rs");
     println!("cargo:rerun-if-changed=src/cmdline.rs");
-    match create_primitives() {
+    match write_primitive() {
         Ok(p) => {
             // The build succeeded. We're going to define the CALYX_PRIMITVE_DIR environment variable
             // so that it can be used by the compiler.
-            println!("cargo:rustc-env={PRIM_DIR}={}", p.to_string_lossy());
+            println!(
+                "cargo:rustc-env=CALYX_PRIMITIVES_DIR={}",
+                p.to_string_lossy()
+            );
         }
         Err(e) => {
             println!(
diff --git a/src/futil.rs b/src/futil.rs
new file mode 100644
index 0000000000..7229f9ff9a
--- /dev/null
+++ b/src/futil.rs
@@ -0,0 +1,8 @@
+use calyx::driver;
+use calyx_utils::CalyxResult;
+
+fn main() -> CalyxResult<()> {
+    driver::run_compiler()?;
+    log::warn!("The `futil` binary is deprecated. Please use `calyx` instead.");
+    Ok(())
+}
diff --git a/tests/frontend/exp/degree-2-unsigned.expect b/tests/frontend/exp/degree-2-unsigned.expect
index b6ef1de1ed..b2e781ae3c 100644
--- a/tests/frontend/exp/degree-2-unsigned.expect
+++ b/tests/frontend/exp/degree-2-unsigned.expect
@@ -105,8 +105,8 @@ component fp_pow(base: 32, integer_exp: 32) -> (out: 32) {
     pow = std_reg(32);
     count = std_reg(32);
     mul = std_fp_mult_pipe(32, 16, 16);
-    count_incr = std_add(32);
-    lt_1 = std_lt(32);
+    lt = std_lt(32);
+    incr = std_add(32);
   }
   wires {
     group init {
@@ -124,26 +124,26 @@ component fp_pow(base: 32, integer_exp: 32) -> (out: 32) {
       pow.in = mul.out;
       execute_mul[done] = pow.done;
     }
-    group count_incr_group {
-      count_incr.left = count.out;
-      count_incr.right = 32'd1;
+    group incr_count {
+      incr.left = 32'd1;
+      incr.right = count.out;
+      count.in = incr.out;
       count.write_en = 1'd1;
-      count.in = count_incr.out;
-      count_incr_group[done] = count.done;
+      incr_count[done] = count.done;
     }
-    comb group lt_1_group {
-      lt_1.left = count.out;
-      lt_1.right = integer_exp;
+    comb group cond {
+      lt.left = count.out;
+      lt.right = integer_exp;
     }
     out = pow.out;
   }
   control {
     seq {
       init;
-      while lt_1.out with lt_1_group {
+      while lt.out with cond {
         par {
           execute_mul;
-          count_incr_group;
+          incr_count;
         }
       }
     }
diff --git a/tests/frontend/exp/degree-4-signed.expect b/tests/frontend/exp/degree-4-signed.expect
index c530c34b25..cfe43411cf 100644
--- a/tests/frontend/exp/degree-4-signed.expect
+++ b/tests/frontend/exp/degree-4-signed.expect
@@ -198,8 +198,8 @@ component fp_pow(base: 16, integer_exp: 16) -> (out: 16) {
     pow = std_reg(16);
     count = std_reg(16);
     mul = std_fp_smult_pipe(16, 8, 8);
-    count_incr = std_sadd(16);
-    lt_1 = std_slt(16);
+    lt = std_slt(16);
+    incr = std_sadd(16);
   }
   wires {
     group init {
@@ -217,26 +217,26 @@ component fp_pow(base: 16, integer_exp: 16) -> (out: 16) {
       pow.in = mul.out;
       execute_mul[done] = pow.done;
     }
-    group count_incr_group {
-      count_incr.left = count.out;
-      count_incr.right = 16'd1;
+    group incr_count {
+      incr.left = 16'd1;
+      incr.right = count.out;
+      count.in = incr.out;
       count.write_en = 1'd1;
-      count.in = count_incr.out;
-      count_incr_group[done] = count.done;
+      incr_count[done] = count.done;
     }
-    comb group lt_1_group {
-      lt_1.left = count.out;
-      lt_1.right = integer_exp;
+    comb group cond {
+      lt.left = count.out;
+      lt.right = integer_exp;
     }
     out = pow.out;
   }
   control {
     seq {
       init;
-      while lt_1.out with lt_1_group {
+      while lt.out with cond {
         par {
           execute_mul;
-          count_incr_group;
+          incr_count;
         }
       }
     }
diff --git a/tests/frontend/exp/degree-4-unsigned.expect b/tests/frontend/exp/degree-4-unsigned.expect
index 91fa242447..f977c57bbf 100644
--- a/tests/frontend/exp/degree-4-unsigned.expect
+++ b/tests/frontend/exp/degree-4-unsigned.expect
@@ -169,8 +169,8 @@ component fp_pow(base: 16, integer_exp: 16) -> (out: 16) {
     pow = std_reg(16);
     count = std_reg(16);
     mul = std_fp_mult_pipe(16, 8, 8);
-    count_incr = std_add(16);
-    lt_1 = std_lt(16);
+    lt = std_lt(16);
+    incr = std_add(16);
   }
   wires {
     group init {
@@ -188,26 +188,26 @@ component fp_pow(base: 16, integer_exp: 16) -> (out: 16) {
       pow.in = mul.out;
       execute_mul[done] = pow.done;
     }
-    group count_incr_group {
-      count_incr.left = count.out;
-      count_incr.right = 16'd1;
+    group incr_count {
+      incr.left = 16'd1;
+      incr.right = count.out;
+      count.in = incr.out;
       count.write_en = 1'd1;
-      count.in = count_incr.out;
-      count_incr_group[done] = count.done;
+      incr_count[done] = count.done;
     }
-    comb group lt_1_group {
-      lt_1.left = count.out;
-      lt_1.right = integer_exp;
+    comb group cond {
+      lt.left = count.out;
+      lt.right = integer_exp;
     }
     out = pow.out;
   }
   control {
     seq {
       init;
-      while lt_1.out with lt_1_group {
+      while lt.out with cond {
         par {
           execute_mul;
-          count_incr_group;
+          incr_count;
         }
       }
     }
diff --git a/tests/frontend/relay/softmax.expect b/tests/frontend/relay/softmax.expect
index e1186d3ba5..8730bd907e 100644
--- a/tests/frontend/relay/softmax.expect
+++ b/tests/frontend/relay/softmax.expect
@@ -619,8 +619,8 @@ component fp_pow(base: 32, integer_exp: 32) -> (out: 32) {
     pow = std_reg(32);
     count = std_reg(32);
     mul = std_fp_smult_pipe(32, 16, 16);
-    count_incr = std_sadd(32);
-    lt_1 = std_slt(32);
+    lt = std_slt(32);
+    incr = std_sadd(32);
   }
   wires {
     group init {
@@ -638,26 +638,26 @@ component fp_pow(base: 32, integer_exp: 32) -> (out: 32) {
       pow.in = mul.out;
       execute_mul[done] = pow.done;
     }
-    group count_incr_group {
-      count_incr.left = count.out;
-      count_incr.right = 32'd1;
+    group incr_count {
+      incr.left = 32'd1;
+      incr.right = count.out;
+      count.in = incr.out;
       count.write_en = 1'd1;
-      count.in = count_incr.out;
-      count_incr_group[done] = count.done;
+      incr_count[done] = count.done;
     }
-    comb group lt_1_group {
-      lt_1.left = count.out;
-      lt_1.right = integer_exp;
+    comb group cond {
+      lt.left = count.out;
+      lt.right = integer_exp;
     }
     out = pow.out;
   }
   control {
     seq {
       init;
-      while lt_1.out with lt_1_group {
+      while lt.out with cond {
         par {
           execute_mul;
-          count_incr_group;
+          incr_count;
         }
       }
     }