diff --git a/calyx-py/calyx/builder.py b/calyx-py/calyx/builder.py
index bbde0fded8..7ee0f55edb 100644
--- a/calyx-py/calyx/builder.py
+++ b/calyx-py/calyx/builder.py
@@ -108,6 +108,15 @@ def control(self, builder: Union[ast.Control, ControlBuilder]):
         else:
             self.component.controls = builder
 
+    def get_port_width(self, name: str) -> int:
+        for input in self.component.inputs:
+            if input.id.name == name:
+                return input.width
+        for output in self.component.outputs:
+            if output.id.name == name:
+                return output.width
+        raise Exception(f"couldn't find port {name} on component {self.component.name}")
+
     def get_cell(self, name: str) -> CellBuilder:
         """Retrieve a cell builder by name."""
         out = self.index.get(name)
@@ -218,6 +227,10 @@ def reg(self, name: str, size: int, is_ref=False) -> CellBuilder:
         """Generate a StdReg cell."""
         return self.cell(name, ast.Stdlib.register(size), False, is_ref)
 
+    def slice(self, name: str, in_width: int, out_width, is_ref=False) -> CellBuilder:
+        """Generate a StdReg cell."""
+        return self.cell(name, ast.Stdlib.slice(in_width, out_width), False, is_ref)
+
     def const(self, name: str, width: int, value: int) -> CellBuilder:
         """Generate a StdConstant cell."""
         return self.cell(name, ast.Stdlib.constant(width, value))
@@ -713,6 +726,9 @@ def infer_width(expr):
 
     # Otherwise, it's a `cell.port` lookup.
     assert isinstance(expr, ast.Atom)
+    if isinstance(expr.item, ast.ThisPort):
+        name = expr.item.id.name
+        return group_builder.comp.get_port_width(name)
     cell_name = expr.item.id.name
     port_name = expr.item.name
 
diff --git a/frontends/systolic-lang/gen-systolic.py b/frontends/systolic-lang/gen-systolic.py
index e2dc7323b2..19abcba3d9 100755
--- a/frontends/systolic-lang/gen-systolic.py
+++ b/frontends/systolic-lang/gen-systolic.py
@@ -10,6 +10,42 @@
 # Name of the ouput array
 OUT_MEM = "out_mem"
 PE_NAME = "mac_pe"
+DEPTH = "depth"
+
+
+class CalyxAdd:
+    """
+    A class that represents addition in Calyx between a port and a constant
+    """
+
+    def __init__(self, port, const):
+        self.port = port
+        self.const = const
+
+    def __eq__(self, other):
+        if type(other) != CalyxAdd:
+            return False
+        return (
+            cb.ExprBuilder.unwrap(self.port) == cb.ExprBuilder.unwrap(other.port)
+            and self.const == other.const
+        )
+
+    def __hash__(self):
+        return hash(self.const)
+
+    def __repr__(self):
+        return (
+            str(cb.ExprBuilder.unwrap(self.port).item.id.name)
+            + "_plus_"
+            + str(self.const)
+        )
+
+    def __str__(self):
+        return (
+            str(cb.ExprBuilder.unwrap(self.port).item.id.name)
+            + "_plus_"
+            + str(self.const)
+        )
 
 
 def pe(prog: cb.Builder):
@@ -91,6 +127,25 @@ def instantiate_indexor(comp: cb.ComponentBuilder, prefix, width) -> cb.CellBuil
     return reg
 
 
+def add_read_mem_argument(comp: cb.ComponentBuilder, name, addr_width):
+    """
+    Add arguments to component `comp` if we want to read from a mem named `name` wth
+    width of `addr_width`
+    """
+    comp.input(f"{name}_read_data", BITWIDTH)
+    comp.output(f"{name}_addr0", addr_width)
+
+
+def add_write_mem_argument(comp: cb.ComponentBuilder, name, addr_width):
+    """
+    Add arguments to component `comp` if we want to write to a mem named `name` wth
+    width of `addr_width`
+    """
+    comp.output(f"{name}_addr0", addr_width)
+    comp.output(f"{name}_write_data", BITWIDTH)
+    comp.output(f"{name}_write_en", 1)
+
+
 def instantiate_memory(comp: cb.ComponentBuilder, top_or_left, idx, size):
     """
     Instantiates:
@@ -110,21 +165,18 @@ def instantiate_memory(comp: cb.ComponentBuilder, top_or_left, idx, size):
 
     idx_width = bits_needed(size)
     # Instantiate the memory
-    mem = comp.mem_d1(
-        name,
-        BITWIDTH,
-        size,
-        idx_width,
-        is_external=True,
-    )
+    add_read_mem_argument(comp, name, idx_width)
+    this = comp.this()
+    addr0_port = cb.ExprBuilder.unwrap(this.port(name + "_addr0"))
+    read_data_port = this.port(name + "_read_data")
     # Instantiate the indexing register
     idx = instantiate_indexor(comp, name, idx_width)
     # Register to save the value from the memory. Defined by [[instantiate_pe]].
     target = comp.get_cell(target_reg)
     group_name = NAME_SCHEME["memory move"].format(prefix=name)
-    with comp.static_group(group_name, 1):
-        mem.addr0 = idx.out
-        target.in_ = mem.read_data
+    with comp.static_group(group_name, 1) as g:
+        g.asgn(addr0_port, idx.out)
+        target.in_ = read_data_port
         target.write_en = 1
 
 
@@ -171,14 +223,20 @@ def instantiate_output_move(comp: cb.ComponentBuilder, row, col, cols):
     """
     group_name = NAME_SCHEME["out mem move"].format(pe=f"pe_{row}_{col}")
     pe = comp.get_cell(f"pe_{row}_{col}")
-    out = comp.get_cell(OUT_MEM + f"_{row}")
-    with comp.static_group(group_name, 1):
-        out.addr0 = col
-        out.write_data = pe.out
-        out.write_en = 1
-
-
-def gen_schedules(top_length, top_depth, left_length, left_depth):
+    this = comp.this()
+    mem_name = OUT_MEM + f"_{row}"
+    addr0_port = cb.ExprBuilder.unwrap(this.port(mem_name + "_addr0"))
+    write_data_port = cb.ExprBuilder.unwrap(this.port(mem_name + "_write_data"))
+    write_en_port = cb.ExprBuilder.unwrap(this.port(mem_name + "_write_en"))
+    with comp.static_group(group_name, 1) as g:
+        g.asgn(addr0_port, col)
+        g.asgn(write_data_port, pe.out)
+        g.asgn(write_en_port, 1)
+
+
+def gen_schedules(
+    top_length, top_depth, left_length, left_depth, comp: cb.ComponentBuilder
+):
     """
     Generates 5 arrays that are the same size as the output (systolic) array
     Each entry in the array has tuple [start, end) that indicates the cycles that
@@ -193,6 +251,9 @@ def gen_schedules(top_length, top_depth, left_length, left_depth):
     `pe_write_sched` contains when to "write" the PE value into memory (i.e., when
     the PE is "finished")
     """
+    depth_port = comp.this().depth
+    min_depth_4_port = comp.get_cell("min_depth_4").port("out")
+    schedules = {}
     update_sched = np.zeros((left_length, top_length), dtype=object)
     pe_fill_sched = np.zeros((left_length, top_length), dtype=object)
     pe_accum_sched = np.zeros((left_length, top_length), dtype=object)
@@ -201,12 +262,20 @@ def gen_schedules(top_length, top_depth, left_length, left_depth):
     for row in range(0, left_length):
         for col in range(0, top_length):
             pos = row + col
-            update_sched[row][col] = (pos, pos + left_depth)
-            pe_fill_sched[row][col] = (pos + 1, pos + min(4, left_depth) + 1)
-            pe_accum_sched[row][col] = (pos + 5, pos + left_depth + 5)
-            pe_move_sched[row][col] = (pos + 1, pos + left_depth + 1)
-            pe_write_sched[row][col] = (pos + left_depth + 5, pos + left_depth + 6)
-    return (update_sched, pe_fill_sched, pe_accum_sched, pe_move_sched, pe_write_sched)
+            update_sched[row][col] = (pos, CalyxAdd(depth_port, pos))
+            pe_fill_sched[row][col] = (pos + 1, CalyxAdd(min_depth_4_port, pos + 1))
+            pe_accum_sched[row][col] = (pos + 5, CalyxAdd(depth_port, pos + 5))
+            pe_move_sched[row][col] = (pos + 1, CalyxAdd(depth_port, pos + 1))
+            pe_write_sched[row][col] = (
+                CalyxAdd(depth_port, pos + 5),
+                CalyxAdd(depth_port, pos + 6),
+            )
+    schedules["update_sched"] = update_sched
+    schedules["fill_sched"] = pe_fill_sched
+    schedules["accum_sched"] = pe_accum_sched
+    schedules["move_sched"] = pe_move_sched
+    schedules["write_sched"] = pe_write_sched
+    return schedules
 
 
 def accum_nec_ranges(nec_ranges, schedule):
@@ -226,12 +295,48 @@ def accum_nec_ranges(nec_ranges, schedule):
     return nec_ranges
 
 
-def instantiate_idx_groups(comp: cb.ComponentBuilder, width, limit):
+def build_calyx_add(comp, obj):
     """
-    Builds groups that instantiate idx to 0 and increment idx
+    Attempts to build an adder for obj, with name str(obj) and group name
+    str(obj) + "_group" that adds obj.port and obj.const
+    Returns true if we actually build it
+    Returns false otherwise
+    """
+    if type(obj) == CalyxAdd:
+        add_str = str(obj)
+        if comp.try_get_cell(add_str) is None:
+            add = comp.add(add_str, BITWIDTH)
+            with comp.static_group(add_str + "_group", 1):
+                add.left = obj.port
+                add.right = obj.const
+            return True
+    return False
+
+
+def instantiate_calyx_adds(comp, nec_ranges):
+    """
+    Instantiates the CalyxAdds objects to adders and actual groups that add things
+    """
+    depth_adders = []
+    for lo, hi in nec_ranges:
+        if build_calyx_add(comp, lo):
+            depth_adders.append(str(lo) + "_group")
+        if build_calyx_add(comp, hi):
+            depth_adders.append(str(hi) + "_group")
+    return depth_adders
+
+
+def instantiate_idx_cond_groups(comp: cb.ComponentBuilder):
     """
-    idx = comp.reg("idx", width)
-    add = comp.add("idx_add", width)
+    Builds groups that instantiate idx to 0 and increment idx
+    Also builds groups that set cond_reg to 1 (runs before the while loop)
+    and that sets cond_reg to idx + 1 < iter_limit
+    """
+    idx = comp.reg("idx", BITWIDTH)
+    add = comp.add("idx_add", BITWIDTH)
+    iter_limit = comp.get_cell("iter_limit")
+    lt_iter_limit = comp.lt("lt_iter_limit", BITWIDTH)
+    cond_reg = comp.reg("cond_reg", 1)
     with comp.static_group("init_idx", 1):
         idx.in_ = 0
         idx.write_en = 1
@@ -240,9 +345,40 @@ def instantiate_idx_groups(comp: cb.ComponentBuilder, width, limit):
         add.right = 1
         idx.in_ = add.out
         idx.write_en = 1
-
-
-def instantiate_idx_between(comp: cb.ComponentBuilder, lo, hi, width) -> list:
+    with comp.static_group("lt_iter_limit_group", 1):
+        lt_iter_limit.left = add.out
+        lt_iter_limit.right = iter_limit.out
+        cond_reg.in_ = lt_iter_limit.out
+        cond_reg.write_en = 1
+    with comp.static_group("init_cond_reg", 1):
+        cond_reg.in_ = 1
+        cond_reg.write_en = 1
+
+
+def init_dyn_vals(comp: cb.ComponentBuilder, depth_port, rem_iter_limit):
+    """
+    Builds group that instantiates the dynamic/runtime values for the systolic
+    array: its depth and iteration limit/count (since its iteration limit depends on
+    its depth).
+    """
+    min_depth_4 = comp.reg("min_depth_4", BITWIDTH)
+    lt_depth_4 = comp.lt("lt_depth_4", BITWIDTH)
+    iter_limit = comp.reg("iter_limit", BITWIDTH)
+    iter_limit_add = comp.add("iter_limit_add", BITWIDTH)
+    with comp.static_group("init_min_depth", 1):
+        lt_depth_4.left = depth_port
+        lt_depth_4.right = 4
+        min_depth_4.in_ = lt_depth_4.out @ depth_port
+        min_depth_4.in_ = ~lt_depth_4.out @ 4
+        min_depth_4.write_en = 1
+    with comp.static_group("init_iter_limit", 1):
+        iter_limit_add.left = rem_iter_limit
+        iter_limit_add.right = depth_port
+        iter_limit.in_ = iter_limit_add.out
+        iter_limit.write_en = 1
+
+
+def instantiate_idx_between(comp: cb.ComponentBuilder, lo, hi) -> list:
     """
     Instantiates a static group and register called "idx_between_{lo}_{hi}_reg/group"
     that should output whether idx is between [lo, hi). That is, whether lo <= idx < hi.
@@ -250,23 +386,31 @@ def instantiate_idx_between(comp: cb.ComponentBuilder, lo, hi, width) -> list:
     Note: If you're trying to understand why this works, we are checking `idx_add` which
     is one higher than idx. This offsets the cycle it takes to update the register.
     """
+    if type(hi) == CalyxAdd:
+        hi_value = comp.get_cell(str(hi)).port("out")
+    else:
+        hi_value = hi
+    if type(lo) == CalyxAdd:
+        lo_value = comp.get_cell(str(lo)).port("out")
+    else:
+        lo_value = lo
     idx_add = comp.get_cell("idx_add")
     reg_str = f"idx_between_{lo}_{hi}_reg"
     comb_str = f"idx_between_{lo}_{hi}_comb"
     group_str = f"idx_between_{lo}_{hi}_group"
-    index_lt = f"index_lt_{hi}"
-    index_ge = f"index_ge_{lo}"
+    index_lt = f"index_lt_{str(hi)}"
+    index_ge = f"index_ge_{str(lo)}"
     reg = comp.reg(reg_str, 1)
     lt = (
         comp.get_cell(index_lt)
         if comp.try_get_cell(index_lt) is not None
-        else comp.lt(index_lt, width)
+        else comp.lt(index_lt, BITWIDTH)
     )
     # if lo == 0, then only need to check if reg < hi
-    if lo == 0:
+    if type(lo) == int and lo == 0:
         with comp.static_group(group_str, 1):
             lt.left = idx_add.out
-            lt.right = hi
+            lt.right = hi_value
             reg.in_ = lt.out
             reg.write_en = 1
     # need to check if reg >= lo and reg < hi
@@ -274,14 +418,14 @@ def instantiate_idx_between(comp: cb.ComponentBuilder, lo, hi, width) -> list:
         ge = (
             comp.get_cell(index_ge)
             if comp.try_get_cell(index_ge) is not None
-            else comp.ge(index_ge, width)
+            else comp.ge(index_ge, BITWIDTH)
         )
         and_ = comp.and_(comb_str, 1)
         with comp.static_group(group_str, 1):
             ge.left = idx_add.out
-            ge.right = lo
+            ge.right = lo_value
             lt.left = idx_add.out
-            lt.right = hi
+            lt.right = hi_value
             and_.left = ge.out
             and_.right = lt.out
             reg.in_ = and_.out
@@ -376,11 +520,8 @@ def generate_control(
     top_depth,
     left_length,
     left_depth,
-    update_sched,
-    fill_sched,
-    accum_sched,
-    move_sched,
-    write_sched,
+    schedules,
+    depth_adders,
     nec_ranges,
 ):
     """
@@ -407,7 +548,12 @@ def generate_control(
             py_ast.Enable(NAME_SCHEME["index init"].format(prefix=f"l{idx}"))
             for idx in range(left_length)
         ]
-        + [py_ast.Enable("init_idx")]
+        + [
+            py_ast.Enable("init_idx"),
+            py_ast.Enable("init_min_depth"),
+            py_ast.Enable("init_iter_limit"),
+            py_ast.Enable("init_cond_reg"),
+        ]
         + [py_ast.Enable(f"init_idx_between_{lo}_{hi}") for (lo, hi) in (nec_ranges)]
     )
     control.append(py_ast.StaticParComp(init_indices))
@@ -425,38 +571,38 @@ def counter():
     # end source pos init
 
     control_stmts = []
-    incr_stmts = [py_ast.Enable("incr_idx")]
+    incr_stmts = [py_ast.Enable("incr_idx"), py_ast.Enable("lt_iter_limit_group")]
     for r in range(left_length):
         for c in range(top_length):
             # build 4 if stmts for the 4 schedules that we need to account for
             input_mem_updates = execute_if_between(
                 comp,
-                update_sched[r][c][0],
-                update_sched[r][c][1],
+                schedules["update_sched"][r][c][0],
+                schedules["update_sched"][r][c][1],
                 get_memory_updates(r, c),
             )
             pe_fills = execute_if_between(
                 comp,
-                fill_sched[r][c][0],
-                fill_sched[r][c][1],
+                schedules["fill_sched"][r][c][0],
+                schedules["fill_sched"][r][c][1],
                 [get_pe_invoke(r, c, top_length, left_length, 0)],
             )
             pe_moves = execute_if_between(
                 comp,
-                move_sched[r][c][0],
-                move_sched[r][c][1],
+                schedules["move_sched"][r][c][0],
+                schedules["move_sched"][r][c][1],
                 get_pe_moves(r, c, top_length, left_length),
             )
             pe_accums = execute_if_between(
                 comp,
-                accum_sched[r][c][0],
-                accum_sched[r][c][1],
+                schedules["accum_sched"][r][c][0],
+                schedules["accum_sched"][r][c][1],
                 [get_pe_invoke(r, c, top_length, left_length, 1)],
             )
             pe_writes = execute_if_between(
                 comp,
-                write_sched[r][c][0],
-                write_sched[r][c][1],
+                schedules["write_sched"][r][c][0],
+                schedules["write_sched"][r][c][1],
                 [py_ast.Enable(NAME_SCHEME["out mem move"].format(pe=f"pe_{r}_{c}"))],
             )
             pe_control = input_mem_updates + pe_fills + pe_moves + pe_accums + pe_writes
@@ -465,26 +611,28 @@ def counter():
             tag = counter()
             source_map[
                 tag
-            ] = f"pe_{r}_{c} filling: [{fill_sched[r][c][0]},{fill_sched[r][c][1]}) \
-accumulating: [{accum_sched[r][c][0]} {accum_sched[r][c][1]})"
+            ] = f"pe_{r}_{c} filling: [{schedules['fill_sched'][r][c][0]},\
+{schedules['fill_sched'][r][c][1]}) accumulating: [{schedules['accum_sched'][r][c][0]} \
+{schedules['accum_sched'][r][c][1]})"
     for start, end in nec_ranges:
         # build the control stmts that assign correct values to
         # idx_between_{start}_{end}_reg, which is what the if stmts above^ rely on
         incr_stmts.append(py_ast.Enable(f"idx_between_{start}_{end}_group"))
+    for depth_adder_group in depth_adders:
+        incr_stmts.append(py_ast.Enable(depth_adder_group))
 
-    repeat_body = py_ast.StaticParComp(
+    while_body = py_ast.StaticParComp(
         [py_ast.StaticParComp(control_stmts), py_ast.StaticParComp(incr_stmts)]
     )
 
-    # build the static repeat
+    # build the while loop with condition cond_reg.
     # num repeats = (top_length - 1) + (left_length - 1) + (top_depth - 1) + 5 + 1
-    static_repeat = cb.static_repeat(
-        top_length + left_length + top_depth + 4, repeat_body
-    )
+    cond_reg_port = comp.get_cell("cond_reg").port("out")
+    while_loop = cb.while_(cond_reg_port, None, while_body)
 
-    control.append(static_repeat)
+    control.append(while_loop)
 
-    return py_ast.StaticSeqComp(stmts=control), source_map
+    return py_ast.SeqComp(stmts=control), source_map
 
 
 def create_systolic_array(
@@ -502,79 +650,119 @@ def create_systolic_array(
         f"{top_length}x{top_depth} and {left_depth}x{left_length}"
     )
 
-    (update_sched, fill_sched, accum_sched, move_sched, write_sched) = gen_schedules(
-        top_length, top_depth, left_length, left_depth
+    computational_unit = prog.component("systolic_array_comp")
+    depth_port = computational_unit.input("depth", BITWIDTH)
+    init_dyn_vals(computational_unit, depth_port, top_length + left_length + 4)
+
+    schedules = gen_schedules(
+        top_length, top_depth, left_length, left_depth, computational_unit
     )
     nec_ranges = set()
-    accum_nec_ranges(nec_ranges, update_sched)
-    accum_nec_ranges(nec_ranges, fill_sched)
-    accum_nec_ranges(nec_ranges, accum_sched)
-    accum_nec_ranges(nec_ranges, move_sched)
-    accum_nec_ranges(nec_ranges, write_sched)
-
-    main = prog.component("main")
+    for sched in schedules.values():
+        accum_nec_ranges(nec_ranges, sched)
+    depth_adders = instantiate_calyx_adds(computational_unit, nec_ranges)
 
     for row in range(left_length):
         for col in range(top_length):
             # Instantiate the PEs and surronding registers
-            instantiate_pe(main, row, col)
+            instantiate_pe(computational_unit, row, col)
 
     # Instantiate all the memories
     for r in range(top_length):
-        instantiate_memory(main, "top", r, top_depth)
+        instantiate_memory(computational_unit, "top", r, top_depth)
 
     for col in range(left_length):
-        instantiate_memory(main, "left", col, left_depth)
+        instantiate_memory(computational_unit, "left", col, left_depth)
 
+    idx_width = BITWIDTH
     # Instantiate output memory
-    out_idx_size = bits_needed(top_length)
     for i in range(left_length):
-        main.mem_d1(
-            OUT_MEM + f"_{i}",
-            BITWIDTH,
-            top_length,
-            out_idx_size,
-            is_external=True,
-        )
+        add_write_mem_argument(computational_unit, OUT_MEM + f"_{i}", idx_width)
 
     # Instantiate all the PEs
     for row in range(left_length):
         for col in range(top_length):
             # Instantiate the mover fabric
             instantiate_data_move(
-                main, row, col, col == top_length - 1, row == left_length - 1
+                computational_unit,
+                row,
+                col,
+                col == top_length - 1,
+                row == left_length - 1,
             )
 
             # Instantiate output movement structure
-            instantiate_output_move(main, row, col, top_length)
-
-    iter_limit = top_length + left_length + top_depth + 4
-    iter_idx_size = bits_needed(iter_limit)
-    # instantiate groups that initialize idx to 0 and increment it
-    instantiate_idx_groups(main, iter_idx_size, iter_limit)
+            instantiate_output_move(computational_unit, row, col, top_length)
 
+    # instantiate groups that handle cond_reg and idx variables
+    instantiate_idx_cond_groups(computational_unit)
     for start, end in nec_ranges:
         # create the groups that create for idx_in_between registers
-        instantiate_idx_between(main, start, end, iter_idx_size)
-        instantiate_init_group(main, start, end)
+        instantiate_idx_between(computational_unit, start, end)
+        instantiate_init_group(computational_unit, start, end)
 
     # Generate the control and set the source map
     control, source_map = generate_control(
-        main,
+        computational_unit,
         top_length,
         top_depth,
         left_length,
         left_depth,
-        update_sched,
-        fill_sched,
-        accum_sched,
-        move_sched,
-        write_sched,
+        schedules,
+        depth_adders,
         nec_ranges,
     )
-    main.control = control
+    computational_unit.control = control
     prog.program.meta = source_map
 
+    # build the main component
+    # instantaites the systolic array/computational_unit and the mems,
+    # and then invokes it
+    main = prog.component("main")
+    systolic_array = main.cell("systolic_array", computational_unit)
+    invoke_args = {}
+    invoke_args["in_depth"] = py_ast.ConstantPort(BITWIDTH, left_depth)
+    for r in range(top_length):
+        name = f"t{r}"
+        idx_width = bits_needed(top_depth)
+        mem = main.mem_d1(
+            name,
+            BITWIDTH,
+            top_depth,
+            idx_width,
+            is_external=True,
+        )
+        invoke_args[f"in_{name}_read_data"] = mem.read_data
+        invoke_args[f"out_{name}_addr0"] = mem.addr0
+    for col in range(left_length):
+        name = f"l{col}"
+        idx_width = bits_needed(left_depth)
+        mem = main.mem_d1(
+            name,
+            BITWIDTH,
+            left_depth,
+            idx_width,
+            is_external=True,
+        )
+        invoke_args[f"in_{name}_read_data"] = mem.read_data
+        invoke_args[f"out_{name}_addr0"] = mem.addr0
+
+    for i in range(left_length):
+        name = OUT_MEM + f"_{i}"
+        mem = main.mem_d1(
+            name,
+            BITWIDTH,
+            top_length,
+            BITWIDTH,
+            is_external=True,
+        )
+        invoke_args[f"out_{name}_addr0"] = mem.addr0
+        invoke_args[f"out_{name}_write_data"] = mem.write_data
+        invoke_args[f"out_{name}_write_en"] = mem.write_en
+
+    invoke = cb.invoke(systolic_array, **invoke_args)
+    main.control = invoke
+
 
 if __name__ == "__main__":
     import argparse
diff --git a/tests/correctness/systolic/output/array-2-3-4.expect b/tests/correctness/systolic/output/array-2-3-4.expect
index cfe7d6ab98..aa115c1883 100644
--- a/tests/correctness/systolic/output/array-2-3-4.expect
+++ b/tests/correctness/systolic/output/array-2-3-4.expect
@@ -1,5 +1,5 @@
 {
-  "cycles": 14,
+  "cycles": 16,
   "memories": {
     "l0": [
       62,
diff --git a/tests/correctness/systolic/output/array-8.expect b/tests/correctness/systolic/output/array-8.expect
index 4cc6701e66..944548e5a1 100644
--- a/tests/correctness/systolic/output/array-8.expect
+++ b/tests/correctness/systolic/output/array-8.expect
@@ -1,5 +1,5 @@
 {
-  "cycles": 29,
+  "cycles": 31,
   "memories": {
     "l0": [
       26,
diff --git a/tests/correctness/systolic/pe/array-1.expect b/tests/correctness/systolic/pe/array-1.expect
index ce98de82e8..df8dfe9783 100644
--- a/tests/correctness/systolic/pe/array-1.expect
+++ b/tests/correctness/systolic/pe/array-1.expect
@@ -1,5 +1,5 @@
 {
-  "cycles": 14,
+  "cycles": 16,
   "pe_00": [
     0,
     120,
diff --git a/tests/correctness/systolic/pe/array-1.systolic.jq b/tests/correctness/systolic/pe/array-1.systolic.jq
index 8e75b41141..a61fe68a98 100644
--- a/tests/correctness/systolic/pe/array-1.systolic.jq
+++ b/tests/correctness/systolic/pe/array-1.systolic.jq
@@ -1,4 +1,4 @@
-.TOP.TOP.main | ({
+.TOP.TOP.main.systolic_array | ({
   "cycles":.clk | add,
   "pe_00": .pe_0_0.acc.out | unique,
 })
diff --git a/tests/correctness/systolic/pe/array-2.expect b/tests/correctness/systolic/pe/array-2.expect
index c947279742..5bcf45bd83 100644
--- a/tests/correctness/systolic/pe/array-2.expect
+++ b/tests/correctness/systolic/pe/array-2.expect
@@ -1,5 +1,5 @@
 {
-  "cycles": 16,
+  "cycles": 18,
   "pe_00": [
     0,
     120,
diff --git a/tests/correctness/systolic/pe/array-2.systolic.jq b/tests/correctness/systolic/pe/array-2.systolic.jq
index 267a10407e..0cedc930a5 100644
--- a/tests/correctness/systolic/pe/array-2.systolic.jq
+++ b/tests/correctness/systolic/pe/array-2.systolic.jq
@@ -1,4 +1,4 @@
-.TOP.TOP.main | ({
+.TOP.TOP.main.systolic_array | ({
   "cycles":.clk | add,
   "pe_00": .pe_0_0.acc.out | unique,
   "pe_01": .pe_0_1.acc.out | unique,
diff --git a/tests/correctness/systolic/pe/array-3.expect b/tests/correctness/systolic/pe/array-3.expect
index 25ea25a921..f8afb09ecd 100644
--- a/tests/correctness/systolic/pe/array-3.expect
+++ b/tests/correctness/systolic/pe/array-3.expect
@@ -1,5 +1,5 @@
 {
-  "cycles": 18,
+  "cycles": 20,
   "pe_00": [
     0,
     120,
diff --git a/tests/correctness/systolic/pe/array-3.systolic.jq b/tests/correctness/systolic/pe/array-3.systolic.jq
index e2a09856e4..d79a90dc55 100644
--- a/tests/correctness/systolic/pe/array-3.systolic.jq
+++ b/tests/correctness/systolic/pe/array-3.systolic.jq
@@ -1,4 +1,4 @@
-.TOP.TOP.main | ({
+.TOP.TOP.main.systolic_array | ({
   "cycles":.clk | add,
 
   "pe_00": .pe_0_0.acc.out | unique,
diff --git a/tests/frontend/systolic/array-1.expect b/tests/frontend/systolic/array-1.expect
index d1ed422c83..46f4792a36 100644
--- a/tests/frontend/systolic/array-1.expect
+++ b/tests/frontend/systolic/array-1.expect
@@ -27,36 +27,80 @@ static<1> component mac_pe(top: 32, left: 32, mul_ready: 1) -> (out: 32) {
     }
   }
 }
-component main() -> () {
+component systolic_array_comp(depth: 32, t0_read_data: 32, l0_read_data: 32) -> (t0_addr0: 2, l0_addr0: 2, out_mem_0_addr0: 32, out_mem_0_write_data: 32, out_mem_0_write_en: 1) {
   cells {
+    min_depth_4 = std_reg(32);
+    lt_depth_4 = std_lt(32);
+    iter_limit = std_reg(32);
+    iter_limit_add = std_add(32);
+    depth_plus_5 = std_add(32);
+    depth_plus_0 = std_add(32);
+    depth_plus_1 = std_add(32);
+    min_depth_4_plus_1 = std_add(32);
+    depth_plus_6 = std_add(32);
     pe_0_0 = mac_pe();
     top_0_0 = std_reg(32);
     left_0_0 = std_reg(32);
-    @external t0 = std_mem_d1(32, 3, 2);
     t0_idx = std_reg(2);
     t0_add = std_add(2);
-    @external l0 = std_mem_d1(32, 3, 2);
     l0_idx = std_reg(2);
     l0_add = std_add(2);
-    @external out_mem_0 = std_mem_d1(32, 1, 1);
-    idx = std_reg(4);
-    idx_add = std_add(4);
-    idx_between_8_9_reg = std_reg(1);
-    index_lt_9 = std_lt(4);
-    index_ge_8 = std_ge(4);
-    idx_between_8_9_comb = std_and(1);
-    idx_between_0_3_reg = std_reg(1);
-    index_lt_3 = std_lt(4);
-    idx_between_1_4_reg = std_reg(1);
-    index_lt_4 = std_lt(4);
-    index_ge_1 = std_ge(4);
-    idx_between_1_4_comb = std_and(1);
-    idx_between_5_8_reg = std_reg(1);
-    index_lt_8 = std_lt(4);
-    index_ge_5 = std_ge(4);
-    idx_between_5_8_comb = std_and(1);
+    idx = std_reg(32);
+    idx_add = std_add(32);
+    lt_iter_limit = std_lt(32);
+    cond_reg = std_reg(1);
+    idx_between_5_depth_plus_5_reg = std_reg(1);
+    index_lt_depth_plus_5 = std_lt(32);
+    index_ge_5 = std_ge(32);
+    idx_between_5_depth_plus_5_comb = std_and(1);
+    idx_between_0_depth_plus_0_reg = std_reg(1);
+    index_lt_depth_plus_0 = std_lt(32);
+    idx_between_1_depth_plus_1_reg = std_reg(1);
+    index_lt_depth_plus_1 = std_lt(32);
+    index_ge_1 = std_ge(32);
+    idx_between_1_depth_plus_1_comb = std_and(1);
+    idx_between_1_min_depth_4_plus_1_reg = std_reg(1);
+    index_lt_min_depth_4_plus_1 = std_lt(32);
+    idx_between_1_min_depth_4_plus_1_comb = std_and(1);
+    idx_between_depth_plus_5_depth_plus_6_reg = std_reg(1);
+    index_lt_depth_plus_6 = std_lt(32);
+    index_ge_depth_plus_5 = std_ge(32);
+    idx_between_depth_plus_5_depth_plus_6_comb = std_and(1);
   }
   wires {
+    static<1> group init_min_depth {
+      lt_depth_4.left = depth;
+      lt_depth_4.right = 32'd4;
+      min_depth_4.in = lt_depth_4.out ? depth;
+      min_depth_4.in = !lt_depth_4.out ? 32'd4;
+      min_depth_4.write_en = 1'd1;
+    }
+    static<1> group init_iter_limit {
+      iter_limit_add.left = 32'd6;
+      iter_limit_add.right = depth;
+      iter_limit.in = iter_limit_add.out;
+      iter_limit.write_en = 1'd1;
+    }
+    static<1> group depth_plus_5_group {
+      depth_plus_5.left = depth;
+      depth_plus_5.right = 32'd5;
+    }
+    static<1> group depth_plus_0_group {
+      depth_plus_0.left = depth;
+      depth_plus_0.right = 32'd0;
+    }
+    static<1> group depth_plus_1_group {
+      depth_plus_1.left = depth;
+      depth_plus_1.right = 32'd1;
+    }
+    static<1> group min_depth_4_plus_1_group {
+      min_depth_4_plus_1.left = min_depth_4.out;
+      min_depth_4_plus_1.right = 32'd1;
+    }
+    static<1> group depth_plus_6_group {
+      depth_plus_6.left = depth;
+      depth_plus_6.right = 32'd6;
+    }
     static<1> group t0_idx_init {
       t0_idx.in = 2'd0;
       t0_idx.write_en = 1'd1;
@@ -68,8 +112,8 @@ component main() -> () {
       t0_idx.write_en = 1'd1;
     }
     static<1> group t0_move {
-      t0.addr0 = t0_idx.out;
-      top_0_0.in = t0.read_data;
+      t0_addr0 = t0_idx.out;
+      top_0_0.in = t0_read_data;
       top_0_0.write_en = 1'd1;
     }
     static<1> group l0_idx_init {
@@ -83,94 +127,122 @@ component main() -> () {
       l0_idx.write_en = 1'd1;
     }
     static<1> group l0_move {
-      l0.addr0 = l0_idx.out;
-      left_0_0.in = l0.read_data;
+      l0_addr0 = l0_idx.out;
+      left_0_0.in = l0_read_data;
       left_0_0.write_en = 1'd1;
     }
     static<1> group pe_0_0_out_write {
-      out_mem_0.addr0 = 1'd0;
-      out_mem_0.write_data = pe_0_0.out;
-      out_mem_0.write_en = 1'd1;
+      out_mem_0_addr0 = 32'd0;
+      out_mem_0_write_data = pe_0_0.out;
+      out_mem_0_write_en = 1'd1;
     }
     static<1> group init_idx {
-      idx.in = 4'd0;
+      idx.in = 32'd0;
       idx.write_en = 1'd1;
     }
     static<1> group incr_idx {
       idx_add.left = idx.out;
-      idx_add.right = 4'd1;
+      idx_add.right = 32'd1;
       idx.in = idx_add.out;
       idx.write_en = 1'd1;
     }
-    static<1> group idx_between_8_9_group {
-      index_ge_8.left = idx_add.out;
-      index_ge_8.right = 4'd8;
-      index_lt_9.left = idx_add.out;
-      index_lt_9.right = 4'd9;
-      idx_between_8_9_comb.left = index_ge_8.out;
-      idx_between_8_9_comb.right = index_lt_9.out;
-      idx_between_8_9_reg.in = idx_between_8_9_comb.out;
-      idx_between_8_9_reg.write_en = 1'd1;
-    }
-    static<1> group init_idx_between_8_9 {
-      idx_between_8_9_reg.in = 1'd0;
-      idx_between_8_9_reg.write_en = 1'd1;
-    }
-    static<1> group idx_between_0_3_group {
-      index_lt_3.left = idx_add.out;
-      index_lt_3.right = 4'd3;
-      idx_between_0_3_reg.in = index_lt_3.out;
-      idx_between_0_3_reg.write_en = 1'd1;
-    }
-    static<1> group init_idx_between_0_3 {
-      idx_between_0_3_reg.in = 1'd1;
-      idx_between_0_3_reg.write_en = 1'd1;
-    }
-    static<1> group idx_between_1_4_group {
-      index_ge_1.left = idx_add.out;
-      index_ge_1.right = 4'd1;
-      index_lt_4.left = idx_add.out;
-      index_lt_4.right = 4'd4;
-      idx_between_1_4_comb.left = index_ge_1.out;
-      idx_between_1_4_comb.right = index_lt_4.out;
-      idx_between_1_4_reg.in = idx_between_1_4_comb.out;
-      idx_between_1_4_reg.write_en = 1'd1;
-    }
-    static<1> group init_idx_between_1_4 {
-      idx_between_1_4_reg.in = 1'd0;
-      idx_between_1_4_reg.write_en = 1'd1;
-    }
-    static<1> group idx_between_5_8_group {
+    static<1> group lt_iter_limit_group {
+      lt_iter_limit.left = idx_add.out;
+      lt_iter_limit.right = iter_limit.out;
+      cond_reg.in = lt_iter_limit.out;
+      cond_reg.write_en = 1'd1;
+    }
+    static<1> group init_cond_reg {
+      cond_reg.in = 1'd1;
+      cond_reg.write_en = 1'd1;
+    }
+    static<1> group idx_between_5_depth_plus_5_group {
       index_ge_5.left = idx_add.out;
-      index_ge_5.right = 4'd5;
-      index_lt_8.left = idx_add.out;
-      index_lt_8.right = 4'd8;
-      idx_between_5_8_comb.left = index_ge_5.out;
-      idx_between_5_8_comb.right = index_lt_8.out;
-      idx_between_5_8_reg.in = idx_between_5_8_comb.out;
-      idx_between_5_8_reg.write_en = 1'd1;
-    }
-    static<1> group init_idx_between_5_8 {
-      idx_between_5_8_reg.in = 1'd0;
-      idx_between_5_8_reg.write_en = 1'd1;
+      index_ge_5.right = 32'd5;
+      index_lt_depth_plus_5.left = idx_add.out;
+      index_lt_depth_plus_5.right = depth_plus_5.out;
+      idx_between_5_depth_plus_5_comb.left = index_ge_5.out;
+      idx_between_5_depth_plus_5_comb.right = index_lt_depth_plus_5.out;
+      idx_between_5_depth_plus_5_reg.in = idx_between_5_depth_plus_5_comb.out;
+      idx_between_5_depth_plus_5_reg.write_en = 1'd1;
+    }
+    static<1> group init_idx_between_5_depth_plus_5 {
+      idx_between_5_depth_plus_5_reg.in = 1'd0;
+      idx_between_5_depth_plus_5_reg.write_en = 1'd1;
+    }
+    static<1> group idx_between_0_depth_plus_0_group {
+      index_lt_depth_plus_0.left = idx_add.out;
+      index_lt_depth_plus_0.right = depth_plus_0.out;
+      idx_between_0_depth_plus_0_reg.in = index_lt_depth_plus_0.out;
+      idx_between_0_depth_plus_0_reg.write_en = 1'd1;
+    }
+    static<1> group init_idx_between_0_depth_plus_0 {
+      idx_between_0_depth_plus_0_reg.in = 1'd1;
+      idx_between_0_depth_plus_0_reg.write_en = 1'd1;
+    }
+    static<1> group idx_between_1_depth_plus_1_group {
+      index_ge_1.left = idx_add.out;
+      index_ge_1.right = 32'd1;
+      index_lt_depth_plus_1.left = idx_add.out;
+      index_lt_depth_plus_1.right = depth_plus_1.out;
+      idx_between_1_depth_plus_1_comb.left = index_ge_1.out;
+      idx_between_1_depth_plus_1_comb.right = index_lt_depth_plus_1.out;
+      idx_between_1_depth_plus_1_reg.in = idx_between_1_depth_plus_1_comb.out;
+      idx_between_1_depth_plus_1_reg.write_en = 1'd1;
+    }
+    static<1> group init_idx_between_1_depth_plus_1 {
+      idx_between_1_depth_plus_1_reg.in = 1'd0;
+      idx_between_1_depth_plus_1_reg.write_en = 1'd1;
+    }
+    static<1> group idx_between_1_min_depth_4_plus_1_group {
+      index_ge_1.left = idx_add.out;
+      index_ge_1.right = 32'd1;
+      index_lt_min_depth_4_plus_1.left = idx_add.out;
+      index_lt_min_depth_4_plus_1.right = min_depth_4_plus_1.out;
+      idx_between_1_min_depth_4_plus_1_comb.left = index_ge_1.out;
+      idx_between_1_min_depth_4_plus_1_comb.right = index_lt_min_depth_4_plus_1.out;
+      idx_between_1_min_depth_4_plus_1_reg.in = idx_between_1_min_depth_4_plus_1_comb.out;
+      idx_between_1_min_depth_4_plus_1_reg.write_en = 1'd1;
+    }
+    static<1> group init_idx_between_1_min_depth_4_plus_1 {
+      idx_between_1_min_depth_4_plus_1_reg.in = 1'd0;
+      idx_between_1_min_depth_4_plus_1_reg.write_en = 1'd1;
+    }
+    static<1> group idx_between_depth_plus_5_depth_plus_6_group {
+      index_ge_depth_plus_5.left = idx_add.out;
+      index_ge_depth_plus_5.right = depth_plus_5.out;
+      index_lt_depth_plus_6.left = idx_add.out;
+      index_lt_depth_plus_6.right = depth_plus_6.out;
+      idx_between_depth_plus_5_depth_plus_6_comb.left = index_ge_depth_plus_5.out;
+      idx_between_depth_plus_5_depth_plus_6_comb.right = index_lt_depth_plus_6.out;
+      idx_between_depth_plus_5_depth_plus_6_reg.in = idx_between_depth_plus_5_depth_plus_6_comb.out;
+      idx_between_depth_plus_5_depth_plus_6_reg.write_en = 1'd1;
+    }
+    static<1> group init_idx_between_depth_plus_5_depth_plus_6 {
+      idx_between_depth_plus_5_depth_plus_6_reg.in = 1'd0;
+      idx_between_depth_plus_5_depth_plus_6_reg.write_en = 1'd1;
     }
   }
   control {
-    static seq {
+    seq {
       static par {
         t0_idx_init;
         l0_idx_init;
         init_idx;
-        init_idx_between_8_9;
-        init_idx_between_0_3;
-        init_idx_between_1_4;
-        init_idx_between_5_8;
+        init_min_depth;
+        init_iter_limit;
+        init_cond_reg;
+        init_idx_between_5_depth_plus_5;
+        init_idx_between_0_depth_plus_0;
+        init_idx_between_1_depth_plus_1;
+        init_idx_between_1_min_depth_4_plus_1;
+        init_idx_between_depth_plus_5_depth_plus_6;
       }
-      static repeat 9 {
+      while cond_reg.out {
         static par {
           static par {
             static par {
-              static if idx_between_0_3_reg.out {
+              static if idx_between_0_depth_plus_0_reg.out {
                 static par {
                   l0_move;
                   l0_idx_update;
@@ -178,17 +250,17 @@ component main() -> () {
                   t0_idx_update;
                 }
               }
-              static if idx_between_1_4_reg.out {
+              static if idx_between_1_min_depth_4_plus_1_reg.out {
                 static par {
                   static invoke pe_0_0(top=top_0_0.out, left=left_0_0.out, mul_ready=1'd0)();
                 }
               }
-              static if idx_between_5_8_reg.out {
+              static if idx_between_5_depth_plus_5_reg.out {
                 static par {
                   static invoke pe_0_0(top=top_0_0.out, left=left_0_0.out, mul_ready=1'd1)();
                 }
               }
-              static if idx_between_8_9_reg.out {
+              static if idx_between_depth_plus_5_depth_plus_6_reg.out {
                 static par {
                   pe_0_0_out_write;
                 }
@@ -197,16 +269,37 @@ component main() -> () {
           }
           static par {
             incr_idx;
-            idx_between_8_9_group;
-            idx_between_0_3_group;
-            idx_between_1_4_group;
-            idx_between_5_8_group;
+            lt_iter_limit_group;
+            idx_between_5_depth_plus_5_group;
+            idx_between_0_depth_plus_0_group;
+            idx_between_1_depth_plus_1_group;
+            idx_between_1_min_depth_4_plus_1_group;
+            idx_between_depth_plus_5_depth_plus_6_group;
+            depth_plus_5_group;
+            depth_plus_0_group;
+            depth_plus_1_group;
+            min_depth_4_plus_1_group;
+            depth_plus_6_group;
           }
         }
       }
     }
   }
 }
+component main() -> () {
+  cells {
+    systolic_array = systolic_array_comp();
+    @external t0 = std_mem_d1(32, 3, 2);
+    @external l0 = std_mem_d1(32, 3, 2);
+    @external out_mem_0 = std_mem_d1(32, 1, 32);
+  }
+  wires {
+
+  }
+  control {
+    invoke systolic_array(depth=32'd3, t0_read_data=t0.read_data, l0_read_data=l0.read_data)(t0_addr0=t0.addr0, l0_addr0=l0.addr0, out_mem_0_addr0=out_mem_0.addr0, out_mem_0_write_data=out_mem_0.write_data, out_mem_0_write_en=out_mem_0.write_en);
+  }
+}
 metadata #{
-0: pe_0_0 filling: [1,4) accumulating: [5 8)
+0: pe_0_0 filling: [1,min_depth_4_plus_1) accumulating: [5 depth_plus_5)
 }#
diff --git a/tests/frontend/systolic/array-2.expect b/tests/frontend/systolic/array-2.expect
index 60218356a4..c8ac3cdcad 100644
--- a/tests/frontend/systolic/array-2.expect
+++ b/tests/frontend/systolic/array-2.expect
@@ -27,8 +27,23 @@ static<1> component mac_pe(top: 32, left: 32, mul_ready: 1) -> (out: 32) {
     }
   }
 }
-component main() -> () {
+component systolic_array_comp(depth: 32, t0_read_data: 32, t1_read_data: 32, l0_read_data: 32, l1_read_data: 32) -> (t0_addr0: 2, t1_addr0: 2, l0_addr0: 2, l1_addr0: 2, out_mem_0_addr0: 32, out_mem_0_write_data: 32, out_mem_0_write_en: 1, out_mem_1_addr0: 32, out_mem_1_write_data: 32, out_mem_1_write_en: 1) {
   cells {
+    min_depth_4 = std_reg(32);
+    lt_depth_4 = std_lt(32);
+    iter_limit = std_reg(32);
+    iter_limit_add = std_add(32);
+    depth_plus_5 = std_add(32);
+    depth_plus_2 = std_add(32);
+    depth_plus_7 = std_add(32);
+    depth_plus_0 = std_add(32);
+    min_depth_4_plus_1 = std_add(32);
+    depth_plus_1 = std_add(32);
+    depth_plus_6 = std_add(32);
+    min_depth_4_plus_3 = std_add(32);
+    depth_plus_3 = std_add(32);
+    min_depth_4_plus_2 = std_add(32);
+    depth_plus_8 = std_add(32);
     pe_0_0 = mac_pe();
     top_0_0 = std_reg(32);
     left_0_0 = std_reg(32);
@@ -41,60 +56,122 @@ component main() -> () {
     pe_1_1 = mac_pe();
     top_1_1 = std_reg(32);
     left_1_1 = std_reg(32);
-    @external t0 = std_mem_d1(32, 3, 2);
     t0_idx = std_reg(2);
     t0_add = std_add(2);
-    @external t1 = std_mem_d1(32, 3, 2);
     t1_idx = std_reg(2);
     t1_add = std_add(2);
-    @external l0 = std_mem_d1(32, 3, 2);
     l0_idx = std_reg(2);
     l0_add = std_add(2);
-    @external l1 = std_mem_d1(32, 3, 2);
     l1_idx = std_reg(2);
     l1_add = std_add(2);
-    @external out_mem_0 = std_mem_d1(32, 2, 2);
-    @external out_mem_1 = std_mem_d1(32, 2, 2);
-    idx = std_reg(4);
-    idx_add = std_add(4);
-    idx_between_9_10_reg = std_reg(1);
-    index_lt_10 = std_lt(4);
-    index_ge_9 = std_ge(4);
-    idx_between_9_10_comb = std_and(1);
-    idx_between_10_11_reg = std_reg(1);
-    index_lt_11 = std_lt(4);
-    index_ge_10 = std_ge(4);
-    idx_between_10_11_comb = std_and(1);
-    idx_between_5_8_reg = std_reg(1);
-    index_lt_8 = std_lt(4);
-    index_ge_5 = std_ge(4);
-    idx_between_5_8_comb = std_and(1);
-    idx_between_7_10_reg = std_reg(1);
-    index_ge_7 = std_ge(4);
-    idx_between_7_10_comb = std_and(1);
-    idx_between_0_3_reg = std_reg(1);
-    index_lt_3 = std_lt(4);
-    idx_between_1_4_reg = std_reg(1);
-    index_lt_4 = std_lt(4);
-    index_ge_1 = std_ge(4);
-    idx_between_1_4_comb = std_and(1);
-    idx_between_8_9_reg = std_reg(1);
-    index_lt_9 = std_lt(4);
-    index_ge_8 = std_ge(4);
-    idx_between_8_9_comb = std_and(1);
-    idx_between_3_6_reg = std_reg(1);
-    index_lt_6 = std_lt(4);
-    index_ge_3 = std_ge(4);
-    idx_between_3_6_comb = std_and(1);
-    idx_between_2_5_reg = std_reg(1);
-    index_lt_5 = std_lt(4);
-    index_ge_2 = std_ge(4);
-    idx_between_2_5_comb = std_and(1);
-    idx_between_6_9_reg = std_reg(1);
-    index_ge_6 = std_ge(4);
-    idx_between_6_9_comb = std_and(1);
+    idx = std_reg(32);
+    idx_add = std_add(32);
+    lt_iter_limit = std_lt(32);
+    cond_reg = std_reg(1);
+    idx_between_5_depth_plus_5_reg = std_reg(1);
+    index_lt_depth_plus_5 = std_lt(32);
+    index_ge_5 = std_ge(32);
+    idx_between_5_depth_plus_5_comb = std_and(1);
+    idx_between_2_depth_plus_2_reg = std_reg(1);
+    index_lt_depth_plus_2 = std_lt(32);
+    index_ge_2 = std_ge(32);
+    idx_between_2_depth_plus_2_comb = std_and(1);
+    idx_between_7_depth_plus_7_reg = std_reg(1);
+    index_lt_depth_plus_7 = std_lt(32);
+    index_ge_7 = std_ge(32);
+    idx_between_7_depth_plus_7_comb = std_and(1);
+    idx_between_0_depth_plus_0_reg = std_reg(1);
+    index_lt_depth_plus_0 = std_lt(32);
+    idx_between_1_min_depth_4_plus_1_reg = std_reg(1);
+    index_lt_min_depth_4_plus_1 = std_lt(32);
+    index_ge_1 = std_ge(32);
+    idx_between_1_min_depth_4_plus_1_comb = std_and(1);
+    idx_between_1_depth_plus_1_reg = std_reg(1);
+    index_lt_depth_plus_1 = std_lt(32);
+    idx_between_1_depth_plus_1_comb = std_and(1);
+    idx_between_depth_plus_6_depth_plus_7_reg = std_reg(1);
+    index_ge_depth_plus_6 = std_ge(32);
+    idx_between_depth_plus_6_depth_plus_7_comb = std_and(1);
+    idx_between_3_min_depth_4_plus_3_reg = std_reg(1);
+    index_lt_min_depth_4_plus_3 = std_lt(32);
+    index_ge_3 = std_ge(32);
+    idx_between_3_min_depth_4_plus_3_comb = std_and(1);
+    idx_between_3_depth_plus_3_reg = std_reg(1);
+    index_lt_depth_plus_3 = std_lt(32);
+    idx_between_3_depth_plus_3_comb = std_and(1);
+    idx_between_depth_plus_5_depth_plus_6_reg = std_reg(1);
+    index_lt_depth_plus_6 = std_lt(32);
+    index_ge_depth_plus_5 = std_ge(32);
+    idx_between_depth_plus_5_depth_plus_6_comb = std_and(1);
+    idx_between_2_min_depth_4_plus_2_reg = std_reg(1);
+    index_lt_min_depth_4_plus_2 = std_lt(32);
+    idx_between_2_min_depth_4_plus_2_comb = std_and(1);
+    idx_between_6_depth_plus_6_reg = std_reg(1);
+    index_ge_6 = std_ge(32);
+    idx_between_6_depth_plus_6_comb = std_and(1);
+    idx_between_depth_plus_7_depth_plus_8_reg = std_reg(1);
+    index_lt_depth_plus_8 = std_lt(32);
+    index_ge_depth_plus_7 = std_ge(32);
+    idx_between_depth_plus_7_depth_plus_8_comb = std_and(1);
   }
   wires {
+    static<1> group init_min_depth {
+      lt_depth_4.left = depth;
+      lt_depth_4.right = 32'd4;
+      min_depth_4.in = lt_depth_4.out ? depth;
+      min_depth_4.in = !lt_depth_4.out ? 32'd4;
+      min_depth_4.write_en = 1'd1;
+    }
+    static<1> group init_iter_limit {
+      iter_limit_add.left = 32'd8;
+      iter_limit_add.right = depth;
+      iter_limit.in = iter_limit_add.out;
+      iter_limit.write_en = 1'd1;
+    }
+    static<1> group depth_plus_5_group {
+      depth_plus_5.left = depth;
+      depth_plus_5.right = 32'd5;
+    }
+    static<1> group depth_plus_2_group {
+      depth_plus_2.left = depth;
+      depth_plus_2.right = 32'd2;
+    }
+    static<1> group depth_plus_7_group {
+      depth_plus_7.left = depth;
+      depth_plus_7.right = 32'd7;
+    }
+    static<1> group depth_plus_0_group {
+      depth_plus_0.left = depth;
+      depth_plus_0.right = 32'd0;
+    }
+    static<1> group min_depth_4_plus_1_group {
+      min_depth_4_plus_1.left = min_depth_4.out;
+      min_depth_4_plus_1.right = 32'd1;
+    }
+    static<1> group depth_plus_1_group {
+      depth_plus_1.left = depth;
+      depth_plus_1.right = 32'd1;
+    }
+    static<1> group depth_plus_6_group {
+      depth_plus_6.left = depth;
+      depth_plus_6.right = 32'd6;
+    }
+    static<1> group min_depth_4_plus_3_group {
+      min_depth_4_plus_3.left = min_depth_4.out;
+      min_depth_4_plus_3.right = 32'd3;
+    }
+    static<1> group depth_plus_3_group {
+      depth_plus_3.left = depth;
+      depth_plus_3.right = 32'd3;
+    }
+    static<1> group min_depth_4_plus_2_group {
+      min_depth_4_plus_2.left = min_depth_4.out;
+      min_depth_4_plus_2.right = 32'd2;
+    }
+    static<1> group depth_plus_8_group {
+      depth_plus_8.left = depth;
+      depth_plus_8.right = 32'd8;
+    }
     static<1> group t0_idx_init {
       t0_idx.in = 2'd0;
       t0_idx.write_en = 1'd1;
@@ -106,8 +183,8 @@ component main() -> () {
       t0_idx.write_en = 1'd1;
     }
     static<1> group t0_move {
-      t0.addr0 = t0_idx.out;
-      top_0_0.in = t0.read_data;
+      t0_addr0 = t0_idx.out;
+      top_0_0.in = t0_read_data;
       top_0_0.write_en = 1'd1;
     }
     static<1> group t1_idx_init {
@@ -121,8 +198,8 @@ component main() -> () {
       t1_idx.write_en = 1'd1;
     }
     static<1> group t1_move {
-      t1.addr0 = t1_idx.out;
-      top_0_1.in = t1.read_data;
+      t1_addr0 = t1_idx.out;
+      top_0_1.in = t1_read_data;
       top_0_1.write_en = 1'd1;
     }
     static<1> group l0_idx_init {
@@ -136,8 +213,8 @@ component main() -> () {
       l0_idx.write_en = 1'd1;
     }
     static<1> group l0_move {
-      l0.addr0 = l0_idx.out;
-      left_0_0.in = l0.read_data;
+      l0_addr0 = l0_idx.out;
+      left_0_0.in = l0_read_data;
       left_0_0.write_en = 1'd1;
     }
     static<1> group l1_idx_init {
@@ -151,8 +228,8 @@ component main() -> () {
       l1_idx.write_en = 1'd1;
     }
     static<1> group l1_move {
-      l1.addr0 = l1_idx.out;
-      left_1_0.in = l1.read_data;
+      l1_addr0 = l1_idx.out;
+      left_1_0.in = l1_read_data;
       left_1_0.write_en = 1'd1;
     }
     static<1> group pe_0_0_right_move {
@@ -164,204 +241,262 @@ component main() -> () {
       top_1_0.write_en = 1'd1;
     }
     static<1> group pe_0_0_out_write {
-      out_mem_0.addr0 = 2'd0;
-      out_mem_0.write_data = pe_0_0.out;
-      out_mem_0.write_en = 1'd1;
+      out_mem_0_addr0 = 32'd0;
+      out_mem_0_write_data = pe_0_0.out;
+      out_mem_0_write_en = 1'd1;
     }
     static<1> group pe_0_1_down_move {
       top_1_1.in = top_0_1.out;
       top_1_1.write_en = 1'd1;
     }
     static<1> group pe_0_1_out_write {
-      out_mem_0.addr0 = 2'd1;
-      out_mem_0.write_data = pe_0_1.out;
-      out_mem_0.write_en = 1'd1;
+      out_mem_0_addr0 = 32'd1;
+      out_mem_0_write_data = pe_0_1.out;
+      out_mem_0_write_en = 1'd1;
     }
     static<1> group pe_1_0_right_move {
       left_1_1.in = left_1_0.out;
       left_1_1.write_en = 1'd1;
     }
     static<1> group pe_1_0_out_write {
-      out_mem_1.addr0 = 2'd0;
-      out_mem_1.write_data = pe_1_0.out;
-      out_mem_1.write_en = 1'd1;
+      out_mem_1_addr0 = 32'd0;
+      out_mem_1_write_data = pe_1_0.out;
+      out_mem_1_write_en = 1'd1;
     }
     static<1> group pe_1_1_out_write {
-      out_mem_1.addr0 = 2'd1;
-      out_mem_1.write_data = pe_1_1.out;
-      out_mem_1.write_en = 1'd1;
+      out_mem_1_addr0 = 32'd1;
+      out_mem_1_write_data = pe_1_1.out;
+      out_mem_1_write_en = 1'd1;
     }
     static<1> group init_idx {
-      idx.in = 4'd0;
+      idx.in = 32'd0;
       idx.write_en = 1'd1;
     }
     static<1> group incr_idx {
       idx_add.left = idx.out;
-      idx_add.right = 4'd1;
+      idx_add.right = 32'd1;
       idx.in = idx_add.out;
       idx.write_en = 1'd1;
     }
-    static<1> group idx_between_9_10_group {
-      index_ge_9.left = idx_add.out;
-      index_ge_9.right = 4'd9;
-      index_lt_10.left = idx_add.out;
-      index_lt_10.right = 4'd10;
-      idx_between_9_10_comb.left = index_ge_9.out;
-      idx_between_9_10_comb.right = index_lt_10.out;
-      idx_between_9_10_reg.in = idx_between_9_10_comb.out;
-      idx_between_9_10_reg.write_en = 1'd1;
-    }
-    static<1> group init_idx_between_9_10 {
-      idx_between_9_10_reg.in = 1'd0;
-      idx_between_9_10_reg.write_en = 1'd1;
-    }
-    static<1> group idx_between_10_11_group {
-      index_ge_10.left = idx_add.out;
-      index_ge_10.right = 4'd10;
-      index_lt_11.left = idx_add.out;
-      index_lt_11.right = 4'd11;
-      idx_between_10_11_comb.left = index_ge_10.out;
-      idx_between_10_11_comb.right = index_lt_11.out;
-      idx_between_10_11_reg.in = idx_between_10_11_comb.out;
-      idx_between_10_11_reg.write_en = 1'd1;
-    }
-    static<1> group init_idx_between_10_11 {
-      idx_between_10_11_reg.in = 1'd0;
-      idx_between_10_11_reg.write_en = 1'd1;
-    }
-    static<1> group idx_between_5_8_group {
+    static<1> group lt_iter_limit_group {
+      lt_iter_limit.left = idx_add.out;
+      lt_iter_limit.right = iter_limit.out;
+      cond_reg.in = lt_iter_limit.out;
+      cond_reg.write_en = 1'd1;
+    }
+    static<1> group init_cond_reg {
+      cond_reg.in = 1'd1;
+      cond_reg.write_en = 1'd1;
+    }
+    static<1> group idx_between_5_depth_plus_5_group {
       index_ge_5.left = idx_add.out;
-      index_ge_5.right = 4'd5;
-      index_lt_8.left = idx_add.out;
-      index_lt_8.right = 4'd8;
-      idx_between_5_8_comb.left = index_ge_5.out;
-      idx_between_5_8_comb.right = index_lt_8.out;
-      idx_between_5_8_reg.in = idx_between_5_8_comb.out;
-      idx_between_5_8_reg.write_en = 1'd1;
-    }
-    static<1> group init_idx_between_5_8 {
-      idx_between_5_8_reg.in = 1'd0;
-      idx_between_5_8_reg.write_en = 1'd1;
-    }
-    static<1> group idx_between_7_10_group {
+      index_ge_5.right = 32'd5;
+      index_lt_depth_plus_5.left = idx_add.out;
+      index_lt_depth_plus_5.right = depth_plus_5.out;
+      idx_between_5_depth_plus_5_comb.left = index_ge_5.out;
+      idx_between_5_depth_plus_5_comb.right = index_lt_depth_plus_5.out;
+      idx_between_5_depth_plus_5_reg.in = idx_between_5_depth_plus_5_comb.out;
+      idx_between_5_depth_plus_5_reg.write_en = 1'd1;
+    }
+    static<1> group init_idx_between_5_depth_plus_5 {
+      idx_between_5_depth_plus_5_reg.in = 1'd0;
+      idx_between_5_depth_plus_5_reg.write_en = 1'd1;
+    }
+    static<1> group idx_between_2_depth_plus_2_group {
+      index_ge_2.left = idx_add.out;
+      index_ge_2.right = 32'd2;
+      index_lt_depth_plus_2.left = idx_add.out;
+      index_lt_depth_plus_2.right = depth_plus_2.out;
+      idx_between_2_depth_plus_2_comb.left = index_ge_2.out;
+      idx_between_2_depth_plus_2_comb.right = index_lt_depth_plus_2.out;
+      idx_between_2_depth_plus_2_reg.in = idx_between_2_depth_plus_2_comb.out;
+      idx_between_2_depth_plus_2_reg.write_en = 1'd1;
+    }
+    static<1> group init_idx_between_2_depth_plus_2 {
+      idx_between_2_depth_plus_2_reg.in = 1'd0;
+      idx_between_2_depth_plus_2_reg.write_en = 1'd1;
+    }
+    static<1> group idx_between_7_depth_plus_7_group {
       index_ge_7.left = idx_add.out;
-      index_ge_7.right = 4'd7;
-      index_lt_10.left = idx_add.out;
-      index_lt_10.right = 4'd10;
-      idx_between_7_10_comb.left = index_ge_7.out;
-      idx_between_7_10_comb.right = index_lt_10.out;
-      idx_between_7_10_reg.in = idx_between_7_10_comb.out;
-      idx_between_7_10_reg.write_en = 1'd1;
-    }
-    static<1> group init_idx_between_7_10 {
-      idx_between_7_10_reg.in = 1'd0;
-      idx_between_7_10_reg.write_en = 1'd1;
-    }
-    static<1> group idx_between_0_3_group {
-      index_lt_3.left = idx_add.out;
-      index_lt_3.right = 4'd3;
-      idx_between_0_3_reg.in = index_lt_3.out;
-      idx_between_0_3_reg.write_en = 1'd1;
-    }
-    static<1> group init_idx_between_0_3 {
-      idx_between_0_3_reg.in = 1'd1;
-      idx_between_0_3_reg.write_en = 1'd1;
-    }
-    static<1> group idx_between_1_4_group {
+      index_ge_7.right = 32'd7;
+      index_lt_depth_plus_7.left = idx_add.out;
+      index_lt_depth_plus_7.right = depth_plus_7.out;
+      idx_between_7_depth_plus_7_comb.left = index_ge_7.out;
+      idx_between_7_depth_plus_7_comb.right = index_lt_depth_plus_7.out;
+      idx_between_7_depth_plus_7_reg.in = idx_between_7_depth_plus_7_comb.out;
+      idx_between_7_depth_plus_7_reg.write_en = 1'd1;
+    }
+    static<1> group init_idx_between_7_depth_plus_7 {
+      idx_between_7_depth_plus_7_reg.in = 1'd0;
+      idx_between_7_depth_plus_7_reg.write_en = 1'd1;
+    }
+    static<1> group idx_between_0_depth_plus_0_group {
+      index_lt_depth_plus_0.left = idx_add.out;
+      index_lt_depth_plus_0.right = depth_plus_0.out;
+      idx_between_0_depth_plus_0_reg.in = index_lt_depth_plus_0.out;
+      idx_between_0_depth_plus_0_reg.write_en = 1'd1;
+    }
+    static<1> group init_idx_between_0_depth_plus_0 {
+      idx_between_0_depth_plus_0_reg.in = 1'd1;
+      idx_between_0_depth_plus_0_reg.write_en = 1'd1;
+    }
+    static<1> group idx_between_1_min_depth_4_plus_1_group {
       index_ge_1.left = idx_add.out;
-      index_ge_1.right = 4'd1;
-      index_lt_4.left = idx_add.out;
-      index_lt_4.right = 4'd4;
-      idx_between_1_4_comb.left = index_ge_1.out;
-      idx_between_1_4_comb.right = index_lt_4.out;
-      idx_between_1_4_reg.in = idx_between_1_4_comb.out;
-      idx_between_1_4_reg.write_en = 1'd1;
-    }
-    static<1> group init_idx_between_1_4 {
-      idx_between_1_4_reg.in = 1'd0;
-      idx_between_1_4_reg.write_en = 1'd1;
-    }
-    static<1> group idx_between_8_9_group {
-      index_ge_8.left = idx_add.out;
-      index_ge_8.right = 4'd8;
-      index_lt_9.left = idx_add.out;
-      index_lt_9.right = 4'd9;
-      idx_between_8_9_comb.left = index_ge_8.out;
-      idx_between_8_9_comb.right = index_lt_9.out;
-      idx_between_8_9_reg.in = idx_between_8_9_comb.out;
-      idx_between_8_9_reg.write_en = 1'd1;
-    }
-    static<1> group init_idx_between_8_9 {
-      idx_between_8_9_reg.in = 1'd0;
-      idx_between_8_9_reg.write_en = 1'd1;
-    }
-    static<1> group idx_between_3_6_group {
+      index_ge_1.right = 32'd1;
+      index_lt_min_depth_4_plus_1.left = idx_add.out;
+      index_lt_min_depth_4_plus_1.right = min_depth_4_plus_1.out;
+      idx_between_1_min_depth_4_plus_1_comb.left = index_ge_1.out;
+      idx_between_1_min_depth_4_plus_1_comb.right = index_lt_min_depth_4_plus_1.out;
+      idx_between_1_min_depth_4_plus_1_reg.in = idx_between_1_min_depth_4_plus_1_comb.out;
+      idx_between_1_min_depth_4_plus_1_reg.write_en = 1'd1;
+    }
+    static<1> group init_idx_between_1_min_depth_4_plus_1 {
+      idx_between_1_min_depth_4_plus_1_reg.in = 1'd0;
+      idx_between_1_min_depth_4_plus_1_reg.write_en = 1'd1;
+    }
+    static<1> group idx_between_1_depth_plus_1_group {
+      index_ge_1.left = idx_add.out;
+      index_ge_1.right = 32'd1;
+      index_lt_depth_plus_1.left = idx_add.out;
+      index_lt_depth_plus_1.right = depth_plus_1.out;
+      idx_between_1_depth_plus_1_comb.left = index_ge_1.out;
+      idx_between_1_depth_plus_1_comb.right = index_lt_depth_plus_1.out;
+      idx_between_1_depth_plus_1_reg.in = idx_between_1_depth_plus_1_comb.out;
+      idx_between_1_depth_plus_1_reg.write_en = 1'd1;
+    }
+    static<1> group init_idx_between_1_depth_plus_1 {
+      idx_between_1_depth_plus_1_reg.in = 1'd0;
+      idx_between_1_depth_plus_1_reg.write_en = 1'd1;
+    }
+    static<1> group idx_between_depth_plus_6_depth_plus_7_group {
+      index_ge_depth_plus_6.left = idx_add.out;
+      index_ge_depth_plus_6.right = depth_plus_6.out;
+      index_lt_depth_plus_7.left = idx_add.out;
+      index_lt_depth_plus_7.right = depth_plus_7.out;
+      idx_between_depth_plus_6_depth_plus_7_comb.left = index_ge_depth_plus_6.out;
+      idx_between_depth_plus_6_depth_plus_7_comb.right = index_lt_depth_plus_7.out;
+      idx_between_depth_plus_6_depth_plus_7_reg.in = idx_between_depth_plus_6_depth_plus_7_comb.out;
+      idx_between_depth_plus_6_depth_plus_7_reg.write_en = 1'd1;
+    }
+    static<1> group init_idx_between_depth_plus_6_depth_plus_7 {
+      idx_between_depth_plus_6_depth_plus_7_reg.in = 1'd0;
+      idx_between_depth_plus_6_depth_plus_7_reg.write_en = 1'd1;
+    }
+    static<1> group idx_between_3_min_depth_4_plus_3_group {
+      index_ge_3.left = idx_add.out;
+      index_ge_3.right = 32'd3;
+      index_lt_min_depth_4_plus_3.left = idx_add.out;
+      index_lt_min_depth_4_plus_3.right = min_depth_4_plus_3.out;
+      idx_between_3_min_depth_4_plus_3_comb.left = index_ge_3.out;
+      idx_between_3_min_depth_4_plus_3_comb.right = index_lt_min_depth_4_plus_3.out;
+      idx_between_3_min_depth_4_plus_3_reg.in = idx_between_3_min_depth_4_plus_3_comb.out;
+      idx_between_3_min_depth_4_plus_3_reg.write_en = 1'd1;
+    }
+    static<1> group init_idx_between_3_min_depth_4_plus_3 {
+      idx_between_3_min_depth_4_plus_3_reg.in = 1'd0;
+      idx_between_3_min_depth_4_plus_3_reg.write_en = 1'd1;
+    }
+    static<1> group idx_between_3_depth_plus_3_group {
       index_ge_3.left = idx_add.out;
-      index_ge_3.right = 4'd3;
-      index_lt_6.left = idx_add.out;
-      index_lt_6.right = 4'd6;
-      idx_between_3_6_comb.left = index_ge_3.out;
-      idx_between_3_6_comb.right = index_lt_6.out;
-      idx_between_3_6_reg.in = idx_between_3_6_comb.out;
-      idx_between_3_6_reg.write_en = 1'd1;
-    }
-    static<1> group init_idx_between_3_6 {
-      idx_between_3_6_reg.in = 1'd0;
-      idx_between_3_6_reg.write_en = 1'd1;
-    }
-    static<1> group idx_between_2_5_group {
+      index_ge_3.right = 32'd3;
+      index_lt_depth_plus_3.left = idx_add.out;
+      index_lt_depth_plus_3.right = depth_plus_3.out;
+      idx_between_3_depth_plus_3_comb.left = index_ge_3.out;
+      idx_between_3_depth_plus_3_comb.right = index_lt_depth_plus_3.out;
+      idx_between_3_depth_plus_3_reg.in = idx_between_3_depth_plus_3_comb.out;
+      idx_between_3_depth_plus_3_reg.write_en = 1'd1;
+    }
+    static<1> group init_idx_between_3_depth_plus_3 {
+      idx_between_3_depth_plus_3_reg.in = 1'd0;
+      idx_between_3_depth_plus_3_reg.write_en = 1'd1;
+    }
+    static<1> group idx_between_depth_plus_5_depth_plus_6_group {
+      index_ge_depth_plus_5.left = idx_add.out;
+      index_ge_depth_plus_5.right = depth_plus_5.out;
+      index_lt_depth_plus_6.left = idx_add.out;
+      index_lt_depth_plus_6.right = depth_plus_6.out;
+      idx_between_depth_plus_5_depth_plus_6_comb.left = index_ge_depth_plus_5.out;
+      idx_between_depth_plus_5_depth_plus_6_comb.right = index_lt_depth_plus_6.out;
+      idx_between_depth_plus_5_depth_plus_6_reg.in = idx_between_depth_plus_5_depth_plus_6_comb.out;
+      idx_between_depth_plus_5_depth_plus_6_reg.write_en = 1'd1;
+    }
+    static<1> group init_idx_between_depth_plus_5_depth_plus_6 {
+      idx_between_depth_plus_5_depth_plus_6_reg.in = 1'd0;
+      idx_between_depth_plus_5_depth_plus_6_reg.write_en = 1'd1;
+    }
+    static<1> group idx_between_2_min_depth_4_plus_2_group {
       index_ge_2.left = idx_add.out;
-      index_ge_2.right = 4'd2;
-      index_lt_5.left = idx_add.out;
-      index_lt_5.right = 4'd5;
-      idx_between_2_5_comb.left = index_ge_2.out;
-      idx_between_2_5_comb.right = index_lt_5.out;
-      idx_between_2_5_reg.in = idx_between_2_5_comb.out;
-      idx_between_2_5_reg.write_en = 1'd1;
-    }
-    static<1> group init_idx_between_2_5 {
-      idx_between_2_5_reg.in = 1'd0;
-      idx_between_2_5_reg.write_en = 1'd1;
-    }
-    static<1> group idx_between_6_9_group {
+      index_ge_2.right = 32'd2;
+      index_lt_min_depth_4_plus_2.left = idx_add.out;
+      index_lt_min_depth_4_plus_2.right = min_depth_4_plus_2.out;
+      idx_between_2_min_depth_4_plus_2_comb.left = index_ge_2.out;
+      idx_between_2_min_depth_4_plus_2_comb.right = index_lt_min_depth_4_plus_2.out;
+      idx_between_2_min_depth_4_plus_2_reg.in = idx_between_2_min_depth_4_plus_2_comb.out;
+      idx_between_2_min_depth_4_plus_2_reg.write_en = 1'd1;
+    }
+    static<1> group init_idx_between_2_min_depth_4_plus_2 {
+      idx_between_2_min_depth_4_plus_2_reg.in = 1'd0;
+      idx_between_2_min_depth_4_plus_2_reg.write_en = 1'd1;
+    }
+    static<1> group idx_between_6_depth_plus_6_group {
       index_ge_6.left = idx_add.out;
-      index_ge_6.right = 4'd6;
-      index_lt_9.left = idx_add.out;
-      index_lt_9.right = 4'd9;
-      idx_between_6_9_comb.left = index_ge_6.out;
-      idx_between_6_9_comb.right = index_lt_9.out;
-      idx_between_6_9_reg.in = idx_between_6_9_comb.out;
-      idx_between_6_9_reg.write_en = 1'd1;
-    }
-    static<1> group init_idx_between_6_9 {
-      idx_between_6_9_reg.in = 1'd0;
-      idx_between_6_9_reg.write_en = 1'd1;
+      index_ge_6.right = 32'd6;
+      index_lt_depth_plus_6.left = idx_add.out;
+      index_lt_depth_plus_6.right = depth_plus_6.out;
+      idx_between_6_depth_plus_6_comb.left = index_ge_6.out;
+      idx_between_6_depth_plus_6_comb.right = index_lt_depth_plus_6.out;
+      idx_between_6_depth_plus_6_reg.in = idx_between_6_depth_plus_6_comb.out;
+      idx_between_6_depth_plus_6_reg.write_en = 1'd1;
+    }
+    static<1> group init_idx_between_6_depth_plus_6 {
+      idx_between_6_depth_plus_6_reg.in = 1'd0;
+      idx_between_6_depth_plus_6_reg.write_en = 1'd1;
+    }
+    static<1> group idx_between_depth_plus_7_depth_plus_8_group {
+      index_ge_depth_plus_7.left = idx_add.out;
+      index_ge_depth_plus_7.right = depth_plus_7.out;
+      index_lt_depth_plus_8.left = idx_add.out;
+      index_lt_depth_plus_8.right = depth_plus_8.out;
+      idx_between_depth_plus_7_depth_plus_8_comb.left = index_ge_depth_plus_7.out;
+      idx_between_depth_plus_7_depth_plus_8_comb.right = index_lt_depth_plus_8.out;
+      idx_between_depth_plus_7_depth_plus_8_reg.in = idx_between_depth_plus_7_depth_plus_8_comb.out;
+      idx_between_depth_plus_7_depth_plus_8_reg.write_en = 1'd1;
+    }
+    static<1> group init_idx_between_depth_plus_7_depth_plus_8 {
+      idx_between_depth_plus_7_depth_plus_8_reg.in = 1'd0;
+      idx_between_depth_plus_7_depth_plus_8_reg.write_en = 1'd1;
     }
   }
   control {
-    static seq {
+    seq {
       static par {
         t0_idx_init;
         t1_idx_init;
         l0_idx_init;
         l1_idx_init;
         init_idx;
-        init_idx_between_9_10;
-        init_idx_between_10_11;
-        init_idx_between_5_8;
-        init_idx_between_7_10;
-        init_idx_between_0_3;
-        init_idx_between_1_4;
-        init_idx_between_8_9;
-        init_idx_between_3_6;
-        init_idx_between_2_5;
-        init_idx_between_6_9;
+        init_min_depth;
+        init_iter_limit;
+        init_cond_reg;
+        init_idx_between_5_depth_plus_5;
+        init_idx_between_2_depth_plus_2;
+        init_idx_between_7_depth_plus_7;
+        init_idx_between_0_depth_plus_0;
+        init_idx_between_1_min_depth_4_plus_1;
+        init_idx_between_1_depth_plus_1;
+        init_idx_between_depth_plus_6_depth_plus_7;
+        init_idx_between_3_min_depth_4_plus_3;
+        init_idx_between_3_depth_plus_3;
+        init_idx_between_depth_plus_5_depth_plus_6;
+        init_idx_between_2_min_depth_4_plus_2;
+        init_idx_between_6_depth_plus_6;
+        init_idx_between_depth_plus_7_depth_plus_8;
       }
-      static repeat 11 {
+      while cond_reg.out {
         static par {
           static par {
             static par {
-              static if idx_between_0_3_reg.out {
+              static if idx_between_0_depth_plus_0_reg.out {
                 static par {
                   l0_move;
                   l0_idx_update;
@@ -369,96 +504,96 @@ component main() -> () {
                   t0_idx_update;
                 }
               }
-              static if idx_between_1_4_reg.out {
+              static if idx_between_1_min_depth_4_plus_1_reg.out {
                 static par {
                   static invoke pe_0_0(top=top_0_0.out, left=left_0_0.out, mul_ready=1'd0)();
                 }
               }
-              static if idx_between_1_4_reg.out {
+              static if idx_between_1_depth_plus_1_reg.out {
                 static par {
                   pe_0_0_down_move;
                   pe_0_0_right_move;
                 }
               }
-              static if idx_between_5_8_reg.out {
+              static if idx_between_5_depth_plus_5_reg.out {
                 static par {
                   static invoke pe_0_0(top=top_0_0.out, left=left_0_0.out, mul_ready=1'd1)();
                 }
               }
-              static if idx_between_8_9_reg.out {
+              static if idx_between_depth_plus_5_depth_plus_6_reg.out {
                 static par {
                   pe_0_0_out_write;
                 }
               }
             }
             static par {
-              static if idx_between_1_4_reg.out {
+              static if idx_between_1_depth_plus_1_reg.out {
                 static par {
                   t1_move;
                   t1_idx_update;
                 }
               }
-              static if idx_between_2_5_reg.out {
+              static if idx_between_2_min_depth_4_plus_2_reg.out {
                 static par {
                   static invoke pe_0_1(top=top_0_1.out, left=left_0_1.out, mul_ready=1'd0)();
                 }
               }
-              static if idx_between_2_5_reg.out {
+              static if idx_between_2_depth_plus_2_reg.out {
                 static par {
                   pe_0_1_down_move;
                 }
               }
-              static if idx_between_6_9_reg.out {
+              static if idx_between_6_depth_plus_6_reg.out {
                 static par {
                   static invoke pe_0_1(top=top_0_1.out, left=left_0_1.out, mul_ready=1'd1)();
                 }
               }
-              static if idx_between_9_10_reg.out {
+              static if idx_between_depth_plus_6_depth_plus_7_reg.out {
                 static par {
                   pe_0_1_out_write;
                 }
               }
             }
             static par {
-              static if idx_between_1_4_reg.out {
+              static if idx_between_1_depth_plus_1_reg.out {
                 static par {
                   l1_move;
                   l1_idx_update;
                 }
               }
-              static if idx_between_2_5_reg.out {
+              static if idx_between_2_min_depth_4_plus_2_reg.out {
                 static par {
                   static invoke pe_1_0(top=top_1_0.out, left=left_1_0.out, mul_ready=1'd0)();
                 }
               }
-              static if idx_between_2_5_reg.out {
+              static if idx_between_2_depth_plus_2_reg.out {
                 static par {
                   pe_1_0_right_move;
                 }
               }
-              static if idx_between_6_9_reg.out {
+              static if idx_between_6_depth_plus_6_reg.out {
                 static par {
                   static invoke pe_1_0(top=top_1_0.out, left=left_1_0.out, mul_ready=1'd1)();
                 }
               }
-              static if idx_between_9_10_reg.out {
+              static if idx_between_depth_plus_6_depth_plus_7_reg.out {
                 static par {
                   pe_1_0_out_write;
                 }
               }
             }
             static par {
-              static if idx_between_3_6_reg.out {
+              static if idx_between_3_min_depth_4_plus_3_reg.out {
                 static par {
                   static invoke pe_1_1(top=top_1_1.out, left=left_1_1.out, mul_ready=1'd0)();
                 }
               }
-              static if idx_between_7_10_reg.out {
+              static if idx_between_7_depth_plus_7_reg.out {
                 static par {
                   static invoke pe_1_1(top=top_1_1.out, left=left_1_1.out, mul_ready=1'd1)();
                 }
               }
-              static if idx_between_10_11_reg.out {
+              static if idx_between_depth_plus_7_depth_plus_8_reg.out {
                 static par {
                   pe_1_1_out_write;
                 }
@@ -467,25 +602,57 @@ component main() -> () {
           }
           static par {
             incr_idx;
-            idx_between_9_10_group;
-            idx_between_10_11_group;
-            idx_between_5_8_group;
-            idx_between_7_10_group;
-            idx_between_0_3_group;
-            idx_between_1_4_group;
-            idx_between_8_9_group;
-            idx_between_3_6_group;
-            idx_between_2_5_group;
-            idx_between_6_9_group;
+            lt_iter_limit_group;
+            idx_between_5_depth_plus_5_group;
+            idx_between_2_depth_plus_2_group;
+            idx_between_7_depth_plus_7_group;
+            idx_between_0_depth_plus_0_group;
+            idx_between_1_min_depth_4_plus_1_group;
+            idx_between_1_depth_plus_1_group;
+            idx_between_depth_plus_6_depth_plus_7_group;
+            idx_between_3_min_depth_4_plus_3_group;
+            idx_between_3_depth_plus_3_group;
+            idx_between_depth_plus_5_depth_plus_6_group;
+            idx_between_2_min_depth_4_plus_2_group;
+            idx_between_6_depth_plus_6_group;
+            idx_between_depth_plus_7_depth_plus_8_group;
+            depth_plus_5_group;
+            depth_plus_2_group;
+            depth_plus_7_group;
+            depth_plus_0_group;
+            min_depth_4_plus_1_group;
+            depth_plus_1_group;
+            depth_plus_6_group;
+            min_depth_4_plus_3_group;
+            depth_plus_3_group;
+            min_depth_4_plus_2_group;
+            depth_plus_8_group;
           }
         }
       }
     }
   }
 }
+component main() -> () {
+  cells {
+    systolic_array = systolic_array_comp();
+    @external t0 = std_mem_d1(32, 3, 2);
+    @external t1 = std_mem_d1(32, 3, 2);
+    @external l0 = std_mem_d1(32, 3, 2);
+    @external l1 = std_mem_d1(32, 3, 2);
+    @external out_mem_0 = std_mem_d1(32, 2, 32);
+    @external out_mem_1 = std_mem_d1(32, 2, 32);
+  }
+  wires {
+
+  }
+  control {
+    invoke systolic_array(depth=32'd3, t0_read_data=t0.read_data, t1_read_data=t1.read_data, l0_read_data=l0.read_data, l1_read_data=l1.read_data)(t0_addr0=t0.addr0, t1_addr0=t1.addr0, l0_addr0=l0.addr0, l1_addr0=l1.addr0, out_mem_0_addr0=out_mem_0.addr0, out_mem_0_write_data=out_mem_0.write_data, out_mem_0_write_en=out_mem_0.write_en, out_mem_1_addr0=out_mem_1.addr0, out_mem_1_write_data=out_mem_1.write_data, out_mem_1_write_en=out_mem_1.write_en);
+  }
+}
 metadata #{
-0: pe_0_0 filling: [1,4) accumulating: [5 8)
-1: pe_0_1 filling: [2,5) accumulating: [6 9)
-2: pe_1_0 filling: [2,5) accumulating: [6 9)
-3: pe_1_1 filling: [3,6) accumulating: [7 10)
+0: pe_0_0 filling: [1,min_depth_4_plus_1) accumulating: [5 depth_plus_5)
+1: pe_0_1 filling: [2,min_depth_4_plus_2) accumulating: [6 depth_plus_6)
+2: pe_1_0 filling: [2,min_depth_4_plus_2) accumulating: [6 depth_plus_6)
+3: pe_1_1 filling: [3,min_depth_4_plus_3) accumulating: [7 depth_plus_7)
 }#
diff --git a/tests/frontend/systolic/array-3.expect b/tests/frontend/systolic/array-3.expect
index 8f08efe898..7d0fa872e2 100644
--- a/tests/frontend/systolic/array-3.expect
+++ b/tests/frontend/systolic/array-3.expect
@@ -27,8 +27,28 @@ static<1> component mac_pe(top: 32, left: 32, mul_ready: 1) -> (out: 32) {
     }
   }
 }
-component main() -> () {
+component systolic_array_comp(depth: 32, t0_read_data: 32, t1_read_data: 32, t2_read_data: 32, l0_read_data: 32, l1_read_data: 32, l2_read_data: 32) -> (t0_addr0: 2, t1_addr0: 2, t2_addr0: 2, l0_addr0: 2, l1_addr0: 2, l2_addr0: 2, out_mem_0_addr0: 32, out_mem_0_write_data: 32, out_mem_0_write_en: 1, out_mem_1_addr0: 32, out_mem_1_write_data: 32, out_mem_1_write_en: 1, out_mem_2_addr0: 32, out_mem_2_write_data: 32, out_mem_2_write_en: 1) {
   cells {
+    min_depth_4 = std_reg(32);
+    lt_depth_4 = std_lt(32);
+    iter_limit = std_reg(32);
+    iter_limit_add = std_add(32);
+    depth_plus_8 = std_add(32);
+    depth_plus_9 = std_add(32);
+    min_depth_4_plus_2 = std_add(32);
+    depth_plus_2 = std_add(32);
+    depth_plus_7 = std_add(32);
+    depth_plus_3 = std_add(32);
+    min_depth_4_plus_3 = std_add(32);
+    depth_plus_5 = std_add(32);
+    depth_plus_6 = std_add(32);
+    depth_plus_10 = std_add(32);
+    depth_plus_4 = std_add(32);
+    min_depth_4_plus_4 = std_add(32);
+    min_depth_4_plus_5 = std_add(32);
+    depth_plus_0 = std_add(32);
+    depth_plus_1 = std_add(32);
+    min_depth_4_plus_1 = std_add(32);
     pe_0_0 = mac_pe();
     top_0_0 = std_reg(32);
     left_0_0 = std_reg(32);
@@ -56,83 +76,170 @@ component main() -> () {
     pe_2_2 = mac_pe();
     top_2_2 = std_reg(32);
     left_2_2 = std_reg(32);
-    @external t0 = std_mem_d1(32, 3, 2);
     t0_idx = std_reg(2);
     t0_add = std_add(2);
-    @external t1 = std_mem_d1(32, 3, 2);
     t1_idx = std_reg(2);
     t1_add = std_add(2);
-    @external t2 = std_mem_d1(32, 3, 2);
     t2_idx = std_reg(2);
     t2_add = std_add(2);
-    @external l0 = std_mem_d1(32, 3, 2);
     l0_idx = std_reg(2);
     l0_add = std_add(2);
-    @external l1 = std_mem_d1(32, 3, 2);
     l1_idx = std_reg(2);
     l1_add = std_add(2);
-    @external l2 = std_mem_d1(32, 3, 2);
     l2_idx = std_reg(2);
     l2_add = std_add(2);
-    @external out_mem_0 = std_mem_d1(32, 3, 2);
-    @external out_mem_1 = std_mem_d1(32, 3, 2);
-    @external out_mem_2 = std_mem_d1(32, 3, 2);
-    idx = std_reg(4);
-    idx_add = std_add(4);
-    idx_between_9_10_reg = std_reg(1);
-    index_lt_10 = std_lt(4);
-    index_ge_9 = std_ge(4);
-    idx_between_9_10_comb = std_and(1);
-    idx_between_10_11_reg = std_reg(1);
-    index_lt_11 = std_lt(4);
-    index_ge_10 = std_ge(4);
-    idx_between_10_11_comb = std_and(1);
-    idx_between_5_8_reg = std_reg(1);
-    index_lt_8 = std_lt(4);
-    index_ge_5 = std_ge(4);
-    idx_between_5_8_comb = std_and(1);
-    idx_between_7_10_reg = std_reg(1);
-    index_ge_7 = std_ge(4);
-    idx_between_7_10_comb = std_and(1);
-    idx_between_0_3_reg = std_reg(1);
-    index_lt_3 = std_lt(4);
-    idx_between_9_12_reg = std_reg(1);
-    index_lt_12 = std_lt(4);
-    idx_between_9_12_comb = std_and(1);
-    idx_between_12_13_reg = std_reg(1);
-    index_lt_13 = std_lt(4);
-    index_ge_12 = std_ge(4);
-    idx_between_12_13_comb = std_and(1);
-    idx_between_1_4_reg = std_reg(1);
-    index_lt_4 = std_lt(4);
-    index_ge_1 = std_ge(4);
-    idx_between_1_4_comb = std_and(1);
-    idx_between_11_12_reg = std_reg(1);
-    index_ge_11 = std_ge(4);
-    idx_between_11_12_comb = std_and(1);
-    idx_between_8_9_reg = std_reg(1);
-    index_lt_9 = std_lt(4);
-    index_ge_8 = std_ge(4);
-    idx_between_8_9_comb = std_and(1);
-    idx_between_3_6_reg = std_reg(1);
-    index_lt_6 = std_lt(4);
-    index_ge_3 = std_ge(4);
-    idx_between_3_6_comb = std_and(1);
-    idx_between_2_5_reg = std_reg(1);
-    index_lt_5 = std_lt(4);
-    index_ge_2 = std_ge(4);
-    idx_between_2_5_comb = std_and(1);
-    idx_between_6_9_reg = std_reg(1);
-    index_ge_6 = std_ge(4);
-    idx_between_6_9_comb = std_and(1);
-    idx_between_4_7_reg = std_reg(1);
-    index_lt_7 = std_lt(4);
-    index_ge_4 = std_ge(4);
-    idx_between_4_7_comb = std_and(1);
-    idx_between_8_11_reg = std_reg(1);
-    idx_between_8_11_comb = std_and(1);
+    idx = std_reg(32);
+    idx_add = std_add(32);
+    lt_iter_limit = std_lt(32);
+    cond_reg = std_reg(1);
+    idx_between_depth_plus_8_depth_plus_9_reg = std_reg(1);
+    index_lt_depth_plus_9 = std_lt(32);
+    index_ge_depth_plus_8 = std_ge(32);
+    idx_between_depth_plus_8_depth_plus_9_comb = std_and(1);
+    idx_between_2_min_depth_4_plus_2_reg = std_reg(1);
+    index_lt_min_depth_4_plus_2 = std_lt(32);
+    index_ge_2 = std_ge(32);
+    idx_between_2_min_depth_4_plus_2_comb = std_and(1);
+    idx_between_2_depth_plus_2_reg = std_reg(1);
+    index_lt_depth_plus_2 = std_lt(32);
+    idx_between_2_depth_plus_2_comb = std_and(1);
+    idx_between_7_depth_plus_7_reg = std_reg(1);
+    index_lt_depth_plus_7 = std_lt(32);
+    index_ge_7 = std_ge(32);
+    idx_between_7_depth_plus_7_comb = std_and(1);
+    idx_between_3_depth_plus_3_reg = std_reg(1);
+    index_lt_depth_plus_3 = std_lt(32);
+    index_ge_3 = std_ge(32);
+    idx_between_3_depth_plus_3_comb = std_and(1);
+    idx_between_3_min_depth_4_plus_3_reg = std_reg(1);
+    index_lt_min_depth_4_plus_3 = std_lt(32);
+    idx_between_3_min_depth_4_plus_3_comb = std_and(1);
+    idx_between_depth_plus_5_depth_plus_6_reg = std_reg(1);
+    index_lt_depth_plus_6 = std_lt(32);
+    index_ge_depth_plus_5 = std_ge(32);
+    idx_between_depth_plus_5_depth_plus_6_comb = std_and(1);
+    idx_between_depth_plus_9_depth_plus_10_reg = std_reg(1);
+    index_lt_depth_plus_10 = std_lt(32);
+    index_ge_depth_plus_9 = std_ge(32);
+    idx_between_depth_plus_9_depth_plus_10_comb = std_and(1);
+    idx_between_8_depth_plus_8_reg = std_reg(1);
+    index_lt_depth_plus_8 = std_lt(32);
+    index_ge_8 = std_ge(32);
+    idx_between_8_depth_plus_8_comb = std_and(1);
+    idx_between_depth_plus_6_depth_plus_7_reg = std_reg(1);
+    index_ge_depth_plus_6 = std_ge(32);
+    idx_between_depth_plus_6_depth_plus_7_comb = std_and(1);
+    idx_between_4_depth_plus_4_reg = std_reg(1);
+    index_lt_depth_plus_4 = std_lt(32);
+    index_ge_4 = std_ge(32);
+    idx_between_4_depth_plus_4_comb = std_and(1);
+    idx_between_4_min_depth_4_plus_4_reg = std_reg(1);
+    index_lt_min_depth_4_plus_4 = std_lt(32);
+    idx_between_4_min_depth_4_plus_4_comb = std_and(1);
+    idx_between_5_min_depth_4_plus_5_reg = std_reg(1);
+    index_lt_min_depth_4_plus_5 = std_lt(32);
+    index_ge_5 = std_ge(32);
+    idx_between_5_min_depth_4_plus_5_comb = std_and(1);
+    idx_between_5_depth_plus_5_reg = std_reg(1);
+    index_lt_depth_plus_5 = std_lt(32);
+    idx_between_5_depth_plus_5_comb = std_and(1);
+    idx_between_0_depth_plus_0_reg = std_reg(1);
+    index_lt_depth_plus_0 = std_lt(32);
+    idx_between_9_depth_plus_9_reg = std_reg(1);
+    index_ge_9 = std_ge(32);
+    idx_between_9_depth_plus_9_comb = std_and(1);
+    idx_between_1_depth_plus_1_reg = std_reg(1);
+    index_lt_depth_plus_1 = std_lt(32);
+    index_ge_1 = std_ge(32);
+    idx_between_1_depth_plus_1_comb = std_and(1);
+    idx_between_1_min_depth_4_plus_1_reg = std_reg(1);
+    index_lt_min_depth_4_plus_1 = std_lt(32);
+    idx_between_1_min_depth_4_plus_1_comb = std_and(1);
+    idx_between_6_depth_plus_6_reg = std_reg(1);
+    index_ge_6 = std_ge(32);
+    idx_between_6_depth_plus_6_comb = std_and(1);
+    idx_between_depth_plus_7_depth_plus_8_reg = std_reg(1);
+    index_ge_depth_plus_7 = std_ge(32);
+    idx_between_depth_plus_7_depth_plus_8_comb = std_and(1);
   }
   wires {
+    static<1> group init_min_depth {
+      lt_depth_4.left = depth;
+      lt_depth_4.right = 32'd4;
+      min_depth_4.in = lt_depth_4.out ? depth;
+      min_depth_4.in = !lt_depth_4.out ? 32'd4;
+      min_depth_4.write_en = 1'd1;
+    }
+    static<1> group init_iter_limit {
+      iter_limit_add.left = 32'd10;
+      iter_limit_add.right = depth;
+      iter_limit.in = iter_limit_add.out;
+      iter_limit.write_en = 1'd1;
+    }
+    static<1> group depth_plus_8_group {
+      depth_plus_8.left = depth;
+      depth_plus_8.right = 32'd8;
+    }
+    static<1> group depth_plus_9_group {
+      depth_plus_9.left = depth;
+      depth_plus_9.right = 32'd9;
+    }
+    static<1> group min_depth_4_plus_2_group {
+      min_depth_4_plus_2.left = min_depth_4.out;
+      min_depth_4_plus_2.right = 32'd2;
+    }
+    static<1> group depth_plus_2_group {
+      depth_plus_2.left = depth;
+      depth_plus_2.right = 32'd2;
+    }
+    static<1> group depth_plus_7_group {
+      depth_plus_7.left = depth;
+      depth_plus_7.right = 32'd7;
+    }
+    static<1> group depth_plus_3_group {
+      depth_plus_3.left = depth;
+      depth_plus_3.right = 32'd3;
+    }
+    static<1> group min_depth_4_plus_3_group {
+      min_depth_4_plus_3.left = min_depth_4.out;
+      min_depth_4_plus_3.right = 32'd3;
+    }
+    static<1> group depth_plus_5_group {
+      depth_plus_5.left = depth;
+      depth_plus_5.right = 32'd5;
+    }
+    static<1> group depth_plus_6_group {
+      depth_plus_6.left = depth;
+      depth_plus_6.right = 32'd6;
+    }
+    static<1> group depth_plus_10_group {
+      depth_plus_10.left = depth;
+      depth_plus_10.right = 32'd10;
+    }
+    static<1> group depth_plus_4_group {
+      depth_plus_4.left = depth;
+      depth_plus_4.right = 32'd4;
+    }
+    static<1> group min_depth_4_plus_4_group {
+      min_depth_4_plus_4.left = min_depth_4.out;
+      min_depth_4_plus_4.right = 32'd4;
+    }
+    static<1> group min_depth_4_plus_5_group {
+      min_depth_4_plus_5.left = min_depth_4.out;
+      min_depth_4_plus_5.right = 32'd5;
+    }
+    static<1> group depth_plus_0_group {
+      depth_plus_0.left = depth;
+      depth_plus_0.right = 32'd0;
+    }
+    static<1> group depth_plus_1_group {
+      depth_plus_1.left = depth;
+      depth_plus_1.right = 32'd1;
+    }
+    static<1> group min_depth_4_plus_1_group {
+      min_depth_4_plus_1.left = min_depth_4.out;
+      min_depth_4_plus_1.right = 32'd1;
+    }
     static<1> group t0_idx_init {
       t0_idx.in = 2'd0;
       t0_idx.write_en = 1'd1;
@@ -144,8 +251,8 @@ component main() -> () {
       t0_idx.write_en = 1'd1;
     }
     static<1> group t0_move {
-      t0.addr0 = t0_idx.out;
-      top_0_0.in = t0.read_data;
+      t0_addr0 = t0_idx.out;
+      top_0_0.in = t0_read_data;
       top_0_0.write_en = 1'd1;
     }
     static<1> group t1_idx_init {
@@ -159,8 +266,8 @@ component main() -> () {
       t1_idx.write_en = 1'd1;
     }
     static<1> group t1_move {
-      t1.addr0 = t1_idx.out;
-      top_0_1.in = t1.read_data;
+      t1_addr0 = t1_idx.out;
+      top_0_1.in = t1_read_data;
       top_0_1.write_en = 1'd1;
     }
     static<1> group t2_idx_init {
@@ -174,8 +281,8 @@ component main() -> () {
       t2_idx.write_en = 1'd1;
     }
     static<1> group t2_move {
-      t2.addr0 = t2_idx.out;
-      top_0_2.in = t2.read_data;
+      t2_addr0 = t2_idx.out;
+      top_0_2.in = t2_read_data;
       top_0_2.write_en = 1'd1;
     }
     static<1> group l0_idx_init {
@@ -189,8 +296,8 @@ component main() -> () {
       l0_idx.write_en = 1'd1;
     }
     static<1> group l0_move {
-      l0.addr0 = l0_idx.out;
-      left_0_0.in = l0.read_data;
+      l0_addr0 = l0_idx.out;
+      left_0_0.in = l0_read_data;
       left_0_0.write_en = 1'd1;
     }
     static<1> group l1_idx_init {
@@ -204,8 +311,8 @@ component main() -> () {
       l1_idx.write_en = 1'd1;
     }
     static<1> group l1_move {
-      l1.addr0 = l1_idx.out;
-      left_1_0.in = l1.read_data;
+      l1_addr0 = l1_idx.out;
+      left_1_0.in = l1_read_data;
       left_1_0.write_en = 1'd1;
     }
     static<1> group l2_idx_init {
@@ -219,8 +326,8 @@ component main() -> () {
       l2_idx.write_en = 1'd1;
     }
     static<1> group l2_move {
-      l2.addr0 = l2_idx.out;
-      left_2_0.in = l2.read_data;
+      l2_addr0 = l2_idx.out;
+      left_2_0.in = l2_read_data;
       left_2_0.write_en = 1'd1;
     }
     static<1> group pe_0_0_right_move {
@@ -232,9 +339,9 @@ component main() -> () {
       top_1_0.write_en = 1'd1;
     }
     static<1> group pe_0_0_out_write {
-      out_mem_0.addr0 = 2'd0;
-      out_mem_0.write_data = pe_0_0.out;
-      out_mem_0.write_en = 1'd1;
+      out_mem_0_addr0 = 32'd0;
+      out_mem_0_write_data = pe_0_0.out;
+      out_mem_0_write_en = 1'd1;
     }
     static<1> group pe_0_1_right_move {
       left_0_2.in = left_0_1.out;
@@ -245,18 +352,18 @@ component main() -> () {
       top_1_1.write_en = 1'd1;
     }
     static<1> group pe_0_1_out_write {
-      out_mem_0.addr0 = 2'd1;
-      out_mem_0.write_data = pe_0_1.out;
-      out_mem_0.write_en = 1'd1;
+      out_mem_0_addr0 = 32'd1;
+      out_mem_0_write_data = pe_0_1.out;
+      out_mem_0_write_en = 1'd1;
     }
     static<1> group pe_0_2_down_move {
       top_1_2.in = top_0_2.out;
       top_1_2.write_en = 1'd1;
     }
     static<1> group pe_0_2_out_write {
-      out_mem_0.addr0 = 2'd2;
-      out_mem_0.write_data = pe_0_2.out;
-      out_mem_0.write_en = 1'd1;
+      out_mem_0_addr0 = 32'd2;
+      out_mem_0_write_data = pe_0_2.out;
+      out_mem_0_write_en = 1'd1;
     }
     static<1> group pe_1_0_right_move {
       left_1_1.in = left_1_0.out;
@@ -267,9 +374,9 @@ component main() -> () {
       top_2_0.write_en = 1'd1;
     }
     static<1> group pe_1_0_out_write {
-      out_mem_1.addr0 = 2'd0;
-      out_mem_1.write_data = pe_1_0.out;
-      out_mem_1.write_en = 1'd1;
+      out_mem_1_addr0 = 32'd0;
+      out_mem_1_write_data = pe_1_0.out;
+      out_mem_1_write_en = 1'd1;
     }
     static<1> group pe_1_1_right_move {
       left_1_2.in = left_1_1.out;
@@ -280,261 +387,341 @@ component main() -> () {
       top_2_1.write_en = 1'd1;
     }
     static<1> group pe_1_1_out_write {
-      out_mem_1.addr0 = 2'd1;
-      out_mem_1.write_data = pe_1_1.out;
-      out_mem_1.write_en = 1'd1;
+      out_mem_1_addr0 = 32'd1;
+      out_mem_1_write_data = pe_1_1.out;
+      out_mem_1_write_en = 1'd1;
     }
     static<1> group pe_1_2_down_move {
       top_2_2.in = top_1_2.out;
       top_2_2.write_en = 1'd1;
     }
     static<1> group pe_1_2_out_write {
-      out_mem_1.addr0 = 2'd2;
-      out_mem_1.write_data = pe_1_2.out;
-      out_mem_1.write_en = 1'd1;
+      out_mem_1_addr0 = 32'd2;
+      out_mem_1_write_data = pe_1_2.out;
+      out_mem_1_write_en = 1'd1;
     }
     static<1> group pe_2_0_right_move {
       left_2_1.in = left_2_0.out;
       left_2_1.write_en = 1'd1;
     }
     static<1> group pe_2_0_out_write {
-      out_mem_2.addr0 = 2'd0;
-      out_mem_2.write_data = pe_2_0.out;
-      out_mem_2.write_en = 1'd1;
+      out_mem_2_addr0 = 32'd0;
+      out_mem_2_write_data = pe_2_0.out;
+      out_mem_2_write_en = 1'd1;
     }
     static<1> group pe_2_1_right_move {
       left_2_2.in = left_2_1.out;
       left_2_2.write_en = 1'd1;
     }
     static<1> group pe_2_1_out_write {
-      out_mem_2.addr0 = 2'd1;
-      out_mem_2.write_data = pe_2_1.out;
-      out_mem_2.write_en = 1'd1;
+      out_mem_2_addr0 = 32'd1;
+      out_mem_2_write_data = pe_2_1.out;
+      out_mem_2_write_en = 1'd1;
     }
     static<1> group pe_2_2_out_write {
-      out_mem_2.addr0 = 2'd2;
-      out_mem_2.write_data = pe_2_2.out;
-      out_mem_2.write_en = 1'd1;
+      out_mem_2_addr0 = 32'd2;
+      out_mem_2_write_data = pe_2_2.out;
+      out_mem_2_write_en = 1'd1;
     }
     static<1> group init_idx {
-      idx.in = 4'd0;
+      idx.in = 32'd0;
       idx.write_en = 1'd1;
     }
     static<1> group incr_idx {
       idx_add.left = idx.out;
-      idx_add.right = 4'd1;
+      idx_add.right = 32'd1;
       idx.in = idx_add.out;
       idx.write_en = 1'd1;
     }
-    static<1> group idx_between_9_10_group {
-      index_ge_9.left = idx_add.out;
-      index_ge_9.right = 4'd9;
-      index_lt_10.left = idx_add.out;
-      index_lt_10.right = 4'd10;
-      idx_between_9_10_comb.left = index_ge_9.out;
-      idx_between_9_10_comb.right = index_lt_10.out;
-      idx_between_9_10_reg.in = idx_between_9_10_comb.out;
-      idx_between_9_10_reg.write_en = 1'd1;
-    }
-    static<1> group init_idx_between_9_10 {
-      idx_between_9_10_reg.in = 1'd0;
-      idx_between_9_10_reg.write_en = 1'd1;
-    }
-    static<1> group idx_between_10_11_group {
-      index_ge_10.left = idx_add.out;
-      index_ge_10.right = 4'd10;
-      index_lt_11.left = idx_add.out;
-      index_lt_11.right = 4'd11;
-      idx_between_10_11_comb.left = index_ge_10.out;
-      idx_between_10_11_comb.right = index_lt_11.out;
-      idx_between_10_11_reg.in = idx_between_10_11_comb.out;
-      idx_between_10_11_reg.write_en = 1'd1;
-    }
-    static<1> group init_idx_between_10_11 {
-      idx_between_10_11_reg.in = 1'd0;
-      idx_between_10_11_reg.write_en = 1'd1;
-    }
-    static<1> group idx_between_5_8_group {
-      index_ge_5.left = idx_add.out;
-      index_ge_5.right = 4'd5;
-      index_lt_8.left = idx_add.out;
-      index_lt_8.right = 4'd8;
-      idx_between_5_8_comb.left = index_ge_5.out;
-      idx_between_5_8_comb.right = index_lt_8.out;
-      idx_between_5_8_reg.in = idx_between_5_8_comb.out;
-      idx_between_5_8_reg.write_en = 1'd1;
-    }
-    static<1> group init_idx_between_5_8 {
-      idx_between_5_8_reg.in = 1'd0;
-      idx_between_5_8_reg.write_en = 1'd1;
-    }
-    static<1> group idx_between_7_10_group {
+    static<1> group lt_iter_limit_group {
+      lt_iter_limit.left = idx_add.out;
+      lt_iter_limit.right = iter_limit.out;
+      cond_reg.in = lt_iter_limit.out;
+      cond_reg.write_en = 1'd1;
+    }
+    static<1> group init_cond_reg {
+      cond_reg.in = 1'd1;
+      cond_reg.write_en = 1'd1;
+    }
+    static<1> group idx_between_depth_plus_8_depth_plus_9_group {
+      index_ge_depth_plus_8.left = idx_add.out;
+      index_ge_depth_plus_8.right = depth_plus_8.out;
+      index_lt_depth_plus_9.left = idx_add.out;
+      index_lt_depth_plus_9.right = depth_plus_9.out;
+      idx_between_depth_plus_8_depth_plus_9_comb.left = index_ge_depth_plus_8.out;
+      idx_between_depth_plus_8_depth_plus_9_comb.right = index_lt_depth_plus_9.out;
+      idx_between_depth_plus_8_depth_plus_9_reg.in = idx_between_depth_plus_8_depth_plus_9_comb.out;
+      idx_between_depth_plus_8_depth_plus_9_reg.write_en = 1'd1;
+    }
+    static<1> group init_idx_between_depth_plus_8_depth_plus_9 {
+      idx_between_depth_plus_8_depth_plus_9_reg.in = 1'd0;
+      idx_between_depth_plus_8_depth_plus_9_reg.write_en = 1'd1;
+    }
+    static<1> group idx_between_2_min_depth_4_plus_2_group {
+      index_ge_2.left = idx_add.out;
+      index_ge_2.right = 32'd2;
+      index_lt_min_depth_4_plus_2.left = idx_add.out;
+      index_lt_min_depth_4_plus_2.right = min_depth_4_plus_2.out;
+      idx_between_2_min_depth_4_plus_2_comb.left = index_ge_2.out;
+      idx_between_2_min_depth_4_plus_2_comb.right = index_lt_min_depth_4_plus_2.out;
+      idx_between_2_min_depth_4_plus_2_reg.in = idx_between_2_min_depth_4_plus_2_comb.out;
+      idx_between_2_min_depth_4_plus_2_reg.write_en = 1'd1;
+    }
+    static<1> group init_idx_between_2_min_depth_4_plus_2 {
+      idx_between_2_min_depth_4_plus_2_reg.in = 1'd0;
+      idx_between_2_min_depth_4_plus_2_reg.write_en = 1'd1;
+    }
+    static<1> group idx_between_2_depth_plus_2_group {
+      index_ge_2.left = idx_add.out;
+      index_ge_2.right = 32'd2;
+      index_lt_depth_plus_2.left = idx_add.out;
+      index_lt_depth_plus_2.right = depth_plus_2.out;
+      idx_between_2_depth_plus_2_comb.left = index_ge_2.out;
+      idx_between_2_depth_plus_2_comb.right = index_lt_depth_plus_2.out;
+      idx_between_2_depth_plus_2_reg.in = idx_between_2_depth_plus_2_comb.out;
+      idx_between_2_depth_plus_2_reg.write_en = 1'd1;
+    }
+    static<1> group init_idx_between_2_depth_plus_2 {
+      idx_between_2_depth_plus_2_reg.in = 1'd0;
+      idx_between_2_depth_plus_2_reg.write_en = 1'd1;
+    }
+    static<1> group idx_between_7_depth_plus_7_group {
       index_ge_7.left = idx_add.out;
-      index_ge_7.right = 4'd7;
-      index_lt_10.left = idx_add.out;
-      index_lt_10.right = 4'd10;
-      idx_between_7_10_comb.left = index_ge_7.out;
-      idx_between_7_10_comb.right = index_lt_10.out;
-      idx_between_7_10_reg.in = idx_between_7_10_comb.out;
-      idx_between_7_10_reg.write_en = 1'd1;
-    }
-    static<1> group init_idx_between_7_10 {
-      idx_between_7_10_reg.in = 1'd0;
-      idx_between_7_10_reg.write_en = 1'd1;
-    }
-    static<1> group idx_between_0_3_group {
-      index_lt_3.left = idx_add.out;
-      index_lt_3.right = 4'd3;
-      idx_between_0_3_reg.in = index_lt_3.out;
-      idx_between_0_3_reg.write_en = 1'd1;
-    }
-    static<1> group init_idx_between_0_3 {
-      idx_between_0_3_reg.in = 1'd1;
-      idx_between_0_3_reg.write_en = 1'd1;
-    }
-    static<1> group idx_between_9_12_group {
+      index_ge_7.right = 32'd7;
+      index_lt_depth_plus_7.left = idx_add.out;
+      index_lt_depth_plus_7.right = depth_plus_7.out;
+      idx_between_7_depth_plus_7_comb.left = index_ge_7.out;
+      idx_between_7_depth_plus_7_comb.right = index_lt_depth_plus_7.out;
+      idx_between_7_depth_plus_7_reg.in = idx_between_7_depth_plus_7_comb.out;
+      idx_between_7_depth_plus_7_reg.write_en = 1'd1;
+    }
+    static<1> group init_idx_between_7_depth_plus_7 {
+      idx_between_7_depth_plus_7_reg.in = 1'd0;
+      idx_between_7_depth_plus_7_reg.write_en = 1'd1;
+    }
+    static<1> group idx_between_3_depth_plus_3_group {
+      index_ge_3.left = idx_add.out;
+      index_ge_3.right = 32'd3;
+      index_lt_depth_plus_3.left = idx_add.out;
+      index_lt_depth_plus_3.right = depth_plus_3.out;
+      idx_between_3_depth_plus_3_comb.left = index_ge_3.out;
+      idx_between_3_depth_plus_3_comb.right = index_lt_depth_plus_3.out;
+      idx_between_3_depth_plus_3_reg.in = idx_between_3_depth_plus_3_comb.out;
+      idx_between_3_depth_plus_3_reg.write_en = 1'd1;
+    }
+    static<1> group init_idx_between_3_depth_plus_3 {
+      idx_between_3_depth_plus_3_reg.in = 1'd0;
+      idx_between_3_depth_plus_3_reg.write_en = 1'd1;
+    }
+    static<1> group idx_between_3_min_depth_4_plus_3_group {
+      index_ge_3.left = idx_add.out;
+      index_ge_3.right = 32'd3;
+      index_lt_min_depth_4_plus_3.left = idx_add.out;
+      index_lt_min_depth_4_plus_3.right = min_depth_4_plus_3.out;
+      idx_between_3_min_depth_4_plus_3_comb.left = index_ge_3.out;
+      idx_between_3_min_depth_4_plus_3_comb.right = index_lt_min_depth_4_plus_3.out;
+      idx_between_3_min_depth_4_plus_3_reg.in = idx_between_3_min_depth_4_plus_3_comb.out;
+      idx_between_3_min_depth_4_plus_3_reg.write_en = 1'd1;
+    }
+    static<1> group init_idx_between_3_min_depth_4_plus_3 {
+      idx_between_3_min_depth_4_plus_3_reg.in = 1'd0;
+      idx_between_3_min_depth_4_plus_3_reg.write_en = 1'd1;
+    }
+    static<1> group idx_between_depth_plus_5_depth_plus_6_group {
+      index_ge_depth_plus_5.left = idx_add.out;
+      index_ge_depth_plus_5.right = depth_plus_5.out;
+      index_lt_depth_plus_6.left = idx_add.out;
+      index_lt_depth_plus_6.right = depth_plus_6.out;
+      idx_between_depth_plus_5_depth_plus_6_comb.left = index_ge_depth_plus_5.out;
+      idx_between_depth_plus_5_depth_plus_6_comb.right = index_lt_depth_plus_6.out;
+      idx_between_depth_plus_5_depth_plus_6_reg.in = idx_between_depth_plus_5_depth_plus_6_comb.out;
+      idx_between_depth_plus_5_depth_plus_6_reg.write_en = 1'd1;
+    }
+    static<1> group init_idx_between_depth_plus_5_depth_plus_6 {
+      idx_between_depth_plus_5_depth_plus_6_reg.in = 1'd0;
+      idx_between_depth_plus_5_depth_plus_6_reg.write_en = 1'd1;
+    }
+    static<1> group idx_between_depth_plus_9_depth_plus_10_group {
+      index_ge_depth_plus_9.left = idx_add.out;
+      index_ge_depth_plus_9.right = depth_plus_9.out;
+      index_lt_depth_plus_10.left = idx_add.out;
+      index_lt_depth_plus_10.right = depth_plus_10.out;
+      idx_between_depth_plus_9_depth_plus_10_comb.left = index_ge_depth_plus_9.out;
+      idx_between_depth_plus_9_depth_plus_10_comb.right = index_lt_depth_plus_10.out;
+      idx_between_depth_plus_9_depth_plus_10_reg.in = idx_between_depth_plus_9_depth_plus_10_comb.out;
+      idx_between_depth_plus_9_depth_plus_10_reg.write_en = 1'd1;
+    }
+    static<1> group init_idx_between_depth_plus_9_depth_plus_10 {
+      idx_between_depth_plus_9_depth_plus_10_reg.in = 1'd0;
+      idx_between_depth_plus_9_depth_plus_10_reg.write_en = 1'd1;
+    }
+    static<1> group idx_between_8_depth_plus_8_group {
+      index_ge_8.left = idx_add.out;
+      index_ge_8.right = 32'd8;
+      index_lt_depth_plus_8.left = idx_add.out;
+      index_lt_depth_plus_8.right = depth_plus_8.out;
+      idx_between_8_depth_plus_8_comb.left = index_ge_8.out;
+      idx_between_8_depth_plus_8_comb.right = index_lt_depth_plus_8.out;
+      idx_between_8_depth_plus_8_reg.in = idx_between_8_depth_plus_8_comb.out;
+      idx_between_8_depth_plus_8_reg.write_en = 1'd1;
+    }
+    static<1> group init_idx_between_8_depth_plus_8 {
+      idx_between_8_depth_plus_8_reg.in = 1'd0;
+      idx_between_8_depth_plus_8_reg.write_en = 1'd1;
+    }
+    static<1> group idx_between_depth_plus_6_depth_plus_7_group {
+      index_ge_depth_plus_6.left = idx_add.out;
+      index_ge_depth_plus_6.right = depth_plus_6.out;
+      index_lt_depth_plus_7.left = idx_add.out;
+      index_lt_depth_plus_7.right = depth_plus_7.out;
+      idx_between_depth_plus_6_depth_plus_7_comb.left = index_ge_depth_plus_6.out;
+      idx_between_depth_plus_6_depth_plus_7_comb.right = index_lt_depth_plus_7.out;
+      idx_between_depth_plus_6_depth_plus_7_reg.in = idx_between_depth_plus_6_depth_plus_7_comb.out;
+      idx_between_depth_plus_6_depth_plus_7_reg.write_en = 1'd1;
+    }
+    static<1> group init_idx_between_depth_plus_6_depth_plus_7 {
+      idx_between_depth_plus_6_depth_plus_7_reg.in = 1'd0;
+      idx_between_depth_plus_6_depth_plus_7_reg.write_en = 1'd1;
+    }
+    static<1> group idx_between_4_depth_plus_4_group {
+      index_ge_4.left = idx_add.out;
+      index_ge_4.right = 32'd4;
+      index_lt_depth_plus_4.left = idx_add.out;
+      index_lt_depth_plus_4.right = depth_plus_4.out;
+      idx_between_4_depth_plus_4_comb.left = index_ge_4.out;
+      idx_between_4_depth_plus_4_comb.right = index_lt_depth_plus_4.out;
+      idx_between_4_depth_plus_4_reg.in = idx_between_4_depth_plus_4_comb.out;
+      idx_between_4_depth_plus_4_reg.write_en = 1'd1;
+    }
+    static<1> group init_idx_between_4_depth_plus_4 {
+      idx_between_4_depth_plus_4_reg.in = 1'd0;
+      idx_between_4_depth_plus_4_reg.write_en = 1'd1;
+    }
+    static<1> group idx_between_4_min_depth_4_plus_4_group {
+      index_ge_4.left = idx_add.out;
+      index_ge_4.right = 32'd4;
+      index_lt_min_depth_4_plus_4.left = idx_add.out;
+      index_lt_min_depth_4_plus_4.right = min_depth_4_plus_4.out;
+      idx_between_4_min_depth_4_plus_4_comb.left = index_ge_4.out;
+      idx_between_4_min_depth_4_plus_4_comb.right = index_lt_min_depth_4_plus_4.out;
+      idx_between_4_min_depth_4_plus_4_reg.in = idx_between_4_min_depth_4_plus_4_comb.out;
+      idx_between_4_min_depth_4_plus_4_reg.write_en = 1'd1;
+    }
+    static<1> group init_idx_between_4_min_depth_4_plus_4 {
+      idx_between_4_min_depth_4_plus_4_reg.in = 1'd0;
+      idx_between_4_min_depth_4_plus_4_reg.write_en = 1'd1;
+    }
+    static<1> group idx_between_5_min_depth_4_plus_5_group {
+      index_ge_5.left = idx_add.out;
+      index_ge_5.right = 32'd5;
+      index_lt_min_depth_4_plus_5.left = idx_add.out;
+      index_lt_min_depth_4_plus_5.right = min_depth_4_plus_5.out;
+      idx_between_5_min_depth_4_plus_5_comb.left = index_ge_5.out;
+      idx_between_5_min_depth_4_plus_5_comb.right = index_lt_min_depth_4_plus_5.out;
+      idx_between_5_min_depth_4_plus_5_reg.in = idx_between_5_min_depth_4_plus_5_comb.out;
+      idx_between_5_min_depth_4_plus_5_reg.write_en = 1'd1;
+    }
+    static<1> group init_idx_between_5_min_depth_4_plus_5 {
+      idx_between_5_min_depth_4_plus_5_reg.in = 1'd0;
+      idx_between_5_min_depth_4_plus_5_reg.write_en = 1'd1;
+    }
+    static<1> group idx_between_5_depth_plus_5_group {
+      index_ge_5.left = idx_add.out;
+      index_ge_5.right = 32'd5;
+      index_lt_depth_plus_5.left = idx_add.out;
+      index_lt_depth_plus_5.right = depth_plus_5.out;
+      idx_between_5_depth_plus_5_comb.left = index_ge_5.out;
+      idx_between_5_depth_plus_5_comb.right = index_lt_depth_plus_5.out;
+      idx_between_5_depth_plus_5_reg.in = idx_between_5_depth_plus_5_comb.out;
+      idx_between_5_depth_plus_5_reg.write_en = 1'd1;
+    }
+    static<1> group init_idx_between_5_depth_plus_5 {
+      idx_between_5_depth_plus_5_reg.in = 1'd0;
+      idx_between_5_depth_plus_5_reg.write_en = 1'd1;
+    }
+    static<1> group idx_between_0_depth_plus_0_group {
+      index_lt_depth_plus_0.left = idx_add.out;
+      index_lt_depth_plus_0.right = depth_plus_0.out;
+      idx_between_0_depth_plus_0_reg.in = index_lt_depth_plus_0.out;
+      idx_between_0_depth_plus_0_reg.write_en = 1'd1;
+    }
+    static<1> group init_idx_between_0_depth_plus_0 {
+      idx_between_0_depth_plus_0_reg.in = 1'd1;
+      idx_between_0_depth_plus_0_reg.write_en = 1'd1;
+    }
+    static<1> group idx_between_9_depth_plus_9_group {
       index_ge_9.left = idx_add.out;
-      index_ge_9.right = 4'd9;
-      index_lt_12.left = idx_add.out;
-      index_lt_12.right = 4'd12;
-      idx_between_9_12_comb.left = index_ge_9.out;
-      idx_between_9_12_comb.right = index_lt_12.out;
-      idx_between_9_12_reg.in = idx_between_9_12_comb.out;
-      idx_between_9_12_reg.write_en = 1'd1;
-    }
-    static<1> group init_idx_between_9_12 {
-      idx_between_9_12_reg.in = 1'd0;
-      idx_between_9_12_reg.write_en = 1'd1;
-    }
-    static<1> group idx_between_12_13_group {
-      index_ge_12.left = idx_add.out;
-      index_ge_12.right = 4'd12;
-      index_lt_13.left = idx_add.out;
-      index_lt_13.right = 4'd13;
-      idx_between_12_13_comb.left = index_ge_12.out;
-      idx_between_12_13_comb.right = index_lt_13.out;
-      idx_between_12_13_reg.in = idx_between_12_13_comb.out;
-      idx_between_12_13_reg.write_en = 1'd1;
-    }
-    static<1> group init_idx_between_12_13 {
-      idx_between_12_13_reg.in = 1'd0;
-      idx_between_12_13_reg.write_en = 1'd1;
-    }
-    static<1> group idx_between_1_4_group {
+      index_ge_9.right = 32'd9;
+      index_lt_depth_plus_9.left = idx_add.out;
+      index_lt_depth_plus_9.right = depth_plus_9.out;
+      idx_between_9_depth_plus_9_comb.left = index_ge_9.out;
+      idx_between_9_depth_plus_9_comb.right = index_lt_depth_plus_9.out;
+      idx_between_9_depth_plus_9_reg.in = idx_between_9_depth_plus_9_comb.out;
+      idx_between_9_depth_plus_9_reg.write_en = 1'd1;
+    }
+    static<1> group init_idx_between_9_depth_plus_9 {
+      idx_between_9_depth_plus_9_reg.in = 1'd0;
+      idx_between_9_depth_plus_9_reg.write_en = 1'd1;
+    }
+    static<1> group idx_between_1_depth_plus_1_group {
       index_ge_1.left = idx_add.out;
-      index_ge_1.right = 4'd1;
-      index_lt_4.left = idx_add.out;
-      index_lt_4.right = 4'd4;
-      idx_between_1_4_comb.left = index_ge_1.out;
-      idx_between_1_4_comb.right = index_lt_4.out;
-      idx_between_1_4_reg.in = idx_between_1_4_comb.out;
-      idx_between_1_4_reg.write_en = 1'd1;
-    }
-    static<1> group init_idx_between_1_4 {
-      idx_between_1_4_reg.in = 1'd0;
-      idx_between_1_4_reg.write_en = 1'd1;
-    }
-    static<1> group idx_between_11_12_group {
-      index_ge_11.left = idx_add.out;
-      index_ge_11.right = 4'd11;
-      index_lt_12.left = idx_add.out;
-      index_lt_12.right = 4'd12;
-      idx_between_11_12_comb.left = index_ge_11.out;
-      idx_between_11_12_comb.right = index_lt_12.out;
-      idx_between_11_12_reg.in = idx_between_11_12_comb.out;
-      idx_between_11_12_reg.write_en = 1'd1;
-    }
-    static<1> group init_idx_between_11_12 {
-      idx_between_11_12_reg.in = 1'd0;
-      idx_between_11_12_reg.write_en = 1'd1;
-    }
-    static<1> group idx_between_8_9_group {
-      index_ge_8.left = idx_add.out;
-      index_ge_8.right = 4'd8;
-      index_lt_9.left = idx_add.out;
-      index_lt_9.right = 4'd9;
-      idx_between_8_9_comb.left = index_ge_8.out;
-      idx_between_8_9_comb.right = index_lt_9.out;
-      idx_between_8_9_reg.in = idx_between_8_9_comb.out;
-      idx_between_8_9_reg.write_en = 1'd1;
-    }
-    static<1> group init_idx_between_8_9 {
-      idx_between_8_9_reg.in = 1'd0;
-      idx_between_8_9_reg.write_en = 1'd1;
-    }
-    static<1> group idx_between_3_6_group {
-      index_ge_3.left = idx_add.out;
-      index_ge_3.right = 4'd3;
-      index_lt_6.left = idx_add.out;
-      index_lt_6.right = 4'd6;
-      idx_between_3_6_comb.left = index_ge_3.out;
-      idx_between_3_6_comb.right = index_lt_6.out;
-      idx_between_3_6_reg.in = idx_between_3_6_comb.out;
-      idx_between_3_6_reg.write_en = 1'd1;
-    }
-    static<1> group init_idx_between_3_6 {
-      idx_between_3_6_reg.in = 1'd0;
-      idx_between_3_6_reg.write_en = 1'd1;
-    }
-    static<1> group idx_between_2_5_group {
-      index_ge_2.left = idx_add.out;
-      index_ge_2.right = 4'd2;
-      index_lt_5.left = idx_add.out;
-      index_lt_5.right = 4'd5;
-      idx_between_2_5_comb.left = index_ge_2.out;
-      idx_between_2_5_comb.right = index_lt_5.out;
-      idx_between_2_5_reg.in = idx_between_2_5_comb.out;
-      idx_between_2_5_reg.write_en = 1'd1;
-    }
-    static<1> group init_idx_between_2_5 {
-      idx_between_2_5_reg.in = 1'd0;
-      idx_between_2_5_reg.write_en = 1'd1;
-    }
-    static<1> group idx_between_6_9_group {
+      index_ge_1.right = 32'd1;
+      index_lt_depth_plus_1.left = idx_add.out;
+      index_lt_depth_plus_1.right = depth_plus_1.out;
+      idx_between_1_depth_plus_1_comb.left = index_ge_1.out;
+      idx_between_1_depth_plus_1_comb.right = index_lt_depth_plus_1.out;
+      idx_between_1_depth_plus_1_reg.in = idx_between_1_depth_plus_1_comb.out;
+      idx_between_1_depth_plus_1_reg.write_en = 1'd1;
+    }
+    static<1> group init_idx_between_1_depth_plus_1 {
+      idx_between_1_depth_plus_1_reg.in = 1'd0;
+      idx_between_1_depth_plus_1_reg.write_en = 1'd1;
+    }
+    static<1> group idx_between_1_min_depth_4_plus_1_group {
+      index_ge_1.left = idx_add.out;
+      index_ge_1.right = 32'd1;
+      index_lt_min_depth_4_plus_1.left = idx_add.out;
+      index_lt_min_depth_4_plus_1.right = min_depth_4_plus_1.out;
+      idx_between_1_min_depth_4_plus_1_comb.left = index_ge_1.out;
+      idx_between_1_min_depth_4_plus_1_comb.right = index_lt_min_depth_4_plus_1.out;
+      idx_between_1_min_depth_4_plus_1_reg.in = idx_between_1_min_depth_4_plus_1_comb.out;
+      idx_between_1_min_depth_4_plus_1_reg.write_en = 1'd1;
+    }
+    static<1> group init_idx_between_1_min_depth_4_plus_1 {
+      idx_between_1_min_depth_4_plus_1_reg.in = 1'd0;
+      idx_between_1_min_depth_4_plus_1_reg.write_en = 1'd1;
+    }
+    static<1> group idx_between_6_depth_plus_6_group {
       index_ge_6.left = idx_add.out;
-      index_ge_6.right = 4'd6;
-      index_lt_9.left = idx_add.out;
-      index_lt_9.right = 4'd9;
-      idx_between_6_9_comb.left = index_ge_6.out;
-      idx_between_6_9_comb.right = index_lt_9.out;
-      idx_between_6_9_reg.in = idx_between_6_9_comb.out;
-      idx_between_6_9_reg.write_en = 1'd1;
-    }
-    static<1> group init_idx_between_6_9 {
-      idx_between_6_9_reg.in = 1'd0;
-      idx_between_6_9_reg.write_en = 1'd1;
-    }
-    static<1> group idx_between_4_7_group {
-      index_ge_4.left = idx_add.out;
-      index_ge_4.right = 4'd4;
-      index_lt_7.left = idx_add.out;
-      index_lt_7.right = 4'd7;
-      idx_between_4_7_comb.left = index_ge_4.out;
-      idx_between_4_7_comb.right = index_lt_7.out;
-      idx_between_4_7_reg.in = idx_between_4_7_comb.out;
-      idx_between_4_7_reg.write_en = 1'd1;
-    }
-    static<1> group init_idx_between_4_7 {
-      idx_between_4_7_reg.in = 1'd0;
-      idx_between_4_7_reg.write_en = 1'd1;
-    }
-    static<1> group idx_between_8_11_group {
-      index_ge_8.left = idx_add.out;
-      index_ge_8.right = 4'd8;
-      index_lt_11.left = idx_add.out;
-      index_lt_11.right = 4'd11;
-      idx_between_8_11_comb.left = index_ge_8.out;
-      idx_between_8_11_comb.right = index_lt_11.out;
-      idx_between_8_11_reg.in = idx_between_8_11_comb.out;
-      idx_between_8_11_reg.write_en = 1'd1;
-    }
-    static<1> group init_idx_between_8_11 {
-      idx_between_8_11_reg.in = 1'd0;
-      idx_between_8_11_reg.write_en = 1'd1;
+      index_ge_6.right = 32'd6;
+      index_lt_depth_plus_6.left = idx_add.out;
+      index_lt_depth_plus_6.right = depth_plus_6.out;
+      idx_between_6_depth_plus_6_comb.left = index_ge_6.out;
+      idx_between_6_depth_plus_6_comb.right = index_lt_depth_plus_6.out;
+      idx_between_6_depth_plus_6_reg.in = idx_between_6_depth_plus_6_comb.out;
+      idx_between_6_depth_plus_6_reg.write_en = 1'd1;
+    }
+    static<1> group init_idx_between_6_depth_plus_6 {
+      idx_between_6_depth_plus_6_reg.in = 1'd0;
+      idx_between_6_depth_plus_6_reg.write_en = 1'd1;
+    }
+    static<1> group idx_between_depth_plus_7_depth_plus_8_group {
+      index_ge_depth_plus_7.left = idx_add.out;
+      index_ge_depth_plus_7.right = depth_plus_7.out;
+      index_lt_depth_plus_8.left = idx_add.out;
+      index_lt_depth_plus_8.right = depth_plus_8.out;
+      idx_between_depth_plus_7_depth_plus_8_comb.left = index_ge_depth_plus_7.out;
+      idx_between_depth_plus_7_depth_plus_8_comb.right = index_lt_depth_plus_8.out;
+      idx_between_depth_plus_7_depth_plus_8_reg.in = idx_between_depth_plus_7_depth_plus_8_comb.out;
+      idx_between_depth_plus_7_depth_plus_8_reg.write_en = 1'd1;
+    }
+    static<1> group init_idx_between_depth_plus_7_depth_plus_8 {
+      idx_between_depth_plus_7_depth_plus_8_reg.in = 1'd0;
+      idx_between_depth_plus_7_depth_plus_8_reg.write_en = 1'd1;
     }
   }
   control {
-    static seq {
+    seq {
       static par {
         t0_idx_init;
         t1_idx_init;
@@ -543,27 +730,35 @@ component main() -> () {
         l1_idx_init;
         l2_idx_init;
         init_idx;
-        init_idx_between_9_10;
-        init_idx_between_10_11;
-        init_idx_between_5_8;
-        init_idx_between_7_10;
-        init_idx_between_0_3;
-        init_idx_between_9_12;
-        init_idx_between_12_13;
-        init_idx_between_1_4;
-        init_idx_between_11_12;
-        init_idx_between_8_9;
-        init_idx_between_3_6;
-        init_idx_between_2_5;
-        init_idx_between_6_9;
-        init_idx_between_4_7;
-        init_idx_between_8_11;
+        init_min_depth;
+        init_iter_limit;
+        init_cond_reg;
+        init_idx_between_depth_plus_8_depth_plus_9;
+        init_idx_between_2_min_depth_4_plus_2;
+        init_idx_between_2_depth_plus_2;
+        init_idx_between_7_depth_plus_7;
+        init_idx_between_3_depth_plus_3;
+        init_idx_between_3_min_depth_4_plus_3;
+        init_idx_between_depth_plus_5_depth_plus_6;
+        init_idx_between_depth_plus_9_depth_plus_10;
+        init_idx_between_8_depth_plus_8;
+        init_idx_between_depth_plus_6_depth_plus_7;
+        init_idx_between_4_depth_plus_4;
+        init_idx_between_4_min_depth_4_plus_4;
+        init_idx_between_5_min_depth_4_plus_5;
+        init_idx_between_5_depth_plus_5;
+        init_idx_between_0_depth_plus_0;
+        init_idx_between_9_depth_plus_9;
+        init_idx_between_1_depth_plus_1;
+        init_idx_between_1_min_depth_4_plus_1;
+        init_idx_between_6_depth_plus_6;
+        init_idx_between_depth_plus_7_depth_plus_8;
       }
-      static repeat 13 {
+      while cond_reg.out {
         static par {
           static par {
             static par {
-              static if idx_between_0_3_reg.out {
+              static if idx_between_0_depth_plus_0_reg.out {
                 static par {
                   l0_move;
                   l0_idx_update;
@@ -571,221 +766,221 @@ component main() -> () {
                   t0_idx_update;
                 }
               }
-              static if idx_between_1_4_reg.out {
+              static if idx_between_1_min_depth_4_plus_1_reg.out {
                 static par {
                   static invoke pe_0_0(top=top_0_0.out, left=left_0_0.out, mul_ready=1'd0)();
                 }
               }
-              static if idx_between_1_4_reg.out {
+              static if idx_between_1_depth_plus_1_reg.out {
                 static par {
                   pe_0_0_down_move;
                   pe_0_0_right_move;
                 }
               }
-              static if idx_between_5_8_reg.out {
+              static if idx_between_5_depth_plus_5_reg.out {
                 static par {
                   static invoke pe_0_0(top=top_0_0.out, left=left_0_0.out, mul_ready=1'd1)();
                 }
               }
-              static if idx_between_8_9_reg.out {
+              static if idx_between_depth_plus_5_depth_plus_6_reg.out {
                 static par {
                   pe_0_0_out_write;
                 }
               }
             }
             static par {
-              static if idx_between_1_4_reg.out {
+              static if idx_between_1_depth_plus_1_reg.out {
                 static par {
                   t1_move;
                   t1_idx_update;
                 }
               }
-              static if idx_between_2_5_reg.out {
+              static if idx_between_2_min_depth_4_plus_2_reg.out {
                 static par {
                   static invoke pe_0_1(top=top_0_1.out, left=left_0_1.out, mul_ready=1'd0)();
                 }
               }
-              static if idx_between_2_5_reg.out {
+              static if idx_between_2_depth_plus_2_reg.out {
                 static par {
                   pe_0_1_down_move;
                   pe_0_1_right_move;
                 }
               }
-              static if idx_between_6_9_reg.out {
+              static if idx_between_6_depth_plus_6_reg.out {
                 static par {
                   static invoke pe_0_1(top=top_0_1.out, left=left_0_1.out, mul_ready=1'd1)();
                 }
               }
-              static if idx_between_9_10_reg.out {
+              static if idx_between_depth_plus_6_depth_plus_7_reg.out {
                 static par {
                   pe_0_1_out_write;
                 }
               }
             }
             static par {
-              static if idx_between_2_5_reg.out {
+              static if idx_between_2_depth_plus_2_reg.out {
                 static par {
                   t2_move;
                   t2_idx_update;
                 }
               }
-              static if idx_between_3_6_reg.out {
+              static if idx_between_3_min_depth_4_plus_3_reg.out {
                 static par {
                   static invoke pe_0_2(top=top_0_2.out, left=left_0_2.out, mul_ready=1'd0)();
                 }
               }
-              static if idx_between_3_6_reg.out {
+              static if idx_between_3_depth_plus_3_reg.out {
                 static par {
                   pe_0_2_down_move;
                 }
               }
-              static if idx_between_7_10_reg.out {
+              static if idx_between_7_depth_plus_7_reg.out {
                 static par {
                   static invoke pe_0_2(top=top_0_2.out, left=left_0_2.out, mul_ready=1'd1)();
                 }
               }
-              static if idx_between_10_11_reg.out {
+              static if idx_between_depth_plus_7_depth_plus_8_reg.out {
                 static par {
                   pe_0_2_out_write;
                 }
               }
             }
             static par {
-              static if idx_between_1_4_reg.out {
+              static if idx_between_1_depth_plus_1_reg.out {
                 static par {
                   l1_move;
                   l1_idx_update;
                 }
               }
-              static if idx_between_2_5_reg.out {
+              static if idx_between_2_min_depth_4_plus_2_reg.out {
                 static par {
                   static invoke pe_1_0(top=top_1_0.out, left=left_1_0.out, mul_ready=1'd0)();
                 }
               }
-              static if idx_between_2_5_reg.out {
+              static if idx_between_2_depth_plus_2_reg.out {
                 static par {
                   pe_1_0_down_move;
                   pe_1_0_right_move;
                 }
               }
-              static if idx_between_6_9_reg.out {
+              static if idx_between_6_depth_plus_6_reg.out {
                 static par {
                   static invoke pe_1_0(top=top_1_0.out, left=left_1_0.out, mul_ready=1'd1)();
                 }
               }
-              static if idx_between_9_10_reg.out {
+              static if idx_between_depth_plus_6_depth_plus_7_reg.out {
                 static par {
                   pe_1_0_out_write;
                 }
               }
             }
             static par {
-              static if idx_between_3_6_reg.out {
+              static if idx_between_3_min_depth_4_plus_3_reg.out {
                 static par {
                   static invoke pe_1_1(top=top_1_1.out, left=left_1_1.out, mul_ready=1'd0)();
                 }
               }
-              static if idx_between_3_6_reg.out {
+              static if idx_between_3_depth_plus_3_reg.out {
                 static par {
                   pe_1_1_down_move;
                   pe_1_1_right_move;
                 }
               }
-              static if idx_between_7_10_reg.out {
+              static if idx_between_7_depth_plus_7_reg.out {
                 static par {
                   static invoke pe_1_1(top=top_1_1.out, left=left_1_1.out, mul_ready=1'd1)();
                 }
               }
-              static if idx_between_10_11_reg.out {
+              static if idx_between_depth_plus_7_depth_plus_8_reg.out {
                 static par {
                   pe_1_1_out_write;
                 }
               }
             }
             static par {
-              static if idx_between_4_7_reg.out {
+              static if idx_between_4_min_depth_4_plus_4_reg.out {
                 static par {
                   static invoke pe_1_2(top=top_1_2.out, left=left_1_2.out, mul_ready=1'd0)();
                 }
               }
-              static if idx_between_4_7_reg.out {
+              static if idx_between_4_depth_plus_4_reg.out {
                 static par {
                   pe_1_2_down_move;
                 }
               }
-              static if idx_between_8_11_reg.out {
+              static if idx_between_8_depth_plus_8_reg.out {
                 static par {
                   static invoke pe_1_2(top=top_1_2.out, left=left_1_2.out, mul_ready=1'd1)();
                 }
               }
-              static if idx_between_11_12_reg.out {
+              static if idx_between_depth_plus_8_depth_plus_9_reg.out {
                 static par {
                   pe_1_2_out_write;
                 }
               }
             }
             static par {
-              static if idx_between_2_5_reg.out {
+              static if idx_between_2_depth_plus_2_reg.out {
                 static par {
                   l2_move;
                   l2_idx_update;
                 }
               }
-              static if idx_between_3_6_reg.out {
+              static if idx_between_3_min_depth_4_plus_3_reg.out {
                 static par {
                   static invoke pe_2_0(top=top_2_0.out, left=left_2_0.out, mul_ready=1'd0)();
                 }
               }
-              static if idx_between_3_6_reg.out {
+              static if idx_between_3_depth_plus_3_reg.out {
                 static par {
                   pe_2_0_right_move;
                 }
               }
-              static if idx_between_7_10_reg.out {
+              static if idx_between_7_depth_plus_7_reg.out {
                 static par {
                   static invoke pe_2_0(top=top_2_0.out, left=left_2_0.out, mul_ready=1'd1)();
                 }
               }
-              static if idx_between_10_11_reg.out {
+              static if idx_between_depth_plus_7_depth_plus_8_reg.out {
                 static par {
                   pe_2_0_out_write;
                 }
               }
             }
             static par {
-              static if idx_between_4_7_reg.out {
+              static if idx_between_4_min_depth_4_plus_4_reg.out {
                 static par {
                   static invoke pe_2_1(top=top_2_1.out, left=left_2_1.out, mul_ready=1'd0)();
                 }
               }
-              static if idx_between_4_7_reg.out {
+              static if idx_between_4_depth_plus_4_reg.out {
                 static par {
                   pe_2_1_right_move;
                 }
               }
-              static if idx_between_8_11_reg.out {
+              static if idx_between_8_depth_plus_8_reg.out {
                 static par {
                   static invoke pe_2_1(top=top_2_1.out, left=left_2_1.out, mul_ready=1'd1)();
                 }
               }
-              static if idx_between_11_12_reg.out {
+              static if idx_between_depth_plus_8_depth_plus_9_reg.out {
                 static par {
                   pe_2_1_out_write;
                 }
               }
             }
             static par {
-              static if idx_between_5_8_reg.out {
+              static if idx_between_5_min_depth_4_plus_5_reg.out {
                 static par {
                   static invoke pe_2_2(top=top_2_2.out, left=left_2_2.out, mul_ready=1'd0)();
                 }
               }
-              static if idx_between_9_12_reg.out {
+              static if idx_between_9_depth_plus_9_reg.out {
                 static par {
                   static invoke pe_2_2(top=top_2_2.out, left=left_2_2.out, mul_ready=1'd1)();
                 }
               }
-              static if idx_between_12_13_reg.out {
+              static if idx_between_depth_plus_9_depth_plus_10_reg.out {
                 static par {
                   pe_2_2_out_write;
                 }
@@ -794,35 +989,77 @@ component main() -> () {
           }
           static par {
             incr_idx;
-            idx_between_9_10_group;
-            idx_between_10_11_group;
-            idx_between_5_8_group;
-            idx_between_7_10_group;
-            idx_between_0_3_group;
-            idx_between_9_12_group;
-            idx_between_12_13_group;
-            idx_between_1_4_group;
-            idx_between_11_12_group;
-            idx_between_8_9_group;
-            idx_between_3_6_group;
-            idx_between_2_5_group;
-            idx_between_6_9_group;
-            idx_between_4_7_group;
-            idx_between_8_11_group;
+            lt_iter_limit_group;
+            idx_between_depth_plus_8_depth_plus_9_group;
+            idx_between_2_min_depth_4_plus_2_group;
+            idx_between_2_depth_plus_2_group;
+            idx_between_7_depth_plus_7_group;
+            idx_between_3_depth_plus_3_group;
+            idx_between_3_min_depth_4_plus_3_group;
+            idx_between_depth_plus_5_depth_plus_6_group;
+            idx_between_depth_plus_9_depth_plus_10_group;
+            idx_between_8_depth_plus_8_group;
+            idx_between_depth_plus_6_depth_plus_7_group;
+            idx_between_4_depth_plus_4_group;
+            idx_between_4_min_depth_4_plus_4_group;
+            idx_between_5_min_depth_4_plus_5_group;
+            idx_between_5_depth_plus_5_group;
+            idx_between_0_depth_plus_0_group;
+            idx_between_9_depth_plus_9_group;
+            idx_between_1_depth_plus_1_group;
+            idx_between_1_min_depth_4_plus_1_group;
+            idx_between_6_depth_plus_6_group;
+            idx_between_depth_plus_7_depth_plus_8_group;
+            depth_plus_8_group;
+            depth_plus_9_group;
+            min_depth_4_plus_2_group;
+            depth_plus_2_group;
+            depth_plus_7_group;
+            depth_plus_3_group;
+            min_depth_4_plus_3_group;
+            depth_plus_5_group;
+            depth_plus_6_group;
+            depth_plus_10_group;
+            depth_plus_4_group;
+            min_depth_4_plus_4_group;
+            min_depth_4_plus_5_group;
+            depth_plus_0_group;
+            depth_plus_1_group;
+            min_depth_4_plus_1_group;
           }
         }
       }
     }
   }
 }
+component main() -> () {
+  cells {
+    systolic_array = systolic_array_comp();
+    @external t0 = std_mem_d1(32, 3, 2);
+    @external t1 = std_mem_d1(32, 3, 2);
+    @external t2 = std_mem_d1(32, 3, 2);
+    @external l0 = std_mem_d1(32, 3, 2);
+    @external l1 = std_mem_d1(32, 3, 2);
+    @external l2 = std_mem_d1(32, 3, 2);
+    @external out_mem_0 = std_mem_d1(32, 3, 32);
+    @external out_mem_1 = std_mem_d1(32, 3, 32);
+    @external out_mem_2 = std_mem_d1(32, 3, 32);
+  }
+  wires {
+
+  }
+  control {
+    invoke systolic_array(depth=32'd3, t0_read_data=t0.read_data, t1_read_data=t1.read_data, t2_read_data=t2.read_data, l0_read_data=l0.read_data, l1_read_data=l1.read_data, l2_read_data=l2.read_data)(t0_addr0=t0.addr0, t1_addr0=t1.addr0, t2_addr0=t2.addr0, l0_addr0=l0.addr0, l1_addr0=l1.addr0, l2_addr0=l2.addr0, out_mem_0_addr0=out_mem_0.addr0, out_mem_0_write_data=out_mem_0.write_data, out_mem_0_write_en=out_mem_0.write_en, out_mem_1_addr0=out_mem_1.addr0, out_mem_1_write_data=out_mem_1.write_data, out_mem_1_write_en=out_mem_1.write_en, out_mem_2_addr0=out_mem_2.addr0, out_mem_2_write_data=out_mem_2.write_data, out_mem_2_write_en=out_mem_2.write_en);
+  }
+}
 metadata #{
-0: pe_0_0 filling: [1,4) accumulating: [5 8)
-1: pe_0_1 filling: [2,5) accumulating: [6 9)
-2: pe_0_2 filling: [3,6) accumulating: [7 10)
-3: pe_1_0 filling: [2,5) accumulating: [6 9)
-4: pe_1_1 filling: [3,6) accumulating: [7 10)
-5: pe_1_2 filling: [4,7) accumulating: [8 11)
-6: pe_2_0 filling: [3,6) accumulating: [7 10)
-7: pe_2_1 filling: [4,7) accumulating: [8 11)
-8: pe_2_2 filling: [5,8) accumulating: [9 12)
+0: pe_0_0 filling: [1,min_depth_4_plus_1) accumulating: [5 depth_plus_5)
+1: pe_0_1 filling: [2,min_depth_4_plus_2) accumulating: [6 depth_plus_6)
+2: pe_0_2 filling: [3,min_depth_4_plus_3) accumulating: [7 depth_plus_7)
+3: pe_1_0 filling: [2,min_depth_4_plus_2) accumulating: [6 depth_plus_6)
+4: pe_1_1 filling: [3,min_depth_4_plus_3) accumulating: [7 depth_plus_7)
+5: pe_1_2 filling: [4,min_depth_4_plus_4) accumulating: [8 depth_plus_8)
+6: pe_2_0 filling: [3,min_depth_4_plus_3) accumulating: [7 depth_plus_7)
+7: pe_2_1 filling: [4,min_depth_4_plus_4) accumulating: [8 depth_plus_8)
+8: pe_2_2 filling: [5,min_depth_4_plus_5) accumulating: [9 depth_plus_9)
 }#