diff --git a/calyx-py/calyx/builder.py b/calyx-py/calyx/builder.py index b190d30ef6..bbde0fded8 100644 --- a/calyx-py/calyx/builder.py +++ b/calyx-py/calyx/builder.py @@ -564,6 +564,13 @@ def port(self, name: str) -> ExprBuilder: """Build a port access expression.""" return ExprBuilder(ast.Atom(ast.CompPort(self._cell.id, name))) + def is_mem_d1(self) -> bool: + """Check if the cell is a StdMemD1 cell.""" + return ( + isinstance(self._cell.comp, ast.CompInst) + and self._cell.comp.id == "std_mem_d1" + ) + @classmethod def unwrap_id(cls, obj): if isinstance(obj, cls): diff --git a/calyx-py/calyx/builder_util.py b/calyx-py/calyx/builder_util.py index f23b33ab2b..13086f580b 100644 --- a/calyx-py/calyx/builder_util.py +++ b/calyx-py/calyx/builder_util.py @@ -1,66 +1,130 @@ +# pylint: disable=import-error import calyx.builder as cb -def insert_eq(comp: cb.ComponentBuilder, a, b, cell, width): - """Inserts wiring into component {comp} to check if {a} == {b}. - 1. Within {comp}, creates a combinational group called {cell}_group. - 2. Within the group, creates a {cell} that checks equalities of {width}. - 3. Puts the values {a} and {b} into {cell}. - 4. Returns the equality-checking cell and the overall group. - """ - eq_cell = comp.eq(cell, width) - with comp.comb_group(f"{cell}_group") as eq_group: - eq_cell.left = a - eq_cell.right = b - return eq_cell, eq_group - - -def insert_neq(comp: cb.ComponentBuilder, a, b, cell, width): - """Inserts wiring into component {comp} to check if {a} != {b}. - 1. Within {comp}, creates a combinational group called {cell}_group. - 2. Within the group, creates a {cell} that checks inequalities of {width}. - 3. Puts the values {a} and {b} into {cell}. - 4. Returns the inequality-checking cell and the overall group. - """ - neq_cell = comp.neq(cell, width) - with comp.comb_group(f"{cell}_group") as neq_group: - neq_cell.left = a - neq_cell.right = b - return neq_cell, neq_group - - -def insert_incr(comp: cb.ComponentBuilder, reg, cell): - """Inserts wiring into component {comp} to increment {reg} by 1. - 1. Within component {comp}, creates a group called cell_{group}. - 2. Within {group}, adds a cell {cell} that computes sums. - 3. Puts the values of {port} and 1 into {cell}. - 4. Then puts the answer of the computation back into {port}. - 4. Returns the group that does this. +def insert_comb_group(comp: cb.ComponentBuilder, left, right, cell, groupname): + """Accepts a cell that performs some computation on values {left} and {right}. + Creates a combinational group {groupname} that wires up the cell with these ports. + Returns the cell and the combintational group. + """ + with comp.comb_group(groupname) as comb_group: + cell.left = left + cell.right = right + return cell, comb_group + + +def insert_eq(comp: cb.ComponentBuilder, left, right, cellname, width): + """Inserts wiring into component {comp} to check if {left} == {right}. + + = std_eq(); + ... + comb group _group { + .left = ; + .right = ; + } + + Returns handles to the cell and the combinational group. + """ + eq_cell = comp.eq(cellname, width) + return insert_comb_group(comp, left, right, eq_cell, f"{cellname}_group") + + +def insert_neq(comp: cb.ComponentBuilder, left, right, cellname, width): + """Inserts wiring into component {comp} to check if {left} != {right}. + + = std_neq(); + ... + comb group _group { + .left = ; + .right = ; + } + + Returns handles to the cell and the combinational group. + """ + neq_cell = comp.neq(cellname, width) + return insert_comb_group(comp, left, right, neq_cell, f"{cellname}_group") + + +def insert_lt(comp: cb.ComponentBuilder, left, right, cellname, width): + """Inserts wiring into component {comp} to check if {left} < {right}. + + = std_lt(); + ... + comb group _group { + .left = ; + .right = ; + } + + Returns handles to the cell and the combinational group. + """ + lt_cell = comp.lt(cellname, width) + return insert_comb_group(comp, left, right, lt_cell, f"{cellname}_group") + + +def insert_add(comp: cb.ComponentBuilder, left, right, cellname, width): + """Inserts wiring into component {comp} to compute {left} + {right}. + + = std_add(); + ... + comb group _group { + .left = ; + .right = ; + } + + Returns handles to the cell and the combinational group. + """ + add_cell = comp.add(cellname, width) + return insert_comb_group(comp, left, right, add_cell, f"{cellname}_group") + + +def insert_sub(comp: cb.ComponentBuilder, left, right, cellname, width): + """Inserts wiring into component {comp} to compute {left} - {right}. + + = std_sub(); + ... + comb group _group { + .left = ; + .right = ; + } + + Returns handles to the cell and the combinational group. + """ + sub_cell = comp.sub(cellname, width) + return insert_comb_group(comp, left, right, sub_cell, f"{cellname}_group") + + +def insert_incr(comp: cb.ComponentBuilder, reg, cellname, val=1): + """Inserts wiring into component {comp} to increment register {reg} by {val}. + 1. Within component {comp}, creates a group called {cellname}_group. + 2. Within the group, adds a cell {cellname} that computes sums. + 3. Puts the values {reg} and {val} into the cell. + 4. Then puts the answer of the computation back into {reg}. + 5. Returns the group that does this. """ - incr_cell = comp.add(cell, 32) - with comp.group(f"{cell}group") as incr_group: - incr_cell.left = reg.out - incr_cell.right = cb.const(32, 1) + add_cell = comp.add(cellname, 32) + with comp.group(f"{cellname}_group") as incr_group: + add_cell.left = reg.out + add_cell.right = cb.const(32, val) reg.write_en = 1 - reg.in_ = incr_cell.out + reg.in_ = add_cell.out incr_group.done = reg.done return incr_group -def insert_decr(comp: cb.ComponentBuilder, reg, cell): - """Inserts wiring into component {comp} to decrement {reg} by 1. - 1. Within component {comp}, creates a group called {group}. - 2. Within {group}, adds a cell {cell} that computes differences. - 3. Puts the values of {port} and 1 into {cell}. - 4. Then puts the answer of the computation back into {port}. - 4. Returns the group that does this. +def insert_decr(comp: cb.ComponentBuilder, reg, cellname, val=1): + """Inserts wiring into component {comp} to decrement register {reg} by {val}. + 1. Within component {comp}, creates a group called {cellname}_group. + 2. Within the group, adds a cell {cellname} that computes differences. + 3. Puts the values {reg} and {val} into the cell. + 4. Then puts the answer of the computation back into {reg}. + 5. Returns the group that does this. """ - decr_cell = comp.sub(cell, 32) - with comp.group(f"{cell}group") as decr_group: - decr_cell.left = reg.out - decr_cell.right = cb.const(32, 1) + sub_cell = comp.sub(cellname, 32) + with comp.group(f"{cellname}_group") as decr_group: + sub_cell.left = reg.out + sub_cell.right = cb.const(32, val) reg.write_en = 1 - reg.in_ = decr_cell.out + reg.in_ = sub_cell.out decr_group.done = reg.done return decr_group @@ -95,7 +159,7 @@ def mem_store(comp: cb.ComponentBuilder, mem, i, val, group): return store_grp -def reg_store(comp: cb.ComponentBuilder, reg, val, group): +def insert_reg_store(comp: cb.ComponentBuilder, reg, val, group): """Stores a value in a register. 1. Within component {comp}, creates a group called {group}. 2. Within {group}, sets the register {reg} to {val}. @@ -166,3 +230,73 @@ def reg_swap(comp: cb.ComponentBuilder, a, b, group): b.in_ = tmp.out swap_grp.done = b.done return swap_grp + + +def insert_mem_load_to_mem(comp: cb.ComponentBuilder, mem, i, ans, j, group): + """Loads a value from one std_mem_d1 memory into another. + 1. Within component {comp}, creates a group called {group}. + 2. Within {group}, reads from memory {mem} at address {i}. + 3. Writes the value into memory {ans} at address {j}. + 4. Returns the group that does this. + """ + assert mem.is_mem_d1() and ans.is_mem_d1() + with comp.group(group) as load_grp: + mem.addr0 = i + ans.write_en = 1 + ans.addr0 = j + ans.write_data = mem.read_data + load_grp.done = ans.done + return load_grp + + +def insert_add_store_in_reg( + comp: cb.ComponentBuilder, + cellname, + left, + right, + ans_reg=None, +): + """Inserts wiring into component {comp} to compute {left} + {right} and + store it in {ans_reg}. + 1. Within component {comp}, creates a group called {cellname}_group. + 2. Within {group}, create a cell {cellname} that computes sums. + 3. Puts the values of {left} and {right} into the cell. + 4. Then puts the answer of the computation into {ans_reg}. + 4. Returns the summing group and the register. + """ + add_cell = comp.add(cellname, 32) + ans_reg = ans_reg or comp.reg(f"reg_{cellname}", 32) + with comp.group(f"{cellname}_group") as adder_group: + add_cell.left = left + add_cell.right = right + ans_reg.write_en = 1 + ans_reg.in_ = add_cell.out + adder_group.done = ans_reg.done + return adder_group, ans_reg + + +def insert_sub_store_in_reg( + comp: cb.ComponentBuilder, + left, + right, + cellname, + width, + ans_reg=None, +): + """Adds wiring into component {comp} to compute {left} - {right} + and store it in {ans_reg}. + 1. Within component {comp}, creates a group called {cellname}_group. + 2. Within {group}, create a cell {cellname} that computes differences. + 3. Puts the values of {left} and {right} into {cell}. + 4. Then puts the answer of the computation into {ans_reg}. + 4. Returns the subtracting group and the register. + """ + sub_cell = comp.sub(cellname, width) + ans_reg = ans_reg or comp.reg(f"reg_{cellname}", width) + with comp.group(f"{cellname}_group") as sub_group: + sub_cell.left = left + sub_cell.right = right + ans_reg.write_en = 1 + ans_reg.in_ = sub_cell.out + sub_group.done = ans_reg.done + return sub_group, ans_reg diff --git a/calyx-py/test/correctness/arbiter_6.py b/calyx-py/test/correctness/arbiter_6.py index a9857a2093..294f77856b 100644 --- a/calyx-py/test/correctness/arbiter_6.py +++ b/calyx-py/test/correctness/arbiter_6.py @@ -1,84 +1,8 @@ # pylint: disable=import-error +import calyx.builder_util as util import calyx.builder as cb -def add_eq(comp: cb.ComponentBuilder, port, const, cell, group): - """Adds wiring into component {comp} to check if {port} == {const}. - 1. Within {comp}, creates a group called {group}. - 2. Within {group}, creates a cell called {cell} that checks equality. - 3. Puts the values of {port} and {const} into {cell}. - 4. Returns the equality-checking cell and the equality-checking group. - """ - eq_cell = comp.eq(cell, 32) - with comp.comb_group(group) as eq_group: - eq_cell.left = port - eq_cell.right = const - return eq_cell, eq_group - - -def add_lt(comp: cb.ComponentBuilder, port, const, cell, group): - """Adds wiring into component {comp} to check if {port} < {const}. - 1. Within component {comp}, creates a group called {group}. - 2. Within {group}, creates a cell called {cell} that checks for less-than. - 3. Puts the values of {port} and {const} into {cell}. - 4. Returns the less-than-checking cell and the less-than-checking group. - """ - lt_cell = comp.lt(cell, 32) - with comp.comb_group(group) as lt_group: - lt_cell.left = port - lt_cell.right = const - return lt_cell, lt_group - - -def add_sub(comp: cb.ComponentBuilder, port, const, sub_cell, ans_reg, group): - """Adds wiring into component {comp} to compute {port} - {const}. - 1. Within component {comp}, creates a group called {group}. - 2. Within {group}, assumes there is a cell {cell} that computes differences. - 3. Puts the values of {port} and {const} into {cell}. - 4. Then puts the answer of the computation into {ans_reg}. - 4. Returns the sub-checking group. - """ - # Note, this one is a little different than the others. - # 1. We assume the subtraction cell already exists. - # 2. We're not returning the cell, because we don't need to. - # 3. We write the answer into `ans_reg`. - - with comp.group(group) as sub_group: - sub_cell.left = port - sub_cell.right = const - ans_reg.write_en = 1 - ans_reg.in_ = sub_cell.out - sub_group.done = ans_reg.done - return sub_group - - -def add_mem_load(comp: cb.ComponentBuilder, mem, i, ans, group): - """Loads a value from one memory into another. - 1. Within component {comp}, creates a group called {group}. - 2. Within {group}, reads from memory {mem} at address {i}. - 3. Writes the value into memory {ans} at address 0. - 4. Returns the group that does this. - """ - with comp.group(group) as load_grp: - mem.addr0 = i - ans.write_en = 1 - ans.write_data = mem.read_data - load_grp.done = ans.done - return load_grp - - -def add_reg_load(comp: cb.ComponentBuilder, port, ans_reg, group): - """Creates a group called {group}. - In that group, loads the value of {port} into {ans_reg}. - Returns the group. - """ - with comp.group(group) as grp: - ans_reg.write_en = 1 - ans_reg.in_ = port - grp.done = ans_reg.done - return grp - - def add_wrap2(prog): """Inserts the component `wrap2` into the program. @@ -106,59 +30,64 @@ def add_wrap2(prog): j_mod_4 = wrap.reg("j_mod_4", 32) # Additional cells and groups to compute equality and lt - eq0cell, eq0grp = add_eq(wrap, i, 0, "eq0", "i_eq_0") - eq1cell, eq1grp = add_eq(wrap, i, 1, "eq1", "i_eq_1") - lt1cell, lt1grp = add_lt(wrap, j, 4, "lt1", "j_lt_4") - lt2cell, lt2grp = add_lt(wrap, j, 8, "lt2", "j_lt_8") + i_eq_0_cell, i_eq_0_grp = util.insert_eq(wrap, i, 0, "i_eq_0", 32) + i_eq_1_cell, i_eq_1_group = util.insert_eq(wrap, i, 1, "i_eq_1", 32) + j_lt_4_cell, j_lt_4_group = util.insert_lt(wrap, j, 4, "j_lt_4", 32) + j_lt_8_cell, j_lt_8_group = util.insert_lt(wrap, j, 8, "j_lt_8", 32) # Load `j` unchanged into `j_mod_4`. - unchanged = add_reg_load(wrap, j, j_mod_4, "j_unchanged") + unchanged = util.insert_reg_store(wrap, j_mod_4, j, "j_unchanged") - # A subtraction cell and wiring to perform j-4 and j-8. - sub_cell = wrap.sub("sub", 32) - sub1cell = add_sub(wrap, j, cb.const(32, 4), sub_cell, j_mod_4, "j_minus_4") - sub2cell = add_sub(wrap, j, cb.const(32, 8), sub_cell, j_mod_4, "j_minus_8") + # Wiring to perform j-4 and j-8. Either of these will store the result in `j_mod_4`. + j_minus_4, j_mod_4 = util.insert_sub_store_in_reg( + wrap, j, cb.const(32, 4), "j_minus_4", 32, j_mod_4 + ) + j_minus_8, j_mod_4 = util.insert_sub_store_in_reg( + wrap, j, cb.const(32, 8), "j_minus_8", 32, j_mod_4 + ) load_from_mems = [ # Add wiring to load the value `j_mod_4` from all of the memory cells. # We'll have to invoke the correct one of these groups later on. - add_mem_load(wrap, mems[i], j_mod_4.out, ans, f"load_from_mem{i}") + util.insert_mem_load_to_mem( + wrap, mems[i], j_mod_4.out, ans, cb.const(32, 0), f"load_from_mem{i}" + ) for i in range(6) ] wrap.control += [ cb.if_( - lt1cell.out, - lt1grp, + j_lt_4_cell.out, + j_lt_4_group, unchanged, - cb.if_(lt2cell.out, lt2grp, sub1cell, sub2cell), + cb.if_(j_lt_8_cell.out, j_lt_8_group, j_minus_4, j_minus_8), ), cb.par( cb.if_( - eq0cell.out, - eq0grp, + i_eq_0_cell.out, + i_eq_0_grp, cb.if_( - lt1cell.out, - lt1grp, + j_lt_4_cell.out, + j_lt_4_group, load_from_mems[0], cb.if_( - lt2cell.out, - lt2grp, + j_lt_8_cell.out, + j_lt_8_group, load_from_mems[1], load_from_mems[2], ), ), ), cb.if_( - eq1cell.out, - eq1grp, + i_eq_1_cell.out, + i_eq_1_group, cb.if_( - lt1cell.out, - lt1grp, + j_lt_4_cell.out, + j_lt_4_group, load_from_mems[3], cb.if_( - lt2cell.out, - lt2grp, + j_lt_8_cell.out, + j_lt_8_group, load_from_mems[4], load_from_mems[5], ), @@ -197,40 +126,49 @@ def add_wrap3(prog): j_mod_4 = wrap.reg("j_mod_4", 32) # Additional cells to compute equality, and lt - eq0cell, eq0grp = add_eq(wrap, i, 0, "eq0", "i_eq_0") - eq1cell, eq1grp = add_eq(wrap, i, 1, "eq1", "i_eq_1") - eq2cell, eq2grp = add_eq(wrap, i, 2, "eq2", "i_eq_2") - ltcell, ltgrp = add_lt(wrap, j, 4, "lt", "j_lt_4") + i_eq_0_cell, i_eq_0_group = util.insert_eq(wrap, i, 0, "i_eq_0", 32) + i_eq_1_cell, i_eq_1_group = util.insert_eq(wrap, i, 1, "i_eq_1", 32) + i_eq_2_cell, i_eq_2_group = util.insert_eq(wrap, i, 2, "i_eq_2", 32) + j_lt_4_cell, j_lt_4_group = util.insert_lt(wrap, j, 4, "j_lt_4", 32) # Load `j` unchanged into `j_mod_4`. - unchanged = add_reg_load(wrap, j, j_mod_4, "j_unchanged") + unchanged = util.insert_reg_store(wrap, j_mod_4, j, "j_unchanged") - # A subtraction cell and wiring to perform j-4. - sub_cell = wrap.sub("sub", 32) - subcell = add_sub(wrap, j, cb.const(32, 4), sub_cell, j_mod_4, "j_minus_4") + # Wiring to perform j-4 and store the result in `j_mod_4`. + subcell, j_mod_4 = util.insert_sub_store_in_reg( + wrap, j, cb.const(32, 4), "j_minus_4", 32, j_mod_4 + ) emit_from_mems = [ - add_mem_load(wrap, mems[i], j_mod_4.out, ans, f"load_from_mem{i}") + util.insert_mem_load_to_mem( + wrap, mems[i], j_mod_4.out, ans, cb.const(32, 0), f"load_from_mem{i}" + ) for i in range(6) ] wrap.control += [ - cb.if_(ltcell.out, ltgrp, unchanged, subcell), + cb.if_(j_lt_4_cell.out, j_lt_4_group, unchanged, subcell), cb.par( cb.if_( - eq0cell.out, - eq0grp, - cb.if_(ltcell.out, ltgrp, emit_from_mems[0], emit_from_mems[1]), + i_eq_0_cell.out, + i_eq_0_group, + cb.if_( + j_lt_4_cell.out, j_lt_4_group, emit_from_mems[0], emit_from_mems[1] + ), ), cb.if_( - eq1cell.out, - eq1grp, - cb.if_(ltcell.out, ltgrp, emit_from_mems[2], emit_from_mems[3]), + i_eq_1_cell.out, + i_eq_1_group, + cb.if_( + j_lt_4_cell.out, j_lt_4_group, emit_from_mems[2], emit_from_mems[3] + ), ), cb.if_( - eq2cell.out, - eq2grp, - cb.if_(ltcell.out, ltgrp, emit_from_mems[4], emit_from_mems[5]), + i_eq_2_cell.out, + i_eq_2_group, + cb.if_( + j_lt_4_cell.out, j_lt_4_group, emit_from_mems[4], emit_from_mems[5] + ), ), ), ] diff --git a/calyx-py/test/correctness/fifo.py b/calyx-py/test/correctness/fifo.py index 0ec2d224f4..8c4e65d259 100644 --- a/calyx-py/test/correctness/fifo.py +++ b/calyx-py/test/correctness/fifo.py @@ -17,7 +17,7 @@ def insert_raise_err_if_i_eq_15(prog): err = raise_err_if_i_eq_15.reg("err", 1, is_ref=True) i_eq_15 = util.insert_eq(raise_err_if_i_eq_15, i, 15, "i_eq_15", 32) - raise_err = util.reg_store(raise_err_if_i_eq_15, err, 1, "raise_err") + raise_err = util.insert_reg_store(raise_err_if_i_eq_15, err, 1, "raise_err") raise_err_if_i_eq_15.control += [ cb.if_( @@ -82,10 +82,14 @@ def insert_fifo(prog, name): len_decr = util.insert_decr(fifo, len, "len_decr") # len-- # Cells and groups to modify flags, which are registers - write_wrap = util.reg_store(fifo, write, 0, "write_wraparound") # zero out `write` - read_wrap = util.reg_store(fifo, read, 0, "read_wraparound") # zero out `read` - raise_err = util.reg_store(fifo, err, 1, "raise_err") # set `err` to 1 - zero_out_ans = util.reg_store(fifo, ans, 0, "zero_out_ans") # zero out `ans` + write_wrap = util.insert_reg_store( + fifo, write, 0, "write_wraparound" + ) # zero out `write` + read_wrap = util.insert_reg_store( + fifo, read, 0, "read_wraparound" + ) # zero out `read` + raise_err = util.insert_reg_store(fifo, err, 1, "raise_err") # set `err` to 1 + zero_out_ans = util.insert_reg_store(fifo, ans, 0, "zero_out_ans") # zero out `ans` # Load and store into an arbitary slot in memory write_to_mem = util.mem_store_seq_d1( @@ -186,13 +190,15 @@ def insert_main(prog): j = main.reg("j", 32) # The index on the answer-list we'll write to command = main.reg("command", 32) # The command we're currently processing - zero_i = util.reg_store(main, i, 0, "zero_i") # zero out `i` - zero_j = util.reg_store(main, j, 0, "zero_j") # zero out `j` - incr_i = util.insert_incr(main, i, "i_incr") # i = i + 1 - incr_j = util.insert_incr(main, j, "j_incr") # j = j + 1 + zero_i = util.insert_reg_store(main, i, 0, "zero_i") # zero out `i` + zero_j = util.insert_reg_store(main, j, 0, "zero_j") # zero out `j` + incr_i = util.insert_incr(main, i, "incr_i") # i = i + 1 + incr_j = util.insert_incr(main, j, "incr_j") # j = j + 1 err_eq_0 = util.insert_eq(main, err.out, 0, "err_eq_0", 1) # is `err` flag down? - cmd_eq_0 = util.insert_eq(main, command.out, 0, "command_eq_0", 32) - cmd_neq_0 = util.insert_neq(main, command.out, cb.const(32, 0), "command_neq_0", 32) + cmd_eq_0 = util.insert_eq(main, command.out, 0, "cmd_eq_0", 32) # is `command` 0? + cmd_neq_0 = util.insert_neq( + main, command.out, cb.const(32, 0), "cmd_neq_0", 32 + ) # is `command` 0? read_command = util.mem_read_seqd1(main, commands, i.out, "read_command_phase1") write_command_to_reg = util.mem_write_seqd1_to_reg( diff --git a/calyx-py/test/correctness/pifo.py b/calyx-py/test/correctness/pifo.py index caf95c2f20..96ef714b4a 100644 --- a/calyx-py/test/correctness/pifo.py +++ b/calyx-py/test/correctness/pifo.py @@ -53,7 +53,7 @@ def insert_propagate_err(prog, name): val = propagate_err.input("val", 1) err = propagate_err.reg("err", 1, is_ref=True) - prop_err = util.reg_store(propagate_err, err, val, "prop_err") + prop_err = util.insert_reg_store(propagate_err, err, val, "prop_err") propagate_err.control += [prop_err] @@ -81,7 +81,7 @@ def insert_pifo(prog, name): - len(PIFO) = len(fifo_0) + len(fifo_1) - `push(v, PIFO)`: + If len(PIFO) = 10, raise an "overflow" err and exit. - + Otherwise, the charge is to enqueue value `v`. + + Otherwise, the charge is to enqueue value `v`. Find out which flow `f` the value `v` should go to; `f` better be either `0` or `1`. Enqueue `v` into `fifo_f`. @@ -116,8 +116,8 @@ def insert_pifo(prog, name): err = pifo.reg("err", 1, is_ref=True) # We'll raise this as a general error flag for overflow and underflow - err_0 = pifo.reg("err_fifo_0", 1) # an error flag dedicated to fifo_1 - err_1 = pifo.reg("err_fifo_1", 1) # and one for fifo_1 + err_0 = pifo.reg("err_fifo_0", 1) # an error flag dedicated to fifo_1 + err_1 = pifo.reg("err_fifo_1", 1) # and one for fifo_1 propagate_err = pifo.cell("prop_err", insert_propagate_err(prog, "propagate_err")) # Sometimes we'll need to propagate an error message to the main `err` flag @@ -142,8 +142,8 @@ def insert_pifo(prog, name): cmd_neq_0 = util.insert_neq(pifo, cmd, cb.const(32, 0), "cmd_neq_0", 32) # cmd != 0 swap = util.reg_swap(pifo, hot, cold, "swap") # Swap `hot` and `cold`. - raise_err = util.reg_store(pifo, err, 1, "raise_err") # set `err` to 1 - zero_out_ans = util.reg_store(pifo, ans, 0, "zero_out_ans") # zero out `ans` + raise_err = util.insert_reg_store(pifo, err, 1, "raise_err") # set `err` to 1 + zero_out_ans = util.insert_reg_store(pifo, ans, 0, "zero_out_ans") # zero out `ans` update_length = insert_len_update(pifo, len, len_0, len_1, "update_length") # The main logic. @@ -354,7 +354,6 @@ def insert_main(prog): incr_i = util.insert_incr(main, i, "incr_i") # i++ incr_j = util.insert_incr(main, j, "incr_j") # j++ - err_eq_zero = util.insert_eq(main, err.out, 0, "err_eq_0", 1) # is `err` flag down? # read_command = util.mem_load(main, commands, i.out, command, "read_command") read_command = util.mem_read_seqd1(main, commands, i.out, "read_command_phase1") diff --git a/calyx-py/test/correctness/reduction_tree.py b/calyx-py/test/correctness/reduction_tree.py index a48989a7db..c32eaa1ed7 100644 --- a/calyx-py/test/correctness/reduction_tree.py +++ b/calyx-py/test/correctness/reduction_tree.py @@ -1,31 +1,9 @@ # pylint: disable=import-error from typing import List +import calyx.builder_util as util import calyx.builder as cb -def add_adder( - comp: cb.ComponentBuilder, - adder: cb.CellBuilder, - group, - port_l, - port_r, - ans_reg, -): - """To component {comp}, adds wiring for an group called {group}. - Assumes the adder cell {adder} is in the component. - In {group}, puts {port_l} and {port_r} into the {adder} cell. - Then puts the output of {adder} into the memory register {ans_reg}. - Returns the group. - """ - with comp.group(group) as adder_group: - adder.left = port_l - adder.right = port_r - ans_reg.write_en = 1 - ans_reg.in_ = adder.out - adder_group.done = ans_reg.done - return adder_group - - def add_tree(prog): """Inserts the component `tree` into the program. It has: @@ -43,20 +21,13 @@ def add_tree(prog): # Add the output port. tree.output("sum", 32) - # Add three registers and two adders. - root = tree.reg("root", 32) - left = tree.reg("left_node", 32) - right = tree.reg("right_node", 32) - add1 = tree.add("add1", 32) - add2 = tree.add("add2", 32) - # Into the component `tree`, add the wiring for three adder groups that will # use the tree to perform their additions. # These need to be orchestrated in the control below. - add_l0_l1 = add_adder(tree, add1, "add_l0_l1", leaf0, leaf1, left) - add_l2_l3 = add_adder(tree, add2, "add_l2_l3", leaf2, leaf3, right) - add_l_r_nodes = add_adder( - tree, add1, "add_left_right_nodes", left.out, right.out, root + add_l0_l1, left = util.insert_add_store_in_reg(tree, "add_l0_l1", leaf0, leaf1) + add_l2_l3, right = util.insert_add_store_in_reg(tree, "add_l2_l3", leaf2, leaf3) + add_l_r_nodes, root = util.insert_add_store_in_reg( + tree, "add_l_r", left.out, right.out ) # Continuously output the value of the root register. diff --git a/docs/debug/cider.md b/docs/debug/cider.md index 2e8d676c35..3cf675a4d1 100644 --- a/docs/debug/cider.md +++ b/docs/debug/cider.md @@ -277,5 +277,6 @@ much of the execution is occurring in parallel at any given point. Use `help` to see all commands. Use `exit` to exit the debugger. -[fud]: /fud/index.md +[fud]: ../fud/index.md [gdb]: https://sourceware.org/gdb/ +[interp]: ../interpreter.md