diff --git a/frontends/mrxl/mrxl/map.py b/frontends/mrxl/mrxl/map.py
index cad0faeb29..0a172b8d11 100644
--- a/frontends/mrxl/mrxl/map.py
+++ b/frontends/mrxl/mrxl/map.py
@@ -68,7 +68,7 @@ def expr_to_port(expr: ast.BaseExpr):
                 f"mul_{suffix}", Stdlib.op("mult_pipe", 32, signed=False)
             )
         else:
-            operation = comp.add(f"add_{suffix}", 32)
+            operation = comp.add(32, f"add_{suffix}")
         # ANCHOR_END: map_op
 
         assert (
diff --git a/frontends/systolic-lang/gen-systolic.py b/frontends/systolic-lang/gen-systolic.py
index e0b35407e1..55631c1d1e 100755
--- a/frontends/systolic-lang/gen-systolic.py
+++ b/frontends/systolic-lang/gen-systolic.py
@@ -408,7 +408,7 @@ def instantiate_idx_cond_groups(comp: cb.ComponentBuilder, leaky_relu):
     # operations are finished yet
     if not leaky_relu:
         iter_limit = comp.get_cell("iter_limit")
-        lt_iter_limit = comp.lt("lt_iter_limit", BITWIDTH)
+        lt_iter_limit = comp.lt(BITWIDTH, "lt_iter_limit")
         with comp.static_group("lt_iter_limit_group", 1):
             lt_iter_limit.left = add.out
             lt_iter_limit.right = iter_limit.out