diff --git a/src/target/at32f43x.c b/src/target/at32f43x.c
index 9e4bccfde32..4041ab84225 100644
--- a/src/target/at32f43x.c
+++ b/src/target/at32f43x.c
@@ -27,6 +27,8 @@
  *   https://www.arterychip.com/download/RM/RM_AT32F435_437_EN_V2.04.pdf
  * AT32F402/405 Series Reference Manual
  *   https://www.arterychip.com/download/RM/RM_AT32F402_405_EN_V2.01.pdf
+ * AT32F423 Series Reference Manual
+ *   https://www.arterychip.com/download/RM/RM_AT32F423_EN_V2.03.pdf
  */
 
 #include "general.h"
@@ -121,6 +123,9 @@ static bool at32f43_mass_erase(target_s *target);
 #define AT32F43_SERIES_2K          0x70083000U
 #define AT32F405_SERIES_256K       0x70053000U
 #define AT32F405_SERIES_128K       0x70042000U
+#define AT32F423_SERIES_256KB      0x700a3000U
+#define AT32F423_SERIES_128KB      0x700a2000U
+#define AT32F423_SERIES_64KB       0x70032000U
 #define AT32F4x_PROJECT_ID         0x1ffff7f3U
 #define AT32F4x_FLASHSIZE          0x1ffff7e0U
 
@@ -330,6 +335,34 @@ static bool at32f405_detect(target_s *target, const uint32_t series)
 	return true;
 }
 
+/* Identify AT32F423 Value line devices */
+static bool at32f423_detect(target_s *target, const uint32_t series)
+{
+	/*
+	 * AT32F423 always has 48 KiB of SRAM and one of
+	 * Flash (C): 256 KiB, 2 KiB per sector, 0x700a_3000
+	 * Flash (B): 128 KiB, 1 KiB per sector, 0x700a_2000
+	 * Flash (8):  64 KiB, 1 KiB per sector, 0x7003_2000
+	 */
+	const uint16_t flash_size = target_mem32_read16(target, AT32F4x_FLASHSIZE);
+	const uint16_t sector_size = (series == AT32F423_SERIES_256KB) ? 2048U : 1024U;
+	at32f43_add_flash(target, 0x08000000, flash_size, sector_size, 0, AT32F43x_FLASH_BANK1_REG_OFFSET);
+
+	target_add_ram32(target, 0x20000000, 48U * 1024U);
+	target->driver = "AT32F423";
+	target->mass_erase = at32f43_mass_erase;
+
+	/* 512 byte User System Data area at 0x1fff_f800 (different USD_BASE, no EOPB0) */
+	//target_add_commands(target, at32f43_cmd_list, target->driver);
+
+	/* Same registers and freeze bits in DBGMCU as F437 */
+	target->attach = at32f43_attach;
+	target->detach = at32f43_detach;
+	at32f43_configure_dbgmcu(target);
+
+	return true;
+}
+
 /* Identify any Arterytek devices with Cortex-M4 and FPEC at 0x4002_3c00 */
 bool at32f43x_probe(target_s *target)
 {
@@ -352,6 +385,9 @@ bool at32f43x_probe(target_s *target)
 	if ((series == AT32F405_SERIES_256K || series == AT32F405_SERIES_128K) &&
 		(project_id == 0x13U || project_id == 0x14U))
 		return at32f405_detect(target, series);
+	if ((series == AT32F423_SERIES_256KB || series == AT32F423_SERIES_128KB || series == AT32F423_SERIES_64KB) &&
+		project_id == 0x12U)
+		return at32f423_detect(target, series);
 
 	return false;
 }