-
Notifications
You must be signed in to change notification settings - Fork 0
/
iommu_r_channel.v
executable file
·485 lines (432 loc) · 17 KB
/
iommu_r_channel.v
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353
354
355
356
357
358
359
360
361
362
363
364
365
366
367
368
369
370
371
372
373
374
375
376
377
378
379
380
381
382
383
384
385
386
387
388
389
390
391
392
393
394
395
396
397
398
399
400
401
402
403
404
405
406
407
408
409
410
411
412
413
414
415
416
417
418
419
420
421
422
423
424
425
426
427
428
429
430
431
432
433
434
435
436
437
438
439
440
441
442
443
444
445
446
447
448
449
450
451
452
453
454
455
456
457
458
459
460
461
462
463
464
465
466
467
468
469
470
471
472
473
474
475
476
477
478
479
480
481
482
483
484
485
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 02/23/2024 10:22:59 AM
// Design Name:
// Module Name: iommu_r_channel
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module iommu_r_channel (
input wire clk,
input wire [63:0] data_s_axi_araddr,
input wire [7:0] data_s_axi_arlen,
input wire [2:0] data_s_axi_arsize,
input wire [1:0] data_s_axi_arburst,
input wire data_s_axi_arlock,
input wire [3:0] data_s_axi_arcache,
input wire [2:0] data_s_axi_arprot,
input wire data_s_axi_arvalid,
output wire data_s_axi_arready,
input wire [2:0] data_s_axi_arid,
output wire [255:0] data_s_axi_rdata,
output wire [1:0] data_s_axi_rresp,
output wire data_s_axi_rlast,
output wire data_s_axi_rvalid,
input wire data_s_axi_rready,
output wire [2:0] data_s_axi_rid,
output wire [33:0] data_m_axi_araddr,
output wire [7:0] data_m_axi_arlen,
output wire [2:0] data_m_axi_arsize,
output wire [1:0] data_m_axi_arburst,
output wire data_m_axi_arlock,
output wire [3:0] data_m_axi_arcache,
output wire [2:0] data_m_axi_arprot,
output wire data_m_axi_arvalid,
input wire data_m_axi_arready,
output wire [2:0] data_m_axi_arid,
input wire [255:0] data_m_axi_rdata,
input wire [1:0] data_m_axi_rresp,
input wire data_m_axi_rlast,
input wire data_m_axi_rvalid,
output wire data_m_axi_rready,
input wire [2:0] data_m_axi_rid,
// The read walker port
output wire [33:0] iommu_read_m_axi_araddr,
output wire [7:0] iommu_read_m_axi_arlen,
output wire [2:0] iommu_read_m_axi_arsize,
output wire [1:0] iommu_read_m_axi_arburst,
output wire iommu_read_m_axi_arlock,
output wire [3:0] iommu_read_m_axi_arcache,
output wire [2:0] iommu_read_m_axi_arprot,
output wire iommu_read_m_axi_arvalid,
input wire iommu_read_m_axi_arready,
output wire [2:0] iommu_read_m_axi_arid,
input wire [255:0] iommu_read_m_axi_rdata,
input wire [1:0] iommu_read_m_axi_rresp,
input wire iommu_read_m_axi_rlast,
input wire iommu_read_m_axi_rvalid,
output wire iommu_read_m_axi_rready,
input wire [2:0] iommu_read_m_axi_rid,
input wire [63:0] ddtp,
input wire [31:0] flush,
// output wire [7:0] dbg_channel_state,
// output wire [7:0] dbg_walker_state,
// output wire dbg_channel_iova_valid,
// output wire dbg_channel_iova_ready,
// output wire [256:0] dbg_walker_cd,
// output wire [63:0] dbg_first_entry,
// output wire [63:0] dbg_second_entry,
// output wire [63:0] dbg_third_entry,
output wire [7:0] dbg_wait_cnt,
output wire [1:0] dbg_condition,
output wire [63:0] dbg_tslt_addr,
output reg dbg_addr_not_match,
output wire [7:0] dbg_translator_state,
output wire [7:0] dbg_walker_state,
output wire dbg_walker_arvalid,
output wire dbg_walker_bug,
output wire dbg_translator_tle,
output wire dbg_walker_reset,
output wire dbg_atc_flush_done,
output wire dbg_translator_should_flush
);
// ** 2.29 modification
reg [8:0] wait_cnt;
reg m_axi_arvalid;
reg s_axi_arready;
reg [63:0] m_axi_araddr;
reg [1:0] condition;
reg [63:0] iova;
reg iova_ready;
reg prev_data_s_axi_arvalid;
assign dbg_wait_cnt = wait_cnt;
assign dbg_condition = condition;
wire [63:0] pa;
wire pa_ready;
initial begin
wait_cnt <= 8'b0;
m_axi_arvalid <= 1'b0;
condition <= 2'b00;
s_axi_arready <= 1'b0;
iova <= 63'b0;
iova_ready <= 1'b0;
prev_data_s_axi_arvalid <= 1'b0;
dbg_addr_not_match <= 1'b0;
end
// always @ (posedge clk) begin
// if ((m_axi_arvalid == 1'b1) && (data_m_axi_arready == 1'b1)) begin
// wait_cnt <= 9'h0;
// condition <= 2'b01;
// end else if ((data_s_axi_arvalid == 1'b1)) begin
// wait_cnt <= wait_cnt + 9'h1;
// condition <= 2'b10;
// end else begin
// wait_cnt <= 9'h0;
// condition <= 2'b11;
// end
// end
always @ (posedge clk) begin
prev_data_s_axi_arvalid <= data_s_axi_arvalid;
end
always @ (posedge clk) begin
if ((prev_data_s_axi_arvalid == 1'b0) && (data_s_axi_arvalid == 1'b1)) begin
iova <= data_s_axi_araddr;
iova_ready <= 1'b1;
end else begin
iova_ready <= 1'b0;
end
end
always @ (posedge clk) begin
if (pa_ready == 1'b1) begin
if (iova != pa) begin
dbg_addr_not_match <= 1'b1;
end
m_axi_araddr <= pa;
m_axi_arvalid <= 1'b1;
s_axi_arready <= 1'b0;
end else if ((m_axi_arvalid == 1'b1) && (data_m_axi_arready == 1'b1)) begin
m_axi_arvalid <= 1'b0;
s_axi_arready <= 1'b1;
end else begin
m_axi_arvalid <= 1'b0;
s_axi_arready <= 1'b0;
end
end
// directly send s signals to m signals
// assign data_m_axi_araddr = data_s_axi_araddr;
assign data_m_axi_araddr = m_axi_araddr;
assign data_m_axi_arlen = data_s_axi_arlen;
assign data_m_axi_arsize = data_s_axi_arsize;
assign data_m_axi_arburst = data_s_axi_arburst;
assign data_m_axi_arlock = data_s_axi_arlock;
assign data_m_axi_arcache = data_s_axi_arcache;
assign data_m_axi_arprot = data_s_axi_arprot;
// assign data_m_axi_arvalid = data_s_axi_arvalid;
assign data_m_axi_arvalid = m_axi_arvalid;
// assign data_s_axi_arready = data_m_axi_arready;
assign data_s_axi_arready = s_axi_arready;
assign data_m_axi_arid = data_s_axi_arid;
assign data_s_axi_rdata = data_m_axi_rdata;
assign data_s_axi_rresp = data_m_axi_rresp;
assign data_s_axi_rlast = data_m_axi_rlast;
assign data_s_axi_rvalid = data_m_axi_rvalid;
assign data_m_axi_rready = data_s_axi_rready;
assign data_s_axi_rid = data_m_axi_rid;
iommu_address_translator translator (
.clk(clk),
.iova(iova),
.iova_ready(iova_ready),
.pa(pa),
.pa_ready(pa_ready),
.ddtp(ddtp),
.flush(flush),
.reset(0),
.iommu_m_axi_araddr(iommu_read_m_axi_araddr),
.iommu_m_axi_arlen(iommu_read_m_axi_arlen),
.iommu_m_axi_arsize(iommu_read_m_axi_arsize),
.iommu_m_axi_arburst(iommu_read_m_axi_arburst),
.iommu_m_axi_arlock(iommu_read_m_axi_arlock),
.iommu_m_axi_arcache(iommu_read_m_axi_arcache),
.iommu_m_axi_arprot(iommu_read_m_axi_arprot),
.iommu_m_axi_arvalid(iommu_read_m_axi_arvalid),
.iommu_m_axi_arready(iommu_read_m_axi_arready),
.iommu_m_axi_arid(iommu_read_m_axi_arid),
.iommu_m_axi_rdata(iommu_read_m_axi_rdata),
.iommu_m_axi_rresp(iommu_read_m_axi_rresp),
.iommu_m_axi_rlast(iommu_read_m_axi_rlast),
.iommu_m_axi_rvalid(iommu_read_m_axi_rvalid),
.iommu_m_axi_rready(iommu_read_m_axi_rready),
.iommu_m_axi_rid(iommu_read_m_axi_rid),
.dbg_tslt_addr(dbg_tslt_addr),
.dbg_translator_state(dbg_translator_state),
.dbg_walker_state(dbg_walker_state),
.dbg_walker_arvalid(dbg_walker_arvalid),
.dbg_walker_bug(dbg_walker_bug),
.dbg_translator_tle(dbg_translator_tle),
.dbg_walker_reset(dbg_walker_reset),
.dbg_atc_flush_done(dbg_atc_flush_done),
.dbg_translator_should_flush(dbg_translator_should_flush)
);
// ** 2.29 modification done
// reg [63:0] iova;
// reg [63:0] phys;
// reg iova_valid;
// reg [63:0] m_araddr;
// reg [7:0] m_arlen;
// reg [2:0] m_arsize;
// reg [1:0] m_arburst;
// reg m_arlock;
// reg [3:0] m_arcache;
// reg [2:0] m_arprot;
// reg m_arvalid;
// reg s_arready;
// reg [2:0] m_arid;
// // also have to cache the other ar signals
// reg [7:0] arlen_cache;
// reg [2:0] arsize_cache;
// reg [1:0] arburst_cache;
// reg arlock_cache;
// reg [3:0] arcache_cache;
// reg [2:0] arprot_cache;
// reg [2:0] arid_cache;
// // assign data_m_axi_araddr = data_s_daxi_araddr[33:0];
// assign data_m_axi_araddr = m_araddr;
// // assign data_m_axi_arlen = data_s_axi_arlen;
// assign data_m_axi_arlen = m_arlen;
// // assign data_m_axi_arsize = data_s_axi_arsize;
// assign data_m_axi_arsize = m_arsize;
// // assign data_m_axi_arburst = data_s_axi_arburst;
// assign data_m_axi_arburst = m_arburst;
// // assign data_m_axi_arlock = data_s_axi_arlock;
// assign data_m_axi_arlock = m_arlock;
// // assign data_m_axi_arcache = data_s_axi_arcache;
// assign data_m_axi_arcache = m_arcache;
// // assign data_m_axi_arprot = data_s_axi_arprot;
// assign data_m_axi_arprot = m_arprot;
// // assign data_m_axi_arvalid = data_s_axi_arvalid;
// assign data_m_axi_arvalid = m_arvalid;
// // assign data_s_axi_arready = data_m_axi_arready;
// assign data_s_axi_arready = s_arready;
// // assign data_s_axi_arready = data_s_axi_arvalid && (iova_valid[data_s_axi_arid] == 1'b0); // cache it!
// // assign data_m_axi_arid = data_s_axi_arid;
// assign data_m_axi_arid = m_arid;
// assign data_s_axi_rdata = data_m_axi_rdata;
// assign data_s_axi_rresp = data_m_axi_rresp;
// assign data_s_axi_rlast = data_m_axi_rlast;
// assign data_s_axi_rvalid = data_m_axi_rvalid;
// assign data_m_axi_rready = data_s_axi_rready;
// // This doesn't have to be postponed, because the master may assert rready before the handshake is finished, but the slave will not response
// assign data_s_axi_rid = data_m_axi_rid;
// // initialize the m registers to 0
// initial begin
// m_araddr <= 34'b0;
// m_arlen <= 8'b0;
// m_arsize <= 3'h0;
// m_arburst <= 2'b0;
// m_arlock <= 1'b0;
// m_arcache <= 4'b0;
// m_arprot <= 3'b0;
// m_arvalid <= 1'b0;
// s_arready <= 1'b0;
// m_arid <= 3'b0;
// end
// // wire s_handshake;
// // wire m_handshake;
// // assign s_handshake = data_s_axi_arvalid & data_s_axi_arready;
// // assign m_handshake = data_m_axi_arvalid & data_m_axi_arready;
// // reg [2:0] current_id;
// reg [7:0] state;
// // reg [63:0] iova;
// reg iova_ready;
// wire [63:0] pa;
// wire pa_ready;
// localparam STATE_IDLE = 8'h0;
// localparam STATE_TSLT = 8'h1;
// localparam STATE_WAIT = 8'h2;
// localparam STATE_HDSK = 8'h3;
// assign dbg_channel_state = state;
// assign dbg_channel_iova_ready = iova_ready;
// initial begin
// // current_id <= 3'b0;
// state <= 8'b0;
// iova_valid <= 0;
// iova_ready <= 0;
// end
// always @ (posedge clk) begin
// if (iova_valid == 0 && data_s_axi_arvalid == 1 && s_arready == 0) begin // the arvalid is not ready
// s_arready <= 1;
// end else begin
// s_arready <= 0;
// end
// end
// always @ (posedge clk) begin
// if (data_s_axi_arvalid && data_s_axi_arready) begin
// iova <= data_s_axi_araddr;
// iova_valid <= 1;
// // cache the other signals
// arlen_cache <= data_s_axi_arlen;
// arsize_cache <= data_s_axi_arsize;
// arburst_cache <= data_s_axi_arburst;
// arlock_cache <= data_s_axi_arlock;
// arcache_cache <= data_s_axi_arcache;
// arprot_cache <= data_s_axi_arprot;
// arid_cache <= data_s_axi_arid;
// end else begin
// iova_valid <= 0;
// end
// end
// assign dbg_channel_iova_valid = iova_valid;
// always @ (posedge clk) begin
// // state <= 8'h0;
// if (state == STATE_IDLE) begin
// m_arvalid <= 0;
// if (iova_valid == 1) begin
// state <= STATE_TSLT;
// end else begin
// state <= STATE_IDLE;
// end
// end else if (state == STATE_TSLT) begin
// iova_ready <= 1;
// state <= STATE_WAIT;
// end else if (state == STATE_WAIT) begin
// iova_ready <= 0;
// if (pa_ready) begin
// phys <= pa;
// state <= STATE_HDSK;
// end else begin
// phys <= 64'b0;
// state <= STATE_WAIT;
// end
// end else if (state == STATE_HDSK) begin
// m_araddr <= iova;
// m_arlen <= arlen_cache;
// m_arsize <= arsize_cache;
// m_arburst <= arburst_cache;
// m_arlock <= arlock_cache;
// m_arcache <= arcache_cache;
// m_arprot <= arprot_cache;
// m_arid <= arid_cache;
// m_arvalid <= 1;
// if (data_m_axi_arready) begin
// state <= STATE_IDLE;
// end else begin
// state <= STATE_HDSK;
// end
// end else begin
// state <= STATE_IDLE;
// end
// end
// // always @ (posedge clk) begin
// // case (state)
// // STATE_IDLE: begin
// // m_arvalid <= 0;
// // if (iova_valid == 1) begin
// // state <= STATE_TSLT;
// // end
// // end
// // STATE_TSLT: begin
// // iova_ready <= 1;
// // state <= STATE_WAIT;
// // end
// // STATE_WAIT: begin
// // iova_ready <= 0;
// // if (pa_ready) begin
// // phys <= pa;
// // state <= STATE_HDSK;
// // end else begin
// // end
// // end
// // STATE_HDSK: begin
// // m_araddr <= phys;
// // m_arlen <= arlen_cache;
// // m_arsize <= arsize_cache;
// // m_arburst <= arburst_cache;
// // m_arlock <= arlock_cache;
// // m_arcache <= arcache_cache;
// // m_arprot <= arprot_cache;
// // m_arid <= arid_cache;
// // // m_arvalid <= 1 & ((data_m_axi_arready == 1) || (data_m_axi_arvalid == 0));
// // if (m_arvalid && data_m_axi_arready) begin
// // state <= STATE_IDLE;
// // end else begin
// // end
// // end
// // default: begin
// // state <= STATE_IDLE;
// // end
// // endcase
// // end
// iommu_walker r_walker (
// .clk(clk),
// .iova(iova),
// .iova_ready(iova_ready),
// .pa(pa),
// .pa_ready(pa_ready),
// .ddtp(ddtp),
// .flush(flush),
// .reset(0),
// .iommu_m_axi_araddr(iommu_read_m_axi_araddr),
// .iommu_m_axi_arlen(iommu_read_m_axi_arlen),
// .iommu_m_axi_arsize(iommu_read_m_axi_arsize),
// .iommu_m_axi_arburst(iommu_read_m_axi_arburst),
// .iommu_m_axi_arlock(iommu_read_m_axi_arlock),
// .iommu_m_axi_arcache(iommu_read_m_axi_arcache),
// .iommu_m_axi_arprot(iommu_read_m_axi_arprot),
// .iommu_m_axi_arvalid(iommu_read_m_axi_arvalid),
// .iommu_m_axi_arready(iommu_read_m_axi_arready),
// .iommu_m_axi_arid(iommu_read_m_axi_arid),
// .iommu_m_axi_rdata(iommu_read_m_axi_rdata),
// .iommu_m_axi_rresp(iommu_read_m_axi_rresp),
// .iommu_m_axi_rlast(iommu_read_m_axi_rlast),
// .iommu_m_axi_rvalid(iommu_read_m_axi_rvalid),
// .iommu_m_axi_rready(iommu_read_m_axi_rready),
// .iommu_m_axi_rid(iommu_read_m_axi_rid),
// .dbg_walker_state(dbg_walker_state),
// .dbg_walker_cd(dbg_walker_cd),
// .dbg_first_entry(dbg_first_entry),
// .dbg_second_entry(dbg_second_entry),
// .dbg_third_entry(dbg_third_entry)
// );
endmodule