From 66bcb7bc6e54b807bb9a05100471a41a5a9dd04b Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Jo=C3=A3o=20Peixoto?= Date: Thu, 19 Sep 2024 14:24:43 +0100 Subject: [PATCH] ref(riscv/sync_exceptions): use vcpu_writepc method MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Refactored the vCPU program counter incrementation by introducing the architecture-agnostic method vcpu_writepc, aligning the implementation with the approach used in the ARM architecture. Signed-off-by: João Peixoto --- src/arch/riscv/sync_exceptions.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/arch/riscv/sync_exceptions.c b/src/arch/riscv/sync_exceptions.c index e44c5414..d685f349 100644 --- a/src/arch/riscv/sync_exceptions.c +++ b/src/arch/riscv/sync_exceptions.c @@ -152,5 +152,5 @@ void sync_exception_handler(void) ERROR("unkown synchronous exception (%d)", _scause); } - cpu()->vcpu->regs.sepc += pc_step; + vcpu_writepc(cpu()->vcpu, vcpu_readpc(cpu()->vcpu) + pc_step); }